First level trigger processor for the ZEUS calorimeter

International Nuclear Information System (INIS)

Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

1990-01-01

This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs

First-level trigger processor for the ZEUS calorimeter

International Nuclear Information System (INIS)

Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

1990-01-01

The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor

A programmable systolic trigger processor for FERA bus data

International Nuclear Information System (INIS)

Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

1992-09-01

A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, N.; Baird, S.A.; Biddulph, P.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

Upgrade of the ATLAS Level‐1 trigger with an FPGA based Topological Processor

CERN Document Server

Caputo, R; The ATLAS collaboration; Buescher, V; Degele, R; Kiese, P; Maldaner, S; Reiss, A; Schaefer, U; Simioni, E; Tapprogge, S; Urejola, P

2013-01-01

The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of high energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). LHC proton collision at a frequency of 40 MHz, requires a trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5$\\mu$s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up to 3$\\times$10$^{34}$cm$^{−2}$s$^{−1}$ in 2015, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receive data in a dedicated format from the calorimeters ...

Upgrade of the ATLAS Level-1 trigger with an FPGA based Topological Processor

CERN Document Server

Caputo, R; The ATLAS collaboration; Buescher, V; Degele, R; Kiese, P; Maldaner, S; Reiss, A; Schaefer, U; Simioni, E; Tapprogge, S; Urrejola, P

2013-01-01

The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of high energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a proton collision at a frequency of 40 MHz, and thus requires a trigger system to efficiently select events down to a manageable event storage rate of about 400Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5$\\mu$s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up to 3$\\times$10$^{34}$ cm$^{−2}$ s$^{−1}$ from 2015 onwards, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receives data in a dedicate...

Commissioning the ATLAS Level-1 Central Trigger System

CERN Document Server

Sherman, Daniel

2010-01-01

The ATLAS Level-1 central trigger is a critical part of ATLAS operation. It receives the 40 MHz bunch clock from the LHC and distributes it to all sub-detectors. It initiates their read-out by forming the Level-1 Accept decision, which is based on information from the calorimeter and muon trigger processors and a variety of additional trigger inputs from detectors in the forward region. It also provides trigger summary information to the data acquisition system and the Level-2 trigger system. In this paper, we present the completion of the installed central trigger system, its performance during cosmic-ray data taking and the experience gained with triggering on the first LHC beams.

Trigger and decision processors

International Nuclear Information System (INIS)

Franke, G.

1980-11-01

In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

The TIGER trigger processor for the CAMERA detector at COMPASS-II

Energy Technology Data Exchange (ETDEWEB)

Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut der Universitaet Freiburg, Freiburg im Breisgau (Germany)

2013-07-01

In today's nuclear and high-energy physics experiments the background-induced occupancy of the detector channels can be quite high; therefore it is important to have sophisticated trigger subsystems which process the data in real-time to generate trigger objects for the global trigger decision. In this work we present a FPGA based low-latency trigger processor for the COMPASS-II experiment. TIGER is a high-performance trigger processor that was developed to fit perfectly in the GANDALF framework and extend its versatility. It is designed as a VXS module and is allocated to the central VXS switch slot, which has a direct link from every payload slot. The synchronous transfer protocol was optimized for low latencies and offers a bandwidth of up to 8 Gbit/s per link. The centerpiece of the board is a Xilinx Virtex-6 SX315T FPGA, offering vast programmable logic, embedded memory and DSP resources. It is accompanied by DDR3 memory, a COM Express CPU and a MXM GPU. Besides the VXS backplane ports, the board features two SFP+ transceivers, 32 LVDS inputs and 32 LVDS outputs to interface with the global trigger system and a Gigabit Ethernet port for configuration and monitoring.

The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade

CERN Document Server

Lazovich, Tomo; The ATLAS collaboration

2015-01-01

The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can ...

The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning

CERN Document Server

Simioni, E; The ATLAS collaboration

2014-01-01

The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of highly energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a beam collision frequency of 40 MHz, and thus requires a trigger system to efficiently select events, thereby reducing the storage rate to a manageable level of about 400 Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up 3 x 10^34/cm2 s from 2015 onwards, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receives data in a specialized format from the ...

The UA1 trigger processor

International Nuclear Information System (INIS)

Grayer, G.H.

1981-01-01

Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)

A fast processor for di-lepton triggers

CERN Document Server

Kostarakis, P; Barsotti, E; Conetti, S; Cox, B; Enagonio, J; Haldeman, M; Haynes, W; Katsanevas, S; Kerns, C; Lebrun, P; Smith, H; Soszyniski, T; Stoffel, J; Treptow, K; Turkot, F; Wagner, R

1981-01-01

As a new application of the Fermilab ECL-CAMAC logic modules a fast trigger processor was developed for Fermilab experiment E-537, aiming to measure the higher mass di-muon production by antiprotons. The processor matches the hit information received from drift chambers and scintillation counters, to find candidate muon tracks and determine their directions and momenta. The tracks are then paired to compute an invariant mass: when the computed mass falls within the desired range, the event is accepted. The process is accomplished in times of 5 to 10 microseconds, while achieving a trigger rate reduction of up to a factor of ten. (5 refs).

A general-purpose trigger processor system and its application to fast vertex trigger

International Nuclear Information System (INIS)

Hazumi, M.; Banas, E.; Natkaniec, Z.; Ostrowicz, W.

1997-12-01

A general-purpose hardware trigger system has been developed. The system comprises programmable trigger processors and pattern generator/samplers. The hardware design of the system is described. An application as a prototype of the very fast vertex trigger in an asymmetric B-factory at KEK is also explained. (author)

The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units

CERN Document Server

Tavares Delgado, Ademar; The ATLAS collaboration

2016-01-01

The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units Type: Talk Abstract: We present the ATLAS Trigger algorithms developed to exploit General­ Purpose Graphics Processor Units. ATLAS is a particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system has two levels, hardware-­based Level 1 and the High Level Trigger implemented in software running on a farm of commodity CPU. Performing the trigger event selection within the available farm resources presents a significant challenge that will increase future LHC upgrades. are being evaluated as a potential solution for trigger algorithms acceleration. Key factors determining the potential benefit of this new technology are the relative execution speedup, the number of GPUs required and the relative financial cost of the selected GPU. We have developed a trigger demonstrator which includes algorithms for reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Cal...

The fast tracker processor for hadronic collider triggers

CERN Document Server

Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G

2000-01-01

Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution traces with transverse momentum above few GeV and search secondary vertexes within typical level-2 times. 15 Refs.

The fast tracker processor for hadron collider triggers

CERN Document Server

Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

2001-01-01

Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

Operation of the Upgraded ATLAS Level-1 Central Trigger System

CERN Document Server

Glatzer, Julian Maximilian Volker; The ATLAS collaboration

2015-01-01

The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of 2 with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the double amount of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to 3 different sub-detector combinations. In this contribution, we give an overview of the operational software framework of the L1CT system with particular emphasis of the configuration, controls and monitoring aspects. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are m...

M7--a high speed digital processor for second level trigger selections

International Nuclear Information System (INIS)

Droege, T.F.; Gaines, I.; Turner, K.J.

1978-01-01

A digital processor is described which reconstructs mass and momentum as a second-level trigger selection. The processor is a five-address, microprogramed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor

On-line trigger processor in PETRA/DORIS experiments at DESY

CERN Document Server

ölschläger, R

1981-01-01

Data, presented at a poster session, on on-line trigger processing are given. Brief details of trigger processors at the detectors CELLO, TASSO and ARAUS are shown, including: general working method; IC technology; power consumption; logic elements for trigger decision; number of chambers; number of input wires; execution time; parameter variation; links to host computer; cost; test features. (0 refs).

The Level 0 Trigger Processor for the NA62 experiment

International Nuclear Information System (INIS)

Chiozzi, S.; Gamberini, E.; Gianoli, A.; Mila, G.; Neri, I.; Petrucci, F.; Soldi, D.

2016-01-01

In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

The Level 0 Trigger Processor for the NA62 experiment

Energy Technology Data Exchange (ETDEWEB)

Chiozzi, S. [INFN, Ferrara (Italy); Gamberini, E. [University of Ferrara and INFN, Ferrara (Italy); Gianoli, A. [INFN, Ferrara (Italy); Mila, G. [University of Turin and INFN, Turin (Italy); Neri, I., E-mail: neri@fe.infn.it [University of Ferrara and INFN, Ferrara (Italy); Petrucci, F. [University of Ferrara and INFN, Ferrara (Italy); Soldi, D. [University of Turin and INFN, Turin (Italy)

2016-07-11

In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

Development of the new trigger processor board for the ATLAS Level-1 endcap muon trigger for Run-3

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00525035; The ATLAS collaboration

2017-01-01

The instantaneous luminosity of the LHC will be increased by up to a factor of three with respect to the original design value at Run-3 (starting 2021). The ATLAS Level-1 end-cap muon trigger in LHC Run-3 will identify muons by combining data from the Thin-Gap Chamber detector (TGC) and the New Small Wheel (NSW), which is a new detector and will be able to operate in a high background hit rate at Run-3, to suppress the Level-1 trigger rate. In order to handle data from both TGC and NSW, a new trigger processor board has been developed. The board has a modern FPGA to make use of Multi-Gigabit transceiver technology. The readout system for trigger data has also been designed with TCP/IP instead of a dedicated ASIC. This letter presents the electronics and its firmware of the ATLAS Level-1 end-cap muon trigger processor board for LHC Run-3.

Level Zero Trigger processor for the ultra rare kaon decay experiment—NA62

CERN Document Server

Chiozzi, S; Gianoli, A; Mila, G; Neri, I; Petrucci, F; Soldi, D

2016-01-01

n the NA62 experiment at CERN-SPS the communication between detectors and the Lowest Level (L0) trigger processor is performed via Ethernet packets, using the UDP protocol. The L0 Trigger Processor handles the signals from sub-detectors that take part to the trigger generation. In order to choose the best solution for its realization, two different approaches have been implemented. The first approach is fully based on a FPGA device while the second one joins an off-the-shelf PC to the FPGA. The performance of the two systems will be discussed and compared.

ATLAS Level-1 Calorimeter Trigger Subsystem Tests of a Prototype Cluster Processor Module

CERN Document Server

Garvey, J; Apostologlou, P; Ay, C; Barnett, B M; Bauss, B; Brawn, I P; Bohm, C; Dahlhoff, A; Davis, A O; Edwards, J; Eisenhandler, E F; Gee, C N P; Gillman, A R; Hanke, P; Hellman, S; Hidévgi, A; Hillier, S J; Jakobs, K; Kluge, E E; Landon, M; Mahboubi, K; Mahout, G; Meier, K; Meshkov, P; Moye, T H; Mills, D; Moyse, E; Nix, O; Penno, K; Perera, V J O; Qian, W; Schmitt, K; Schäfer, U; Silverstein, S; Staley, R J; Thomas, J; Trefzger, T M; Watkins, P M; Watson, A; 9th Workshop On Electronics For LHC Experiments - LECC 2003

2003-01-01

The Level-1 Calorimeter Trigger consists of a Preprocessor (PP), a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce trigger multiplicity and Region-of-Interest (RoI) information. The trigger will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes by using Readout Driver (ROD) Modules. The CP Modules (CPM) are designed to find isolated electron/photon and hadron/tau clusters in overlapping windows of trigger towers. Each pipelined CPM processes 8-bit data from a total of 128 trigger towers at each LHC crossing. Four full-specification prototypes of CPMs have been built and results of complete tests on individual boards will be presented. These modules were then integrated with other modules to build an ATLAS Level-1 Calorimeter Trigger subsystem test bench. Realtime data were exchanged between modules, and time-slice readout data were tagged and transferr...

A fast filter processor as a part of the trigger logic in an elastic scattering experiment

International Nuclear Information System (INIS)

Kenyon Gjerpe, I.

1981-01-01

A fast special purpose processor as a part of the trigger logic in an elastic scattering experiment is described. The decision to incorporate such a processor was taken because the trigger rate was estimated to be an order of magnitude higher than the date taking capability of the on-line minicomputer, a NORD 10. The processor is capable of checking the coplanarity and the opening angle of the two outgoing tracks within about 100 μs. This is done with a spatial resolution of 1 mm by using two points each track given by 3 MWPCs. For comparison this is two orders of magnitude faster than the same algorithm coded in assembly language on a PDP 11/40. The main contribution to this increased speed is due to extensive use of pipelining and parallelism. When running with the processor in the trigger, 75% more elastic events per incoming beam particle were collected, and 3 times as many elastic events per trigger were recorded on to tape for further in-depth analysis, than previously. Due to major improvements in the primary trigger logic this was less than the gain initially anticipated. A first version of the processor was designed and constructed in the CERN DD division by J. Joosten, M. Letheren and B. Martin under the supervision of C. Verkerk. The author was involved in the final design, construction and testing, and subsequently was responsible for the intergration, programming and running of the processor in the experiment. (orig.)

The processor farm for online triggering and full event reconstruction of the HERA-B experiment at HERA

International Nuclear Information System (INIS)

Gellrich, A.; Dippel, R.; Gensch, U.; Kowallik, R.; Legrand, I.C.; Leich, H.; Sun, F.; Wegner, P.

1996-01-01

The main goal of the HERA-B experiment which start taking data in 1988 is to study CP violation in B decays. This article describes the concept and the planned implementation of a multi-processor system, called processor farm,as the last part of the data acquisition and trigger system of the HERA B experiment. The third level trigger task and a full online event reconstruction will be performed on this processor farm, consisting of more then 100 powerful RISC processors which are based on commercial hardware boards. The controlling will be done by a real-time operating system which provides a software development environment, including FORTRAN and C compilers. (author)

Programmable level-1 trigger with 3D-Flow processor array

International Nuclear Information System (INIS)

Crosetto, D.

1994-01-01

The 3D-Flow parallel processing system is a new concept in processor architecture, system architecture, and assembly architecture. Compared to the electronics used in present systems, this approach reduces the cost and complexity of the hardware and allows easy assembly, disassembly, incremental upgrading, and maintenance of different interconnection topologies. The 3D-Flow parallel-processing system benefits high energy physics (HEP) by allowing: (1) common less costly hardware to be used in different experiments. (2) new uses of existing installations. (3) tuning of trigger based on the first analyzed data, and (4) selection of desired events directly from raw data. The goal of this parallel-processing architecture is to acquire multiple data in parallel (up to 100 million frames per second) and to process them at high speed, accomplishing digital filtering on the input data, pattern recognition (particle identification), data moving, and data formatting. The main features of the system are its programmability, scalability, high-speed communication, and low cost. The compactness of the 3D-Flow parallel-processing system in concert with the processor architecture allows processor interconnections to be mapped into the geometry of sensors (detectors in HEP) without large interconnection signal delay, enabling real-time pattern recognition. The overall 3D-Flow project has passed a major design review at Fermilab (Reviewers included experts in computers, triggering, system assembly, and electronics)

Eight-Channel Digital Signal Processor and Universal Trigger Module

Science.gov (United States)

Skulski, Wojtek; Wolfs, Frank

2003-04-01

A 10-bit, 8-channel, 40 megasamples per second digital signal processor and waveform digitizer DDC-8 (nicknamed Universal Trigger Module) is presented. The digitizer features 8 analog inputs, 1 analog output for a reconstructed analog waveform, 16 NIM logic inputs, 8 NIM logic outputs, and a pool of 16 TTL logic lines which can be individually configured as either inputs or outputs. The first application of this device is to enhance the present trigger electronics for PHOBOS at RHIC. The status of the development and the first results are presented. Possible applications of the new device are discussed. Supported by the NSF grant PHY-0072204.

A track reconstructing low-latency trigger processor for high-energy physics

International Nuclear Information System (INIS)

Cuveland, Jan de

2009-01-01

The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 μs to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 μs with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

A track reconstructing low-latency trigger processor for high-energy physics

Energy Technology Data Exchange (ETDEWEB)

Cuveland, Jan de

2009-09-17

The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 {mu}s to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 {mu}s with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

Physics performances with the new ATLAS Level-1 Topological trigger in Run 2

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00414333; The ATLAS collaboration

2016-01-01

The ATLAS trigger system aims at reducing the 40 MHz proton-proton collision event rate to a manageable event storage rate of 1 kHz, preserving events valuable for physics analysis. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: The Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. More than one hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. This information will be essential to improve background reject...

The ATLAS Level-1 Trigger Timing Setup

CERN Document Server

Spiwoks, R; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

2005-01-01

The ATLAS detector at CERN's LHC will be exposed to proton-proton collisions at a bunch-crossing rate of 40 MHz. In order to reduce the data rate, a three-level trigger system selects potentially interesting physics. The first trigger level is implemented in electronics and firmware. It aims at reducing the output rate to less than 100 kHz. The Central Trigger Processor combines information from the calorimeter and muon trigger processors and makes the final Level-1-Accept decision. It is a central element in the timing setup of the experiment. Three aspects are considered in this article: the timing setup with respect to the Level-1 trigger, with respect to the expriment, and with respect to the world.

Topological and Central Trigger Processor for 2014 LHC luminosities

CERN Document Server

Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; Buscher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; Mattig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Schafer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

2012-01-01

The ATLAS experiment is located at the European Center for Nuclear Research (CERN) in Switzerland. It is designed to observe phenomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4 10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 micro seconds. It is primarily composed of the Calori...

Topological and Central Trigger Processor for 2014 LHC luminosities

CERN Document Server

Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; B\\"{u}scher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; M\\"{a}ttig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Sch\\"{a}fer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

2012-01-01

The ATLAS experiment is located at the European Center for Nu- clear Research (CERN) in Switzerland. It is designed to observe phe- nomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4×10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the AT- LAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5μs. It is primarily composed of the Calorimete...

Fast track-finding trigger processor for the SLAC/LBL Mark II Detector

International Nuclear Information System (INIS)

Brafman, H.; Breidenbach, M.; Hettel, R.; Himel, T.; Horelick, D.

1977-10-01

The SLAC/LBL Mark II Magnetic Detector consists of various particle detectors arranged in cylindrical symmetry located in and around an axial magnetic field. A versatile, programmable secondary trigger processor was designed and built to find curved tracks in the detector. The system operates at a 10 MHz clock rate with a total processing time of 34 μsec and is used to ''trigger'' the data processing computer, thereby rejecting background and greatly improving the data acquisition aspects of the detector-computer combination

Smart Trigger Pre-Processor Custom Electronics for the PHENIX Experiment

International Nuclear Information System (INIS)

Nagle, James L.

2003-01-01

OAK-B135 The document provides a final technical report on activities and accomplishments of the experimental relativistic heavy ion physics group at the University of Colorado at Boulder as supported by the Outstanding Junior Investigator Program, Division of Nuclear Physics at the Department of Energy. All of the goals of the grant proposal were achieved during this last year of the Outstanding Junior Investigator funding period. The development of a Smart Trigger Pre-Processor module for fast trigger primitive calculations in the PHENIX experiment has been completed. We finalized the board design, constructed and tested two prototype modules, and with additional funding from the PHENIX project, we fabricated a full set of 15 modules for the Muon Tracking system. During Run-4 at RHIC:, we have begun the process of integrating these modules into the PHENIX data acquisition system, Additionally, we put a large Effort into developing new trigger and fast-track analysis methods for J j J data filtering and reconstruction. These algorithms make use of the trigger primitivE∼s generated via the new electronics

Upgrade of the PreProcessor System for the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Khomich, A

2010-01-01

The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5\\,us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serialisers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.

Upgrade of the PreProcessor System for the ATLAS LVL1 Calorimeter Trigger

CERN Document Server

Khomich, A; The ATLAS collaboration

2010-01-01

The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serializers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.

A Track Reconstructing Low-latency Trigger Processor for High-energy Physics

CERN Document Server

AUTHOR|(CDS)2067518

2009-01-01

The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 µs to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbps via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's dr...

Physics performances with the new ATLAS Level-1 Topological trigger in the LHC High-Luminosity Era

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00414333; The ATLAS collaboration

2016-01-01

The ATLAS trigger system aim at reducing the 40 MHz protons collision event rate to a manageable event storage rate of 1 kHz, preserving events with valuable physics meaning. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: L1Topo, the Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. Over hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. Such information will be essential to improve background rejection and ...

Level Zero Trigger Processor for the NA62 experiment

Science.gov (United States)

Soldi, D.; Chiozzi, S.

2018-05-01

The NA62 experiment is designed to measure the ultra-rare decay K+ arrow π+ ν bar nu branching ratio with a precision of ~ 10% at the CERN Super Proton Synchrotron (SPS). The trigger system of NA62 consists in three different levels designed to select events of physics interest in a high beam rate environment. The L0 Trigger Processor (L0TP) is the lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the NA62 L0TP system is a new approach compared to existing systems used in high-energy physics experiments. It is fully digital, based on a standard gigabit Ethernet communication between detectors and the L0TP Board. The L0TP Board is a commercial development board, mounting a programmable logic device (FPGA). The primitives generated by sub-detectors are sent asynchronously using the UDP protocol to the L0TP during the entire beam spill period. The L0TP realigns in time the primitives coming from seven different sources and performs a data selection based on the characteristics of the event such as energy, multiplicity and topology of hits in the sub-detectors. It guarantees a maximum latency of 1 ms. The maximum input rate is about 10 MHz for each sub-detector, while the design maximum output trigger rate is 1 MHz. A description of the trigger algorithm is presented here.

The ATLAS Level-1 Topological Trigger Performance

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00371751; The ATLAS collaboration

2016-01-01

The LHC will collide protons in the ATLAS detector with increasing luminosity through 2016, placing stringent operational and physical requirements to the ATLAS trigger system in order to reduce the 40 MHz collision rate to a manageable event storage rate of 1 kHz, while not rejecting interesting physics events. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. During the LHC shutdown after the Run 1 finished in 2013, the Level-1 trigger system was upgraded including hardware, firmware and software updates. In particular, new electronics modules were introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. They receive real-time information from the Level-1 calorimeter and muon triggers, which...

Level-1 Calorimeter Trigger starts firing

CERN Multimedia

Stephen Hillier

2007-01-01

L1Calo is one of the major components of ATLAS First Level trigger, along with the Muon Trigger and Central Trigger Processor. It forms all of the first-level calorimeter-based triggers, including electron, jet, tau and missing ET. The final system consists of over 250 custom designed 9U VME boards, most containing a dense array of FPGAs or ASICs. It is subdivided into a PreProcessor, which digitises the incoming trigger signals from the Liquid Argon and Tile calorimeters, and two separate processor systems, which perform the physics algorithms. All of these are highly flexible, allowing the possibility to adapt to beam conditions and luminosity. All parts of the system are read out through Read-Out Drivers, which provide monitoring data and Region of Interest (RoI) information for the Level-2 trigger. Production of the modules is now essentially complete, and enough modules exist to populate the full scale system in USA15. Installation is proceeding rapidly - approximately 90% of the final modules are insta...

An FPGA based demonstrator for a topological processor in the future ATLAS L1-Calo trigger “GOLD”

CERN Document Server

Ebling, A; Büscher, V; Degele, R; Ji, W; Meyer, C; Moritz, S; Schäfer, U; Simioni, E; Tapprogge, S; Wenzel, V

2012-01-01

Abstract: The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the maximum value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the ATLAS Level-1 Calorimeter Trigger electronics chain: the Topological Processor (TP). Such a processor needs fast optical I/O and large aggregate bandwidth to use the information on trigger object position in space (e.g. jets in the calorimeters or muons measured in the muon detectors) to improve the purity of the L1 triggers streams by applying topological cuts within the L1 latency budget. In this paper, an overview of the adopted technological solutions and the R&D activities on the demonstrator for th...

Beam Test of the ATLAS Level-1 Calorimeter Trigger System

CERN Document Server

Garvey, J; Mahout, G; Moye, T H; Staley, R J; Thomas, J P; Typaldos, D; Watkins, P M; Watson, A; Achenbach, R; Föhlisch, F; Geweniger, C; Hanke, P; Kluge, E E; Mahboubi, K; Meier, K; Meshkov, P; Rühr, F; Schmitt, K; Schultz-Coulon, H C; Ay, C; Bauss, B; Belkin, A; Rieke, S; Schäfer, U; Tapprogge, T; Trefzger, T; Weber, GA; Eisenhandler, E F; Landon, M; Apostologlou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Mirea, A; Perera, V J O; Qian, W; Sankey, D P C; Bohm, C; Hellman, S; Hidvegi, A; Silverstein, S

2005-01-01

The Level-1 Calorimter Trigger consists of a Preprocessor (PP), a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce Region-of-Interest (RoIs) and trigger multiplicities. The latter are sent in real time to the Central Trigger Processor (CTP) where the Level-1 decision is made. On receipt of a Level-1 Accept, Readout Driver Modules (RODs), provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purpose. RoI information is sent to the RoI builder (RoIB) to help reduce the amount of data required for the Level-2 Trigger The Level-1 Calorimeter Trigger System at the test beam consisted of 1 Preprocessor module, 1 Cluster Processor Module, 1 Jet/Energy Module and 2 Common Merger Modules. Calorimeter energies were sucessfully handled thourghout the chain and trigger object sent to the CTP. Level-1 Accepts were sucessfully produced and used to drive the readout path. Online diagno...

A trigger simulation framework for the ALICE experiment

International Nuclear Information System (INIS)

Antinori, F; Carminati, F; Gheata, A; Gheata, M

2011-01-01

A realistic simulation of the trigger system in a complex HEP experiment is essential for performing detailed trigger efficiency studies. The ALICE trigger simulation is evolving towards a framework capable of replaying the full trigger chain starting from the input to the individual trigger processors and ending with the decision mechanisms of the ALICE central trigger processor. This paper describes the new ALICE trigger simulation framework that is being tested and deployed. The framework handles details like trigger levels, signal delays and busy signals, implementing the trigger logic via customizable trigger device objects managed by a robust scheduling mechanism. A big advantage is the high flexibility of the framework, which is able to mix together components described with very different levels of detail. The framework is being gradually integrated within the ALICE simulation and reconstruction frameworks.

Firmware implementation of algorithms for the new topological processor in the ATLAS first level trigger

Energy Technology Data Exchange (ETDEWEB)

Maldaner, Stephan; Caputo, Regina; Schaefer, Ulrich; Tapprogge, Stefan [Universitaet Mainz, Staudingerweg 7, 55128 Mainz (Germany)

2013-07-01

After the upgrade of the Large Hadron Collider in 2013/2014 proton-proton collisions will be provided at a center-of-mass energy of up to 14 TeV with an instantaneous luminosity of at least 1 . 10{sup 34} cm{sup -2}s{sup -1}. During this upgrade a new FPGA based electronics system (Topological Processor) will be included in the ATLAS trigger chain to keep up with the increased rate of events. To reduce rates while maintaining high signal efficiency of the trigger the processor will make its decisions based upon topological criteria like angular cuts and mass calculations. As a hardware based trigger, it will have to fit into the tight first level trigger latency budget of 2.5 μs and thus provides the challenge of making decisions within very short time. Beside the latency, the main constraints on the algorithms are the required amount of logic resources of the FPGA which will be implemented as firmware. Therefore to be able to use as much information as possible, each module will be equipped with 2 state-of-the-art Xilinx Virtex 7 FPGAs to process the incoming data. This talk will present some of the topological algorithms and discuss properties of their implementation in firmware.

The STAR Level-3 trigger system

International Nuclear Information System (INIS)

Adler, C.; Berger, J.; Demello, M.; Dietel, T.; Flierl, D.; Landgraf, J.; Lange, J.S.; LeVine, M.J.; Ljubicic, A.; Nelson, J.; Roehrich, D.; Stock, R.; Struck, C.; Yepes, P.

2003-01-01

The STAR Level-3 trigger issues a trigger decision upon a complete online reconstruction of Au+Au collisions at relativistic heavy ion collider energies. Central interactions are processed up to a rate of 50 s -1 including a simple analysis of physics observables. The setup of the processor farm and the event reconstruction as well as experiences and the proposed trigger algorithms are described

Calorimeter trigger system for the ISR axial-field spectrometer

International Nuclear Information System (INIS)

1981-01-01

A fast and flexible trigger processor system designed to run in parallel up to 51 different types of trigger is used in a large hadron calorimeter experiment at CERN-ISR. A very fast data bus connected to 255 10 bit address ECL memory chips allows programmable selection of events according to their topology and energy pattern in less than 150 ns. In addition this system can interrogate two programmable processors (ESOP) to isolate events characterized by a large energy flow in the central drift chamber (< 500 μs). All functions of the trigger processor can be checked externally by a computer through injecting in parallel simulated input signals into various stages of the system. Salient features and performances will be discussed

A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

International Nuclear Information System (INIS)

Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

1991-01-01

The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

The Hardware Topological Trigger of ATLAS: Commissioning and Operations

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00226165; The ATLAS collaboration

2018-01-01

The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. To improve the physics potential reach in ATLAS, during the LHC shutdown after Run 1, the Level-1 trigger system was upgraded at hardware, firmware and software level. In particular, a new electronics sub-system was introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. For individual blades, real-time information from calorimeter and muon Level-1 trigger systems, is processed by four individual state-of-the-art FPGAs. It needs to deal with a large input bandwidth of up to 6 Tb/s, optical connectivity and low processing latency on the real-time data path. The L1Topo firmware apply measurements of angles between jets and/or leptons and several...

Online track processor for the CDF upgrade

International Nuclear Information System (INIS)

Thomson, E. J.

2002-01-01

A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

arXiv Level Zero Trigger Processor for the NA62 experiment

CERN Document Server

INSPIRE-00584493; Chiozzi, Stefano

2018-05-02

The NA62 experiment is designed to measure the ultra-rare decay K+ arrow π+ ν  branching ratio with a precision of ~ 10% at the CERN Super Proton Synchrotron (SPS). The trigger system of NA62 consists in three different levels designed to select events of physics interest in a high beam rate environment. The L0 Trigger Processor (L0TP) is the lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the NA62 L0TP system is a new approach compared to existing systems used in high-energy physics experiments. It is fully digital, based on a standard gigabit Ethernet communication between detectors and the L0TP Board. The L0TP Board is a commercial development board, mounting a programmable logic device (FPGA). The primitives generated by sub-detectors are sent asynchronously using the UDP protocol to the L0TP during the entire beam spill period. The L0TP realigns in time the primitives coming from seven different sources and performs a data selectio...

The ATLAS Level-1 Topological Trigger Design and Operation in Run-2

CERN Document Server

Igonkina, Olga; The ATLAS collaboration

2018-01-01

The ATLAS Level-1 Trigger system performs initial event selection using data from calorimeters and the muon spectrometer to reduce the LHC collision event rate down to about 100 kHz. Trigger decisions from the different sub-systems are combined in the Central Trigger Processor for the final Level-1 decision. A new FPGAs-based AdvancedTCA sub-system was introduced to calculate in real time complex kinematic observables: the Topological Processor System. It was installed during the shutdown and commissioning started in 2015 and continued during 2016. The design and operation of the Level-1 Topological Trigger in Run-2 will be illustrated.

Multi­-Threaded Algorithms for General purpose Graphics Processor Units in the ATLAS High Level Trigger

CERN Document Server

Conde Mui\\~no, Patricia; The ATLAS collaboration

2016-01-01

General purpose Graphics Processor Units (GPGPU) are being evaluated for possible future inclusion in an upgraded ATLAS High Level Trigger farm. We have developed a demonstrator including GPGPU implementations of Inner Detector and Muon tracking and Calorimeter clustering within the ATLAS software framework. ATLAS is a general purpose particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system consists of two levels, with level 1 implemented in hardware and the High Level Trigger implemented in software running on a farm of commodity CPU. The High Level Trigger reduces the trigger rate from the 100 kHz level 1 acceptance rate to 1 kHz for recording, requiring an average per­-event processing time of ~250 ms for this task. The selection in the high level trigger is based on reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Calorimeter. Performing this reconstruction within the available farm resources presents a significant ...

Track recognition in 4 μs by a systolic trigger processor using a parallel Hough transform

International Nuclear Information System (INIS)

Klefenz, F.; Noffz, K.H.; Conen, W.; Zoz, R.; Kugel, A.; Maenner, R.; Univ. Heidelberg

1993-01-01

A parallel Hough transform processor has been developed that identifies circular particle tracks in a 2D projection of the OPAL jet chamber. The high-speed requirements imposed by the 8 bunch crossing mode of LEP could be fulfilled by computing the starting angle and the radius of curvature for each well defined track in less than 4 μs. The system consists of a Hough transform processor that determines well defined tracks, and a Euler processor that counts their number by applying the Euler relation to the thresholded result of the Hough transform. A prototype of a systolic processor has been built that handles one sector of the jet chamber. It consists of 35 x 32 processing elements that were loaded into 21 programmable gate arrays (XILINX). This processor runs at a clock rate of 40 MHz. It has been tested offline with about 1,000 original OPAL events. No deviations from the off-line simulation have been found. A trigger efficiency of 93% has been obtained. The prototype together with the associated drift time measurement unit has been installed at the OPAL detector at LEP and 100k events have been sampled to evaluate the system under detector conditions

Elementary function calculation programs for the central processor-6

International Nuclear Information System (INIS)

Dobrolyubov, L.V.; Ovcharenko, G.A.; Potapova, V.A.

1976-01-01

Subprograms of elementary functions calculations are given for the central processor (CP AS-6). A procedure is described to obtain calculated formulae which represent the elementary functions as a polynomial. Standard programs for random numbers are considered. All the programs described are based upon the algorithms of respective programs for BESM computer

Upgrade of the ATLAS Level-1 Trigger with event topology information

CERN Document Server

Simioni, Eduard; The ATLAS collaboration; Bauss, B; Büscher, V; Jakobi, K; Kaluza, A; Kahra, C; Reiss, A; Schäffer, J; Schulte, A; Simon, M; Tapprogge, S; Vogel, A; Zinser, M; Palka, M

2015-01-01

The Large Hadron Collider (LHC) in 2015 will collide proton beams with increased luminosity from \\unit{10^{34}} up to \\unit{3 \\times 10^{34}cm^{-2}s^{-1}}. ATLAS is an LHC experiment designed to measure decay properties of high energetic particles produced in the protons collisions. The higher luminosity places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events with valuable physics meaning. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than 2.5$\\mu s$. It is composed of the Calorimeter Trigger (L1Calo), the Muon Trigger (L1Muon) and the Central Trigger Processor (CTP). In 2014, there will be a new electronics element in the chain: the Topological Processor System (L1Topo system).\\\\ The L1Topo system consist of a single AdvancedTCA shelf equipped with three L1Topo processor ...

A dedicated line-processor as used at the SHF

International Nuclear Information System (INIS)

Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.

1985-01-01

A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made

The new Level-1 Topological Trigger for the ATLAS experiment at the Large Hadron Collider

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00047907; The ATLAS collaboration

2017-01-01

At the CERN Large Hadron Collider, the world’s most powerful particle accelerator, the ATLAS experiment records high-energy proton collision to investigate the properties of fundamental particles. These collisions take place at a 40 MHz, and the ATLAS trigger system selects the interesting ones, reducing the rate to 1 kHz, allowing for their storage and subsequent offline analysis. The ATLAS trigger system is organized in two levels, with increasing degree of details and of accuracy. The first level trigger reduces the event rate to 100 kHz with a decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. A new component of the first-level trigger was introduced in 2015: the Topological Processor (L1Topo). It allows to use detailed real-time information from the Level-1 calorimeter and muon systems, to compute advanced kinematic quantities using state of the art FPGA processors, and to select interesting events based on several com...

The JET fast central acquisition and trigger system

International Nuclear Information System (INIS)

Blackler, K.; Edwards, A.W.

1994-01-01

This paper describes a new data acquisition system at JET which uses Texas TMS320C40 parallel digital signal processors and the HELIOS parallel operating system to reduce the large amounts of experimental data produced by fast diagnostics. This unified system features a two level trigger system which performs real-time activity detection together with asynchronous event classification and selection. This provides automated data reduction during an experiment. The system's application to future fusion machines which have almost continuous operation is discussed

The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning

CERN Document Server

Simioni, E; The ATLAS collaboration

2014-01-01

The ATLAS detector at the Large Hadron Collider (LHC) is designed to measure decay properties of high energetic particles produced in the proton-proton collisions. During its first run, the LHC collided proton bunches at a frequency of 20 MHz, and therefore the detector required a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3$\\times$$10^{34}cm^{-2}s^{-1}$: this represent an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from physics point of view, a new element will be included in the Level-1 Trigger scheme after 2015: the Topological Processor (L1Topo).\\\\ The L1Topo system, currently developed at CERN, will consist initially of an ATCA crate and two L1Topo modules. A high density opto-electroconverter (AVAGO miniPOD) drives up to 1.6 Tb/s of data from the calorimeter and muon detectors into two high end ...

Sub-nanosecond clock synchronization and trigger management in the nuclear physics experiment AGATA

International Nuclear Information System (INIS)

Bellato, M; Isocrate, R; Rampazzo, G; Bazzacco, D; Bortolato, D; Triossi, A; Chavas, J; Mengoni, D; Recchia, F

2013-01-01

The new-generation spectrometer AGATA, the Advanced GAmma Tracking Array, requires sub-nanosecond clock synchronization among readout and front-end electronics modules that may lie hundred meters apart. We call GTS (Global Trigger and Synchronization System) the infrastructure responsible for precise clock synchronization and for the trigger management of AGATA. It is made of a central trigger processor and nodes, connected in a tree structure by means of optical fibers operated at 2Gb/s. The GTS tree handles the synchronization and the trigger data flow, whereas the trigger processor analyses and eventually validates the trigger primitives centrally. Sub-nanosecond synchronization is achieved by measuring two different types of round-trip times and by automatically correcting for phase-shift differences. For a tree of depth two, the peak-to-peak clock jitter at each leaf is 70 ps; the mean phase difference is 180 ps, while the standard deviation over such phase difference, namely the phase equalization repeatability, is 20 ps. The GTS system has run flawlessly for the two-year long AGATA campaign, held at the INFN Legnaro National Laboratories, Italy, where five triple clusters of the AGATA sub-array were coupled with a variety of ancillary detectors

Sub-nanosecond clock synchronization and trigger management in the nuclear physics experiment AGATA

Science.gov (United States)

Bellato, M.; Bortolato, D.; Chavas, J.; Isocrate, R.; Rampazzo, G.; Triossi, A.; Bazzacco, D.; Mengoni, D.; Recchia, F.

2013-07-01

The new-generation spectrometer AGATA, the Advanced GAmma Tracking Array, requires sub-nanosecond clock synchronization among readout and front-end electronics modules that may lie hundred meters apart. We call GTS (Global Trigger and Synchronization System) the infrastructure responsible for precise clock synchronization and for the trigger management of AGATA. It is made of a central trigger processor and nodes, connected in a tree structure by means of optical fibers operated at 2Gb/s. The GTS tree handles the synchronization and the trigger data flow, whereas the trigger processor analyses and eventually validates the trigger primitives centrally. Sub-nanosecond synchronization is achieved by measuring two different types of round-trip times and by automatically correcting for phase-shift differences. For a tree of depth two, the peak-to-peak clock jitter at each leaf is 70 ps; the mean phase difference is 180 ps, while the standard deviation over such phase difference, namely the phase equalization repeatability, is 20 ps. The GTS system has run flawlessly for the two-year long AGATA campaign, held at the INFN Legnaro National Laboratories, Italy, where five triple clusters of the AGATA sub-array were coupled with a variety of ancillary detectors.

The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning

CERN Document Server

INSPIRE-00226165

2014-01-01

The ATLAS detector at LHC will require a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3 x 10^34 cm-2s-1, this represents an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from a physics point of view, a new element will be included in the Level-1 Trigger scheme after 2015: the Topological Processor (L1Topo). The L1Topo system, currently developed at CERN, will consist initially of an ATCA crate and two L1Topo modules. A high density opto-electroconverter (AVAGO miniPOD) drives up to 1.6 Tb/s of data from the calorimeter and muon detectors into two high-end FPGA (Virtex7-690), to be processed in about 200 ns. The design has been optimized to guarantee excellent signal in- tegrity of the high-speed links and low latency data transmission on the Real Time Data Path (RTDP). The L1Topo receives data in a standa...

An R&D programme on alternative technologies for the ATLAS level-1 calorimeter trigger

CERN Document Server

Appelquist, G; Bohm, C; Engström, M; Hellman, S; Holmgren, S O; Johansson, E; Yamdagni, N; Zhao, X; Sundblad, R; Ödmark, A; Bodo, P; Elderstig, H; Hentzell, H; Lindgren, S; Tober, M; Johansson, H; Svensson, C; Yuan, J R; Mohktari, M; Ellis, Nick

1995-01-16

This note describes a first-level calorimeter trigger processor designed to take advantage of new possibilities that arise as a consequence of modern design techniques and components such as optical interconnections, application specific integrated circuits (ASICs) and multi-chip modules (MCMs). The design is homogeneous down to the trigger cell level. This means that no boundary effects occur due to the system partitioning. The construction presented relies mainly on two different types of highly complex ASICs for processing and an MCM for opto-electrical conversion of input data. The trigger processor performs electron/photon identification, jet detection and missing ET calculations for the central first-level trigger and region of interest (RoI) selection for the second-level trigger. Exploring the possibilities given by advanced technologies leads to a first-level trigger architecture with advantages over more traditional designs, allowing, for example, higher precision calculations. Remaining degrees of ...

Progress on the Level-1 Calorimeter Trigger

CERN Multimedia

Eric Eisenhandler

The Level-1 Calorimeter Trigger (L1Calo) has recently passed a number of major hurdles. The various electronic modules that make up the trigger are either in full production or are about to be, and preparations in the ATLAS pit are well advanced. L1Calo has three main subsystems. The PreProcessor converts analogue calorimeter signals to digital, associates the rather broad trigger pulses with the correct proton-proton bunch crossing, and does a final calibration in transverse energy before sending digital data streams to the two algorithmic trigger processors. The Cluster Processor identifies and counts electrons, photons and taus, and the Jet/Energy-sum Processor looks for jets and also sums missing and total transverse energy. Readout drivers allow the performance of the trigger to be monitored online and offline, and also send region-of-interest information to the Level-2 Trigger. The PreProcessor (Heidelberg) is the L1Calo subsystem with the largest number of electronic modules (124), and most of its fu...

Trigger processing using reconfigurable logic in the CMS calorimeter trigger

Energy Technology Data Exchange (ETDEWEB)

Brooke, J J; Cussans, D G; Heath, G P; Maddox, A J; Newbold, D M; Rabbetts, P D

2001-04-01

We present the design of the Global Calorimeter Trigger processor for the CMS detector at LHC. This is a fully pipelined processor system which collects data from all the CMS calorimeters and produces summary information used in forming the Level-1 trigger decision for each event. The design in based on the use of state-of-the-art reconfigurable logic devices (FPGAs) and fast data links. We present the results of device testing using a low-latency pipelined sort algorithm, which demonstrate that an FPGA can be used to perform processing previously foreseen to require custom ASICs. Our design approach results in a powerful, flexible and compact processor system.

Data driven processor 'Vertex Trigger' for B experiments

International Nuclear Information System (INIS)

Hartouni, E.P.

1993-01-01

Data Driven Processors (DDP's) are specialized computation engines configured to solve specific numerical problems, such as vertex reconstruction. The architecture of the DDP which is the subject of this talk was designed and implemented by W. Sippach and B.C. Knapp at Nevis Lab. in the early 1980's. This particular implementation allows multiple parallel streams of data to provide input to a heterogenous collection of simple operators whose interconnection form an algorithm. The local data flow control allows this device to execute algorithms extremely quickly provided that care is taken in the layout of the algorithm. I/O rates of several hundred megabytes/second are routinely achieved thus making DDP's attractive candidates for complex online calculations. The original question was open-quote can a DDP reconstruct tracks in a Silicon Vertex Detector, find events with a separated vertex and do it fast enough to be used as an online trigger?close-quote Restating this inquiry as three questions and describing the answers to the questions will be the subject of this talk. The three specific questions are: (1) Can an algorithm be found which reconstructs tracks in a planar geometry and no magnetic field; (2) Can separated vertices be recognized in some way; (3) Can the algorithm be implemented in the Nevis-UMass and DDP and execute in 10-20 μs?

The ATLAS Muon and Tau Trigger

CERN Document Server

Dell'Asta, L; The ATLAS collaboration

2013-01-01

[Muon] The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys a three-levels processing scheme for the trigger system. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 (L2) trigger followed by an event filter (EF) for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. Trigger-specific algorithms were developed and are used for the L2 to increase processing speed for instance by making use of look-up tables and simpler algorithms, while the EF muon triggers mostly benefit from offline reconstruction software to obtain most precise determination of the track parameters. There are two algorithms with different approaches, namely inside-out and outside-in...

Graphical processors for HEP trigger systems

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R. [INFN Sezione di Roma Tor Vergata, Via della Ricerca Scientifica, 1, 00133 Roma (Italy); Biagioni, A. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Chiozzi, S.; Cotta Ramusino, A. [INFN Sezione di Ferrara, Via Saragat, 1, 44122 Ferrara (Italy); Di Lorenzo, S. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Università di Pisa, Lungarno Pacinotti 43, 56126 Pisa (Italy); Fantechi, R. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Fiorini, M. [INFN Sezione di Ferrara, Via Saragat, 1, 44122 Ferrara (Italy); Università di Ferrara, Via Ludovico Ariosto 35, 44121 Ferrara (Italy); Frezza, O. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Lamanna, G. [INFN, Laboratori Nazionali di Frascati (Italy); Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P.S.; Pastorelli, E. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Piandani, R. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Pontisso, L., E-mail: luca.pontisso@cern.ch [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Rossetti, D. [NVIDIA Corp., Santa Clara, CA (United States); Simula, F. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Sozzi, M. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Università di Pisa, Lungarno Pacinotti 43, 56126 Pisa (Italy); and others

2017-02-11

General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.

Graphical processors for HEP trigger systems

International Nuclear Information System (INIS)

Ammendola, R.; Biagioni, A.; Chiozzi, S.; Cotta Ramusino, A.; Di Lorenzo, S.; Fantechi, R.; Fiorini, M.; Frezza, O.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P.S.; Pastorelli, E.; Piandani, R.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.

2017-01-01

General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.

VIRTUS: a multi-processor system in FASTBUS

International Nuclear Information System (INIS)

Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

1986-01-01

VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

Central Nervous System (CNS Disease Triggering Takotsubo Syndrome

Directory of Open Access Journals (Sweden)

Josef Finsterer

2016-01-01

Full Text Available Takotsubo syndrome (TTS is usually triggered by psychological or physical stress. One of the many physical sources of stress are central nervous system (CNS disorders. CNS disorders most frequently triggering TTS include subarachnoid bleeding, epilepsy, ischemic stroke, migraine, and intracerebral bleeding. More rare CNS-triggers of TTS include posterior reversible encephalopathy syndrome (PRES, amyotrophic lateral sclerosis, encephalitis, or traumatic brain or spinal cord injury. TTS triggered by any of the CNS disorders needs to be recognized since adequate treatment of TTS may improve the general outcome from the CNS disorder as well. Neurologists need to be aware of TTS as a complication of specific CNS disorders but TTS may be triggered also by CNS disorders so far not recognised as causes of TTS.

Proceedings of the workshop on triggering and data acquisition for experiments at the Supercollider

Energy Technology Data Exchange (ETDEWEB)

Donaldson, R. [ed.

1989-04-01

This meeting covered the following subjects: triggering requirements for SSC physics; CDF level 3 trigger; D0 trigger design; AMY trigger systems; Zeus calorimeter first level trigger; data acquisition for the Zeus Central Tracking Detector; trigger and data acquisition aspects for SSC tracking; data acquisition systems for the SSC; validating triggers in CDF level 3; optical data transmission at SSC; time measurement system at SSC; SSC/BCD data acquisition system; microprocessors and other processors for triggering and filtering at the SSC; data acquisition, event building, and on-line processing; LAA real-time benchmarks; object-oriented system building at SSC; and software and project management. Selected papers are indexed separately for inclusion in the Energy Science and Technology Database.

Triggers in UA2 and UA1

International Nuclear Information System (INIS)

Dorenbosch, J.

1985-01-01

The UA2 and UA1 trigger systems are described as they will be used after the upgrade of the CERN SPPS. The luminosity of the collider will increase to 3x10 30 . The bunch spacing is 4 microseconds, comparable to the time available for a second level trigger at the SSC. The first level triggers are very powerful and deliver trigger rates of about 100 Hz. The UA1 second level trigger operates on the final digitizings with a combination of special and general purpose processors. At the highest trigger levels a small farm of processors performs the final reduction. (orig.)

Use of a track and vertex processor in a fixed-target charm experiment

International Nuclear Information System (INIS)

Schub, M.H.; Carey, T.A.; Hsiung, Y.B.; Kaplan, D.M.; Lee, C.; Miller, G.; Sa, J.; Teng, P.K.

1996-01-01

We have constructed and operated a high-speed parallel-pipelined track and vertex processor and used it to trigger data acquisition in a high-rate charm and beauty experiment at Fermilab. The processor uses information from hodoscopes and wire chambers to reconstruct tracks in the bend view of a magnetic spectrometer, and uses these tracks to find the corresponding tracks in a set of silicon-strip detectors. The processor then forms vertices and triggers the experiment if at least one vertex is downstream of the target. Under typical charm running conditions, with an interaction rate of ∼5 MHz, the processor rejects 80-90% of lower-level triggers while maintaining efficiency of ∼70% for two-prong D-meson decays. (orig.)

A programmable systolic array correlator as a trigger processor for electron pairs in rich (ring image Cherenkov) counters

Science.gov (United States)

Männer, R.

1989-12-01

This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128 x 128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8 x 8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology.

A programmable systolic array correlator as a trigger processor for electron pairs in RICH (ring image Cherenkov) counters

International Nuclear Information System (INIS)

Maenner, R.

1989-01-01

This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128x128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8x8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology. (orig.)

Performance of the ATLAS first-level Trigger with first LHC Data

CERN Document Server

Lundberg, J; The ATLAS collaboration

2010-01-01

ATLAS is one of the two general-purpose detectors at the Large Hadron Collider (LHC). Its trigger system must reduce the anticipated proton collision rate of up to 40 MHz to a recordable event rate of 100-200 Hz. This is realized through a multi-level trigger system. The first-level trigger is implemented with custom-built electronics and makes an initial selection which reduces the rate to less than 100 kHz. The subsequent trigger selection is done in software run on PC farms. The first-level trigger decision is made by the central-trigger processor using information from coarse grained calorimeter information, dedicated muon-trigger detectors, and a variety of additional trigger inputs from detectors in the forward regions. We present the performance of the first-level trigger during the commissioning of the ATLAS detector during early LHC running. We cover the trigger strategies used during the different machine commissioning phases from first circulating beams and splash events to collisions. It is descri...

An FPGA-based trigger processor for a measurement of deeply virtual Compton scattering at the COMPASS-II experiment

Energy Technology Data Exchange (ETDEWEB)

Schopferer, Sebastian

2013-12-16

The COMPASS-II experiment at CERN is focusing on a measurement of the deeply virtual Compton scattering. Several upgrades of the experimental setup have been performed in 2012, namely the construction of a long liquid hydrogen target and a surrounding recoil proton detector called CAMERA. Based on a time-of-flight measurement between two barrels of scintillators, the CAMERA detector allows to detect protons with a kinetic energy down to 35 MeV, which leave the target under large polar angles. At the same time, protons can be distinguished from other particles resulting from background processes by means of an energy loss measurement in the scintillating material. In order to extend the existing COMPASS trigger scheme, a digital trigger system has been developed, which is detailed in the thesis at hand. The trigger system is able to select events with a recoil proton in the final state while suppressing background events, using the particle identification capabilities of the CAMERA detector. Challenging selection criteria based on both the time-of-flight and the energy loss measurement call for a powerful programmable logic board. At the same time, the integration into the existing COMPASS trigger system poses strict constraints on the latency of the trigger decision. For the implementation of the proton trigger system, a new FPGA-based trigger and DAQ hardware called TIGER has been built. The module is operated in two firmware configurations, serving two distinct purposes. Firstly, the trigger processor is responsible for the generation of a trigger signal based on recoil particles, which is included in the global first-level trigger decision. Secondly, a readout concentrator allows to multiplex the data streams of up to 18 readout modules into one link to the DAQ. The CAMERA detector and the corresponding readout and trigger electronics was commissioned during a test run in autumn 2012. This thesis contains details about the trigger concept, the development of the

ATLAS FTK: Fast Track Trigger

CERN Document Server

Volpi, Guido; The ATLAS collaboration

2015-01-01

An overview of the ATLAS Fast Tracker processor is presented, reporting the design of the system, its expected performance, and the integration status. The next LHC runs, with a significant increase in instantaneous luminosity, will provide a big challenge to the trigger and data acquisition systems of all the experiments. An intensive use of the tracking information at the trigger level will be important to keep high efficiency in interesting events, despite the increase in multiple p-p collisions per bunch crossing (pile-up). In order to increase the use of tracks within the High Level Trigger (HLT), the ATLAS experiment planned the installation of an hardware processor dedicated to tracking: the Fast TracKer (FTK) processor. The FTK is designed to perform full scan track reconstruction at every Level-1 accept. To achieve this goal, the FTK uses a fully parallel architecture, with algorithms designed to exploit the computing power of custom VLSI chips, the Associative Memory, as well as modern FPGAs. The FT...

The new UA1 calorimeter trigger

International Nuclear Information System (INIS)

Eisenhandler, E.

1988-01-01

The new UA1 first-level calorimeter trigger processor is described, with emphasis on the fast two-dimensional electromagnetic cluster-finding that is its most novel feature. This processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. (author)

The Level-1 Tile-Muon Trigger in the Tile Calorimeter upgrade program

International Nuclear Information System (INIS)

Ryzhov, A.

2016-01-01

The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). TileCal provides highly-segmented energy measurements for incident particles. Information from TileCal's outermost radial layer can assist in muon tagging in the Level-1 Muon Trigger by rejecting fake muon triggers due to slow charged particles (typically protons) without degrading the efficiency of the trigger. The main activity of the Tile-Muon Trigger in the ATLAS Phase-0 upgrade program was to install and to activate the TileCal signal processor module for providing trigger inputs to the Level-1 Muon Trigger. This report describes the Tile-Muon Trigger, focusing on the new detector electronics such as the Tile Muon Digitizer Board (TMDB) that receives, digitizes and then provides the signal from eight TileCal modules to three Level-1 muon endcap Sector-Logic Boards.

Natrium: Use of FPGA embedded processors for real-time data compression

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

2011-12-15

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Natrium: Use of FPGA embedded processors for real-time data compression

International Nuclear Information System (INIS)

Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2011-01-01

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

A silicon track trigger for the DOe experiment

International Nuclear Information System (INIS)

Narain, Meenakshi

2000-01-01

The design of a processor to trigger on long-lived particles (e.g. b-quarks) for the DOe experiment at the Fermilab Tevatron is presented. This device reconstructs the trajectory of the charged particles in the DOe tracking system, which consists of a central fiber tracker and a silicon microstrip tracker. The r-phi impact parameter resolution of the fitted tracks is about 40 μm. This enables the identification of the long-lived b-quarks produced in the decays of various particles, e.g. the top quarks, Higgs Boson, techni-particles and other exotic particles produced in pp-bar collisions at the Tevatron. In this report we describe the design of the architecture and algorithms for the Silicon Track Trigger

A silicon track trigger for the DOe experiment

CERN Document Server

Narain, M

2000-01-01

The design of a processor to trigger on long-lived particles (e.g. b-quarks) for the DOe experiment at the Fermilab Tevatron is presented. This device reconstructs the trajectory of the charged particles in the DOe tracking system, which consists of a central fiber tracker and a silicon microstrip tracker. The r-phi impact parameter resolution of the fitted tracks is about 40 mu m. This enables the identification of the long-lived b-quarks produced in the decays of various particles, e.g. the top quarks, Higgs Boson, techni-particles and other exotic particles produced in pp-bar collisions at the Tevatron. In this report we describe the design of the architecture and algorithms for the Silicon Track Trigger.

Graphics Processors in HEP Low-Level Trigger Systems

International Nuclear Information System (INIS)

Ammendola, Roberto; Biagioni, Andrea; Chiozzi, Stefano; Ramusino, Angelo Cotta; Cretaro, Paolo; Lorenzo, Stefano Di; Fantechi, Riccardo; Fiorini, Massimiliano; Frezza, Ottorino; Lamanna, Gianluca; Cicero, Francesca Lo; Lonardo, Alessandro; Martinelli, Michele; Neri, Ilaria; Paolucci, Pier Stanislao; Pastorelli, Elena; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Vicini, Piero

2016-01-01

Usage of Graphics Processing Units (GPUs) in the so called general-purpose computing is emerging as an effective approach in several fields of science, although so far applications have been employing GPUs typically for offline computations. Taking into account the steady performance increase of GPU architectures in terms of computing power and I/O capacity, the real-time applications of these devices can thrive in high-energy physics data acquisition and trigger systems. We will examine the use of online parallel computing on GPUs for the synchronous low-level trigger, focusing on tests performed on the trigger system of the CERN NA62 experiment. To successfully integrate GPUs in such an online environment, latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Furthermore, it is assessed how specific trigger algorithms can be parallelized and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen Large Hadron Collider (LHC) luminosity upgrade where highly selective algorithms will be essential to maintain sustainable trigger rates with very high pileup

Commodity multi-processor systems in the ATLAS level-2 trigger

International Nuclear Information System (INIS)

Abolins, M.; Blair, R.; Bock, R.; Bogaerts, A.; Dawson, J.; Ermoline, Y.; Hauser, R.; Kugel, A.; Lay, R.; Muller, M.; Noffz, K.-H.; Pope, B.; Schlereth, J.; Werner, P.

2000-01-01

Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems

Commodity multi-processor systems in the ATLAS level-2 trigger

CERN Document Server

Abolins, M; Bock, R; Bogaerts, J A C; Dawson, J; Ermoline, Y; Hauser, R; Kugel, A; Lay, R; Müller, M; Noffz, K H; Pope, B; Schlereth, J L; Werner, P

2000-01-01

Low cost SMP (symmetric multi-processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS we consider them as intelligent input buffers (an "active" ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4- processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term programme of work. The SMP systems may be considered as an important building block in future data acquisition systems. (9 refs).

The multilevel trigger system of the DIRAC experiment

International Nuclear Information System (INIS)

Afanas'ev, L.; Gallas, M.; Goldin, D.

2002-01-01

The multilevel trigger system of the DIRAC experiment at CERN is presented. It includes a fast first level trigger as well as various trigger processors to select events with a pair of pions having a low relative momentum typical of the physical process under study. One of these processors employs the drift chamber data, another one is based on a neural network algorithm and the others use various hit-map detector correlations. Two versions of the trigger system used at different stages of the experiment are described. The complete system reduces the event rate by a factor of 1000, with efficiency ≥ 95 % of detecting the events in the relative momentum range of interest

The Heidelberg POLYP - a flexible and fault-tolerant poly-processor

International Nuclear Information System (INIS)

Maenner, R.; Deluigi, B.

1981-01-01

The Heidelberg poly-processor system POLYP is described. It is intended to be used in nuclear physics for reprocessing of experimental data, in high energy physics as second-stage trigger processor, and generally in other applications requiring high-computing power. The POLYP system consists of any number of I/O-processors, processor modules (eventually of different types), global memory segments, and a host processor. All modules (up to several hundred) are connected by a multiple common-data-bus system; all processors, additionally, by a multiple sync bus system for processor/task-scheduling. All hard- and software is designed to be decentralized and free of bottle-necks. Most hardware-faults like single-bit errors in memory or multi-bit errors during transfers are automatically corrected. Defective modules, buses, etc., can be removed with only a graceful degradation of the system-throughput. (orig.)

The new Global Muon Trigger of the CMS experiment

CERN Document Server

Fulcher, Jonathan Richard; Rabady, Dinyar Sebastian; Reis, Thomas; Sakulin, Hannes

2016-01-01

For the 2016 physics data runs the L1 trigger system of the Compact Muon Solenoid (CMS) experiment underwent a major upgrade to cope with the increasing instantaneous luminosity of the CERN LHC whilst maintaining a high event selection efficiency for the CMS physics program. Most subsystem specific trigger processor boards were replaced with powerful general purpose processor boards, conforming to the MicroTCA standard, whose tasks are performed by firmware on an FPGA of the Xilinx Virtex 7 family. Furthermore, the muon trigger system moved from a subsystem centered approach, where each of the three muon detector systems provides muon candidates to the Global Muon Trigger (GMT), to a region based system, where muon track finders (TFs) combine information from the subsystems to generate muon candidates in three detector regions, that are then sent to the upgraded GMT. The upgraded GMT receives up to 108 muons from the processors of the muon TFs in the barrel, overlap, and endcap detector regions. The muons are...

Timing, Trigger and Control Systems for LHC Detectors

CERN Multimedia

2002-01-01

\\\\ \\\\At the LHC, precise bunch-crossing clock and machine orbit signals must be broadcast over distances of several km from the Prevessin Control Room to the four experiment areas and other destinations. At the LHC experiments themselves, quite extensive distribution systems are also required for the transmission of timing, trigger and control (TTC) signals to large numbers of front-end electronics controllers from a single location in the vicinity of the central trigger processor. The systems must control the detector synchronization and deliver the necessary fast signals and messages that are phased with the LHC clock, orbit or bunch structure. These include the bunch-crossing clock, level-1 trigger decisions, bunch and event numbers, as well as test signals and broadcast commands. A common solution to this TTC system requirement is expected to result in important economies of scale and permit a rationalization of the development, operational and support efforts required. LHC Common Project RD12 is developi...

Starbursts triggered by central overpressure in interacting galaxies

Science.gov (United States)

Jog, Chanda J.; Das, Mousumi

1993-01-01

A triggering mechanism for the origin of enhanced, massive-star formation in the central regions of interacting spiral galaxy pairs is proposed. Our mechanism is based on the detailed evolution of a realistic interstellar medium in a galaxy following an encounter. As a disk giant molecular cloud (GMC) tumbles into the central region following a galaxy encounter, it undergoes a radiative shock compression via the pre-existing high pressure of the central intercloud medium. The shocked outer shell of a GMC becomes gravitationally unstable and begins to fragment thus resulting in a burst of star formation, when the growth time for the gravitational instabilities in the shell becomes smaller than the crossing time of the shock. The resulting values of typical infrared luminosity agree with observations.

Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC Operations

CERN Document Server

Madorsky, Alexander

2009-01-01

D. Acosta, M. Fisher, I. Furic, J. Gartner, G.P. Di Giovanni, A. Hammar, K. Kotov, A. Madorsky, D. Wang University of Florida/Physics, POB 118440, Gainesville, FL, USA, 32611 L. Uvarov Petersburg Nuclear Physics Institute, Gatchina, Russia M. Matveev, P. Padley Rice University, MS 61, 6100 Main Street, Houston, TX, USA, 77005 The conceptual design for a Level-1 muon track-finder trigger for the CMS endcap muon system is proposed that can accommodate the increased particle occupancy and system constraints of the proposed SLHC accelerator upgrade and the CMS detector upgrades. A brief review of the architecture of the current track-finder for LHC trigger operation is given, with potential bottlenecks indicated for SLHC operation. The upgraded track-finding processors described here would receive as many as two track segments detected from every cathode strip chamber comprising the endcap muon system, up to a total of 18 per 60 degree azimuthal sector. This would dramatically improve the efficiency of the ...

Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC operations

CERN Document Server

Acosta, D; Furic, I; Gartner, J; Di Giovanni, G P; Hammar, A; Kotov, K; Madorsky, A; Matveev, M; Padley, P; Uvarov, L; Wang, D

2009-01-01

The conceptual design for a Level-1 muon track-finder trigger for the CMS endcap muon system is proposed that can accommodate the increased particle occupancy and system constraints of the proposed SLHC accelerator upgrade and the CMS detector upgrades. A brief review of the architecture of the current track-finder for LHC trigger operation is given, with potential bottlenecks indicated for SLHC operation. The upgraded track-finding processors described here would receive as many as two track segments detected from every cathode strip chamber comprising the endcap muon system, up to a total of 18 per 60° azimuthal sector. This would dramatically improve the efficiency of the track reconstruction in a high occupancy environment over the current design. However, such an improvement would require significantly higher bandwidth and logic resources. We propose to use the fastest available serial links, running asynchronously to the machine clock to use their full bandwidth. The work of creating a firmware model f...

The D-Zero Run II Trigger

International Nuclear Information System (INIS)

Blazey, G. C.

1997-01-01

The general purpose D0 collider detector, located at Fermi National Accelerator Laboratory, requires significantly enhanced data acquisition and triggering to operate in the high luminosity (L = 2 x 10 32 cm -2 s -1 ), high rate environment (7 MHz or 132 ns beam crossings) of the upgraded TeVatron proton anti-proton accelerator. This article describes the three major levels and frameworks of the new trigger. Information from the first trigger stage (L1) which includes scintillating, tracking and calorimeter detectors will provide a deadtimeless, 4.2 (micro)s trigger decision with an accept rate of 10 kHz. The second stage (L2), comprised of hardware engines associated with specific detectors and a single global processor will test for correlations between L1 triggers. L2 will have an accept rate of 1 kHz at a maximum deadtime of 5% and require a 100 (micro)s decision time. The third and final stage (L3) will reconstruct events in a farm of processors for a final instantaneous accept rate of 50 Hz

The Phase-1 Upgrade for the Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC

CERN Document Server

Izzo, Vincenzo; The ATLAS collaboration

2018-01-01

The Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC makes use of Resistive Plate Chamber (RPC) detectors. The on-detector trigger electronics modules are able to identify muons with predefined transverse momentum values (pT) by executing a coincidence logic on signals coming from the various detector layers. On-detector trigger boards then transfer trigger data to the off-detector electronics. A complex trigger system processes the incoming data by combining trigger information from the barrel and the endcap regions, and providing the combined muon candidate to the Central Trigger Processor (CTP). For almost a decade, the Level-1 Trigger system operated very well, despite the challenging requirements on trigger efficiency and performance, and the continuously increasing LHC luminosity. In order to cope with these constraints, various upgrades for the full trigger system were already deployed, and others have been designed to be installed in the next years. Most of the upgrades to the trigger system...

A Time-Multiplexed Track-Trigger architecture for CMS

CERN Document Server

Hall, Geoffrey; Pesaresi, Mark Franco; Rose, A

2014-01-01

The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ``PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on cur...

Performance measurement of the upgraded D0 central track trigger

International Nuclear Information System (INIS)

Mommsen, Remigius K.; Manchester U.

2006-01-01

The D0 experiment was upgraded in spring 2006 to harvest the full physics potential of the Tevatron accelerator at Fermi National Accelerator Laboratory, Batavia, Illinois, USA. It is expected that the peak luminosity delivered by the accelerator will increase to over 300 x 10 30 cm -2 s -1 . One of the upgraded systems is the Central Track Trigger (CTT). The CTT uses the Central Fiber Tracker (CFT) and Preshower detectors to identify central tracks with p T > 1.5GeV at the first trigger level. Track candidates are formed by comparing fiber hits to predefined track equations. In order to minimize latency, this operation is performed in parallel using combinatorial logic implemented in FPGAs. Limited hardware resources prevented the use of the full granularity of the CFT. This leads to a high fake track rate as the occupancy increases. In order to mitigate the problem, new track-finding hardware was designed and commissioned. We report on the upgrade and the improved performance of the CTT system

The Phase-1 Upgrade for the Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC

CERN Document Server

Izzo, Vincenzo; The ATLAS collaboration

2018-01-01

The Level-1 Barrel Trigger of the ATLAS Experiment is based on Resistive Plate Chambers (RPC) detectors. The on-detector trigger electronics identifies muons with specific values of transverse momentum (pT), by using coincidences between different layers of detectors. Trigger data is then transferred from on-detector to the off-detector trigger electronics boards. Data is processed by a complex system, which combines trigger data from the Barrel and the End-cap regions, and provides the combined muon candidate to the Central Trigger Processor (CTP). The system has been performing very well for almost a decade. However, in order to cope with continuously increasing LHC luminosity and more demanding requirements on trigger efficiency and performance, various upgrades for the full trigger system were already deployed, and others are foreseen in the next years. Most of the trigger upgrades are based on state-of-the-art technologies and allow designing more complex trigger menus, increasing processing power and da...

The Phase-1 Upgrade for the Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC

CERN Document Server

Izzo, Vincenzo; The ATLAS collaboration

2018-01-01

The Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC makes use of Resistive Plate Chamber (RPC) detectors. The on-detector trigger electronics modules are able to identify muons with predefined transverse momentum values (pT) by executing a coincidence logic on signals coming from the various detector layers. Then, on-detector trigger boards transfer trigger data to the off-detector electronics. A complex trigger system processes the incoming data by combining trigger information from the Barrel and the End-cap regions, and by providing the combined muon candidate to the Central Trigger Processor (CTP). For almost a decade, the Level-1 Trigger system has been operating very well, despite the challenging requirements on trigger efficiency and performance, and the continuously increasing LHC luminosity. In order to cope with these constraints, various upgrades for the full trigger system were already deployed, and others have been designed to be installed in the next years. Most of the upgrades to the...

XOP: A second generation fast processor for on-line use in high energy physics experiments

International Nuclear Information System (INIS)

Lingjaerde, T.

1981-01-01

Processors for trigger calculations and data compression in high energy physics are characterized by a high data input capability combined with fas execution of relatively simple routines. In order to achieve the required performance it is advantageous to replace the classical computer instruction-set by microcoded instructions, the various fields of which control the internal subunits in parallel. The fast processor called ESOP is based on such a principle: the different operations are handled step by step by dedicated optimized modules under control of a central instruction unit. Thus, the arithmetic operations, address calculations, conditional checking, loop counts and next instruction evaluation all overlap in time. Based upon the experience from ESOP the architecture of a new processor 'XOP' is beginning to take shape which will be faster and easier to use. In this context the most important innovations are: easy handling of operands in the arithmetic unit by means of three data buses and large data files, a powerful data addressing unit for easy handling of vectors, as well as single operands, and a very flexible logic for conditional branching. Input/output will be made transparent through the introduction of internal fast processors which will be used in conjunction with powerful firmware as a software debugging aid. (orig.)

Programmable trigger for electron pairs in ring image Cherenkov counters

International Nuclear Information System (INIS)

Glab, J.; Baur, R.; Manner, R.

1990-01-01

This paper describes a programmable trigger processor for the recognition of Cherenkov rings in a RICH counter. It identifies open electron pairs and suppresses close conversion and Dalitz pairs within 20 μs. More generally, the system can be used for correlating pixel images with pattern masks in order to locate all relatively well defined patterns of a certain type. The trigger processor consists of a systolic processor array of 160 x 176, i.e., 28,160 identical processing elements (PEs) that filter out open electron pairs, and a pseudo adder array that determines whether there was at least one such pair. The processor array is assembled of 20 x 22 VLSI chips containing 8 x 8 PEs each. The semi-custom chip has been developed in 2 μ CMOS standard cell technology

Flexible trigger menu implementation on the Global Trigger for the CMS Level-1 trigger upgrade

CERN Document Server

Matsushita, Takashi

2017-01-01

The CMS experiment at the Large Hadron Collider (LHC) has continued to explore physics at the high-energy frontier in 2016. The integrated luminosity delivered by the LHC in 2016 was 41~fb$^{-1}$ with a peak luminosity of 1.5 $\\times$ 10$^{34}$ cm$^{-2}$s$^{-1}$ and peak mean pile-up of about 50, all exceeding the initial estimations for 2016. The CMS experiment has upgraded its hardware-based Level-1 trigger system to maintain its performance for new physics searches and precision measurements at high luminosities. The Global Trigger is the final step of the CMS \\mbox{Level-1} trigger and implements a trigger menu, a set of selection requirements applied to the final list of objects from calorimeter and muon triggers, for reducing the 40 MHz collision rate to 100 kHz. The Global Trigger has been upgraded with state-of-the-art FPGA processors on Advanced Mezzanine Cards with optical links running at 10 GHz in a MicroTCA crate. The powerful processing resources of the upgraded system enable implemen...

ATLAS Level-1 Topological Trigger

CERN Document Server

Zheng, Daniel; The ATLAS collaboration

2018-01-01

The ATLAS experiment has introduced and recently commissioned a completely new hardware sub-system of its first-level trigger: the topological processor (L1Topo). L1Topo consist of two AdvancedTCA blades mounting state-of-the-art FPGA processors, providing high input bandwidth (up to 4 Gb/s) and low latency data processing (200 ns). L1Topo is able to select collision events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Results from data recorded using the L1Topo trigger will be presented. These results demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-pT leptons, including H->tau tau and J/Psi->mu mu. In addition to describing the L1Topo trigger system, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize...

Monitoring ATLAS L1 CTP data from P-BEAST

CERN Document Server

Roggel, Jens

2017-01-01

The ATLAS Level-1 Central Trigger Processor combines information from the calori-meters and the muon detectors and takes a decision to accept an event based on a list of selection criteria (trigger items). Busy signals from the detectors and generated dead time by the Central Trigger Processor prevents the buffers to become full. The visualisation of this data is useful to check the functionality of the system. My project during the CERN summer student programme was to develop an application, which produces plots of relevant Central Trigger Processor data and presents the results in an appropriate format for experts and users.

The ATLAS muon trigger performance in pp collisions at sqrt(s) = 8 TeV in year 2012 runs

CERN Document Server

Nobe, T; The ATLAS collaboration

2012-01-01

Events with muons in the final state are an important signature for many physics topics at Large Hadron Collider (LHC), for instance, searches for Higgs boson production or new phenomena, measurements on the standard model processes like top-quark, W, Z production. Thus, efficient trigger on muons in data taking and understanding its performance are crucial to perform these physics studies. At LHC high rejection power against large backgrounds, while maintaining high efficiency for rare signal events, is required for online selection at the trigger level. The ATLAS experiment employs a multi-level trigger architecture that selects the events in three sequential steps of increasing complexity and accuracy to cope with this challenging task. The L1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The Muon HLT is purely software ba...

The CMS Level-1 Calorimeter Trigger for LHC Run II

CERN Document Server

Zabi, Alexandre; Cadamuro, Luca; Davignon, Olivier; Romanteau, Thierry; Strebler, Thomas; Cepeda, Maria Luisa; Sauvan, Jean-baptiste; Wardle, Nicholas; Aggleton, Robin Cameron; Ball, Fionn Amhairghen; Brooke, James John; Newbold, David; Paramesvaran, Sudarshan; Smith, D; Taylor, Joseph Ross; Fountas, Konstantinos; Baber, Mark David John; Bundock, Aaron; Breeze, Shane Davy; Citron, Matthew; Elwood, Adam Christopher; Hall, Geoffrey; Iles, Gregory Michiel; Laner Ogilvy, Christian; Penning, Bjorn; Rose, A; Shtipliyski, Antoni; Tapper, Alexander; Durkin, Timothy John; Harder, Kristian; Harper, Sam; Shepherd-Themistocleous, Claire; Thea, Alessandro; Williams, Thomas Stephen; Dasu, Sridhara Rao; Dodd, Laura Margaret; Klabbers, Pamela Renee; Levine, Aaron; Ojalvo, Isabel Rose; Ruggles, Tyler Henry; Smith, Nicholas Charles; Smith, Wesley; Svetek, Ales; Forbes, R; Tikalsky, Jesra Lilah; Vicente, Marcelo

2017-01-01

Results from the completed Phase 1 Upgrade of the Compact Muon Solenoid (CMS) Level-1 Calorimeter Trigger are presented. The upgrade was completed in two stages, with the first running in 2015 for proton and Heavy Ion collisions and the final stage for 2016 data taking. The Level-1 trigger has been fully commissioned and has been used by CMS to collect over 43 fb-1 of data since the start of the Large Hadron Collider (LHC) Run II. The new trigger has been designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). For this purpose it uses a novel design, the Time Multiplexed Trigger (TMT), which enables the data from an event to be processed by a single trigger processor at full granularity over several bunch crossings. The TMT design is a modular design based on the uTCA standard. The trigger processors are instrumented with Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links. The TMT architecture is flexible and the number of trigger p...

The ATLAS muon trigger: Experience and performance in the first 3 years of LHC pp runs

International Nuclear Information System (INIS)

Ventura, Andrea

2013-01-01

The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys a three-level processing scheme for the trigger system. The Level-1 muon trigger system gets its input from fast muon trigger detectors. Sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a Level-2 trigger followed by an event filter for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. The ATLAS experiment has taken data with high efficiency continuously over entire running periods from 2010 to 2012, for which sophisticated triggers to guard the highest physics output while reducing effectively the event rate were mandatory. The ATLAS muon trigger has successfully adapted to this challenging environment. The selection strategy has been optimized for the various physics analyses involving muons in the final state. This work briefly summarizes these three years of experience in the ATLAS muon trigger and reports about efficiency, resolution, and general performance of the muon trigger

Upgrade of the ALICE transition radiation detector pre-trigger system

Energy Technology Data Exchange (ETDEWEB)

Klewin, Sebastian [Physikalisches Institut, Heidelberg Univ. (Germany); Collaboration: ALICE-Collaboration

2015-07-01

The ALICE TRD pre-trigger system has been designed and built to provide an early wake-up signal for the TRD front-end electronics (FEE). This signal has to arrive 1.15 μs before the Level-0 trigger, which is generated by the Central Trigger Processor (CTP). This independent generation of the signal had during RUN1 some probability of not being confirmed by the CTP L0, which lead to some dead-times. To avoid this, an upgrade strategy has been worked out in which a level-minus-1 (LM) trigger signal, generated by the CTP, replaces the pre-trigger signal. Several efforts had to be made to achieve the ambitious timing: cables had to be rerouted and some electronics had to be relocated to minimize the latency. Additionally a new device had to be developed, which mixes the LM into the TTC protocol and modifies it to a stream suitable for the TRD FEE. Further this device checks the timing of the signals, takes care of the busy handling and provides additional monitoring capabilities. In standalone mode it is also able to generate the necessary signals to trigger the TRD without the CTP. A standard CTP Local Trigger Unit (LTU) was used as hardware, for which a new firmware has been developed to provide these functionalities.

The ATLAS high level trigger region of interest builder

International Nuclear Information System (INIS)

Blair, R.; Dawson, J.; Drake, G.; Haberichter, W.; Schlereth, J.; Zhang, J.; Ermoline, Y.; Pope, B.; Aboline, M.; High Energy Physics; Michigan State Univ.

2008-01-01

This article describes the design, testing and production of the ATLAS Region of Interest Builder (RoIB). This device acts as an interface between the Level 1 trigger and the high level trigger (HLT) farm for the ATLAS LHC detector. It distributes all of the Level 1 data for a subset of events to a small number of (16 or less) individual commodity processors. These processors in turn provide this information to the HLT. This allows the HLT to use the Level 1 information to narrow data requests to areas of the detector where Level 1 has identified interesting objects

Optical computing - an alternate approach to trigger processing

International Nuclear Information System (INIS)

Cleland, W.E.

1981-01-01

The enormous rate reduction factors required by most ISABELLE experiments suggest that we should examine every conceivable approach to trigger processing. One approach that has not received much attention by high energy physicists is optical data processing. The past few years have seen rapid advances in optoelectronic technology, stimulated mainly by the military and the communications industry. An intriguing question is whether one can utilize this technology together with the optical computing techniques that have been developed over the past two decades to develop a rapid trigger processor for high energy physics experiments. Optical data processing is a method for performing a few very specialized operations on data which is inherently two dimensional. Typical operations are the formation of convolution or correlation integrals between the input data and information stored in the processor in the form of an optical filter. Optical processors are classed as coherent or incoherent, according to the spatial coherence of the input wavefront. Typically, in a coherent processor a laser beam is modulated with a photographic transparency which represents the input data. In an incoherent processor, the input may be an incoherently illuminated transparency, but self-luminous objects, such as an oscilloscope trace, have also been used. We consider here an incoherent processor in which the input data is converted into an optical wavefront through the excitation of an array of point sources - either light emitting diodes or injection lasers

3D-Flow processor for a programmable Level-1 trigger (feasibility study)

International Nuclear Information System (INIS)

Crosetto, D.

1992-10-01

A feasibility study has been made to use the 3D-Flow processor in a pipelined programmable parallel processing architecture to identify particles such as electrons, jets, muons, etc., in high-energy physics experiments

Calibration for the ATLAS Level-1 Calorimeter-Trigger

International Nuclear Information System (INIS)

Foehlisch, F.

2007-01-01

This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

Calibration for the ATLAS Level-1 Calorimeter-Trigger

Energy Technology Data Exchange (ETDEWEB)

Foehlisch, F.

2007-12-19

This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

Graphics processor efficiency for realization of rapid tabular computations

International Nuclear Information System (INIS)

Dudnik, V.A.; Kudryavtsev, V.I.; Us, S.A.; Shestakov, M.V.

2016-01-01

Capabilities of graphics processing units (GPU) and central processing units (CPU) have been investigated for realization of fast-calculation algorithms with the use of tabulated functions. The realization of tabulated functions is exemplified by the GPU/CPU architecture-based processors. Comparison is made between the operating efficiencies of GPU and CPU, employed for tabular calculations at different conditions of use. Recommendations are formulated for the use of graphical and central processors to speed up scientific and engineering computations through the use of tabulated functions

ATLAS calorimeter and topological trigger upgrades for Phase 1

CERN Document Server

Silverstein, S

2011-01-01

The ATLAS Level-1 Calorimeter Trigger (L1Calo) collaboration is pursuing two hardware upgrade programs for Phase 1 of the LHC upgrade. The first of these is development of a new mixed-signal multi-chip module (MCM) for the PreProcessor system. based on faster FADCs and a modern FPGA. Designed as a drop-in replacement for the existing MCM, the FPGA also enables future upgrades to the PreProcessor algorithms, including enhanced digital filtering and compensation for time-variation of pedestals. It is also planned to augment the current multiplicity-based trigger by adding topology-based algorithms. This is made possible by adding jet and EM/hadron Regions of Interest (ROIs) to the L1Calo real time data path. A synchronous, pipelined topological processor (TP) based on high-density FPGAs and multi-Gbit optical links gathers all ROI information and performs topological algorithms.

Flexible trigger menu implementation on the Global Trigger for the CMS Level-1 trigger upgrade

Science.gov (United States)

MATSUSHITA, Takashi; CMS Collaboration

2017-10-01

The CMS experiment at the Large Hadron Collider (LHC) has continued to explore physics at the high-energy frontier in 2016. The integrated luminosity delivered by the LHC in 2016 was 41 fb-1 with a peak luminosity of 1.5 × 1034 cm-2s-1 and peak mean pile-up of about 50, all exceeding the initial estimations for 2016. The CMS experiment has upgraded its hardware-based Level-1 trigger system to maintain its performance for new physics searches and precision measurements at high luminosities. The Global Trigger is the final step of the CMS Level-1 trigger and implements a trigger menu, a set of selection requirements applied to the final list of objects from calorimeter and muon triggers, for reducing the 40 MHz collision rate to 100 kHz. The Global Trigger has been upgraded with state-of-the-art FPGA processors on Advanced Mezzanine Cards with optical links running at 10 GHz in a MicroTCA crate. The powerful processing resources of the upgraded system enable implementation of more algorithms at a time than previously possible, allowing CMS to be more flexible in how it handles the available trigger bandwidth. Algorithms for a trigger menu, including topological requirements on multi-objects, can be realised in the Global Trigger using the newly developed trigger menu specification grammar. Analysis-like trigger algorithms can be represented in an intuitive manner and the algorithms are translated to corresponding VHDL code blocks to build a firmware. The grammar can be extended in future as the needs arise. The experience of implementing trigger menus on the upgraded Global Trigger system will be presented.

A Time-Multiplexed Track-Trigger for the CMS HL-LHC upgrade

CERN Document Server

Hall, Geoffrey

2016-01-01

A new CMS Tracker is under development for operation at the High Luminosity LHC from 2025. It includes an outer tracker based on special modules of two different types which will construct track stubs using spatially coincident clusters in two closely spaced sensor layers, to reject low transverse momentum track hits and reduce the data volume before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data outside the detector is under study, using several alternative approaches. One attractive possibility is to exploit a Time Multiplexed design similar to the one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The novel Time Multiplexed Trig...

gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

CERN Document Server

AUTHOR|(SzGeCERN)759889; The ATLAS collaboration; Begel, Michael; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

2016-01-01

The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

CERN Document Server

Tang, Shaochun; The ATLAS collaboration

2015-01-01

The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

Upgrade of the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Wessels, M; The ATLAS collaboration

2014-01-01

The Level-1 Calorimeter Trigger (L1Calo) of the ATLAS experiment has been operating well since the start of LHC data taking, and played a major role in the Higgs boson discovery. To face the new challenges posed by the upcoming increases of the LHC proton beam energy and luminosity, a series of upgrades is planned for L1Calo. The initial upgrade phase in 2013-14 includes substantial improvements to the analogue and digital signal processing to allow more sophisticated digital filters for energy and timing measurement, as well as compensate for pile-up and baseline shifting effects. Two existing digital algorithm processor subsystems will receive substantial hardware and firmware upgrades to increase the real-time data path bandwidth, allowing topological information to be transmitted and processed at Level-1. An entirely new subsystem, the Level-1 Topological Processor, will receive real-time data from both the upgraded L1Calo and Level-1 Muon Trigger to perform trigger algorithms based on entire event topolo...

Commissioning and validation of the ATLAS Level-1 topological trigger

CERN Document Server

AUTHOR|(SzGeCERN)788741; The ATLAS collaboration; Hong, Tae Min

2017-01-01

The ATLAS experiment has recently commissioned a new hardware component of its first-level trigger: the topological processor (L1Topo). This innovative system, using state-of-the-art FPGA processors, selects events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Since the first-level trigger is a synchronous pipelined system, such requirements are applied within a latency of 200ns. We will present the first results from data recorded using the L1Topo trigger; these demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-$P_{T}$ leptons, including $H\\to{}\\tau{}\\tau{}$ and $J/\\Psi\\to{}\\mu{}\\mu{}$. In addition, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize the performance of this new trigger system. To reach ...

A first-level calorimeter trigger for the ATLAS experiment

International Nuclear Information System (INIS)

Perera, V.; Edwards, J.; Gee, N.

1995-01-01

In the RD27 collaboration the authors have carried out system studies on the implementation of the first level calorimeter trigger processor system for the ATLAS experiment to be mounted at the Large Hadron Collider (LHC) at CERN. A demonstrator trigger system operated successfully with the RD3 and RD33 calorimeters at the full 40 MHz LHC bunch crossing (BC) rate. The prototype application-specific integrated circuits (ASICs) in this system each processed data from only a single trigger cell and its environment, which would lead to an extremely large system for ATLAS. Using eight-bit parallel data even the use of ASICs, processing multiple trigger cells would demand unacceptably large numbers of input pins and module connections. Initial studies of this I/O problem produced a solution based on asynchronous transmission of zero-suppressed and BC-tagged data on 160 Mbit/s serial links. This approach appeared to be feasible but would have introduced additional latency of about 20 BCs. Further studies have led to the design of a fully-synchronous calorimeter trigger processor system using commercial high-speed optical links. The links will terminate in multi-chip modules (MCMs) incorporating custom-designed integrated optics, and the trigger algorithms will be implemented in ASICs

The ATLAS fast tracker processor design

CERN Document Server

Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

2015-01-01

The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

The associative memory system for the FTK processor at ATLAS

CERN Document Server

Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

2014-01-01

In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

The design of the ZEUS tracking trigger and studies of b quark fragmentation

Energy Technology Data Exchange (ETDEWEB)

Silvester, I M

1989-01-01

This thesis consists of two parts, describing two very different aspects of experimental elementary particle physics. The first part describes, in detail, the design and estimated performance of a hardware track finding trigger processor. This processor is being built as part of the trigger for the ZEUS experiment, one of the two experiments being built to take data at the HERA electron-proton collider, currently under construction at the DESY laboratories in Hamburg. By using information from the main tracking chamber, the CTD, to reject data from events taking place outside the interaction region, this processor should be able to reduce the event rate from a beam crossing rate of 10{sup 6} s{sup -1} to approximately 9500 s{sup -1}. Used in conjunction with a trigger processor processing calorimeter data it should be able to achieve the desired first level trigger rate of 1 kHz. The second part describes two measurements of the fragmentation variable z for b quarks, made using a b enriched sample of 381 jets taken from the 31000 hadronic events with a centre of mass energy of 35 GeV observed with the TASSO detector during 1986. These measurements, obtained from the mean charged multiplicity and the rapidity distribution, have largely independent systematic uncertainties. The values obtained for (z{sub b}) were combined to give a value of 0.87{+-}0.02{+-}0.04. (author).

The ZEUS second level calorimeter trigger

International Nuclear Information System (INIS)

Jong, S.J. de.

1990-01-01

ZEUS is a detector for the HERA ep collider, consisting of several large components. The most important being the inner tracking detectors, which are positioned nearest to the interaction point, the calorimeter surrounding the inner tracking detectors and the muon detectors on the outside of the experimental setup. Each component will deliver a vast amount of information. In order to keep this information manageable, data is preprocessed and condensed per component and then combined to obtain the final global trigger result. The main subject of this thesis is the second level calorimeter trigger processor of the ZEUS detector. In order to be able to reject the unwanted events passing the first level, the topological event signature will have to be used at the second level. The most demanding task of the second level is the recognition of local energy depositions corresponding to isolated electrons and hadron jets. Also part of the work performed by the first level will be repeated with a higher level of accuracy. Additional information not available to the first level trigger will be processed and will be made available to the global second level trigger decision module. For the second level calorimeter trigger processor a special VME module, containing two transputers, has been developed. The second level calorimeter trigger algorithm described in this thesis was tested with simulated events, that were tracked through a computer simulation of the ZEUS detector. A part of this thesis is therefore devoted to the description of the various Monte Carlo models and the justification of the way in which they were used. (author). 132 refs.; 76 figs.; 18 tabs

ATLAS Level-1 Topological Trigger : Commissioning and Validation in Run 2

CERN Document Server

AUTHOR|(SzGeCERN)788741; The ATLAS collaboration; Hong, Tae Min

2017-01-01

The ATLAS experiment has recently commissioned a new hardware component of its first-level trigger: the topological processor (L1Topo). This innovative system, using state-of-the-art FPGA processors, selects events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Since the first-level trigger is a synchronous pipelined system, such requirements are applied within a latency of 200ns. We will present the first results from data recorded using the L1Topo trigger; these demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-$P_{T}$ leptons, including $H\\to{}\\tau{}\\tau{}$ and $J/\\Psi\\to{}\\mu{}\\mu{}$. In addition, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize the performance of this new trigger system. To reach ...

The data path of the ATLAS level-1 calorimeter trigger preprocessor

Energy Technology Data Exchange (ETDEWEB)

Andrei, George Victor

2010-10-27

The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

The data path of the ATLAS level-1 calorimeter trigger preprocessor

International Nuclear Information System (INIS)

Andrei, George Victor

2010-01-01

The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

The data path of the ATLAS level-1 calorimeter trigger preprocessor

Energy Technology Data Exchange (ETDEWEB)

Andrei, George Victor

2010-10-27

The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

The second level trigger of the L3 experiment. Pt. 1

International Nuclear Information System (INIS)

Bertsch, Y.; Blaising, J.J.; Bonnefon, H.; Chollet-Leflour, F.; Degre, A.; Dromby, G.; Lecoq, J.; Morand, R.; Moynot, M.; Perrot, G.; Riccadonna, X.

1994-01-01

The second level trigger of the L3 experiment performs online background rejection and reduces the first level trigger rate to a value fitting with the third level trigger processing capability. Designed around a set of three bit-slice XOP microprocessors, it can process up to 500 first level triggers per second without significant dead time in the data acquisition. At each LEP beam crossing (45/90 kHz) the complete trigger information (5 kbytes) is memorized in a 1.4 gigabyte bandwidth real dual port memory. The XOP processor builds up the trigger block in less than 400 μs, and signs the background or physics origin of the current event in less than 3 ms. These very high performances rely essentially on the association of parallelism with high speed ECL technology, provided by dedicated processors fully integrated in Fastbus. Emphasis is given here to the specific hardware developed, to its operation and technical aspects of its installation and integration. The system described here ensures the L3 data taking since the beginning of LEP in July 1989 and the online rejection since 1990. (orig.)

A time-multiplexed track-trigger for the CMS HL-LHC upgrade

Energy Technology Data Exchange (ETDEWEB)

Hall, G., E-mail: g.hall@imperial.ac.uk

2016-07-11

A new CMS Tracker is under development for operation at the High Luminosity LHC from 2025. It includes an outer tracker based on special modules of two different types which will construct track stubs using spatially coincident clusters in two closely spaced sensor layers, to reject low transverse momentum track hits and reduce the data volume before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data outside the detector is under study, using several alternative approaches. One attractive possibility is to exploit a Time Multiplexed design similar to the one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The novel Time Multiplexed Trigger concept is explained, the potential benefits for processing future tracker data are described and a feasible design based on currently existing hardware is outlined.

The CDF level-3 trigger

International Nuclear Information System (INIS)

Devlin, T.

1993-01-01

The Collider Detector at Fermilab (CDF) has been operating at the Tevatron and collecting data on proton-antiproton interactions with collision rates above 250,000 Hz. Three levels of filtering select events for data logging at a rate of about 4 Hz. The Level 3 trigger provides most of the capabilities of the offline production programs for event reconstruction and physics analysis. The type of physics triggers, application of cuts, and combinations of logical requirements for event selection are controlled at run time by a trigger table using a syntax fully integrated with the Level 1 and Level 2 hardware triggers. The level 3 software operates in 48 RISC/UNIX processors (over 1000 mips) served by four 20-MByte/sec data buses for input, output and control. The system architecture, debugging, code validation, error reporting, analysis capabilities and performance will be described

Simulation of the ATLAS New Small Wheel trigger

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00399900; The ATLAS collaboration

2018-01-01

The instantaneous luminosity of the LHC will increase up to a factor of seven with respect to the original design value to explore physics at higher energy scale. The inner station of the ATLAS muon end-cap system (Small Wheel) will be replaced by the New Small Wheel (NSW) to benefit from the high luminosity. The NSW will provide precise track-segment information to the Level-1 trigger system in order to suppress the trigger rate from fake muon tracks. This article summarizes the NSW trigger decision system and track-segment finding algorithm implemented in the trigger processor, and discusses results of performance studies on the trigger system. The results demonstrate that the NSW trigger system is capable of working with good performance satisfying the requirements.

Performance of ATLAS RPC Level-1 Muon trigger during the 2015 data taking

CERN Document Server

Corradi, Massimo; The ATLAS collaboration

2016-01-01

The Level-1 Muon Barrel Trigger is one of the main elements of the event selection of the ATLAS experiment at the Large Hadron Collider. Its input stage consists of an array of processors receiving the full granularity of data from Resistive Plate Chambers in the central area of the ATLAS detector ("Barrel"). The trigger efficiency and the level of synchronisation of its elements with the rest of ATLAS and the LHC clock are crucial figures of this system: many parameters of the constituent RPC detector and the trigger electronics have to be constantly and carefully checked to assure a correct functioning of the Level-1 selection. Notwithstanding the complexity of such a large array of integrated RPC detectors, the ATLAS Level-1 system has resumed operations successfully after the past 2 year shutdown, with levels similar to those of Run 1. We present the inclusive monitoring of the RPC+L1 system that we have developed to characterise the behaviour of the system, using reconstructed muons in events selected by...

The DOe Silicon Track Trigger

International Nuclear Information System (INIS)

Steinbrueck, Georg

2003-01-01

We describe a trigger preprocessor to be used by the DOe experiment for selecting events with tracks from the decay of long-lived particles. This Level 2 impact parameter trigger utilizes information from the Silicon Microstrip Tracker to reconstruct tracks with improved spatial and momentum resolutions compared to those obtained by the Level 1 tracking trigger. It is constructed of VME boards with much of the logic existing in programmable processors. A common motherboard provides the I/O infrastructure and three different daughter boards perform the tasks of identifying the roads from the tracking trigger data, finding the clusters in the roads in the silicon detector, and fitting tracks to the clusters. This approach provides flexibility for the design, testing and maintenance phases of the project. The track parameters are provided to the trigger framework in 25 μs. The effective impact parameter resolution for high-momentum tracks is 35 μm, dominated by the size of the Tevatron beam

Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

DEFF Research Database (Denmark)

Liu, Weifeng; Vinter, Brian

2015-01-01

of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement over...

Simulation of the ATLAS New Small Wheel Trigger Sysmtem

CERN Document Server

Saito, Tomoyuki; The ATLAS collaboration

2017-01-01

The instantaneous luminosity of the Large Hadron Collider (LHC) at CERN will be increased up to a factor of five with respect to the original design value to explore higher energy scale. In order to benefit from the expected high luminosity performance, the first station of the ATLAS muon end-cap Small Wheel system will be replaced by a New Small Wheel (NSW) detector. The NSW provide precise track segment information to the muon Level-1 trigger to reduce fake triggers. This contribution will summarize a detail of the NSW trigger decision system, track reconstruction algorithm implemented into the trigger processor and results of performance studies on the trigger system.

ATLAS FTK Fast Track Trigger

CERN Document Server

Iizawa, T; The ATLAS collaboration

2014-01-01

The Fast TracKer (FTK) will perform global track reconstruction after each Level-1 trigger accept signal to enable the software-based higher level trigger to have early access to tracking information. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGAs) form an important part of the system architecture, and the large level of computing power required for pattern recognition is provided by incorporating standard-cell ASICs named Associative Memory (AM). Motivation and the architecture of the FTK system will be presented, and the status of hardware and simulation will be following.

Use of Digital Signal Processors (DSP) in high energy physics experiments

International Nuclear Information System (INIS)

Crosetto, D.

1988-01-01

The FDDP - Fast Digital Data Processor - is a modular system for executing parallel digital processing algorithms to perform programmable trigger decisions or programmable on-line data reduction. Typical application involve zero suppression and pulse shape analysis. The characteristics of the system are: modularity, expandability and flexibility. (author). 4 refs, 5 figs

HEP - A semaphore-synchronized multiprocessor with central control. [Heterogeneous Element Processor

Science.gov (United States)

Gilliland, M. C.; Smith, B. J.; Calvert, W.

1976-01-01

The paper describes the design concept of the Heterogeneous Element Processor (HEP), a system tailored to the special needs of scientific simulation. In order to achieve high-speed computation required by simulation, HEP features a hierarchy of processes executing in parallel on a number of processors, with synchronization being largely accomplished by hardware. A full-empty-reserve scheme of synchronization is realized by zero-one-valued hardware semaphores. A typical system has, besides the control computer and the scheduler, an algebraic module, a memory module, a first-in first-out (FIFO) module, an integrator module, and an I/O module. The architecture of the scheduler and the algebraic module is examined in detail.

The ARGUS vertex trigger

International Nuclear Information System (INIS)

Koch, N.; Kolander, M.; Kolanoski, H.; Siegmund, T.; Bergter, J.; Eckstein, P.; Schubert, K.R.; Waldi, R.; Imhof, M.; Ressing, D.; Weiss, U.; Weseler, S.

1995-09-01

A fast second level trigger has been developed for the ARGUS experiment which recognizes tracks originating from the interaction region. The processor compares the hits in the ARGUS Micro Vertex Drift Chamber to 245760 masks stored in random access memories. The masks which are fully defined in three dimensions are able to reject tracks originating in the wall of the narrow beampipe of 10.5 mm radius. (orig.)

ATLAS calorimetry: Trigger, simulation and jet calibration

CERN Document Server

Weber, Pavel

2008-01-01

The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle phi and in pseud...

The ATLAS Level-1 Calorimeter Trigger Architecture

CERN Document Server

Garvey, J; Mahout, G; Moye, T H; Staley, R J; Watkins, P M; Watson, A T; Achenbach, R; Hanke, P; Kluge, E E; Meier, K; Meshkov, P; Nix, O; Penno, K; Schmitt, K; Ay, Cc; Bauss, B; Dahlhoff, A; Jakobs, K; Mahboubi, K; Schäfer, U; Trefzger, T M; Eisenhandler, E F; Landon, M; Moyse, E; Thomas, J; Apostoglou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Perera, V J O; Qian, W; Bohm, C; Hellman, S; Hidvégi, A; Silverstein, S; RT 2003 13th IEEE-NPSS Real Time Conference

2004-01-01

The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em/tt cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC Timing, Trigger and Control system (TTC). A common data merger module (CMM) uses FPGAs with multiple configurations for summing electron/photon and tau/hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquis...

Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

CERN Document Server

Annovi, A; The ATLAS collaboration; Beretta, M; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Hoff, J; Liu, T; Liberali, V; Sacco, I; Schoening, A; Soltveit, H K; Stabile, A; Tripiccione, R

2011-01-01

We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution patt...

Smart trigger logic for focal plane arrays

Science.gov (United States)

Levy, James E; Campbell, David V; Holmes, Michael L; Lovejoy, Robert; Wojciechowski, Kenneth; Kay, Randolph R; Cavanaugh, William S; Gurrieri, Thomas M

2014-03-25

An electronic device includes a memory configured to receive data representing light intensity values from pixels in a focal plane array and a processor that analyzes the received data to determine which light values correspond to triggered pixels, where the triggered pixels are those pixels that meet a predefined set of criteria, and determines, for each triggered pixel, a set of neighbor pixels for which light intensity values are to be stored. The electronic device also includes a buffer that temporarily stores light intensity values for at least one previously processed row of pixels, so that when a triggered pixel is identified in a current row, light intensity values for the neighbor pixels in the previously processed row and for the triggered pixel are persistently stored, as well as a data transmitter that transmits the persistently stored light intensity values for the triggered and neighbor pixels to a data receiver.

The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

International Nuclear Information System (INIS)

Becam, C.; Bernaudin, P.; Delanghe, J.; Mencik, M.; Merkel, B.; Plothow, H.; Fest, H.M.; Lecoq, J.; Martin, H.; Meyer, J.M.

1981-01-01

The bit slice micro-processor GESPRO, as it is proposed for use in the UA 2 data acquisition chain and trigger system, is a CAMAC module plugged into a standard Elliott System crate via which it communicates as a slave with its host computer (ND, DEC). It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine (150 ns effective cycle time) with multi-mode memory addressing capacity of 64 K words. The micro-processor structure uses 5 busses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2 K (RAM) words of 48 bits each. A special hardwired module allows floating point (as well as integer) multiplication of 24 x 24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: a) online data reduction, i.e. to read DURANDAL (fast ADC's = the hardware trigger in the experiment), process the information (effective mass calculation, etc.) resulting in accepting or rejecting the event. b) read out and analysis of the accepted data (collect statistical information). c) preprocess the data (calculation of pointers, address decoding, etc.). The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hardware and software will be tested with simulated data. First results are expected in about one year from now. (orig.)

Chronic whiplash and central sensitization; an evaluation of the role of a myofascial trigger points in pain modulation

Directory of Open Access Journals (Sweden)

Freeman Michael D

2009-04-01

Full Text Available Abstract Objective it has been established that chronic neck pain following whiplash is associated with the phenomenon of central sensitization, in which injured and uninjured parts of the body exhibit lowered pain thresholds due to an alteration in central pain processing. it has furthermore been hypothesized that peripheral sources of nociception in the muscles may perpetuate central sensitization in chronic whiplash. the hypothesis explored in the present study was whether myofascial trigger points serve as a modulator of central sensitization in subjects with chronic neck pain. Design controlled case series. Setting outpatient chronic pain clinic. Subjects seventeen patients with chronic and intractable neck pain and 10 healthy controls without complaints of neck pain. Intervention symptomatic subjects received anesthetic infiltration of myofascial trigger points in the upper trapezius muscles and controls received the anesthetic in the thigh. Outcome measures: pre and post injection cervical range of motion, pressure pain thresholds (ppt over the infraspinatus, wrist extensor, and tibialis anterior muscles. sensitivity to light (photophobia and subjects' perception of pain using a visual analog scale (vas were also evaluated before and after injections. only the ppt was evaluated in the asymptomatic controls. Results immediate (within 1 minute alterations in cervical range of motion and pressure pain thresholds were observed following an average of 3.8 injections with 1–2 cc of 1% lidocaine into carefully identified trigger points. cervical range of motion increased by an average of 49% (p = 0.000 in flexion and 44% (p = 0.001 in extension, 47% (p = 0.000 and 28% (p Conclusion the present data suggest that myofascial trigger points serve to perpetuate lowered pain thresholds in uninjured tissues. additionally, it appears that lowered pain thresholds associated with central sensitization can be immediately reversed, even when associated

LHCb base-line level-0 trigger 3D-Flow implementation

International Nuclear Information System (INIS)

Crosetto, Dario B.

1999-01-01

The LHCb Level-0 trigger implementation with the 3D-Flow system offers full programmability, allowing it to adapt to unexpected operating conditions and enabling new, unpredicted physics. The implementation is described in detail and refers to components and technology available today. The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on the replication of a single type of circuit of 100k gates, which communicates in six directions: bi-directional with North, East, West, and South neighbors, unidirectional from Top to Bottom, the system offers full programmability, modularity, ease of expansion and adaptation to the latest technology. A complete study of its applicability to the LHCb calorimeter triggers is presented. Full description of the input data handling, either in digital or mixed digital-analog form, of the data processing, and the transmission of results to the global level-0 trigger decision unit are provided. Any level-0 trigger algorithm (2x2, 3x3, 4x4, etc.) with up to 20 steps, can be implemented with zero dead-time, while sustaining input data rate (up to 32-bit per input channel, per bunch crossing) at 40 MHz. For each step, each 3D-Flow processor can execute up to 26 operations, inclusive of compare, ranging, finding local maxima, and efficient data exchange with neighboring channels. (One-to-one correspondence between input channel and trigger tower.) Populated with only two main types of components, front-end FPGAs and 3D-Flow processors, a single type of board, it is shown how the whole Level-0 calorimeter trigger can be accommodated into six crates (9U), each containing 16 identical boards. All 3D-Flow inter-chip Bottom to Top ports connection are all contained on the board (data are multiplexed 2 : 1, PCB traces are shorter than 6 cm); all 3D-flow inter-chip North, East, West, and South ports connections, between boards and crates, are multiplexed (8+2) : 1 and are

The CMS High-Level Trigger

International Nuclear Information System (INIS)

Covarelli, R.

2009-01-01

At the startup of the LHC, the CMS data acquisition is expected to be able to sustain an event readout rate of up to 100 kHz from the Level-1 trigger. These events will be read into a large processor farm which will run the 'High-Level Trigger'(HLT) selection algorithms and will output a rate of about 150 Hz for permanent data storage. In this report HLT performances are shown for selections based on muons, electrons, photons, jets, missing transverse energy, τ leptons and b quarks: expected efficiencies, background rates and CPU time consumption are reported as well as relaxation criteria foreseen for a LHC startup instantaneous luminosity.

The CMS High-Level Trigger

CERN Document Server

Covarelli, Roberto

2009-01-01

At the startup of the LHC, the CMS data acquisition is expected to be able to sustain an event readout rate of up to 100 kHz from the Level-1 trigger. These events will be read into a large processor farm which will run the "High-Level Trigger" (HLT) selection algorithms and will output a rate of about 150 Hz for permanent data storage. In this report HLT performances are shown for selections based on muons, electrons, photons, jets, missing transverse energy, tau leptons and b quarks: expected efficiencies, background rates and CPU time consumption are reported as well as relaxation criteria foreseen for a LHC startup instantaneous luminosity.

The CMS High-Level Trigger

Science.gov (United States)

Covarelli, R.

2009-12-01

At the startup of the LHC, the CMS data acquisition is expected to be able to sustain an event readout rate of up to 100 kHz from the Level-1 trigger. These events will be read into a large processor farm which will run the "High-Level Trigger" (HLT) selection algorithms and will output a rate of about 150 Hz for permanent data storage. In this report HLT performances are shown for selections based on muons, electrons, photons, jets, missing transverse energy, τ leptons and b quarks: expected efficiencies, background rates and CPU time consumption are reported as well as relaxation criteria foreseen for a LHC startup instantaneous luminosity.

Trigger Algorithms and Electronics for the ATLAS Muon NSW Upgrade

CERN Document Server

Guan, Liang; The ATLAS collaboration

2015-01-01

The ATLAS New Small Wheel (NSW), comprising MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), will upgrade the ATLAS muon system for a high background environment. Particularly, the NSW trigger will reduce the rate of fake triggers coming from background tracks in the endcap. We will present an overview of the FPGA-based trigger processor for NSW and trigger algorithms for sTGC and Micromegas detector sub systems. In additional, we will present development of NSW trigger electronics, in particular, the sTGC Trigger Data Serializer (TDS) ASIC, sTGC Pad Trigger board, the sTGC data packet router and L1 Data Driver Card. Finally, we will detail the challenges of meeting the low latency requirements of the trigger system and coping with the high background rates of the HL-LHC.

Parallel computation for distributed parameter system-from vector processors to Adena computer

Energy Technology Data Exchange (ETDEWEB)

Nogi, T

1983-04-01

Research on advanced parallel hardware and software architectures for very high-speed computation deserves and needs more support and attention to fulfil its promise. Novel architectures for parallel processing are being made ready. Architectures for parallel processing can be roughly divided into two groups. One is a vector processor in which a single central processing unit involves multiple vector-arithmetic registers. The other is a processor array in which slave processors are connected to a host processor to perform parallel computation. In this review, the concept and data structure of the Adena (alternating-direction edition nexus array) architecture, which is conformable to distributed-parameter simulation algorithms, are described. 5 references.

Performances of the ATLAS RPC Level-1 Muon trigger during the Run-II data taking

CERN Document Server

Alberghi, Gian Luigi; The ATLAS collaboration

2018-01-01

The Level-1 Muon Barrel Trigger is one of the main elements of the event selection of the ATLAS experiment at the Large Hadron Collider. Its input stage consists of an array of processors receiving the full granularity of data from Resistive Plate Chambers in the central area of the ATLAS detector ("Barrel"). The RPCs, placed in the barrel region of the ATLAS detector, are arranged in three concentric double layers and operate in a strong magnetic toroidal field. RPC detectors cover the pseudo-rapidity range |η|<1.05 for a total surface of more than 4000 m2 and about 3600 gas volumes. The Level-1 Muon Trigger in the barrel region allows to select muon candidates with respect to their transverse momentum and associates them with the correct bunch-crossing number. The trigger system is able to take a decision within a latency of about 2 μs. We illustrate the selections, strategy and validation for an unbiased determination of the efficiency and timing of the RPC and the L1 from data; and show the results w...

The BTeV trigger system

International Nuclear Information System (INIS)

Kaplan, D.M.

2000-01-01

BTeV is a dedicated beauty and charm experiment proposed for the Fermilab Tevatron. The broad physics program envisaged for BTeV requires a trigger that is efficient for a wide variety of heavy-quark decays, including those to all-hadronic final states. To achieve this, we plan to trigger on evidence of detached vertices at the very first trigger level, taking advantage of fast-readout pixel detectors to facilitate fast pattern recognition. Simulations show that 100-to-1 rejection of light-quark background events can be achieved at Level 1 using specialized trackfinding hardware, and that an additional factor of 10-100 in data reduction can be achieved using general purpose processor farms at Levels 2 and 3. This is adequate to allow data taking at luminosities in excess of 2x10 32 cm -2 s -1

The JET diagnostic fast central acquisition and trigger system (abstract)

Science.gov (United States)

Edwards, A. W.; Blackler, K.

1995-01-01

Most plasma physics diagnostics sample at a fixed frequency that is normally matched to available memory limits. This technique is not appropriate for long pulse machines such as JET where sampling frequencies of hundreds of kHz are required to diagnose very fast events. As a result of work using real-time event selection within the previous JET soft x-ray diagnostic, a single data acquisition and event triggering system for all suitable fast diagnostics, the fast central acquisition and trigger system (Fast CATS), has been developed for JET. The front-end analog-to-digital conversion (ADC) part samples all channels at 250 kHz, with a 100 kHz pass band and a stop band of 125 kHz. The back-end data collection system is based around Texas Instruments TMS320C40 microprocessors. Within this system, two levels of trigger algorithms are able to evaluate data. The first level typically analyzes data on a per diagnostic and individual channel basis. The second level looks at the data from one or more diagnostics in a window around the time of interest flagged by the first level system. Selection criteria defined by the diagnosticians are then imposed on the results from the second level to decide whether that data should be kept. The use of such a system involving intelligent real time trigger algorithms and fast data analysis will improve both the quantity and quality of JET diagnostic data, while providing valuable input to the design of data acquisition systems for very long pulse machines such as ITER. This paper will give an overview of the various elements of this new system. In addition, first results from this system following the restart of JET operation will be presented.

XOP, a fast versatile processor, as a building block for parallel processing in high energy physics experiments

International Nuclear Information System (INIS)

Baehler, P.; Bosco, N.; Lingjaerde, T.; Ljuslin, C.; Van Praag, A.; Werner, P.

1986-01-01

The XOP processor has been designed for trigger calculation and data compression in high energy physics experiments. Therefore, emphasis has been placed upon fast execution and high input/output rate. The fast execution is achieved by a wide instruction word holding operations which are executed concurrently. Thus, the arithmetic operations, data address calculations, data accessing, condition checking, loop count checking and next instruction evaluation all overlap in time. In conventional micro-processors these operations are performed sequentially. In addition, the instruction set comprises not only the classical computer instructions, but also specialized instructions suitable for trigger calculations, such as bit search, population count, loose compare and vector instructions. In order to achieve a high input/output rate, each XOP ECLine interface board is equipped with an input and an output port which fulfil the LeCroy ECLine specifications. The autonomous input port allows a data rate of 40 Mbytes/sec, while the program controlled output port allows 20 Mbytes/sec. For Fastbus based systems a dual Fastbus master interface is under design which allows to build up a Fastbus multi-processor system. This design is being done in collaboration with LAPP Annecy for the CERN Lep L3 experiment. Their scheme comprises 4-5 XOP processors, each of them with a master interface on a data input segment and a master interface on a data output segment. This paper describes the structure of the XOP processor, the interface capabilities and the software development and debugging tools. (Auth.)

Design and Test Space Exploration of Transport-Triggered Architectures

NARCIS (Netherlands)

Zivkovic, V.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.

2000-01-01

This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The

Upgrade of the CMS Global Muon Trigger

CERN Document Server

Lingemann, Joschka; Sakulin, Hannes; Jeitler, Manfred; Stahl, Achim

2015-01-01

The increase in center-of-mass energy and luminosity for Run 2 of the Large Hadron Collider pose new challenges for the trigger systems of the experiments. To keep triggering with a similar performance as in Run 1, the CMS muon trigger is currently being upgraded. The new algorithms will provide higher resolution, especially for the muon transverse momentum and will make use of isolation criteria that combine calorimeter with muon information already in the level-1 trigger. The demands of the new algorithms can only be met by upgrading the level-1 trigger system to new powerful FPGAs with high bandwidth I/O. The processing boards will be based on the new microTCA standard. We report on the planned algorithms for the upgraded Global Muon Trigger (GMT) which combines information from the muon trigger sub-systems and assigns the isolation variable. The upgraded GMT will be implemented using a Master Processor 7 card, built by Imperial College, that features a large Xilinx Virtex 7 FPGA. Up to 72 optical links at...

ATLAS calorimetry. Trigger, simulation and jet calibration

Energy Technology Data Exchange (ETDEWEB)

Weber, P

2007-02-06

The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle {phi} and in pseudorapidity {eta}. The performance of the calibration methods including possible systematic and statistical effects is described. (orig.)

Use of GPUs in Trigger Systems

Science.gov (United States)

Lamanna, Gianluca

In recent years the interest for using graphics processor (GPU) in general purpose high performance computing is constantly rising. In this paper we discuss the possible use of GPUs to construct a fast and effective real time trigger system, both in software and hardware levels. In particular, we study the integration of such a system in the NA62 trigger. The first application of GPUs for rings pattern recognition in the RICH will be presented. The results obtained show that there are not showstoppers in trigger systems with relatively low latency. Thanks to the use of off-the-shelf technology, in continous development for purposes related to video game and image processing market, the architecture described would be easily exported to other experiments, to build a versatile and fully customizable online selection.

The second level trigger of the L3 experiment. Pt. 2

International Nuclear Information System (INIS)

Beingessner, S.P.; Blaising, J.J.; Chollet-Le Flour, F.; Degre, A.; Dromby, G.; Goy, C.; Lecoq, J.; Morand, R.; Moynot, M.; Perrot, G.; Rosier-Lees, S.; Forconi, G.

1993-07-01

The events recorded by the L3 Data Acquisition System are selected by three levels of trigger. The event filtering performed by software at the second trigger level is described. First coded offline in FORTRAN, the filtering software is microcoded for online execution in a farm of 3 XOP processors operating in a round robin mode. It identifies and rejects background events. Depending on running conditions and trigger type, rejection factors ranging from 45% to 80% are obtained on first level energy, muon and tec triggers. Selection efficiencies greater than 99.95% are achieved. (authors). 14 refs., 3 figs., 2 tabs

Supervision of the ATLAS High Level Trigger System

CERN Document Server

Wheeler, S.; Meessen, C.; Qian, Z.; Touchard, F.; Negri, France A.; Zobernig, H.; CHEP 2003 Computing in High Energy Physics; Negri, France A.

2003-01-01

The ATLAS High Level Trigger (HLT) system provides software-based event selection after the initial LVL1 hardware trigger. It is composed of two stages, the LVL2 trigger and the Event Filter. The HLT is implemented as software tasks running on large processor farms. An essential part of the HLT is the supervision system, which is responsible for configuring, coordinating, controlling and monitoring the many hundreds of processes running in the HLT. A prototype implementation of the supervision system, using tools from the ATLAS Online Software system is presented. Results from scalability tests are also presented where the supervision system was shown to be capable of controlling over 1000 HLT processes running on 230 nodes.

TRIGGER

CERN Multimedia

Wesley Smith

Trigger Hardware The status of the trigger components was presented during the September CMS Week and Annual Review and at the monthly trigger meetings in October and November. Procedures for cold and warm starts (e.g. refreshing of trigger parameters stored in registers) of the trigger subsystems have been studied. Reviews of parts of the Global Calorimeter Trigger (GCT) and the Global Trigger (GT) have taken place in October and November. The CERN group summarized the status of the Trigger Timing and Control (TTC) system. All TTC crates and boards are installed in the underground counting room, USC55. The central clock system will be upgraded in December (after the Global Run at the end of November GREN) to the new RF2TTC LHC machine interface timing module. Migration of subsystem's TTC PCs to SLC4/ XDAQ 3.12 is being prepared. Work is on going to unify the access to Local Timing Control (LTC) and TTC CMS interface module (TTCci) via SOAP (Simple Object Access Protocol, a lightweight XML-based messaging ...

Contribution to the elaboration and implementation of LEP-L3 second level microcoded Trigger

International Nuclear Information System (INIS)

Chollet, F.

1988-03-01

This thesis is devoted to the elaboration of the L3 second level trigger which is based on the dedicated programmable XOP processor. This system will reduce the trigger rate by a factor of ten and will ensure that the hardwired level-one processors function correctly. The present document describes all developments that L.A.P.P. is engaged in from the system design up to the complete experimental set up, especially: - The hardware development of the fast input memories as well as the FASTBUS interface unit which allows the microprocessor XOP to run as a performant FASTBUS Master, - the associated software developments, - the implementation of a VME test system dedicated to all control tasks [fr

Using of opportunities of graphic processors for acceleration of scientific and technical calculations

International Nuclear Information System (INIS)

Dudnik, V.A.; Kudryavtsev, V.I.; Sereda, T.M.; Us, S.A.; Shestakov, M.V.

2009-01-01

The new opportunities of modern graphic processors (GPU) for acceleration of the scientific and technical calculations with the help of paralleling of a calculating task between the central processor and GPU are described. The description of using the technology NVIDIA CUDA for connection of parallel computing opportunities of GPU within the programme of the some intensive mathematical tasks is resulted. The examples of comparison of parameters of productivity in the process of these tasks' calculation without application of GPU and with use of opportunities NVIDIA CUDA for graphic processor GeForce 8800 are resulted

TRIGGER

CERN Multimedia

W. Smith

At the March meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, the program of trigger pattern tests and vertical slice tests and planning for the Global Runs starting this summer. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and integration testing is in full swing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. After full checkout, trigger subsystems will be then operated in the CMS Global Runs. Continuous...

Centralized digital control of accelerators

International Nuclear Information System (INIS)

Melen, R.E.

1984-01-01

Upon careful examination of the architecture of SLAC's computer control systems, it becomes evident that the distribution of the systems' intelligence generally falls into tree-like layers. The first layer typically consists of a central computer complex incorporating one or more relatively large and powerful processors. The more modern systems use state-of-the-art 32-bit processors with several megabytes of RAM and several hundreds of megabytes of disk memory. Further, they support extensive user-friendly operating systems and program development facilities. The second layer typically consists of several smaller processors which are downloaded from the central complex and whose primary task is to provide data acquisition and distribution. The more modern systems are 16-bit processors with several hundred kilobytes of RAM and no disk memory. The third layer typically consists of several tens or hundreds of micro-processors, each dedicated to a single device. The micro-processors for these ''dedicated intelligent controllers'' are small and inexpensive and typically require less than 32 kilobytes of RAM or EPROM memory. Their hardware may be general purpose in nature or may be built into the architecture of the device itself. Figure 5 illustrates several of the relevant features of each of these layers. This paper serves to illustrate that SLAC is commited to the centralized digital control of its accelerators

Boosted object hardware trigger development and testing for the Phase I upgrade of the ATLAS Experiment

CERN Document Server

Stark, Giordon Holtsberg; The ATLAS collaboration

2015-01-01

The Global Feature Extraction (gFEX) module is a Level 1 jet trigger system planned for installation in ATLAS during the Phase 1 upgrade in 2018. The gFEX selects large-radius jets for capturing Lorentz-boosted objects by means of wide-area jet algorithms refined by subjet information. The architecture of the gFEX permits event-by-event local pile-up suppression for these jets using the same subtraction techniques developed for offline analyses. The gFEX architecture is also suitable for other global event algorithms such as missing transverse energy (MET), centrality for heavy ion collisions, and "jets without jets". The gFEX will use 4 processor FPGAs to perform calculations on the incoming data and a Hybrid APU-FPGA for slow control of the module. The gFEX is unique in both design and implementation and substantially enhance the selectivity of the L1 trigger and increases sensitivity to key physics channels.

Implementation of a level 1 trigger system using high speed serial (VXS) techniques for the 12GeV high luminosity experimental programs at Thomas Jefferson National Accelerator Facility

International Nuclear Information System (INIS)

Cuevas, C.; Raydo, B.; Dong, H.; Gupta, A.; Barbosa, F.J.; Wilson, J.; Taylor, W.M.; Jastrzembski, E.; Abbott, D.

2009-01-01

We will demonstrate a hardware and firmware solution for a complete fully pipelined multi-crate trigger system that takes advantage of the elegant high speed VXS serial extensions for VME. This trigger system includes three sections starting with the front end crate trigger processor (CTP), a global Sub-System Processor (SSP) and a Trigger Supervisor that manages the timing, synchronization and front end event readout. Within a front end crate, trigger information is gathered from each 16 Channel, 12 bit Flash ADC module at 4 nS intervals via the VXS backplane, to a Crate Trigger Processor (CTP). Each Crate Trigger Processor receives these 500 MB/S VXS links from the 16 FADC-250 modules, aligns skewed data inherent of Aurora protocol, and performs real time crate level trigger algorithms. The algorithm results are encoded using a Reed-Solomon technique and transmission of this Level 1 trigger data is sent to the SSP using a multi-fiber link. The multi-fiber link achieves an aggregate trigger data transfer rate to the global trigger at 8 Gb/s. The SSP receives and decodes Reed-Solomon error correcting transmission from each crate, aligns the data, and performs the global level trigger algorithms. The entire trigger system is synchronous and operates at 250 MHz with the Trigger Supervisor managing not only the front end event readout, but also the distribution of the critical timing clocks, synchronization signals, and the global trigger signals to each front end readout crate. These signals are distributed to the front end crates on a separate fiber link and each crate is synchronized using a unique encoding scheme to guarantee that each front end crate is synchronous with a fixed latency, independent of the distance between each crate. The overall trigger signal latency is <3 uS, and the proposed 12GeV experiments at Jefferson Lab require up to 200KHz Level 1 trigger rate.

Development of a processor embedded timing unit for the synchronized operation in KSTAR

Energy Technology Data Exchange (ETDEWEB)

Lee, Woongryol, E-mail: wrlee@nfri.re.kr; Lee, Taegu; Hong, Jaesic

2016-11-15

Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

Development of a processor embedded timing unit for the synchronized operation in KSTAR

International Nuclear Information System (INIS)

Lee, Woongryol; Lee, Taegu; Hong, Jaesic

2016-01-01

Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

FPGA Co-processor for the ALICE High Level Trigger

CERN Document Server

Grastveit, G.; Lindenstruth, V.; Loizides, C.; Roehrich, D.; Skaali, B.; Steinbeck, T.; Stock, R.; Tilsner, H.; Ullaland, K.; Vestbo, A.; Vik, T.

2003-01-01

The High Level Trigger (HLT) of the ALICE experiment requires massive parallel computing. One of the main tasks of the HLT system is two-dimensional cluster finding on raw data of the Time Projection Chamber (TPC), which is the main data source of ALICE. To reduce the number of computing nodes needed in the HLT farm, FPGAs, which are an intrinsic part of the system, will be utilized for this task. VHDL code implementing the Fast Cluster Finder algorithm, has been written, a testbed for functional verification of the code has been developed, and the code has been synthesized

Some questions of using the algebraic coding theory for construction of special-purpose processors in high energy physics spectrometers

International Nuclear Information System (INIS)

Nikityuk, N.M.

1989-01-01

The results of investigations of using the algebraic coding theory for the creation of parallel encoders, majority coincidence schemes and coordinate processors for the first and second trigger levels are described. Concrete examples of calculation and structure of special-purpose processor using the table arithmetic method are given for multiplicity t ≤ 5. The question of using parallel and sequential syndrome coding methods for the registration of events with clusters is discussed. 30 refs.; 10 figs

The ATLAS Level-1 Topological Trigger performance in Run 2

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00120419; The ATLAS collaboration

2017-01-01

The Level-1 trigger is the first event rate reducing step in the ATLAS detector trigger system, with an output rate of up to 100 kHz and decision latency smaller than 2.5 μs. During the LHC shutdown after Run 1, the Level-1 trigger system was upgraded at hardware, firmware and software levels. In particular, a new electronics sub-system was introduced in the real-time data processing path: the Level-1 Topological trigger system. It consists of a single electronics shelf equipped with two Level-1 Topological processor blades. They receive real-time information from the Level-1 calorimeter and muon triggers, which is processed to measure angles between trigger objects, invariant masses or other kinematic variables. Complementary to other requirements, these measurements are taken into account in the final Level-1 trigger decision. The system was installed and commissioning started in 2015 and continued during 2016. As part of the commissioning, the decisions from individual algorithms were simulated and compar...

Array processor architecture

Science.gov (United States)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

Directory of Open Access Journals (Sweden)

R. Maheswari

2012-04-01

Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

Science.gov (United States)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Probabilistic programmable quantum processors

International Nuclear Information System (INIS)

Buzek, V.; Ziman, M.; Hillery, M.

2004-01-01

We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

OpenAIRE

Abdul Kareem PARCHUR; Ram Asaray SINGH

2012-01-01

High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

Using the automata processor for fast pattern recognition in high energy physics experiments—A proof of concept

Energy Technology Data Exchange (ETDEWEB)

Wang, Michael H.L.S., E-mail: mwang@fnal.gov [Fermi National Accelerator Laboratory, Batavia, IL 60510 (United States); Cancelo, Gustavo; Green, Christopher [Fermi National Accelerator Laboratory, Batavia, IL 60510 (United States); Guo, Deyuan; Wang, Ke [University of Virginia, Charlottesville, VA 22904 (United States); Zmuda, Ted [Fermi National Accelerator Laboratory, Batavia, IL 60510 (United States)

2016-10-01

We explore the Micron Automata Processor (AP) as a suitable commodity technology that can address the growing computational needs of pattern recognition in High Energy Physics (HEP) experiments. A toy detector model is developed for which an electron track confirmation trigger based on the Micron AP serves as a test case. Although primarily meant for high speed text-based searches, we demonstrate a proof of concept for the use of the Micron AP in a HEP trigger application.

The LASS hardware processor

International Nuclear Information System (INIS)

Kunz, P.F.

1976-01-01

The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

Trigger algorithms and electronics for the ATLAS muon new small wheel upgrade

International Nuclear Information System (INIS)

Guan, L.

2016-01-01

The New Small Wheel Upgrade for the ATLAS experiment will replace the innermost station of the Muon Spectrometer in the forward region in order to maintain its current performance during high luminosity data-taking after the LHC Phase-I upgrade. The New Small Wheel, comprising Micromegas and small Thin Gap Chambers, will reduce the rate of fake triggers coming from backgrounds in the forward region and significantly improve the Level-1 muon trigger selectivity by providing precise on-line segment measurements with ∼ 1 mrad angular resolution. Such demanding precision, together with the short time (∼ 1 μs) to prepare trigger data and perform on-line reconstruction, implies very stringent requirements on the design of trigger system and trigger electronics. This paper presents an overview of the design of the New Small Wheel trigger system, trigger algorithms and processor hardware

Commissioning and Validation of the ATLAS Level-1 Topological Trigger in Run 2

CERN Document Server

Zheng, Daniel; The ATLAS collaboration

2017-01-01

The ATLAS experiment has introduced and recently commissioned a completely new hardware sub-system of its first-level trigger: the topological processor (L1Topo). L1Topo consist of two AdvancedTCA blades mounting state-of-the-art FPGA processors, providing high input bandwidth (up to 4 Gb/s) and low latency data processing (200 ns). L1Topo is able to select collision events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Results from data recorded using the L1Topo trigger will be presented. These results demonstrate a significantly improved background event rejection, thus allowing for rate reduction with minimal efficiency loss. This improvement has been shown for several physics processes leading to low-$p_T$ leptons, including $H\\rightarrow\\tau \\tau$ and $J/\\psi \\rightarrow \\mu \\mu$. In addition to describing the L1Topo trigger system, we will discuss the use of an accurate L1Topo simulation as a pow...

The design and performance of the ATLAS Inner Detector trigger for Run 2

CERN Document Server

Penc, Ondrej; The ATLAS collaboration

2016-01-01

The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm with the early LHC Run 2 data are discussed. The redesign of the ID trigger, which took place during the 2013-15 long shutdown, in order to satisfy the demands of the higher energy LHC Run 2 operation is described. The ID trigger HLT algorithms are essential for nearly all trigger signatures within the ATLAS trigger. The detailed performance of the tracking algorithms with the early Run 2 data for the different trigger signatures is presented, including the detailed timing performance for the algorithms running on the redesigned single stage ATLAS HLT Farm. Comparison with the Run 1 strategy are made and demonstrate the superior performance of the strategy adopted for Run 2.

A compact pre-processor system for the ATLAS level-1 calorimeter trigger

CERN Document Server

Pfeiffer, U

1999-01-01

This thesis describ es the researc h whose aim is to dev elop a compact Pre-Pro cessor system for the A TLAS Lev el-1 Calorimeter T rigger. Con tributions to the p erformance and the arc hitecture of the Pre-Pro cessor w ere made. A demonstrator Multi-Chip Mo dule (PPrD- MCM) w as dev elop ed and assem bled whic h p erforms most of the prepro cessing of four analogue trigger-to w er signals. The prepro cessing includes digitisation to 8-bit precision, iden ti cation of the corresp onding bunc h-crossing in time (BCID), calibration of the transv erse energy , readout of ra w trigger data, and high-sp eed serial data transmission to the trigger pro cessors. The demonstrator Multi-Chip Mo dule has a size of 15.9 cm 2 and it consists of 9 dies. The MCM w as designed with a smallest feature size of 100 m and it w as fabricated in a laminated MCM-L pro cess o ered b yW urth Elektronik. A Flip-Chip in terconnection ASIC (Finco) w as dev elop ed for the PPrD-MCM and fabricated in a 0.8 m BiCMOS- pro cess o ered b ...

Simulation and Validation of the ATLAS Level-1 Topological Trigger

CERN Document Server

Bakker, Pepijn Johannes; The ATLAS collaboration

2017-01-01

The ATLAS experiment has recently commissioned a new component of its first-level trigger: the L1 topological trigger. This system, using state-of-the-art FPGA processors, makes it possible to reject events by applying topological requirements, such as kinematic criteria involving clusters, jets, muons, and total transverse energy. The data recorded using the L1Topological trigger demonstrates that this innovative trigger strategy allows for an improved rejection rate without efficiency loss. This improvement has been shown for several relevant physics processes leading to low-$p_T$ leptons, including $H\\to{}\\tau{}\\tau{}$ and $J/\\Psi\\to{}\\mu{}\\mu{}$. In addition, an accurate simulation of the L1Topological trigger is used to validate and optimize the performance of this trigger. To reach such an accuracy, this simulation must take into account the fact that the firmware algorithms are executed on a FPGA architecture, while the simulation is executed on a floating point architecture.

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

Science.gov (United States)

Lindgren, R. W.; Tarbell, T. D.

1981-01-01

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

Directory of Open Access Journals (Sweden)

Abdul Kareem PARCHUR

2012-08-01

Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

Simulation of a parallel processor on a serial processor: The neutron diffusion equation

International Nuclear Information System (INIS)

Honeck, H.C.

1981-01-01

Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

Continuously live image processor for drift chamber track segment triggering

International Nuclear Information System (INIS)

Berenyi, A.; Chen, H.K.; Dao, K.

1999-01-01

The first portion of the BaBar experiment Level 1 Drift Chamber Trigger pipeline is the Track Segment Finder (TSF). Using a novel method incorporating both occupancy and drift-time information, the TSF system continually searches for segments in the supercells of the full 7104-wire Drift Chamber hit image at 3.7 MHz. The TSF was constructed to operate in a potentially high beam-background environment while achieving high segment-finding efficiency, deadtime-free operation, a spatial resolution of 5 simulated physics events

The selective read-out processor for the CMS electromagnetic calorimeter

CERN Document Server

Girão de Almeida, Nuño Miguel; Faure, Jean Louis; Gachelin, Olivier; Gras, Philippe; Mandjavidze, Irakli; Mur, Michel; Varela, João

2005-01-01

This paper describes the selective read-out processor (SRP) proposed for the electromagnetic calorimeter (ECAL) of the Compact Muon Solenoid (CMS) experiment at LHC (CERN). The aim is to reduce raw ECAL data to a level acceptable by the CMS data acquisition (DAQ) system. For each positive level 1 trigger, the SRP is guided by trigger primitive generation electronics to identify ECAL regions with energy deposition satisfying certain programmable criteria. It then directs the ECAL read-out electronics to apply predefined zero suppression levels to the crystal data, depending whether the crystals fall within these regions or not. The main challenges for the SRP are some 200 high speed (1.6 Gbit/s) I/O channels, asynchronous operation at up to 100 kHz level 1 trigger rate, a 5- mu s real-time latency requirement and a need to retain flexibility in choice of selection algorithms. The architecture adopted for the SRP is based on modern parallel optic pluggable modules and high density field programmable gate array ...

Functional unit for a processor

NARCIS (Netherlands)

Rohani, A.; Kerkhoff, Hans G.

2013-01-01

The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

Architecture of a Level 1 Track Trigger for the CMS Experiment

CERN Document Server

Heintz, Ulrich

2010-01-01

The luminosity goal for the Super-LHC is 1035/cm2/s. At this luminosity the number of proton-proton interactions in each beam crossing will be in the hundreds. This will stress many components of the CMS detector. One system that has to be upgraded is the trigger system. To keep the rate at which the level 1 trigger fires manageable, information from the tracker has to be integrated into the level 1 trigger. Current design proposals foresee tracking detectors that perform on-detector filtering to reject hits from low-momentum particles. In order to build a trigger system, the filtered hit data from different layers and sectors of the tracker will have to be transmitted off the detector and brought together in a logic processor that generates trigger tracks within the time window allowed by the level 1 trigger latency. I will describe a possible architecture for the off-detector logic that accomplishes this goal.

Multi-threaded algorithms for GPGPU in the ATLAS High Level Trigger

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00212700; The ATLAS collaboration

2017-01-01

General purpose Graphics Processor Units (GPGPU) are being evaluated for possible future inclusion in an upgraded ATLAS High Level Trigger farm. We have developed a demonstrator including GPGPU implementations of Inner Detector and Muon tracking and Calorimeter clustering within the ATLAS software framework. ATLAS is a general purpose particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system consists of two levels, with Level-1 implemented in hardware and the High Level Trigger implemented in software running on a farm of commodity CPU. The High Level Trigger reduces the trigger rate from the 100 kHz Level-1 acceptance rate to 1.5 kHz for recording, requiring an average per-event processing time of ∼ 250 ms for this task. The selection in the high level trigger is based on reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Calorimeter. Performing this reconstruction within the available farm resources presents a significa...

TRIGGER

CERN Multimedia

W. Smith

At the December meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, and results from the Magnet Test and Cosmic Challenge (MTCC) phase II. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and moving towards integration testing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. This is combined with operations and testing without beam that will continue until startup. The plans for start-up, pilot and early running tri...

Adaptive signal processor

Energy Technology Data Exchange (ETDEWEB)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

Adaptive signal processor

International Nuclear Information System (INIS)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

Multithreading in vector processors

Science.gov (United States)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

2018-01-16

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00010976; Albicocco, P.; Alison, J.; Ancu, L.S.; Anderson, J.; Andari, N.; Andreani, A.; Andreazza, A.; Annovi, A.; Antonelli, M.; Asbah, N.; Atkinson, M.; Baines, J.; Barberio, E.; Beccherle, R.; Beretta, M.; Bertolucci, F.; Biesuz, N.V.; Blair, R.; Bogdan, M.; Boveia, A.; Britzger, D.; Bryant, P.; Burghgrave, B.; Calderini, G.; Camplani, A.; Cavasinni, V.; Chakraborty, D.; Chang, P.; Cheng, Y.; Citraro, S.; Citterio, M.; Crescioli, F.; Dawe, N.; Dell'Orso, M.; Donati, S.; Dondero, P.; Drake, G.; Gadomski, S.; Gatta, M.; Gentsos, C.; Giannetti, P.; Gkaitatzis, S.; Gramling, J.; Howarth, J.W.; Iizawa, T.; Ilic, N.; Jiang, Z.; Kaji, T.; Kasten, M.; Kawaguchi, Y.; Kim, Y.K.; Kimura, N.; Klimkovich, T.; Kolb, M.; Kordas, K.; Krizka, K.; Kubota, T.; Lanza, A.; Li, H.L.; Liberali, V.; Lisovyi, M.; Liu, L.; Love, J.; Luciano, P.; Luongo, C.; Magalotti, D.; Maznas, I.; Meroni, C.; Mitani, T.; Nasimi, H.; Negri, A.; Neroutsos, P.; Neubauer, M.; Nikolaidis, S.; Okumura, Y.; Pandini, C.; Petridou, C.; Piendibene, M.; Proudfoot, J.; Rados, P.; Roda, C.; Rossi, E.; Sakurai, Y.; Sampsonidis, D.; Saxon, J.; Schmitt, S.; Schoening, A.; Shochet, M.; Shojaii, S.; Soltveit, H.; Sotiropoulou, C.L.; Stabile, A.; Swiatlowski, M.; Tang, F.; Taylor, P.T.; Testa, M.; Tompkins, L.; Vercesi, V.; Volpi, G.; Wang, R.; Watari, R.; Webster, J.; Wu, X.; Yorita, K.; Yurkewicz, A.; Zeng, J.C.; Zhang, J.; Zou, R.

2016-01-01

The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger an data acquisition (TDAQ) system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100$\\mu$s, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

The ATLAS online High Level Trigger framework: Experience reusing offline software components in the ATLAS trigger

International Nuclear Information System (INIS)

Wiedenmann, Werner

2010-01-01

Event selection in the ATLAS High Level Trigger is accomplished to a large extent by reusing software components and event selection algorithms developed and tested in an offline environment. Many of these offline software modules are not specifically designed to run in a heavily multi-threaded online data flow environment. The ATLAS High Level Trigger (HLT) framework based on the GAUDI and ATLAS ATHENA frameworks, forms the interface layer, which allows the execution of the HLT selection and monitoring code within the online run control and data flow software. While such an approach provides a unified environment for trigger event selection across all of ATLAS, it also poses strict requirements on the reused software components in terms of performance, memory usage and stability. Experience of running the HLT selection software in the different environments and especially on large multi-node trigger farms has been gained in several commissioning periods using preloaded Monte Carlo events, in data taking periods with cosmic events and in a short period with proton beams from LHC. The contribution discusses the architectural aspects of the HLT framework, its performance and its software environment within the ATLAS computing, trigger and data flow projects. Emphasis is also put on the architectural implications for the software by the use of multi-core processors in the computing farms and the experiences gained with multi-threading and multi-process technologies.

Modular formal analysis of the central guardian in the Time-Triggered Architecture

International Nuclear Information System (INIS)

Pfeifer, Holger; Henke, Friedrich W. von

2007-01-01

The Time-Triggered Protocol TTP/C constitutes the core of the communication level of the Time-Triggered Architecture for dependable real-time systems. TTP/C ensures consistent data distribution, even in the presence of faults occurring to nodes or the communication channel. However, the protocol mechanisms of TTP/C rely on a rather optimistic fault hypothesis. Therefore, an independent component, the central guardian, employs static knowledge about the system to transform arbitrary node failures into failure modes that are covered by the fault hypothesis. This paper presents a modular formal analysis of the communication properties of TTP/C based on the guardian approach. Through a hierarchy of formal models, we give a precise description of the arguments that support the desired correctness properties of TTP/C. First, requirements for correct communication are expressed on an abstract level. By stepwise refinement we show both that these abstract requirements are met under the optimistic fault hypothesis, and how the guardian model allows a broader class of node failures to be tolerated. The models have been developed and mechanically checked using the specification and verification system PVS

Dual-core Itanium Processor

CERN Multimedia

2006-01-01

Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

Performance Study of Earth Networks Total Lightning Network using Rocket-Triggered Lightning Data in 2014

Science.gov (United States)

Heckman, S.

2015-12-01

Modern lightning locating systems (LLS) provide real-time monitoring and early warning of lightningactivities. In addition, LLS provide valuable data for statistical analysis in lightning research. It isimportant to know the performance of such LLS. In the present study, the performance of the EarthNetworks Total Lightning Network (ENTLN) is studied using rocket-triggered lightning data acquired atthe International Center for Lightning Research and Testing (ICLRT), Camp Blanding, Florida.In the present study, 18 flashes triggered at ICLRT in 2014 were analyzed and they comprise of 78negative cloud-to-ground return strokes. The geometric mean, median, minimum, and maximum for thepeak currents of the 78 return strokes are 13.4 kA, 13.6 kA, 3.7 kA, and 38.4 kA, respectively. The peakcurrents represent typical subsequent return strokes in natural cloud-to-ground lightning.Earth Networks has developed a new data processor to improve the performance of their network. Inthis study, results are presented for the ENTLN data using the old processor (originally reported in 2014)and the ENTLN data simulated using the new processor. The flash detection efficiency, stroke detectionefficiency, percentage of misclassification, median location error, median peak current estimation error,and median absolute peak current estimation error for the originally reported data from old processorare 100%, 94%, 49%, 271 m, 5%, and 13%, respectively, and those for the simulated data using the newprocessor are 100%, 99%, 9%, 280 m, 11%, and 15%, respectively. The use of new processor resulted inhigher stroke detection efficiency and lower percentage of misclassification. It is worth noting that theslight differences in median location error, median peak current estimation error, and median absolutepeak current estimation error for the two processors are due to the fact that the new processordetected more number of return strokes than the old processor.

3081/E processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.

1984-04-01

The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

Integrated fuel processor development

International Nuclear Information System (INIS)

Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

2001-01-01

The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

CERN Document Server

Becam, C; Delanghe, J; Fest, H M; Lecoq, J; Martin, H; Mencik, M; MerkeI, B; Meyer, J M; Perrin, M; Plothow, H; Rampazzo, J P; Schittly, A

1981-01-01

The bit slice micro-processor GESPRO is a CAMAC module plugged into a standard Elliot system crate via which it communicates as a slave with its host computer. It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine with multi-mode memory addressing capacity of 64K words. The micro-processor structure uses 5 buses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2K (RAM) words of 48 bits each. A special hardwired module allows floating point, as well as integer, multiplication of 24*24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: (a) online data reduction, i.e. to read DURANDAL, process the information resulting in accepting or rejecting the event; (b) readout and analysis of the accepted data; (c) preprocess the data. The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hard...

Scalable architecture for a room temperature solid-state quantum information processor.

Science.gov (United States)

Yao, N Y; Jiang, L; Gorshkov, A V; Maurer, P C; Giedke, G; Cirac, J I; Lukin, M D

2012-04-24

The realization of a scalable quantum information processor has emerged over the past decade as one of the central challenges at the interface of fundamental science and engineering. Here we propose and analyse an architecture for a scalable, solid-state quantum information processor capable of operating at room temperature. Our approach is based on recent experimental advances involving nitrogen-vacancy colour centres in diamond. In particular, we demonstrate that the multiple challenges associated with operation at ambient temperature, individual addressing at the nanoscale, strong qubit coupling, robustness against disorder and low decoherence rates can be simultaneously achieved under realistic, experimentally relevant conditions. The architecture uses a novel approach to quantum information transfer and includes a hierarchy of control at successive length scales. Moreover, it alleviates the stringent constraints currently limiting the realization of scalable quantum processors and will provide fundamental insights into the physics of non-equilibrium many-body quantum systems.

NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

International Nuclear Information System (INIS)

Ammendola, Roberto; Biagioni, Andrea; Frezza, Ottorino; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Rossetti, Davide; Simula, Francesco; Tosoratto, Laura; Vicini, Piero; Fantechi, Riccardo; Lamanna, Gianluca; Pantaleo, Felice; Piandani, Roberto; Sozzi, Marco; Pontisso, Luca

2014-01-01

We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

Energy Technology Data Exchange (ETDEWEB)

Ammendola, Roberto [INFN, Rome – Tor Vergata (Italy); Biagioni, Andrea; Frezza, Ottorino; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Rossetti, Davide; Simula, Francesco; Tosoratto, Laura; Vicini, Piero [INFN, Rome – Sapienza (Italy); Fantechi, Riccardo [CERN, Geneve (Switzerland); Lamanna, Gianluca; Pantaleo, Felice; Piandani, Roberto; Sozzi, Marco [INFN, Pisa (Italy); Pontisso, Luca [University, Rome (Italy)

2014-06-11

We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems

CERN Document Server

INSPIRE-00646837; Biagioni, Andrea; Fantechi, Riccardo; Frezza, Ottorino; Lamanna, Gianluca; Lo Cicero, Francesca; Lonardo, Alessandro; Paolucci, Pier Stanislao; Pantaleo, Felice; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Tosoratto, Laura; Vicini, Piero

2014-01-01

We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

Multi-Threaded Algorithms for GPGPU in the ATLAS High Level Trigger

Science.gov (United States)

Conde Muíño, P.; ATLAS Collaboration

2017-10-01

General purpose Graphics Processor Units (GPGPU) are being evaluated for possible future inclusion in an upgraded ATLAS High Level Trigger farm. We have developed a demonstrator including GPGPU implementations of Inner Detector and Muon tracking and Calorimeter clustering within the ATLAS software framework. ATLAS is a general purpose particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system consists of two levels, with Level-1 implemented in hardware and the High Level Trigger implemented in software running on a farm of commodity CPU. The High Level Trigger reduces the trigger rate from the 100 kHz Level-1 acceptance rate to 1.5 kHz for recording, requiring an average per-event processing time of ∼ 250 ms for this task. The selection in the high level trigger is based on reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Calorimeter. Performing this reconstruction within the available farm resources presents a significant challenge that will increase significantly with future LHC upgrades. During the LHC data taking period starting in 2021, luminosity will reach up to three times the original design value. Luminosity will increase further to 7.5 times the design value in 2026 following LHC and ATLAS upgrades. Corresponding improvements in the speed of the reconstruction code will be needed to provide the required trigger selection power within affordable computing resources. Key factors determining the potential benefit of including GPGPU as part of the HLT processor farm are: the relative speed of the CPU and GPGPU algorithm implementations; the relative execution times of the GPGPU algorithms and serial code remaining on the CPU; the number of GPGPU required, and the relative financial cost of the selected GPGPU. We give a brief overview of the algorithms implemented and present new measurements that compare the performance of various configurations exploiting GPGPU cards.

Centralized digital control of accelerators

International Nuclear Information System (INIS)

Melen, R.E.

1983-09-01

In contrasting the title of this paper with a second paper to be presented at this conference entitled Distributed Digital Control of Accelerators, a potential reader might be led to believe that this paper will focus on systems whose computing intelligence is centered in one or more computers in a centralized location. Instead, this paper will describe the architectural evolution of SLAC's computer based accelerator control systems with respect to the distribution of their intelligence. However, the use of the word centralized in the title is appropriate because these systems are based on the use of centralized large and computationally powerful processors that are typically supported by networks of smaller distributed processors

An Overview of the ATLAS High Level Trigger Dataflow and Supervision

CERN Document Server

Wheeler, S; Baines, J T M; Bee, C P; Biglietti, M; Bogaerts, A; Boisvert, V; Bosman, M; Brandt, S; Caron, B; Casado, M P; Cataldi, G; Cavalli, D; Cervetto, M; Comune, G; Corso-Radu, A; Di Mattia, A; Díaz-Gómez, M; Dos Anjos, A; Drohan, J; Ellis, Nick; Elsing, M; Epp, B; Etienne, F; Falciano, S; Farilla, A; George, S; Ghete, V M; González, S; Grothe, M; Kaczmarska, A; Karr, K M; Khomich, A; Konstantinidis, N P; Krasny, W; Li, W; Lowe, A; Luminari, L; Meessen, C; Mello, A G; Merino, G; Morettini, P; Moyse, E; Nairz, A; Negri, A; Nikitin, N V; Nisati, A; Padilla, C; Parodi, F; Pérez-Réale, V; Pinfold, J L; Pinto, P; Polesello, G; Qian, Z; Resconi, S; Rosati, S; Scannicchio, D A; Schiavi, C; Schörner-Sadenius, T; Segura, E; De Seixas, J M; Shears, T G; Sivoklokov, S Yu; Smizanska, M; Soluk, R A; Stanescu, C; Tapprogge, Stefan; Touchard, F; Vercesi, V; Watson, A; Wengler, T; Werner, P; Wickens, F J; Wiedenmann, W; Wielers, M; Zobernig, G; RT 2003 13th IEEE-NPSS Real Time Conference

2004-01-01

The ATLAS High Level Trigger (HLT) system provides software-based event selection after the initial LVL1 hardware trigger. It is composed of two stages, the LVL2 trigger and the Event Filter (EF). The LVL2 trigger performs event selection with optimized algorithms using selected data guided by Region of Interest pointers provided by the LVL1 trigger. Those events selected by LVL2, are built into complete events, which are passed to the EF for a further stage of event selection and classification using off-line algorithms. Events surviving the EF selection are passed for off-line storage. The two stages of HLT are implemented on processor farms. The concept of distributing the selection process between LVL2 and EF is a key element in the architecture, which allows it to be flexible to changes (luminosity, detector knowledge, background conditions etc.) Although there are some differences in the requirements between these sub-systems there are many commonalities. An overview of the dataflow (event selection) an...

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

Science.gov (United States)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

The Molen Polymorphic Media Processor

NARCIS (Netherlands)

Kuzmanov, G.K.

2004-01-01

In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

Event-Triggered Output-Feedback Control for Disturbed Linear Systems

Directory of Open Access Journals (Sweden)

Hao Jiang

2018-01-01

Full Text Available In the last few decades, event-triggered control received considerable attention, because of advantages in reducing the resource utilization, such as communication load and processor. In this paper, we propose an event-triggered output-feedback controller for disturbed linear systems, in order to achieve both better resource utilization and disturbance attenuation properties at the same time. Based on our prior work on state-feedback H∞ control for disturbed systems, we propose an approach to design an output-feedback H∞ controller for the system whose states are not completely observable, and a sufficient condition guaranteeing the asymptotic stability and robustness of the system is given in the form of LMIs (Linear Matrix Inequalities.

Overview and performance of the ATLAS Level-1 Topological Trigger

CERN Document Server

Damp, Johannes Frederic; The ATLAS collaboration

2018-01-01

In 2017 the LHC provided proton-proton collisions to the ATLAS experiment with high luminosity (up to 2.06x10^34), placing stringent operational and physical requirements on the ATLAS trigger system in order to reduce the 40 MHz collision rate to a manageable event storage rate of 1 kHz, while not rejecting interesting physics events. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency of less than 2.5 μs. An important role is played by its newly commissioned component: the L1 topological trigger (L1Topo). This innovative system consists of two blades designed in AdvancedTCA form factor, mounting four individual state-of-the-art processors, and providing high input bandwidth and low latency data processing. Up to 128 topological trigger algorithms can be implemented to select interesting events by applying kinematic and angular requirements on electromagnetic clusters, jets, muons and total energy. This results in a significantly...

Digital Filter Performance for the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Hadley, D R; The ATLAS collaboration

2010-01-01

The ATLAS Level-1 Calorimeter Trigger is a hardware-based system designed to identify high-pT jets, electron/photon and tau candidates, and to measure total and missing ET in the ATLAS Liquid Argon and Tile calorimeters. It is a pipelined processor system, with a new set of inputs being evaluated every 25ns. The overall trigger decision has a latency budget of 2µs, including all transmission delays. The calorimeter trigger uses about 7200 reduced granularity analogue signals, which are first digitized at the 40 MHz LHC bunch-crossing frequency, before being passed to a digital Finite Impulse Response (FIR) filter. Due to latency and chip real-estate constraints, only a simple 5-element filter with limited precision can be used. Nevertheless this filter achieves a significant reduction in noise, along with improving the bunch-crossing assignment and energy resolution for small signals. The context in which digital filters are used for the ATLAS Level-1 Calorimeter Trigger will be presented, before describing ...

The Level 0 Pixel Trigger system for the ALICE experiment

International Nuclear Information System (INIS)

Rinella, G Aglieri; Kluge, A; Krivda, M

2007-01-01

The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper

The D OE software trigger

International Nuclear Information System (INIS)

Linnemann, J.T.; Michigan State Univ., East Lansing, MI

1992-10-01

In the D OE experiment, the software filter operates in a processor farm with each node processing a single event. Processing is data-driven: the filter does local processing to verify the candidates from the hardware trigger. The filter code consists of independent pieces called ''tools''; processing for a given hardware bit is a ''script'' invoking one or more ''tools'' sequentially. An offline simulator drives the same code with the same configuration files, running on real or simulated data. Online tests use farm nodes parasiting on the data stream. We discuss the performance of the system and how we attempt to verify its correctness

Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

CERN Document Server

Zhu, Junjie; The ATLAS collaboration

2017-01-01

The planned Phase-I and Phase-II upgrades of the LHC accelerator drastically impacts the ATLAS trigger and trigger rates. A replacement of the ATLAS innermost endcap muon station with a new small wheel (NSW) detector is planned for the second long shutdown period of 2019 - 2020. This upgrade will allow us to maintain a low pT threshold for single muon and excellent tracking capability even after the High-Luminosity LHC upgrade. The NSW detector will feature two new detector technologies, Resistive Micromegas and small-strip Thin Gap Chambers. Both detector technologies will provide trigger and tracking primitives. The total number of trigger and readout channels is about 2.4 millions, and the overall power consumption is expected to be about 75 kW. The electronics design will be implemented in some 8000 front-end boards including the design of four custom front-end ASICs capable to drive trigger and tracking primitives with high speed sterilizers to drive trigger candidates to the backend trigger processor sy...

A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

International Nuclear Information System (INIS)

Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Wilson, Peter; Phillips, Thomas J.

2005-01-01

We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2ns, a minimum input pulse width of 4.8ns and a minimum separation of 4.8ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and

A Fast hardware Tracker for the ATLAS Trigger system

CERN Document Server

Pandini, Carlo Enrico; The ATLAS collaboration

2015-01-01

The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. After a very successful data taking run the LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals, which requires a more extensive use of tracking information. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful, Field Programmable Gate Arrays form an important part of the system architecture, and the combinatorial problem of pattern r...

JPP: A Java Pre-Processor

OpenAIRE

Kiniry, Joseph R.; Cheong, Elaine

1998-01-01

The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

A hardware fast tracker for the ATLAS trigger

Science.gov (United States)

Asbah, Nedaa

2016-09-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 1034 cm-2 s-1. After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

Producing chopped firewood with firewood processors

International Nuclear Information System (INIS)

Kaerhae, K.; Jouhiaho, A.

2009-01-01

The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

The Associative Memory Serial Link Processor of the ALTAS Fast TracKer Processing System

CERN Document Server

Sotiropoulou, Calliope Louisa; The ATLAS collaboration

2017-01-01

The upgraded trigger system of the ATLAS experiment at LHC will improve the capability of the detectors to select the events with the greatest scientific potential. The FastTracker (FTK) is one of the ATLAS trigger upgrade that is presently under commissioning. FTK is a hardware system that feeds the High Level Trigger with charged particle tracks reconstructed from hits in silicon detectors at the rate of 105 events per second. Once a track candidate is found, the track reconstruction proceeds by matching low resolution hits to predefined patterns. Selected hits matching the predefined pattern are used in a second processing step for a more precise track fitting algorithm. The main processing element of FTK is the Associative Memory (AM) system that is used to perform pattern matching with high degree of parallelism. Its implementation is called the AM Board Serial Link Processor (AMBSLP) and it is a very efficient pattern matching machine that handles massively parallel data. The AMB SLP consists of two typ...

Optical Associative Processors For Visual Perception"

Science.gov (United States)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

AMD's 64-bit Opteron processor

CERN Multimedia

CERN. Geneva

2003-01-01

This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

Composable processor virtualization for embedded systems

NARCIS (Netherlands)

Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

2010-01-01

Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

Deterministic chaos in the processor load

International Nuclear Information System (INIS)

Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

2007-01-01

In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

Digital Filtering Performance in the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Hadley, D R; The ATLAS collaboration

2010-01-01

The ATLAS Level-1 Calorimeter Trigger is a hardware-based system designed to identify high-pT jets, elec- tron/photon and tau candidates, and to measure total and missing ET in the ATLAS Liquid Argon and Tile calorimeters. It is a pipelined processor system, with a new set of inputs being evaluated every 25ns. The overall trigger decision has a latency budget of 2µs, including all transmission delays. The calorimeter trigger uses about 7200 reduced granularity analogue signals, which are first digitized at the 40 MHz LHC bunch-crossing frequency, before being passed to a digital Finite Impulse Re- sponse (FIR) filter. Due to latency and chip real-estate constraints, only a simple 5-element filter with limited precision can be used. Nevertheless, this filter achieves a significant reduction in noise, along with improving the bunch-crossing assignment and energy resolution for small signals. The context in which digital filters are used for the ATLAS Level-1 Calorimeter Trigger is presented, before descr...

A Hardware Fast Tracker for the ATLAS trigger

CERN Document Server

Asbah, Nedaa; The ATLAS collaboration

2015-01-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10^{34} cm^{-2}s^{-1}. After a successful period of data taking from 2010 to early 2013, the LHC restarted with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide, at every level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondar...

Minimum Bias Trigger in ATLAS

International Nuclear Information System (INIS)

Kwee, Regina

2010-01-01

Since the restart of the LHC in November 2009, ATLAS has collected inelastic pp collisions to perform first measurements on charged particle densities. These measurements will help to constrain various models describing phenomenologically soft parton interactions. Understanding the trigger efficiencies for different event types are therefore crucial to minimize any possible bias in the event selection. ATLAS uses two main minimum bias triggers, featuring complementary detector components and trigger levels. While a hardware based first trigger level situated in the forward regions with 2.2 < |η| < 3.8 has been proven to select pp-collisions very efficiently, the Inner Detector based minimum bias trigger uses a random seed on filled bunches and central tracking detectors for the event selection. Both triggers were essential for the analysis of kinematic spectra of charged particles. Their performance and trigger efficiency measurements as well as studies on possible bias sources will be presented. We also highlight the advantage of these triggers for particle correlation analyses. (author)

New Fast Interaction Trigger for ALICE

Energy Technology Data Exchange (ETDEWEB)

Trzaska, Wladyslaw Henryk

2017-02-11

The LHC heavy-ion luminosity and collision rate from 2021 onwards will considerably exceed the design parameters of the present ALICE forward trigger detectors and the introduction of the Muon Forward Tracker (MFT) will significantly reduce the space available for the new trigger detectors. To comply with these conditions a new Fast Interaction Trigger (FIT) will be built. FIT will be the main forward trigger, luminometer, and interaction-time detector. It will also determine multiplicity, centrality, and reaction plane of heavy-ion collisions. FIT will consist of two arrays of Cherenkov quartz radiators with MCP-PMT sensors and of a plastic scintillator ring. By increasing the overall acceptance of FIT, the scintillator will improve centrality and event plane resolution. It will also add sensitivity for the detection of beam-gas events and provide some degree of redundancy. FIT is currently undergoing an intense R&D and prototyping period. It is scheduled for installation in ALICE during 2020.

Interference and protection of electromagnetic pulse to digital signal processor

International Nuclear Information System (INIS)

Wang Yan; Jiao Hongling; He Shanhong; Pan Chao; Feng Deren; Che Wenquan; Xiong Ying

2013-01-01

The effective electromagnetic pulse protection is studied in this paper, first the interference of electromagnetic pulse simulator path is analyzed, including the digital signal processor (DSP) and the discharge circuit of coupling interference and net electricity coupling interference. Using the structure optimization design, the hardware block reinforcement measurement and the setting of open software trap, and the watchdog anti-jamming measures, the interference test is completed such as the central processor core voltage of DSP, input/output (I/O) ports of DSP and the display screen. The experimental results show that the combination of hardware and software protection reinforcement technology is effective, and the interference pulse amplitude of DSP board I/O port and the kernel work voltage are reduced, and the interference duration is reduced from 2 μs to 400 ns. The interference pulse is effectively restrained. (authors)

Neurovision processor for designing intelligent sensors

Science.gov (United States)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

A Highly Selective First-Level Muon Trigger With MDT Chamber Data for ATLAS at HL-LHC

CERN Document Server

INSPIRE-00390105

2016-07-11

Highly selective triggers are essential for the physics programme of the ATLAS experiment at HL-LHC where the instantaneous luminosity will be about an order of magnitude larger than the LHC instantaneous luminosity in Run 1. The first level muon trigger rate is dominated by low momentum muons below the nominal trigger threshold due to the moderate momentum resolution of the Resistive Plate and Thin Gap trigger chambers. The resulting high trigger rates at HL-LHC can be su?ciently reduced by using the data of the precision Muon Drift Tube chambers for the trigger decision. This requires the implementation of a fast MDT read-out chain and of a fast MDT track reconstruction algorithm with a latency of at most 6 microseconds. A hardware demonstrator of the fast read-out chain has been successfully tested at the HL-LHC operating conditions at the CERN Gamma Irradiation Facility. The fast track reconstruction algorithm has been implemented on a fast trigger processor.

A Highly Selective First-Level Muon Trigger With MDT Chamber Data for ATLAS at HL-LHC

CERN Document Server

Nowak, Sebastian; The ATLAS collaboration

2015-01-01

Highly selective triggers are essential for the physics programme of the ATLAS experiment at HL-LHC where the instantaneous luminosity will be about an order of magnitude larger than the LHC design luminosity. The Level-1 muon trigger rate is dominated by low momentum muons below the nominal trigger threshold due to the limited momentum resolution of the Resistive Plate and Thin Gap trigger chambers. The resulting high trigger rates at HL-LHC can be sufficient reduced by using the data of the precision Muon Drift Tube chambers for the trigger decision. This requires the implementation of a fast MDT read-out chain and of a fast MDT track reconstruction algorithm with a latency of at most 6~$\\mu$s. A hardware demonstrator of the fast read-out chain has been successfully tested at the high HL-LHC background rates at the CERN Gamma Irradiation Facility. The fast track reconstruction algorithm has been implemented on a fas trigger processor.

A Hardware Fast Tracker for the ATLAS trigger

International Nuclear Information System (INIS)

Asbah, N.

2016-01-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10 34 cm -2 · s -1 . After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 μs, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

Development of a parallel trigger framework for rare decay searches

CERN Document Server

Pantaleo, Felice

The simplicity of kaon decays (few decay channels, low final-state multiplicities) enable the possibility to reach an excellent sensitivity in the searches of lepton flavor violating decays. The experimental characteristics of decays like $K^+\\to \\pi^- \\mu^+ \\mu^+$ are very clear and allow an efficient background rejection. However, the measurement of this kind of events requires the production of a remarkable number of kaon decays. The bandwidth of tape recording system currently available does not allow the storage of all the produced events. A multi-stage selection of the potentially interesting events is required (trigger). At NA62, a first selection is done in real-time (response time $<1$ ms) by the level 0 trigger. The level 0 trigger is based on programmable logic (FPGA) that does not allow the same flexibility of the processors used for software programmable computers. The performance of parallel architectures like multi-cores CPUs and GPUs (Graphics Processing Units), located on computers grap...

LHCb base-line level-0 trigger 3D-flow implementation

CERN Document Server

Crosetto, D

1999-01-01

The LHCb Level-0 trigger implementation with the 3D-Flow system offers full programmability, allowing it to adapt to unexpected operating conditions and enabling new, unpredicted physics. The implementation is described in detail and refers to components and technology available today. The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on the replication of a single type of circuit of 100 k gates, which communicates in six directions: bi-directional with North, East, West, and South neighbors, unidirectional from Top to Bottom, the system offers full programmability, modularity, ease of expansion and adaptation to the latest technology. A complete study of its applicability to the LHCb calorimeter triggers is presented. Full description of the input data handling, either in digital or mixed digital-analog form, of the data processing, and the transmission of results to the global level-0 trigger decision unit are provided. Any level-0 trig...

ATLAS Level-1 Calorimeter Trigger: Initial Timing and Energy Calibration

CERN Document Server

Childers, J T; The ATLAS collaboration

2010-01-01

The ATLAS Level-1 Calorimeter Trigger identifies high-pT objects in the Liquid Argon and Tile Calorimeters with a fixed latency of ~2.0 µs using a hardware-based, pipelined system built with custom electronics. The Preprocessor Module conditions and digitizes about 7200 pre-summed analogue signals from the calorimeters at the LHC bunch-crossing frequency of 40 MHz, and performs bunch-crossing identification (BCID) and deposited energy measurement for each input signal. This information is passed to further processors for object classification and total energy calculation, and the results used to make the Level-1 trigger decision for the ATLAS detector. The BCID and energy measurement in the trigger depend on precise timing adjustment to achieve correct sampling of the input signal peak. Test pulses from the calorimeters were analysed to derive the initial timing and energy calibration, and first data from the LHC restart in autumn 2009 and early 2010 were used for validation and further optimization. The res...

A lock circuit for a multi-core processor

DEFF Research Database (Denmark)

2015-01-01

An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

Sensitometric control of roentgen film processors

International Nuclear Information System (INIS)

Forsberg, H.; Karolinska Sjukhuset, Stockholm

1987-01-01

Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

Special purpose processors for high energy physics applications

International Nuclear Information System (INIS)

Verkerk, C.

1978-01-01

The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

Performance and development for the Inner Detector Trigger algorithms at ATLAS

CERN Document Server

Penc, O; The ATLAS collaboration

2014-01-01

The performance of the ATLAS Inner Detector (ID) Trigger algorithms being developed for running on the ATLAS High Level Trigger (HLT) processor farm during Run 2 of the LHC are presented. During the 2013-14 LHC long shutdown modifications are being carried out to the LHC accelerator to increase both the beam energy and luminosity. These modifications will pose significant challenges for the ID Trigger algorithms, both in terms execution time and physics performance. To meet these challenges, the ATLAS HLT software is being restructured to run as a more flexible single stage HLT, instead of two separate stages (Level2 and Event Filter) as in Run 1. This will reduce the overall data volume that needs to be requested by the HLT system, since data will no longer need to be requested for each of the two separate processing stages. Development of the ID Trigger algorithms for Run 2, currently expected to be ready for detector commissioning near the end of 2014, is progressing well and the current efforts towards op...

Preemptive and Non-Preemptive Real-Time UniProcessor Scheduling

OpenAIRE

George , Laurent; Rivierre , Nicolas; Spuri , Marco

1996-01-01

Projet REFLECS; Scheduling theory, as it applies to hard-real-time environment, has been widely studied in the last twenty years and it might be unclear to make it out within the plethora of results available. Our goal is first to collect in a single paper the results known for uniproces sor, non-idling, preemptive/non-preemptive, fixed/dynamic priority driven contexts, consid ering general task sets as a central figure for the description of possible processor loads. Second to establish new ...

Very Long Instruction Word Processors

Indian Academy of Sciences (India)

Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

A readout buffer prototype for ATLAS high-level triggers

CERN Document Server

Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

2001-01-01

Readout buffers are critical components in the dataflow chain of the ATLAS trigger/data-acquisition system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several readout buffers are grouped to form a readout buffer complex that acts as a data server for the high-level trigger selection algorithms and for the final data-collection system. This paper describes a functional prototype of a readout buffer based on a custom-made PCI mezzanine card that is designed to accept input data at up to 160 MB /s, to store up to 8 MB of data, and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and complex programmable logic devices. We present the integration of several of these cards in a readout buffer complex. We measure various performance figures and discuss to which extent these can fulfil ATLAS needs. (5 refs).

Considerations for control system software verification and validation specific to implementations using distributed processor architectures

International Nuclear Information System (INIS)

Munro, J.K. Jr.

1993-01-01

Until recently, digital control systems have been implemented on centralized processing systems to function in one of several ways: (1) as a single processor control system; (2) as a supervisor at the top of a hierarchical network of multiple processors; or (3) in a client-server mode. Each of these architectures uses a very different set of communication protocols. The latter two architectures also belong to the category of distributed control systems. Distributed control systems can have a central focus, as in the cases just cited, or be quite decentralized in a loosely coupled, shared responsibility arrangement. This last architecture is analogous to autonomous hosts on a local area network. Each of the architectures identified above will have a different set of architecture-associated issues to be addressed in the verification and validation activities during software development. This paper summarizes results of efforts to identify, describe, contrast, and compare these issues

An IMPI-compliant control system for the ATLAS TileCal Phase II Upgrade PreProcessor module

CERN Document Server

Zuccarello, Pedro Diego; The ATLAS collaboration

2016-01-01

TileCal is the Tile hadronic calorimeter of the ATLAS experiment at the LHC. The LHC upgrade program, currently under development, will culminate in the High Luminosity LHC (HL-LHC), which is expected to increase about five times the LHC nominal instantaneous luminosity. The readout electronics of the Tile calorimenter being redesigned introducing a new read-out strategy in order to accommodate the detector to the new HL-LHC parameters. The data generated inside the detector at every bunch crossing will be transmitted to the PreProcessor (PPR) boards before any event selection is applied. The PPRs will be located at off-detector sites. The PPR will be responsible of providing preprocessed trigger information to the ATLAS first level of trigger (L1). In overall it will represent the interface between the data acquisition, trigger and control systems and the on-detector electronics. The PPR, being an important part of the readout system, needs to be remotely accessed and monitored to prevent failures or, in cas...

Experimental testing of the noise-canceling processor.

Science.gov (United States)

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

Commissioning of the ATLAS high-level trigger with single beam and cosmic rays

CERN Document Server

Özcan, V Erkcan

2010-01-01

ATLAS is one of the two general-purpose detectors at the Large Hadron Collider (LHC). Using fast reconstruction algorithms, its trigger system needs to efficiently reject a huge rate of background events and still select potentially interesting ones with good efficiency. After a first processing level using custom electronics, the trigger selection is made by software running on two processor farms, designed to have a total of around two thousand multi-core machines. This system is known as the High Level Trigger (HLT). To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise reconstruction, aiming at the earliest possible rejection of background events. The recent LHC startup and short single-beam run provided a "stress test" of the trigger. Following this period, ATLAS continued to collect cosmic-ray events for detector alignment and calibration purposes. These running periods allowed strict tests of the HLT reconstruction and selection algorithms as we...

Development of a highly reliable CRT processor

International Nuclear Information System (INIS)

Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

1996-01-01

Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

Computer Generated Inputs for NMIS Processor Verification

International Nuclear Information System (INIS)

J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

2001-01-01

Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

3081//sub E/ processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

1983-03-01

Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

ATLAS level-1 calorimeter trigger hardware: initial timing and energy calibration

CERN Document Server

Childers, JT; The ATLAS collaboration

2010-01-01

The ATLAS Level-1 Calorimeter Trigger identifies high-pT objects in the Liquid Argon and Tile Calorimeters with a fixed latency of up to 2.4 microseconds using a hardware-based, pipelined system built with custom electronics. The Preprocessor Module conditions and digitizes about 7200 pre-summed analogue signals from the calorimeters at the LHC bunch-crossing frequency of 40 MHz, and performs bunch-crossing identification (BCID) and deposited energy measurement for each input signal. This information is passed to further processors for object classification and total energy calculation, and the results are used to make the Level-1 trigger decision for the ATLAS detector. The BCID and energy measurement in the trigger depend on precise timing adjustments to achieve correct sampling of the input signal peak. Test pulses from the calorimeters were analysed to derive the initial timing and energy calibration, and first data from the LHC restart in autumn 2009 and early 2010 were used for validation and further op...

Event-building and PC farm based level-3 trigger at the CDF experiment

CERN Document Server

Anikeev, K; Furic, I K; Holmgren, D; Korn, A J; Kravchenko, I V; Mulhearn, M; Ngan, P; Paus, C; Rakitine, A; Rechenmacher, R; Shah, T; Sphicas, Paris; Sumorok, K; Tether, S; Tseng, J

2000-01-01

In the technical design report the event building process at Fermilab's CDF experiment is required to function at an event rate of 300 events/sec. The events are expected to have an average size of 150 kBytes (kB) and are assembled from fragments of 16 readout locations. The fragment size from the different locations varies between 12 kB and 16 kB. Once the events are assembled they are fed into the Level-3 trigger which is based on processors running programs to filter events using the full event information. Computing power on the order of a second on a Pentium II processor is required per event. The architecture design is driven by the cost and is therefore based on commodity components: VME processor modules running VxWorks for the readout, an ATM switch for the event building, and Pentium PCs running Linux as an operation system for the Level-3 event processing. Pentium PCs are also used to receive events from the ATM switch and further distribute them to the processing nodes over multiple 100 Mbps Ether...

Multimode power processor

Science.gov (United States)

O'Sullivan, George A.; O'Sullivan, Joseph A.

1999-01-01

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

PixonVision real-time video processor

Science.gov (United States)

Puetter, R. C.; Hier, R. G.

2007-09-01

PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

Processors and systems (picture processing)

Energy Technology Data Exchange (ETDEWEB)

Gemmar, P

1983-01-01

Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

Special processor for in-core control systems

International Nuclear Information System (INIS)

Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.

1978-01-01

The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time

Functional Verification of Enhanced RISC Processor

OpenAIRE

SHANKER NILANGI; SOWMYA L

2013-01-01

This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

Effect of processor temperature on film dosimetry

International Nuclear Information System (INIS)

Srivastava, Shiv P.; Das, Indra J.

2012-01-01

Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

Status of the NA62 liquid krypton electromagnetic calorimeter Level 0 trigger processor

CERN Document Server

Bonaiuto, V; Fucci, A; Paoluzzi, G; Salamon, A; Salina, G; Santovetti, E; Sargeni, F; Venditti, S

2013-01-01

The NA62 experiment at the CERN SPS aims to measure the Branching Ratio of the very rare kaon decay K(+)→π(+)νbar nu collecting O(100) events with a 10% background in two years of data taking. To reject the K(+)→π(+)π(0) background the NA48 liquid krypton calorimeter will be used in the 1-10 mrad angular region. The status of the Liquid Krypton Electromagnetic Calorimeter Level 0 Trigger is presented.

A read-out buffer prototype for ATLAS high level triggers

CERN Document Server

Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

2000-01-01

Read-Out Buffers are critical components in the dataflow chain of the ATLAS Trigger/DAQ system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several Read-Out Buffers are grouped to form a Read-Out Buffer Complex that acts as a data server for the High Level Triggers selection algorithms and for the final data collection system. This paper describes a functional prototype of a Read-Out Buffer based on a custom made PCI mezzanine card that is designed to accept input data at up to 160 MB/s, to store up to 8 MB of data and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel I960 processor and CPLDs. We present the integration of several of these cards in a Read-Out Buffer Complex. We measure various performance figures and we discuss to which extent these can fulfill ATLAS needs. 5 Refs.

Bank switched memory interface for an image processor

International Nuclear Information System (INIS)

Barron, M.; Downward, J.

1980-09-01

A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

SLAC Scanner Processor applications in the data acquisition system for the upgraded Mark II detector

International Nuclear Information System (INIS)

Barklow, T.; Glanzman, T.; Lankford, A.J.; Riles, K.

1985-09-01

The SLAC Scanner Processor is a general purpose, programmable FASTBUS crate/cable master/slave module. This device plays a central role in the readout, buffering and pre-processing of data from the upgraded Mark II detector's new central drift chamber. In addition to data readout, the SSPs assist in a variety of other services, such as detector calibration, FASTBUS system management, FASTBUS system initialization and verification, and FASTBUS module testing. 9 refs., 1 fig., 2 tabs

Toward a rational understanding of migraine trigger factors.

Science.gov (United States)

Martin, V T; Behbehani, M M

2001-07-01

The typical migraine patient is exposed to a myriad of migraine triggers on a daily basis. These triggers potentially can act at various sites within the cerebral vasculature and the central nervous system to promote the development of migraine headache. The challenge to the physician is in the identification and avoidance of migraine trigger factors within patients suffering from migraine headache. Only through a rational approach to migraine trigger factors can physicians develop an appropriate treatment strategy for migraine patients.

VON WISPR Family Processors: Volume 1

National Research Council Canada - National Science Library

Wagstaff, Ronald

1997-01-01

...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

An Alternative Flight Software Trigger Paradigm: Applying Multivariate Logistic Regression to Sense Trigger Conditions Using Inaccurate or Scarce Information

Science.gov (United States)

Smith, Kelly M.; Gay, Robert S.; Stachowiak, Susan J.

2013-01-01

In late 2014, NASA will fly the Orion capsule on a Delta IV-Heavy rocket for the Exploration Flight Test-1 (EFT-1) mission. For EFT-1, the Orion capsule will be flying with a new GPS receiver and new navigation software. Given the experimental nature of the flight, the flight software must be robust to the loss of GPS measurements. Once the high-speed entry is complete, the drogue parachutes must be deployed within the proper conditions to stabilize the vehicle prior to deploying the main parachutes. When GPS is available in nominal operations, the vehicle will deploy the drogue parachutes based on an altitude trigger. However, when GPS is unavailable, the navigated altitude errors become excessively large, driving the need for a backup barometric altimeter to improve altitude knowledge. In order to increase overall robustness, the vehicle also has an alternate method of triggering the parachute deployment sequence based on planet-relative velocity if both the GPS and the barometric altimeter fail. However, this backup trigger results in large altitude errors relative to the targeted altitude. Motivated by this challenge, this paper demonstrates how logistic regression may be employed to semi-automatically generate robust triggers based on statistical analysis. Logistic regression is used as a ground processor pre-flight to develop a statistical classifier. The classifier would then be implemented in flight software and executed in real-time. This technique offers improved performance even in the face of highly inaccurate measurements. Although the logistic regression-based trigger approach will not be implemented within EFT-1 flight software, the methodology can be carried forward for future missions and vehicles.

Digital signal integrity and stability in the ATLAS Level-1 Calorimeter Trigger

CERN Document Server

Achenbach, R; Aharrouche, M; Andrei, V; Åsman, B; Barnett, B M; Bauss, B; Bendel, M; Bohm, C; Booth, J R A; Bracinik, J; Brawn, I P; Charlton, D G; Childers, J T; Collins, N J; Curtis, C J; Davis, A O; Eckweiler, S; Eisenhandler, E F; Faulkner, P J W; Fleckner, J; Föhlisch, F; Gee, C N P; Gillman, A R; Goringer, C; Groll, M; Hadley, D R; Hanke, P; Hellman, S; Hidvegi, A; Hillier, S J; Johansen, M; Kluge, E E; Kühl, T; Landon, M; Lendermann, V; Lilley, J N; Mahboubi, K; Mahout, G; Meier, K; Middleton, R P; Moa, T; Morris, J D; Müller, F; Neusiedl, A; Ohm, C; Oltmann, B; Perera, V J O; Prieur, D P F; Qian, W; Rieke, S; Rühr, F; Sankey, D P C; Schäfer, U; Schmitt, K; Schultz-Coulon, H C; Silverstein, S; Sjölin, J; Staley, R J; Stamen, R; Stockton, M C; Tan, C L A; Tapprogge, S; Thomas, J P; Thompson, P D; Watkins, P M; Watson, A; Weber, P; Wessels, M; Wildt, M

2008-01-01

The ATLAS Level-1 calorimeter trigger is a hardware-based system with the goal of identifying high-pT objects and to measure total and missing ET in the ATLAS calorimeters within an overall latency of 2.5 microseconds. This trigger system is composed of the Preprocessor which digitises about 7200 analogue input channels and two digital processors to identify high-pT signatures and to calculate the energy sums. The digital part consists of multi-stage, pipelined custom-built modules. The high demands on connectivity between the initial analogue stage and digital part and between the custom-built modules are presented. Furthermore the techniques to establish timing regimes and verify connectivity and stable operation of these digital links will be described.

The LVL2 trigger goes online

CERN Multimedia

David Berge

On Friday, the 9th of February, the ATLAS TDAQ community reached an important milestone. In a successful integration test, cosmic-ray muons were recorded with parts of the muon spectrometer, the central-trigger system and a second-level trigger algorithm. This was actually the first time that a full trigger slice all the way from the first-level trigger muon chambers up to event building after event selection by the second-level trigger ran online with cosmic rays. The ATLAS trigger and data acquisition system has a three-tier structure that is designed to cope with the enormous demands of proton-proton collisions at a bunch-crossing frequency of 40 MHz, with a typical event size of 1-2 MB. The online event selection has to reduce the incoming rate by a factor of roughly 200,000 to 200 Hz, a rate digestible by the archival-storage and offline-processing facilities. ATLAS has a mixed system: the first-level trigger (LVL1) is in hardware, while the other two consecutive levels, the second-level trigger (LVL2)...

The Database Driven ATLAS Trigger Configuration System

CERN Document Server

Martyniuk, Alex; The ATLAS collaboration

2015-01-01

This contribution describes the trigger selection configuration system of the ATLAS low- and high-level trigger (HLT) and the upgrades it received in preparation for LHC Run 2. The ATLAS trigger configuration system is responsible for applying the physics selection parameters for the online data taking at both trigger levels and the proper connection of the trigger lines across those levels. Here the low-level trigger consists of the already existing central trigger (CT) and the new Level-1 Topological trigger (L1Topo), which has been added for Run 2. In detail the tasks of the configuration system during the online data taking are Application of the selection criteria, e.g. energy cuts, minimum multiplicities, trigger object correlation, at the three trigger components L1Topo, CT, and HLT On-the-fly, e.g. rate-dependent, generation and application of prescale factors to the CT and HLT to adjust the trigger rates to the data taking conditions, such as falling luminosity or rate spikes in the detector readout ...

Many - body simulations using an array processor

International Nuclear Information System (INIS)

Rapaport, D.C.

1985-01-01

Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

Multi-processor network implementations in Multibus II and VME

International Nuclear Information System (INIS)

Briegel, C.

1992-01-01

ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)

The Soft X-ray real time fast trigger system

International Nuclear Information System (INIS)

Blackler, K.; Edwards, A.; Holm, J.

1992-05-01

Most current diagnostics are limited to recording data either at fixed times and data rates, or in response to certain predefined events - such as the injection of a pellet. The previous Soft X-Ray trigger system at Joint European Torus Joint Undertaking (JET)(A.W. Edwards et al., Rev Sci Instrum. 57(8), p2142, 1986) improved upon this by using Analogue Signal Processors to monitor the analogue data in real time and to provide 'triggers' to the data acquisition system in response to an event such as a sawtooth collapse. This system was however limited in the type of events that could be detected. It was also incapable of being rapidly re-configured. Advances in digital electronics caused a study to be undertaken to see if this situation could be improved. The system described below is the result of this study and has successfully run at JET since the summer of 1990, providing a greatly increased quality of data as well as recording some new phenomena such as the spontaneous snake. This note has been produced to describe the function and operation of the trigger system. (author)

Evaluation of the Intel Sandy Bridge-EP server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2012-01-01

In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

Array processors based on Gaussian fraction-free method

Energy Technology Data Exchange (ETDEWEB)

Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

1998-03-01

The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

The charged particle trigger of the CELLO-detector

International Nuclear Information System (INIS)

Schroeder, V.

1981-01-01

The fast charged particle trigger of the CELLO-detector at the PETRA e + e - storage ring (DESY) is a fast software programmable hardware processor. It is using multiwire chamber signals as inputs and takes a decision on charged tracks coming from the interaction region in less than 1 μsec. The input signals are addressing Random Access Memory devices in which the mask schemes of all meaningful physical tracks are stored. The RAM output signals give information about the numbers and shapes of the valid masks found. This information is used for fast event acquisition and online data analysis done by a PDP 11 computer. (orig.)

Centralized multiprocessor control system for the frascati storage rings DAΦNE

International Nuclear Information System (INIS)

Di Pirro, G.; Milardi, C.; Serio, M.

1992-01-01

We describe the status of the DANTE (DAΦne New Tools Environment) control system for the new DAΦNE Φ-factory under construction at the Frascati National Laboratories. The system is based on a centralized communication architecture for simplicity and reliability. A central processor unit coordinates all communications between the consoles and the lower level distributed processing power, and continuously updates a central memory that contains the whole machine status. We have developed a system of VME Fiber Optic interfaces allowing very fast point to point communication between distant processors. Macintosh II personal computers are used as consoles. The lower levels are all built using the VME standard. (author)

Multiple Embedded Processors for Fault-Tolerant Computing

Science.gov (United States)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

Design Principles for Synthesizable Processor Cores

DEFF Research Database (Denmark)

Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

2012-01-01

As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

Data register and processor for multiwire chambers

International Nuclear Information System (INIS)

Karpukhin, V.V.

1985-01-01

A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

Improving the ATLAS physics potential with the Fast Track Trigger System

CERN Document Server

Cavaliere, Viviana; The ATLAS collaboration

2015-01-01

The ATLAS Fast TracKer (FTK) is a custom electronics system that will operate at the full Level-1 accept rate, 100 kHz, to provide high quality tracks as input to the High-Level Trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories (AM) and FPGAs. We present the advantages for the physics goals of the ATLAS experiment and the recent results on the design, technological advancements and testing of some of the core components used in the processor.

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

The performance of an LSI-11/23 with a SKYMNK-Q array processor as a high speed front end processor

International Nuclear Information System (INIS)

Clark, D.L.

1983-01-01

The NSRL has recently installed a VAX-11/750 based data acquisition system which is networked to two LSI-11/23 satellite processors. Each of the LSI's are connected to CAMAC branch drivers. The LSI's have small array processors installed for use in preprocessing data. The objective is to provide an easy to use high speed processor that will relieve the VAX of some of the real-time data analysis tasks. The basic operation of the array processor and some of the results of performance tests are described

Embedded Processor Laboratory

Data.gov (United States)

Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

Science.gov (United States)

Cerati, Giuseppe; Elmer, Peter; Krutelyov, Slava; Lantz, Steven; Lefebvre, Matthieu; Masciovecchio, Mario; McDermott, Kevin; Riley, Daniel; Tadel, Matevž; Wittich, Peter; Würthwein, Frank; Yagil, Avi

2017-08-01

For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

Directory of Open Access Journals (Sweden)

Cerati Giuseppe

2017-01-01

Full Text Available For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU, ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC, for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

Energy Technology Data Exchange (ETDEWEB)

Cerati, Giuseppe [Fermilab; Elmer, Peter [Princeton U.; Krutelyov, Slava [UC, San Diego; Lantz, Steven [Cornell U.; Lefebvre, Matthieu [Princeton U.; Masciovecchio, Mario [UC, San Diego; McDermott, Kevin [Cornell U.; Riley, Daniel [Cornell U., LNS; Tadel, Matevž [UC, San Diego; Wittich, Peter [Cornell U.; Würthwein, Frank [UC, San Diego; Yagil, Avi [UC, San Diego

2017-01-01

For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

Science.gov (United States)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Architectural design and analysis of a programmable image processor

International Nuclear Information System (INIS)

Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

2003-01-01

In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

Analytical Bounds on the Threads in IXP1200 Network Processor

OpenAIRE

Ramakrishna, STGS; Jamadagni, HS

2003-01-01

Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

A UNIX-based prototype biomedical virtual image processor

International Nuclear Information System (INIS)

Fahy, J.B.; Kim, Y.

1987-01-01

The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge

ATLAS level-1 calorimeter trigger hardware: initial timing and energy calibration

International Nuclear Information System (INIS)

Childers, J T

2011-01-01

The ATLAS Level-1 Calorimeter Trigger identifies high-pT objects in the Liquid Argon and Tile Calorimeters with a fixed latency of up to 2.5μs using a hardware-based, pipelined system built with custom electronics. The Preprocessor Module conditions and digitizes about 7200 pre-summed analogue signals from the calorimeters at the LHC bunch-crossing frequency of 40 MHz, and performs bunch-crossing identification (BCID) and deposited energy measurement for each input signal. This information is passed to further processors for object classification and total energy calculation, and the results are used to make the Level-1 trigger decision for the ATLAS detector. The BCID and energy measurement in the trigger depend on precise timing adjustments to achieve correct sampling of the input signal peak. Test pulses from the calorimeters were analysed to derive the initial timing and energy calibration, and first data from the LHC restart in autumn 2009 and early 2010 were used for validation and further optimization. The results from these calibration measurements are presented.

Acceleration of spiking neural network based pattern recognition on NVIDIA graphics processors.

Science.gov (United States)

Han, Bing; Taha, Tarek M

2010-04-01

There is currently a strong push in the research community to develop biological scale implementations of neuron based vision models. Systems at this scale are computationally demanding and generally utilize more accurate neuron models, such as the Izhikevich and the Hodgkin-Huxley models, in favor of the more popular integrate and fire model. We examine the feasibility of using graphics processing units (GPUs) to accelerate a spiking neural network based character recognition network to enable such large scale systems. Two versions of the network utilizing the Izhikevich and Hodgkin-Huxley models are implemented. Three NVIDIA general-purpose (GP) GPU platforms are examined, including the GeForce 9800 GX2, the Tesla C1060, and the Tesla S1070. Our results show that the GPGPUs can provide significant speedup over conventional processors. In particular, the fastest GPGPU utilized, the Tesla S1070, provided a speedup of 5.6 and 84.4 over highly optimized implementations on the fastest central processing unit (CPU) tested, a quadcore 2.67 GHz Xeon processor, for the Izhikevich and the Hodgkin-Huxley models, respectively. The CPU implementation utilized all four cores and the vector data parallelism offered by the processor. The results indicate that GPUs are well suited for this application domain.

The communication processor of TUMULT-64

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Jansen, P.G.

1988-01-01

Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

High-Speed General Purpose Genetic Algorithm Processor.

Science.gov (United States)

Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

2016-07-01

In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

Accuracies Of Optical Processors For Adaptive Optics

Science.gov (United States)

Downie, John D.; Goodman, Joseph W.

1992-01-01

Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

Making CSB + -Trees Processor Conscious

DEFF Research Database (Denmark)

Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

2005-01-01

of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

Upgrade of the cathode strip chamber level 1 trigger optical links at CMS

International Nuclear Information System (INIS)

Ecklund, K; Liu, J; Matveev, M; Padley, P; Madorsky, A

2012-01-01

At the Large Hadron Collider (LHC) at CERN, the CMS experiment's Level 1 Trigger system for the endcap Cathode Strip Chambers (CSC) has 180 optical links to transmit Level 1 trigger primitives from 60 peripheral crates to the CSC Track Finder (CSCTF) which reconstructs muon candidates. Currently there is a limit of 3 trigger primitives per crate serving a cluster of 9 chambers. With the anticipated LHC luminosity increase up to 10 35 cm −2 s −1 at full energy of 7 TeV/beam the Muon Port Card (MPC), which transmits the primitives, the receiver in the CSCTF (Sector Processor) and the optical transmission system itself need to be upgraded. At the same time it is very desirable to preserve all the old optical links intact for compatibility with the present Track Finder during transition period. We present here the results of our efforts in the past two years to upgrade the MPC board, including the hardware developments, data transmission tests and latency measurements.

Lipsi: Probably the Smallest Processor in the World

DEFF Research Database (Denmark)

Schoeberl, Martin

2018-01-01

While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

Recommending the heterogeneous cluster type multi-processor system computing

International Nuclear Information System (INIS)

Iijima, Nobukazu

2010-01-01

Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

Use of modeling to assess the scalability of Ethernet networks for the ATLAS second level trigger

CERN Document Server

Korcyl, K; Dobinson, Robert W; Saka, F

1999-01-01

The second level trigger of LHC's ATLAS experiment has to perform real-time analyses on detector data at 10 GBytes/s. A switching network is required to connect more than thousand read-out buffers to about thousand processors that execute the trigger algorithm. We are investigating the use of Ethernet technology to build this large switching network. Ethernet is attractive because of the huge installed base, competitive prices, and recent introduction of the high-performance Gigabit version. Due to the network's size it has to be constructed as a layered structure of smaller units. To assess the scalability of such a structure we evaluated a single switch unit. (0 refs).

The Level-1 Calorimeter Global Feature Extractor (gFEX) Boosted Object Trigger for the Phase-I Upgrade of the ATLAS Experiment

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00235957; The ATLAS collaboration; Stark, Giordon; Miller, David

2016-01-01

The Global Feature Extractor (gFEX) module is a planned component of the Level 1 online trigger system for the ATLAS experiment planned for installation during the Phase I upgrade in 2018. This unique single electronics board with multiple high speed processors will receive coarse-granularity information from all the ATLAS calorimeters enabling the identification in real time of large-radius jets for capturing Lorentz-boosted objects such as top quarks, Higgs, $Z$ and $W$ bosons. The gFEX architecture also facilitates the calculation of global event variables such as missing transverse energy, centrality for heavy ion collisions, and event-by-event pile-up energy density. Details of the electronics architecture that provides these capabilities are presented, along with results of tests of the prototype systems now available. The status of the firmware algorithm design and implementation as well as monitoring capabilities are also presented.

Computation of Molecular Spectra on a Quantum Processor with an Error-Resilient Algorithm

Science.gov (United States)

Colless, J. I.; Ramasesh, V. V.; Dahlen, D.; Blok, M. S.; Kimchi-Schwartz, M. E.; McClean, J. R.; Carter, J.; de Jong, W. A.; Siddiqi, I.

2018-02-01

Harnessing the full power of nascent quantum processors requires the efficient management of a limited number of quantum bits with finite coherent lifetimes. Hybrid algorithms, such as the variational quantum eigensolver (VQE), leverage classical resources to reduce the required number of quantum gates. Experimental demonstrations of VQE have resulted in calculation of Hamiltonian ground states, and a new theoretical approach based on a quantum subspace expansion (QSE) has outlined a procedure for determining excited states that are central to dynamical processes. We use a superconducting-qubit-based processor to apply the QSE approach to the H2 molecule, extracting both ground and excited states without the need for auxiliary qubits or additional minimization. Further, we show that this extended protocol can mitigate the effects of incoherent errors, potentially enabling larger-scale quantum simulations without the need for complex error-correction techniques.

A Hardware Fast Tracker for the ATLAS Trigger: The Fast TracKer (FTK) Project.

CERN Document Server

Asbah, Nedaa; The ATLAS collaboration

2015-01-01

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10^{34} cm^{-2} s{-1}. After a successful period of data taking from 2010 to early 2013, the LHC is restarting in 2015 with much higher instantaneous luminosity and this will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide, at every level-1 accept (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast extensive access to tracking information, with resolution comparable to the offline reconstruction, the Fast Tracker will for example help the High Level Trigger...

The Design and Performance of the ATLAS Inner Detector Trigger for Run 2 LHC Collisions at 13 TeV

CERN Document Server

Kilby, Callum; The ATLAS collaboration

2016-01-01

The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm with the LHC Run 2 data with collisions at both 50 ns and 25 ns are discussed. The HLT ID tracking algorithms are essential for the identification of nearly all physics signatures in the ATLAS trigger. In order to deal with the expected higher rates for LHC Run 2, the ID trigger was redesigned during the 2013-15 long shutdown to satisfy the demands of the higher energy LHC operation. The detailed performance of the tracking algorithms with the Run 2 data taken so far for the different trigger signatures in terms of both efficiency, and resolution is presented. The online processing times for running trigger tracking for the different trigger signatures are discussed in detail. Where appropriate, comparison of the new strategy for Run 2, with that adopted in Run 1 are made to demonstrate successful application and superior performance of the strategy adopted for Run 2.

A digital retina-like low-level vision processor.

Science.gov (United States)

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

Median and Morphological Specialized Processors for a Real-Time Image Data Processing

Directory of Open Access Journals (Sweden)

Kazimierz Wiatr

2002-01-01

Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

Java Processor Optimized for RTSJ

Directory of Open Access Journals (Sweden)

Tu Shiliang

2007-01-01

Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

International Nuclear Information System (INIS)

Meng, X.T.; Levin, D.S.; Chapman, J.W.; Zhou, B.

2016-01-01

The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

Central Diffraction in ALICE

CERN Document Server

Schicker, R

2012-01-01

The ALICE experiment at the Large Hadron Collider (LHC) at CERN consists of a central barrel, a muon spectrometer and of additional detectors for trigger and event classification purposes. The low transverse momentum threshold of the central barrel gives ALICE a unique opportunity to study the low mass sector of central production at the LHC. I will report on first analysis results of meson production in double gap events in minimum-bias proton-proton collisions at sqrt{s} = 7 TeV, and will describe a dedicated double gap trigger for future data taking.

ALICE High Level Trigger

CERN Multimedia

Alt, T

2013-01-01

The ALICE High Level Trigger (HLT) is a computing farm designed and build for the real-time, online processing of the raw data produced by the ALICE detectors. Events are fully reconstructed from the raw data, analyzed and compressed. The analysis summary together with the compressed data and a trigger decision is sent to the DAQ. In addition the reconstruction of the events allows for on-line monitoring of physical observables and this information is provided to the Data Quality Monitor (DQM). The HLT can process event rates of up to 2 kHz for proton-proton and 200 Hz for Pb-Pb central collisions.

Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

International Nuclear Information System (INIS)

Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

1983-01-01

This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

Commissioning of the ATLAS High Level Trigger with single beam and cosmic rays

International Nuclear Information System (INIS)

Di Mattia, A

2010-01-01

ATLAS is one of the two general-purpose detectors at the Large Hadron Collider (LHC). The trigger system is responsible for making the online selection of interesting collision events. At the LHC design luminosity of 10 34 cm -2 s -1 it will need to achieve a rejection factor of the order of 10 -7 against random proton-proton interactions, while selecting with high efficiency events that are needed for physics analyses. After a first processing level using custom electronics based on FPGAs and ASICs, the trigger selection is made by software running on two processor farms, containing a total of around two thousand multi-core machines. This system is known as the High Level Trigger (HLT). To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise reconstruction, aiming at the earliest possible rejection of background events. The recent LHC startup and short single-beam run provided a 'stress test' of the system and some initial calibration data. Following this period, ATLAS continued to collect cosmic-ray events for detector alignment and calibration purposes. After giving an overview of the trigger design and its innovative features, this paper focuses on the experience gained from operating the ATLAS trigger with single LHC beams and cosmic-rays.

New development for low energy electron beam processor

International Nuclear Information System (INIS)

Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi

2003-01-01

Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)

New shower maximum trigger for electrons and photons at CDF

International Nuclear Information System (INIS)

Amidei, D.; Burkett, K.; Gerdes, D.; Miao, C.; Wolinski, D.

1994-01-01

For the 1994 Tevatron collider run, CDF has upgraded the electron and photo trigger hardware to make use of shower position and size information from the central shower maximum detector. For electrons, the upgrade has resulted in a 50% reduction in backgrounds while retaining approximately 90% of the signal. The new trigger also eliminates the background to photon triggers from single-phototube spikes

New shower maximum trigger for electrons and photons at CDF

International Nuclear Information System (INIS)

Gerdes, D.

1994-08-01

For the 1994 Tevatron collider run, CDF has upgraded the electron and photon trigger hardware to make use of shower position and size information from the central shower maximum detector. For electrons, the upgrade has resulted in a 50% reduction in backgrounds while retaining approximately 90% of the signal. The new trigger also eliminates the background to photon triggers from single-phototube discharge

A data base processor semantics specification package

Science.gov (United States)

Fishwick, P. A.

1983-01-01

A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

CERN Document Server

Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. ...

A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

CERN Document Server

Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. T...

Globe hosts launch of new processor

CERN Multimedia

2006-01-01

Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

The ATLAS High Level Trigger Infrastructure, Performance and Future Developments

CERN Document Server

The ATLAS collaboration

2009-01-01

The ATLAS High Level Trigger (HLT) is a distributed real-time software system that performs the final online selection of events produced during proton-proton collisions at the Large Hadron Collider (LHC). It is designed as a two-stage event filter running on a farm of commodity PC hardware. Currently the system consists of about 850 multi-core processing nodes that will be extended incrementally following the increasing luminosity of the LHC to about 2000 nodes depending on the evolution of the processor technology. Due to the complexity and similarity of the algorithms a large fraction of the software is shared between the online and offline event reconstruction. The HLT Infrastructure serves as the interface between the two domains and provides common services for the trigger algorithms. The consequences of this design choice will be discussed and experiences from the operation of the ATLAS HLT during cosmic ray data taking and first beam in 2008 will be presented. Since the event processing time at the HL...

GPUs for fast triggering and pattern matching at the CERN experiment NA62

International Nuclear Information System (INIS)

Lamanna, Gianluca; Collazuol, Gianmaria; Sozzi, Marco

2011-01-01

In rare decays experiments an effective trigger is crucial to reduce both the quantity of data written on tape and the bandwidth requirements for the DAQ (Data Acquisition) system. A multilevel architecture is commonly used to achieve a higher reduction factor, exploiting dedicated custom hardware and flexible software in standard computers. In this paper we discuss the possibility to use commercial video card processors (GPU) to build a fast and effective trigger system, both at hardware and software level. The case of fast pattern matching in the RICH detector of the NA62 experiment at CERN aiming at measuring the Branching Ratio of the ultra rare decay K + →π + νν-bar is considered as use case although the versatility and the customizability of this approach easily allow exporting the concept to different contexts.

XL-100S microprogrammable processor

International Nuclear Information System (INIS)

Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

1983-01-01

The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

Science.gov (United States)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

Simulation of a processor switching circuit with APLSV

International Nuclear Information System (INIS)

Dilcher, H.

1979-01-01

The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de

The ATLAS FTK system: how to improve the physics potential with a tracking trigger

CERN Document Server

Iizawa, T; The ATLAS collaboration

2014-01-01

After a very successful data taking run, the ATLAS experiment is being upgraded to cope with the higher luminosity and higher center of mass energy that the Large Hadron Collider will provide in the next years. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to operate at the level-1 trigger output rate. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGAs) form an important part of the system architecture, and the large level of computing power required for pattern recognition is provided by incorporating standard-cell ASICs named Associative Memories (AM). FTK provides global track reconstruction in the full inner silicon detector, with resolution comparable to the offline algorithms, in approximately 100 microseconds, allowing a fast and precise detection of the primary and secondary vertex information. The track and vertex information is then used by t...

The ATLAS FTK system: how to improve the physics potential with a tracking trigger

CERN Document Server

Iizawa, T; The ATLAS collaboration

2016-01-01

After a very successful data taking run, the ATLAS experiment [1] is being upgraded to cope with the higher luminosity and higher center of mass energy that the Large Hadron Collider (LHC) will provide in the next years. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device processor based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGAs) form an important part of the system architecture, and the large level of computing power required for pattern recognition is provided by incorporating standard-cell ASICs named Associative Memory (AM). FTK provides global track reconstruction in the full inner silicon detector, with resolution comparable to the offline algorithms, in approximately 100 microseconds, allowing a fast and precise detection of the primary and secondary vertex information. The track and vertex information is then used by the high-level trigger (HLT) algorithms, allowing highly improved tr...

Accuracy Limitations in Optical Linear Algebra Processors

Science.gov (United States)

Batsell, Stephen Gordon

1990-01-01

One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

Global search of triggered non-volcanic tremor

Science.gov (United States)

Chao, Tzu-Kai Kevin

Deep non-volcanic tremor is a newly discovered seismic phenomenon with low amplitude, long duration, and no clear P- and S-waves as compared with regular earthquake. Tremor has been observed at many major plate-boundary faults, providing new information about fault slip behaviors below the seismogenic zone. While tremor mostly occurs spontaneously (ambient tremor) or during episodic slow-slip events (SSEs), sometimes tremor can also be triggered during teleseismic waves of distance earthquakes, which is known as "triggered tremor". The primary focus of my Ph.D. work is to understand the physical mechanisms and necessary conditions of triggered tremor by systematic investigations in different tectonic regions. In the first chapter of my dissertation, I conduct a systematic survey of triggered tremor beneath the Central Range (CR) in Taiwan for 45 teleseismic earthquakes from 1998 to 2009 with Mw ≥ 7.5. Triggered tremors are visually identified as bursts of high-frequency (2-8 Hz), non-impulsive, and long-duration seismic energy that are coherent among many seismic stations and modulated by the teleseismic surface waves. A total of 9 teleseismic earthquakes has triggered clear tremor in Taiwan. The peak ground velocity (PGV) of teleseismic surface waves is the most important factor in determining tremor triggering potential, with an apparent threshold of ˜0.1 cm/s, or 7-8 kPa. However, such threshold is partially controlled by the background noise level, preventing triggered tremor with weaker amplitude from being observed. In addition, I find a positive correlation between the PGV and the triggered tremor amplitude, which is consistent with the prediction of the 'clock-advance' model. This suggests that triggered tremor can be considered as a sped-up occurrence of ambient tremor under fast loading from the passing surface waves. Finally, the incident angles of surface waves also play an important rule in controlling the tremor triggering potential. The next

Computation of Molecular Spectra on a Quantum Processor with an Error-Resilient Algorithm

Directory of Open Access Journals (Sweden)

J. I. Colless

2018-02-01

Full Text Available Harnessing the full power of nascent quantum processors requires the efficient management of a limited number of quantum bits with finite coherent lifetimes. Hybrid algorithms, such as the variational quantum eigensolver (VQE, leverage classical resources to reduce the required number of quantum gates. Experimental demonstrations of VQE have resulted in calculation of Hamiltonian ground states, and a new theoretical approach based on a quantum subspace expansion (QSE has outlined a procedure for determining excited states that are central to dynamical processes. We use a superconducting-qubit-based processor to apply the QSE approach to the H_{2} molecule, extracting both ground and excited states without the need for auxiliary qubits or additional minimization. Further, we show that this extended protocol can mitigate the effects of incoherent errors, potentially enabling larger-scale quantum simulations without the need for complex error-correction techniques.

Stimulation of the Basal and Central Amygdala in the Mustached Bat Triggers Echolocation and Agonistic Vocalizations within Multimodal Output

Directory of Open Access Journals (Sweden)

Jie eMa

2014-03-01

Full Text Available The neural substrate for the perception of vocalization is relatively well described, but we know much less about how the timing and specificity of vocalizations is tightly coupled with audiovocal communication behavior. In many vocal species, well-timed vocalizations accompany fear, vigilance and aggression. These emotive responses likely originate within the amygdala and other limbic structures, but the organization of motor outputs for triggering species-appropriate behaviors remains unclear. We performed electrical microstimulation at 461 highly restricted loci within the basal and central amygdala in awake mustached bats. At a subset of these sites, high frequency stimulation with weak constant current pulses presented at near-threshold levels triggered vocalization of either echolocation pulses or social calls. At the vast majority of locations, microstimulation produced a constellation of changes in autonomic and somatomotor outputs. These changes included widespread co-activation of significant tachycardia and hyperventilation and/or rhythmic ear pinna movements. In a few locations, responses were constrained to vocalization and/or pinna movements despite increases in the intensity of stimulation. The probability of eliciting echolocation pulses versus social calls decreased in a medial-posterior to anterolateral direction within the centrobasal amygdala. Microinjections of kainic acid at stimulation sites confirmed the contribution of cellular activity rather than fibers-of-passage in the control of multimodal outputs. The results suggest that multimodal clusters of neurons may simultaneously modulate the activity of multiple central pattern generators present within the brainstem.

Should a reliable information processor be chaotic (brain models)

Energy Technology Data Exchange (ETDEWEB)

Nicolis, J S

1982-01-01

Brain-like structures have evolved by performing signal processing initially by minimizing tracking errors on a competitive basis. Such systems are highly complex and at the same time notoriously disordered. The functional trace of the cerebral cortex of the human brain is a good example. The electroencephalogram (EEG) appears particularly fragmented during the execution of mental tasks, as well as during the recurrent episodes of rem sleep. A stochastically regular or a highly synchronized EEG on the other hand, characterises a drowsy (relaxing) or epileptic subject respectively and indicates-in both cases-a very incompetent information processor. The author suggests that such behavioral changeovers are produced via bifurcations which trigger the thalamocortical nonlinear pacemaking oscillator to switch from an unstable limit cycle to a strange attractor regime (i.e. to chaos), or vice versa. This analysis aims to show that the EEGs characteristics are not accidental but inevitable and even necessary and, therefore, functionally significant. 25 references.

Dead Time in the LAr Calorimeter Front-End Readout

CERN Document Server

Gingrich, D M

2002-01-01

We present readout time, latency, buffering, and dead-time calculations for the switched capacitor array controllers of the LAr calorimeter. The dead time is compared with algorithms for the dead-time generation in the level-1 central trigger processor.

Embedded processor extensions for image processing

Science.gov (United States)

Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

2008-04-01

The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

The Associative Memory Serial Link Processor of the ALTAS Fast TracKer Processing System

CERN Document Server

Sotiropoulou, Calliope Louisa; The ATLAS collaboration

2017-01-01

The upgraded Trigger and Data Acquisition (TDAQ) system of the ATLAS experiment at the LHC will improve the capability of the detector to select the events with the greatest scientific potential. The Fast TracKer (FTK) is one of the ATLAS TDAQ upgrades that is presently under commissioning. FTK is a custom hardware system that feeds the High Level Trigger (HLT) with charged particle tracks reconstructed from hits in silicon detectors at the rate of 105 events per second. The main processing element of FTK is the Associative Memory (AM) system that is used to perform pattern matching with a high degree of parallelism. Its implementation is called the AM Board Serial Link Processor (AMBSLP) and it is a very efficient pattern matching machine that handles in parallel massive data samples. The AMBSLP consists of two types of boards: the Little Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME motherboard that hosts four LAMB daughter-boar...

The Associative Memory system for the FTK processor at ATLAS

CERN Document Server

Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

2013-01-01

Experiments at the LHC hadron collider search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and instantaneus luminosity increase, increasingly complex and exclusive selections are necessary. We present results and performances of a new prototype of Associative Memory (AM) system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the ATLAS experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the "combinatorial challenge", is beat by the AM technology exploiting parallelism to the maximum level. The Associative Memory compares the event to pre-calculated "expectations" or "patterns" (pattern matching) at once and look for candidate tracks called "roads". The problem is solved by the time data are loaded into the AM devices. We report ...

Front-end electronics and trigger systems-Status and challenges

International Nuclear Information System (INIS)

Spieler, Helmuth

2007-01-01

The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not reduce the power required for the desired noise levels, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems, they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

Front-end electronics and trigger systems - status and challenges

International Nuclear Information System (INIS)

Spieler, Helmuth G; Spieler, Helmuth G

2007-01-01

The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

Sojourn time tails in processor-sharing systems

NARCIS (Netherlands)

Egorova, R.R.

2009-01-01

The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

An interactive parallel processor for data analysis

International Nuclear Information System (INIS)

Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

1984-01-01

A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

Optical Array Processor: Laboratory Results

Science.gov (United States)

Casasent, David; Jackson, James; Vaerewyck, Gerard

1987-01-01

A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities

OpenAIRE

Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto

2016-01-01

International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...

Multi-processor developments in the United States for future high energy physics experiments and accelerators

International Nuclear Information System (INIS)

Gaines, I.

1988-03-01

The use of multi-processors for analysis and high-level triggering in High Energy Physics experiments, pioneered by the early emulator systems, has reached maturity, in particular with the multiple microprocessor systems in use at Fermilab. It is widely acknowledged that such systems will fulfill the major portion of the computing needs of future large experiments. Recent developments at Fermilab's Advanced Computer Program will make such systems even more powerful, cost-effective, and easier to use than they are at present. The next generation of microprocessors, already available, will provide CPU power of about one VAX 780 equivalent/$300, while supporting most VMS FORTRAN extensions and large (>8MB) amounts of memory. Low cost high density mass storage devices (based on video tape cartridge technology) will allow parallel I/O to remove potential I/O bottlenecks in systems of over 1000 VAX equipment processors. New interconnection schemes and system software will allow more flexible topologies and extremely high data bandwidth, especially for on-line systems. This talk will summarize the work at the Advanced Computer Program and the rest of the US in this field. 3 refs., 4 figs

DZERO Level 3 DAQ/Trigger Closeout

CERN Multimedia

CERN. Geneva

2012-01-01

The Tevatron Collider, located at the Fermi National Accelerator Laboratory, delivered its last 1.96 TeV proton-antiproton collisions on September 30th, 2011. The DZERO experiment continues to take cosmic data for final alignment for several more months . Since Run 2 started, in March 2001, all DZERO data has been collected by the DZERO Level 3 Trigger/DAQ System. The system is a modern, networked, commodity hardware trigger and data acquisition system based around a large central switch with about 60 front ends and 200 trigger computers. DZERO front end crates are VME based. Single Board Computer interfaces between detector data on VME and the network transport for the DAQ system. Event flow is controlled by the Routing Master which can steer events to clusters of farm nodes based on the low level trigger bits that fired. The farm nodes are multi-core commodity computer boxes, without special hardware, that run isolated software to make the final Level 3 trigger decision. Passed events are transferred to th...

Towards a Process Algebra for Shared Processors

DEFF Research Database (Denmark)

Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

2002-01-01

We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

High-speed packet filtering utilizing stream processors

Science.gov (United States)

Hummel, Richard J.; Fulp, Errin W.

2009-04-01

Parallel firewalls offer a scalable architecture for the next generation of high-speed networks. While these parallel systems can be implemented using multiple firewalls, the latest generation of stream processors can provide similar benefits with a significantly reduced latency due to locality. This paper describes how the Cell Broadband Engine (CBE), a popular stream processor, can be used as a high-speed packet filter. Results show the CBE can potentially process packets arriving at a rate of 1 Gbps with a latency less than 82 μ-seconds. Performance depends on how well the packet filtering process is translated to the unique stream processor architecture. For example the method used for transmitting data and control messages among the pseudo-independent processor cores has a significant impact on performance. Experimental results will also show the current limitations of a CBE operating system when used to process packets. Possible solutions to these issues will be discussed.

Commissioning of the ATLAS High Level Trigger with single beam and cosmic rays

Energy Technology Data Exchange (ETDEWEB)

Di Mattia, A, E-mail: dimattia@mail.cern.c [Michigan State University - Department of Physics and Astronomy 3218 Biomedical Physical Science - East Lansing, MI 48824-2320 (United States)

2010-04-01

ATLAS is one of the two general-purpose detectors at the Large Hadron Collider (LHC). The trigger system is responsible for making the online selection of interesting collision events. At the LHC design luminosity of 10{sup 34} cm{sup -2}s{sup -1} it will need to achieve a rejection factor of the order of 10{sup -7} against random proton-proton interactions, while selecting with high efficiency events that are needed for physics analyses. After a first processing level using custom electronics based on FPGAs and ASICs, the trigger selection is made by software running on two processor farms, containing a total of around two thousand multi-core machines. This system is known as the High Level Trigger (HLT). To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise reconstruction, aiming at the earliest possible rejection of background events. The recent LHC startup and short single-beam run provided a 'stress test' of the system and some initial calibration data. Following this period, ATLAS continued to collect cosmic-ray events for detector alignment and calibration purposes. After giving an overview of the trigger design and its innovative features, this paper focuses on the experience gained from operating the ATLAS trigger with single LHC beams and cosmic-rays.

Design of RISC Processor Using VHDL and Cadence

Science.gov (United States)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

The Fast Interaction Trigger Upgrade for ALICE

CERN Document Server

Garcia-Solis, Edmundo

2016-01-01

The ALICE Collaboration is preparing a major detector upgrade for the second LHC long shutdown (2019–20). The LHC heavy-ion luminosity and collision rate from 2021 onwards will considerably exceed the design parameters of the present ALICE forward trigger detectors. Furthermore, the introduction of a new Muon Forward Tracker (MFT) will significantly reduce the space available for the upgraded trigger detectors. To comply with these conditions a Fast Interaction Trigger (FIT) has been designed. FIT will be the primary forward trigger, luminosity, and collision time measurement detector. The FIT will be capable of triggering at an interaction rate of 50 kHz, with a time resolution better than 30 ps, with 99% efficiency. It will also determine multiplicity, centrality, and reaction plane. FIT will consist of two arrays of Cherenkov radiators with MCP-PMT sensors and of a single, large-size scintillator ring. The arrays will be placed on both sides of the interaction point (IP). Because of the presence of the h...

Real time processor for array speckle interferometry

Science.gov (United States)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-02-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

The design and performance of the ATLAS Inner Detector trigger in high pileup collisions at 13 TeV at the Large Hadron Collider

CERN Document Server

Sotiropoulou, Calliope Louisa; The ATLAS collaboration

2017-01-01

The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm for 13 TeV LHC collision data with high pileup are discussed. The HLT ID tracking is a vital component in all physics signatures in the ATLAS Trigger for the precise selection of the rare or interesting events necessary for physics analysis without overwhelming the offine data storage in terms of both size and rate. To cope with the high expected interaction rates in the 13 TeV LHC collisions the ID trigger was redesigned during the 2013-15 long shutdown. The performance of the ID Trigger in the 2016 data from 13 TeV LHC collisions has been excellent and exceeded expectations as the interaction multiplicity increased throughout the year. The detailed efficiencies and resolutions of the trigger in a wide range of physics signatures are presented, to demonstrate how the trigger responded well under the extreme pileup conditions. The performance of the ID Trigger algorithms...

The design and performance of the ATLAS Inner Detector trigger in high pileup collisions at 13 TeV at the Large Hadron Collider

CERN Document Server

Kilby, Callum; The ATLAS collaboration

2017-01-01

The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm for 13 TeV LHC collision data with high pileup are discussed. The HLT ID tracking is a vital component in all physics signatures in the ATLAS Trigger for the precise selection of the rare or interesting events necessary for physics analysis without overwhelming the offline data storage in terms of both size and rate. To cope with the high expected interaction rates in the 13 TeV LHC collisions the ID trigger was redesigned during the 2013-15 long shutdown. The performance of the ID Trigger in the 2016 data from 13 TeV LHC collisions has been excellent and exceeded expectations as the interaction multiplicity increased throughout the year. The detailed efficiencies and resolutions of the trigger in a wide range of physics signatures are presented, to demonstrate how the trigger responded well under the extreme pileup conditions. The performance of the ID Trigger algorithm...

Global tracker for the ALICE high level trigger

International Nuclear Information System (INIS)

Vik, Thomas

2006-01-01

This thesis deals with two main topics. The first is the implementation and testing of a Kalman filter algorithm in the HLT (High Level Trigger) reconstruction code. This will perform the global tracking in the HLT, that is merging tracklets and hits from the different sub-detectors in the central barrel detector. The second topic is a trigger mode of the HLT which uses the global tracking of particles through the TRD (Transition Radiation Detector), TPC (Time Projection Chamber) and the ITS (Inner Tracking System): The dielectron trigger. Global tracking: The Kalman filter algorithm has been introduced to the HLT tracking scheme. (Author)

Vector and parallel processors in computational science

International Nuclear Information System (INIS)

Duff, I.S.; Reid, J.K.

1985-01-01

These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

The ATLAS High-Level Calorimeter Trigger in Run-2

CERN Document Server

Wiglesworth, Craig; The ATLAS collaboration

2018-01-01

The ATLAS Experiment uses a two-level triggering system to identify and record collision events containing a wide variety of physics signatures. It reduces the event rate from the bunch-crossing rate of 40 MHz to an average recording rate of 1 kHz, whilst maintaining high efficiency for interesting collision events. It is composed of an initial hardware-based level-1 trigger followed by a software-based high-level trigger. A central component of the high-level trigger is the calorimeter trigger. This is responsible for processing data from the electromagnetic and hadronic calorimeters in order to identify electrons, photons, taus, jets and missing transverse energy. In this talk I will present the performance of the high-level calorimeter trigger in Run-2, noting the improvements that have been made in response to the challenges of operating at high luminosity.

A High Performance Multi-Core FPGA Implementation for 2D Pixel Clustering for the ATLAS Fast TracKer (FTK) Processor

CERN Document Server

Sotiropoulou, C-L; The ATLAS collaboration; Beretta, M; Gkaitatzis, S; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

2014-01-01

The high performance multi-core 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors read out drivers (RODs) at 760Gbps, the full rate of level 1 triggers. Clustering is required as a method to reduce the high rate of the received data before further processing, as well as to determine the cluster centroid for obtaining obtain the best spatial measurement. Our implementation targets the pixel detectors and uses a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The design is fully generic and the cluster detection window size can be adjusted for optimizing the cluster identification process. Τhe implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility mak...

MPC Related Computational Capabilities of ARMv7A Processors

DEFF Research Database (Denmark)

Frison, Gianluca; Jørgensen, John Bagterp

2015-01-01

In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

The Associative Memory system for the FTK processor at ATLAS

CERN Document Server

Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

2013-01-01

Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

The Associative Memory system for the FTK processor at ATLAS

CERN Document Server

Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

2014-01-01

Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

Air-Lubricated Thermal Processor For Dry Silver Film

Science.gov (United States)

Siryj, B. W.

1980-09-01

Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

Logistic Fuel Processor Development

National Research Council Canada - National Science Library

Salavani, Reza

2004-01-01

The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

Electronics for CMS Endcap Muon Level-1 Trigger System Phase-1 and HL LHC Upgrades Summary

CERN Document Server

Madorsky, Alexander

2017-01-01

To accommodate high-luminosity LHC operation at 13 TeV collision energy, the CMS Endcap Muon Level-1 Trigger system had to be significantly modified. To provide the best track reconstruction, the trigger system must now import all available trigger primitives generated by Cathode Strip Chambers and by certain other subsystems, such as Resistive Plate Chambers (RPC). In addition to massive input bandwidth, this also required significant increase in logic and memory resources.To satisfy these requirements, a new Sector Processor unit has been designed. It consists of three modules. The Core Logic module houses the large FPGA that contains the track-finding logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Pt Lookup Table (PTLUT) module contains 1 GB of low-latency memory that is used to assign the final Pt to reconstructed muon tracks. The µTCA architecture (ado...

Advanced control system for the Integral Fast Reactor fuel pin processor

International Nuclear Information System (INIS)

Lau, L.D.; Randall, P.F.; Benedict, R.W.; Levinskas, D.

1993-01-01

A computerized control system has been developed for the remotely-operated fuel pin processor used in the Integral Fast Reactor Program, Fuel Cycle Facility (FCF). The pin processor remotely shears cast EBR- reactor fuel pins to length, inspects them for diameter, straightness, length, and weight, and then inserts acceptable pins into new sodium-loaded stainless-steel fuel element jackets. Two main components comprise the control system: (1) a programmable logic controller (PLC), together with various input/output modules and associated relay ladder-logic associated computer software. The PLC system controls the remote operation of the machine as directed by the OCS, and also monitors the machine operation to make operational data available to the OCS. The OCS allows operator control of the machine, provides nearly real-time viewing of the operational data, allows on-line changes of machine operational parameters, and records the collected data for each acceptable pin on a central data archiving computer. The two main components of the control system provide the operator with various levels of control ranging from manual operation to completely automatic operation by means of a graphic touch screen interface

Real time monitoring of electron processors

International Nuclear Information System (INIS)

Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

1995-01-01

A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

Multi-processor data acquisition and monitoring systems for particle physics

International Nuclear Information System (INIS)

White, V.; Burch, B.; Eng, K.; Heinicke, P.; Pyatetsky, M.; Ritchie, D.

1983-01-01

A high speed distributed processing system, using PDP-11 and VAX processors, is being developed at Fermilab. The acquisition of data is done using one or more PDP-11s. Additional processors are connected to provide either data logging or extra data analysis capabilities. Within this framework, functional interchangeability of PDP-11 and VAX processors and of the PDP-11 operating systems, RT-11 and RSX-11M, has been maintained. Inter-processor connections have been implemented in a general way using the 5 megabit DR11-W hardware currently selected for the purpose. Using this approach the authors have been able to make use of several existing data acquisition and analysis packages, such as RT/MULTI, in a multi-processor system

The design and performance of the ATLAS Inner Detector trigger in high pileup collisions at 13 TeV at the Large Hadron Collider

CERN Document Server

Grandi, Mario; The ATLAS collaboration

2018-01-01

The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the High Level Trigger (HLT) processor farm for 13 TeV LHC collision data with high pileup are discussed. The HLT ID tracking is a vital component in all physics signatures in the ATLAS Trigger for the precise selection of the rare or interesting events necessary for physics analysis without overwhelming the offline data storage in terms of both size and rate. To cope with the high interaction rates expected in the 13 TeV LHC collisions the ID trigger was redesigned during the 2013-15 long shutdown. The performance of the ID Trigger in both the 2016 and 2017 data from 13 TeV LHC collisions has been excellent and exceeded expectations, even at the very high interaction multiplicities observed at the end of data taking in 2017. The detailed efficiencies and resolutions of the trigger in a wide range of physics signatures are presented for the Run 2 data, illustrating the superb performance of the ID trigger algorith...

Functionality and performance of the ALFA_CTPIN module

CERN Document Server

Iwanski, Wieslaw; Korcyl, Krzysztof; Oechsle, Jan

2017-01-01

The ALFA_CTPIN module has been designed in response to increased internal processing time of the Central Trigger Processor (CTP) of the ATLAS experiment which resulted in reducing time left to the ALFA detector to deliver its own triggers to the CTP within specified latency. Accelerated extraction of ALFA triggers from encoded signals and the possibility to perform local triggers processing by this module allowed ALFA to contribute to global triggering of the ATLAS detector. A huge number of implemented scalers and flexibility in defining triggers processing criteria make also from this module a very attractive tool for in-depth analysis of properties of the LHC beam.

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

Science.gov (United States)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

The CDF II eXtremely Fast Tracker Upgrade

CERN Document Server

Fedorko, I; Errede, D; Gerberich, H; Junk, T; Kasten, M; Levine, S; Mokos, R; Pitts, K; Rogers, E; Veramendi, G; Azzurri, P; Donati, S; Staveris-Polykalas, A; Cochran, E; Efron, J; Gartner, J; Hughes, R; Johnson, M; Kilminster, B; Lannon, K; McKim, J; Olivito, D; Parks, B; Slaunwhite, J; Winer, B; Dittmann, J; Hewamanage, S; Krumnack, N; Wilson, J S; Erbacher, R; Forrest, R; Ivanov, A; Soha, A; Flanagan, G; Jones, T; Holm, S; Klein, R; Schmidt, E E; Scott, L; Shaw, T; Wilson, P J

2008-01-01

The CDF II eXtremely Fast Tracker (XFT) is the trigger processor which reconstructs charged particle tracks in the transverse plane of the central tracking chamber. The XFT tracks are also extrapolated to the electromagnetic calorimeter and muon chambers to generate trigger electron and muon candidates. The XFT is crucial for the entire CDF II physics program: it detects high pT leptons from W/Z and heavy flavor decays and, in conjunction with the Level 2 processors, it identifies secondary vertices from beauty decays. The XFT has thus been crucial for the recent measurement of the oscilation and Σb discovery. The increase of the Tevatron instantaneous luminosity demanded an upgrade of the system to cope with the higher occupancy of the chamber. In the upgraded XFT, three dimensional tracking reduces the level of fake tracks and measures the longitudinal track parameters, which strongly reinforce the trigger selections. This allows to mantain the trigger perfectly efficient at the record luminosities 2–3·...

Optical backplane interconnect switch for data processors and computers

Science.gov (United States)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Conception and validation software tools for the level 0 muon trigger of LHCb

International Nuclear Information System (INIS)

Aslanides, E.; Cachemiche, J. P.; Cogan, J.; Duval, P. Y.; Le Gac, R.; Hachon, F.; Leroy, O.; Liotard, P. L.; Marin, F.; Tsaregorodtsev, A.

2009-01-01

The Level-0 muon trigger processor of the LHCb experiment looks for straight particles crossing muon detector and measures their transverse momentum. It processes 40*10 6 proton-proton collisions per second. The tracking uses a road algorithm relying on the projectivity of the muon detector (the logical layout in the 5 muon station is projective in y to the interaction point and it is also projective in x when the bending in the horizontal direction introduced by the magnetic field is ignored). The architecture of the Level-0 muon trigger is complex with a dense network of data interconnections. The design and validation of such an intricate system has only been possible with intense use of software tools for the detector simulation, the modelling of the hardware components behaviour and the validation. A database describing the data-flow is the corner stone between the software and hardware components. (authors)

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

Science.gov (United States)

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

Fast digital processor for event selection according to particle number difference

International Nuclear Information System (INIS)

Basiladze, S.G.; Gus'kov, B.N.; Li Van Sun; Maksimov, A.N.; Parfenov, A.N.

1978-01-01

A fast digital processor for a magnetic spectrometer is described. It is used in experimental searches for charmed particles. The basic purpose of the processor is discriminating events in the difference of numbers of particles passing through two proportional chambers (PC). The processor consists of three units for detecting signals with PC, and a binary coder. The number of inputs of the processor is 32 for the first PC and 64 for the second. The difference in the number of particles discriminated is from 0 to 8. The resolution time is 180 ns. The processor is built in the CAMAC standard

Upside to downsizing : Acceleware's graphic processor technology propels seismic data processing revolution

Energy Technology Data Exchange (ETDEWEB)

Smith, M.

2009-11-15

Accelware has developed a graphic processor technology (GPU) that is transforming the petroleum industry. The benefits of the technology are its small-footprint, low-wattage, and high speed. The software brings supercomputing speed to the desktop by leveraging the massive parallel processing capacity to the very latest in GPU technology. This article discussed the GPU technology and its emergence as a powerful supercomputing tool. Accelware's partnering with California-based NVIDIA was also outlined. The advantages of the technology were also discussed including its smaller footprint. Accelware's hardware takes up a fraction of the space and uses up to 70 per cent less power than a traditional central processing unit. By combining Accelware's core knowledge in making complex algorithms run in parallel with an in-house team of seismic industry experts, the company provides software solutions for seismic data processors that access the massively parallel processing capabilities of GPUs. 1 fig.

Logistic Fuel Processor Development

National Research Council Canada - National Science Library

Salavani, Reza

2004-01-01

... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

On the efficacy of using the transfer-controlled procedure during periods of STP processor overloads in SS7 networks

Science.gov (United States)

Rumsewicz, Michael

1994-04-01

In this paper, we examine call completion performance, rather than message throughput, in a Common Channel Signaling network in which the processing resources, and not transmission resources, of a Signaling Transfer Point (STP) are overloaded. Specifically, we perform a transient analysis, via simulation, of a network consisting of a single Central Processor-based STP connecting many local exchanges. We consider the efficacy of using the Transfer Controlled (TFC) procedure when the network call attempt rate exceeds the processing capability of the STP. We find the following: (1) the success of the control depends critically on the rate at which TFC's are sent; (2) use of the TFC procedure in theevent of processor overload can provide reasonable call completion rates.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Science.gov (United States)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Directory of Open Access Journals (Sweden)

David R. W. Barr

2009-01-01

Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

TRIGGER

CERN Multimedia

Wesley Smith

Level-1 Trigger Hardware and Software The hardware of the trigger components has been mostly finished. The ECAL Endcap Trigger Concentrator Cards (TCC) are in production while Barrel TCC firmware has been upgraded, and the Trigger Primitives can now be stored by the Data Concentrator Card for readout by the DAQ. The Regional Calorimeter Trigger (RCT) system is complete, and the timing is being finalized. All 502 HCAL trigger links to RCT run without error. The HCAL muon trigger timing has been equalized with DT, RPC, CSC and ECAL. The hardware and firmware for the Global Calorimeter Trigger (GCT) jet triggers are being commissioned and data from these triggers is available for readout. The GCT energy sums from rings of trigger towers around the beam pipe beam have been changed to include two rings from both sides. The firmware for Drift Tube Track Finder, Barrel Sorter and Wedge Sorter has been upgraded, and the synchronization of the DT trigger is satisfactory. The CSC local trigger has operated flawlessly u...

Control structures for high speed processors

Science.gov (United States)

Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

1982-01-01

A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

Science.gov (United States)

Downie, John D.; Goodman, Joseph W.

1989-10-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

High performance graphics processors for medical imaging applications

International Nuclear Information System (INIS)

Goldwasser, S.M.; Reynolds, R.A.; Talton, D.A.; Walsh, E.S.

1989-01-01

This paper describes a family of high- performance graphics processors with special hardware for interactive visualization of 3D human anatomy. The basic architecture expands to multiple parallel processors, each processor using pipelined arithmetic and logical units for high-speed rendering of Computed Tomography (CT), Magnetic Resonance (MR) and Positron Emission Tomography (PET) data. User-selectable display alternatives include multiple 2D axial slices, reformatted images in sagittal or coronal planes and shaded 3D views. Special facilities support applications requiring color-coded display of multiple datasets (such as radiation therapy planning), or dynamic replay of time- varying volumetric data (such as cine-CT or gated MR studies of the beating heart). The current implementation is a single processor system which generates reformatted images in true real time (30 frames per second), and shaded 3D views in a few seconds per frame. It accepts full scale medical datasets in their native formats, so that minimal preprocessing delay exists between data acquisition and display

Evaluation of the Intel Westmere-EP server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2010-01-01

In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

Keystone Business Models for Network Security Processors

OpenAIRE

Arthur Low; Steven Muegge

2013-01-01

Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

Development of level 2 processor for the readout of TMC

International Nuclear Information System (INIS)

Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

1995-01-01

We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

The prefrontal landscape: implications of functional architecture for understanding human mentation and the central executive.

Science.gov (United States)

Goldman-Rakic, P S

1996-10-29

The functional architecture of prefrontal cortex is central to our understanding of human mentation and cognitive prowess. This region of the brain is often treated as an undifferentiated structure, on the one hand, or as a mosaic of psychological faculties, on the other. This paper focuses on the working memory processor as a specialization of prefrontal cortex and argues that the different areas within prefrontal cortex represent iterations of this function for different information domains, including spatial cognition, object cognition and additionally, in humans, semantic processing. According to this parallel processing architecture, the 'central executive' could be considered an emergent property of multiple domain-specific processors operating interactively. These processors are specializations of different prefrontal cortical areas, each interconnected both with the domain-relevant long-term storage sites in posterior regions of the cortex and with appropriate output pathways.

Using FPGA coprocessor for ATLAS level 2 trigger application

International Nuclear Information System (INIS)

Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

2006-01-01

Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

Design studies for the Double Chooz trigger

International Nuclear Information System (INIS)

Cucoanes, Andi Sebastian

2009-01-01

The main characteristic of the neutrino mixing effect is assumed to be the coupling between the flavor and the mass eigenstates. Three mixing angles (θ 12 , θ 23 , θ 13 ) are describing the magnitude of this effect. Still unknown, θ 13 is considered very small, based on the measurement done by the CHOOZ experiment. A leading experiment will be Double Chooz, placed in the Ardennes region, on the same site as used by CHOOZ. The Double Chooz goal is the exploration of ∝80% from the currently allowed θ 13 region, by searching the disappearance of reactor antineutrinos. Double Chooz will use two similar detectors, located at different distances from the reactor cores: a near one at ∝150 m where no oscillations are expected and a far one at 1.05 km distance, close to the first minimum of the survival probability function. The measurement foresees a precise comparison of neutrino rates and spectra between both detectors. The detection mechanism is based on the inverse β-decay. The Double Chooz detectors have been designed to minimize the rate of random background. In a simplified view, two optically separated regions are considered. The target, filled with Gd-doped liquid scintillator, is the main antineutrino interaction volume. Surrounding the target, the inner veto region aims to tag the cosmogenic muon background which hits the detector. Both regions are viewed by photomultipliers. The Double Chooz trigger system has to be highly efficient for antineutrino events as well as for several types of background. The trigger analyzes discriminated signals from the central region and the inner veto photomultipliers. The trigger logic is fully programmable and can combine the input signals. The trigger conditions are based on the total energy released in event and on the PMT groups multiplicity. For redundancy, two independent trigger boards will be used for the central region, each of them receiving signals from half of the photomultipliers. A third trigger board

Software-defined reconfigurable microwave photonics processor.

Science.gov (United States)

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

International Nuclear Information System (INIS)

Alberti, F; Citterio, M; Liberali, V; Meroni, C; Andreani, A; Stabile, A; Annovi, A; Beretta, M; Crescioli, F; Dell'Orso, M; Piendibene, M; Volpi, G; Giannetti, P; Lanza, A; Magalotti, D; Sacco, I

2013-01-01

Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.

Designing a dataflow processor using CλaSH

NARCIS (Netherlands)

Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria

2010-01-01

In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

TRIGGER

CERN Multimedia

Wesley Smith

Level-1 Trigger Hardware and Software The trigger synchronization procedures for running with cosmic muons and operating with the LHC were reviewed during the May electronics week. Firmware maintenance issues were also reviewed. Link tests between the new ECAL endcap trigger concentrator cards (TCC48) and the Regional Calorimeter Trigger have been performed. Firmware for the energy sum triggers and an upgraded tau trigger of the Global Calorimeter Triggers has been developed and is under test. The optical fiber receiver boards for the Track-Finder trigger theta links of the DT chambers are now all installed. The RPC trigger is being made more robust by additional chamber and cable shielding and also by firmware upgrades. For the CSC’s the front-end and trigger motherboard firmware have been updated. New RPC patterns and DT/CSC lookup tables taking into account phi asymmetries in the magnetic field configuration are under study. The motherboard for the new pipeline synchronizer of the Global Trigg...

Researching, building a soft-processor and Ethernet interface circuit using EDK

International Nuclear Information System (INIS)

Tuong Thi Thu Huong; Pham Ngoc Tuan; Truong Van Dat, Dang Lanh; Chau Thi Nhu Quynh

2014-01-01

The processor is an indispensable component in the measurement and automatic control systems. This report describes the fabrication of a soft-processor (32-bits, on-chip block RAM 64K, 50M clock, internal and peripheral bus) for receiving, sending and processing of data Ethernet packets. This processor is fabricated using the XPS component from EDK (Xilinx) software toolkit. After that, it is configured on the FPGA named Spartan XC3S500E circuit. A firmware of a processor for controlling the interface between processor and Ethernet port is written in C language and can play a role of a HOST (station) which has its own IP to connect to Ethernet network. Besides, there are some needed parts as follows: an Ethernet interfacing controller chip, a suitable cable providing a speed up to 100 Mbs and an application program running under Window XP environment written in LabView to communicate with soft-processor. (author)

A high-accuracy optical linear algebra processor for finite element applications

Science.gov (United States)

Casasent, D.; Taylor, B. K.

1984-01-01

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

Monitoring and Tracking the LHC Beam Spot within the ATLAS High Level Trigger

CERN Document Server

Winklmeier, F; The ATLAS collaboration

2012-01-01

The parameters of the beam spot produced by the LHC in the ATLAS interaction region are computed online using the ATLAS High Level Trigger (HLT) system. The high rate of triggered events is exploited to make precise measurements of the position, size and orientation of the luminous region in near real-time, as these parameters change significantly even during a single data-taking run. We present the challenges, solutions and results for the online determination, monitoring and beam spot feedback system in ATLAS. A specially designed algorithm, which uses tracks registered in the silicon detectors to reconstruct event vertices, is executed on the HLT processor farm of several thousand CPU cores. Monitoring histograms from all the cores are sampled and aggregated across the farm every 60 seconds. The reconstructed beam values are corrected for detector resolution effects, measured in situ from the separation of vertices whose tracks have been split into two collections. Furthermore, measurements for individual ...

The CDF II eXtremely fast tracker upgrade

Energy Technology Data Exchange (ETDEWEB)

Abulencia, A.; Azzurri, P.; Cochran, E.; Dittmann, J.; Donati, S.; Efron, J.; Erbacher, R.; Errede, D.; Fedorko, I.; Flanagan, G.; Forrest, R.; /Illinois U., Urbana

2006-09-01

The CDF II Extremely Fast Tracker is the trigger track processor which reconstructs charged particle tracks in the transverse plane of the CDF II central outer tracking chamber. The system is now being upgraded to perform a three dimensional track reconstruction. A review of the upgrade is presented here.

Low voltage 80 KV to 125 KV electron processors

International Nuclear Information System (INIS)

Lauppi, U.V.

1999-01-01

The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

Science.gov (United States)

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Satellite on-board real-time SAR processor prototype

Science.gov (United States)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

Particle simulation on a distributed memory highly parallel processor

International Nuclear Information System (INIS)

Sato, Hiroyuki; Ikesaka, Morio

1990-01-01

This paper describes parallel molecular dynamics simulation of atoms governed by local force interaction. The space in the model is divided into cubic subspaces and mapped to the processor array of the CAP-256, a distributed memory, highly parallel processor developed at Fujitsu Labs. We developed a new technique to avoid redundant calculation of forces between atoms in different processors. Experiments showed the communication overhead was less than 5%, and the idle time due to load imbalance was less than 11% for two model problems which contain 11,532 and 46,128 argon atoms. From the software simulation, the CAP-II which is under development is estimated to be about 45 times faster than CAP-256 and will be able to run the same problem about 40 times faster than Fujitsu's M-380 mainframe when 256 processors are used. (author)

Code compression for VLIW embedded processors

Science.gov (United States)

Piccinelli, Emiliano; Sannino, Roberto

2004-04-01

The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

Recursive Matrix Inverse Update On An Optical Processor

Science.gov (United States)

Casasent, David P.; Baranoski, Edward J.

1988-02-01

A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.

Evaluation of the Intel Nehalem-EX server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2010-01-01

In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

Graphical user interface for TOUGH/TOUGH2 - development of database, pre-processor, and post-processor

Energy Technology Data Exchange (ETDEWEB)

Sato, Tatsuya; Okabe, Takashi; Osato, Kazumi [Geothermal Energy Research and Development Co., Ltd., Tokyo (Japan)

1995-03-01

One of the advantages of the TOUGH/TOUGH2 (Pruess, 1987 and 1991) is the modeling using {open_quotes}free shape{close_quotes} polygonal blocks. However, the treatment of three-dimensional information, particularly for TOUGH/TOUGH2 is not easy because of the {open_quotes}free shape{close_quotes} polygonal blocks. Therefore, we have developed a database named {open_quotes}GEOBASE{close_quotes} and a pre/post-processor named {open_quotes}GEOGRAPH{close_quotes} for TOUGH/TOUGH2 on engineering work station (EWS). {open_quotes}GEOGRAPH{close_quotes} is based on the ORACLE{sup *1} relational database manager system to access data sets of surface exploration (geology, geophysics, geochemistry, etc.), drilling (well trajectory, geological column, logging, etc.), well testing (production test, injection test, interference test, tracer test, etc.) and production/injection history.{open_quotes}GEOGRAPH{close_quotes} consists of {open_quotes}Pre-processor{close_quotes} that can construct the three-dimensional free shape reservoir modeling by mouse operation on X-window and {open_quotes}Post-processor{close_quotes} that can display several kinds of two/three-dimensional maps and X-Y plots to compile data on {open_quotes}GEOBASE{close_quotes} and result of TOUGH/TOUGH2 calculation. This paper shows concept of the systems and examples of utilization.

TRIGGER

CERN Multimedia

W. Smith

2012-01-01

  Level-1 Trigger The Level-1 Trigger group is ready to deploy improvements to the L1 Trigger algorithms for 2012. These include new high-PT patterns for the RPC endcap, an improved CSC PT assignment, a new PT-matching algorithm for the Global Muon Trigger, and new calibrations for ECAL, HCAL, and the Regional Calorimeter Trigger. These should improve the efficiency, rate, and stability of the L1 Trigger. The L1 Trigger group also is migrating the online systems to SLC5. To make the data transfer from the Global Calorimeter Trigger to the Global Trigger more reliable and also to allow checking the data integrity online, a new optical link system has been developed by the GCT and GT groups and successfully tested at the CMS electronics integration facility in building 904. This new system is now undergoing further tests at Point 5 before being deployed for data-taking this year. New L1 trigger menus have recently been studied and proposed by Emmanuelle Perez and the L1 Detector Performance Group...

Triggered tremor sweet spots in Alaska

Science.gov (United States)

Gomberg, Joan; Prejean, Stephanie

2013-01-01

To better understand what controls fault slip along plate boundaries, we have exploited the abundance of seismic and geodetic data available from the richly varied tectonic environments composing Alaska. A search for tremor triggered by 11 large earthquakes throughout all of seismically monitored Alaska reveals two tremor “sweet spots”—regions where large-amplitude seismic waves repeatedly triggered tremor between 2006 and 2012. The two sweet spots locate in very different tectonic environments—one just trenchward and between the Aleutian islands of Unalaska and Akutan and the other in central mainland Alaska. The Unalaska/Akutan spot corroborates previous evidence that the region is ripe for tremor, perhaps because it is located where plate-interface frictional properties transition between stick-slip and stably sliding in both the dip direction and laterally. The mainland sweet spot coincides with a region of complex and uncertain plate interactions, and where no slow slip events or major crustal faults have been noted previously. Analyses showed that larger triggering wave amplitudes, and perhaps lower frequencies (tremor. However, neither the maximum amplitude in the time domain or in a particular frequency band, nor the geometric relationship of the wavefield to the tremor source faults alone ensures a high probability of triggering. Triggered tremor at the two sweet spots also does not occur during slow slip events visually detectable in GPS data, although slow slip below the detection threshold may have facilitated tremor triggering.

Biomass is beginning to threaten the wood-processors

International Nuclear Information System (INIS)

Beer, G.; Sobinkovic, B.

2004-01-01

In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors

Triggering of internal transport barrier in JET

Energy Technology Data Exchange (ETDEWEB)

Joffrin, E. [Association Euratom-CEA pour la Fusion, CEA Cadarache, St. Paul lez Durance (France); Gorini, G. [Istituto di Fisica del Plasma, EURATOM-ENEA-CNR Association, Milan (Italy); Challis, C.D. [Euratom/UKAEA Fusion Association, Culham Science Centre, Abingdon, Oxon (United Kingdom)] [and others

2002-08-01

Internal transport barriers (ITBs) can be produced in JET by the application of strong additional heating during the current rise phase of the plasma discharge. Using up to 3 MW of lower hybrid power to tailor the q-profile prior to the main heating phase, a large variety of q-profiles ranging from low positive to strong negative central shear have been obtained during the current rise (0.4 MA s{sup -1}). With negative central magnetic shear s=(r/q)(r/q), the analysis of ITB triggering reveals a correlation between the formation of the ITB and q{sub andmin;} reaching an integer value (q=2 or q=3). This observation is confirmed by the analysis of the Alfven cascades. The minimum power required to access regimes with ITBs is probably related to the transport and magnetohydrodynamic properties of integer magnetic surfaces. Laser ablation and shallow pellet injection have also been attempted in recent JET ITB triggering experiments. (author)

Reconfigurable signal processor designs for advanced digital array radar systems

Science.gov (United States)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

TRIGGER

CERN Multimedia

Wesley Smith

Level-1 Trigger Hardware and Software The production of the trigger hardware is now basically finished, and in time for the turn-on of the LHC. The last boards produced are the Trigger Concentrator Cards for the ECAL Endcaps (TCC-EE). After the recent installation of the four EE Dees, the TCC-EE prototypes were used for their commissioning. Production boards are arriving and are being tested continuously, with the last ones expected in November. The Regional Calorimeter Trigger hardware is fully integrated after installation of the last EE cables. Pattern tests from the HCAL up to the GCT have been performed successfully. The HCAL triggers are fully operational, including the connection of the HCAL-outer and forward-HCAL (HO/HF) technical triggers to the Global Trigger. The HCAL Trigger and Readout (HTR) board firmware has been updated to permit recording of the tower “feature bit” in the data. The Global Calorimeter Trigger hardware is installed, but some firmware developments are still n...

Parallel processor for fast event analysis

International Nuclear Information System (INIS)

Hensley, D.C.

1983-01-01

Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

Sensitivity to Regional Earthquake Triggering and Magnitude-Frequency Characteristics of Microseismicity Detected via Matched-Filter Analysis, Central Southern Alps, New Zealand

Science.gov (United States)

Boese, C. M.; Townend, J.; Chamberlain, C. J.; Warren-Smith, E.

2016-12-01

Microseismicity recorded since 2008 by the Southern Alps Microseismicity Borehole Array (SAMBA) and other predominantly short-period seismic networks deployed in the central Southern Alps, New Zealand, reveals distinctive patterns of triggering in response to regional seismicity (magnitudes larger than 5, epicentral distances of 100-500 km). Using matched-filter detection methods implemented in the EQcorrscan package (Chamberlain et al., in prep.), we analyze microseismicity occurring in several geographically distinct swarms in order to examine the responses of specific microearthquake sources to earthquakes of different sizes occurring at different distances and azimuths. The swarms exhibit complex responses to regional seismicity which reveal that microearthquake triggering in these cases involves a combination of extrinsic factors (related to the dynamic stresses produced by the regional earthquake) and intrinsic factors (controlled by the local state of stress and possibly by hydrogeological processes). We find also that the microearthquakes detected by individual templates have Gutenberg-Richter magnitude-frequency characteristics. Since the detected events, by design, have very similar hypocentres and focal mechanisms, the observed scaling pertains to a restricted set of fault planes.

Asymmetrical floating point array processors, their application to exploration and exploitation

Energy Technology Data Exchange (ETDEWEB)

Geriepy, B L

1983-01-01

An asymmetrical floating point array processor is a special-purpose scientific computer which operates under asymmetrical control of a host computer. Although an array processor can receive fixed point input and produce fixed point output, its primary mode of operation is floating point. The first generation of array processors was oriented towards time series information. The next generation of array processors has proved much more versatile and their applicability ranges from petroleum reservoir simulation to speech syntheses. Array processors are becoming commonplace in mining, the primary usage being construction of grids-by usual methods or by kriging. The Australian mining community is among the world's leaders in regard to computer-assisted exploration and exploitation systems. Part of this leadership role must be providing guidance to computer vendors in regard to current and future requirements.

On the effective parallel programming of multi-core processors

NARCIS (Netherlands)

Varbanescu, A.L.

2010-01-01

Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

Design studies for the Double Chooz trigger

Energy Technology Data Exchange (ETDEWEB)

Cucoanes, Andi Sebastian

2009-07-24

The main characteristic of the neutrino mixing effect is assumed to be the coupling between the flavor and the mass eigenstates. Three mixing angles ({theta}{sub 12}, {theta}{sub 23}, {theta}{sub 13}) are describing the magnitude of this effect. Still unknown, {theta}{sub 13} is considered very small, based on the measurement done by the CHOOZ experiment. A leading experiment will be Double Chooz, placed in the Ardennes region, on the same site as used by CHOOZ. The Double Chooz goal is the exploration of {proportional_to}80% from the currently allowed {theta}{sub 13} region, by searching the disappearance of reactor antineutrinos. Double Chooz will use two similar detectors, located at different distances from the reactor cores: a near one at {proportional_to}150 m where no oscillations are expected and a far one at 1.05 km distance, close to the first minimum of the survival probability function. The measurement foresees a precise comparison of neutrino rates and spectra between both detectors. The detection mechanism is based on the inverse {beta}-decay. The Double Chooz detectors have been designed to minimize the rate of random background. In a simplified view, two optically separated regions are considered. The target, filled with Gd-doped liquid scintillator, is the main antineutrino interaction volume. Surrounding the target, the inner veto region aims to tag the cosmogenic muon background which hits the detector. Both regions are viewed by photomultipliers. The Double Chooz trigger system has to be highly efficient for antineutrino events as well as for several types of background. The trigger analyzes discriminated signals from the central region and the inner veto photomultipliers. The trigger logic is fully programmable and can combine the input signals. The trigger conditions are based on the total energy released in event and on the PMT groups multiplicity. For redundancy, two independent trigger boards will be used for the central region, each of

Real-time digital filtering, event triggering, and tomographic reconstruction of JET soft x-ray data (abstract)

Science.gov (United States)

Edwards, A. W.; Blackler, K.; Gill, R. D.; van der Goot, E.; Holm, J.

1990-10-01

Based upon the experience gained with the present soft x-ray data acquisition system, new techniques are being developed which make extensive use of digital signal processors (DSPs). Digital filters make 13 further frequencies available in real time from the input sampling frequency of 200 kHz. In parallel, various algorithms running on further DSPs generate triggers in response to a range of events in the plasma. The sawtooth crash can be detected, for example, with a delay of only 50 μs from the onset of the collapse. The trigger processor interacts with the digital filter boards to ensure data of the appropriate frequency is recorded throughout a plasma discharge. An independent link is used to pass 780 and 24 Hz filtered data to a network of transputers. A full tomographic inversion and display of the 24 Hz data is carried out in real time using this 15 transputer array. The 780 Hz data are stored for immediate detailed playback following the pulse. Such a system could considerably improve the quality of present plasma diagnostic data which is, in general, sampled at one fixed frequency throughout a discharge. Further, it should provide valuable information towards designing diagnostic data acquisition systems for future long pulse operation machines when a high degree of real-time processing will be required, while retaining the ability to detect, record, and analyze events of interest within such long plasma discharges.

Benchmarking NWP Kernels on Multi- and Many-core Processors