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Sample records for voltage adder accelerator

  1. Proposed inductive voltage adder based accelerator concepts for the second axis of DARHT

    Energy Technology Data Exchange (ETDEWEB)

    Smith, D.L.; Johnson, D.L.; Boyes, J.D. [and others

    1997-06-01

    As participants in the Technology Options Study for the second axis of the Dual Axis Radiographic HydroTest (DARHT) facility located at Los Alamos National Laboratories, the authors have considered several accelerator concepts based on the Inductive Voltage Adder (IVA) technology that is being used successfully at Sandia on the SABRE and HERMES-III facilities. The challenging accelerator design requirements for the IVA approach include: {ge}12-MeV beam energy; {approximately}60-ns electrical pulse width; {le}40-kA electron beam current; {approximately}1-mm diameter e-beam; four pulses on the same axis or as close as possible to that axis; and an architecture that fits within the existing building envelope. To satisfy these requirements the IVA concepts take a modular approach. The basic idea is built upon a conservative design for eight ferromagnetically isolated 2-MV cavities that are driven by two 3 to 4-{Omega} water dielectric pulse forming lines (PFLs) synchronized with laser triggered gas switches. The 100-{Omega} vacuum magnetically insulated transmission line (MITL) would taper to a needle cathode that produces the electron beam(s). After considering many concepts the authors narrowed their study to the following options: (A) Four independent single pulse drivers powering four single pulse diodes; (B) Four series adders with interleaved cavities feeding a common MITL and diode; (C) Four stages of series PFLs, isolated from each other by triggered spark gap switches, with single-point feeds to a common adder, MITL, and diode; and (D) Isolated PFLs with multiple-feeds to a common adder using spark gap switches in combination with saturable magnetic cores to isolate the non-energized lines. The authors will discuss these options in greater detail identifying the challenges and risks associated with each.

  2. Excitation of voltage oscillations in an induction voltage adder

    Directory of Open Access Journals (Sweden)

    Nichelle Bruner

    2009-07-01

    Full Text Available The induction voltage adder is an accelerator architecture used in recent designs of pulsed-power driven x-ray radiographic systems such as Sandia National Laboratories’ Radiographic Integrated Test Stand (RITS, the Atomic Weapons Establishment’s planned Hydrus Facility, and the Naval Research Laboratory’s Mercury. Each of these designs relies on magnetic insulation to prevent electron loss across the anode-cathode gap in the vicinity of the adder as well as in the coaxial transmission line. Particle-in-cell simulations of the RITS adder and transmission line show that, as magnetic insulation is being established during a pulse, some electron loss occurs across the gap. Sufficient delay in the cavity pulse timings provides an opportunity for high-momentum electrons to deeply penetrate the cavities of the adder cells where they can excite radio-frequency resonances. These oscillations may be amplified in subsequent gaps, resulting in oscillations in the output power. The specific modes supported by the RITS-6 accelerator and details of the mechanism by which they are excited are presented in this paper.

  3. Inductive voltage adder (IVA) for submillimeter radius electron beam

    Energy Technology Data Exchange (ETDEWEB)

    Mazarakis, M.G.; Poukey, J.W.; Maenchen, J.E. [and others

    1996-12-31

    The authors have already demonstrated the utility of inductive voltage adder accelerators for production of small-size electron beams. In this approach, the inductive voltage adder drives a magnetically immersed foilless diode to produce high-energy (10--20 MeV), high-brightness pencil electron beams. This concept was first demonstrated with the successful experiments which converted the linear induction accelerator RADLAC II into an IVA fitted with a small 1-cm radius cathode magnetically immersed foilless diode (RADLAC II/SMILE). They present here first validations of extending this idea to mm-scale electron beams using the SABRE and HERMES-III inductive voltage adders as test beds. The SABRE experiments are already completed and have produced 30-kA, 9-MeV electron beams with envelope diameter of 1.5-mm FWHM. The HERMES-III experiments are currently underway.

  4. Reproducible and controllable induction voltage adder for scaled beam experiments

    Science.gov (United States)

    Sakai, Yasuo; Nakajima, Mitsuo; Horioka, Kazuhiko

    2016-08-01

    A reproducible and controllable induction adder was developed using solid-state switching devices and Finemet cores for scaled beam compression experiments. A gate controlled MOSFET circuit was developed for the controllable voltage driver. The MOSFET circuit drove the induction adder at low magnetization levels of the cores which enabled us to form reproducible modulation voltages with jitter less than 0.3 ns. Preliminary beam compression experiments indicated that the induction adder can improve the reproducibility of modulation voltages and advance the beam physics experiments.

  5. Inductive voltage adder advanced hydrodynamic radiographic technology demonstration

    Energy Technology Data Exchange (ETDEWEB)

    Mazarakis, M.G.; Poukey, J.W.; Maenchen; Rovang, D.C. [and others

    1997-04-01

    This paper presents the design, results, and analysis of a high-brightness electron beam technology demonstration experiment completed at Sandia National Laboratories, performed in collaboration with Los Alamos National Laboratory. The anticipated electron beam parameters were: 12 MeV, 35-40 kA, 0.5-mm rms radius, and 40-ns full width half maximum (FWHM) pulse duration. This beam, on an optimum thickness tantalum converter, should produce a very intense x-ray source of {approximately} 1.5-mm spot size and 1 kR dose @ 1 m. The accelerator utilized was SABRE, a pulsed inductive voltage adder, and the electron source was a magnetically immersed foilless electron diode. For these experiments, SABRE was modified to high-impedance negative-polarity operation. A new 100-ohm magnetically insulated transmission line cathode electrode was designed and constructed; the cavities were rotated 180{degrees} poloidally to invert the central electrode polarity to negative; and only one of the two pulse forming lines per cavity was energized. A twenty- to thirty-Tesla solenoidal magnet insulated the diode and contained the beam at its extremely small size. These experiments were designed to demonstrate high electron currents in submillimeter radius beams resulting in a high-brightness high-intensity flash x-ray source for high-resolution thick-object hydrodynamic radiography. The SABRE facility high-impedance performance was less than what was hoped. The modifications resulted in a lower amplitude (9 MV), narrower-than-anticipated triangular voltage pulse, which limited the dose to {approximately} 20% of the expected value. In addition, halo and ion-hose instabilities increased the electron beam spot size to > 1.5 mm. Subsequent, more detailed calculations explain these reduced output parameters. An accelerator designed (versus retrofit) for this purpose would provide the desired voltage and pulse shape.

  6. Inductive Voltage Adder Network Analysis and Model Simplification

    Science.gov (United States)

    2007-06-01

    ORGANIZATION NAME(S) AND ADDRESS(ES) Brookhaven National Laboratory Upton, NY 11973 USA 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING/ MONITORING ... Kicker Pulser for DARHT-II”, Proceedings of the 20th International LINAC Conference, pp. 509-511, 2000. [4] Wang, G. J. Caporaso, E. G. Cook...Modeling of an Inductive Adder Kicker Pulser for a Proton Radiography System”, Digest of Technical Papers, Pulsed Power Plasma Science, 2001. PPPS-2001

  7. Dragon-I injector based on the induction voltage adder technique

    Directory of Open Access Journals (Sweden)

    Zhang Kaizhi

    2006-08-01

    Full Text Available The Dragon-I injector based on the induction voltage adder technique is introduced. Twelve ferrite loaded induction cells are connected in a series through central conducting stalks to achieve a pulsed voltage higher than 3.5 MV across the diode. Electrons are extracted from the velvet emitter and guided through the anode pipe by the magnets placed inside the cathode and anode shrouds. Measurements at the exit of injector show that, with an electric field of 200  kV/cm near the velvet surface and suitable magnetic field distribution, an electron beam up to 2.8 kA can be obtained with a normalized emittance of 1040π   mm mrad, and energy spread of 2.1% (3σ around the central energy of 3.5 MeV.

  8. MOSFET-based high voltage double square-wave pulse generator with an inductive adder configuration

    Energy Technology Data Exchange (ETDEWEB)

    Zhao, Xin [State Key Laboratory of Electrical Insulation and Power Equipment, Xi' an Jiaotong University, Xi' an 710049 (China); Zhang, Qiaogen, E-mail: hvzhang@mail.xjtu.edu.cn [State Key Laboratory of Electrical Insulation and Power Equipment, Xi' an Jiaotong University, Xi' an 710049 (China); Long, Jinghua [College of Physics, Shenzhen University, Shenzhen 518060 (China); Lei, Yunfei; Liu, Jinyuan [Institute of Optoelectronics, Shenzhen University, Shenzhen 518060 (China)

    2015-09-01

    This paper presents a fast MOSFET-based solid-state pulse generator for high voltage double square-wave pulses. The generator consists mainly of an inductive adder system stacked of 20 solid-state modules. Each of the modules has 18 power MOSFETs in parallel, which are triggered by individual drive circuits; these drive circuits themselves are synchronously triggered by a signal from avalanche transistors. Our experiments demonstrate that the output pulses with amplitude of 8.1 kV and peak current of about 405 A are available at a load impedance of 20 Ω. The pulse has a double square-wave form with a rise and fall time of 40 ns and 26 ns, respectively and bottom flatness better than 12%. The interval time of the double square-wave pulses can be adjustable by varying the interval time of the trigger pulses.

  9. Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

    Directory of Open Access Journals (Sweden)

    Sudarshan Tiwari

    2012-05-01

    Full Text Available This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T logic circuits. Gate Diffusion Input (GDI technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T based full adder designs in term of delay, power and powerdelay product (PDP compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP.

  10. Low voltage electron beam accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Ochi, Masafumi [Iwasaki Electric Co., Ltd., Tokyo (Japan)

    2003-02-01

    Widely used electron accelerators in industries are the electron beams with acceleration voltage at 300 kV or less. The typical examples are shown on manufactures in Japan, equipment configuration, operation, determination of process parameters, and basic maintenance requirement of the electron beam processors. New electron beam processors with acceleration voltage around 100 kV were introduced maintaining the relatively high dose speed capability of around 10,000 kGy x mpm at production by ESI (Energy Science Inc. USA, Iwasaki Electric Group). The application field like printing and coating for packaging requires treating thickness of 30 micron or less. It does not require high voltage over 110 kV. Also recently developed is a miniature bulb type electron beam tube with energy less than 60 kV. The new application area for this new electron beam tube is being searched. The drive force of this technology to spread in the industries would be further development of new application, process and market as well as the price reduction of the equipment, upon which further acknowledgement and acceptance of the technology to societies and industries would entirely depend. (Y. Tanaka)

  11. A pulsed-power generator merging inductive voltage and current adders and its switch trigger application example.

    Science.gov (United States)

    Li, Lee; Yafeng, Ge; Heqin, Zhong; Bin, Yu; Longjun, Xie

    2013-07-01

    A pulsed-power generator using inductive adder technology is proposed for the case of a discharge gap. The merit of this generator is to merge the pulsed-voltage and pulsed-current adders via the dual secondary windings with special circuit. For the nonlinear impedance in any discharge gap, the standalone voltage-pulse and current-pulse can be outputted successively by this generator. The proposed generator is especially useful for the common resolution of implementing pulse discharge at less cost. As an application example, a compact trigger prototype was developed to compatibly use in the gas-insulated and vacuum switches. Experiments achieved good results that the triggered switches showed stable performance and long life. If the basic circuit of this proposed generator is regarded as a pulsed-generating unit, a certain number of such units connected in parallel can be expected to form a general device with generating greater breakdown-voltage and sustained-current pulses for discharge gaps.

  12. Design and analysis of 32 bit CMOS adder using sub-threshold voltage at deep submicron technology

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    Kaur Jaspreet

    2016-01-01

    Full Text Available FA is basic cell for arithmetic operation and lots of efforts have put to minimize power consumption and delay. This paper evaluates conventional CMOS adder, bridge style adders in sub-threshold region. Circuits are designed at 20 MHz and 50 MHz frequencies with VDD= 200 mv. All adder designs are simulated at 32 nm technology. In 1 bit and 32 bit conventional CMOS adder design, an efficient trade-off between delay and power is achieved. Experimental results show that 32 bit adder designs have significant improvements in delay and power delay product.

  13. Control of a large vacuum wave precursor on the SABRE voltage adder MITL and extraction ion diode

    Science.gov (United States)

    Cuneo, M. E.; Hanson, D. L.; Poukey, J. W.; Menge, P. R.; Savage, M. E.; Smith, J. R.; Bernard, M. A.

    SABRE is a ten-cavity magnetically insulated voltage adder (6MV, 300 kA) used to study ion beam production in high voltage extraction applied-B ion diodes. Observations indicate that the machine power initially propagates in a large-amplitude vacuum wave prior to electron emission. This vacuum wave 'precursor' has an important impact on the turn-on and impedance history of ion diodes. Some typical precursor characteristics are shown using transmission line, diode, and beam current and voltage data and are compared to TWOQUICK simulations. Two techniques are under investigation to control the precursor and its effects on diode performance. A plasma opening switch (POS) has been used to erode the precursor. Field enhancing inserts are also planned to decrease the macroscopic field required for electron emission from the cathode. This will limit the distance over which vacuum and insulated waves separate by propagation at different velocities. Experimental data from the POS technique and TWOQUICK simulations of the insert technique are presented and discussed.

  14. Experiments investigating the generation and transport of 10--12 MeV, 30-kA, mm-size electron beams with linear inductive voltage adders

    Energy Technology Data Exchange (ETDEWEB)

    Mazarakis, M.G.; Poukey, J.W.; Maenchen, J.E.

    1997-06-01

    The authors present the design, analysis, and results of the high-brightness electron beam experiments currently under investigation at Sandia National Laboratories. The anticipated beam parameters are the following: 8--12 MeV, 35--50 kA, 30--60 ns FWHM, and 0.5-mm rms beam radius. The accelerators utilized are SABRE and HERMES III. Both are linear inductive voltage adders modified to higher impedance and fitted with magnetically immersed foil less electron diodes. In the strong 20--50 Tesla solenoidal magnetic field of the diode, mm-size electron beams are generated and propagated to a beam stop. The electron beam is field emitted from mm-diameter needle-shaped cathode electrode and is contained in a similar size envelop by the strong magnetic field. These extremely space charge dominated beams provide the opportunity to study beam dynamics and possible instabilities in a unique parameter space. The SABRE experiments are already completed and have produced 30-kA, 1.5-mm FWHM electron beams, while the HERMES-III experiments are on-going.

  15. Scanning transmission electron microscopy imaging dynamics at low accelerating voltages

    Energy Technology Data Exchange (ETDEWEB)

    Lugg, N.R. [School of Physics, University of Melbourne, Parkville, Victoria 3010 (Australia); Findlay, S.D. [Institute of Engineering Innovation, The University of Tokyo, Tokyo 116-0013 (Japan); Shibata, N. [Institute of Engineering Innovation, The University of Tokyo, Tokyo 116-0013 (Japan); PRESTO, Japan Science and Technology Agency, Saitama 332-0012 (Japan); Mizoguchi, T. [Institute of Industrial Science, The University of Tokyo, Tokyo 153-8505 (Japan); D' Alfonso, A.J. [School of Physics, University of Melbourne, Parkville, Victoria 3010 (Australia); Allen, L.J., E-mail: lja@unimelb.edu.au [School of Physics, University of Melbourne, Parkville, Victoria 3010 (Australia); Ikuhara, Y. [Institute of Engineering Innovation, The University of Tokyo, Tokyo 116-0013 (Japan); Nanostructures Research Laboratory, Japan Fine Ceramic Center, Nagoya 456-8587 (Japan); WPI Advanced Institute for Materials Research, Tohoku University, Sendai 980-8577 (Japan)

    2011-07-15

    Motivated by the desire to minimize specimen damage in beam sensitive specimens, there has been a recent push toward using relatively low accelerating voltages (<100kV) in scanning transmission electron microscopy. To complement experimental efforts on this front, this paper seeks to explore the variations with accelerating voltage of the imaging dynamics, both of the channelling of the fast electron and of the inelastic interactions. High-angle annular-dark field, electron energy loss spectroscopic imaging and annular bright field imaging are all considered. -- Highlights: {yields} Both elastic and inelastic scattering in STEM are acceleration voltage dependent. {yields} HAADF, EELS and ABF imaging are assessed with a view to optimum imaging. {yields} Lower accelerating voltages improve STEM EELS contrast in very thin crystals. {yields} Higher accelerating voltages give better STEM EELS contrast in thicker crystals. {yields} At fixed resolution, higher accelerating voltage aids ABF imaging of light elements.

  16. High Voltage Operation of Helical Pulseline Structures for Ion Acceleration

    CERN Document Server

    Waldron, William; Reginato, Lou

    2005-01-01

    The basic concept for the acceleration of heavy ions using a helical pulseline requires the launching of a high voltage traveling wave with a waveform determined by the beam transport physics in order to maintain stability and acceleration.* This waveform is applied to the front of the helix, creating over the region of the ion bunch a constant axial acceleration electric field that travels down the line in synchronism with the ions. Several methods of driving the helix have been considered. Presently, the best method of generating the waveform and also maintaining the high voltage integrity appears to be a transformer primary loosely coupled to the front of the helix, generating the desired waveform and achieving a voltage step-up from primary to secondary (the helix). This can reduce the drive voltage that must be brought into the helix enclosure through the feedthroughs by factors of 5 or more. The accelerating gradient is limited by the voltage holding of the vacuum insulator, and the material and helix g...

  17. Carry Select Adder Circuit with A Successively Incremented Carry Number Block

    OpenAIRE

    Deepak; Bal Krishan

    2014-01-01

    This paper reports a conditional carry select (CCS) adder circuit with a successively-incremented-carry-number block (SICNB) structure for low-voltage VLSI implementation. Owing to the successively-incremented-carry-number block (SICNB) structure, the new 16-bit SICNB CCS adder provides a 37% faster speed as compared to the conventional conditional Carry select adder based on the SPICE results

  18. Voltage holding optimization of the MITICA electrostatic accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Pilan, N., E-mail: nicola.pilan@igi.cnr.it [Consorzio RFX, Associazione EURATOM-ENEA sulla Fusione, Corso Stati Uniti 4, I-35127 Padova (Italy); Bettini, P. [Consorzio RFX, Associazione EURATOM-ENEA sulla Fusione, Corso Stati Uniti 4, I-35127 Padova (Italy); DII, Università di Padova, v. Gradenigo 6/A, I-35131 Padova (Italy); De Lorenzi, A. [Consorzio RFX, Associazione EURATOM-ENEA sulla Fusione, Corso Stati Uniti 4, I-35127 Padova (Italy); Specogna, R. [DIEGM, Università di Udine, v. delle Scienze 208, I-33100 Udine (Italy)

    2013-10-15

    Highlights: ► A set of electrostatic analyses of the region surrounding the MITICA electrostatic accelerator has been carried out. ► The distribution of the breakdown probability of the system has been calculated. ► The analyses have allowed identifying the weak point of the system to address the future design optimizations. -- Abstract: Two Heating Neutral Beam Injectors (H-NBI) are planned to be installed in ITER with a total delivered heating power of 33 MW [1]. The main parameters are: 870 kV acceleration voltage with 46 A beam current for hydrogen beam, and 1 MV voltage with 40 A current for deuterium beam. The voltage holding in the 1 MV ITER Neutral Beam Accelerator is recognized to be one of the most critical issues for long pulse (3600 s) beam operation, due to the complex electrostatic structure formed by electrodes polarized at different potentials immersed in vacuum or low-pressure gas. As a matter of fact, the system shall work in a p × d range at the left of the Paschen curve where the classical Townsend breakdown criterion is no longer valid. The voltage holding is governed by the mechanism of the long gap insulation in high vacuum, not yet well consolidated from the physical point of view. This paper is aimed to describe the optimization of the voltage holding capability for MITICA electrostatic accelerator. The results of this analysis will constitute the input for the probabilistic model [3] which is adopted to predict the breakdown probability by means of 2D analyses of the multi electrode – multi voltage system.

  19. How the Inductive Voltage Adder (IVA) output impedance affects impedance dynamics of a Self-Magnetic Pinch (SMP) diode

    Science.gov (United States)

    Renk, Timothy; Simpson, Sean; Webb, Timothy; Mazarakis, Michael; Kiefer, Mark

    2016-10-01

    The SMP diode, fielded on the RITS-6 (3.5-8.5 MV) IVA accelerator at Sandia National Laboratories, produces a focused electron beam (IVA flow impedance has on ZDIODE. A preliminary conclusion is that ZDIODE should be at least 1.5 times the flow impedance before ZDIODE is a parameter independent of flow impedance. This has implications for SMP as a load for a IVA, since ZDIODE >100 ohms has not been consistently demonstrated. Data analysis is ongoing, and latest results will be reported. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

  20. Efficient adders for assistive devices

    Directory of Open Access Journals (Sweden)

    Mansi Jhamb

    2017-02-01

    Full Text Available The Body sensor network [IEEE 802.15] is a wireless communication network consisting of assistive devices which are of prime importance in medical applications. The delay critical and power hungry blocks in these assistive devices are designed so that they consume less power, have low latency and require a lesser area on chip. In this paper, we present a qualitative as well as a quantitative analysis of an asynchronous pipelined adder design with two latest computation completion sensing approaches based on Pseudo NMOS logic and other based on C-element. The Pseudo NMOS based completion sensing approach provides a maximum improvement of 76.92% in critical path delay at supply voltage of 1.2 V and the maximum drop in power dissipation has been observed at a supply voltage of 1.1 V which is 85.60% as compared to C-element based completion sensing approach. Even at low voltages such as 0.8 V, there is a significant improvement in speed and power which is 75.64% and 74.79% respectively. Since the adder is the most widely used component in all present day assistive devices, this analysis acts as a pointer for the application of asynchronous pipelined circuits with efficient Pseudo NMOS based completion sensing approach in low voltage/low power rehabilitative devices.

  1. Voltage stress effects on microcircuit accelerated life test failure rates

    Science.gov (United States)

    Johnson, G. M.

    1976-01-01

    The applicability of Arrhenius and Eyring reaction rate models for describing microcircuit aging characteristics as a function of junction temperature and applied voltage was evaluated. The results of a matrix of accelerated life tests with a single metal oxide semiconductor microcircuit operated at six different combinations of temperature and voltage were used to evaluate the models. A total of 450 devices from two different lots were tested at ambient temperatures between 200 C and 250 C and applied voltages between 5 Vdc and 15 Vdc. A statistical analysis of the surface related failure data resulted in bimodal failure distributions comprising two lognormal distributions; a 'freak' distribution observed early in time, and a 'main' distribution observed later in time. The Arrhenius model was shown to provide a good description of device aging as a function of temperature at a fixed voltage. The Eyring model also appeared to provide a reasonable description of main distribution device aging as a function of temperature and voltage. Circuit diagrams are shown.

  2. GDI based full adders for energy efficient arithmetic applications

    Directory of Open Access Journals (Sweden)

    Mohan Shoba

    2016-03-01

    Full Text Available Addition is a vital arithmetic operation and acts as a building block for synthesizing all other operations. A high-performance adder is one of the key components in the design of application specific integrated circuits. In this paper, three low power full adders are designed with full swing AND, OR and XOR gates to alleviate threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed designs is compared with the other full adder designs, namely CMOS, CPL, hybrid and GDI through SPICE simulations using 45 nm technology models. Simulation results reveal that proposed designs have lower energy consumption among all the conventional designs taken for comparison.

  3. On fast carry select adders

    Science.gov (United States)

    Shamanna, M.; Whitaker, S.

    1992-01-01

    This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme has the same transistor count, without suffering any performance degradation, compared to the Manchester carry chain adder.

  4. On fast carry select adders

    Science.gov (United States)

    Shamanna, M.; Whitaker, S.

    This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme has the same transistor count, without suffering any performance degradation, compared to the Manchester carry chain adder.

  5. Current-voltage relationship in the auroral particle acceleration region

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    M. Morooka

    2004-11-01

    Full Text Available The current-voltage relationship in the auroral particle acceleration region has been studied statistically by the Akebono (EXOS-D satellite in terms of the charge carriers of the upward field-aligned current. The Akebono satellite often observed field-aligned currents which were significantly larger than the model value predicted by Knight (1973. We compared the upward field-aligned current estimated by three different methods, and found that low-energy electrons often play an important role as additional current carriers, together with the high-energy primary electrons which are expected from Knight's relation. Such additional currents have been observed especially at high and middle altitudes of the particle acceleration region. Some particular features of electron distribution functions, such as "cylindrical distribution functions" and "electron conics", have often been observed coinciding with the additional currents. They indicated time variability of the particle acceleration region. Therefore, we have concluded that the low-energy electrons within the "forbidden" region of electron phase space in the stationary model often contribute to charge carriers of the current because of the rapid time variability of the particle acceleration region. "Cylindrical distribution functions" are expected to be found below the time-varying potential difference. We statistically examined the locations of "cylindrical distribution function", and found that their altitudes are related to the location where the additional currents have been observed. This result is consistent with the idea that the low-energy electrons can also carry significant current when the acceleration region changes in time.

  6. The Forbidden Quantum Adder

    Science.gov (United States)

    Alvarez-Rodriguez, U.; Sanz, M.; Lamata, L.; Solano, E.

    2015-01-01

    Quantum information provides fundamentally different computational resources than classical information. We prove that there is no unitary protocol able to add unknown quantum states belonging to different Hilbert spaces. This is an inherent restriction of quantum physics that is related to the impossibility of copying an arbitrary quantum state, i.e., the no-cloning theorem. Moreover, we demonstrate that a quantum adder, in absence of an ancillary system, is also forbidden for a known orthonormal basis. This allows us to propose an approximate quantum adder that could be implemented in the lab. Finally, we discuss the distinct character of the forbidden quantum adder for quantum states and the allowed quantum adder for density matrices. PMID:26153134

  7. Carry Select Adder Circuit with A Successively Incremented Carry Number Block

    Directory of Open Access Journals (Sweden)

    Deepak

    2014-04-01

    Full Text Available This paper reports a conditional carry select (CCS adder circuit with a successively-incremented-carry-number block (SICNB structure for low-voltage VLSI implementation. Owing to the successively-incremented-carry-number block (SICNB structure, the new 16-bit SICNB CCS adder provides a 37% faster speed as compared to the conventional conditional Carry select adder based on the SPICE results

  8. Design of High Speed 128 bit Parallel Prefix Adders

    OpenAIRE

    T.KIRAN KUMAR; Srikanth, P

    2014-01-01

    In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel pref...

  9. The Forbidden Quantum Adder

    CERN Document Server

    Alvarez-Rodriguez, U; Lamata, L; Solano, E

    2014-01-01

    Addition plays a central role in mathematics and physics, while adders are ubiquitous devices in computation and electronics. In this sense, usual sum operations can be realized by classical Turing machines and also, with a suitable algorithm, by quantum Turing machines. Moreover, the sum of state vectors in the same Hilbert space, known as quantum superposition, is at the core of quantum physics. In fact, entanglement and the promised exponential speed-up of quantum computing are based on such superpositions. Here, we consider the existence of a quantum adder, defined as a unitary operation mapping two unknown quantum states encoded in different quantum systems onto their sum codified in a single one. The surprising answer is that this quantum adder is forbidden and it has the quantum cloning machine as a special case. This no-go result is of fundamental nature and its deep implications should be further studied.

  10. High Speed Boosted Cmos Differential Logic for Ripple Carry Adders

    Directory of Open Access Journals (Sweden)

    Meenu Roy,

    2014-01-01

    Full Text Available This paper describes a high speed boosted CMOS differential logic which is applicable in Ripple Carry Adders. The proposed logic operating with supply voltage approaching the MOS threshold voltage. The logic style improves switching speed by boosting the gate-source voltage of transistors along timing critical signal path. It allows a single boosting circuit to be shared by complementary outputs as a result the area overhead also minimizes. As compared to the conventional logic gates the EDP (energy delay product is improved. The test sets of logic gates and adders where designed in tsmc0.18μm of Mentor Graphics EDA tool. The experimental result for Ripple Carry Adders using the proposed logic style revealed that the addition time is reduced as compared with the conventional CMOS circuits.

  11. Two novel low-power and high-speed dynamic carbon nanotube full-adder cells

    Directory of Open Access Journals (Sweden)

    Eshghi Mohammad

    2011-01-01

    Full Text Available Abstract In this paper, two novel low-power and high-speed carbon nanotube full-adder cells in dynamic logic style are presented. Carbon nanotube field-effect transistors (CNFETs are efficient in designing a high performance circuit. To design our full-adder cells, CNFETs with three different threshold voltages (low threshold, normal threshold, and high threshold are used. First design generates SUM and COUT through separate transistors, and second design is a multi-output dynamic full adder. Proposed full adders are simulated using HSPICE based on CNFET model with 0.9 V supply voltages. Simulation result shows that the proposed designs consume less power and have low power-delay product compared to other CNFET-based full-adder cells.

  12. Two novel low-power and high-speed dynamic carbon nanotube full-adder cells.

    Science.gov (United States)

    Bagherizadeh, Mehdi; Eshghi, Mohammad

    2011-09-02

    In this paper, two novel low-power and high-speed carbon nanotube full-adder cells in dynamic logic style are presented. Carbon nanotube field-effect transistors (CNFETs) are efficient in designing a high performance circuit. To design our full-adder cells, CNFETs with three different threshold voltages (low threshold, normal threshold, and high threshold) are used. First design generates SUM and COUT through separate transistors, and second design is a multi-output dynamic full adder. Proposed full adders are simulated using HSPICE based on CNFET model with 0.9 V supply voltages. Simulation result shows that the proposed designs consume less power and have low power-delay product compared to other CNFET-based full-adder cells.

  13. Influence of acceleration voltage on scanning electron microscopy of human blood platelets.

    Science.gov (United States)

    Pretorius, E

    2010-03-01

    Scanning electron microscopy (SEM) is used to view a variety of surface structures, molecules, or nanoparticles of different materials, ranging from metals, dental and medical instruments, and chemistry (e.g. polymer analysis) to biological material. Traditionally, the operating conditions of the SEM are very important in the material sciences, particularly the acceleration voltage. However, in biological sciences, it is not typically seen as an important parameter. Acceleration voltage allows electrons to penetrate the sample; thus, the higher the acceleration voltage the more penetration into the sample will occur. As a result, ultrastructural information from deeper layers will interfere with the actual surface morphology that is seen. Therefore, ultimately, if acceleration voltage is lower, a better quality of the surface molecules and structures will be produced. However, in biological sciences, this is an area that is not well-documented. Typically, acceleration voltages of between 5 and 20 kV are used. This manuscript investigates the influence of acceleration voltages ranging from 5 kV to as low as 300 V, by studying surface ultrastructure of a human platelet aggregate. It is concluded that, especially at higher magnifications, much more surface detail is visible in biological samples when using an acceleration voltage between 2 kV and 300 V.

  14. Design of a High Speed Adder

    OpenAIRE

    Aritra Mitra; Amit Bakshi; Bhavesh Sharma; Nilesh Didwania

    2015-01-01

    In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are ...

  15. Comparative Design of 16-Bit Sparse-Tree Rsfq Adder

    OpenAIRE

    S. Saddam Hussain; S. Mahaboob Basha

    2014-01-01

    In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and ar...

  16. Voltage holding study of 1 MeV accelerator for ITER neutral beam injector.

    Science.gov (United States)

    Taniguchi, M; Kashiwagi, M; Umeda, N; Dairaku, M; Takemoto, J; Tobari, H; Tsuchida, K; Yamanaka, H; Watanabe, K; Kojima, A; Hanada, M; Sakamoto, K; Inoue, T

    2012-02-01

    Voltage holding test on MeV accelerator indicated that sustainable voltage was a half of that of ideal quasi-Rogowski electrode. It was suggested that the emission of the clumps is enhanced by a local electric field concentration, which leads to discharge initiation at lower voltage. To reduce the electric field concentration in the MeV accelerator, gaps between the grid supports were expanded and curvature radii at the support corners were increased. After the modifications, the accelerator succeeded in sustaining -1 MV in vacuum without beam acceleration. However, the beam energy was still limited at a level of 900 keV with a beam current density of 150 A∕m(2) (346 mA) where the 3 × 5 apertures were used. Measurement of the beam profile revealed that deflection of the H(-) ions was large and a part of the H(-) ions was intercepted at the acceleration grid. This causes high heat load on the grids and the breakdowns during beam acceleration. To suppress the direct interception, new grid system was designed with proper aperture displacement based on a 3D beam trajectory analysis. As the result, the beam deflection was compensated and the voltage holding during the beam acceleration was improved. Beam parameter of the MeV accelerator was increased to 980 keV, 185 A∕m(2) (427 mA), which is close to the requirement of ITER accelerator (1 MeV, 200 A∕m(2)).

  17. Area, Delay and Power Comparison of Adder Topologies

    OpenAIRE

    R.Uma; Vidya Vijayan; M. Mohanapriya; Sharon Paul

    2012-01-01

    Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, ca...

  18. Area, Delay and Power Comparison of Adder Topologies

    OpenAIRE

    R.UMA,Vidya Vijayan; M. Mohanapriya; Sharon Paul

    2012-01-01

    Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the trade off between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry look ahead adder, carry skip adder, carry select adder, carry increment adder, ...

  19. Design of an energy-efficient CNFET Full Adder Cell

    Directory of Open Access Journals (Sweden)

    Arezoo Taeb

    2012-05-01

    Full Text Available In this paper by using the carbon nanotube field effect transistor (CNFET, which is a promising alternative for the MOSFET transistor, two novel energy-efficient Full Adders are proposed. The proposed Full Adders show full swing logic and strong output drivability. The first design uses eight transistors and nine capacitors and the second design utilizes three capacitors less than the first design. Simulations, carried out using HSPICE based on the Stanford University CNFET model at 0.6V and 0.9V supply voltages, demonstrate the efficiency of type proposed circuit parameters such as delay, power and power-delay product.

  20. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  1. Comparative Design of 16-Bit Sparse-Tree Rsfq Adder

    Directory of Open Access Journals (Sweden)

    S. Saddam Hussain

    2014-06-01

    Full Text Available In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam, kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders, and carry lookahead adders(area consuming adders are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area and delay values.

  2. Nicotiana Occidentalis Chloroplast Ultrastructure imaged with Transmission Electron Microscopes Working at Different Accelerating Voltages

    OpenAIRE

    SVIDENSKÁ, Silvie

    2010-01-01

    The main goal of this thesis is to study and compare electron microscopy images of Nicotiana Occidentalis chloroplasts, obtained from two types of transmission electron microscopes,which work with different accelerating voltage of 80kV and 5kV. The two instruments, TEM JEOL 1010 and low voltage electron microscope LVEM5 are employed for experiments. In the first theoretical part, principle of electron microscopy and chloroplast morphology is described. In experimental part, electron microscop...

  3. Study and Evaluation in CMOS Full Adders

    Institute of Scientific and Technical Information of China (English)

    陈国章; 陈昊; 何丕廉

    2003-01-01

    Low power adder circuits, SERF, 10T-Ⅰ,10T-Ⅱ,10T-Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.

  4. High-Voltage Terminal Test of Test Stand for 1-MV Electrostatic Accelerator

    CERN Document Server

    Park, Sae-Hoon

    2015-01-01

    The Korea Multipurpose Accelerator Complex (KOMAC) has been developing a 300-kV test stand for a 1-MV electrostatic accelerator ion source. The ion source and accelerating tube will be installed in a high-pressure vessel. The ion source in the high-pressure vessel is required to have a high reliability. The test stand has been proposed and developed to confirm the stable operating conditions of the ion source. The ion source will be tested at the test stand to verify the long-time operating conditions. The test stand comprises a 300-kV high-voltage terminal, a battery for the ion-source power, a 60-Hz inverter, 200-MHz RF power, a 5-kV extraction power supply, a 300-kV accelerating tube, and a vacuum system. The results of the 300-kV high-voltage terminal tests are presented in this paper.

  5. Design of a high DC voltage generator and D-T fuser based on particle accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Araujo, Wagner L.; Campos, Tarcisio P.R., E-mail: wagnerleite@ufmg.b, E-mail: campos@nuclear.ufmg.b [Universidade Federal de Minas Gerais (DEN/ UFMG), Belo Horizonte, MG (Brazil). Dept. de Engenharia Nuclear

    2011-07-01

    This paper approaches a design and simulation of a high voltage Cockcroft Walton multiplier and a compact size deuteron accelerator addressed in neutron generation by d-t fusion. We proposed a circuit arrangement, which was led to simulations. The particle accelerator was computer-generated providing particle transport and electric potential analysis. As results, the simulated voltage multiplier achieved 119 kV, and the accelerator presented a deuteron beam current up to 15 mA, achieving energies in order to 100 keV. In conclusion, the simulation motivates experimental essays in order to investigate the viability of a deuteron accelerator powered by a Cockcroft-Walton source. Such d-t fusor shall produce an interesting ion beam profile, reaching energy values near the d-t fusion cross section peak. (author)

  6. Towards Physarum binary adders.

    Science.gov (United States)

    Jones, Jeff; Adamatzky, Andrew

    2010-07-01

    Plasmodium of Physarum polycephalum is a single cell visible by unaided eye. The plasmodium's foraging behaviour is interpreted in terms of computation. Input data is a configuration of nutrients, result of computation is a network of plasmodium's cytoplasmic tubes spanning sources of nutrients. Tsuda et al. (2004) experimentally demonstrated that basic logical gates can be implemented in foraging behaviour of the plasmodium. We simplify the original designs of the gates and show - in computer models - that the plasmodium is capable for computation of two-input two-output gate x, y-->xy, x+y and three-input two-output x,y,z-->x yz,x+y+z. We assemble the gates in a binary one-bit adder and demonstrate validity of the design using computer simulation.

  7. Towards Physarum Binary Adders

    CERN Document Server

    Jones, Jeff; 10.1016/j.biosystems.2010.04.005

    2010-01-01

    Plasmodium of \\emph{Physarum polycephalum} is a single cell visible by unaided eye. The plasmodium's foraging behaviour is interpreted in terms of computation. Input data is a configuration of nutrients, result of computation is a network of plasmodium's cytoplasmic tubes spanning sources of nutrients. Tsuda et al (2004) experimentally demonstrated that basic logical gates can be implemented in foraging behaviour of the plasmodium. We simplify the original designs of the gates and show --- in computer models --- that the plasmodium is capable for computation of two-input two-output gate $ \\to $ and three-input two-output $ \\to $. We assemble the gates in a binary one-bit adder and demonstrate validity of the design using computer simulation.

  8. Virtual gap dielectric wall accelerator

    Science.gov (United States)

    Caporaso, George James; Chen, Yu-Jiuan; Nelson, Scott; Sullivan, Jim; Hawkins, Steven A

    2013-11-05

    A virtual, moving accelerating gap is formed along an insulating tube in a dielectric wall accelerator (DWA) by locally controlling the conductivity of the tube. Localized voltage concentration is thus achieved by sequential activation of a variable resistive tube or stalk down the axis of an inductive voltage adder, producing a "virtual" traveling wave along the tube. The tube conductivity can be controlled at a desired location, which can be moved at a desired rate, by light illumination, or by photoconductive switches, or by other means. As a result, an impressed voltage along the tube appears predominantly over a local region, the virtual gap. By making the length of the tube large in comparison to the virtual gap length, the effective gain of the accelerator can be made very large.

  9. Experimental research on the feature of Talbot-Lau interferometer vs. tube accelerating voltage

    CERN Document Server

    Wang, Shenghao; Wang, Zhili; Gao, Kun; Zhang, Kai; Momose, Atsushi; Wu, Ziyu

    2014-01-01

    Talbot-Lau interferometer has been used most widely to perform X-ray phase-contrast imaging with a conventional low-brilliance X-ray source, it yields high-sensitivity phase and dark-field images of sample producing low absorption contrast, thus bearing tremendous potential for future clinical diagnosis. In this manuscript, while changing accelerating voltage of the X-ray tube from 35KV to 45KV, X-ray phase-contrast imaging of a test sample were performed at each integer KV position to investigate the characteristic of a Talbot-Lau interferometer (located in the Institute of Multidisciplinary Research for Advanced Materials, Tohoku University, Japan.) vs. tube voltage. Experimental results and data analysis show that this Talbot-Lau interferometer is insensitive to the tube accelerating voltage within a certain range, fringe visibility around 44% is maintained in the aforementioned tube voltage range. This experimental research is of guiding significance for choosing optimal tube accelerating voltage with thi...

  10. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    Science.gov (United States)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  11. Design and Implementation of High Speed Carry Select Adder

    OpenAIRE

    B. Gopinath; N Sangeetha; S.Jenifer nancy; T.Umarani

    2015-01-01

    In electronic adder is a digital circuit that performs addition of numbers. Adders can be constructed for many numerical representations such as arithmetic and logical operation. The most adders operates on binary numbers. Among the different types of adders, carry select adder is a one of the fastest adder.The gate level modification is to reduce the power and area of carry select adder by using the concept of Arithmetic Logic Unit (ALU). In this paper , different techniques such as Binary T...

  12. Implementation of Binary Coded Decimal Digit Adders and Multipliers on Fpga Platform

    Directory of Open Access Journals (Sweden)

    Prof. R. P. Sarnaik

    2014-04-01

    Full Text Available Binary-coded decimal (BCD is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits. The main problem in existing decimal adders is the need of correction circuit as the result is in binary form which increases delay & area. In this paper, we propose a high speed BCD adder and multiplier without need of correction circuit. The Decimal carry-save adders (CSAs are used to design BCD digit adders which consist less area, low power and high speed performance. BCD Multiplier is design using Wallace Tree Architecture, explaining the use of half and full adders for addition of intermediate product terms obtained after the multiplication of two nibbles (4 bits.In this paper, correction free BCD Adder is efficient one. FPGAs provide an efficient hardware platform that can be employed for accelerating decimal algorithms. These designs are described and simulated using VHDL hardware description language Modelsim Simulator SE 6.3f. BCD Adders & BCD Multipliers are synthesized with the help of Altera Quartus II 9.1 sp2. Implementation results and comparison with existing designs are provided.

  13. [Compartment syndrome following adder bites].

    Science.gov (United States)

    Roed, Casper; Bayer, Lasse; Lebech, Anne-Mette Kjaer; Poulsen, Jesper Brøndum; Katzenstein, Terese

    2009-01-26

    Bites from the adder, Vipera Berus, can have serious clinical consequences due to systemic effects. Meanwhile, the local swelling calls for attention as well. Two cases of seven- and eleven-year-old boys are reported. The first patient was bitten in the 5th toe, the second in the thumb. Both developed fasciotomy-requiring compartment syndrome of the lower and upper limb, respectively. Recognition of this most seldom complication of an adder bite is vital to save the limb. We recommend that the classical signs and symptoms of compartment syndrome serve as indication for surgery. However, compartment pressure measurement can be helpful in the assessment of children.

  14. Timing-Driven-Testable Convergent Tree Adders

    Directory of Open Access Journals (Sweden)

    Johnnie A. Huang

    2002-01-01

    Full Text Available Carry lookahead adders have been, over the years, implemented in complex arithmetic units due to their regular structure which leads to efficient VLSI implementation for fast adders. In this paper, timing-driven testability synthesis is first performed on a tree adder. It is shown that the structure of the tree adder provides for a high fanout with an imbalanced tree structure, which likely contributes to a racing effect and increases the delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder, the optimization produces a 6.37%increase in speed of the critical path while only contributing a 2.16% area overhead. The full testability of the circuit is achieved in the optimized adder design.

  15. New half-voltage and double phase operation of the Hermes III linear induction accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Mikkelson, K.A.; Westfall, R.L.; Harper-Slaboszewicz, V.J. (Sandia National Labs., Albuquerque, NM (United States)); Neely, S.M. (K-Tech Corp., Albuquerque, NM (United States))

    1991-01-01

    The standard operating mode produces bremsstrahlung with an endpoint energy of about 18 MeV. This paper describes a new mode with a 8.5 MeV endpoint energy and the same standard mode pulse characteristics achieved by operating only half of the accelerator at full charge with the advantage of minimal setup time. An extension of the new half-voltage mode is to use the other half of the accelerator for delivering a second pulse at a later time with the same technique. The double pulse mode is ideal for beam generation which requires a long interpulse time in the millisecond regime. The beam characteristics of the two half-voltage pulses are nearly identical with the nominal radiation pulse full width at half maximum of 21 ns and 10--90 risetime of 11 ns recorded by the same Compton diode radiation monitors on instruments triggered 30 ms apart.

  16. Power supply design for the filament of the high-voltage electron accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Lige; Yang, Lei; Yang, Jun, E-mail: jyang@mail.hust.edu.cn; Huang, Jiang; Liu, Kaifeng; Zuo, Chen

    2015-12-21

    The filament is a key component for the electron emission in the high-voltage electron accelerator. In order to guarantee the stability of the beam intensity and ensure the proper functioning for the power supply in the airtight steel barrel, an efficient filament power supply under accurate control is required. The paper, based on the dual-switch forward converter and synchronous rectification technology, puts forward a prototype of power supply design for the filament of the high-voltage accelerator. The simulation is conducted with MATLAB-Simulink on the main topology and the control method. Loss analysis and thermal analysis are evaluated using the FEA method. Tests show that in this prototype, the accuracy of current control is higher than 97.5%, and the efficiency of the power supply reaches 87.8% when the output current is 40 A.

  17. Accelerator Fast Kicker R&D with Ultra Compact 50MVA Nano-Second FID Pulse Generator

    Science.gov (United States)

    2013-06-01

    multistage and multi-branch adder such as Marx generator and inductive voltage adder require simultaneous conduction of many switches. The pulse rise...and build inductive voltage adder can achieve the technical requirements, but the Marx generator design would have difficulty to meet pulse rise

  18. Accelerator mass spectrometer with ion selection in high-voltage terminal

    Science.gov (United States)

    Rastigeev, S. A.; Goncharov, A. D.; Klyuev, V. F.; Konstantinov, E. S.; Kutnyakova, L. A.; Parkhomchuk, V. V.; Petrozhitskii, A. V.; Frolov, A. R.

    2016-12-01

    The folded electrostatic tandem accelerator with ion selection in a high-voltage terminal is the basis of accelerator mass spectrometry (AMS) at the BINP. Additional features of the BINP AMS are the target based on magnesium vapors as a stripper without vacuum deterioration and a time-of-flight telescope with thin films for reliable ion identification. The acceleration complex demonstrates reliable operation in a mode of 1 MV with 50 Hz counting rate of 14C+3 radiocarbon for modern samples (14C/12C 1.2 × 10-12). The current state of the AMS has been considered and the experimental results of the radiocarbon concentration measurements in test samples have been presented.

  19. Voltage measurements at the vacuum post-hole convolute of the Z pulsed-power accelerator

    Directory of Open Access Journals (Sweden)

    E. M. Waisman

    2014-12-01

    Full Text Available Presented are voltage measurements taken near the load region on the Z pulsed-power accelerator using an inductive voltage monitor (IVM. Specifically, the IVM was connected to, and thus monitored the voltage at, the bottom level of the accelerator’s vacuum double post-hole convolute. Additional voltage and current measurements were taken at the accelerator’s vacuum-insulator stack (at a radius of 1.6 m by using standard D-dot and B-dot probes, respectively. During postprocessing, the measurements taken at the stack were translated to the location of the IVM measurements by using a lossless propagation model of the Z accelerator’s magnetically insulated transmission lines (MITLs and a lumped inductor model of the vacuum post-hole convolute. Across a wide variety of experiments conducted on the Z accelerator, the voltage histories obtained from the IVM and the lossless propagation technique agree well in overall shape and magnitude. However, large-amplitude, high-frequency oscillations are more pronounced in the IVM records. It is unclear whether these larger oscillations represent true voltage oscillations at the convolute or if they are due to noise pickup and/or transit-time effects and other resonant modes in the IVM. Results using a transit-time-correction technique and Fourier analysis support the latter. Regardless of which interpretation is correct, both true voltage oscillations and the excitement of resonant modes could be the result of transient electrical breakdowns in the post-hole convolute, though more information is required to determine definitively if such breakdowns occurred. Despite the larger oscillations in the IVM records, the general agreement found between the lossless propagation results and the results of the IVM shows that large voltages are transmitted efficiently through the MITLs on Z. These results are complementary to previous studies [R. D. McBride et al., Phys. Rev. ST Accel. Beams 13, 120401 (2010

  20. An efficient ternary serial adder based on carbon nanotube FETs

    Directory of Open Access Journals (Sweden)

    Mohammad Hossein Moaiyeri

    2016-03-01

    Full Text Available This paper presents an efficient ternary serial adder for nanotechnology employing negative, positive and standard ternary logics. Multiple-valued logic results in chips with more density, less complexity and high-bandwidth data transfer. The unique properties of CNTFETs such as the capability of adapting the desired threshold voltage by changing the diameters of the nanotubes and same carrier mobility for the n-type and p-type devices play an important role in designing this circuit. The proposed design method considerably reduces the number of required devices of a ternary serial adder. In addition, the results of the simulations conducted using HSPICE with the Stanford comprehensive 32 nm CNTFET model, demonstrate improvements in terms of speed and power-delay product as compared to the cutting-edge CNTFET-based ternary designs.

  1. Atomic Resolution Imaging at an Ultralow Accelerating Voltage by a Monochromatic Transmission Electron Microscope

    Science.gov (United States)

    Morishita, Shigeyuki; Mukai, Masaki; Suenaga, Kazu; Sawada, Hidetaka

    2016-10-01

    Transmission electron microscopy using low-energy electrons would be very useful for atomic resolution imaging of specimens that would be damaged at higher energies. However, the resolution at low voltages is degraded because of geometrical and chromatic aberrations. In the present study, we diminish the effect of these aberrations by using a delta-type corrector and a monochromator. The dominant residual aberration in a delta-type corrector, which is the sixth-order three-lobe aberration, is counterbalanced by other threefold aberrations. Defocus spread caused by chromatic aberration is reduced by using a monochromated beam with an energy spread of 0.05 eV. We obtain images of graphene and demonstrate atomic resolution at an ultralow accelerating voltage of 15 kV.

  2. Performance and Environmental Test Results of the High Voltage Hall Accelerator Engineering Development Unit

    Science.gov (United States)

    Kamhawi, Hani; Haag, Thomas; Huang, Wensheng; Shastry, Rohit; Pinero, Luis; Peterson, Todd; Mathers, Alex

    2012-01-01

    NASA Science Mission Directorate's In-Space Propulsion Technology Program is sponsoring the development of a 3.5 kW-class engineering development unit Hall thruster for implementation in NASA science and exploration missions. NASA Glenn and Aerojet are developing a high fidelity high voltage Hall accelerator that can achieve specific impulse magnitudes greater than 2,700 seconds and xenon throughput capability in excess of 300 kilograms. Performance, plume mappings, thermal characterization, and vibration tests of the high voltage Hall accelerator engineering development unit have been performed. Performance test results indicated that at 3.9 kW the thruster achieved a total thrust efficiency and specific impulse of 58%, and 2,700 sec, respectively. Thermal characterization tests indicated that the thruster component temperatures were within the prescribed material maximum operating temperature limits during full power thruster operation. Finally, thruster vibration tests indicated that the thruster survived the 3-axes qualification full-level random vibration test series. Pre and post-vibration test performance mappings indicated almost identical thruster performance. Finally, an update on the development progress of a power processing unit and a xenon feed system is provided.

  3. Dual-harmonic auto voltage control for the rapid cycling synchrotron of the Japan Proton Accelerator Research Complex

    Directory of Open Access Journals (Sweden)

    Fumihiko Tamura

    2008-07-01

    Full Text Available The dual-harmonic operation, in which the accelerating cavities are driven by the superposition of the fundamental and the second harmonic rf voltage, is useful for acceleration of the ultrahigh intensity proton beam in the rapid cycling synchrotron (RCS of Japan Proton Accelerator Research Complex (J-PARC. However, the precise and fast voltage control of the harmonics is necessary to realize the dual-harmonic acceleration. We developed the dual-harmonic auto voltage control system for the J-PARC RCS. We describe details of the design and the implementation. Various tests of the system are performed with the RCS rf system. Also, a preliminary beam test has been done. We report the test results.

  4. FPGA adders: performance evaluation and optimal design

    OpenAIRE

    Xing, S.; Yu, WWH

    1998-01-01

    Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.

  5. Ultra low power full adder topologies

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Mahmoodi, Hamid

    In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While...

  6. Parallelization of Reversible Ripple-carry Adders

    DEFF Research Database (Denmark)

    Thomsen, Michael Kirkedal; Axelsen, Holger Bock

    2009-01-01

    The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of \\emph{garbage}. Here, we present a novel parallelization scheme...... wherein $m$ parallel $k$-bit reversible ripple-carry adders are combined to form a reversible $mk$-bit \\emph{ripple-block carry adder} with logic depth $\\mathcal{O}(m+k)$ for a \\emph{minimal} logic depth $\\mathcal{O}(\\sqrt{mk})$, thus improving on the $mk$-bit ripple-carry adder logic depth $\\mathcal......{O}(m\\cdot k)$. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures...

  7. LOW POWER-AREA DESIGN OF FULL ADDER USING SELF RESETTING LOGIC WITH GDI TECHNIQUE

    Directory of Open Access Journals (Sweden)

    Simran Khokha1

    2016-08-01

    Full Text Available Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very Large Scale Integration technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area ,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic Circuits are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs have been proposed over last few years with different logic styles. To reduce the power consumption several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets, charge sharing by parasitic components while connecting source and drain of CMOS transistors There are situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset themselves after some prescribed delays. These circuits are hence called postcharge or self-resetting logic which are widely used in dynamic logic circuits. Overall performance of various adder designs is evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V. On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low PDP among its counterparts.

  8. A novel low-power A2 adder scheme based on reduced transistor count Full-Adder cells

    OpenAIRE

    Hatem Boukadida; Néjib Hassen; Zied Gafsi; Kamel Besbes

    2014-01-01

    A power-efficient 8-bits digital adder using the new arithmetic A2 redundant binary representation is presented. This structure is very suitable for implementation in VLSI of mixed-signal circuits built around Multiplier Digital to Analog Converter (MDAC) cells. Using a reduced transistor count Full-Adder cells shows that our approach significantly reduces the power consumption of such adders compared to the classical scheme using classical Full-Adder cells. The adder being studied was optimi...

  9. A New Adder Theory Based on Half Adder and Implementation in COMS Gates

    Directory of Open Access Journals (Sweden)

    Zhanfeng Zhang

    2010-12-01

    Full Text Available This paper proposes a new theory of adder and its basic structure. The new adder of asynchronous structure constructed by half adders, called Parallel Feedback Carry Adder (PFCA as its carry mode is parallel feedback. In theory, the area consumption of n-bit PFCA is close to O(n and the average length of carry chain is O(log n. A CMOS gate implementation scheme is implemented. HSPICE simulation results show that PFCA has obvious advantages over RCA, CLA, CSeA in speed and area, especially when n is bigger.

  10. A new type of accelerator power supply based on voltage-type space vector PWM rectification technology

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Fengjun, E-mail: wufengjun@impcas.ac.cn [Institute of Modern Physics, CAS, Lanzhou 730000 (China); University of Chinese Academy of Sciences, Beijing 100049 (China); Gao, Daqing; Shi, Chunfeng; Huang, Yuzhen [Institute of Modern Physics, CAS, Lanzhou 730000 (China); Cui, Yuan [Institute of Modern Physics, CAS, Lanzhou 730000 (China); University of Chinese Academy of Sciences, Beijing 100049 (China); Yan, Hongbin [Institute of Modern Physics, CAS, Lanzhou 730000 (China); Zhang, Huajian [Institute of Modern Physics, CAS, Lanzhou 730000 (China); University of Chinese Academy of Sciences, Beijing 100049 (China); Wang, Bin [University of Chinese Academy of Sciences, Beijing 100049 (China); Li, Xiaohui [Institute of Modern Physics, CAS, Lanzhou 730000 (China)

    2016-08-01

    To solve the problems such as low input power factor, a large number of AC current harmonics and instable DC bus voltage due to the diode or thyristor rectifier used in an accelerator power supply, particularly in the Heavy Ion Research Facility in Lanzhou-Cooler Storage Ring (HIRFL-CSR), we designed and built up a new type of accelerator power supply prototype base on voltage-type space vector PWM (SVPWM) rectification technology. All the control strategies are developed in TMS320C28346, which is a digital signal processor from TI. The experimental results indicate that an accelerator power supply with a SVPWM rectifier can solve the problems above well, and the output performance such as stability, tracking error and ripple current meet the requirements of the design. The achievement of prototype confirms that applying voltage-type SVPWM rectification technology in an accelerator power supply is feasible; and it provides a good reference for design and build of this new type of power supply. - Highlights: • Applying SVPWM rectification technology in an accelerator power supply improves its grid-side performance. • New Topology and its control strategies make an accelerator power supply have bidirectional power flow ability. • Hardware and software of controller provide a good reference for design of this new type of power supply.

  11. Determination of the aging offset voltage of AMR sensors based on accelerated degradation test

    NARCIS (Netherlands)

    Zambrano, Andreina; Kerkhoff, Hans G.

    2015-01-01

    Usually Anisotropic Magnetoresistance angle sensors are configured with two Wheatstone bridges, but an undesirable offset voltage included in the sensor output affects its accuracy. The total offset voltage combines a voltage due to resistance mismatches during manufacturing and a voltage from inequ

  12. Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

    Directory of Open Access Journals (Sweden)

    Marco Lanuzza

    2011-04-01

    Full Text Available Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.

  13. Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders.

    Science.gov (United States)

    Balasubramanian, P; Yamashita, S

    2016-01-01

    This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.

  14. Design and Performance Analysis of Various Adders using Verilog

    OpenAIRE

    Maroju SaiKumar; Dr. P. Samundiswary

    2013-01-01

    Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), ...

  15. Investigation of the Effects of Facility Background Pressure on the Performance and Voltage-Current Characteristics of the High Voltage Hall Accelerator

    Science.gov (United States)

    Kamhawi, Hani; Huang, Wensheng; Haag, Thomas; Spektor, Rostislav

    2014-01-01

    The National Aeronautics and Space Administration (NASA) Science Mission Directorate In-Space Propulsion Technology office is sponsoring NASA Glenn Research Center to develop a 4 kW-class Hall thruster propulsion system for implementation in NASA science missions. A study was conducted to assess the impact of varying the facility background pressure on the High Voltage Hall Accelerator (HiVHAc) thruster performance and voltage-current characteristics. This present study evaluated the HiVHAc thruster performance in the lowest attainable background pressure condition at NASA GRC Vacuum Facility 5 to best simulate space-like conditions. Additional tests were performed at selected thruster operating conditions to investigate and elucidate the underlying physics that change during thruster operation at elevated facility background pressure. Tests were performed at background pressure conditions that are three and ten times higher than the lowest realized background pressure. Results indicated that the thruster discharge specific impulse and efficiency increased with elevated facility background pressure. The voltage-current profiles indicated a narrower stable operating region with increased background pressure. Experimental observations of the thruster operation indicated that increasing the facility background pressure shifted the ionization and acceleration zones upstream towards the thruster's anode. Future tests of the HiVHAc thruster are planned at background pressure conditions that are expected to be two to three times lower than what was achieved during this test campaign. These tests will not only assess the impact of reduced facility background pressure on thruster performance, voltage-current characteristics, and plume properties; but will also attempt to quantify the magnitude of the ionization and acceleration zones upstream shifting as a function of increased background pressure.

  16. Improvement in the Design of Metal-Ceramic High Voltage Feedthroughs for use in High Energy Particle Accelerators

    CERN Document Server

    Weterings, W

    1999-01-01

    Large high-voltage devices operate in particle accelerators to steer charged particles in the desired direction. Solid and hollow rods of sintered alumina are used as insulating supports and high-voltage feedthroughs to power the electrodes of these electrostatic systems. The performance of the systems is often limited by voltage breakdown along the surface of the ceramic insulator (so-called surface flashover) or discharge between feedthrough and vacuum tank, which can lead to significant disruptions in terms of overall machine efficiency. Available results on the influence of the mechanical preparation, thermal history and particular cleaning techniques on commercially obtainable alumina samples have been studied in order to investigate possibilities for better preparation methodology of the insulating supports. Also the influence of the relative position of the feedthrough inside the vacuum tank on the high-voltage breakdown behaviour has been studied. This paper describes the theoretical and practical bac...

  17. High Voltage Hall Accelerator Propulsion System Development for NASA Science Missions

    Science.gov (United States)

    Kamhawi, Hani; Haag, Thomas; Huang, Wensheng; Shastry, Rohit; Pinero, Luis; Peterson, Todd; Dankanich, John; Mathers, Alex

    2013-01-01

    NASA Science Mission Directorates In-Space Propulsion Technology Program is sponsoring the development of a 3.8 kW-class engineering development unit Hall thruster for implementation in NASA science and exploration missions. NASA Glenn Research Center and Aerojet are developing a high fidelity high voltage Hall accelerator (HiVHAc) thruster that can achieve specific impulse magnitudes greater than 2,700 seconds and xenon throughput capability in excess of 300 kilograms. Performance, plume mappings, thermal characterization, and vibration tests of the HiVHAc engineering development unit thruster have been performed. In addition, the HiVHAc project is also pursuing the development of a power processing unit (PPU) and xenon feed system (XFS) for integration with the HiVHAc engineering development unit thruster. Colorado Power Electronics and NASA Glenn Research Center have tested a brassboard PPU for more than 1,500 hours in a vacuum environment, and a new brassboard and engineering model PPU units are under development. VACCO Industries developed a xenon flow control module which has undergone qualification testing and will be integrated with the HiVHAc thruster extended duration tests. Finally, recent mission studies have shown that the HiVHAc propulsion system has sufficient performance for four Discovery- and two New Frontiers-class NASA design reference missions.

  18. Unimolecular binary half-adders with orthogonal chemical inputs.

    Science.gov (United States)

    Zhang, Lu; Whitfield, Wesley A; Zhu, Lei

    2008-04-28

    Unimolecular half-adders based upon an arylvinyl-bipyridyl fluorophore platform were demonstrated where all the chemical input combinations were fully processed by half-adder molecules to generate the arithmetic results of the entire truth table.

  19. A new type of accelerator power supply based on voltage-type space vector PWM rectification technology

    Science.gov (United States)

    Wu, Fengjun; Gao, Daqing; Shi, Chunfeng; Huang, Yuzhen; Cui, Yuan; Yan, Hongbin; Zhang, Huajian; Wang, Bin; Li, Xiaohui

    2016-08-01

    To solve the problems such as low input power factor, a large number of AC current harmonics and instable DC bus voltage due to the diode or thyristor rectifier used in an accelerator power supply, particularly in the Heavy Ion Research Facility in Lanzhou-Cooler Storage Ring (HIRFL-CSR), we designed and built up a new type of accelerator power supply prototype base on voltage-type space vector PWM (SVPWM) rectification technology. All the control strategies are developed in TMS320C28346, which is a digital signal processor from TI. The experimental results indicate that an accelerator power supply with a SVPWM rectifier can solve the problems above well, and the output performance such as stability, tracking error and ripple current meet the requirements of the design. The achievement of prototype confirms that applying voltage-type SVPWM rectification technology in an accelerator power supply is feasible; and it provides a good reference for design and build of this new type of power supply.

  20. A compact 300 kV solid-state high-voltage nanosecond generator for dielectric wall accelerator

    Science.gov (United States)

    Shen, Yi; Wang, Wei; Liu, Yi; Xia, Liansheng; Zhang, Huang; Pan, Haifeng; Zhu, Jun; Shi, Jinshui; Zhang, Linwen; Deng, Jianjun

    2015-05-01

    Compact solid-state system is the main development trend in pulsed power technologies. A compact solid-state high-voltage nanosecond pulse generator with output voltage of 300 kV amplitude, 10 ns duration (FWHM), and 3 ns rise-time was designed for a dielectric wall accelerator. The generator is stacked by 15 planar-plate Blumlein pulse forming lines (PFL). Each Blumlein PFL consists of two solid-state planar transmission lines, a GaAs photoconductive semiconductor switch, and a laser diode trigger. The key components of the generator and the experimental results are reported in this paper.

  1. Optimal design method for fast carry-skip adders

    Science.gov (United States)

    Lee, Songjun; Swartzlander, Earl E., Jr.

    2001-11-01

    A carry-skip adder is faster than a ripple carry adder and it has a simple structure. To maximize the speed it is necessary to optimize the width of the blocks that comprise the carry skip adder. This paper presents a simple algorithm to select the size of each block. Assuming that each logic gate has a unit delay, the algorithm achieves slightly faster designs for 64 and 128 bit adders than previous methods developed by Guyot, et al. and Kantabutra.

  2. Functional Verification of High Performance Adders in COQ

    Directory of Open Access Journals (Sweden)

    Qian Wang

    2014-01-01

    formalize and verify adders in a formal proof assistant COQ. The proposed approach succeeds in formalizing the gate-level implementations and verifying the functional correctness of the most important adders of interest in industry, in a faithful, scalable, and modularized way. The methodology can be extended to other adder architectures as well.

  3. Design and analysis of carbon nanotube FET based quaternary full adders

    Institute of Scientific and Technical Information of China (English)

    Mohammad Hossein MOAIYERI; Shima SEDIGHIANI; Fazel SHARIFI; Keivan NAVI

    2016-01-01

    CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.

  4. Modelling of Parasitic Inductances of a High Precision Inductive Adder for CLIC

    CERN Document Server

    Holma, J; Ovaska, S J

    2013-01-01

    The CLIC study is exploring the scheme for an electron-positron collider with high luminosity and a nominal centre-of-mass energy of 3 TeV. The CLIC pre-damping rings and damping rings will produce, through synchrotron radiation, ultra-low emittance beam with high bunch charge. To avoid beam emittance increase, the damping ring kicker systems must provide extremely flat, high-voltage, pulses. The specifications for the extraction kickers of the DRs are particularly demanding: the flat-top of the pulses must be ±12.5 kV with a combined ripple and droop of not more than ±0.02 % (±2.5 V). An inductive adder is a very promising approach to meeting the specifications. However, the output impedance of the inductive adder needs to be well matched to the system impedance. The primary leakage inductance, which cannot be computed accurately analytically, has a significant effect upon the output impedance of the inductive adder. This paper presents predictions, obtained by modelling the 3D geometry of the adder struc...

  5. A Low power and area efficient CLA adder design using Full swing GDI technique

    OpenAIRE

    Matcha Hemanth Kumar; Prof. Dr.S.M.VALI

    2015-01-01

    The low power VLSI design has an important role in designing of many electronic systems. While designing any combinational or sequential circuits, the important parameters like power consumption, implementation area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient data path logic systems forms the largest areas of research in VLSI system design. This paper presents a low power Carry look ahead adder design using Full swing Gat...

  6. Correlations of Capacitance-Voltage Hysteresis with Thin-Film CdTe Solar Cell Performance During Accelerated Lifetime Testing

    Energy Technology Data Exchange (ETDEWEB)

    Albin, D.; del Cueto, J.

    2011-03-01

    In this paper we present the correlation of CdTe solar cell performance with capacitance-voltage hysteresis, defined presently as the difference in capacitance measured at zero-volt bias when collecting such data with different pre-measurement bias conditions. These correlations were obtained on CdTe cells stressed under conditions of 1-sun illumination, open-circuit bias, and an acceleration temperature of approximately 100 degrees C.

  7. Novel Optimized Designs for QCA Serial Adders

    Directory of Open Access Journals (Sweden)

    A. Mostafaee

    2017-02-01

    Full Text Available Quantum-dot Cellular Automata (QCA is a new and efficient technology to implement logic Gates and digital circuits at the nanoscale range. In comparison with the conventional CMOS technology, QCA has many attractive features such as: low-power, extremely dense and high speed structures. Adders are the most important part of an arithmetic logic unit (ALU. In this paper, four optimized designs of QCA serial adders are presented. One of the proposed designs is optimized in terms of the number of cells, area and delay without any wire crossing methods. Also, two new designs of QCA serial adders and a QCA layout equivalent to the internal circuit of TM4006 IC are presented. QCADesigner software is used to simulate the proposed designs. Finally, the proposed QCA designs are compared with the previous QCA, CNTFET-based and CMOS technologies.

  8. Design and analysis of a high-performance CNFET-based Full Adder

    Science.gov (United States)

    Moaiyeri, Mohammad Hossein; Faghih Mirzaee, Reza; Navi, Keivan; Momeni, Amir

    2012-01-01

    This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product, and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells.

  9. Optimal Final Carry Propagate Adder Design for Parallel Multipliers

    CERN Document Server

    B., Ramkumar

    2011-01-01

    Based on the ASIC layout level simulation of 7 types of adder structures each of four different sizes, i.e. a total of 28 adders, we propose expressions for the width of each of the three regions of the final Carry Propagate Adder (CPA) to be used in parallel multipliers. We also propose the types of adders to be used in each region that would lead to the optimal performance of the hybrid final adders in parallel multipliers. This work evaluates the complete performance of the analyzed designs in terms of delay, area, power through custom design and layout in 0.18 um CMOS process technology.

  10. Design and Analysis of a High Speed Carry Select Adder

    OpenAIRE

    Simarpreet Singh Chawla; Swapnil Aggarwal; Anshika; Nidhi Goel

    2015-01-01

    An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devis...

  11. Design and Analysis of a High Speed Carry Select Adder

    OpenAIRE

    Simarpreet Singh Chawla; Swapnil Aggarwal; Anshika; Nidhi Goel

    2015-01-01

    An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devi...

  12. Optimized reversible binary-coded decimal adders

    DEFF Research Database (Denmark)

    Thomsen, Michael Kirkedal; Glück, Robert

    2008-01-01

    their design. The optimized 1-decimal BCD full-adder, a 13 × 13 reversible logic circuit, is faster, and has lower circuit cost and less garbage bits. It can be used to build a fast reversible m-decimal BCD full-adder that has a delay of only m + 17 low-power reversible CMOS gates. For a 32-decimal (128-bit...... in reversible logic design by drastically reducing the number of garbage bits. Specialized designs benefit from support by reversible logic synthesis. All circuit components required for optimizing the original design could also be synthesized successfully by an implementation of an existing synthesis algorithm...

  13. Design the High Speed Kogge-Stone Adder by Using

    Directory of Open Access Journals (Sweden)

    MUX

    2015-08-01

    Full Text Available In this Technical era the high speed and low area of VLSI chip are very- very essential factors. Day by day number of transistors and other active and passive elements are growing on VLSI chip. In Integral part of the processor adders play an important role. In this paper we are using proposed kogge-stone adders for binary addition to reduce the size and increase the efficiency or processors speed. Proposing kogge stone adder provides less components, less path delay and better speed compare to other existing kogge stone adder and other adders. Here we are comparing the kogge stone adders of different-different word size from other adders. The design and experiment can be done by the aid of Xilinx 14.1i Spartan 3 device family.

  14. Delay Efficient 32-Bit Carry-Skip Adder

    Directory of Open Access Journals (Sweden)

    Yu Shen Lin

    2008-01-01

    Full Text Available The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 m CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18% faster than the current fastest carry-skip adder.

  15. Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

    Science.gov (United States)

    Zhou, Rigui; Zhang, Manqun; Wu, Qian; Shi, Yang

    2012-10-01

    Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays than the existing designs.

  16. Efficient carry skip Adder design using full adder and carry skip block based on reversible Logic

    Directory of Open Access Journals (Sweden)

    Varun Pratap Singh

    2015-12-01

    Full Text Available In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, binary full Adder with Design I and Design II are proposed. The performance analysis is verified using number of reversible gates, Garbage input/outputs, delay, number of logical calculations and Quantum Cost. According to the suitability of full adder design I and design II carry skip adder block is also constructed with some improvement in terms of delay in block carry generation. It is observed that Reversible carry skip Binary Adder with Design II is efficient compared to Design I

  17. Optimized design of BCD adder and Carry skip BCD adder using reversible logic gates

    OpenAIRE

    H.R.Bhagyalakshmi,; M K Venkatesha

    2011-01-01

    Reversible logic is very essential for the construction of low power, low loss computational structures which are very essential for the construction of arithmetic circuits used in quantum computation, nano technology and other low power digital circuits. In the present paper an optimized and low quantum cost one digit BCD adder and an optimized one digit carry skip BCD adder using new reversible logic gates are proposed. The proposed work is best compared to the other existing circuits.

  18. DESIGN OF OPTIMAL CARRY SKIP ADDER AND CARRY SKIP BCD ADDER USING REVERSIBLE LOGIC GATES

    OpenAIRE

    Praveena Murugesan; Thanushkodi Keppanagounder

    2014-01-01

    Reversible logic circuits have the ability to produce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic circuits for carry skip adder and carry skip BCD adder. The performance of the proposed architecture is better than the existing works in terms of gate count, garbage outputs and constant inputs. This design forms the basis for different quantum ALU and embe...

  19. Optimized design of BCD adder and Carry skip BCD adder using reversible logic gates

    Directory of Open Access Journals (Sweden)

    H.R.Bhagyalakshmi,

    2011-04-01

    Full Text Available Reversible logic is very essential for the construction of low power, low loss computational structures which are very essential for the construction of arithmetic circuits used in quantum computation, nano technology and other low power digital circuits. In the present paper an optimized and low quantum cost one digit BCD adder and an optimized one digit carry skip BCD adder using new reversible logic gates are proposed. The proposed work is best compared to the other existing circuits.

  20. Characteristics of "Adders" in Proportional Reasoning.

    Science.gov (United States)

    Lin, Fou-Lai

    1991-01-01

    The errors and strategies made by students who consistently use the incorrect-addition strategy on "hard" ratio tasks were investigated. The characteristics of these "adders," such as awareness of noninteger multiples, the use of fractions and decimals, awareness of both within and between ratios, and distinguishing nonratio…

  1. Near threshold operation of 16-bit adders in 65nm CMOStechnology

    OpenAIRE

    Maddula, Ravi

    2014-01-01

    The main objective of the thesis is to implement different architectures of 16-bit adders such as; Ripple CarryAdder (RCA), Manchester Carry Chain Adder (MCCA) and Kogge Stone Adder (KSA), in 65nm CMOS technology and to study their performance in terms of power, operating frequency and speed at near threshold operating regions. The performance of these adders are evaluated and compared with each other and a final conclusion is made as to which adder structure is more suitable for implementati...

  2. A comparison of two fast binary adder configurations

    Science.gov (United States)

    Canaris, J.; Cameron, K.

    1990-01-01

    Conditional sum and binary lookahead carry are two methods for performing fast binary addition. These methods are quite different, but the adders have a common feature that makes them interesting to compare. Both adders have the carry generating logic implemented as a binary tree, which grows in depth as log(sub 2) n,n equals the number of bits in the adder. The delay in the carry paths also grows in proportion to log(sub 2) n. This paper shows that the Transmission-Gate Conditional-Sum adder and the binary lookahead carry adder have the same speed of addition, but that the conditional sum adder requires only 46 percent of the area.

  3. A C-Testable Multiple-Block Carry Select Adder

    Science.gov (United States)

    Kito, Nobutaka; Fujii, Shinichi; Takagi, Naofumi

    We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2: 1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.

  4. Design of High-Speed Hybrid Carry Select Adders using VHDL

    OpenAIRE

    Mr. Vijay V. Gotmare; Dr. Pankaj Agarwal

    2016-01-01

    Carry select adder (CSA) is a square-root time high-speed adder. CSA is one of the fastest adders used in many data processing systems to perform fast arithmetic operations. In this project we propose to design hybrid carry select adders with a focus on high speed. CSA is a compromise between the longer delay Ripple carry adder (RCA) and the shorter delay Carry look-ahead adder (CLA). Conventionally carry select adders are realize using the full adders and 2:1 multiplexers. On the other hand ...

  5. Functional Verification of High Performance Adders in COQ

    OpenAIRE

    Qian Wang; Xiaoyu Song; Ming Gu; Jiaguang Sun

    2014-01-01

    Addition arithmetic design plays a crucial role in high performance digital systems. The paper proposes a systematic method to formalize and verify adders in a formal proof assistant COQ. The proposed approach succeeds in formalizing the gate-level implementations and verifying the functional correctness of the most important adders of interest in industry, in a faithful, scalable, and modularized way. The methodology can be extended to other adder architectures as well.

  6. High performance pipelined multiplier with fast carry-save adder

    Science.gov (United States)

    Wu, Angus

    1990-01-01

    A high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.

  7. Static power dissipation in adder circuits: the UDSM domain

    Science.gov (United States)

    Cayouette, Steve; Al-Khalili, Dhamin

    2009-05-01

    This paper presents adder circuits of various architectures aimed at reducing static power dissipation. Circuit topologies for basic building blocks were evaluated for fabrication technologies of 65nm down to 32nm, and simulation results are presented. This work has lead to the development of various low power adder circuits and provides comparative analysis leading to the recommendation that a variable size block carry select adder is the best performer, taking into consideration both static and dynamic power dissipation.

  8. Self-timed Manchester chain carry propagate adder

    OpenAIRE

    Escribà, J; Carrasco, Juan A.

    1996-01-01

    The authors present a self-timed adder that uses two Manchester chains to propagate carries in a two-rail code. With the inclusion of buffers in the chains, the adder meets the timing conditions typical of an asynchronous design based in the ‘bundled-data, bounded-delay’ model and is signifcantly faster than self-timed adders with restoring logic and similar complexity.

  9. The COBRA accelerator pulsed-power driver for Cornell/Sandia ICF research

    Energy Technology Data Exchange (ETDEWEB)

    Smith, D.L.; Ingwersen, P.; Bennett, L.F.; Boyes, J.D. [Sandia National Labs., Albuquerque, NM (United States); Anderson, D.E.; Greenly, J.B.; Sudan, R.N.; Hammer, D.A. [Cornell Univ., Ithaca, NY (United States)

    1995-07-01

    This paper introduces and describes the new Cornell Beam Research Accelerator, COBRA, the result of a three and one-half year collaboration. The flexible 4 to 5-MV, 100 to 250-kA, 46-ns pulse width accelerator is based on a four-cavity Inductive Voltage Adder (IVA) design. In addition to being a mix of new and existing components, COBRA is unique in the sense that each cavity is driven by a single pulse forming line, and the IVA output polarity may be reversed by rotating the cavities 1800 about their vertical axis. Our tests with negative high voltage on the inner MITL stalk indicate that the vacuum power flow has established reasonable azimuthal symmetry within about 2 ns (or 0.6 m) after the cavity output cap. Preliminary results with the accelerator, single cavity, and MITL are presented alone, with the design details and circuit model predictions.

  10. Approximate Quantum Adders with Genetic Algorithms: An IBM Quantum Experience

    Directory of Open Access Journals (Sweden)

    Li Rui

    2017-07-01

    Full Text Available It has been proven that quantum adders are forbidden by the laws of quantum mechanics. We analyze theoretical proposals for the implementation of approximate quantum adders and optimize them by means of genetic algorithms, improving previous protocols in terms of efficiency and fidelity. Furthermore, we experimentally realize a suitable approximate quantum adder with the cloud quantum computing facilities provided by IBM Quantum Experience. The development of approximate quantum adders enhances the toolbox of quantum information protocols, paving the way for novel applications in quantum technologies.

  11. A Novel Reversible BCD Adder For Nanotechnology Based Systems

    Directory of Open Access Journals (Sweden)

    Majid Haghparast

    2008-01-01

    Full Text Available This paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as “Copying Circuit” to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all Boolean functions. It also can be used to design optimized adder architectures. This paper also proposes a novel reversible full adder. One of the prominent functionalities of the proposed HNG gate is that it can work singly as a reversible full adder unit. The proposed reversible full adder contains only one gate. We show that its hardware complexity is less than the existing reversible full adders. The proposed full adder is then applied to the design of a reversible 4-bit parallel adder. A reversible Binary Coded Decimal (BCD adder circuit is also proposed. The proposed circuit can add two 4-bit binary variables and it transforms the result into the appropriate BCD number using efficient error correction modules. We show that the proposed reversible BCD adder has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and garbage outputs with compared to the existing counterparts.

  12. Power comparison of CMOS and adiabatic full adder circuit

    CERN Document Server

    Reddy, Sunil Gavaskar; 10.5121/vlsic.2011.2306

    2011-01-01

    Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

  13. An Efficient Power Optimized 1-bit CMOS Full Adder

    Directory of Open Access Journals (Sweden)

    R.M.Poojithaa

    2013-06-01

    Full Text Available Adders are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Apart from addition, adders are also used in performing useful operations such as subtraction, multiplication, division and address calculation etc. In this paper, we have presented the study of different logic style using 1-bit full adder circuit and we have compared this 1-bit full adder on certain parameters such as power, number of transistor and frequency using microwind and T-spice.

  14. Two Novel Quantum-Dot Cellular Automata Full Adders

    OpenAIRE

    Mahdie Qanbari; Reza Sabbaghi-Nadooshan

    2013-01-01

    Quantum-dot cellular automata (QCA) is an efficient technology to create computing devices. QCA is a suitable candidate for the next generation of digital systems. Full adders are the main member of computational systems because other operations can be implemented by adders. In this paper, two QCA full adders are introduced. The first one is implemented in one layer, and the second one is implemented in three layers. Five-input majority gate is used in both of them. These full adders are bett...

  15. Two Novel Quantum-Dot Cellular Automata Full Adders

    Directory of Open Access Journals (Sweden)

    Mahdie Qanbari

    2013-01-01

    Full Text Available Quantum-dot cellular automata (QCA is an efficient technology to create computing devices. QCA is a suitable candidate for the next generation of digital systems. Full adders are the main member of computational systems because other operations can be implemented by adders. In this paper, two QCA full adders are introduced. The first one is implemented in one layer, and the second one is implemented in three layers. Five-input majority gate is used in both of them. These full adders are better than pervious designs in terms of area, delay, and complexity.

  16. Approximate Quantum Adders with Genetic Algorithms: An IBM Quantum Experience

    Science.gov (United States)

    Li, Rui; Alvarez-Rodriguez, Unai; Lamata, Lucas; Solano, Enrique

    2017-07-01

    It has been proven that quantum adders are forbidden by the laws of quantum mechanics. We analyze theoretical proposals for the implementation of approximate quantum adders and optimize them by means of genetic algorithms, improving previous protocols in terms of efficiency and fidelity. Furthermore, we experimentally realize a suitable approximate quantum adder with the cloud quantum computing facilities provided by IBM Quantum Experience. The development of approximate quantum adders enhances the toolbox of quantum information protocols, paving the way for novel applications in quantum technologies.

  17. Pipelined Two-Operand Modular Adders

    Directory of Open Access Journals (Sweden)

    M. Czyzak

    2015-04-01

    Full Text Available Pipelined two-operand modular adder (TOMA is one of basic components used in digital signal processing (DSP systems that use the residue number system (RNS. Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The design of pipelined TOMAs is usually obtained by inserting an appriopriate number of latch layers inside a nonpipelined TOMA structure. Hence their area is also determined by the number of latches and the delay by the number of latch layers. In this paper we propose a new pipelined TOMA that is based on a new TOMA, that has the smaller area and smaller delay than other known structures. Comparisons are made using data from the very large scale of integration (VLSI standard cell library.

  18. A decimal carry-free adder

    Science.gov (United States)

    Nikmehr, Hooman; Phillips, Braden; Lim, Cheng-Chew

    2005-02-01

    Recently, decimal arithmetic has become attractive in the financial and commercial world including banking, tax calculation, currency conversion, insurance and accounting. Although computers are still carrying out decimal calculation using software libraries and binary floating-point numbers, it is likely that in the near future, all processors will be equipped with units performing decimal operations directly on decimal operands. One critical building block for some complex decimal operations is the decimal carry-free adder. This paper discusses the mathematical framework of the addition, introduces a new signed-digit format for representing decimal numbers and presents an efficient architectural implementation. Delay estimation analysis shows that the adder offers improved performance over earlier designs.

  19. Reviewing High-Radix Signed Digit Adders

    DEFF Research Database (Denmark)

    Kornerup, Peter

    2015-01-01

    Higher radix values of the form $\\beta=2^r$ have been employed traditionally for recoding of multipliers, and for determining quotient- and root-digits in iterative division and square root algorithms, usually only for quite moderate values of $r$, like 2 or 3. For fast additions, in particular f......, on the contrary, there are significant savings in using standard 4-to-2 adders, even saving half of the operations in multi-operand addition....

  20. Initial measurements on a prototype inductive adder for the CLIC kicker systems

    CERN Document Server

    Holma, Janne

    2013-01-01

    The CLIC study is exploring the scheme for an electron-positron collider with high luminosity and a nominal centre-of-mass energy of 3 TeV. The CLIC pre-damping rings and damping rings will produce, through synchrotron radiation, ultra-low emittance beam with high bunch charge. To avoid beam emittance increase, the damping ring kicker systems must provide extremely flat, high-voltage, pulses. The specifications for the extraction kickers of the DRs are particularly demanding: the flattops of the pulses must be ±12.5 kV with a combined ripple and droop of not more than ±0.02 % (±2.5 V). An inductive adder is a very promising approach to meeting the specifications. To achieve ultra-flat pulses with a fast rise time the output impedance of the inductive adder needs to be well matched to the system impedance. The parasitic circuit elements of the inductive adder have a significant effect upon the output impedance and these values are very difficult to calculate accurately analytically. To predict these paramet...

  1. Acceleration Induced Voltage Variations in the Electrocardiogram during Exhaustive Simulated Aerial Combat Maneuvering

    Science.gov (United States)

    1982-01-01

    ACESSION *40 3.IEJPtEN TS CAT ALOG NUMBER SAM TR # 81-330 soI 11f(~(~ 4. TITLE (and Subtitle) S. TYPE OF REPORT & PERIOD COVERED Acceleration-Induced...PROJECT, TASK USAF School of Aerospace Medicine (VNB) AREA & WORK UNIT NUMBERSo Aerospace Medical Division (AFSC) S Brooks AFB, TX 78235 I. CONTROLLING...OFFICE NAME AND ADDRESS 12. REPORT DATE USAF School of Aerospace Medicine 28 July 1981 Aerospace Medical Division (AFSC) 13. NUMBER OF PAGES Brooks AFB

  2. Proposal to Negotiate, without Competitive Tendering, a Blanket Order for High-Voltage Thyratrons for the CERN Accelerators

    CERN Document Server

    2002-01-01

    This document concerns the supply of thyratrons to be used as high-voltage and high-current switches for the fast-pulsed magnet systems of the CERN accelerators and for the protection of the klystrons of RF systems. Following a market survey (MS-3136/SL/LHC) carried out among 18 firms in ten Member States, CERN entered into negotiations with one firm in one Member State. The Finance Committee is invited to agree to the negotiation, without competitive tendering, of a new blanket order with E2V TECHNOLOGIES (GB) for up to 800 000 pounds sterling to cover the supply of thyratrons for the years 2003, 2004 and 2005, subject to price revision for inflation for deliveries after 31 December 2003. At the present rate of exchange, this amount is equivalent to 1 855 000 Swiss francs. The firm has indicated the following distribution by country of the order value covered by this adjudication proposal: GB - 100%.

  3. Efficient Implementation of Decimal Floating Point Adder in FPGA

    Directory of Open Access Journals (Sweden)

    Yang Huijing

    2013-10-01

    Full Text Available Decimal floating Point adder is one of the most frequent operations used by many financial, business and user-oriented applications but current implementations in FPGAs are very inefficient in terms of both area and latency when compared to binary floating point adder. This paper has shown an efficient implementation of a new parallel decimal floating point module on a reconfigurable platform, which is both area as well as performance optimal. The decimal floating-point Adder was further pipelined into five stages to increase the maximum frequency of operation. The synthesis results for a Stratix IV device indicate that our implementations have 25.1% reduction of the latency and 1.1% reduction of area compared to an existing alter-core adder design, presenting area and delay figures close to those of optimal binary adder trees.  

  4. Lane of parallel through carry in ternary optical adder

    Institute of Scientific and Technical Information of China (English)

    JIN Yi; HE Huacan; AI Lirong

    2005-01-01

    At the present 50 to 100 microseconds are necessary for a liquid crystal to change its state from opacity to clarity; 1.14× 10-5 microseconds are however proved to be enough for light to pass through a clarity liquid crystal device. Rooted from this great difference in time, an optical adder was constructed with parallel through carry lanes (PTCL) composed of liquid crystals. Because all carries in PTCL process in parallel, the carry delay in the ternary optical computer's adder is avoided. Eliminating the carry delay in adder of ternary optical computer by physical means, the PTCL is also applicable for other types of optical adders. Moreover a light diagram of the adder and one PTCL structure are provided.

  5. OPTIMIZATION OF HYBRID FINAL ADDER FOR THE HIGH PERFORMANCE MULTIPLIER

    Directory of Open Access Journals (Sweden)

    RAMKUMAR B.

    2013-04-01

    Full Text Available In this work we evaluated arrival profile of the HPM based multiplier partial products reduction tree in two ways: 1.manual delay, area calculation through logical effort, 2.ASIC implementation. Based on the arrival profile, we worked with some recently proposed optimal adders and finally we proposed an optimal hybrid adder for the final addition in HPM based parallel multiplier. This work derives some mathematical expressions to find the size of different regions in the partial product arrival profile which helps to design optimal adder for each region. This work evaluates the performance of proposed hybrid adder in terms of area, power and delay using 90nm technology. This work deals with manual calculation for 8-b and ASIC simulation of different adder designs for 8-b, 16-b, 32-b and 64-b multiplier bit sizes.

  6. A novel reversible carry-selected adder with low latency

    Science.gov (United States)

    Li, Ming-Cui; Zhou, Ri-Gui

    2016-07-01

    Reversible logic is getting more and more attention in quantum computing, optical computing, nanotechnology and low-power complementary metal oxide semiconductor designs since reversible circuits do not loose information during computation and have only small energy dissipation. In this paper, a novel carry-selected reversible adder is proposed primarily optimised for low latency. A 4-bit reversible full adder with two kinds of outputs, minimum delay and optimal quantum cost is presented as the building block for ?-bit reversible adder. Three new reversible gates NPG (new Peres gate), TEPG (triple extension of Peres gate) and RMUX21 (reversible 2-to-1 multiplexer) are proposed and utilised to design efficient adder units. The secondary carry propagation chain is carefully designed to reduce the time consumption. The novelty of the proposed design is the consideration of low latency. The comparative study shows that the proposed adder achieves the improvement from 61.46% to 95.29% in delay over the existing designs.

  7. On the Design and Analysis of Quaternary Serial and Parallel Adders

    CERN Document Server

    Das, Anindya; Hasan, Masud

    2010-01-01

    Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We develop the equations for single-stage parallel adder which works as a carry look-ahead adder. We also provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the designs and finally propose a hybrid adder which combines the advantages of serial and parallel adder.

  8. VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

    Directory of Open Access Journals (Sweden)

    S. Karunakaran

    2012-01-01

    Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

  9. High Speed Multiple Valued Logic Full Adder Using Carbon Nano Tube Field Effect Transistor

    CERN Document Server

    Khatir, Ashkan; Mahmoudi, Iman

    2011-01-01

    High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts

  10. High Speed Multiple Valued Logic Full Adder Using Carbon Nano Field Effect Transistor

    Directory of Open Access Journals (Sweden)

    Ashkan Khatir

    2011-03-01

    Full Text Available High speed Full-Adder (FA module is a critical element in designing high performance arithmeticcircuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FAis constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFETtechnology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and0.9v. The observed results reveal power consumption and power delay product (PDP improvementscompared to existing FA counterparts.

  11. The Prototype Inductive Adder With Droop Compensation for the CLIC Kicker Systems

    CERN Document Server

    Holma, J

    2014-01-01

    The Compact Linear Collider (CLIC) study is exploring the scheme for an electron-positron collider with high luminosity and a nominal center-of-mass energy of 3 TeV. The CLIC predamping rings and damping rings (DRs) will produce, through synchrotron radiation, an ultralow emittance beam with high bunch charge. To avoid beam emittance increase, the DR kicker systems must provide extremely flat, high-voltage, pulses. The specifications for the extraction kickers of the DRs are particularly demanding: the flattops of the pulses must be ±12.5 kV with a combined ripple and droop of not more than ±0.02% (±2.5 V). An inductive adder is a very promising approach to meeting the specifications. Recently, a five-layer prototype has been built at CERN. Passive analog modulation has been applied to compensate the voltage droop, for example of the pulse capacitors. The output waveforms of the prototype inductive adder have been compared with predictions of the voltage droop and pulse shape. Conclusions are drawn concern...

  12. Design & Analysis of Low Power, Area-Efficient Carry Select Adder

    Directory of Open Access Journals (Sweden)

    Shuchi Verma

    2014-03-01

    Full Text Available This paper deals with the design & analysis of Carry Select Adder (CSLA & Carry lookahead adder (CLA. Adders are designed using 0.18µm CMOS process technology & simulated with Modelsim6.3f. The adder designs, Regular CSLA, modified CSLA using BEC, modified CSLA without using multiplexer, modified CSLA using D-Latch & Carry lookahead adders in 4-bit, 16-bit, 32-bit, are compared with the simulated results on the basis area.

  13. Error correction in adders using systematic subcodes.

    Science.gov (United States)

    Rao, T. R. N.

    1972-01-01

    A generalized theory is presented for the construction of a systematic subcode for a given AN code in such a way that error control properties of the AN code are preserved in this new code. The 'systematic weight' and 'systematic distance' functions in this new code depend not only on its number representation system but also on its addition structure. Finally, to illustrate this theory, a simple error-correcting adder organization using a systematic subcode of 29 N code is sketched in some detail.

  14. A Novel Approach For Error Detection And Correction Using Prefix-Adders

    Directory of Open Access Journals (Sweden)

    B. Naga Jyothi

    2016-06-01

    Full Text Available The variable latency speculative Han-Carlson adder is a newly proposed adder to perform high speed arithmetic operations. Han-Carlson adder gives accurate results with error detection when compared to other adders like Kogge-Stone adder. In this paper, number of parallel prefix adders can be sub divided into number of stages and perform arithmetic operations. By using the Xilinx 14.2 software, the design of Kogge-Stone adder and Han-Carlson adder is developed. This paper focuses on the implementation and simulation of 8-bit, 16-bit Kogge-stone adder and Han- Carlson adder based on Verilog code and compared for their performance in Xilinx. When compared to other adders the delay performance for Han Carlson adder is less and it reduces the complexity. It is concluded that the proposed adder is better in terms of computational delay. By using Brent –Kung and Kogge-stone adder the parallel prefix Han-Carlson adder also be proposed.

  15. Operation Manual of the high voltage generator of the Pelletron electron accelerator; Manual de operacion del generador de alto voltaje del acelerador de electrones Pelletron

    Energy Technology Data Exchange (ETDEWEB)

    Hernandez M, V.; Lopez V, H.; Alba P, U

    1988-04-15

    The first version of a manual to operate the generator of high voltage generator of the Pelletron electron accelerator built in the ININ is presented. Since this generator has several components and/or elements, the one manual present has the purpose that the armed one or maintenance of anyone on its parts, is carried out in an orderly and efficient way. (Author)

  16. Sensitivity Analysis for the CLIC Damping Ring Inductive Adder

    CERN Document Server

    Holma, Janne

    2012-01-01

    The CLIC study is exploring the scheme for an electron-positron collider with high luminosity and a nominal centre-of-mass energy of 3 TeV. The CLIC pre-damping rings and damping rings will produce, through synchrotron radiation, ultra-low emittance beam with high bunch charge, necessary for the luminosity performance of the collider. To limit the beam emittance blow-up due to oscillations, the pulse generators for the damping ring kickers must provide extremely flat, high-voltage pulses. The specifications for the extraction kickers of the CLIC damping rings are particularly demanding: the flattop of the output pulse must be 160 ns duration, 12.5 kV and 250 A, with a combined ripple and droop of not more than ±0.02 %. An inductive adder allows the use of different modulation techniques and is therefore a very promising approach to meeting the specifications. PSpice has been utilised to carry out a sensitivity analysis of the predicted output pulse to the value of both individual and groups of circuit compon...

  17. Preliminary Design of an Inductive Adder for CLIC Damping Rings

    CERN Document Server

    Holma, J

    2011-01-01

    The Compact Linear Collider (CLIC) study is exploring the scheme for an electron-positron collider with high luminosity and a nominal centre-of-mass energy of 3 TeV. The CLIC damping rings will produce ultra-low emittance beam, with high bunch charge, necessary for the luminosity performance of the collider. To limit the beam emittance blow-up due to oscillations, the pulse power modulators for the damping rings kickers must provide extremely flat, high-voltage, pulses: specifications call for a 160 ns duration flattop of 12.5 kV, 250 A, with a combined ripple and droop of not more than ±0.02 %. A solid-state modulator, the inductive adder, is a very promising approach to meeting the demanding specifications; this topology allows the use of both digital and analogue modulation. To effectively use modulation techniques to achieve such low ripple and droop requires an in-depth knowledge of the behaviour of the solid-state switching components and their gate drivers, as well as a good understanding of the overa...

  18. Testability Synthesis for Jumping Carry Adders

    Directory of Open Access Journals (Sweden)

    Chien-In Henry Chen

    2002-01-01

    Full Text Available Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area.

  19. Molecule-based photonically switched half-adder.

    Science.gov (United States)

    Andréasson, Joakim; Kodis, Gerdenis; Terazono, Yuichi; Liddell, Paul A; Bandyopadhyay, Subhajit; Mitchell, Reginald H; Moore, Thomas A; Moore, Ana L; Gust, Devens

    2004-12-15

    A molecule-based binary half-adder with optical inputs and outputs has been demonstrated. The half-adder consists of two photochromic organic molecules in solution and a third-harmonic-generating crystal. One substance acts as an AND Boolean logic gate and the other as an XOR gate. Inputs are laser pulses at 1064 or 532 nm that initiate photoisomerization reactions. Outputs are the optical absorbance of a fullerene radical anion (AND gate) and fluorescence of a porphyrin (XOR gate). The system carries out binary addition based on the laser input pulses. Half-adders in combination are capable of carrying out all mathematical operations necessary for digital computing.

  20. Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder

    DEFF Research Database (Denmark)

    Thomsen, Michael Kirkedal; Axelsen, Holger Bock

    2008-01-01

    The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. The CDKM-adder is a recent garbage-less reversible (quantum......(mk). We also show designs for garbage-less reversible set-less-than circuits. We compare the circuit costs of the CDKM and parallel adder in measures of circuit delay, width, gate and transistor count, and find that the parallelized adder offers significant speedups at realistic word sizes with modest...

  1. Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits

    Directory of Open Access Journals (Sweden)

    Vikas K. Saini

    2016-01-01

    Full Text Available Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR. In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA, Common Boolean Logic (CBL based adders, ripple carry adder (RCA, and Carry Look-Ahead Adder (CLA for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1 using Synopsis TetraMAX.

  2. Efficient carry skip Adder design using full adder and carry skip block based on reversible Logic

    OpenAIRE

    Varun Pratap Singh; Shiv Dayal; Manish Rai

    2015-01-01

    In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, binary full Adder with Design I and Design II are proposed. The performance analysis is verified using number of reversible gates, Garbage input/outputs, delay, number of logical calculations and Quantum Cost. According t...

  3. All-optical prefix tree adder with the help of terahertz optical asymmetric demultiplexer

    Institute of Scientific and Technical Information of China (English)

    Dilip Kumar Gayen; Tanay Chattopadhyay; Rajat Kumar Pal; Jitendra Nath Roy

    2011-01-01

    We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches. The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder. We also describe the principle and possibilities of the all-optical prefix tree adder. The theoretical model is presented and verified through numerical simulation. The new method promises higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.%@@ We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches.The prefix tree adder is useful in compound adder implementation.It is preferred over the ripple carry adder and the carry lookahead adder.We also describe the principle and possibilities of the all-optical prefix tree adder.The theoretical model is presented and verified through numerical simulation.The new method promises higher processing speed and accuracy.The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.

  4. Measurements on Prototype Inductive Adders with Ultra-Flat-Top Output Pulses for CLIC DR Kickers

    CERN Document Server

    Holma, J; Belver-Aguilar, C

    2014-01-01

    The CLIC study is investigating the technical feasibility of an electron-positron collider with high luminosity and a nominal centre-of-mass energy of 3 TeV. The CLIC pre-damping rings and damping rings (DRs) will produce ultra-low emittance beam with high bunch charge. To avoid beam emittance increase, the DR kicker systems must provide extremely flat, high-voltage, pulses. The specifications for the DR extraction kickers call for a 160 ns duration flat-top pulses of ±12.5 kV, 250 A, with a combined ripple and droop of not more than ±0.02 % (±2.5 V). An inductive adder is a very promising approach to meeting the specifications because this topology allows the use of both passive and analogue modulation methods to adjust the output waveform. Recently, two five-layer, 3.5 kV, prototype inductive adders have been built at CERN. The first of these has been used to test the passive and active analogue modulation methods to compensate voltage droop and ripple of the output pulses. Pulse waveforms have been reco...

  5. A pharmacological examination of venoms from three species of death adder (Acanthophis antarcticus, Acanthophis praelongus and Acanthophis pyrrhus).

    Science.gov (United States)

    Wickramaratna, J C; Hodgson, W C

    2001-01-01

    The common (A. antarcticus), northern (A. praelongus) and desert (A. pyrrhus) death adders are species belonging to the Acanthophis genus. The present study compared some pharmacological aspects of the venoms of these species and examined the in vitro efficacy of death adder antivenom. Neurotoxicity was determined by the time to produce 90% inhibition (t(90)) of indirect (0.1 Hz, 0.2 ms, supramaximal voltage) twitches in the chick biventer cervicis nerve-muscle (3-10 microg/ml) and mouse phrenic nerve-diaphragm (10 microg/ml) preparations. A. praelongus venom was significantly less neurotoxic than A. antarcticus venom but was not significantly different from A. pyrrhus venom. In the biventer muscle, all three venoms (3-10 microg/ml) abolished responses to exogenous ACh (1 mM) and carbachol (20 microM), but not KCl (40 mM), indicating activity at post-synaptic nicotinic receptors. All venoms (30 microg/ml) failed to produce significant inhibition of direct twitches (0.1 Hz, 2.0 ms, supramaximal voltage) in the chick biventer cervicis nerve-muscle preparation. However, A. praelongus (30 microg/ml) venom initiated a significant direct contracture of muscle, indicative of some myotoxic activity. The prior (10 min) administration of death adder antivenom (1 unit/ml), which is raised against A. antarcticus venom, markedly attenuated the twitch blockade produced by all venoms (10 microg/ml). Administration of antivenom (1.5 units/ml) at t(90) markedly reversed, over a period of 4 h, the inhibition of twitches produced by A. praelongus (3 microg/ml, 72+/-6% recovery) and A. pyrrhus (3 microg/ml, 51+/-9% recovery) but was less effective against A. antarcticus venom (3 microg/ml, 22+/-7% recovery). These results suggest that all three venoms contain postsynaptic neurotoxins. Death adder antivenom displayed differing efficacy against the in vitro neurotoxicity of the three venoms.

  6. Delay Efficient 32-Bit Carry-Skip Adder

    OpenAIRE

    Yu Shen Lin; Damu Radhakrishnan

    2008-01-01

    The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture ...

  7. REALIZATION OF MULTIPLEOPERAND ADDER-SUBTRACTOR BASED ON VEDIC MATHEMATICS

    Directory of Open Access Journals (Sweden)

    NEETA PANDEY

    2014-07-01

    Full Text Available This paper presents multiple-operand adder-subtractor based on Nikhilam Sutra of Vedic mathematics. The Sutra is adapted for binary operands. The hardware implementation uses carry save adders and a new 2’s exponent subtractor for faster operation and hardware reduction. The suitability of the theoretical proposition is demonstrated through exhaustive examples. The functionality of the circuit is verified through VHDL simulations. The synthesis results and comparisons with conventional methods are also included.

  8. A Review of the 0.09 uM Standard Full Adders

    OpenAIRE

    Vijay, V; Prathiba, J.; S. Niranjan Reddy; P. Praveen Kumar

    2012-01-01

    This paper presents power analysis of the seven full adder cells [6] reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existed standard full adders and the proposed full adders [6] are designed and showed the better result comparison. This paper describes how the proposed full adders [6] are better in contrast to the standard full adders. And ment...

  9. Design of Digital Adder Using Reversible Logic

    Directory of Open Access Journals (Sweden)

    Gowthami P

    2016-02-01

    Full Text Available Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design, Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them another main prominent application of reversible logic is Quantum computers where the quantum devices are essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible logic components. This makes the reversible logic as a one of the most promising research areas in the past few decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents the implementation of Ripple Carry Adder (RCA circuits using reversible logic gates are discussed.

  10. Low power adder based auditory filter architecture.

    Science.gov (United States)

    Rahiman, P F Khaleelur; Jayanthi, V S

    2014-01-01

    Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

  11. A transmon-based quantum half-adder scheme

    Science.gov (United States)

    Chatterjee, Dibyendu; Roy, Arijit

    2015-09-01

    A four-level qubit system is applied to realize quantum half-adder operation. The half-adder circuit is obtained in terms of a quantum CPHASE gate realized by the qubits comprised of four energy levels [C. P. Yang, Prog. Theor. Phys. 128, 587 (2012)], and such a CPHASE gate is demonstrated using the transmon. Commonly, higher energy levels are very sensitive and are easily perturbed by the noise sources. Compared to other qubit systems, the higher energy levels of the transmon are less prone to noise such as charge noise, flux noise and other noises. Further, the order of the dephasing time of the higher energy levels (third and fourth energy levels) is nearly the same as that of the lower energy levels of the transmon when the ratio between the Josephson energy and the charging energy ≫ 1. A system of three transmons coupled to a single high quality-factor superconducting coplanar resonator is demonstrated to obtain two- and three-qubit CPHASE gates which are in turn used to obtain the quantum half-adder operation. The main advantage of this quantum half-adder scheme is the reduction in the number of required elementary gates, leading to a significant increase in operational speed and robustness compared to the other existing half-adder schemes. The operational time of a complete half-adder operation is ˜ 37 ns. The methods presented in this article can also be implemented for more complicated quantum circuits.

  12. Area-Delay Efficient Binary Adders in QCA

    Directory of Open Access Journals (Sweden)

    Vikram. Gowda

    2016-05-01

    Full Text Available In this paper, a novel quantum-dot cellular automata (QCA adder design is presented that decrease the number of QCA cells compared to previously method designs. The proposed one-bit QCA adder is based on a new algorithm that requires only three majority gates and two inverters for the QCA addition. A novel 128-bit adder designed in QCA was implemented. It achieved speed performances higher than all the existing. QCA adders, with an area requirement comparable with the low RCA and CFA established. The novel adder operates in the RCA functional, but it could propagate a carry signal through a number of cascaded MGs significantly lower than conventional RCA adders. In adding together, because of the adopted basic logic and layout strategy, the number of clock cycles required for completing the explanation was limited. As transistors reduce in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot find much smaller than their current size. The quantum-dot cellular automata approach represents one of the possible solutions in overcome this physical limit, even though the design of logic modules in QCA is not forever straightforward

  13. Direct observation of atomic columns in a Bi-2223 polycrystal by aberration-corrected STEM using a low accelerating voltage

    Energy Technology Data Exchange (ETDEWEB)

    Nagai, Takuro, E-mail: nagai.takuro@nims.go.jp [National Institute for Materials Science (NIMS), Tsukuba, Ibaraki 305-0044 (Japan); Haruta, Mitsutaka [National Institute for Materials Science (NIMS), Tsukuba, Ibaraki 305-0044 (Japan); Institute for Chemical Research, Kyoto University, Uji, Kyoto 611-0011 (Japan); Kikuchi, Masashi [Sumitomo Electric Industries Ltd., Konohana-ku, Osaka 554-0024 (Japan); Zhang, Weizhu; Takeguchi, Masaki; Kimoto, Koji [National Institute for Materials Science (NIMS), Tsukuba, Ibaraki 305-0044 (Japan)

    2014-05-15

    Highlights: • We investigate a Ag-sheathed Bi-2223 wire by low-voltage aberration-corrected STEM. • Atomic displacements enable each layer to be continuous at edge grain boundaries. • The grains are terminated with deficient (Bi,Pb)–O layers at the other boundaries. • EELS mapping visualizes atomic columns in the intergrowth of Bi-2212 and 2234 phases. • HAADF analysis shows modulation of the occupancy of the (Bi,Pb) sites along [1 1 0]. - Abstract: Aberration correction in scanning transmission electron microscopy (STEM) enables an atomic-scale probe size of ∼0.1 nm at a low accelerating voltage of 80 kV that avoids knock-on damage in materials including light elements such as oxygen. We used this advanced method of microscopy to directly observe atomic columns in a (Bi,Pb){sub 2}Sr{sub 2}Ca{sub 2}Cu{sub 3}O{sub 10+δ} (Bi-2223) superconducting wire produced by a powder-in-tube method. Using the atomic-number (Z) contrast mechanism, incoherent high-angle annular dark-field (HAADF) imaging clearly showed the atomic columns. Atomic displacements toward the boundary with a maximum magnitude of ∼0.26 nm enable each atomic layer to be continuous at edge grain boundaries (EGBs). The grains tend to be terminated with deficient (Bi,Pb)–O single layers at c-axis twist boundaries (TWBs) and small-angle asymmetrical tilt boundaries (ATBs); a quantitative HAADF analysis showed that the occupancies of the (Bi,Pb) sites around these boundaries are ∼0.66 and ∼0.72, respectively. Electron energy-loss spectroscopy (EELS) mapping successfully visualized atomic columns in the half-unit cell intergrowth of (Bi,Pb){sub 2}Sr{sub 2}CaCu{sub 2}O{sub 8+δ} (Bi-2212) and (Bi,Pb){sub 2}Sr{sub 2}Ca{sub 3}Cu{sub 4}O{sub 12+δ} (Bi-2234) phases. Furthermore, the HAADF analysis indicated that the occupancy of the (Bi,Pb) sites is modulated between ∼0.88 and 1.0 along the diagonal direction of the primitive perovskite cell with the same period as the structural modulation.

  14. Differential B-dot and D-dot monitors for current and voltage measurements on a 20-MA 3-MV pulsed-power accelerator.

    Energy Technology Data Exchange (ETDEWEB)

    Shoup, Roy Willlam (ITT Industries, Albuquerque, NM); Gilliland, Terrance Leo (Ktech Corporation, Albuquerque, NM); Lee, James R.; Speas, Christopher Shane; Kim, Alexandre A. (High Current Electronic Institute, Russian Academy of Sciences, Tomsk, Russia); Struve, Kenneth William; York, Mathew William; Leifeste, Gordon T.; Rochau, Gregory Alan; Sharpe, Arthur William; Stygar, William A.; Porter, John Larry Jr.; Wagoner, Tim C. (Ktech Corporation, Albuquerque, NM); Reynolds, Paul Gerard (Team Specialty Products Corporation, Albuquerque, NM); Slopek, Jeffrey Scott (Ktech Corporation, Albuquerque, NM); Moore, William B. S.; Dinwoodie, Thomas Albert (Ktech Corporation, Albuquerque, NM); Woodring, R. M. (Ktech Corporation, Albuquerque, NM); Broyles, Robin Scott (Ktech Corporation, Albuquerque, NM); Mills, Jerry Alan; Melville, J. A. (Prodyn Technologies Incorporated, Albuquerque, NM); Dudley, M. E. (Ktech Corporation, Albuquerque, NM); Androlewicz, K. E. (Ktech Corporation, Albuquerque, NM); Mourning, R. W. (Ktech Corporation, Albuquerque, NM); Moore, J. K. (Ktech Corporation, Albuquerque, NM); Serrano, Jason Dimitri (Ktech Corporation, Albuquerque, NM); Ives, H. C. (EG& G, Albuquerque, NM); Johnson, M. F. (Team Specialty Products Corporation, Albuquerque, NM); Peyton, B. P. (Ktech Corporation, Albuquerque, NM); Leeper, Ramon Joe; Savage, Mark Edward; Donovan, Guy Louis; Spielman, R. B. (Ktech Corporation, Albuquerque, NM); Seamen, Johann F.

    2007-12-01

    We have developed a system of differential-output monitors that diagnose current and voltage in the vacuum section of a 20-MA 3-MV pulsed-power accelerator. The system includes 62 gauges: 3 current and 6 voltage monitors that are fielded on each of the accelerator's 4 vacuum-insulator stacks, 6 current monitors on each of the accelerator's 4 outer magnetically insulated transmission lines (MITLs), and 2 current monitors on the accelerator's inner MITL. The inner-MITL monitors are located 6 cm from the axis of the load. Each of the stack and outer-MITL current monitors comprises two separate B-dot sensors, each of which consists of four 3-mm-diameter wire loops wound in series. The two sensors are separately located within adjacent cavities machined out of a single piece of copper. The high electrical conductivity of copper minimizes penetration of magnetic flux into the cavity walls, which minimizes changes in the sensitivity of the sensors on the 100-ns time scale of the accelerator's power pulse. A model of flux penetration has been developed and is used to correct (to first order) the B-dot signals for the penetration that does occur. The two sensors are designed to produce signals with opposite polarities; hence, each current monitor may be regarded as a single detector with differential outputs. Common-mode-noise rejection is achieved by combining these signals in a 50-{Omega} balun. The signal cables that connect the B-dot monitors to the balun are chosen to provide reasonable bandwidth and acceptable levels of Compton drive in the bremsstrahlung field of the accelerator. A single 50-{omega} cable transmits the output signal of each balun to a double-wall screen room, where the signals are attenuated, digitized (0.5-ns/sample), numerically compensated for cable losses, and numerically integrated. By contrast, each inner-MITL current monitor contains only a single B-dot sensor. These monitors are fielded in opposite-polarity pairs. The two

  15. Note: A pulsed laser ion source for linear induction accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, H., E-mail: bamboobbu@hotmail.com [Institute of Fluid Physics, China Academy of Engineering Physics, P.O. Box 919-106, Mianyang 621900 (China); School of Physics, Peking University, Beijing 100871 (China); Zhang, K.; Shen, Y.; Jiang, X.; Dong, P.; Liu, Y.; Wang, Y.; Chen, D.; Pan, H.; Wang, W.; Jiang, W.; Long, J.; Xia, L.; Shi, J.; Zhang, L.; Deng, J. [Institute of Fluid Physics, China Academy of Engineering Physics, P.O. Box 919-106, Mianyang 621900 (China)

    2015-01-15

    We have developed a high-current laser ion source for induction accelerators. A copper target was irradiated by a frequency-quadrupled Nd:YAG laser (266 nm) with relatively low intensities of 10{sup 8} W/cm{sup 2}. The laser-produced plasma supplied a large number of Cu{sup +} ions (∼10{sup 12} ions/pulse) during several microseconds. Emission spectra of the plasma were observed and the calculated electron temperature was about 1 eV. An induction voltage adder extracted high-current ion beams over 0.5 A/cm{sup 2} from a plasma-prefilled gap. The normalized beam emittance measured by a pepper-pot method was smaller than 1 π mm mrad.

  16. Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology

    Directory of Open Access Journals (Sweden)

    Abbas Asadi Aghbolaghi

    2015-07-01

    Full Text Available The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and division. so, in this paper a new low power and high performance full adder cell has been proposed with the benefit of using carbon nano tube field effect transistors. The proposed design contains 12 CNTFET transistors which are connected in pass transistor logic style to make the desired functionality. Carbon Nano Tube Field Effect Transistor (CNTFET has modified electrical characteristics such as low power consumption and high speed in comparison with MOSFET transistor; The proposed design is simulated using Hspice software based on CNTFET model and 0.65V supply voltage. the simulations are done considering three different frequencies, and three different load capacitors. The simulation results, which demonstrated in tables and diagrams, proved the superiority of proposed design in terms of power consumption and performance (PDP compared to the existing counterparts.

  17. Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

    CERN Document Server

    Kumar, Manoj; Pandey, Sujata

    2012-01-01

    In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\\mu$W in 0.35$\\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542$\\mu$W. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35$\\mu$m CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit's shows better performance in terms of power consumption and transistor count.

  18. Partitioning and characterization of high speed adder structures in deep-submicron technologies

    Science.gov (United States)

    Estrada, Adrián; Sassaw, Gashaw; Jiménez, Carlos J.; Valencia, Manuel

    2007-05-01

    The availability of higher performance (in area, time and power consumption) and greater precision binary adders is a constant requirement in digital systems. Consequently, the design and characterization of adders and, most of all, their adaptation to the requisites of present-day deep-submicron technologies, are today still issues of concern. The binary adder structures in deep-submicron technologies must be revised to achieve the best balance between the number of bits in the adder and its delay, area and power consumption. It is therefore very important to make an effort to carefully optimize adder structures, thus obtaining improvements in digital systems. This communication presents the optimization of adder structures for implementations in deep-submicron technologies through their partitioning into blocks. This partitioning consists of dividing the number of input bits to the adder into several subsets of bits that will constitute the inputs to several adder structures of the same or of different types. The structures used to accomplish this study range from the more traditional types, such as the carry look ahead adder, the ripple carry adder or the carry select adder, to more innovative kinds, like the parallel prefix adders of the type proposed by Brent-Kung, Han-Carlson, Kogge-Stone or Ladner-Fischer. The analyses carried out allow the characterization of structures implemented in deep-submicron technologies for area, delay and power consumption parameters.

  19. FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

    Directory of Open Access Journals (Sweden)

    V. Kokilavani

    2015-01-01

    Full Text Available Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i full adders and 2 : 1 multiplexers, (ii full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

  20. On Design of Parity Preserving Reversible Adder Circuits

    Science.gov (United States)

    Haghparast, Majid; Bolhassani, Ali

    2016-12-01

    In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.

  1. Ultracompact all-optical full-adder and half-adder based on nonlinear plasmonic nanocavities

    Directory of Open Access Journals (Sweden)

    Xie Jingya

    2017-08-01

    Full Text Available Ultracompact chip-integrated all-optical half- and full-adders are realized based on signal-light induced plasmonic-nanocavity-modes shift in a planar plasmonic microstructure covered with a nonlinear nanocomposite layer, which can be directly integrated into plasmonic circuits. Tremendous nonlinear enhancement is obtained for the nanocomposite cover layer, attributed to resonant excitation, slow light effect, as well as field enhancement effect provided by the plasmonic nanocavity. The feature size of the device is <15 μm, which is reduced by three orders of magnitude compared with previous reports. The operating threshold power is determined to be 300 μW (corresponding to a threshold intensity of 7.8 MW/cm2, which is reduced by two orders of magnitude compared with previous reports. The intensity contrast ratio between two output logic states, “1” and “0,” is larger than 27 dB, which is among the highest values reported to date. Our work is the first to experimentally realize on-chip half- and full-adders based on nonlinear plasmonic nanocavities having an ultrasmall feature size, ultralow threshold power, and high intensity contrast ratio simultaneously. This work not only provides a platform for the study of nonlinear optics, but also paves a way to realize ultrahigh-speed signal computing chips.

  2. Low Power Reversible Parallel Binary Adder/Subtractor

    Directory of Open Access Journals (Sweden)

    Rangaraju H G

    2010-09-01

    Full Text Available In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design

  3. Novel designs for fault tolerant reversible binary coded decimal adders

    Science.gov (United States)

    Zhou, Ri-Gui; Li, Yan-Cheng; Zhang, Man-Qun

    2014-10-01

    Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.

  4. Low Power Reversible Parallel Binary Adder/Subtractor

    CERN Document Server

    Rangaraju, H G; Muralidhara, K N; Raja, K B; 10.5121/vlsic.2010.1303

    2010-01-01

    In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

  5. Low Power Reversible Parallel Binary Adder/Subtractor

    Directory of Open Access Journals (Sweden)

    Muralidhara K N

    2010-09-01

    Full Text Available In recent years, Reversible Logic is becoming more and more prominent technology having its applications inLow Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays animportant role when energy efficient computations are considered. In this paper, Reversible eight-bit ParallelBinary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three designapproaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbageinput/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractorwith Design III is efficient compared to Design I, Design II and existing design

  6. A compact control system to achieve stable voltage and low jitter trigger for repetitive intense electron-beam accelerator based on resonant charging

    Science.gov (United States)

    Qiu, Yongfeng; Liu, Jinliang; Yang, Jianhua; Cheng, Xinbing; Yang, Xiao

    2017-08-01

    A compact control system based on Delphi and Field Programmable Gate Array(FPGA) is developed for a repetitive intense electron-beam accelerator(IEBA), whose output power is 10GW and pulse duration is 160ns. The system uses both hardware and software solutions. It comprises a host computer, a communication module and a main control unit. A device independent applications programming interface, devised using Delphi, is installed on the host computer. Stability theory of voltage in repetitive mode is analyzed and a detailed overview of the hardware and software configuration is presented. High voltage experiment showed that the control system fulfilled the requests of remote operation and data-acquisition. The control system based on a time-sequence control method is used to keep constant of the voltage of the primary capacitor in every shot, which ensured the stable and reliable operation of the electron beam accelerator in the repetitive mode during the experiment. Compared with the former control system based on Labview and PIC micro-controller developed in our laboratory, the present one is more compact, and with higher precision in the time dimension. It is particularly useful for automatic control of IEBA in the high power microwave effects research experiments where pulse-to-pulse reproducibility is required.

  7. Design and Verification of Advanced Carry Select Adder

    Directory of Open Access Journals (Sweden)

    Guru Dixit Chepuri

    2014-05-01

    Full Text Available Design ofareaefficient data pathlogicsystems formsthelargestareasofresearch inVLSIsystem design.Indigital adders, thespeed of addition islimitedbythetimerequired totransmit a carrythroughtheadder.CarrySelectAdder (CSA isoneofthefastestadders usedinmanydata-processingprocessorstoperform fastarithmetic functions. Fromthestructure oftheCSA,itisclear thatthereisscopeforreducing thearea and powerintheCSA. This work usesasimpleandefficient gate-level modification todrasticallyreducetheareaandpower oftheCSA.Basedonthismodification 16,32,64 and128-bitsquare-root CSA(SQRT CSA architectureshavebeendevelopedandcomparedwith theregularSQRTCSAarchitecture. Theproposed designhasreducedarea and powerascompared withtheregular SQRTCSA.Thisworkestimates theperformanceof theproposed designsintermsofpower,areaand isimplementedusingXilinxISE and synthesized using cadence in 90nm technology.

  8. RECONSTRUCTION OF EXISTING LIVESTOCK FEED PRODUCTION PLANTS BY ADDING A HYDRAULIC ADDER

    Directory of Open Access Journals (Sweden)

    D. Kiš

    2007-06-01

    Full Text Available Recipes determine the quality of livestock feed and the hydraulic adders are one of the elements determining if the given recipe will be carried out. Generally, construction of existing adders does not allow accomplishment of that aim i.e. they do not meet recipe requirements. Consequently, researches which determined deviations in ingredient adding present with existing adders and with the experimental hydraulic adder were conducted. The research was conducted for two years (2005 and 2006 in two livestock feed factories in the Republic of Croatia on samples of feed mixtures for pigs weighing up to 15 and 25 kilos. Relative error was the means for comparison of weighing deviations between the hydraulic adder and the adders powered by means of an electric motor. Research results indicate that none of the two observed livestock feed production plants in 30 repetitions for two kinds of feed mixture showed a feed mixture weighing that would correspond to the specifications in the recipe. Additionally, hydraulic adders showed a greater precision in adding fish meal, extruded soybean and soybean meal when compared with the adders powered by means of an electric motor. However, the adders powered by means of an electric motor showed greater precision in adding corn. Based on the research results it can be concluded that using hydraulic adders instead of the adders powered by means of an electric motor will result in more accuracy in dosing ingredients with fine and middle granularity, whereas this can not be applied to dosing coarse grained ingredients.

  9. High Speed, Low Power, Area Efficient Mux-Add and Bec Based Implementation of Carry Select Adder.

    OpenAIRE

    Assistant Professor New Horizon College of Engineering

    2013-01-01

    Adder being the basic hardware block of any arithmetic operation, the major constraint in the field of signal processors, data processors to perform any operations are highly dependent on the adder performance of the circuit. The gate level implementation of the carry select adder (CSLA) and modified carry select adder has significantly reduced the area and power consumption which replaced the ripple carry adder (RCA) used in modified CSLA with MUX-ADD block has further reduced the power ...

  10. Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum Cost and Low Power Consumption

    Directory of Open Access Journals (Sweden)

    Nidhi

    2014-07-01

    Full Text Available The addition of two binary numbers is the important and most frequently used arithmetic process on microprocessors, digital signal processors (DSP, and data-processing application-specific integrated circuits (ASIC. Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI circuits. Their effective application is not trivial because a costly carry spread operation involving all operand bits has to be achieved. Many different circuit constructions for binary addition have been planned over the last decades, covering a wide range of presentation characteristics. In today era, reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL language.

  11. Morbidity and mortality following envenomation by the common night adder (Causus rhombeatus) in three dogs.

    Science.gov (United States)

    de Cramer, Kurt G M; van Bart, Garreth A; Huberts, Freek

    2012-10-12

    In South Africa dogs are frequently presented to veterinarians following snakebite. The offending snakes are usually puff adders (Bitis arietans), cobras (Naja spp.) and mambas (Dendroaspis spp.). Night adder (Causus rhombeatus) bites in dogs have not yet been reported in South Africa. This article deals with three cases of dogs bitten by night adders in which extensive tissue damage was noted and one fatality occurred. Night adder bites may be indistinguishable from puff adder bites. Non-specific treatment included addressing the hypovolaemia and swelling. Specific treatment involving immunotherapy using the South African polyvalent antivenom would be ineffective as it does not contain immunoglobulins against night adder venom. Veterinarians should also include night adders as the possible cause of dogs suffering from severe and painful swellings suspected to be due to snakebites.

  12. Morbidity and mortality following envenomation by the common night adder (Causus rhombeatus in three dogs

    Directory of Open Access Journals (Sweden)

    Kurt G.M. de Cramer

    2012-04-01

    Full Text Available In South Africa dogs are frequently presented to veterinarians following snakebite. The offending snakes are usually puff adders (Bitis arietans, cobras (Naja spp. and mambas (Dendroaspis spp.. Night adder (Causus rhombeatus bites in dogs have not yet been reported in South Africa. This article deals with three cases of dogs bitten by night adders in which extensive tissue damage was noted and one fatality occurred. Night adder bites may be indistinguishable from puff adder bites. Non-specific treatment included addressing the hypovolaemia and swelling. Specific treatment involving immunotherapy using the South African polyvalent antivenom would be ineffective as it does not contain immunoglobulins against night adder venom. Veterinarians should also include night adders as the possible cause of dogs suffering from severe and painful swellings suspected to be due to snakebites.

  13. Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

    Directory of Open Access Journals (Sweden)

    C. Senthilpari

    2017-02-01

    Full Text Available The 1-bit adder circuits are schematized using pass transistor logic (PTL technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed-Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC interconnect parameter such as capacitive impedance, inductive impedance, power factor sin ϕ, tan ϕ for applying frequency. The 32 bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin ϕ and tan ϕ.

  14. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

    Directory of Open Access Journals (Sweden)

    A. Kishore Kumar

    2013-01-01

    Full Text Available Asynchronous adiabatic logic (AAL is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

  15. Current-voltage and kinetic energy flux relations for relativistic field-aligned acceleration of auroral electrons

    Directory of Open Access Journals (Sweden)

    S. W. H. Cowley

    2006-03-01

    Full Text Available Recent spectroscopic observations of Jupiter's "main oval" auroras indicate that the primary auroral electron beam is routinely accelerated to energies of ~100 keV, and sometimes to several hundred keV, thus approaching the relativistic regime. This suggests the need to re-examine the classic non-relativistic theory of auroral electron acceleration by field-aligned electric fields first derived by Knight (1973, and to extend it to cover relativistic situations. In this paper we examine this problem for the case in which the source population is an isotropic Maxwellian, as also assumed by Knight, and derive exact analytic expressions for the field-aligned current density (number flux and kinetic energy flux of the accelerated population, for arbitrary initial electron temperature, acceleration potential, and field strength beneath the acceleration region. We examine the limiting behaviours of these expressions, their regimes of validity, and their implications for auroral acceleration in planetary magnetospheres (and like astrophysical systems. In particular, we show that for relativistic accelerating potentials, the current density increases as the square of the minimum potential, rather than linearly as in the non-relativistic regime, while the kinetic energy flux then increases as the cube of the potential, rather than as the square.

  16. Solid-state Marx based two-switch voltage modulator for the On-Line Isotope Mass Separator accelerator at the European Organization for Nuclear Research.

    Science.gov (United States)

    Redondo, L M; Silva, J Fernando; Canacsinh, H; Ferrão, N; Mendes, C; Soares, R; Schipper, J; Fowler, A

    2010-07-01

    A new circuit topology is proposed to replace the actual pulse transformer and thyratron based resonant modulator that supplies the 60 kV target potential for the ion acceleration of the On-Line Isotope Mass Separator accelerator, the stability of which is critical for the mass resolution downstream separator, at the European Organization for Nuclear Research. The improved modulator uses two solid-state switches working together, each one based on the Marx generator concept, operating as series and parallel switches, reducing the stress on the series stacked semiconductors, and also as auxiliary pulse generator in order to fulfill the target requirements. Preliminary results of a 10 kV prototype, using 1200 V insulated gate bipolar transistors and capacitors in the solid-state Marx circuits, ten stages each, with an electrical equivalent circuit of the target, are presented, demonstrating both the improved voltage stability and pulse flexibility potential wanted for this new modulator.

  17. Differential-output B-dot and D-dot monitors for current and voltage measurements on a 20-MA, 3-MV pulsed-power accelerator

    Directory of Open Access Journals (Sweden)

    T. C. Wagoner

    2008-10-01

    Full Text Available We have developed a system of differential-output monitors that diagnose current and voltage in the vacuum section of a 20-MA 3-MV pulsed-power accelerator. The system includes 62 gauges: 3 current and 6 voltage monitors that are fielded on each of the accelerator’s 4 vacuum-insulator stacks, 6 current monitors on each of the accelerator’s 4 outer magnetically insulated transmission lines (MITLs, and 2 current monitors on the accelerator’s inner MITL. The inner-MITL monitors are located 6 cm from the axis of the load. Each of the stack and outer-MITL current monitors comprises two separate B-dot sensors, each of which consists of four 3-mm-diameter wire loops wound in series. The two sensors are separately located within adjacent cavities machined out of a single piece of copper. The high electrical conductivity of copper minimizes penetration of magnetic flux into the cavity walls, which minimizes changes in the sensitivity of the sensors on the 100-ns time scale of the accelerator’s power pulse. A model of flux penetration has been developed and is used to correct (to first order the B-dot signals for the penetration that does occur. The two sensors are designed to produce signals with opposite polarities; hence, each current monitor may be regarded as a single detector with differential outputs. Common-mode-noise rejection is achieved by combining these signals in a 50-Ω balun. The signal cables that connect the B-dot monitors to the balun are chosen to provide reasonable bandwidth and acceptable levels of Compton drive in the bremsstrahlung field of the accelerator. A single 50-Ω cable transmits the output signal of each balun to a double-wall screen room, where the signals are attenuated, digitized (0.5-ns/sample, numerically compensated for cable losses, and numerically integrated. By contrast, each inner-MITL current monitor contains only a single B-dot sensor. These monitors are fielded in opposite-polarity pairs. The two

  18. Low Power 256-bit Modified Carry Select Adder

    Directory of Open Access Journals (Sweden)

    P. Ramani

    2014-09-01

    Full Text Available Carry Select Adder (CSLA is one of the high speed adders used in many computational systems to perform fast arithmetic operations. When compared to earlier Ripple Carry Adder and Carry Look Ahead Adder, Regular CSLA (R-CSLA is observed to provide optimized results in terms of area. This study proposes an efficient method which replaces the RCA using BEC. The modified CSLA architecture has been developed using gate-level modification to significantly reduce the delay and power of the CSLA. Based on this modification 8-, 16-, 32-, 64- and 128-bit Square-Root CSLA (SQRT CSLA architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design for 256-bit has reduced power and delay as compared with the regular SQRT CSLA. Designs were developed using structural Verilog module and synthesized using Xilinx ISE simulator and the implementation is done in cadence RTL compiler using 0.18 µm technology. For 256-bit addition in this study, it is proposed to simple gate level modification which significantly reduces the power by 19.4% when compared with R-CSLA. The result analysis shows that the proposed architecture achieves two folded advantages in terms of delay and power.

  19. Gluttony Causes Death in Juvenile Puff Adder Bitis arietans

    Directory of Open Access Journals (Sweden)

    G.V. Haagner

    1988-10-01

    Full Text Available Little is known about the predator/prey relationship in reptiles. The puff adder Bitis arietans is known to feed on a variety of food items, their diet consisting mainly of rodents, while birds, lizards and toads may be included (Broadley 1983, FitzSimons' Snakes of Southern Africa, Johannesburg: Delta Books. Pitman (1974, The Snakes of Uganda, Glasgow: Wheldon and Wesley recorded larger prey for puff adders in East Africa, while Robertson, Chapman & Chapman (1965, Puku 3: 149-170 reported on the diet of puff adders in Tanzania and Zambia, respectively. A gravid puff adder was collected in the Manyeleti Game Reserve in the Mhala district (24@38'S, 31@28'E of Gazankulu. On 12 February 1986 she gave birth to 28 young. The average length of the fry was 219,12 mm (S.D. 9,72 mm and their average mass 15, 72 g (S.D. 0,67 g. The young were separated from the mother and placed in another cage. The first ecdysis was com- pleted within 24 hours. After 10 days some newly weaned mice were placed in the cage. On subsequent inspection, it was found that a young snake gorged itself to death. The young puff adder contained three young mice with a total mass of 13,8 g, while the post-mortem mass of the snake was 14,2 g. Having swallowed 97,2 of its own body weight, the snake evidently died of suffocation. The specimen was preserved and is now part of the Transvaal Museum collection in Pretoria (TM 64088.

  20. Investigation of the Effects of Cathode Flow Fraction and Position on the Performance and Operation of the High Voltage Hall Accelerator

    Science.gov (United States)

    Kamhawi, Hani; Huang, Wensheng; Haag, Thomas

    2014-01-01

    The National Aeronautics and Space Administration (NASA) Science Mission Directorate In- Space Propulsion Technology office is sponsoring NASA Glenn Research Center (GRC) to develop a 4 kW-class Hall thruster propulsion system for implementation in NASA science missions. Tests were performed within NASA GRC Vacuum Facility 5 at background pressure levels that were six times lower than what has previously been attained in other vacuum facilities. A study was conducted to assess the impact of varying the cathode-to-anode flow fraction and cathode position on the performance and operational characteristics of the High Voltage Hall Accelerator (HiVHAc) thruster. In addition, the impact of injecting additional xenon propellant in the vicinity of the cathode was also assessed. Cathode-to-anode flow fraction sensitivity tests were performed for power levels between 1.0 and 3.9 kW. It was found that varying the cathode flow fraction from 5 to approximately 10% of the anode flow resulted in the cathode-to-ground voltage becoming more positive. For an operating condition of 3.8 kW and 500 V, varying the cathode position from a distance of closest approach to 600 mm away did not result in any substantial variation in thrust but resulted in the cathode-to-ground changing from -17 to -4 V. The change in the cathode-to-ground voltage along with visual observations indicated a change in how the cathode plume was coupling to the thruster discharge. Finally, the injection of secondary xenon flow in the vicinity of the cathode had an impact similar to increasing the cathode-to-anode flow fraction, where the cathode-to-ground voltage became more positive and discharge current and thrust increased slightly. Future tests of the HiVHAc thruster are planned with a centrally mounted cathode in order to further assess the impact of cathode position on thruster performance.

  1. Design, construction and operational results of the IGBT controlled solid state modulator high voltage power supply used in the high power RF systems of the Low Energy Demonstration Accelerator of the accelerator production of tritium (APT) project

    Energy Technology Data Exchange (ETDEWEB)

    Bradley, J.T. III; Rees, D.; Przeklasa, R.S. [Los Alamos National Lab., NM (United States); Scott, M.C. [Continental Electronics Corp., Dallas, TX (United States)

    1998-12-31

    The 1700 MeV, 100 mA Accelerator Production of Tritium (APT) Proton Linac will require 244 1 MW, continuous wave RF systems. 1 MW continuous wave klystrons are used as the RF source and each klystron requires 95 kV, 17 A of beam voltage and current. The cost of the DC power supplies is the single largest percentage of the total RF system cost. Power supply reliability is crucial to overall RF system availability and AC to DC conversion efficiency affects the operating cost. The Low Energy Demonstration Accelerator (LEDA) being constructed at Los Alamos National Laboratory (LANL) will serve as the prototype and test bed for APT. The design of the RF systems used in LEDA is driven by the need to field test high efficiency systems with extremely high reliability before APT is built. The authors present a detailed description and test results of one type of advanced high voltage power supply system using Insulated Gate Bipolar Transistors (IGBTs) that has been used with the LEDA High Power RF systems. The authors also present some of the distinctive features offered by this power supply topology, including crowbarless tube protection and modular construction which allows graceful degradation of power supply operation.

  2. High Speed Reconfigurable FIR Filter using Russian Peasant Multiplier with Sklansky Adder

    Directory of Open Access Journals (Sweden)

    K. Gunasekaran

    2014-12-01

    Full Text Available The Reconfigurable FIR filters are commonly used digital filters which find its major applications in digital signal processing and multi-standard wireless communications. The Direct form of FIR filter used in DSP application which consumes more area and power. To overcome this problem Multiplier Control Signal Decision (MCSD window schemes is incorporated into direct form FIR filter in order to dynamically change the filter order. Conventional reconfigurable FIR filter is designed using Russian Peasant Multiplier which consumes more area and delay due to poor performance of adder used in multiplication unit. In this study, modified reconfigurable FIR filter is designed to further reduce the area, power and time. In proposed Reconfigurable FIR filter, a Wallace adder is replaced by carry select adder with sklansky adder in Russian Peasant Multiplication technique. Hence, modified Reconfigurable FIR filter with carry select adder with sklansky adder consumes less area, delay and power than the conventional Reconfigurable FIR architecture with Russian Peasant Multiplication technique.

  3. Design of High-Speed Adders for Efficient Digital Design Blocks

    OpenAIRE

    Deepa Yagain; Vijaya Krishna A; Akansha Baliga

    2012-01-01

    The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Lin...

  4. Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

    Directory of Open Access Journals (Sweden)

    Gagandeep Singh

    2014-01-01

    Full Text Available In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP as compared to regular CSLA and modified CSLA.

  5. Optimized parity preserving quantum reversible full adder/subtractor

    Science.gov (United States)

    Haghparast, Majid; Bolhassani, Ali

    2016-07-01

    Reversible logic is one of the indispensable aspects of emerging technologies for reducing physical entropy gain, since reversible circuits do not lose information in the form of internal heat during computation. This paper aimed to initiate constructing parity preserving reversible circuits. A novel parity preserving reversible block, HB is presented. Then a new design of a cost-effective parity preserving reversible full adder/subtractor (PPFA/S) is proposed. Next, we suggested a new parity preserving binary to BCD converter. Finally, we proposed new realization of parity preserving reversible BCD adder. The proposed designs are cost-effective in terms of quantum cost and delay. All the scales are in the NANO-metric area.

  6. Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

    CERN Document Server

    Islam, Md Saiful; 10.3329/jbas.v32i2.2431

    2010-01-01

    Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

  7. Quantum Cost Efficient Reversible BCD Adder for Nanotechnology Based Systems

    CERN Document Server

    Islam, Md Saiful; Begum, Zerina

    2011-01-01

    Reversible logic allows low power dissipating circuit design and founds its application in cryptography, digital signal processing, quantum and optical information processing. This paper presents a novel quantum cost efficient reversible BCD adder for nanotechnology based systems using PFAG gate. It has been demonstrated that the proposed design offers less hardware complexity and requires minimum number of garbage outputs than the existing counterparts. The remarkable property of the proposed designs is that its quantum realization is given in NMR technology.

  8. Design of a 5-MA 100-ns linear-transformer-driver accelerator for wire array Z-pinch experiments

    Science.gov (United States)

    Zhou, Lin; Li, Zhenghong; Wang, Zhen; Liang, Chuan; Li, Mingjia; Qi, Jianmin; Chu, Yanyun

    2016-03-01

    The linear-transformer-driver (LTD) is a recently developed pulsed-power technology that shows great promise for a number of applications. These include a Z -pinch-driven fission-fusion-hybrid reactor that is being developed by the Chinese Academy of Engineering Physics. In support of the reactor development effort, we are planning to build an LTD-based accelerator that is optimized for driving wire-array Z -pinch loads. The accelerator comprises six modules in parallel, each of which has eight series 0.8-MA LTD cavities in a voltage-adder configuration. Vacuum transmission lines are used from the interior of the adder to the central vacuum chamber where the load is placed. Thus the traditional stack-flashover problem is eliminated. The machine is 3.2 m tall and 12 m in outer diameter including supports. A prototype cavity was built and tested for more than 6000 shots intermittently at a repetition rate of 0.1 Hz. A novel trigger, in which only one input trigger pulse is needed by utilizing an internal trigger brick, was developed and successfully verified in these shots. A full circuit modeling was conducted for the accelerator. The simulation result shows that a current pulse rising to 5.2 MA in 91 ns (10%-90%) can be delivered to the wire-array load, which is 1.5 cm in height, 1.2 cm in initial radius, and 1 mg in mass. The maximum implosion velocity of the load is 32 cm /μ s when compressed to 0.1 of the initial radius. The maximum kinetic energy is 78 kJ, which is 11.7% of the electric energy stored in the capacitors. This accelerator is supposed to enable a radiation energy efficiency of 20%-30%, providing a high efficient facility for research on the fast Z pinch and technologies for repetition-rate-operated accelerators.

  9. Costs of reproduction in a population of European adders.

    Science.gov (United States)

    Madsen, Thomas; Shine, Richard

    1993-07-01

    Eleven years of data on a small population of adders (Vipera berus) in southern Sweden provide quantitative information on the nature and degree of costs faced by reproducing animals. Reproduction imposes both an energy cost (measured by loss in body mass) and a mortality cost on adders of both sexes. The extent of the energy cost is broadly independent of levels of reproductive activity in males, but mortality costs are highest for large males, perhaps because they are more obvious to predators. In females, energy costs include a high 'fixed' (fecundity-independent) component, such that a large litter may cost little more to produce than would a small litter. Energy costs and mortality costs are separate in males, but inter-related in females. Mortality of reproducing females is high (40% per year), primarily because post-parturient females are emaciated and must forage actively, hence increasing their vulnerability to predators. Females producing relatively large litters (high Relative Clutch Mass) lose more body mass, and are less likely to survive after reproducing. The observed low reproductive frequencies of female adders may result from the presence of high fecundity-independent costs of reproduction.

  10. New low power adders in Self Resetting Logic with Gate Diffusion Input Technique

    Directory of Open Access Journals (Sweden)

    R. Uma

    2017-04-01

    Full Text Available The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logic with Gate Diffusion Input (SRLGDI. This logic family resolves the issues in dynamic circuits like charge sharing, charge leakage, short circuit power dissipation, monotonicity requirement and low output voltage. In the proposed design structure of SRLGDI, the pull down tree is implemented with Gate Diffusion Input (GDI with level restoration which apparently eliminated the conductance overlap between nMOS and pMOS devices, thereby reducing the short circuit power dissipation and providing High Output Voltage VoH. The output stage of SRLGDI has been incorporated with an inverter to produce both true and complementary output function. The Resistance Capacitance (RC delay model has been proposed to obtain the total delay of the circuit during precharge and evaluation phases. Using SRLGDI, the primitive cells and 3 different full adder circuits were designed and simulated in a 0.250 μm Complementary Metal Oxide Semiconductor (CMOS process technology. The simulated result demonstrates that the proposed SRLGDI logic family is superior in terms of speed and power consumption with respect to other logic families like Dynamic logic (DY, CMOS, Self Resetting CMOS (SRCMOS and GDI.

  11. An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

    Science.gov (United States)

    Ajitha, D.; Ramanaiah, K. V.; Sumalatha, V.

    2017-02-01

    The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

  12. Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum Cost and Low Power Consumption

    OpenAIRE

    Nidhi; Gurinderpal Singh

    2014-01-01

    The addition of two binary numbers is the important and most frequently used arithmetic process on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits. Their effective application is not trivial because a costly carry spread operation involving all operand bits has to be achieved. Many different circuit constru...

  13. An Optical Carry Chain Fast Adder

    Directory of Open Access Journals (Sweden)

    D. Al-Dabass

    1994-12-01

    Full Text Available A significant problem in Arithmetic Unit design and particularly for systolic arrays remains the speed attainable in achieving high speed addition. The root of the problem is carry propagation and a method is presented which is relatively independent of word length. The problem is addressed by the description of a suggested radical design involving a hybrid optical and electronic approach. The method of carry chain addition through pass gates is explained and a suggested implementation utilising Fabry-Perott resonators, optical waveguides and voltage controlled couplers is described. The design is suitable for n-stage modular expansion.

  14. Fast Multi Operand Decimal Adders using Digit Compressors with Decimal Carry Generation

    DEFF Research Database (Denmark)

    Dadda, Luigi; Nannarelli, Alberto

    We consider multi operand decimal adders designed with an architecture implementing first the addition of all the digits of each column (i.e. with the same decimal weight) and then combining in various ways such column sums for obtaining the final result. Different and efficient architectures can...... of cells. A comparison is also made between multi-operand adders of different architectures....

  15. Design and implementation of a microfluidic half adder chip based on double-stranded DNA.

    Science.gov (United States)

    Wang, Jing; Huang, Yourui

    2014-06-01

    In recent years, DNA computing has gained significant research interest. The design of a biochip with DNA computing as a carrier has become a key area in the development of a DNA molecular computer. The half adder, as the basic unit of various arithmetic units, has a complex structure that directly affects the overall complexity of a computer's structure. In this study, a half adder on a microfluidic chip is developed by means of bio-reaction. This technology is combined with a biochip and adopts glass and polydimethylsiloxane to fabricate a microscale hybrid chip. Using a DNA strand as an operand, realization of the half adder on a microfluidic chip is achieved by controlling the annealing and denaturation of double-stranded DNA. The computing results are rapidly and accurately obtained by detecting the presence of double-stranded DNA in a solution by agarose gel electrophoresis. The microfluidic half-adder chip accurately realizes half-adder computations and overcomes the shortcomings of traditional integrated circuit half adders, optical half adders, and chemical molecule half adders, such as complex structure, limited component size, and low accuracy.

  16. High Speed, Low Power, Area Efficient Mux-Add and Bec Based Implementation of Carry Select Adder.

    Directory of Open Access Journals (Sweden)

    Assistant Professor New Horizon College of Engineering

    2013-11-01

    Full Text Available Adder being the basic hardware block of any arithmetic operation, the major constraint in the field of signal processors, data processors to perform any operations are highly dependent on the adder performance of the circuit. The gate level implementation of the carry select adder (CSLA and modified carry select adder has significantly reduced the area and power consumption which replaced the ripple carry adder (RCA used in modified CSLA with MUX-ADD block has further reduced the power consumption by efficiently utilizing the area with faster performance.

  17. High Speed Carry Select Adder for ALU Blocks

    Directory of Open Access Journals (Sweden)

    J.Rama Krishna Reddy

    2013-06-01

    Full Text Available The regular SQRT CSLA consists of two RCA blocks with carry input as 0 and 1.The Final sum will be selected from multiplexers (Mux by the carry out generated by the pervious block. This paper, proposes an area and delay efficient carry select adder with logical reduction of excess redundant hardware. In the proposed architecture, we had implemented the RCA with carry input as 1, only with Mux, Or gate and And gate. For 16-bit regular SQRT CSLA there is a reduction of basic logic gates from 434 to 323.The delay is reduced by replacing Full-adder with half-adder in first bit of every RCA in theproposed architecture. This will reduces the number of Iterations required to get the final sum. The proposed architecture shows that there is reduction of area and delay. Based on this architecture, wedesigned 4-bit,8-bit,16-bit and 32-bit Square-root CSLA (SQRT CSLA and compared with the regular SQRT CSLA. In this work, we evaluated the performance of the proposed design in 90-ηm CMOS Technology in Cadence Tools. The result analysis shows that, the proposed SQRT CSLA of 4-bit, 8-bit 16- bit and 32-bit has a reduction of 31.74%, 30.13%, 21.92% and 21.76 % respectively compared with regular SQRT CSLA in area. The delay of Proposed SQRT CSLA of 4-bit,8-bit 16-bit and 32-bit are reduce by 27.47%, 17.23%, 14.32% and 11.63% respectively.

  18. Optimized reversible BCD adder using new reversible logic gates

    CERN Document Server

    Bhagyalakshmi, H R

    2010-01-01

    Reversible logic has received great attention in the recent years due to their ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications advanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. This paper presents an optimized reversible BCD adder using a new reversible gate. A comparative result is presented which shows that the proposed design is more optimized in terms of number of gates, number of garbage outputs and quantum cost than the existing designs.

  19. Integration Tests of the 4 kW-Class High Voltage Hall Accelerator Power Processing Unit with the HiVHAc and the SPT-140 Hall Effect Thrusters

    Science.gov (United States)

    Kamhawi, Hani; Pinero, Luis; Haag, Thomas; Huang, Wensheng; Ahern, Drew; Liang, Ray; Shilo, Vlad

    2016-01-01

    NASA's Science Mission Directorate is sponsoring the development of a 4 kW-class Hall propulsion system for implementation in NASA science and exploration missions. The main components of the system include the High Voltage Hall Accelerator (HiVHAc), an engineering model power processing unit (PPU) developed by Colorado Power Electronics, and a xenon flow control module (XFCM) developed by VACCO Industries. NASA Glenn Research Center is performing integrated tests of the Hall thruster propulsion system. This paper presents results from integrated tests of the PPU and XFCM with the HiVHAc engineering development thruster and a SPT-140 thruster provided by Space System Loral. The results presented in this paper demonstrate thruster discharge initiation along with open-loop and closed-loop control of the discharge current with anode flow for both the HiVHAc and the SPT-140 thrusters. Integrated tests with the SPT-140 thruster indicated that the PPU was able to repeatedly initiate the thruster's discharge, achieve steady state operation, and successfully throttle the thruster between 1.5 and 4.5 kW. The measured SPT-140 performance was identical to levels reported by Space Systems Loral.

  20. Evaluation of Components for the High Precision Inductive Adder for the CLIC Damping Rings

    CERN Document Server

    Holma, J

    2012-01-01

    The CLIC study is exploring the scheme for an electron-positron collider with high luminosity and a nominal centre-of-mass energy of 3 TeV. The CLIC damping rings will produce, through synchrotron radiation, ultra-low emittance beam with high bunch charge, necessary for the luminosity performance of the collider. To limit the beam emittance blow-up due to oscillations, the pulse generators for the damping ring kickers must provide extremely flat high-voltage pulses. The specifications for the extraction kickers of the CLIC damping rings are particularly demanding: the flattop of the output pulse must be 160 ns duration, 12.5 kV and 250 A, with a combined ripple and droop of not more than ±0.02 %. An inductive adder allows the use of different modulation techniques and is therefore a very promising approach to meeting the specifications. In addition to semiconductors working in their saturated region, semiconductors working in their linear region are needed for applying analogue modulation techniques. Simulat...

  1. Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique

    Directory of Open Access Journals (Sweden)

    Simran kaur

    2015-10-01

    Full Text Available With the active development of portable electronic devices, the need for low power dissipation, high speed and compact implementation, give rise to several research intentions. There are several design techniques used for the circuit configuration in VLSI systems but there are very few design techniques that gives the required extensibility. This paper describes the implementation of various adders and multipliers. The design approach proposed in the article is based on the GDI (Gate Diffusion Input technique. The paper also includes a comparative analysis of this low power method over CMOS design style with respect to power consumption, area complexity and delay. In this paper, a new GDI based cell designs are projected and are found to be efficient in terms of power consumption and area in comparison with existing CMOS based cell functionality. Power and delay has been calculated using Cadence Virtuoso tool at 45nm CMOS technology. The results obtained show better power and delay performance of the proposed designs at 1.3V supply voltage.

  2. A Low power and area efficient CLA adder design using Full swing GDI technique

    Directory of Open Access Journals (Sweden)

    Matcha Hemanth Kumar

    2015-10-01

    Full Text Available The low power VLSI design has an important role in designing of many electronic systems. While designing any combinational or sequential circuits, the important parameters like power consumption, implementation area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient data path logic systems forms the largest areas of research in VLSI system design. This paper presents a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI technique. The proposed CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI logic style suffers from some practical limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections. These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing restoration (SR transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results have shown a greater reduction in delay, power dissipation and area.

  3. Death adder envenoming causes neurotoxicity not reversed by antivenom--Australian Snakebite Project (ASP-16.

    Directory of Open Access Journals (Sweden)

    Christopher I Johnston

    Full Text Available BACKGROUND: Death adders (Acanthophis spp are found in Australia, Papua New Guinea and parts of eastern Indonesia. This study aimed to investigate the clinical syndrome of death adder envenoming and response to antivenom treatment. METHODOLOGY/PRINCIPAL FINDINGS: Definite death adder bites were recruited from the Australian Snakebite Project (ASP as defined by expert identification or detection of death adder venom in blood. Clinical effects and laboratory results were collected prospectively, including the time course of neurotoxicity and response to treatment. Enzyme immunoassay was used to measure venom concentrations. Twenty nine patients had definite death adder bites; median age 45 yr (5-74 yr; 25 were male. Envenoming occurred in 14 patients. Two further patients had allergic reactions without envenoming, both snake handlers with previous death adder bites. Of 14 envenomed patients, 12 developed neurotoxicity characterised by ptosis (12, diplopia (9, bulbar weakness (7, intercostal muscle weakness (2 and limb weakness (2. Intubation and mechanical ventilation were required for two patients for 17 and 83 hours. The median time to onset of neurotoxicity was 4 hours (0.5-15.5 hr. One patient bitten by a northern death adder developed myotoxicity and one patient only developed systemic symptoms without neurotoxicity. No patient developed venom induced consumption coagulopathy. Antivenom was administered to 13 patients, all receiving one vial initially. The median time for resolution of neurotoxicity post-antivenom was 21 hours (5-168. The median peak venom concentration in 13 envenomed patients with blood samples was 22 ng/mL (4.4-245 ng/mL. In eight patients where post-antivenom bloods were available, no venom was detected after one vial of antivenom. CONCLUSIONS/SIGNIFICANCE: Death adder envenoming is characterised by neurotoxicity, which is mild in most cases. One vial of death adder antivenom was sufficient to bind all circulating venom

  4. Death Adder Envenoming Causes Neurotoxicity Not Reversed by Antivenom - Australian Snakebite Project (ASP-16)

    Science.gov (United States)

    Johnston, Christopher I.; O'Leary, Margaret A.; Brown, Simon G. A.; Currie, Bart J.; Halkidis, Lambros; Whitaker, Richard; Close, Benjamin; Isbister, Geoffrey K.

    2012-01-01

    Background Death adders (Acanthophis spp) are found in Australia, Papua New Guinea and parts of eastern Indonesia. This study aimed to investigate the clinical syndrome of death adder envenoming and response to antivenom treatment. Methodology/Principal Findings Definite death adder bites were recruited from the Australian Snakebite Project (ASP) as defined by expert identification or detection of death adder venom in blood. Clinical effects and laboratory results were collected prospectively, including the time course of neurotoxicity and response to treatment. Enzyme immunoassay was used to measure venom concentrations. Twenty nine patients had definite death adder bites; median age 45 yr (5–74 yr); 25 were male. Envenoming occurred in 14 patients. Two further patients had allergic reactions without envenoming, both snake handlers with previous death adder bites. Of 14 envenomed patients, 12 developed neurotoxicity characterised by ptosis (12), diplopia (9), bulbar weakness (7), intercostal muscle weakness (2) and limb weakness (2). Intubation and mechanical ventilation were required for two patients for 17 and 83 hours. The median time to onset of neurotoxicity was 4 hours (0.5–15.5 hr). One patient bitten by a northern death adder developed myotoxicity and one patient only developed systemic symptoms without neurotoxicity. No patient developed venom induced consumption coagulopathy. Antivenom was administered to 13 patients, all receiving one vial initially. The median time for resolution of neurotoxicity post-antivenom was 21 hours (5–168). The median peak venom concentration in 13 envenomed patients with blood samples was 22 ng/mL (4.4–245 ng/mL). In eight patients where post-antivenom bloods were available, no venom was detected after one vial of antivenom. Conclusions/Significance Death adder envenoming is characterised by neurotoxicity, which is mild in most cases. One vial of death adder antivenom was sufficient to bind all circulating venom. The

  5. Determinants of reproductive success in female adders, Vipera berus.

    Science.gov (United States)

    Madsen, Thomas; Shine, Richard

    1992-10-01

    Female lifetime reproductive success in a small population of individually-marked adders in southern Sweden was studied over a period of seven years. Reproductive characteristics varied little from year to year and were consistent through time in individual females. Most females mature at four years of age and reproduce every two years. The total number of offspring produced by a female depends on her adult body size (and thus, litter size) and longevity (and thus, number of litters per lifetime). Adult body size in females is influenced mainly by subadult growth rates. Offspring size depends on maternal body size and a tradeoff between offspring size and offspring number. Maternal age does not affect litter sizes and offspring sizes except through ontogenetic changes in maternal body size.Survival of females after parturition is low because of the high energy costs of reproduction, compounded by low feeding rates of gravid females because of their sedentary behaviour at this time. About one-half of females produce only a single litter during their lifetimes, although some females live to produce four or five litters. On a proximate basis, rates of energy accumulation for growth (in subadults) and reproduction (in adults) may be the most important determinants of fitness in female adders.

  6. Cold hardiness in the boreal adder, Vipera berus.

    Science.gov (United States)

    Andersson, S; Johansson, L

    2001-01-01

    In three freezing experiments we examined the freeze tolerance in newborn adders, Vipera berus, from East-central Sweden. After a two to three hours exposure to freezing, ten out of eleven fast frozen snakes survived and recovered completely after being exposed to -3.1 degrees C on average. In the other two experiments with fast and slow freezing followed by long exposures lasting for 22-30 hours, none of the snakes survived average exposures at -4.8 degrees C or -3.8 degrees C, respectively. The glucose content of blood from frozen snakes was significantly higher than in unfrozen ones. The increase was small and its contribution to freeze tolerance doubtful. Compared to other freeze tolerant reptiles, the adder was categorised as virtually non freeze tolerant capable of surviving only a short exposure not colder than approximately -4 degrees C. Supercooling could play a role in winter survival but their precise choice of hibernation site is probably the most important.

  7. Low power adder based digital filter for QRS detector.

    Science.gov (United States)

    Murali, L; Chitra, D; Manigandan, T

    2014-01-01

    Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

  8. Quantitative transformation for implementation of adder circuits in physical systems.

    Science.gov (United States)

    Jones, Jeff; Whiting, James G H; Adamatzky, Andrew

    2015-08-01

    Computing devices are composed of spatial arrangements of simple fundamental logic gates. These gates may be combined to form more complex adding circuits and, ultimately, complete computer systems. Implementing classical adding circuits using unconventional, or even living substrates such as slime mould Physarum polycephalum, is made difficult and often impractical by the challenges of branching fan-out of inputs and regions where circuit lines must cross without interference. In this report we explore whether it is possible to avoid spatial propagation, branching and crossing completely in the design of adding circuits. We analyse the input and output patterns of a single-bit full adder circuit. A simple quantitative transformation of the input patterns which considers the total number of bits in the input string allows us to map the respective input combinations to the correct outputs patterns of the full adder circuit, reducing the circuit combinations from a 2:1 mapping to a 1:1 mapping. The mapping of inputs to outputs also shows an incremental linear progression, suggesting its implementation in a range of physical systems. We demonstrate an example implementation, first in simulation, inspired by self-oscillatory dynamics of the acellular slime mould P. polycephalum. We then assess the potential implementation using plasmodium of slime mould itself. This simple transformation may enrich the potential for using unconventional computing substrates to implement digital circuits.

  9. 正离子静电加速器高压电压稳定系统的分析%Analysis of high voltage stability system of positive ion accelerator

    Institute of Scientific and Technical Information of China (English)

    姜胜南

    2001-01-01

    对正离子静电加速器的电晕放电法高压电压稳定系统进行了较为细致的分析,同时也分析了另外两种稳压方法:电子枪法和控制喷电电流法。%This article mainly analyzes the corona drain high voltage stability system of the positive ion accelerator, and introduces the other two high voltage stability methods: the electron gun method and the controlling up-charge spray current method.

  10. Upper limb compartment syndrome after an adder bite:a case report

    Institute of Scientific and Technical Information of China (English)

    Mohamed Faouzi Hamdi; Sayed Baccari; Mehdi Daghfous; Lamjed Tarhouni

    2010-01-01

    Compartment syndrome after an adder bite is extremely rare, whose effects are only secondary to the cytotoxic and hemorrhagic effects of venom.Here we reported a case of compartment syndrome in the upper limb following an adder bite in the thenar eminence.Elevated compartment pressure was documented and immediate sur-gical fasciotomy was practiced.The patient achieved com-plete recovery with a good functional result.We discussed the controversies on fasciotomy and non-invasive measures in such a situation, and recommended intracompartmental pressure monitoring during the management of compart-ment syndrome following adder bites.

  11. Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)

    OpenAIRE

    Priya Meshram; Prof.Mamta Sarode

    2015-01-01

    In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converte...

  12. Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)

    OpenAIRE

    Priya Meshram; Prof.Mamta Sarode

    2015-01-01

    In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converte...

  13. Low Power, Area- Efficient and High Speed Fast Adder for Processing Element

    OpenAIRE

    J.Ponmalar; T.R.Sureshkumar; T.Kowsalya

    2015-01-01

    In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bi...

  14. Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System

    Directory of Open Access Journals (Sweden)

    Somayeh Timarchi

    2008-01-01

    Full Text Available Modulo 2n+1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and delay.

  15. Upper limb compartment syndrome after an adder bite: a case report.

    Science.gov (United States)

    Hamdi, Mohamed Faouzi; Baccari, Sayed; Daghfous, Mehdi; Tarhouni, Lamjed

    2010-04-01

    Compartment syndrome after an adder bite is extremely rare, whose effects are only secondary to the cytotoxic and hemorrhagic effects of venom. Here we reported a case of compartment syndrome in the upper limb following an adder bite in the thenar eminence. Elevated compartment pressure was documented and immediate surgical fasciotomy was practiced. The patient achieved complete recovery with a good functional result. We discussed the controversies on fasciotomy and non-invasive measures in such a situation, and recommended intracompartmental pressure monitoring during the management of compartment syndrome following adder bites.

  16. Reduction of RF accelerating voltage of Pohang Light Source-II superconducting RF cavity for stable top-up mode operation

    Science.gov (United States)

    Joo, Y.; Yu, I.; Park, I.; Chun, M. H.; Sohn, Y.

    2017-03-01

    The Pohang Light Source-II (PLS-II) is currently providing a top-up mode user-service operation with maximum available beam current of 400 mA and a beam emittance of below 10 nm-rad. The dimension of the beam bunch shortened to accomplish a low beam emittance of below 10 nm-rad from a high beam current of 400 mA increases the bunch charge density. As a result, the electron beam lifetime is significantly degraded and a high gradient of power is lost in the vacuum components of the storage ring. A study on how to reduce the bunch charge density without degrading beam emittance found that reducing the RF accelerating voltage (Vacc) can lower the bunch charge density by lengthening the bunch in the longitudinal direction. In addition, the Vacc required for stable operation with beam current of 400 mA can be reduced by lowering the external cavity quality factors (Qext values) of the superconducting cavities (SCs). To control the Qext values of SCs gradually without accessing the accelerator tunnel, a remote control motorized three-probe-tuner was installed in the transmission line of each SC. The optimum installation position of the three-probe-tuner was determined by using a finite-difference time-domain (FDTD) simulation and by experimenting on various installation positions of the three-probe-tuner. The Qext values of all the SCs were lowered to 1.40 × 105, and then, the Vacc required to store the beam current of 400 mA was decreased from 4.8 MV to 4.2 MV, which corresponds to 10% lengthening of the beam bunches. The stable operation with the reduced Vacc was confirmed during a 400 mA ten-day top-up mode user-service. Currently, the RF system of the PLS-II storage ring delivers the user-service operation with lowered Qext values to reduce the power loss at the vacuum components as well as the cryogenic heat load of SCs, and no significant problems have been found. This method of reducing the Vacc may also be applied in other synchrotron facilities.

  17. Envenoming following bites by the Balkan adder Vipera berus bosniensis - first documented case series from Bulgaria.

    Science.gov (United States)

    Westerström, Alexander; Petrov, Boyan; Tzankov, Nikolay

    2010-12-01

    We report the first detailed accounts of bites by the Balkan adder, Vipera berus bosniensis from Bulgaria. Documentation of bites by this subspecies is very rare in the literature and most available accounts are from the northern limit of its distribution. V. berus bosniensis is considered to possess neurotoxic venom but little evidence has hitherto been available to support this supposition. In this case series symptoms typical of adder bites developed including oedema, nausea, dizziness, lymphangitis, vomiting, and diarrhoea together with aberrant symptoms such as diplopia and ptosis that confirm the presence of neurotoxic venom in Balkan adders. In addition, unusual and atypical symptoms of adder bites such as painless bites and muscle cramps appeared. The inadequate treatment in hospital and the remote habitats in which this species is encountered are potential sources of complication.

  18. Recoded and nonrecoded trinary signed-digit adders and multipliers with redundant-bit representations.

    Science.gov (United States)

    Cherri, A K; Alam, M S

    1998-07-10

    Highly-efficient two-step recoded and one-step nonrecoded trinary signed-digit (TSD) carry-free adders-subtracters are presented on the basis of redundant-bit representation for the operands' digits. It has been shown that only 24 (30) minterms are needed to implement the two-step recoded (the one-step nonrecoded) TSD addition for any operand length. Optical implementation of the proposed arithmetic can be carried out by use of correlation- or matrix-multiplication-based schemes, saving 50% of the system memory. Furthermore, we present four different multiplication designs based on our proposed recoded and nonrecoded TSD adders. Our multiplication designs require a small number of reduced minterms to generate the multiplication partial products. Finally, a recently proposed pipelined iterative-tree algorithm can be used in the TSD adders-multipliers; consequently, efficient use of all available adders can be made.

  19. Design of efficient full adder in quantum-dot cellular automata.

    Science.gov (United States)

    Sen, Bibhash; Rajoria, Ayush; Sikdar, Biplab K

    2013-01-01

    Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μ m(2)) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

  20. Design of Efficient Full Adder in Quantum-Dot Cellular Automata

    Directory of Open Access Journals (Sweden)

    Bibhash Sen

    2013-01-01

    Full Text Available Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA, a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock with high compaction (0.01 μm2 for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

  1. Design and Analysis of a New Carbon Nanotube Full Adder Cell

    Directory of Open Access Journals (Sweden)

    M. H. Ghadiry

    2011-01-01

    Full Text Available A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

  2. Implementation of Low Power And Propagation Delay Optimized Multiplexers Based Full Adder Cells

    Directory of Open Access Journals (Sweden)

    J. Mallikarjuna Rao

    2014-05-01

    Full Text Available Power consumption has emerged as a primary design constraint for integrated circuits (ICs. In the Nanometer technology regime, leakage power has become a major component of total power [1]. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering the power consumption of Full adder. So the full adder designs with low power characteristics are becoming more popular these days. In this paper we are going to design four different types of Full adder these are applied to 32-bit RCA .The four designs will be developed using Verilog HDL evaluating the performance using Cadence.

  3. High-performance full adder architecture in quantum-dot cellular automata

    Directory of Open Access Journals (Sweden)

    Hamid Rashidi

    2017-06-01

    Full Text Available Quantum-dot cellular automata (QCA is a new and promising computation paradigm, which can be a viable replacement for the complementary metal–oxide–semiconductor technology at nano-scale level. This technology provides a possible solution for improving the computation in various computational applications. Two QCA full adder architectures are presented and evaluated: a new and efficient 1-bit QCA full adder architecture and a 4-bit QCA ripple carry adder (RCA architecture. The proposed architectures are simulated using QCADesigner tool version 2.0.1. These architectures are implemented with the coplanar crossover approach. The simulation results show that the proposed 1-bit QCA full adder and 4-bit QCA RCA architectures utilise 33 and 175 QCA cells, respectively. Our simulation results show that the proposed architectures outperform most results so far in the literature.

  4. A NOVEL DESIGN OF MULTIPLEXER BASED FULL-ADDER CELL FOR POWER AND PROPAGATION DELAY OPTIMIZATIONS

    Directory of Open Access Journals (Sweden)

    G. RAMANA MURTHY

    2013-12-01

    Full Text Available This paper presents a novel high-speed and high-performance multiplexer based full adder cell for low-power applications. The proposed full adder is composed of two separate modules with identical hardware configurations that generate Sum and Carry signals in a parallel manner. The proposed adder circuit has an advantage in terms of short critical path when compared with various existing previous designs. Comprehensive experiments were performed in various situations to evaluate the performance of the proposed design. Simulations were performed by Microwind 2 VLSI CAD tool for LVS and BSIM 4 for parametric analysis of various feature sizes. The simulation results demonstrate clearly the improvement of the proposed design in terms of lower power dissipation, less propagation delay, less occupying area and low power delay product (PDP compared to other widely used existing full adder circuits.

  5. A new species of death adder (Acanthophis: Serpentes: Elapidae) from north-western Australia.

    Science.gov (United States)

    Maddock, Simon T; Ellis, Ryan J; Doughty, Paul; Smith, Lawrence A; Wüster, Wolfgang

    2015-08-28

    Australian death adders (genus Acanthophis) are highly venomous snakes with conservative morphology and sit-and-wait predatory habits, with only moderate taxonomic diversity that nevertheless remains incompletely understood. Analyses of mitochondrial and nuclear gene sequences and morphological characteristics of death adders in northern Australia reveal the existence of a new species from the Kimberley region of Western Australia and the Northern Territory, which we describe as Acanthophis cryptamydros sp. nov. Although populations from the Kimberley were previously considered conspecific with Northern Territory death adders of the A. rugosus complex, our mtDNA analysis indicates that its closest relatives are desert death adders, A. pyrrhus. We found that A. cryptamydros sp. nov. is distinct in both mtDNA and nDNA analysis, and possesses multiple morphological characteristics that allow it to be distinguished from all other Acanthophis species. This study further supports the Kimberley region as an area with high endemic biodiversity.

  6. A 485ps 64-Bit Parallel Adder in 0.18μm CMOS

    Institute of Scientific and Technical Information of China (English)

    Dong-Yu Zheng; Yan Sun; Shao-Qing Li; Liang Fang

    2007-01-01

    This paper presents an optimized 64-bit parallel adder.Sparse-tree architecture enables low carry-merge fan-outs and inter-stage wiring complexity.Single-rail and semi-dynamic circuit improves operation speed.Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process.It achieves the goal of higher speed and lower power.

  7. 医科达加速器高压部分的工作原理及应用%Research on the principle and application of high voltage of the Elekta accelerator

    Institute of Scientific and Technical Information of China (English)

    张海成; 王健红

    2014-01-01

    Objective: Through getting acknowledge of the High-voltage of medical linear accelerator, it makes it possible for the relative medical workers to do a quick reaction to the repairmen and maintenance to the accelerator, and to maintain the machine to a good performance efficiently. While through understanding the application situation and development of accelerator, we could do a better choice at the terms of choosing an accelerator for hospital which meet the basic requirements and accuracy. Methods:Using the block diagram to introduce the main part of High-voltage of medical linear accelerator, and especially introduce the charging pinciple of charging transformer and the charge and discharge of PFN. The accelerator plays a vital fuction at radiation therapy, and we introduce the accelerator application in various fields and the development situation of technology application. Results:It’s significant to know the working principle of High-voltage as it’s helpful to ensure whether the machine works normal or not and to diagnose faults in it. Conclusion:In addition, through understanding the application situation and the development of accelerator, we could choose an appropriate accelerator for our hospital.%目的:通过掌握医用直线加速器高压部分的工作原理,使医技等相关工作人员在加速器高压部分出现故障时做出快速判断、修理和维护,有效保持加速器的正常性能,确保其正常使用。方法:了解医用直线加速器的主要组成部分,通过框图重点介绍加速器高压部分,着重讨论充电变压器的充电原理和PFN的充放电原理。结果:通过掌握医用直线加速器高压部分的工作原理对保证加速器的使用性能正常和判断高压部分的故障原因有着重要意义。结论:了解加速器的应用进展情况可更好为医院选择合适的医用直线加速器。

  8. Bit-Serial Adder Based on Quantum Dots

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Mathew

    2003-01-01

    A proposed integrated circuit based on quantum-dot cellular automata (QCA) would function as a bit-serial adder. This circuit would serve as a prototype building block for demonstrating the feasibility of quantum-dots computing and for the further development of increasingly complex and increasingly capable quantum-dots computing circuits. QCA-based bit-serial adders would be especially useful in that they would enable the development of highly parallel and systolic processors for implementing fast Fourier, cosine, Hartley, and wavelet transforms. The proposed circuit would complement the QCA-based circuits described in "Implementing Permutation Matrices by Use of Quantum Dots" (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42 and "Compact Interconnection Networks Based on Quantum Dots" (NPO-20855), which appears elsewhere in this issue. Those articles described the limitations of very-large-scale-integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCA-based signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. To enable a meaningful description of the proposed bit-serial adder, it is necessary to further recapitulate the description of a quantum-dot cellular automation from the first-mentioned prior article: A quantum-dot cellular automaton contains four quantum dots positioned at the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the

  9. An Improved Structure Of Reversible Adder And Subtractor

    Directory of Open Access Journals (Sweden)

    Aakash Gupta

    2013-03-01

    Full Text Available In today’s world everyday a new technology which is faster, smaller and more complex than its predecessor is being developed. The increased number of transistors packed onto a chip of a conventional system results in increased power consumption that is why Reversible logic has drawn attention of Researchers due to its less heat dissipating characteristics. Reversible logic can be imposed over applications such as quantum computing, optical computing, quantum dot cellular automata, low power VLSI circuits, DNA computing. This paper presents the reversible combinational circuit of adder, subtractor and parity preserving subtractor. The suggested circuit in this paper are designed using Feynman, Double Feynman and MUX gates which are better than the existing one in literature in terms of Quantum cost, Garbage output and Total logical calculations.

  10. The adder (Vipera berus) in Southern Altay Mountains: population characteristics, distribution, morphology and phylogenetic position.

    Science.gov (United States)

    Cui, Shaopeng; Luo, Xiao; Chen, Daiqiang; Sun, Jizhou; Chu, Hongjun; Li, Chunwang; Jiang, Zhigang

    2016-01-01

    As the most widely distributed snake in Eurasia, the adder (Vipera berus) has been extensively investigated in Europe but poorly understood in Asia. The Southern Altay Mountains represent the adder's southern distribution limit in Central Asia, whereas its population status has never been assessed. We conducted, for the first time, field surveys for the adder at two areas of Southern Altay Mountains using a combination of line transects and random searches. We also described the morphological characteristics of the collected specimens and conducted analyses of external morphology and molecular phylogeny. The results showed that the adder distributed in both survey sites and we recorded a total of 34 sightings. In Kanas river valley, the estimated encounter rate over a total of 137 km transects was 0.15 ± 0.05 sightings/km. The occurrence of melanism was only 17%. The small size was typical for the adders in Southern Altay Mountains in contrast to other geographic populations of the nominate subspecies. A phylogenetic tree obtained by Bayesian Inference based on DNA sequences of the mitochondrial cytochrome b (1,023 bp) grouped them within the Northern clade of the species but failed to separate them from the subspecies V. b. sachalinensis. Our discovery extends the distribution range of V. berus and provides a basis for further researches. We discuss the hypothesis that the adder expands its distribution border to the southwest along the mountains' elevation gradient, but the population abundance declines gradually due to a drying climate.

  11. Towards constructing multi-bit binary adder based on Belousov-Zhabotinsky reaction.

    Science.gov (United States)

    Zhang, Guo-Mao; Wong, Ieong; Chou, Meng-Ta; Zhao, Xin

    2012-04-28

    It has been proposed that the spatial excitable media can perform a wide range of computational operations, from image processing, to path planning, to logical and arithmetic computations. The realizations in the field of chemical logical and arithmetic computations are mainly concerned with single simple logical functions in experiments. In this study, based on Belousov-Zhabotinsky reaction, we performed simulations toward the realization of a more complex operation, the binary adder. Combining with some of the existing functional structures that have been verified experimentally, we designed a planar geometrical binary adder chemical device. Through numerical simulations, we first demonstrated that the device can implement the function of a single-bit full binary adder. Then we show that the binary adder units can be further extended in plane, and coupled together to realize a two-bit, or even multi-bit binary adder. The realization of chemical adders can guide the constructions of other sophisticated arithmetic functions, ultimately leading to the implementation of chemical computer and other intelligent systems.

  12. Towards constructing multi-bit binary adder based on Belousov-Zhabotinsky reaction

    Science.gov (United States)

    Zhang, Guo-Mao; Wong, Ieong; Chou, Meng-Ta; Zhao, Xin

    2012-04-01

    It has been proposed that the spatial excitable media can perform a wide range of computational operations, from image processing, to path planning, to logical and arithmetic computations. The realizations in the field of chemical logical and arithmetic computations are mainly concerned with single simple logical functions in experiments. In this study, based on Belousov-Zhabotinsky reaction, we performed simulations toward the realization of a more complex operation, the binary adder. Combining with some of the existing functional structures that have been verified experimentally, we designed a planar geometrical binary adder chemical device. Through numerical simulations, we first demonstrated that the device can implement the function of a single-bit full binary adder. Then we show that the binary adder units can be further extended in plane, and coupled together to realize a two-bit, or even multi-bit binary adder. The realization of chemical adders can guide the constructions of other sophisticated arithmetic functions, ultimately leading to the implementation of chemical computer and other intelligent systems.

  13. HARDWARE MODELING OF BINARY CODED DECIMAL ADDER IN FIELD PROGRAMMABLE GATE ARRAY

    Directory of Open Access Journals (Sweden)

    Muhammad Ibn Ibrahimy

    2013-01-01

    Full Text Available There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA based hardware implementation of Binary Coded Decimal (BCD adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA and Ripple Carry (RC adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device.

  14. An accelerator facility for WDM, HEDP, and HIF investigations in Nazarbayev University

    Science.gov (United States)

    Kaikanov, M.; Baigarin, K.; Tikhonov, A.; Urazbayev, A.; Kwan, J. W.; Henestroza, E.; Remnev, G.; Shubin, B.; Stepanov, A.; Shamanin, V.; Waldron, W. L.

    2016-05-01

    Nazarbayev University (NU) in Astana, Kazakhstan, is planning to build a new multi-MV, ∼10 to several hundred GW/cm2 ion accelerator facility which will be used in studies of material properties at extreme conditions relevant to ion-beam-driven inertial fusion energy, and other applications. Two design options have been considered. The first option is a 1.2 MV induction linac similar to the NDCX-II at LBNL, but with modifications, capable of heating a 1 mm spot size thin targets to a few eV temperature. The second option is a 2 - 3 MV, ∼200 kA, single-gap-diode proton accelerator powered by an inductive voltage adder. The high current proton beam can be focused to ∼1 cm spot size to obtain power densities of several hundred GW/cm2, capable of heating thick targets to temperatures of tens of eV. In both cases, a common requirement to achieving high beam intensity on target and pulse length compression is to utilize beam neutralization at the final stage of beam focusing. Initial experiments on pulsed ion beam neutralization have been carried out on a 0.3 MV, 1.5 GW single-gap ion accelerator at Tomsk Polytechnic University with the goal of creating a plasma region in front of a target at densities exceeding ∼1012 cm-3.

  15. How a heavy-bodied snake strikes quickly: high-power axial musculature in the puff adder (Bitis arietans).

    Science.gov (United States)

    Young, Bruce A

    2010-02-01

    Despite being large, heavy-bodied snakes, puff adders (Bitis arietans) are capable of achieving strike velocities and accelerations similar to, or greater than, those of much smaller snakes (means of 2.6 and 72 m/sec(2), respectively). The mechanistic basis of the strike was examined using high-speed digital videography, coupled with electromyographic (EMG) analysis, of the two main extensors of the vertebral column, the semispinalis and longissimus. Although the strike involves the rapid extension of preformed body curves, the extensor muscles were not electrically active during body extension. The vertebral extensor muscles exhibited bursts of electrical activity before the onset of movement-and quantified features of these EMG signals were significantly related to kinematic aspects of the strike (e.g., acceleration)-however, this electrical activity terminated shortly (approximately 50 msec) before the onset of movement. It is hypothesized that the prestrike activity of the extensor muscles functions to place the (extensive) musculo-tendon complex of the snake's epaxial muscles under tension, and that the displacement of the body during the strike is due to the elastic recoil of this musculo-tendon complex. Incorporation of this type of elastic recoil would increase the power output of the vertebral extensors. Power amplification of the vertebral extensors may be an evolutionary necessity if a large, heavy-bodied snake, like B. arietans, is going to achieve rapid acceleration during the strike.

  16. Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders

    Directory of Open Access Journals (Sweden)

    M.Bharathi

    2012-05-01

    Full Text Available Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardwarecomplexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.

  17. FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

    Directory of Open Access Journals (Sweden)

    David H. K. Hoe

    2013-01-01

    Full Text Available This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.

  18. The adder (Vipera berus in Southern Altay Mountains: population characteristics, distribution, morphology and phylogenetic position

    Directory of Open Access Journals (Sweden)

    Shaopeng Cui

    2016-08-01

    Full Text Available As the most widely distributed snake in Eurasia, the adder (Vipera berus has been extensively investigated in Europe but poorly understood in Asia. The Southern Altay Mountains represent the adder’s southern distribution limit in Central Asia, whereas its population status has never been assessed. We conducted, for the first time, field surveys for the adder at two areas of Southern Altay Mountains using a combination of line transects and random searches. We also described the morphological characteristics of the collected specimens and conducted analyses of external morphology and molecular phylogeny. The results showed that the adder distributed in both survey sites and we recorded a total of 34 sightings. In Kanas river valley, the estimated encounter rate over a total of 137 km transects was 0.15 ± 0.05 sightings/km. The occurrence of melanism was only 17%. The small size was typical for the adders in Southern Altay Mountains in contrast to other geographic populations of the nominate subspecies. A phylogenetic tree obtained by Bayesian Inference based on DNA sequences of the mitochondrial cytochrome b (1,023 bp grouped them within the Northern clade of the species but failed to separate them from the subspecies V. b. sachalinensis. Our discovery extends the distribution range of V. berus and provides a basis for further researches. We discuss the hypothesis that the adder expands its distribution border to the southwest along the mountains’ elevation gradient, but the population abundance declines gradually due to a drying climate.

  19. Implementation of High Performance Fir Filter Using Low Power Multiplier and Adder

    Directory of Open Access Journals (Sweden)

    Sweety Kashyap,

    2014-01-01

    Full Text Available The ever increasing growth in laptop and portable systems in cellular networks has intensified the research efforts in low power microelectronics. Now a day, there are many portable applications requiring low power and high throughput than ever before. Thus, low power system design has become a significant performance goal. So this paper is face with more constraints: high speed, high throughput, and at the same time, consumes as minimal power as possible. The Finite Impulse Response (FIR Filter is the important component for designing an efficient digital signal processing system. So, in this paper author trying, a FIR filter is constructing, which is efficient not only in terms of power and speed but also in terms of delay. When consider the elementary structure of an FIR filter, it is found that it is a combination of multipliers and delays, which in turn are the combination of adders. . This paper presents an efficient implementation and analysis for performance evaluation of multiplier and adder to minimize the consumption of energy during multiplication and addition methodology to improve the performance by compares different type of Multipliers and adder, respectively. By using, power comparison result of adders and multiplier, choice low power adder and multiplier to implementation of high performance FIR filter.

  20. An $\\Theta(\\sqrt{n})$-depth Quantum Adder on a 2D NTC Quantum Computer Architecture

    CERN Document Server

    Choi, Byung-Soo

    2010-01-01

    In this work, we propose an adder for the 2D NTC architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computation of the final carry for each register position. In the last phase, each column, except the first one, generates the summation output using this column-level carry. The depth and the number of qubits of the proposed adder are $\\Theta(\\sqrt{n})$ and O(n), respectively. The proposed adder executes faster than the adders designed for the 1D NTC architecture when the length of the input registers $n$ is larger than 58.

  1. Design of RSFQ wave pipelined Kogge-Stone Adder and developing custom compound gates

    Science.gov (United States)

    Ozer, M.; Eren Çelik, M.; Tukel, Y.; Bozbey, A.

    2014-09-01

    Since the invention of computers, the calculation of arithmetic and logic operations using digital circuits has been one of the leading problems in processor designs. The challenge has been to compute more operations with less clock cycles by using additional specific logic circuits. One of the most fundamental processes is addition; in which the carry bit should be transferred from the least significant bit to the most significant one. A wide range of digital circuit designs have been sustained for specialized faster addition operation. One of these adder algorithms is Kogge Stone Adder which does faster calculation with fewer levels and minimum fan-out compared to today’s adders despite the only disadvantage of having an excessive amount of wiring. In this study, a custom Rapid Single Flux Quantum (RSFQ) based, wave pipelined, Kogge Stone Adder is proposed to be used later in an Arithmetic Logic Unit (ALU). Two different design methodologies have been considered. In the first approach, we used standard logic gates for the whole adder design. In the second approach, utilization to compound gate design with adjustments over component parameters is done by using Particle Swarm Optimization and Statistical Timing Analysis Tools, to increase both efficiency and bias margin.

  2. Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders

    Directory of Open Access Journals (Sweden)

    M.Bharathi

    2012-04-01

    Full Text Available Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.

  3. 18 CFR 35.22 - Limits for percentage adders in rates for transmission services; revision of rate schedules...

    Science.gov (United States)

    2010-04-01

    ... 18 Conservation of Power and Water Resources 1 2010-04-01 2010-04-01 false Limits for percentage adders in rates for transmission services; revision of rate schedules, tariffs or service agreements. 35... Filing Requirements § 35.22 Limits for percentage adders in rates for transmission services; revision...

  4. Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Ramiro Taco

    2015-01-01

    Full Text Available The gate level body biasing (GLBB is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations.

  5. Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low Power applications

    Directory of Open Access Journals (Sweden)

    Shanthala S

    2010-12-01

    Full Text Available Majority of Digital Signal Processing (DSP applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bitpipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.

  6. A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology

    CERN Document Server

    Islam, Md Saiful

    2010-01-01

    Reversible logic has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its applications in low power CMOS design, cryptography, optical information processing and nanotechnology. This paper presents a novel and quantum cost efficient reversible full adder gate in nanotechnology. This gate can work singly as a reversible full adder unit and requires only one clock cycle. The proposed gate is a universal gate in the sense that it can be used to synthesize any arbitrary Boolean functions. It has been demonstrated that the hardware complexity offered by the proposed gate is less than the existing counterparts. The proposed reversible full adder gate also adheres to the theoretical minimum established by the researchers.

  7. Quaternary Galois field adder based all-optical multivalued logic circuits.

    Science.gov (United States)

    Chattopadhyay, Tanay; Taraphdar, Chinmoy; Roy, Jitendra Nath

    2009-08-01

    Galois field (GF) algebraic expressions have been found to be promising choices for reversible and quantum implementation of multivalued logic. For the first time to our knowledge, we developed GF(4) adder multivalued (four valued) logic circuits in an all-optical domain. The principle and possibilities of an all-optical GF(4) adder circuit are described. The theoretical model is presented and verified through numerical simulation. The quaternary inverter, successor, clockwise cycle, and counterclockwise cycle gates are proposed with the help of the all-optical GF(4) adder circuit. In this scheme different quaternary logical states are represented by different polarized light. A terahertz optical asymmetric demultiplexer interferometric switch plays an important role in this scheme.

  8. DESIGN OF A LOW LATENCY ASYNCHRONOUS ADDER USING EARLY COMPLETION DETECTION

    Directory of Open Access Journals (Sweden)

    KOK KEONG LAI

    2014-12-01

    Full Text Available A new method for designing completion detection for asynchronous adders is introduced. The new completion detection is based on the property of a carrymerge tree for parallel-prefix adders where a generate bit at one level will have the same value as that in the previous level if there is no carry into the sequence of bits. This method has the advantages of a bundled data approach, allowing the use of single-rail completion detection design methodology, yet it allows the detection of early completion with very minimal gate count overhead. An alternative to "speculative completion," this method has approximately 10% improvement in performance at the costs of a 4% increase in area and a negligible increase in power consumption for Hybrid Skalansky Carry-Select and self-timed Kogge-Stone parallel prefix adders.

  9. Design and Implementation of 16-Bit Magnitude Comparator Using Efficient Low Power High Performance Full Adders

    Directory of Open Access Journals (Sweden)

    Ajaykumar S Kulkarni

    2014-08-01

    Full Text Available In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder [1]. The paper attempts to examine the features of certain adder circuits which promise superior performance compared to existing circuits. The advantages of these circuits are low-power consumption, a high degree of regularity and simplicity. In this paper, the design of a 16-bit comparator is proposed. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI designers using low power high performance efficient full adders.

  10. Evaluation of renal impairment in dogs after envenomation by the common European adder (Vipera berus berus).

    Science.gov (United States)

    Palviainen, Mari; Raekallio, Marja; Vainionpää, Mari; Lahtinen, Heini; Vainio, Outi

    2013-12-01

    Envenomation by the common European adder (Vipera berus berus) causes clinical renal injury in dogs. In this study, serum concentrations of albumin, creatinine, total protein and urea were measured in 32 dogs bitten by adders. Urinary creatinine, protein, and retinol binding protein 4 concentrations, and the activities of γ-glutamyl transpeptidase (GGT) and alkaline phosphatase (ALP), were measured in 32 affected dogs and 23 healthy controls. Clinical assessment was conducted with a grading scale and a renal function score was applied to classify dogs based on laboratory findings. Urinary protein:creatinine, GGT:creatinine and ALP:creatinine ratios appear to be useful in evaluating renal impairment in dogs with adder envenomation. Increasing kidney function score was correlated with increased urinary ALP:creatinine and GGT:creatinine ratios.

  11. Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

    Directory of Open Access Journals (Sweden)

    Abdul Rehman Buzdar

    2016-07-01

    Full Text Available An Arithmetic Logic Unit (ALU is the heart of every central processing unit (CPU which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.

  12. SEMICONDUCTOR INTEGRATED CIRCUITS: 4 GHz bit-stream adder based on ΣΔ modulation

    Science.gov (United States)

    Yong, Liang; Zhigong, Wang; Qiao, Meng; Xiaodan, Guo

    2010-08-01

    The conventional circuit model of a bit-stream adder based on sigma delta (ΣΔ) modulation is improved with pipeline technology to make it work correctly at high frequencies. The integrated circuit (IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency. The IC is fabricated in TSMC's 0.18-μm CMOS process. The chip area is 475 × 570 μm2. A fully digital ΣΔ signal generator is designed with a field programmable gate array to test the chip. Experimental results show that the chip meets the function and performance demand of the design, and the chip can work at a frequency of higher than 4 GHz. The noise performance of the adder is analyzed and compared with both theory and experimental results.

  13. Test setup for accelerated test of high power IGBT modules with online monitoring of Vce and Vf voltage during converter operation

    DEFF Research Database (Denmark)

    de Vega, Angel Ruiz; Ghimire, Pramod; Pedersen, Kristian Bonderup;

    2014-01-01

    of the device in real application. The hypothesis is that ageing of power modules closer to real environment including cooling system, full dc-link voltage and continuous PWM operation could lead to more accurate study of failure mechanism. A new type of test setup is proposed, which can create different real...

  14. The genetic structure of adders (Vipera berus) in Fennoscandia: congruence between different kinds of genetic markers.

    Science.gov (United States)

    Carlsson, M; Söderberg, L; Tegelström, H

    2004-10-01

    In order to elucidate the colonization history of Fennoscandian adders (Vipera berus), the phylogeographical patterns of two nuclear sets of DNA markers (random amplified polymorphic DNA and microsatellite) are compared with that previously obtained from mitochondrial DNA. An eastern and a western lineage within Fennoscandian adders is readily distinguishable using both sets of nuclear markers, corroborating the hypothesis that the lineages stem from separate glacial refugia. Moreover, the same contact zones as were derived from mitochondrial data are clearly identifiable. Both sets of nuclear markers detect a high level of admixture across one zone in northern Finland, with introgression reaching far west into Sweden.

  15. A Novel Design of Low Power High Speed Carry Select Adder

    Directory of Open Access Journals (Sweden)

    U. Sandhya

    2014-04-01

    Full Text Available Carry Select Adder (CSLA is one of the fastest adders used in many computational systems to perform fast arithmetic operations. It performs n-bit addition and provides a sum of n+1 bit. The structure of CSLA gives the future scope of reducing the area and power consumption which are needed for the rapidly growing mobile industry. The modified 64-Bit CSLA architecture has developed using Binary to Excess-1 converter(BEC.This paper proposes an efficient method of replacing RCA in regular proposal with BEC in modified proposal.

  16. Optoelectronic Recoded and Nonrecoded Trinary Signed-Digit Adder that uses Optical Correlation.

    Science.gov (United States)

    Cherri, A K; Habib, M K; Alam, M S

    1998-04-10

    A symbolic-substitution-based optical numeric processor that uses recoded and nonrecoded trinary signed-digit (TSD) number representations is proposed. Also, we propose new joint spatial encodings for the TSD numbers that reduce the symbolic-substitution computation rules involved in the processor. Optoelectronic implementation of the proposed recoded adder is feasible. Also, the nonrecoded TSD addition can be performed optically in two steps. Both the proposed recoded and nonrecoded adders are more compact than a recently reported modified signed-digit counterpart and use fewer correlators and spatial light modulators.

  17. All-optical adder/subtractor based on tera-hertz optical asymmetric demultiplexer

    Institute of Scientific and Technical Information of China (English)

    Dilip Kumar Gayen; Rajat Kumar Pal; Jitendra Nath Roy

    2009-01-01

    An all-optical adder/subtractor (A/S) unit with the help of terahertz optical asymmetric demultiplexer (TOAD) is proposed.Tile all-optical A/S unit with a set of all-optical full-adders and optical exclusive-ORs (XORs),can be used to perform a fast central processor unit using optical hardware components.We try to exploit the advantages of TOAD-based optical switch to design an integrated all-optical circuit which can perform binary addition and subtraction.With computer simulation results confirming the described methods,conclusions are given.

  18. An Area-Efficient Carry Select Adder Design by using 180 nm Technology

    OpenAIRE

    Garish Kumar Wadhwa; Amit Grover; Neeti Grover; GurpreetSingh

    2013-01-01

    In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can b...

  19. An Area-Efficient Carry Select Adder Design by using 180 nm Technology

    Directory of Open Access Journals (Sweden)

    Garish Kumar Wadhwa

    2013-02-01

    Full Text Available In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960.

  20. The symmetric MSD encoder for one-step adder of ternary optical computer

    Science.gov (United States)

    Kai, Song; LiPing, Yan

    2016-08-01

    The symmetric Modified Signed-Digit (MSD) encoding is important for achieving the one-step MSD adder of Ternary Optical Computer (TOC). The paper described the symmetric MSD encoding algorithm in detail, and developed its truth table which has nine rows and nine columns. According to the truth table, the state table was developed, and the optical-path structure and circuit-implementation scheme of the symmetric MSD encoder (SME) for one-step adder of TOC were proposed. Finally, a series of experiments were designed and performed. The observed results of the experiments showed that the scheme to implement SME was correct, feasible and efficient.

  1. Adder bite: an uncommon cause of compartment syndrome in northern hemisphere.

    Science.gov (United States)

    Evers, Lars H; Bartscher, Tanja; Lange, Thomas; Mailänder, Peter

    2010-09-20

    Snakebite envenomation is an uncommon condition in the northern hemisphere, but requires high vigilance with regard to both the systemic effects of the venom and the locoregional impact on the soft tissues. Bites from the adder, Vipera Berus, may have serious clinical consequences due to systemic effects. A case of a 44-year-old man is reported. The patient was bitten in the right hand. He developed fasciotomy-requiring compartment syndrome of the upper limb. Recognition of this most seldom complication of an adder bite is vital to save the limb. We recommend that the classical signs and symptoms of compartment syndrome serve as indication for surgical decompression.

  2. Design of High Speed Low Power Reversible Logic Adder Using HNG Gate

    Directory of Open Access Journals (Sweden)

    Manjeet Singh Sankhwar,

    2014-01-01

    Full Text Available Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, optical information processing, quantum computing and nanotechnology. This research proposes a new implementation of adder in reversible logic. The design reduces the number of gate operations compared to the existing adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay. We can use it to construct more complex systems in nanotechnology.

  3. Design of a 5-MA 100-ns linear-transformer-driver accelerator for wire array Z-pinch experiments

    Directory of Open Access Journals (Sweden)

    Zhou Lin

    2016-03-01

    Full Text Available The linear-transformer-driver (LTD is a recently developed pulsed-power technology that shows great promise for a number of applications. These include a Z-pinch-driven fission-fusion-hybrid reactor that is being developed by the Chinese Academy of Engineering Physics. In support of the reactor development effort, we are planning to build an LTD-based accelerator that is optimized for driving wire-array Z-pinch loads. The accelerator comprises six modules in parallel, each of which has eight series 0.8-MA LTD cavities in a voltage-adder configuration. Vacuum transmission lines are used from the interior of the adder to the central vacuum chamber where the load is placed. Thus the traditional stack-flashover problem is eliminated. The machine is 3.2 m tall and 12 m in outer diameter including supports. A prototype cavity was built and tested for more than 6000 shots intermittently at a repetition rate of 0.1 Hz. A novel trigger, in which only one input trigger pulse is needed by utilizing an internal trigger brick, was developed and successfully verified in these shots. A full circuit modeling was conducted for the accelerator. The simulation result shows that a current pulse rising to 5.2 MA in 91 ns (10%–90% can be delivered to the wire-array load, which is 1.5 cm in height, 1.2 cm in initial radius, and 1 mg in mass. The maximum implosion velocity of the load is 32  cm/μs when compressed to 0.1 of the initial radius. The maximum kinetic energy is 78 kJ, which is 11.7% of the electric energy stored in the capacitors. This accelerator is supposed to enable a radiation energy efficiency of 20%–30%, providing a high efficient facility for research on the fast Z pinch and technologies for repetition-rate-operated accelerators.

  4. Quantum dot ternary-valued full-adder: Logic synthesis by a multiobjective design optimization based on a genetic algorithm

    Energy Technology Data Exchange (ETDEWEB)

    Klymenko, M. V.; Remacle, F., E-mail: fremacle@ulg.ac.be [Department of Chemistry, B6c, University of Liege, B4000 Liege (Belgium)

    2014-10-28

    A methodology is proposed for designing a low-energy consuming ternary-valued full adder based on a quantum dot (QD) electrostatically coupled with a single electron transistor operating as a charge sensor. The methodology is based on design optimization: the values of the physical parameters of the system required for implementing the logic operations are optimized using a multiobjective genetic algorithm. The searching space is determined by elements of the capacitance matrix describing the electrostatic couplings in the entire device. The objective functions are defined as the maximal absolute error over actual device logic outputs relative to the ideal truth tables for the sum and the carry-out in base 3. The logic units are implemented on the same device: a single dual-gate quantum dot and a charge sensor. Their physical parameters are optimized to compute either the sum or the carry out outputs and are compatible with current experimental capabilities. The outputs are encoded in the value of the electric current passing through the charge sensor, while the logic inputs are supplied by the voltage levels on the two gate electrodes attached to the QD. The complex logic ternary operations are directly implemented on an extremely simple device, characterized by small sizes and low-energy consumption compared to devices based on switching single-electron transistors. The design methodology is general and provides a rational approach for realizing non-switching logic operations on QD devices.

  5. Quantum dot ternary-valued full-adder: Logic synthesis by a multiobjective design optimization based on a genetic algorithm

    Science.gov (United States)

    Klymenko, M. V.; Remacle, F.

    2014-10-01

    A methodology is proposed for designing a low-energy consuming ternary-valued full adder based on a quantum dot (QD) electrostatically coupled with a single electron transistor operating as a charge sensor. The methodology is based on design optimization: the values of the physical parameters of the system required for implementing the logic operations are optimized using a multiobjective genetic algorithm. The searching space is determined by elements of the capacitance matrix describing the electrostatic couplings in the entire device. The objective functions are defined as the maximal absolute error over actual device logic outputs relative to the ideal truth tables for the sum and the carry-out in base 3. The logic units are implemented on the same device: a single dual-gate quantum dot and a charge sensor. Their physical parameters are optimized to compute either the sum or the carry out outputs and are compatible with current experimental capabilities. The outputs are encoded in the value of the electric current passing through the charge sensor, while the logic inputs are supplied by the voltage levels on the two gate electrodes attached to the QD. The complex logic ternary operations are directly implemented on an extremely simple device, characterized by small sizes and low-energy consumption compared to devices based on switching single-electron transistors. The design methodology is general and provides a rational approach for realizing non-switching logic operations on QD devices.

  6. Implementation of High Speed FIR Filter: Performance Comparison with Different Parallel Prefix Adders in FPGAs

    Directory of Open Access Journals (Sweden)

    R. Uma

    2014-04-01

    Full Text Available This study describes the design of high speed FIR filter using parallel prefix adders and factorized multiplier. The fundamental component in constructing any high speed FIR filter consists of adders, multipliers and delay elements. To meet the constraint of high speed performance and low power consumption parallel prefix adders are more suitable. This study focus the design of new Parallel Prefix Adder (PPA and new multiplier cell called factorized multiplier with minimal depth algorithm and its functional characteristics is compared with the existing architecture in terms of delay and area. The performance evaluation of the proposed PPA and multiplier are examined for the bit sizes of 8, 16, 32 and 64. The coefficient of the filter is obtained through hamming window using MATLAB program. The proposed FIR filter using new PPA and factorized multiplier has been prototyped on XC3S1600EFG320 in Spartan-3E Platform using Integrated Synthesis Environment (ISE for 90 nm process. Nearly 14% of slice utilization and 34% of speed improvement has been obtained for FIR using new PPA and factorized multiplier.

  7. A New Design Technique of Reversible BCD Adder Based on NMOS With Pass Transistor Gates

    CERN Document Server

    Hossain, Md Sazzad; Rahman, Md Motiur; Hossain, A S M Delowar; Hasan, Md Minul

    2012-01-01

    In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

  8. 1-bit sub threshold full adders in 65nm CMOS technology

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Tuan Vu, Cao

    In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results...

  9. Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit

    Directory of Open Access Journals (Sweden)

    Rajkumar Sarma

    2012-06-01

    Full Text Available Adder cells using Gate Diffusion Technique (GDI & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay productwhereas Pass Transistor Logic (PTL reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented.In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180 nm environment.

  10. Power efficient, clock gated multiplexer based full adder cell using 28 nm technology

    Science.gov (United States)

    Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

    2016-03-01

    Clock gating is a leading technique used for power saving. Full adders is one of the basic circuit that can be found in maximum VLSI circuits. In this paper clock gated multiplexer based full adder cell is implemented on 28 nm technology. We have designed a full adder cell using a multiplexer with a gated clock without degrading its performance of the cell. We have negative latch circuit for generating gated clock. This gated clock is used to control the multiplexer based full adder cell. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. The total power of the circuit has been reduced by 7.41% without degrading the performance of original circuit. The power has been calculated using XPower Analyzer tool of XILINX ISE DESIGN SUITE 14.3.

  11. 1-bit sub threshold full adders in 65nm CMOS technology

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Tuan Vu, Cao

    In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation resul...

  12. Case report: Hyperbaric oxygen in the treatment of puff adder (Bitis arietans) bite.

    Science.gov (United States)

    Rainer, Peter P; Kaufmann, Peter; Smolle-Juettner, Freyja M; Krejs, Guenter J

    2010-01-01

    The puff adder (Bitis arietans) is a venomous viper mainly found in sub-Saharan Africa. Due to its common occurrence and potent venom, it is considered to be the most dangerous snake in Africa, responsible for most snakebite fatalities there. Puff adder bites outside Africa are rare and involve captive vipers. We present the unusual case of puff adder envenomation in an Austrian man. A 26-year-old Austrian man was bitten by a puff adder that he kept illegally in his home. On admission he showed signs of local and systemic toxicity. He was stabilized with antivenom, intravenous fluids, catecholamines and packed platelets. Hyperbaric oxygenation was begun due to incipient compartment syndrome on the second day and continued until the eleventh day, when the patient had recovered completely and could be discharged. The venom of Bitis arietans can cause serious systemic and local complications. Our patient suffered from both. Systemic signs included hemodynamic as well as hemostaseologic impairment. Local effects included swelling and incipient compartment syndrome. Systemic and local treatment, including hyperbaric oxygenation, effected a full recovery. We suggest that, whenever feasible, hyperbaric oxygenation should be considered as adjunct treatment in snake bites to avert adverse outcomes.

  13. Developments of All-optical Half-adder%全光半加器的研究进展

    Institute of Scientific and Technical Information of China (English)

    孙晓寅; 李培丽; 徐荣青

    2009-01-01

    综述了全光半加器的研究进展和现状.阐述了不同结构全光半加器的工作原理、优缺点,并展望了全光半加器未来的发展方向.%It is summarized for current all-optical half-adder.The principles of different kinds of all-optical half-adders are analyzed,and their advantages and disadvantages are also discussed.Finally,the prospects of all-optical half-adder are given.

  14. Morphology, reproduction and diet in Australian and Papuan death adders (Acanthophis, Elapidae).

    Science.gov (United States)

    Shine, Richard; Spencer, Carol L; Keogh, J Scott

    2014-01-01

    Death adders (genus Acanthophis) differ from most other elapid snakes, and resemble many viperid snakes, in their thickset morphology and ambush foraging mode. Although these snakes are widely distributed through Australia and Papua New Guinea, their basic biology remains poorly known. We report morphological and ecological data based upon dissection of >750 museum specimens drawn from most of the range of the genus. Female death adders grow larger than conspecific males, to about the same extent in all taxa (20% in mean adult snout-vent length,  =  SVL). Most museum specimens were adult rather than juvenile animals, and adult males outnumbered females in all taxa except A. pyrrhus. Females have shorter tails (relative to SVL) than males, and longer narrower heads (relative to head length) in some but not all species. The southern A. antarcticus is wider-bodied (relative to SVL) than the other Australian species. Fecundity of these viviparous snakes was similar among taxa (mean litter sizes 8 to 14). Death adders encompass a broad range of ecological attributes, taking a wide variety of vertebrate prey, mostly lizards (55%), frogs and mammals (each 21%; based on 217 records). Dietary composition differed among species (e.g. frogs were more common in tropical than temperate-zone species), and shifted with snake body size (endotherms were taken by larger snakes) and sex (male death adders took more lizards than did females). Overall, death adders take a broader array of prey types, including active fast-moving taxa such as endotherms and large diurnal skinks, than do most other Australian elapids of similar body sizes. Ambush foraging is the key to capturing such elusive prey.

  15. Morphology, reproduction and diet in Australian and Papuan death adders (Acanthophis, Elapidae.

    Directory of Open Access Journals (Sweden)

    Richard Shine

    Full Text Available Death adders (genus Acanthophis differ from most other elapid snakes, and resemble many viperid snakes, in their thickset morphology and ambush foraging mode. Although these snakes are widely distributed through Australia and Papua New Guinea, their basic biology remains poorly known. We report morphological and ecological data based upon dissection of >750 museum specimens drawn from most of the range of the genus. Female death adders grow larger than conspecific males, to about the same extent in all taxa (20% in mean adult snout-vent length,  =  SVL. Most museum specimens were adult rather than juvenile animals, and adult males outnumbered females in all taxa except A. pyrrhus. Females have shorter tails (relative to SVL than males, and longer narrower heads (relative to head length in some but not all species. The southern A. antarcticus is wider-bodied (relative to SVL than the other Australian species. Fecundity of these viviparous snakes was similar among taxa (mean litter sizes 8 to 14. Death adders encompass a broad range of ecological attributes, taking a wide variety of vertebrate prey, mostly lizards (55%, frogs and mammals (each 21%; based on 217 records. Dietary composition differed among species (e.g. frogs were more common in tropical than temperate-zone species, and shifted with snake body size (endotherms were taken by larger snakes and sex (male death adders took more lizards than did females. Overall, death adders take a broader array of prey types, including active fast-moving taxa such as endotherms and large diurnal skinks, than do most other Australian elapids of similar body sizes. Ambush foraging is the key to capturing such elusive prey.

  16. Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell Based and SOC Technology

    Directory of Open Access Journals (Sweden)

    K.Swathi

    2014-09-01

    Full Text Available As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.

  17. Mathematical Analysis of Ripple Carry Adders Based on Complements%行波进位补码加法器的数学分析

    Institute of Scientific and Technical Information of China (English)

    李小霞

    2012-01-01

    Adders are very important to high-powered microprocessors and DSP. Most of the adders adopt the code of complements, and they are designed based on ripple carry adders. At present, the mathematical foundation of such adders is lacking in strictness and systematicness. This paper puts forward an irregular adder, based on complements and ripple carry. The design philosophy of the adder is very simple and different from the familiar adders. Then a systematic, concise and strict mathematical analysis is carried out on the new adder and the familiar ripple carry complemented adders.%加法器对于高性能微处理器和DSP处理器至关重要,而多数加法器是补码加法器,补码加法器的基础是行波进位加法器.目前,行波进位补码加法器的数学基础缺乏严密性与系统性.提出一种不规则补码加法器,其设计思想很简单并且完全不同于常用的补码加法器—变形补码加法器和单符号位加法器.然后对这三种补码加法器的行波进位电路进行了严密、系统、简洁的数学分析.

  18. Design of Sub-Microwatt Ultra-low Power Adder using Symmetric MRF Logics%采用对称结构MRF逻辑的亚微瓦级超低功耗加法器设计

    Institute of Scientific and Technical Information of China (English)

    耿强; 段成华

    2012-01-01

    文中提出了一种具有高抗干扰能力的对称结构改进型MRF逻辑,并由此采用混合设计策略实现了一个8位超前进位加法器.该加法器在SynopsysHSPICE模拟仿真平台上使用台积电的65nm低K电介质工艺器件模型进行了验证.电路仿真结果表明,在0.25V的工作电压下,该加法器的功耗达到了亚微瓦级.与先前的对应设计相比,晶体管数量减小44.3%,功耗降低了34.9%~38.8%.%A modified MRF logic with symmetrical structure is proposed in this paper, using which an 8-bit carry look-ahead adder is implemented based on a hybrid design methodology. The adder is verified using 65nm low-k TSMC technology on Synopsys HSPICE D-2010 platform. Simulations show that at 0. 25V supply voltage, the proposed adder consumes less than one microwatt per MHz. Compared with former design, the transistor count can be saved by 44. 3% and 34. 9%-38. 8% power consumption is reduced.

  19. Design of a Ternary Reversible/Quantum Adder using Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    Vitaly G. Deibuk

    2015-08-01

    Full Text Available —Typical methods of quantum/reversible synthesis are based on using the binary character of quantum computing. However, multi-valued logic is a promising choice for future computer technologies, given a set of advantages when comparing to binary circuits. In this work, we have developed a genetic algorithm-based synthesis of ternary reversible circuits using Muthukrishnan-Stroud gates. The method for chromosomes coding that we present, as well as a judicious choice of algorithm parameters, allowed obtaining circuits for half-adder and full adder which are better than other published methods in terms of cost, delay times and amount of input ancillary bits. A structure of the circuits is analyzed in details, based on their decomposition.

  20. Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders

    CERN Document Server

    Islam, Md Saiful; begum, Zerina; Hafiz, Mohd Zulfiquar

    2010-01-01

    Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit implements only the functions having one-to-one mapping between its input and output vectors and therefore naturally takes care of heating. Reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing fault tolerant reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed high speed reversible adders include MIG gates for the realization of its basic building block. The MIG gate is universal and parity preserving. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs...

  1. Clarks Originals Sport Series Adder Shoe猪鼻休闲鞋

    Institute of Scientific and Technical Information of China (English)

    2009-01-01

    已逾百年历史的英国休闲鞋品牌Clarks近日推出了新鞋款Adder Shoe。在鞋款的整体设计上。Clarks还是秉承了品牌一贯的英伦风格,并且在舒适性上升级,生胶大底与加厚中底的组合让这双Adder Shoe更加舒适,经典的深棕色也是最受欢迎的Clarks鞋款颜色。不论从颜色还是制作水平上来看,Clarks依旧是领先业界的品牌之一。穿上它。你的双脚并不是被禁锢而是在享受。

  2. Unimolecular half-adders and half-subtractors based on acid-base reaction

    Institute of Scientific and Technical Information of China (English)

    Wei JIANG; Hengyi ZHANG; Yu LIU

    2009-01-01

    According to the structural analysis of reported mole-cular processors with acids and bases as inputs, we proposed a general method for constructing molecular half-adders and/or half-subtractors based on acid-base reaction. The method is preliminarily supported by four molecular processors (8-hydroxyquinoline, 4-hydroxypyridine, 4-aminophenol and 5-amino-1-naphthol) capable of the elementary addition and/or subtraction algebraic operations. Noticeably, 8-hydroxyquinoline can mimic the functions of three logic devices, i.e. half-adder, half-subtractor and digital comparator, by the use of superposition and reconfi-guration. The method described in this paper may be useful not only for designing new unimolecular arithmetical processors with the same inputs and outputs as standard devices for the construction of future molecular computers, but it can also help us disclose the simplest molecules and biomolecules with computational properties concealed around us.

  3. Adder bite: an uncommon cause of compartment syndrome in northern hemisphere

    Directory of Open Access Journals (Sweden)

    Evers Lars H

    2010-09-01

    Full Text Available Abstract Snakebite envenomation is an uncommon condition in the northern hemisphere, but requires high vigilance with regard to both the systemic effects of the venom and the locoregional impact on the soft tissues. Bites from the adder, Vipera Berus, may have serious clinical consequences due to systemic effects. A case of a 44-year-old man is reported. The patient was bitten in the right hand. He developed fasciotomy-requiring compartment syndrome of the upper limb. Recognition of this most seldom complication of an adder bite is vital to save the limb. We recommend that the classical signs and symptoms of compartment syndrome serve as indication for surgical decompression.

  4. A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates

    Directory of Open Access Journals (Sweden)

    Md. Sazzad Hossain

    2011-12-01

    Full Text Available In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

  5. Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique

    OpenAIRE

    Simran kaur; Balwinder Singh; Jain, D.K.

    2015-01-01

    With the active development of portable electronic devices, the need for low power dissipation, high speed and compact implementation, give rise to several research intentions. There are several design techniques used for the circuit configuration in VLSI systems but there are very few design techniques that gives the required extensibility. This paper describes the implementation of various adders and multipliers. The design approach proposed in the article is based on the GDI (G...

  6. Optimized design of Carry Skip BCD adder using new FHNG reversible logic gates

    Directory of Open Access Journals (Sweden)

    Md.Belayet Ali

    2012-07-01

    Full Text Available Reversible logic is very essential for the construction of low power, low loss computational structures which are very essential for the construction of arithmetic circuits used in quantum computation, nanotechnology and other low power digital circuits. In the present paper an optimized and low quantum cost one digit carry skip BCD adder using new reversible logic gates are proposed. The proposed work is best compared to the other existing circuits.

  7. High Performance Hardware Design Of IEEE Floating Point Adder In FPGA With VHDL

    Directory of Open Access Journals (Sweden)

    2013-07-01

    Full Text Available In this paper, we present the design and implementation of a floating-point adder that is compliant with the current draft revision of this standard. We provide synthesis results indicating the estimated area and delay for our design when it is pipelined to various depths.Our work is an important design resource for development of floating-point adder hardware on FPGAs. All sub components within the floating-point adder and known algorithms are researched and implemented to provide versatility and flexibility to designers as an alternative to intellectual property where they have no control over the design. The VHDL code is open source and can be used by designers with proper reference. Each of the sub-operation is researched for different implementations and then synthesized onto a Spartan FPGA device to be chosen for best performance. Our implementation of the standard algorithm occupied 370 slices and had an overall delay of 31 ns. The standard algorithm was pipelined into five stages to run at 100 MHz which took an area of 324 slices and power is 30mw.

  8. Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

    Directory of Open Access Journals (Sweden)

    P. Balasubramanian

    2012-01-01

    Full Text Available A novel concept of logic redundancy insertion is presented that facilitates significant latency reduction in self-timed adder circuits. The proposed concept is universal in the sense that it can be extended to a variety of self-timed design methods. Redundant logic can be incorporated to generate efficient self-timed realizations of iterative logic specifications. Based on the case study of a 32-bit self-timed carry-ripple adder, it has been found that redundant implementations minimize the data path latency by 21.1% at the expense of increases in area and power by 2.3% and 0.8% on average compared to their nonredundant counterparts. However, when considering further peephole logic optimizations, it has been observed in a specific scenario that the delay reduction could be as high as 31% while accompanied by only meager area and power penalties of 0.6% and 1.2%, respectively. Moreover, redundant logic adders pave the way for spacer propagation in constant time and garner actual case latency for addition of valid data.

  9. Modified 16-b Square-root Low Power Area Efficient Carry Select Adder

    Directory of Open Access Journals (Sweden)

    R.P. Meenaakshi Sundhari

    2014-12-01

    Full Text Available Due to acceptance of the portable system with fast growth of power density in the integrated circuits, the power dissipation and the performance is considered while the system is designed. The main goal of the VLSI design is to design the adders in more efficient way. By that way the Carry Select Adder (CSLA is an adder designed, which computes n+1 bit sum of two n bit numbers. In this study Modified 16-b SQRT with Modified Area efficient CSLA is proposed. From the design of Modified Area Efficient CSLA it is experiential that there is an option of reducing the area more and consumes low power when compared with Regular CSLA. Modified Area Efficient CSLA (MA-CSLA utilizes BEC which reduces the area more and the total gate count is also gets condensed. The proposed study makes use of a simple and well-organized gate-level alteration to considerably reduce the area and power of the CSLA. By the support of alteration 8-, 16-, 32- and 64-b, respectively Square-Root CSLA (SQRT CSLA model have been evolved and evaluated with the regular SQRT CSLA model. This study estimates the performance of the proposed designs in terms of delay, area and power. The results analysis shows that the proposed Modified Area Efficient CSLA structure is better than the regular SQRT CSLA.

  10. Simulation of 64-bit MAC Unit using Kogge Stone Adder and Ancient Indian Mathematics

    Directory of Open Access Journals (Sweden)

    Aapurva Kaul

    2016-05-01

    Full Text Available This paper describes that multiply and accumulate (MAC unit plays a very vital role in various Digital Signal Processing applications. Speed of these applications depends on the speed of these three sub units of MAC multiply unit, adder unit and accumulator unit. In this paper the delay of 64-bit MAC unit is decreased as compared to the previous MAC units. In this Kogge Stone Adder is used as adder in design Vedic Multiplier using Urdhva Tiryakbhyam sutra. The designing of MAC unit is done under VIRTEX-4 family, XC4VFX140 device, FF1517 package and -11 speed and comparison of proposed MAC unit design is done under SPARTAN- 3E family, XC3S500 device, FG320 package and -5 speed in Xilinx ISE 8.1i. The combinational path delay of the 64-bit MAC unit is 59.705ns in SPARTAN-3E family. Ancient Indian mathematics is being used for designing of multiplier unit to decrease the overall delay of the MAC unit.

  11. An optimal adder-based hardware architecture for the DCT/SA-DCT

    Science.gov (United States)

    Kinane, Andrew; Muresan, Valentin; O'Connor, Noel

    2005-07-01

    The explosive growth of the mobile multimedia industry has accentuated the need for ecient VLSI implemen- tations of the associated computationally demanding signal processing algorithms. This need becomes greater as end-users demand increasingly enhanced features and more advanced underpinning video analysis. One such feature is object-based video processing as supported by MPEG-4 core profile, which allows content-based in- teractivity. MPEG-4 has many computationally demanding underlying algorithms, an example of which is the Shape Adaptive Discrete Cosine Transform (SA-DCT). The dynamic nature of the SA-DCT processing steps pose significant VLSI implementation challenges and many of the previously proposed approaches use area and power consumptive multipliers. Most also ignore the subtleties of the packing steps and manipulation of the shape information. We propose a new multiplier-less serial datapath based solely on adders and multiplexers to improve area and power. The adder cost is minimised by employing resource re-use methods. The number of (physical) adders used has been derived using a common sub-expression elimination algorithm. Additional energy eciency is factored into the design by employing guarded evaluation and local clock gating. Our design implements the SA-DCT packing with minimal switching using ecient addressing logic with a transpose mem- ory RAM. The entire design has been synthesized using TSMC 0.09µm TCBN90LP technology yielding a gate count of 12028 for the datapath and its control logic.

  12. Low impedance z-pinch drivers without post-hole convolute current adders.

    Energy Technology Data Exchange (ETDEWEB)

    Savage, Mark Edward; Seidel, David Bruce; Mendel, Clifford Will, Jr.

    2009-09-01

    Present-day pulsed-power systems operating in the terawatt regime typically use post-hole convolute current adders to operate at sufficiently low impedance. These adders necessarily involve magnetic nulls that connect the positive and negative electrodes. The resultant loss of magnetic insulation results in electron losses in the vicinity of the nulls that can severely limit the efficiency of the delivery of the system's energy to a load. In this report, we describe an alternate transformer-based approach to obtaining low impedance. The transformer consists of coils whose windings are in parallel rather than in series, and does not suffer from the presence of magnetic nulls. By varying the pitch of the coils windings, the current multiplication ratio can be varied, leading to a more versatile driver. The coupling efficiency of the transformer, its behavior in the presence of electron flow, and its mechanical strength are issues that need to be addressed to evaluate the potential of transformer-based current multiplication as a viable alternative to conventional current adder technology.

  13. An unusual phospholipase A₂ from puff adder Bitis arietans venom--a novel blocker of nicotinic acetylcholine receptors.

    Science.gov (United States)

    Vulfius, Catherine A; Gorbacheva, Elena V; Starkov, Vladislav G; Osipov, Alexey V; Kasheverov, Igor E; Andreeva, Tatyana V; Astashev, Maxim E; Tsetlin, Victor I; Utkin, Yuri N

    2011-04-01

    The venoms of snakes from Viperidae family mainly influence the function of various blood components. However, the published data indicate that these venoms contain also neuroactive components, the most studied being neurotoxic phospholipases A₂ (PLA₂s). Earlier we have shown (Gorbacheva et al., 2008) that several Viperidae venoms blocked nicotinic acetylcholine receptors (nAChRs) and voltage-gated Ca²+ channels in isolated identified neurons of the fresh-water snail Lymnaea stagnalis. In this paper, we report on isolation from puff adder Bitis arietans venom and characterization of a novel protein bitanarin that reversibly blocks nAChRs. To isolate the protein, the venom of B. arietans was fractionated by gel-filtration, ion-exchange and reversed phase chromatography and fractions obtained were screened for capability to block nAChRs. The isolated protein competed with [¹²⁵I]iodinated α-bungarotoxin for binding to human α7 and Torpedo californica nAChRs, as well as to acetylcholine-binding protein from L. stagnalis, the IC₅₀ being 20 ± 1.5, 4.3 ± 0.2, and 10.6 ± 0.6 μM, respectively. It also blocked reversibly acetylcholine-elicited current in isolated L. stagnalis neurons with IC₅₀ of 11.4 μM. Mass-spectrometry analysis determined the molecular mass of 27.4 kDa and the presence of 28 cysteine residues forming 14 disulphide bonds. Edman degradation of the protein and tryptic fragments showed its similarity to PLA₂s from snake venoms. Indeed, the protein possessed high PLA₂ activity, which was 1.95 mmol/min/μmol. Bitanarin is the first described PLA₂ that contains 14 disulphide bonds and the first nAChR blocker possessing PLA₂ activity. Copyright © 2011 Elsevier Ltd. All rights reserved.

  14. Binary full adder, made of fusion gates, in a subexcitable Belousov-Zhabotinsky system.

    Science.gov (United States)

    Adamatzky, Andrew

    2015-09-01

    In an excitable thin-layer Belousov-Zhabotinsky (BZ) medium a localized perturbation leads to the formation of omnidirectional target or spiral waves of excitation. A subexcitable BZ medium responds to asymmetric local perturbation by producing traveling localized excitation wave-fragments, distant relatives of dissipative solitons. The size and life span of an excitation wave-fragment depend on the illumination level of the medium. Under the right conditions the wave-fragments conserve their shape and velocity vectors for extended time periods. I interpret the wave-fragments as values of Boolean variables. When two or more wave-fragments collide they annihilate or merge into a new wave-fragment. States of the logic variables, represented by the wave-fragments, are changed in the result of the collision between the wave-fragments. Thus, a logical gate is implemented. Several theoretical designs and experimental laboratory implementations of Boolean logic gates have been proposed in the past but little has been done cascading the gates into binary arithmetical circuits. I propose a unique design of a binary one-bit full adder based on a fusion gate. A fusion gate is a two-input three-output logical device which calculates the conjunction of the input variables and the conjunction of one input variable with the negation of another input variable. The gate is made of three channels: two channels cross each other at an angle, a third channel starts at the junction. The channels contain a BZ medium. When two excitation wave-fragments, traveling towards each other along input channels, collide at the junction they merge into a single wave-front traveling along the third channel. If there is just one wave-front in the input channel, the front continues its propagation undisturbed. I make a one-bit full adder by cascading two fusion gates. I show how to cascade the adder blocks into a many-bit full adder. I evaluate the feasibility of my designs by simulating the evolution

  15. Fir Filter Design Using The Signed-Digit Number System and Carry Save Adders – A Comparison

    Directory of Open Access Journals (Sweden)

    Hesham Altwaijry

    2013-01-01

    Full Text Available This work looks at optimizing finite impulse response (FIR filters from an arithmetic perspective. Since the main two arithmetic operations in the convolution equations are addition and multiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniques should enhance the addition operation of the filter. The signed-digit number system is utilized to speedup addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also used here to compare its performance to the signed-digit adder. For multiplication, Booth encoding is used to reduce the number of partial products. The two filters are modeled in VHDL, synthesized and place-and-routed. The filters are deployed on a development board to filter digital images. The resultant hardware is analyzed for speed and logic utilization

  16. Design of Improved One's Complement Adder%一种改进的反码加法器设计

    Institute of Scientific and Technical Information of China (English)

    唐敏; 许团辉; 王玉艳

    2011-01-01

    Conventional adder adding the required number of.signed operands into the form of complement operations, and return a result in signed magnitude number. This paper proposes a new structure one's complement Signed Adder(SA) based on the flagged prefix adder, which could combine the increment unit with the adder, to reduce the delay of the signed adder. A 64-bits enhanced SA has been implemented in SMIC 180nm CMOS technology. Compared with previous work, the area, power, and delay of our design are decreased by 39.1%, 39.9%, and 5.1%, respectively.Results show that this structure is superior to two's complement adder.%传统的加法器在有符号数相加时需将操作数转化为补码形式进行运算,运算结束将计算结果再转化为原码.为减少关键路径延迟,在标志前缀加法器的基础上,提出一种改进的反码加法器,将常用反码加法器中的加一单元合并到加法运算中.在SMIC 0.18μm工艺下,将改进的64位反码加法器与常用的64位补码加法器进行比较,数据显示面积减少了39.1%,功耗降低了39.9%,关键路径延迟降低了5.1%.结果表明,改进的反码加法器性能较优.

  17. A 3-input all magnetic full adder with misalignment-free clocking mechanism

    Science.gov (United States)

    Li, Zheng; Krishnan, Kannan M.

    2017-01-01

    The clocking field misalignment is a critical issue for the application of Magnetic Quantum-dot Cellular Automata (MQCA). Recent work demonstrates a novel architecture to address this issue—by progressively tuning the shape anisotropy, we could enforce a misalignment-free signal propagation and logic operation. In this paper, we propose a novel architecture of a 3-input full adder based on the 45°-clocking field mechanism. The effectiveness of this design is confirmed through both simulation and experiments. Our work paves the way for the application of MQCA logic.

  18. Experimental study on all-optical half-adder based on semi-conductor optical amplifier

    Institute of Scientific and Technical Information of China (English)

    HAN Bing-chen; YU Jin-long; WANG Wen-rui; ZHANG Li-tai; HU Hao; YANG En-ze

    2009-01-01

    We demonstrate a novel all-optical half-adder based on two semiconductor optical amplifiers (SOAS). Two optical band-pass filters are used to select the two idlers generated by four-wave mixing (FWM) effect of the first SOA. Therefore, the AND gate and XNOR logic are realized simultaneously. The second SOA acts as a NOT gate, in which the NOR logic is achieved with the input of the logic XNOR. As a result, the output is the sum of the two input bits and the carry. In the experiment, all-optical half-addition calculation is achieved between two 10 Gb/s signals.

  19. An Enzyme-Based Half-Adder and Half-Subtractor with a Modular Design.

    Science.gov (United States)

    Fratto, Brian E; Lewer, Jessica M; Katz, Evgeny

    2016-07-18

    A half-adder and a half-subtractor have been realized using enzymatic reaction cascades performed in a flow cell device. The individual cells were modified with different enzymes and assembled in complex networks to perform logic operations and arithmetic functions. The modular design of the logic devices allowed for easy re-configuration, enabling them to perform various functions. The final output signals, represented by redox species [Fe(CN)6 ](3-/4-) or NADH/NAD(+) , were analyzed optically to derive the calculation results. These output signals might be applicable in the future for actuation processes, for example, substance release activated by logically processed signals.

  20. The mathematics of a quantum Hamiltonian computing half adder Boolean logic gate.

    Science.gov (United States)

    Dridi, G; Julien, R; Hliwa, M; Joachim, C

    2015-08-28

    The mathematics behind the quantum Hamiltonian computing (QHC) approach of designing Boolean logic gates with a quantum system are given. Using the quantum eigenvalue repulsion effect, the QHC AND, NAND, OR, NOR, XOR, and NXOR Hamiltonian Boolean matrices are constructed. This is applied to the construction of a QHC half adder Hamiltonian matrix requiring only six quantum states to fullfil a half Boolean logical truth table. The QHC design rules open a nano-architectronic way of constructing Boolean logic gates inside a single molecule or atom by atom at the surface of a passivated semi-conductor.

  1. Study of protection devices against the effects of electric discharges inside a very high voltage generator: the Vivitron accelerator; Etude de dispositifs de protection contre les effets des decharges electriques au sein d`un generateur de tres haute tension: l`accelerateur Vivitron

    Energy Technology Data Exchange (ETDEWEB)

    Nolot, E.

    1996-10-31

    The Vivitron tandem is a large electrostatic accelerator comprising a Van de Graaff generator designed to reach terminal voltages of around 30 MV. The machine is limited at rather lower nominal voltages (about 20 MV) due to the sensitivity of the insulating column structure to transient overvoltages. These are induced by electrical discharges in compressed SF{sub 6}. This thesis first aims at analysing the fundamental reasons of electrical discharges in order to limit the probability of their occurrence. Then we simulate the transient overvoltages induced and present some improvements which may lead to a stable behaviour of the Vivitron at nominal voltages higher than 20 MV. Initially we deduce discharge onset voltages and actual breakdown field limitations in the different gap geometries from analysis of possible breakdown mechanisms in compressed SF{sub 6}. In a second part, some electrical characteristics of the insulating column structure are measured at high voltage. Fast rising oscillating waves induced by sparking in the Vivitron, along with the associated energies,are determined in the third part. The last part deals with new surge protections of the insulating column structure. Spark gaps with precise onset voltage and optimized shielding electrodes are discussed. ZnO-based varistors designed for operation at very high fields have also been developed in order to reduce transient overvoltage values. (author). 122 refs.

  2. Design of Optimized Low Power and Area Efficient Digital FIR Filter using Modified Group Structures based Square Root Carry Select Adder

    Directory of Open Access Journals (Sweden)

    S. Murugeswari

    2015-01-01

    Full Text Available In Digital Signal Processing, Finite Impulse Response (FIR filter is mostly used for communications and radar applications. The Performance of FIR filter depends on Multiplier and adder circuits used in filter. To reduce the dynamic power consumption and chip size, different multiplier and adder combinations are used in order to improve the overall performance of FIR filter. The Low Power Modified Square Root Carry Select Adder (M-SQRT CSLA is presented in this study by introducing half adders instead of full adders. The proposed M-SQRT CSLA has been designed to reduce dynamic power consumption. Hence the modified SQRT CSLA is applied into Wallace multiplier for addition process after the partial product generation stage. MAC unit of the Digital FIR filter is designed by using modified Wallace multipliers and M-SQRT CSLA. Further the Group 2, Group 3; Group 4 and Group5 structures of SQRT CSLA were constructed using half adders only. Comparison between proposed SQRT CSLA and Modified Carry Save Adder (MCSA has been done with reference to the Area, Power and Delay. It is proved that the proposed SQRT CSLA consumes less area and power than all other methods. Simulation is performed by Modelsim6.3c and Synthesis process is done by Xilinx 10.1. The simulation result shows that digital filter with proposed SQRT CSLA occupies less area and consumes low power.

  3. Combined generating-accelerating buncher for compact linear accelerators

    Science.gov (United States)

    Savin, E. A.; Matsievskiy, S. V.; Sobenin, N. P.; Sokolov, I. D.; Zavadtsev, A. A.

    2016-09-01

    Described in the previous article [1] method of the power extraction from the modulated electron beam has been applied to the compact standing wave electron linear accelerator feeding system, which doesnt require any connection waveguides between the power source and the accelerator itself [2]. Generating and accelerating bunches meet in the hybrid accelerating cell operating at TM020 mode, thus the accelerating module is placed on the axis of the generating module, which consists from the pulsed high voltage electron sources and electrons dumps. This combination makes the accelerator very compact in size which is very valuable for the modern applications such as portable inspection sources. Simulations and geometry cold tests are presented.

  4. Automated Voltage Control in LHCb

    CERN Document Server

    Granado Cardoso, L; Jacobsson, R

    2011-01-01

    LHCb is one of the 4 LHC experiments. In order to ensure the safety of the detector and to maximize efficiency, LHCb needs to coordinate its own operations, in particular the voltage configuration of the different subdetectors, according to the accelerator status. A control software has been developed for this purpose, based on the Finite State Machine toolkit and the SCADA system used for control throughout LHCb (and the other LHC experiments). This software permits to efficiently drive both the Low Voltage (LV) and High Voltage (HV) systems of the 10 different sub-detectors that constitute LHCb, setting each sub-system to the required voltage (easily configurable at run-time) based on the accelerator state. The control software is also responsible for monitoring the state of the Sub-detector voltages and adding it to the event data in the form of status-bits. Safe and yet flexible operation of the LHCb detector has been obtained and automatic actions, triggered by the state changes of the ...

  5. Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders

    CERN Document Server

    Islam, Md Saiful; Begum, Zerina; Hafiz, Mohd Zulfiquar; 10.1109/ACTEA.2009.5227871

    2010-01-01

    Irreversible logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed 16-bit high speed reversible adder will include IG gates for the realization of its basic building block. The IG gate is universal in the sense that it can be used to synthesize any arbitrary Boolean-functions. The IG gate is parity preserving, that is, the parity of the input...

  6. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  7. An ambusher's arsenal: chemical crypsis in the puff adder (Bitis arietans).

    Science.gov (United States)

    Miller, Ashadee Kay; Maritz, Bryan; McKay, Shannon; Glaudas, Xavier; Alexander, Graham J

    2015-12-22

    Ambush foragers use a hunting strategy that places them at risk of predation by both visual and olfaction-oriented predators. Resulting selective pressures have driven the evolution of impressive visual crypsis in many ambushing species, and may have led to the development of chemical crypsis. However, unlike for visual crypsis, few studies have attempted to demonstrate chemical crypsis. Field observations of puff adders (Bitis arietans) going undetected by several scent-orientated predator and prey species led us to investigate chemical crypsis in this ambushing species. We trained dogs (Canis familiaris) and meerkats (Suricata suricatta) to test whether a canid and a herpestid predator could detect B. arietans using olfaction. We also tested for chemical crypsis in five species of active foraging snakes, predicted to be easily detectable. Dogs and meerkats unambiguously indicated active foraging species, but failed to correctly indicate puff adder, confirming that B. arietans employs chemical crypsis. This is the first demonstration of chemical crypsis anti-predatory behaviour, though the phenomenon may be widespread among ambushers, especially those that experience high mortality rates owing to predation. Our study provides additional evidence for the existence of an ongoing chemically mediated arms race between predator and prey species.

  8. Implementation of an Arithmetic Logic Using Area Efficient Carry Lookahead Adder

    Directory of Open Access Journals (Sweden)

    Navneet Dubey

    2014-12-01

    Full Text Available An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a c omputer. And it is a digital circuit comprised of the basic electronics components, which is used to perform va rious function of arithmetic and logic and integral opera tions further the purpose of this work is to propos e the design of an 8-bit ALU which supports 4-bit multipl ication. Thus, the functionalities of the ALU in th is study consist of following main functions like addi tion also subtraction, increment, decrement, AND, O R, NOT, XOR, NOR also two complement generation Multip lication. And the functions with the adder in the airthemetic logic unit are implemented using a Carr y Look Ahead adder joined by a ripple carry approac h. The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed A LU can be designed by using verilog or VHDL and can al so be designed on Cadence Virtuoso platform

  9. Design and Analysis of Adders using Nanotechnology Based Quantum dot Cellular Automata

    Directory of Open Access Journals (Sweden)

    S. K. Lakshmi

    2011-01-01

    Full Text Available Problem statement: The area and complexity are the major issues in circuit design. Here, we propose different types of adder designs based on Quantum dot Cellular Automata (QCA that reduces number of QCA cells and area compare to previous designs. The quantum dot cellular automata is a novel computing paradigm in nanotechnology that can implement digital circuits with faster speed, smaller size and low power consumption. By taking the advantages of QCA we are able to design interesting computational architectures. The QCA cell is a basic building block of nanotechnology that can be used to make gates, wires and memories. The basic logic circuits used in this technology are the inverter and the Majority Gate (MG, using this other logical circuits can be designed. Approach: In this paper, the adders such as half, full and serial bit were designed and analyzed. These structures were designed with minimum number of cells by using cell minimization techniques. The techniques are (1 using two cells inverter and (2 suitable arrangement of cells without overlapping of neighboring cells. The proposed method can be used to minimize area and complexity. Results: These circuits were designed by majority gate and implemented by QCA cells. Then, they simulated using QCA Designer. The simulated results were verified according to the truth table. Conclusion: The performance analyses of those circuits are compared according to complexity, area and number of clock cycles and are also compared with previous designs.

  10. Life-threatening systemic toxicity and airway compromise from a common European adder bite to the tongue

    DEFF Research Database (Denmark)

    Hoegberg, L C G; Jessen, C L; Lambertsen, K

    2009-01-01

    A 24-year-old man was bit on the tongue by a European common adder. Within 15 min following envenomation, he experienced tongue swelling, hypotension and impaired consciousness. Antihistamine, corticosteroid and crystalloids were administered. Within 105 min of envenomation, increasing oral...

  11. Accurate Switched-Voltage voltage averaging circuit

    OpenAIRE

    金光, 一幸; 松本, 寛樹

    2006-01-01

    Abstract ###This paper proposes an accurate Switched-Voltage (SV) voltage averaging circuit. It is presented ###to compensated for NMOS missmatch error at MOS differential type voltage averaging circuit. ###The proposed circuit consists of a voltage averaging and a SV sample/hold (S/H) circuit. It can ###operate using nonoverlapping three phase clocks. Performance of this circuit is verified by PSpice ###simulations.

  12. The design of the asynchronous abacus adder%异步算盘加法器设计

    Institute of Scientific and Technical Information of China (English)

    徐阳扬; 杨银堂; 周端; 弥晓华

    2011-01-01

    目的 开发一种新型的高速低功耗加法器设计方案.以满足SOC对高速低功耗运算的需要.方法 采用中国算盘算法,接口采用异步双轨握手协议,将算盘加法与异步自定时技术相结合,减少运算的进位产生,提高运算并行度.结果 提出了一种新的高速加法器电路.测试结果表明,在SMIC 0.18 μm工艺下,32位异步算盘加法器平均运算完成时间为0.957ns,其速度是同步串行加法器的6.747倍,是异步串行加法器的1.517倍和异步进位选择加法器的1.033倍.且电路平均功耗只有异步进位选择加法器的25%.结论 中国算盘算法与异步自定时电路相结合的加法器电路,有很好的速度和功耗特性,有很广阔的应用和研究前景.%Aim To develop a new high speed and low power adder design scheme for the demand of high speed and low power computing in SOC. Methods A new adder design is proposed in this paper. The adder adopts the Chinese abacus algorithm, combined with asynchronous self-timed techniques, and it also introduces the hybrid handshake protocol in the scheme. It can decrease the number of the carries and increase the parallel computing degrees. So it can achieve high speed while maintaining low power. Results The adder implemented the 0. 18μm technique of SMIC. The test result shows the 32-bit asynchronous parallel adder achieves the average computation duration is 0.957ns. Its speed is 7. 33 times faster than the synchronous ripple adder, 1.517 times faster than the a-synchronous ripple adder, and 1.033 times faster than the asynchronous carry-select adder. And its average power is only 25% of the asynchronous carry-select adder. Conclusion The adder design which combine with Chinese abacus algorithm and asynchronous self-timed techniques has good performance on high speed and low power. It has wide implement and develop prospective.

  13. The Design of Quantum Ternary Full Adder%量子三值全加器设计

    Institute of Scientific and Technical Information of China (English)

    2014-01-01

    量子多值加法器是构建量子多值计算机的基本模块。通过认真分析三元域上加法的运算规则及带进位加法的真值表,通过设置扩展三值 Toffoli 门的控制条件有效实现一位加法在各种情况下的进位,利用三值 Feynman 门实现一位加法的求和运算,由此设计出一位量子三值全加器,再利用进位线将各位量子全加器连接起来构造出 n 位量子三值全加器。与同类电路相比,此量子全加器所使用的辅助线及量子代价都有所减少。%Quantum multiple-valued adder is the basic module to construct quantum multiple-valued computer .By analyzing addition operation rules and truth table of addition with carry in ternary field ,setting control conditions of quantum generalized ternary Toffoli gates to realize the addition carry in all cases and making use of ternary Feynman gates to realize sum ,one qutrit full adder is given .At last ,nqutrit ternary full adder is constructed by using carry bit to connect all one qutrit full adders .Compared with other same type circuits ,the ancilla qubits and quantum costs of this quantum full adder have been decreased .

  14. Real-time fault tolerant full adder design for critical applications

    Directory of Open Access Journals (Sweden)

    Pankaj Kumar

    2016-09-01

    Full Text Available In the complex computing system, processing units are dealing with devices of smaller size, which are sensitive to the transient faults. A transient fault occurs in a circuit caused by the electromagnetic noises, cosmic rays, crosstalk and power supply noise. It is very difficult to detect these faults during offline testing. Hence an area efficient fault tolerant full adder for testing and repairing of transient and permanent faults occurred in single and multi-net is proposed. Additionally, the proposed architecture can also detect and repair permanent faults. This design incurs much lower hardware overheads relative to the traditional hardware architecture. In addition to this, proposed design also provides higher error detection and correction efficiency when compared to the existing designs.

  15. Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

    Directory of Open Access Journals (Sweden)

    Dempster Andrew G

    2007-01-01

    Full Text Available It has recently been shown that the -dimensional reduced adder graph (RAG- technique is beneficial for many DSP applications such as for FIR and IIR filters, where multipliers can be grouped in multiplier blocks. This paper highlights the importance of DFT and FFT as DSP objects and also explores how the RAG- technique can be applied to these algorithms. This RAG- DFT will be shown to be of low complexity and possess an attractively regular VLSI data flow when implemented with the Rader DFT algorithm or the Bluestein chirp- algorithm. ASIC synthesis data are provided and demonstrate the low complexity and high speed of the design when compared to other alternatives.

  16. Analysis of intraspecific variation in venoms of Acanthophis antarcticus death adders from South Australia.

    Science.gov (United States)

    Herzig, Volker; Kohler, Maxie; Grund, Kai F; Reeve, Shane; Smith, A Ian; Hodgson, Wayne C

    2013-01-01

    Intraspecific variation in venom composition and activity has been reported from a wide range of snakes. Geographical origin can be one cause for this variation and has recently been documented from Acanthophis antarcticus death adders sampled across four different Australian states. The present study examined whether a narrower sampling range of A. antarcticus from four collection sites within one Australian state (i.e., South Australia) would also exhibit variation in venom composition and/or activity. The present LC-MS results reveal marked differences in the venom composition from different collection sites. The most striking difference was the reduced venom complexity found in the only venom originating from a mallee scrub habitat in comparison to the venoms from coastal heath scrub habitats. Interestingly, the pharmacological activity of all venoms was found to be the same, independent of the collection site.

  17. Electrospray liquid chromatography/mass spectrometry fingerprinting of Acanthophis (death adder) venoms: taxonomic and toxinological implications.

    Science.gov (United States)

    Fry, Bryan G; Wickramaratna, Janith C; Hodgson, Wayne C; Alewood, Paul F; Kini, R M; Ho, Hao; Wüster, Wolfgang

    2002-01-01

    Death adders (genus Acanthophis) are unique among elapid snakes in both morphology and venom composition. Despite this genus being among the most divergent of all elapids, the venom has been historically regarded as relatively quite simple. In this study, liquid chromatography/mass spectrometry (LC/MS) analysis has revealed a much greater diversity in venom composition, including the presence of molecules of novel molecular weights that may represent a new class of venom component. Furthermore, significant variation exists between species and populations, which allow for the LC/MS fingerprinting of each species. Mass profiling of Acanthophis venoms clearly demonstrates the effectiveness of this technique which underpins fundamental studies ranging from chemotaxonomy to drug design.

  18. Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

    Directory of Open Access Journals (Sweden)

    ‘Aqilah binti Abdul Tahrim

    2015-01-01

    Full Text Available The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS, Complementary Pass-Transistor Logic (CPL, Transmission Gate (TG, and Hybrid CMOS (HCMOS. The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP, and energy-delay-product (EDP are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

  19. Phylogeography of the widespread African puff adder (Bitis arietans) reveals multiple Pleistocene refugia in southern Africa.

    Science.gov (United States)

    Barlow, Axel; Baker, Karis; Hendry, Catriona R; Peppin, Lindsay; Phelps, Tony; Tolley, Krystal A; Wüster, Catharine E; Wüster, Wolfgang

    2013-02-01

    Evidence from numerous Pan-African savannah mammals indicates that open-habitat refugia existed in Africa during the Pleistocene, isolated by expanding tropical forests during warm and humid interglacial periods. However, comparative data from other taxonomic groups are currently lacking. We present a phylogeographic investigation of the African puff adder (Bitis arietans), a snake that occurs in open-habitat formations throughout sub-Saharan Africa. Multiple parapatric mitochondrial clades occur across the current distribution of B. arietans, including a widespread southern African clade that is subdivided into four separate clades. We investigated the historical processes responsible for generating these phylogeographic patterns in southern Africa using species distribution modelling and genetic approaches. Our results show that interior regions of South Africa became largely inhospitable for B. arietans during glacial maxima, whereas coastal and more northerly areas remained habitable. This corresponds well with the locations of refugia inferred from mitochondrial data using a continuous phylogeographic diffusion model. Analysis of data from five anonymous nuclear loci revealed broadly similar patterns to mtDNA. Secondary admixture was detected between previously isolated refugial populations. In some cases, this is limited to individuals occurring near mitochondrial clade contact zones, but in other cases, more extensive admixture is evident. Overall, our study reveals a complex history of refugial isolation and secondary expansion for puff adders and a mosaic of isolated refugia in southern Africa. We also identify key differences between the processes that drove isolation in B. arietans and those hypothesized for sympatric savannah mammals.

  20. Collective accelerator for electron colliders

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, R.J.

    1985-05-13

    A recent concept for collective acceleration and focusing of a high energy electron bunch is discussed, in the context of its possible applicability to large linear colliders in the TeV range. The scheme can be considered to be a member of the general class of two-beam accelerators, where a high current, low voltage beam produces the acceleration fields for a trailing high energy bunch.

  1. A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

    Directory of Open Access Journals (Sweden)

    Mauro Olivieri

    2013-01-01

    Full Text Available Synchronous early-completion-prediction adders (ECPAs are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

  2. Toward defect guard-banding of EUV exposures by full chip optical wafer inspection of EUV mask defect adders

    Science.gov (United States)

    Halle, Scott D.; Meli, Luciana; Delancey, Robert; Vemareddy, Kaushik; Crispo, Gary; Bonam, Ravi; Burkhardt, Martin; Corliss, Daniel

    2015-03-01

    The detection of EUV mask adder defects has been investigated with an optical wafer defect inspection system employing a methodology termed Die-to-"golden" Virtual Reference Die (D2VRD). Both opaque and clear type mask absorber programmed defects were inspected and characterized over a range of defect sizes, down to (4x mask) 40 nm. The D2VRD inspection system was capable of identifying the corresponding wafer print defects down to the limit of the defect printability threshold at approximately 30 nm (1x wafer). The efficacy of the D2VRD scheme on full chip wafer inspection to suppress random process defects and identify real mask defects is demonstrated. Using defect repeater analysis and patch image classification of both the reference die and the scanned die enables the unambiguous identification of mask adder defects.

  3. Species and regional variations in the effectiveness of antivenom against the in vitro neurotoxicity of death adder (Acanthophis) venoms.

    Science.gov (United States)

    Fry, B G; Wickramaratna, J C; Jones, A; Alewood, P F; Hodgson, W C

    2001-09-01

    Although viperlike in appearance and habit, death adders belong to the Elapidae family of snakes. Systemic envenomation represents a serious medical problem with antivenom, which is raised against Acanthophis antarcticus venom, representing the primary treatment. This study focused on the major Acanthophis variants from Australia and islands in the Indo-Pacific region. Venoms were profiled using liquid chromatography-mass spectrometry, and analyzed for in vitro neurotoxicity (0.3-10 microg/ml), as well as the effectiveness of antivenom (1-5 units/ml; 10 min prior to the addition of 10 microg/ml venom). The following death adder venoms were examined: A. antarcticus (from separate populations in New South Wales, Queensland, South Australia, and Western Australia), A. hawkei, A. praelongus, A. pyrrhus, A. rugosus, A. wellsi, and venom from an unnamed species from the Indonesian island of Seram. All venoms abolished indirect twitches of the chick isolated biventer cervicis nerve-muscle preparation in a dose-dependent manner. In addition, all venoms blocked responses to exogenous acetylcholine (1 mM) and carbachol (20 microM), but not KCl (40 mM), suggesting postsynaptic neurotoxicity. Death adder antivenom (1 unit/ml) prevented the neurotoxic effects of A. pyrrhus, A. praelongus, and A. hawkei venoms, although it was markedly less effective against venoms from A. antarcticus (NSW, SA, WA), A. rugosus, A. wellsi, and A. sp. Seram. However, at 5 units/ml, antivenom was effective against all venoms tested. Death adder venoms, including those from A. antarcticus geographic variants, differed not only in their venom composition but also in their neurotoxic activity and susceptibility to antivenom. For the first time toxicological aspects of A. hawkei, A. wellsi, A. rugosus, and A. sp. Seram venoms were studied.

  4. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    Science.gov (United States)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  5. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    Science.gov (United States)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  6. On-Chip Implementation of High Resolution High Speed Floating Point Adder/Subtractor with Reducing Mean Latency for OFDM

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: Fast Fourier Transform (FFT is widely applied in OFDM trance-receiver communications system. Hence efficient FFT algorithm is always considered. Approach: This study proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 standard for floating-point arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Results: Consequently, synthesis report indicated the latency of 4 clock cycles due to each stage operated within just one clock cycle. The unique structure of designed adder well thought out resulted 6691 equivalent gate count and lead us to obtain low area on chip. Conclusion: The synthesis Xilinx ISE software provided results representing the estimated area and delay for design when it is pipelined to various depths. The report showed the minimum delay of 3.592 ns or maximum frequency of 278.42 MHz.

  7. Design and implementation of floating-point adders%FPU加法器的设计与实现

    Institute of Scientific and Technical Information of China (English)

    田祎; 颜军

    2012-01-01

    Floating point adders is the core component of FPU, It's the foundation of floating-point operation instruction, To improve the design optimization is very important of floating-point calculation speed and precision. This article from the floating-point adder algorithm and circuit implementation give design method, Through the VHDL language in Quartusii in design and validation ,The adder through the FSM control operations, Effective to reduce the power consumption, Improve the speed and function.%浮点运算器的核心运算部件是浮点加法器,它是实现浮点指令各种运算的基础,其设计优化对于提高浮点运算的速度和精度相当关键。文章从浮点加法器算法和电路实现的角度给出设计方法,通过VHDL语言在QuartusⅡ中进行设计和验证,此加法器通过状态机控制运算,有效地降低了功耗,提高了速度,改善了性能。

  8. 三值绝热多米诺加法器开关级设计%Design of Ternary Adiabatic Domino Adder on Switch-level

    Institute of Scientific and Technical Information of China (English)

    汪鹏君; 杨乾坤; 郑雪松

    2012-01-01

    通过对绝热多米诺电路和加法器的研究,该文提出一种新颖低功耗三值加法器的开关级设计方案.该方案首先利用开关-信号理论,结合绝热多米诺电路结构特点,推导出三值加法器本位和电路与进位电路的开关级结构式,由此得到一位三值加法器单元电路;然后通过单元电路的级联得到四位三值绝热多米诺加法器;最后,利用Spice软件对所设计的电路进行模拟,结果显示所设计的四位三值绝热多米诺加法器具有正确的逻辑功能,与四位常规多米诺三值加法器相比,能耗节省约61%.%By researching the adiabatic domino circuit and the adder, a novel design of low power ternary adder on switch-level is proposed. First, the switch-level structure of ternary adder's summing circuit and carrying circuit are derived according to the switch-signal theory and the peculiarity of adiabatic domino circuit. The design of the one bit adiabatic Domino adder unit and the four bit adder are obtained. Finally, the circuit is simulated by Spice tool and the results show that the logic function of the four bit adiabatic Domino adder is correct. The energy consumption of the four bit adiabatic Domino adder is 61% less than the conventional Domino counterpart.

  9. KEK digital accelerator

    Science.gov (United States)

    Iwashita, T.; Adachi, T.; Takayama, K.; Leo, K. W.; Arai, T.; Arakida, Y.; Hashimoto, M.; Kadokura, E.; Kawai, M.; Kawakubo, T.; Kubo, Tomio; Koyama, K.; Nakanishi, H.; Okazaki, K.; Okamura, K.; Someya, H.; Takagi, A.; Tokuchi, A.; Wake, M.

    2011-07-01

    The High Energy Accelerator Research Organization KEK digital accelerator (KEK-DA) is a renovation of the KEK 500 MeV booster proton synchrotron, which was shut down in 2006. The existing 40 MeV drift tube linac and rf cavities have been replaced by an electron cyclotron resonance (ECR) ion source embedded in a 200 kV high-voltage terminal and induction acceleration cells, respectively. A DA is, in principle, capable of accelerating any species of ion in all possible charge states. The KEK-DA is characterized by specific accelerator components such as a permanent magnet X-band ECR ion source, a low-energy transport line, an electrostatic injection kicker, an extraction septum magnet operated in air, combined-function main magnets, and an induction acceleration system. The induction acceleration method, integrating modern pulse power technology and state-of-art digital control, is crucial for the rapid-cycle KEK-DA. The key issues of beam dynamics associated with low-energy injection of heavy ions are beam loss caused by electron capture and stripping as results of the interaction with residual gas molecules and the closed orbit distortion resulting from relatively high remanent fields in the bending magnets. Attractive applications of this accelerator in materials and biological sciences are discussed.

  10. KEK digital accelerator

    Directory of Open Access Journals (Sweden)

    T. Iwashita

    2011-07-01

    Full Text Available The High Energy Accelerator Research Organization KEK digital accelerator (KEK-DA is a renovation of the KEK 500 MeV booster proton synchrotron, which was shut down in 2006. The existing 40 MeV drift tube linac and rf cavities have been replaced by an electron cyclotron resonance (ECR ion source embedded in a 200 kV high-voltage terminal and induction acceleration cells, respectively. A DA is, in principle, capable of accelerating any species of ion in all possible charge states. The KEK-DA is characterized by specific accelerator components such as a permanent magnet X-band ECR ion source, a low-energy transport line, an electrostatic injection kicker, an extraction septum magnet operated in air, combined-function main magnets, and an induction acceleration system. The induction acceleration method, integrating modern pulse power technology and state-of-art digital control, is crucial for the rapid-cycle KEK-DA. The key issues of beam dynamics associated with low-energy injection of heavy ions are beam loss caused by electron capture and stripping as results of the interaction with residual gas molecules and the closed orbit distortion resulting from relatively high remanent fields in the bending magnets. Attractive applications of this accelerator in materials and biological sciences are discussed.

  11. Peptides from puff adder Bitis arietans venom, novel inhibitors of nicotinic acetylcholine receptors.

    Science.gov (United States)

    Vulfius, Catherine A; Spirova, Ekaterina N; Serebryakova, Marina V; Shelukhina, Irina V; Kudryavtsev, Denis S; Kryukova, Elena V; Starkov, Vladislav G; Kopylova, Nina V; Zhmak, Maxim N; Ivanov, Igor A; Kudryashova, Ksenia S; Andreeva, Tatyana V; Tsetlin, Victor I; Utkin, Yuri N

    2016-10-01

    Phospholipase A2 (named bitanarin) possessing capability to block nicotinic acetylcholine receptors (nAChRs) was isolated earlier (Vulfius et al., 2011) from puff adder Bitis arietans venom. Further studies indicated that low molecular weight fractions of puff adder venom inhibit nAChRs as well. In this paper, we report on isolation from this venom and characterization of three novel peptides called baptides 1, 2 and 3 that reversibly block nAChRs. To isolate the peptides, the venom of B. arietans was fractionated by gel-filtration and reversed phase chromatography. The amino acid sequences of peptides were established by de novo sequencing using MALDI mass spectrometry. Baptide 1 comprised 7, baptides 2 and 3-10 amino acid residues, the latter being acetylated at the N-terminus. This is the first indication for the presence of such post-translational modification in snake venom proteins. None of the peptides contain cysteine residues. For biological activity studies the peptides were prepared by solid phase peptide synthesis. Baptide 3 and 2 blocked acetylcholine-elicited currents in isolated Lymnaea stagnalis neurons with IC50 of about 50 μM and 250 μM, respectively. In addition baptide 2 blocked acetylcholine-induced currents in muscle nAChR heterologously expressed in Xenopus oocytes with IC50 of about 3 μM. The peptides did not compete with radioactive α-bungarotoxin for binding to Torpedo and α7 nAChRs at concentration up to 200 μM that suggests non-competitive mode of inhibition. Calcium imaging studies on α7 and muscle nAChRs heterologously expressed in mouse neuroblastoma Neuro2a cells showed that on α7 receptor baptide 2 inhibited acetylcholine-induced increasing intracellular calcium concentration with IC50 of 20.6 ± 3.93 μM. On both α7 and muscle nAChRs the suppression of maximal response to acetylcholine by about 50% was observed at baptide 2 concentration of 25 μM, the value being close to IC50 on α7 nAChR. These data are in

  12. 加法器的QCA设计与研究进展%Design and Research Progress of the Adder Implemented with the QCA

    Institute of Scientific and Technical Information of China (English)

    汪慧; 解光军; 黄文龙

    2012-01-01

    量子细胞自动机(QCA)是一种基于元胞自动机结构的纳米器件,该器件通过电子占据量子点的位置来表征二进制信息.针对QCA加法器电路的国内外研究状况,首先分别详细地综述了进位传送加法器、载流加法器、超前进位加法器和并行前缀加法器,得出QCA加法器向大规模和规律化方向发展的结论.然后进一步从元胞个数、元胞所占面积和时钟延迟上进行分析评述,指出了载流加法器的整体性能是最优的;但与其他加法器相比,前缀加法器中的Brent-Kung Adder的稳定性最好,并对今后QCA加法器电路的研究方向进行了展望.%Quantum cellular automata (QCA) is a kind of nano-device based on the cellular automata structure, and the position of the quantum dot is occupied by electron to represent binary information. According to the research status of QCA adder circuits at home and abroad, the ripple carry adder, carry flow adder, carry look-ahead adder and parallel prefix adder are reviewed in detail, respectively. The conclusion is obtained that the QCA adder circuits are developing into the large-scale and regularity. Furthermore, the number of cells, the occupied area and the delay of clocks are analyzed. It shows that the overall performance of CFA is the best and the stability of Brent-Kung Adder is the best compared with other adders. The research orientation of the QCA adder circuits in future is prospected.

  13. Low Power and Low Ground Bouncing Noise Nanometer CMOS Full Adder%低功耗低电源线噪声纳米CMOS全加器

    Institute of Scientific and Technical Information of China (English)

    田曦; 乔飞; 董在望

    2012-01-01

    A low power and low ground bouncing noise nanometer CMOS full adder is presented. The full adder with power gating structure is used to reduce leakage power consumption. The sum generator circuit of complementary CMOS full adder is modified and the transistor counts are reduced. Sizing of the sleep transistor and the transistors for the full adder is done. The proposed full adder is simulated using 45nm CMOS technology and the simulation results demonstrate better improvements in average power -delay product, leakage power consumption and grounding bouncing noise.%提出一种低功耗低电源线噪声的纳米CMOS全加器.采用电源门控结构的全加器来降低纳米CMOS电路的漏电功耗,改进了传统互补CMOS全加器的求和电路,减少了所需晶体管的数目,并进一步对休眠晶体管的尺寸和全加器的晶体管尺寸进行了联合优化.用Hspice在45nmCMOS工艺下的电路仿真结果表明,改进后的全加器电路在平均功耗时延积、漏电功耗和电源线噪声等方面取得了很好的效果.

  14. Transient Voltage Recorder

    Science.gov (United States)

    Medelius, Pedro J. (Inventor); Simpson, Howard J. (Inventor)

    2002-01-01

    A voltage transient recorder can detect lightning induced transient voltages. The recorder detects a lightning induced transient voltage and adjusts input amplifiers to accurately record transient voltage magnitudes. The recorder stores voltage data from numerous monitored channels, or devices. The data is time stamped and can be output in real time, or stored for later retrieval. The transient recorder, in one embodiment, includes an analog-to-digital converter and a voltage threshold detector. When an input voltage exceeds a pre-determined voltage threshold, the recorder stores the incoming voltage magnitude and time of arrival. The recorder also determines if its input amplifier circuits clip the incoming signal or if the incoming signal is too low. If the input data is clipped or too low, the recorder adjusts the gain of the amplifier circuits to accurately acquire subsequent components of the lightning induced transients.

  15. The Pulse Line Ion Accelerator Concept

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Richard J.

    2006-02-15

    The Pulse Line Ion Accelerator concept was motivated by the desire for an inexpensive way to accelerate intense short pulse heavy ion beams to regimes of interest for studies of High Energy Density Physics and Warm Dense Matter. A pulse power driver applied at one end of a helical pulse line creates a traveling wave pulse that accelerates and axially confines the heavy ion beam pulse. Acceleration scenarios with constant parameter helical lines are described which result in output energies of a single stage much larger than the several hundred kilovolt peak voltages on the line, with a goal of 3-5 MeV/meter acceleration gradients. The concept might be described crudely as an ''air core'' induction linac where the PFN is integrated into the beam line so the accelerating voltage pulse can move along with the ions to get voltage multiplication.

  16. Venom physiology and composition in a litter of Common Death Adders (Acanthophis antarcticus) and their parents.

    Science.gov (United States)

    Pintor, Anna F V; Winter, Kelly L; Krockenberger, Andrew K; Seymour, Jamie E

    2011-01-01

    Metabolic expenditure has been shown to increase abruptly in several snake species directly after venom expenditure, while the later stages of venom replenishment seem to involve minor costs. This study examines the dependence of increases in metabolic rate following venom expenditure on the stage of venom replenishment that the venom producing tissue is in at the time of venom extraction in the Common Death Adder, Acanthophis antarcticus. Potential changes in venom composition during venom replenishment are also explored to elucidate whether replenishment is achieved via low rates of synthesis of all venom components or by non-parallel protein production, i.e. initial production of some venom components and subsequent synthesis of others. The results of this study indicate that venom expenditure is followed by a sudden increase in metabolic rate when snakes have previously not expended venom for at least two days, suggesting that repetitive venom expenditure does not further increase the activity of venom gland tissue in this initial time period but that a second upregulation occurs when the tissue is past the initial activation stage. In addition, venom composition appears to remain constant during replenishment within an individual, while substantial variations can be observed even between siblings.

  17. Design of an Inductive Adder for the FCC injection kicker pulse generator

    Science.gov (United States)

    Woog, D.; Barnes, M. J.; Ducimetière, L.; Holma, J.; Kramer, T.

    2017-07-01

    The injection system for a 100 TeV centre-of-mass collider is an important part of the Future Circular Collider (FCC) study. Due to issues with conventional kicker systems, such as self-triggering and long term availability of thyratrons and limitations of HV-cables, innovative design changes are planned for the FCC injection kicker pulse generator. An inductive adder (IA) based on semiconductor (SC) switches is a promising technology for kicker systems. Its modular design, and the possibility of an active ripple suppression are significant advantages. Since the IA is a complex device, with multiple components whose characteristics are important, a detailed design study and construction of a prototype is necessary. This paper summarizes the system requirements and constraints, and describes the main components and design challenges of the prototype IA. It outlines the results from simulations and measurements on different magnetic core materials as well as on SC switches. The paper concludes on the design choices and progress for the prototype to be built at CERN.

  18. A snake in the clinical grass: late compartment syndrome in a child bitten by an adder.

    Science.gov (United States)

    Cawrse, N H; Inglefield, C J; Hayes, C; Palmer, J H

    2002-07-01

    Snakebite envenomation is an uncommon condition in the UK, but requires vigilance with regard to both the systemic effects of the venom and the locoregional impact on the soft tissues. We describe a case requiring delayed fasciotomies for closed compartment syndrome of the leg and thigh, and discuss in detail the controversies surrounding decompression in such a case. Adder bites are uncommon in the UK, but can result in envenomation of varying severity. Apart from the numerous possible systemic effects that require attention, there are local effects that, very rarely, can be limb threatening. Of these, elevated limb compartment pressures are of paramount importance, and recognition of closed compartment ischaemia is vital if the limb is to be saved by surgical decompression. Guidelines on threshold compartment pressures and fasciotomies are indistinct regarding snakebite, with diagnostic emphasis still placed on clinical signs and symptoms. In the paediatric setting, measurement of compartment pressures is a valuable adjunct to clinical suspicion in the diagnosis of acute compartment syndrome secondary to snakebite.

  19. ALL OPTICAL IMPLEMENTATION OF HIGH SPEED AND LOW POWER REVERSIBLE FULL ADDER USING SEMICONDUCTOR OPTICAL AMPLIFIER BASED MACH-ZEHNDER INTERFEROMETER

    Directory of Open Access Journals (Sweden)

    R. M. Bommi

    2014-01-01

    Full Text Available In the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversible Full adder using combination of all optical Toffoli and all optical TNOR and to compare it with the Full adder designed using all optical Toffoli gate in terms of optical cost. All optical TNOR gate can work as a replacement of existing NAND based All optical Toffoli Gate (TG. The gates are designed using Mach-Zehnder Interferometer (MZI based optical switch. The proposed system is developed with the basic of reversibility to design all optical full Adder implemented with CMOS transistors. The design is efficient in terms of both architecture and in power consumption.

  20. Automatic voltage imbalance detector

    Science.gov (United States)

    Bobbett, Ronald E.; McCormick, J. Byron; Kerwin, William J.

    1984-01-01

    A device for indicating and preventing damage to voltage cells such as galvanic cells and fuel cells connected in series by detecting sequential voltages and comparing these voltages to adjacent voltage cells. The device is implemented by using operational amplifiers and switching circuitry is provided by transistors. The device can be utilized in battery powered electric vehicles to prevent galvanic cell damage and also in series connected fuel cells to prevent fuel cell damage.

  1. All-Optical Half-Adder Using All-Optical XOR and AND Gates for Optical Generation of "Sum" and "Carry"

    Science.gov (United States)

    Menezes, J. W. M.; Fraga, W. B.; Ferreira, A. C.; Guimarães, G. F.; Filho, A. F. G. F.; Sobrinho, C. S.; Sombra, A. S. B.

    2010-07-01

    In this article, a numerical simulation study using the symmetric planar three-core non-linear directional coupler, operating with a short light pulse (2 ps), for the implementation of an all-optical half-adder is presented. The half-adder is the key building block for many digital processing functions such as shift register, binary counter, and serial parallel data converters. Optical couplers are an important component for application in optical fiber telecommunication systems and all integrated optical circuits because of very high switching speeds (as high as the femto-second range). In this numerical simulation, the symmetric planar three-core non-linear directional coupler presents a planar symmetrical structure with three cores in a parallel equidistant arrangement, three logical inputs (CP, A, and B), and two output logic functions (C and S). The CP(ΔΦ) input is a control pulse with a phase difference ΔΦ = Δθπ (0 ≤ Δθ ≤ 2) between inputs A and B (logical inputs of the half-adder) and one amplitude discriminator circuit. The half-adder uses two output logic functions of Sum(S) and Carry(C), which can be demonstrated by using XOR and AND gates, respectively. For the half-adder, the phase [ΔΦMIN, ΔΦMAX] intervals are studied, allowing the operation of the device as a half-adder. For the selected range of CP(ΔΦBETTER), the extinction ratio was studied, the compression factors for both Sum(S) and Carry(C) outputs of the symmetric planar three-core non-linear directional coupler.

  2. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  3. Low voltage arc formation in railguns

    Science.gov (United States)

    Hawke, Ronald S.

    1987-01-01

    A low voltage plasma arc is first established across the rails behind the projectile by switching a low voltage high current source across the rails to establish a plasma arc by vaporizing a fuse mounted on the back of the projectile, maintaining the voltage across the rails below the railgun breakdown voltage to prevent arc formation ahead of the projectile. After the plasma arc has been formed behind the projectile a discriminator switches the full energy bank across the rails to accelerate the projectile. A gas gun injector may be utilized to inject a projectile into the breech of a railgun. The invention permits the use of a gas gun or gun powder injector and an evacuated barrel without the risk of spurious arc formation in front of the projectile.

  4. Separate and simultaneous generation of multioutputs in a polarization-encoded optical shadow-casting scheme: design of half- and full adders and subtractors.

    Science.gov (United States)

    Rizvi, R A; Zaheer, K; Zubairy, M S

    1988-12-15

    A design algorithm for separate and simultaneous generation of multioutputs in a polarization-encoded optical shadow-casting (POSC) scheme is presented. The logic unit truth table is converted into POSC logic equations for true and false logic. These are then solved consistently to obtain source plane, input pixel, and the decoding mask characteristics. The algorithm is used to design binary half-adder and half-subtractor and full adder and full subtractor to carry out all operations with a fixed source plane and a fixed decoding mask. The results have been verified experimentally.

  5. Quantum half-adder Boolean logic gate with a nano-graphene molecule and graphene nano-electrodes

    Science.gov (United States)

    Srivastava, Saurabh; Kino, Hiori; Joachim, Christian

    2017-01-01

    A molecule Boolean 1 / 2 -adder is designed and the XOR and AND truth table calculated at +0.1 V using 4 graphene electrodes. It functions with level repulsion and destructive interferences effects using 4 molecule electronic states in a quantum Hamiltonian computing approach (QHC) with the abrupt change of the molecular orbital weight of those 4 calculating states as a function of the logical input configuration. The logical inputs enter rotating the two nitro groups of the central board. With QHC, a complex Boolean digital function can be implemented employing the same graphene material for interconnects and the molecule calculating parts.

  6. Presence of presynaptic neurotoxin complexes in the venoms of Australo-Papuan death adders (Acanthophis spp.).

    Science.gov (United States)

    Blacklow, Benjamin; Konstantakopoulos, Nicki; Hodgson, Wayne C; Nicholson, Graham M

    2010-06-01

    Australo-papuan death adders (Acanthophis spp.) are a cause of serious envenomations in Papua New Guinea and northern Australia often resulting in neurotoxic paralysis. Furthermore, victims occasionally present with delayed-onset neurotoxicity that sometimes responds poorly to antivenom or anticholinesterase treatment. This clinical outcome could be explained by the presence of potent snake presynaptic phospholipase A(2) neurotoxin (SPAN) complexes and monomers, in addition to long- and short-chain postsynaptic alpha-neurotoxins, that bind irreversibly, block neurotransmitter release and result in degeneration of the nerve terminal. The present study therefore aimed to determine within-genus variations in expression of high molecular mass SPAN complexes in the venoms of six major species of Acanthophis, four geographic variants of Acanthophis antarcticus. Venoms were separated by size-exclusion liquid chromatography under non-denaturing conditions and fractions corresponding to proteins in the range of 22 to >60 kDa were subjected to pharmacological characterization using the isolated chick biventer cervicis nerve-muscle (CBCNM) preparation. All venoms, except Acanthophis wellsi and Acanthophis pyrrhus, contained high mass fractions with phospholipase A(2) activity that inhibited twitch contractions of the CBCNM preparation. This inhibition was of slow onset, and responses to exogenous nicotinic agonists were not blocked, consistent with the presence of SPAN complexes. The results of the present study indicate that clinicians may need to be aware of possible prejunctional neurotoxicity following envenomations from A. antarcticus (all geographic variants except perhaps South Australia), Acanthophis praelongus, Acanthophis rugosus and Acanthophis. laevis species, and that early antivenom intervention is important in preventing further development of toxicity.

  7. Towards constructing one-bit binary adder in excitable chemical medium

    Science.gov (United States)

    Lacy Costello, Ben De; Adamatzky, Andy; Jahan, Ishrat; Zhang, Liang

    2011-03-01

    The light-sensitive modification (ruthenium catalysed) of the Belousov-Zhabotinsky reaction exhibits various excitability regimes depending on the level of illumination. Within a narrow range of applied illumination levels the medium is in a sub-excitable state. When in this state an asymmetric perturbation of the medium leads to formation of a travelling localized excitation (wave-fragment) which moves along a predetermined trajectory, ideally preserving its shape and velocity over an extended time period. Collision-based computing can be implemented with these wave-fragments whereby values of Boolean variables are represented as the presence/absence of a wave-fragment at specific sites. When two wave-fragments collide they either annihilate, or form new wave-fragments. The trajectories of the wave-fragments after the collision represent the result of a computation, e.g. construction of a simple logical gate. However, wave-fragments in sub-excitable chemical media are difficult to control. Therefore, we adopted a hybrid procedure in order to construct collision-based logical gates. We used channels of low light intensity projected onto the excitable media in order to subtly tune and stabilise the propagating wave-fragments allowing them to collide at the junctions between channels. Using this methodology we were able to implement both in theoretical models (using the Oregonator) and in experiment two interaction-based logical gates and assemble the gates into a basic one-bit binary adder. We present the first ever experimental approach towards constructing arithmetic circuits in spatially-extended excitable chemical systems where light is used to impart functionality.

  8. Future accelerators (?)

    Energy Technology Data Exchange (ETDEWEB)

    John Womersley

    2003-08-21

    I describe the future accelerator facilities that are currently foreseen for electroweak scale physics, neutrino physics, and nuclear structure. I will explore the physics justification for these machines, and suggest how the case for future accelerators can be made.

  9. Neurotoxicity, anticoagulant activity and evidence of rhabdomyolysis in patients bitten by death adders (Acanthophis sp.) in southern Papua New Guinea.

    Science.gov (United States)

    Lalloo, D G; Trevett, A J; Black, J; Mapao, J; Saweri, A; Naraqi, S; Owens, D; Kamiguti, A S; Hutton, R A; Theakston, R D; Warrell, D A

    1996-01-01

    Thirty-two patients with enzyme-immunoassay-proven death adder (Acanthophis sp.) bites were studied in Port Moresby, Papua New Guinea. Eighteen were envenomed; local signs were rare and none had incoagulable blood, but all except one had signs of neurotoxicity. Five (27.7%) envenomed patients required intubation and ventilation. One patient developed renal failure, previously undescribed following death adder bites. Laboratory investigations showed mild prolongation of prothrombin and partial thromboplastin times in some patients. In vitro studies showed that the venom contains anticoagulant activity, but does not cause fibrinogenolysis. In contrast to taipan envenoming, neurotoxicity did not progress after antivenom administration, and there was reversal of neurotoxicity, evident within 6 h, in three severely envenomed patients treated less than 12 h after the bite. One patient treated with antivenom and anticholinesterases had the most dramatic response to treatment; the optimum management of bites by this species may include prompt treatment with both antivenom and anticholinesterases in addition to effective first aid.

  10. New adders using hybrid circuit consisting of three-gate single-electron transistors (TG-SETs) and MOSFETs.

    Science.gov (United States)

    Yu, YunSeop; Choi, JungBum

    2007-11-01

    A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional CMOS FA with 0.35 microm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs.

  11. Technological Aspects: High Voltage

    CERN Document Server

    Faircloth, D C

    2013-01-01

    This paper covers the theory and technological aspects of high-voltage design for ion sources. Electric field strengths are critical to understanding high-voltage breakdown. The equations governing electric fields and the techniques to solve them are discussed. The fundamental physics of high-voltage breakdown and electrical discharges are outlined. Different types of electrical discharges are catalogued and their behaviour in environments ranging from air to vacuum are detailed. The importance of surfaces is discussed. The principles of designing electrodes and insulators are introduced. The use of high-voltage platforms and their relation to system design are discussed. The use of commercially available high-voltage technology such as connectors, feedthroughs and cables are considered. Different power supply technologies and their procurement are briefly outlined. High-voltage safety, electric shocks and system design rules are covered.

  12. 新型8管一位全加器电路设计%Design of a novel 8-transistor full adder circuit

    Institute of Scientific and Technical Information of China (English)

    董艳燕; 韦一; 陈君

    2013-01-01

    Based on the research and analysis of existing full adder circuits, a novel full adder cell used only 8 transistors was proposed. The novel circuit was composed of two 3-XNOR gates and one multiplexer. Compared with the typical full adder circuits,the proposed full adder circuit shows a significant improvement in transistor count power consumption and power delay product by tested with HSPICE simulation based on 0. 18μm CMOS process.%通过对已有全加器电路的研究与分析,提出了仅需8个晶体管的新型全加器单元.新电路包括2个3管同或门模块和1个选择器模块.在台积电(TSMC)0.18 μm互补氧化物半导体(CMOS)工艺器件参数下经电路模拟程序(HSPICE)进行性能测试,与现有典型的全加器相比,新电路在晶体管数目、功耗和功耗延迟积有较大的优势.

  13. Particle Accelerator Focus Automation

    Directory of Open Access Journals (Sweden)

    Lopes José

    2017-08-01

    Full Text Available The Laboratório de Aceleradores e Tecnologias de Radiação (LATR at the Campus Tecnológico e Nuclear, of Instituto Superior Técnico (IST has a horizontal electrostatic particle accelerator based on the Van de Graaff machine which is used for research in the area of material characterization. This machine produces alfa (He+ and proton (H+ beams of some μA currents up to 2 MeV/q energies. Beam focusing is obtained using a cylindrical lens of the Einzel type, assembled near the high voltage terminal. This paper describes the developed system that automatically focuses the ion beam, using a personal computer running the LabVIEW software, a multifunction input/output board and signal conditioning circuits. The focusing procedure consists of a scanning method to find the lens bias voltage which maximizes the beam current measured on a beam stopper target, which is used as feedback for the scanning cycle. This system, as part of a wider start up and shut down automation system built for this particle accelerator, brings great advantages to the operation of the accelerator by turning it faster and easier to operate, requiring less human presence, and adding the possibility of total remote control in safe conditions.

  14. Particle Accelerator Focus Automation

    Science.gov (United States)

    Lopes, José; Rocha, Jorge; Redondo, Luís; Cruz, João

    2017-08-01

    The Laboratório de Aceleradores e Tecnologias de Radiação (LATR) at the Campus Tecnológico e Nuclear, of Instituto Superior Técnico (IST) has a horizontal electrostatic particle accelerator based on the Van de Graaff machine which is used for research in the area of material characterization. This machine produces alfa (He+) and proton (H+) beams of some μA currents up to 2 MeV/q energies. Beam focusing is obtained using a cylindrical lens of the Einzel type, assembled near the high voltage terminal. This paper describes the developed system that automatically focuses the ion beam, using a personal computer running the LabVIEW software, a multifunction input/output board and signal conditioning circuits. The focusing procedure consists of a scanning method to find the lens bias voltage which maximizes the beam current measured on a beam stopper target, which is used as feedback for the scanning cycle. This system, as part of a wider start up and shut down automation system built for this particle accelerator, brings great advantages to the operation of the accelerator by turning it faster and easier to operate, requiring less human presence, and adding the possibility of total remote control in safe conditions.

  15. Stray voltage mitigation

    Energy Technology Data Exchange (ETDEWEB)

    Jamali, B.; Piercy, R.; Dick, P. [Kinetrics Inc., Toronto, ON (Canada). Transmission and Distribution Technologies

    2008-04-09

    This report discussed issues related to farm stray voltage and evaluated mitigation strategies and costs for limiting voltage to farms. A 3-phase, 3-wire system with no neutral ground was used throughout North America before the 1930s. Transformers were connected phase to phase without any electrical connection between the primary and secondary sides of the transformers. Distribution voltage levels were then increased and multi-grounded neutral wires were added. The earth now forms a parallel return path for the neutral current that allows part of the neutral current to flow continuously through the earth. The arrangement is responsible for causing stray voltage. Stray voltage causes uneven milk production, increased incidences of mastitis, and can create a reluctance to drink water amongst cows when stray voltages are present. Off-farm sources of stray voltage include phase unbalances, undersized neutral wire, and high resistance splices on the neutral wire. Mitigation strategies for reducing stray voltage include phase balancing; conversion from single to 3-phase; increasing distribution voltage levels, and changing pole configurations. 22 refs., 5 tabs., 13 figs.

  16. High voltage engineering

    CERN Document Server

    Rizk, Farouk AM

    2014-01-01

    Inspired by a new revival of worldwide interest in extra-high-voltage (EHV) and ultra-high-voltage (UHV) transmission, High Voltage Engineering merges the latest research with the extensive experience of the best in the field to deliver a comprehensive treatment of electrical insulation systems for the next generation of utility engineers and electric power professionals. The book offers extensive coverage of the physical basis of high-voltage engineering, from insulation stress and strength to lightning attachment and protection and beyond. Presenting information critical to the design, selec

  17. High voltage test techniques

    CERN Document Server

    Kind, Dieter

    2001-01-01

    The second edition of High Voltage Test Techniques has been completely revised. The present revision takes into account the latest international developments in High Voltage and Measurement technology, making it an essential reference for engineers in the testing field.High Voltage Technology belongs to the traditional area of Electrical Engineering. However, this is not to say that the area has stood still. New insulating materials, computing methods and voltage levels repeatedly pose new problems or open up methods of solution; electromagnetic compatibility (EMC) or components and systems al

  18. Mitigation of Unbalanced Voltage Sags and Voltage Unbalance in CIGRE Low Voltage Distribution Network

    OpenAIRE

    Mustafa, Ghullam; Bak-Jensen, Birgitte; Mahat, Pukar; Cecati, Carlo

    2013-01-01

    Any problem with voltage in a power network is undesirable as it aggravates the quality of the power. Power electronic devices such as Voltage Source Converter (VSC) based Static Synchronous Compensator (STATCOM) etc. can be used to mitigate the voltage problems in the distribution system. The voltage problems dealt with in this paper are to show how to mitigate unbalanced voltage sags and voltage unbalance in the CIGRE Low Voltage (LV) test network and net-works like this. The voltage unbala...

  19. Accelerating Value Creation with Accelerators

    DEFF Research Database (Denmark)

    Jonsson, Eythor Ivar

    2015-01-01

    accelerator programs. Microsoft runs accelerators in seven different countries. Accelerators have grown out of the infancy stage and are now an accepted approach to develop new ventures based on cutting-edge technology like the internet of things, mobile technology, big data and virtual reality. It is also...... with the traditional audit and legal universes and industries are examples of emerging potentials both from a research and business point of view to exploit and explore further. The accelerator approach may therefore be an Idea Watch to consider, no matter which industry you are in, because in essence accelerators...

  20. Simulation design and analysis of full adder function and application%全加器功能及应用的仿真设计分析

    Institute of Scientific and Technical Information of China (English)

    孙津平

    2011-01-01

    加法运算是数字系统中最基本的算术运算.为了能更好地利用加法器实现减法、乘法、除法、码制转换等运算,提出用Multisim虚拟仿真软件中的逻辑转换仪、字信号发生器、逻辑分析仪,时全加器进行功能仿真设计、转换、测试、分析,强化Multisim的使用,并通过用集成全加器74LS283实现两个一位8421码十进制数的减法运算,掌握了全加器的应用方法.测试证明,全加器功能的扩展和应用,利用Multisim软件的仿真设计能较好地实现.%Addition operation is the most basic digital system arithmetic. In order to achieve better use of adder subtraction ,multiplication,division ,transcoding operations ,this paper proposed using Multisim virtual simulation software ,the logic of conversion device,digital signal generator,logic analyzer,the full adder design for functional simulation,conversion,testing,analysis,and strengthened the use of Multisim and by using a full adder 74LS283 integrated to achieve a 8421 yards two decimal subtraction and master the application method of the full adder. Testing shows the expansion and application of full adder function can be well implemented by using simulation design of Multisim software.

  1. Accelerating Value Creation with Accelerators

    DEFF Research Database (Denmark)

    Jonsson, Eythor Ivar

    2015-01-01

    Accelerators can help to accelerate value creation. Accelerators are short-term programs that have the objective of creating innovative and fast growing ventures. They have gained attraction as larger corporations like Microsoft, Barclays bank and Nordea bank have initiated and sponsored accelera......Accelerators can help to accelerate value creation. Accelerators are short-term programs that have the objective of creating innovative and fast growing ventures. They have gained attraction as larger corporations like Microsoft, Barclays bank and Nordea bank have initiated and sponsored...... an approach to facilitate implementation and realization of business ideas and is a lucrative approach to transform research into ventures and to revitalize regions and industries in transition. Investors have noticed that the accelerator approach is a way to increase the possibility of success by funnelling...

  2. Voltage verification unit

    Science.gov (United States)

    Martin, Edward J.

    2008-01-15

    A voltage verification unit and method for determining the absence of potentially dangerous potentials within a power supply enclosure without Mode 2 work is disclosed. With this device and method, a qualified worker, following a relatively simple protocol that involves a function test (hot, cold, hot) of the voltage verification unit before Lock Out/Tag Out and, and once the Lock Out/Tag Out is completed, testing or "trying" by simply reading a display on the voltage verification unit can be accomplished without exposure of the operator to the interior of the voltage supply enclosure. According to a preferred embodiment, the voltage verification unit includes test leads to allow diagnostics with other meters, without the necessity of accessing potentially dangerous bus bars or the like.

  3. Acceleration of microparticle

    CERN Document Server

    Shibata, H

    2002-01-01

    A microparticle (dust) ion source has been installed at the high voltage terminal of the 3.75 MV single ended Van de Graaff electrostatic accelerator and a beam line for microparticle experiments has been build at High Fluence Irradiation Facility (HIT) of Research Center for Nuclear Science and Technology, the University of Tokyo. Microparticle acceleration has been successful in obtaining expected velocities of 1-20 km/s or more for micron or submicron sized particles. Development of in situ dust detectors and analyzers on board satellites and spacecraft in the expected mass and velocity range of micrometeoroids and investigation of hypervelocity impact phenomena by using time of flight mass spectrometry, impact flash or luminescence measurement and scanning electron or laser microscope observation for metals, ceramics, polymers and semiconductors bombarded by micron-sized particles were started three years ago. (author)

  4. 对数跳跃加法器的静态CMOS实现%Static CMOS Implementation of Logarithmic Skip Adder

    Institute of Scientific and Technical Information of China (English)

    贾嵩; 刘飞; 刘凌; 陈中建; 吉利久

    2003-01-01

    Circuit design of 32-bit logarithmic skip adder (LSA) is introduced to implement high performance,low power addition.ELM carry lookahead adder is included into groups of carry skip adder and the hybrid structure costs 30% less hardware than ELM.At circuit level,a carry-incorporating structure to include the primary carry input in carry chain and an "and-xor" structure to implement final sum logic in 32-bit LSA are designed for better optimization.For 5V,1μm process,32-bit LSA has a critical delay of 5.9ns and costs an area of 0.62mm2,power consumption of 23mW at 100MHz.For 2.5V,0.25μm process,critical delay of 0.8ns,power dissipation of 5.2mW at 100MHz is simulated.%介绍了一种32位对数跳跃加法器结构.该结构采用ELM超前进位加法器代替进位跳跃结构中的组内串行加法器,同ELM相比节约了30%的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用Ling算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现"与-民或"功能;1.0μm CMOS工世实现的32位对数跳跃加法器面积为0.62mm2,采用1μm和0.25μm 工世参数的关键路径延迟分别为6ns和0.8ns,在100MHz下功耗分别为23和5.2mW.

  5. RECIRCULATING ACCELERATION

    Energy Technology Data Exchange (ETDEWEB)

    BERG,J.S.; GARREN,A.A.; JOHNSTONE,C.

    2000-04-07

    This paper compares various types of recirculating accelerators, outlining the advantages and disadvantages of various approaches. The accelerators are characterized according to the types of arcs they use: whether there is a single arc for the entire recirculator or there are multiple arcs, and whether the arc(s) are isochronous or non-isochronous.

  6. LIBO accelerates

    CERN Multimedia

    2002-01-01

    The prototype module of LIBO, a linear accelerator project designed for cancer therapy, has passed its first proton-beam acceleration test. In parallel a new version - LIBO-30 - is being developed, which promises to open up even more interesting avenues.

  7. Accelerating Inspire

    CERN Document Server

    AUTHOR|(CDS)2266999

    2017-01-01

    CERN has been involved in the dissemination of scientific results since its early days and has continuously updated the distribution channels. Currently, Inspire hosts catalogues of articles, authors, institutions, conferences, jobs, experiments, journals and more. Successful orientation among this amount of data requires comprehensive linking between the content. Inspire has lacked a system for linking experiments and articles together based on which accelerator they were conducted at. The purpose of this project has been to create such a system. Records for 156 accelerators were created and all 2913 experiments on Inspire were given corresponding MARC tags. Records of 18404 accelerator physics related bibliographic entries were also tagged with corresponding accelerator tags. Finally, as a part of the endeavour to broaden CERN's presence on Wikipedia, existing Wikipedia articles of accelerators were updated with short descriptions and links to Inspire. In total, 86 Wikipedia articles were updated. This repo...

  8. Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog

    Directory of Open Access Journals (Sweden)

    Addanki Purna Ramesh

    2012-06-01

    Full Text Available In this paper, we propose a new multiplier-and-accumulator (MAC architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition and spikes (0 to 1 transition. Adder designed using spurious power suppression technique (SPST avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

  9. Shaft Voltage and Life of Bearing electric-erosion for the Brushless DC Motor

    Science.gov (United States)

    Maetani, Tatsuo; Isomura, Yoshinori; Komiyama, Hiroshi; Morimoto, Shigeo

    This paper describes the life of noise of bearing electro-erosion in the shaft voltage of brushless DC motors. We confirmed that shaft voltage is suppressed to equal to or less than the dielectric breakdown voltage of bearing lubricant in the insulated rotor proposed for suppression of shaft voltage. However, since bearing electro-erosion appears over time along with the deterioration of noise performance, the threshold of the shaft voltage to secure noise performance over long periods of time is necessary. Therefore, the threshold of the shaft voltage that influences the life of noise was obtained in acceleration tests.

  10. 基于全加器的逻辑判别电路设计%Based on the logic of full adder discriminant circuit design

    Institute of Scientific and Technical Information of China (English)

    马敬敏

    2016-01-01

    Full adder is realized arithmetic addition of the basic device is configured to use a conventional multi-bit binary number or arithmetic adder circuit. This paper discusses on the full adder logic function expansion method, the purpose is to explore the full adder using unconventional direction change application logic design technology, which uses a combination of more than one full adder, connected to form a plurality of inputs plus arithmetic operation circuit, the number of input variables in a different result of the addition is different, based on the result of the addition and then design a majority vote, other odd or even logic discrimination circuit. The innovation of the proposed method is applied to change the direction of the full adder logic design methods.%全加器是实现算术加法运算的基本器件,常规使用是构成1位或多位二进制数算术加法运算电路。本文探讨了对全加器进行逻辑功能扩展的方法,目的是探索全加器进行非常规使用改变应用方向的逻辑设计技术,即用多个一位全加器组合、连接构成对多个输入量算术加运算电路,输入变量中1的个数不同,相加的结果也就不同,在相加结果的基础上再进行多数表决、奇偶数判别等逻辑判别电路的设计。所述方法的创新点是提出了全加器改变应用方向的逻辑设计方法。

  11. Accelerated lifetime testing of energy storage capacitors used in particle accelerators power converters

    CERN Document Server

    AUTHOR|(SzGeCERN)679542; Genton, Charles-Mathieu

    2015-01-01

    Energy storage capacitors are used in large quantities in high power converters for particle accelerators. In this application capacitors see neither a DC nor an AC voltage but a combination of the two. The paper presents a new power converter explicitly designed to perform accelerated testing on these capacitors and the results of the tests.

  12. High Voltage Distribution

    Science.gov (United States)

    Norbeck, Edwin; Miller, Michael; Onel, Yasar

    2010-11-01

    For detector arrays that require 5 to 10 kV at a few microamps each for hundreds of detectors, using hundreds of HV power supplies is unreasonable. Bundles of hundreds of HV cables take up space that should be filled with detectors. A typical HV module can supply 1 ma, enough current for hundreds of detectors. It is better to use a single HV module and distribute the current as needed. We show a circuit that, for each detector, measures the current, cuts off the voltage if the current exceeds a set maximum, and allows the HV to be turned on or off from a control computer. The entire array requires a single HV cable and 2 or 3 control lines. This design provides the same voltage to all of the detectors, the voltage set by the single HV module. Some additional circuitry would allow a computer controlled voltage drop between the HV and each individual detector.

  13. High voltage engineering fundamentals

    CERN Document Server

    Kuffel, E; Hammond, P

    1984-01-01

    Provides a comprehensive treatment of high voltage engineering fundamentals at the introductory and intermediate levels. It covers: techniques used for generation and measurement of high direct, alternating and surge voltages for general application in industrial testing and selected special examples found in basic research; analytical and numerical calculation of electrostatic fields in simple practical insulation system; basic ionisation and decay processes in gases and breakdown mechanisms of gaseous, liquid and solid dielectrics; partial discharges and modern discharge detectors; and over

  14. Low-voltage gyrotrons

    Science.gov (United States)

    Glyavin, M. Yu.; Zavolskiy, N. A.; Sedov, A. S.; Nusinovich, G. S.

    2013-03-01

    For a long time, the gyrotrons were primarily developed for electron cyclotron heating and current drive of plasmas in controlled fusion reactors where a multi-megawatt, quasi-continuous millimeter-wave power is required. In addition to this important application, there are other applications (and their number increases with time) which do not require a very high power level, but such issues as the ability to operate at low voltages and have compact devices are very important. For example, gyrotrons are of interest for a dynamic nuclear polarization, which improves the sensitivity of the nuclear magnetic resonance spectroscopy. In this paper, some issues important for operation of gyrotrons driven by low-voltage electron beams are analyzed. An emphasis is made on the efficiency of low-voltage gyrotron operation at the fundamental and higher cyclotron harmonics. These efficiencies calculated with the account for ohmic losses were, first, determined in the framework of the generalized gyrotron theory based on the cold-cavity approximation. Then, more accurate, self-consistent calculations for the fundamental and second harmonic low-voltage sub-THz gyrotron designs were carried out. Results of these calculations are presented and discussed. It is shown that operation of the fundamental and second harmonic gyrotrons with noticeable efficiencies is possible even at voltages as low as 5-10 kV. Even the third harmonic gyrotrons can operate at voltages about 15 kV, albeit with rather low efficiency (1%-2% in the submillimeter wavelength region).

  15. DARHT II Scaled Accelerator Tests on the ETA II Accelerator*

    Energy Technology Data Exchange (ETDEWEB)

    Weir, J T; Anaya Jr, E M; Caporaso, G J; Chambers, F W; Chen, Y; Falabella, S; Lee, B S; Paul, A C; Raymond, B A; Richardson, R A; Watson, J A; Chan, D; Davis, H A; Day, L A; Scarpetti, R D; Schultze, M E; Hughes, T P

    2005-05-26

    The DARHT II accelerator at LANL is preparing a series of preliminary tests at the reduced voltage of 7.8 MeV. The transport hardware between the end of the accelerator and the final target magnet was shipped to LLNL and installed on ETA II. Using the ETA II beam at 5.2 MeV we completed a set of experiments designed reduce start up time on the DARHT II experiments and run the equipment in a configuration adapted to the reduced energy. Results of the beam transport using a reduced energy beam, including the kicker and kicker pulser system will be presented.

  16. Systems and methods for the magnetic insulation of accelerator electrodes in electrostatic accelerators

    Science.gov (United States)

    Grisham, Larry R

    2013-12-17

    The present invention provides systems and methods for the magnetic insulation of accelerator electrodes in electrostatic accelerators. Advantageously, the systems and methods of the present invention improve the practically obtainable performance of these electrostatic accelerators by addressing, among other things, voltage holding problems and conditioning issues. The problems and issues are addressed by flowing electric currents along these accelerator electrodes to produce magnetic fields that envelope the accelerator electrodes and their support structures, so as to prevent very low energy electrons from leaving the surfaces of the accelerator electrodes and subsequently picking up energy from the surrounding electric field. In various applications, this magnetic insulation must only produce modest gains in voltage holding capability to represent a significant achievement.

  17. Choice of operating voltage for a transmission electron microscope

    Energy Technology Data Exchange (ETDEWEB)

    Egerton, R.F., E-mail: regerton@ualberta.ca

    2014-10-15

    An accelerating voltage of 100–300 kV remains a good choice for the majority of TEM or STEM specimens, avoiding the expense of high-voltage microscopy but providing the possibility of atomic resolution even in the absence of lens-aberration correction. For specimens thicker than a few tens of nm, the image intensity and scattering contrast are likely to be higher than at lower voltage, as is the visibility of ionization edges below 1000 eV (as required for EELS elemental analysis). In thick (>100 nm) specimens, higher voltage ensures less beam broadening and better spatial resolution for STEM imaging and EDX spectroscopy. Low-voltage (e.g. 30 kV) TEM or STEM is attractive for a very thin (e.g. 10 nm) specimen, as it provides higher scattering contrast and fewer problems for valence-excitation EELS. Specimens that are immune to radiolysis suffer knock-on damage at high current densities, and this form of radiation damage can be reduced or avoided by choosing a low accelerating voltage. Low-voltage STEM with an aberration-corrected objective lens (together with a high-angle dark-field detector and/or EELS) offers atomic resolution and elemental identification from very thin specimens. Conventional TEM can provide atomic resolution in low-voltage phase-contrast images but requires correction of chromatic aberration and preferably an electron-beam monochromator. Many non-conducting (e.g. organic) specimens damage easily by radiolysis and radiation damage then determines the TEM image resolution. For bright-field scattering contrast, low kV can provide slightly better dose-limited resolution if the specimen is very thin (a few nm) but considerably better resolution is possible from a thicker specimen, for which higher kV is required. Use of a phase plate in a conventional TEM offers the most dose-efficient way of achieving atomic resolution from beam-sensitive specimens. - Highlights: • 100–300 kV accelerating voltage is suitable for TEM specimens of typical

  18. Horizontal Accelerator

    Data.gov (United States)

    Federal Laboratory Consortium — The Horizontal Accelerator (HA) Facility is a versatile research tool available for use on projects requiring simulation of the crash environment. The HA Facility is...

  19. Future accelerators

    CERN Document Server

    Hübner, K

    1999-01-01

    An overview of the various schemes for electron-positron linear colliders is given and the status of the development of key components and the various test facilities is given. The present studies of muon-muon colliders and very large hadron colliders are summarized including the plans for component development and tests. Accelerator research and development to achieve highest gradients in linear accelerators is outlined. (44 refs).

  20. Device for monitoring cell voltage

    Science.gov (United States)

    Doepke, Matthias [Garbsen, DE; Eisermann, Henning [Edermissen, DE

    2012-08-21

    A device for monitoring a rechargeable battery having a number of electrically connected cells includes at least one current interruption switch for interrupting current flowing through at least one associated cell and a plurality of monitoring units for detecting cell voltage. Each monitoring unit is associated with a single cell and includes a reference voltage unit for producing a defined reference threshold voltage and a voltage comparison unit for comparing the reference threshold voltage with a partial cell voltage of the associated cell. The reference voltage unit is electrically supplied from the cell voltage of the associated cell. The voltage comparison unit is coupled to the at least one current interruption switch for interrupting the current of at least the current flowing through the associated cell, with a defined minimum difference between the reference threshold voltage and the partial cell voltage.

  1. High voltage pulse generator

    Science.gov (United States)

    Fasching, George E.

    1977-03-08

    An improved high-voltage pulse generator has been provided which is especially useful in ultrasonic testing of rock core samples. An N number of capacitors are charged in parallel to V volts and at the proper instance are coupled in series to produce a high-voltage pulse of N times V volts. Rapid switching of the capacitors from the paralleled charging configuration to the series discharging configuration is accomplished by using silicon-controlled rectifiers which are chain self-triggered following the initial triggering of a first one of the rectifiers connected between the first and second of the plurality of charging capacitors. A timing and triggering circuit is provided to properly synchronize triggering pulses to the first SCR at a time when the charging voltage is not being applied to the parallel-connected charging capacitors. Alternate circuits are provided for controlling the application of the charging voltage from a charging circuit to be applied to the parallel capacitors which provides a selection of at least two different intervals in which the charging voltage is turned "off" to allow the SCR's connecting the capacitors in series to turn "off" before recharging begins. The high-voltage pulse-generating circuit including the N capacitors and corresponding SCR's which connect the capacitors in series when triggered "on" further includes diodes and series-connected inductors between the parallel-connected charging capacitors which allow sufficiently fast charging of the capacitors for a high pulse repetition rate and yet allow considerable control of the decay time of the high-voltage pulses from the pulse-generating circuit.

  2. Multi-beam linear accelerator EVT

    Energy Technology Data Exchange (ETDEWEB)

    Teryaev, Vladimir E., E-mail: vladimir_teryaev@mail.ru [Omega-P, Inc., New Haven, CT 06510 (United States); Kazakov, Sergey Yu. [Fermilab, Batavia, IL 60510 (United States); Hirshfield, Jay L. [Omega-P, Inc., New Haven, CT 06510 (United States); Yale University, New Haven, CT 06511 (United States)

    2016-09-01

    A novel electron multi-beam accelerator is presented. The accelerator, short-named EVT (Electron Voltage Transformer) belongs to the class of two-beam accelerators. It combines an RF generator and essentially an accelerator within the same vacuum envelope. Drive beam-lets and an accelerated beam are modulated in RF modulators and then bunches pass into an accelerating structure, comprising uncoupled with each other and inductive tuned cavities, where the energy transfer from the drive beams to the accelerated beam occurs. A phasing of bunches is solved by choice correspond distances between gaps of the adjacent cavities. Preliminary results of numerical simulations and the initial specification of EVT operating in S-band, with a 60 kV gun and generating a 2.7 A, 1.1 MV beam at its output is presented. A relatively high efficiency of 67% and high design average power suggest that EVT can find its use in industrial applications.

  3. STATUS OF THE DIELECTRIC WALL ACCELERATOR

    Energy Technology Data Exchange (ETDEWEB)

    Caporaso, G J; Chen, Y; Sampayan, S; Akana, G; Anaya, R; Blackfield, D; Carroll, J; Cook, E; Falabella, S; Guethlein, G; Harris, J; Hawkins, S; Hickman, B; Holmes, C; Horner, A; Nelson, S; Paul, A; Pearson, D; Poole, B; Richardson, R; Sanders, D; Selenes, K; Sullivan, J; Wang, L; Watson, J; Weir, J

    2009-04-22

    The dielectric wall accelerator (DWA) system being developed at the Lawrence Livermore National Laboratory (LLNL) uses fast switched high voltage transmission lines to generate pulsed electric fields on the inside of a high gradient insulating (HGI) acceleration tube. High electric field gradients are achieved by the use of alternating insulators and conductors and short pulse times. The system is capable of accelerating any charge to mass ratio particle. Applications of high gradient proton and electron versions of this accelerator will be discussed. The status of the developmental new technologies that make the compact system possible will be reviewed. These include, high gradient vacuum insulators, solid dielectric materials, photoconductive switches and compact proton sources.

  4. Upgrading of the high-current accelerator 'Tonus'

    CERN Document Server

    Ryabchikov, A I; Karpov, V B; Usov, Y P

    2001-01-01

    In the paper presented,the new technical development of the high-current electron accelerator 'Tonus - NT' (Tomsk nanosecond accelerator - new technologies ) is described. It has been developed taking into account the experience of 30-years exploitation of the previous analogue - the accelerator 'Tonus'. The scheme of the accelerator includes the high-voltage transformer with resonant contours (Tesla transformer) charging the double forming line filled with the transformer oil and the high-voltage diode. The gas-filled trigatron spark gap with up to 10 atm operating pressure is used for the double forming line switching. The main accelerator parameters are as follows:accelerating voltage range 0.4-1.7 MeV, line impedance 36.6 OMEGA, pulse duration 60 ns, pulse repetition rate up to 10 pps.

  5. 新型BCD加法器及其可逆逻辑实现%New BCD Adders and Their Reversible Logic Implementation

    Institute of Scientific and Technical Information of China (English)

    周日贵; 张满群; 吴茜; 施洋

    2011-01-01

    Reversible logic is a new research area that has developed rapidly in recent years. It has received great attention in all aspects due to their ability to reduce the power dissipation. This paper proposes a new reversible logic gate-NC gate. This gate can independently complete Binary Coded Decimal (BCD) adder overflow detection logic. Meanwhile, with 4×4 reversible adder circuits-ZS gate which was designed by the author, a new reversible BCD adder is designed in this paper. The proposed reversible BCD adder is optimized in terms of number of reversible gates and garbage outputs compared to the previous counterparts.%可逆逻辑是最近几年迅速发展起来的新兴研究领域,由于它在传递信息时能减少能量损耗而引起各方面越来越多的关注.该文设计了一种新型的4×4可逆逻辑门—NC门,该门能够独立实现可逆BCD溢出检测逻辑电路.同时,借助作者曾经设计的4×4可逆加法电路—ZS门,设计出一种新型可逆BCD加法电路.设计的电路与以往的相比,无论是在门的数量上还是在垃圾输出的数量上都达到最优的效果.

  6. 低功耗非全摆幅互补传输管加法器%Low-Power Non-full Swing Complementary Pass-Transistor Logic Adder

    Institute of Scientific and Technical Information of China (English)

    王宗静; 齐家月

    2006-01-01

    文章提出了一种新型传输管全加器,该全加器采用互补传输管逻辑(Complementary Pass-Transistor Logic)实现.与现有的CPL全加器相比:该全加器具有面积、进位速度和功耗上的优势:并且提供了进位传播信号的输出,可以更简单的构成旁路进位加法器(Carry SkipAdder).在此全加器基础上可以实现一种新型行波进位加法器(Ripple Carry Adder),其内部进位信号处于非全摆幅状态,具有高速低功耗的特点.HSPICE模拟表明:对4位加法器而言,其速度接近CMOS提前进位加法器(Carry Look ahead Adder),而功耗减小了61%.适用于高性能、低功耗的VLSI电路设计.

  7. 基于组间进位预测的快速进位加法器%Rapid Carry Adder Based on Carry Forecast Between Groups

    Institute of Scientific and Technical Information of China (English)

    丁宜栋; 刘昌明; 方湘艳

    2011-01-01

    为加快密码系统中大数加法的运算速度,提出并实现一种基于组间进位预测的快速进位加法器.将参与加法运算的大数进行分组,每个分组采用改进的超前进位技术以减少组内进位延时,组间通过进位预测完成不同进位状态下的加法运算,通过每个组产生的进位状态判断最终结果.性能分析表明,该进位加法器实现1024位大数加法运算的速度较快.%This paper presents and realizes a rapid carry adder based on carry forecast between groups to improve the speed of the large numbers adder in some cryptography systems. The large numbers is divided into many groups, the delay of carry-chain is reduced by carry lookahead in group. The group addition operation of different carry state is finished by carry forecast between groups. The addition sun of different carry forecast state is selected as the final result based on the carry state. Performance analysis shows that the computing speed of the carry adder is faster when realizing the 1 024 bit large numbers add operation.

  8. 量子全加法器的修改和算法研究%Research on the algorithm of a corrected quantum full adder

    Institute of Scientific and Technical Information of China (English)

    郭良; 王利光; TERENCE K S W; TSUKADA M

    2007-01-01

    通过与经典全加器的基本模型进行比较后,讨论了一个改进后的量子平面加法器的基本构型.对其原理、组件和算法进行了研究,比较了本加法器两个主要组件与一般量子加法器的不同.作为应用的例,设计了一个n比特量子全加法器的模型,对其具体运算过程和基本功能进行了说明.%A corrected prototype of quantum plain adder after comparing with the classical counter part is presented. The authors discuss its basic principles, components and algorithm in this prototype, and also explain the difference between two main components used in the adder and those in the general quantum adder. For application, a construction model to perform n -qubit addition is built and its function is simply desoribed.

  9. The Application of Full Adder in the Logical Design%全加器在逻辑设计中的应用

    Institute of Scientific and Technical Information of China (English)

    唐民丽; 吴恒玉

    2016-01-01

    This paper provides some design methods of irregular logical circuits with full adders based on the logical function and universality of full adders.Some examples are given to illustrate the process of the logical design of full adders and the application methods in logical circuits designs in detail. This method enjoys such merits as convenience in usage, rapidity in design and simplification of the circuits.%从全加器的逻辑功能和通用性出发,提出一些应用全加器的非常规逻辑电路设计方法,并举例说明全加器的逻辑设计过程及全加器在逻辑电路设计中的具体应用方法。利用全加器的非常规逻辑电路设计方法,具有使用方便、设计迅速、简化电路等优点。

  10. Voltage Regulators for Photovoltaic Systems

    Science.gov (United States)

    Delombard, R.

    1986-01-01

    Two simple circuits developed to provide voltage regulation for highvoltage (i.e., is greater than 75 volts) and low-voltage (i.e., is less than 36 volts) photovoltaic/battery power systems. Use of these circuits results in voltage regulator small, low-cost, and reliable, with very low power dissipation. Simple oscillator circuit controls photovoltaic-array current to regulate system voltage and control battery charging. Circuit senses battery (and system) voltage and adjusts array current to keep battery voltage from exceeding maximum voltage.

  11. Studying Voltage Transformer Ferroresonance

    Directory of Open Access Journals (Sweden)

    Hamid Radmanesh

    2012-09-01

    Full Text Available This study studies the effect of Circuit Breaker Shunt Resistance (CBSR, Metal Oxide Vaistor (MOV and Neutral earth Resistance (NR on the control of ferroresonance in the voltage transformer. It is expected that NR can controlled ferroresonance better than MOV and CBSR. Study has been done on a one phase voltage transformer rated 100 VA, 275 kV. The simulation results reveal that considering the CBSR and MOV exhibits a great mitigating effect on ferroresonance overvoltages, but these resistances cannot control these phenomena for all range of parameters. By applying NR to the system structure, ferroresonance has been controlled and its amplitude has been damped for all parameters values.

  12. Helical Pulseline Structures for Ion Acceleration

    CERN Document Server

    Briggs, R J; Waldron, William

    2005-01-01

    The basic concept of the "Pulseline Ion Accelerator" involves launching a ramped high voltage pulse on a broad band traveling wave (slow-wave) structure. An applied voltage pulse at the input end with a segment rising linearly in time becomes a linear voltage ramp in space that propagates down the line, corresponding to a (moving) region of constant axial accelerating electric field. The ions can "surf" on this traveling wave, experiencing a total energy gain that can greatly exceed the peak of the applied voltage. The applied voltage waveform can also be shaped to longitudinally confine the beam against its own space charge forces, and (in the final stage) to impart an inward compression to the beam for neutralized drift compression in heavy ion HEDP applications. In the first stages of a heavy ion accelerator, the pulseline velocity needs to be the order of 1% of the speed of light and the line must be sufficiently non-dispersive for the broad band voltage pulse propagating down the line to have minimal dis...

  13. Conception design of helium ion FFAG accelerator with induction accelerating cavity

    Institute of Scientific and Technical Information of China (English)

    LUO Huan-Li; XU Yu-Cun; WANG Xiang-Qi; XU Hong-Liang

    2013-01-01

    In the recent decades of particle accelerator R&D area,the fixed field alternating gradient (FFAG) accelerator has become a highlight for some advantages of its higher beam intensity and lower cost,although there are still some technical challenges.In this paper,the FFAG accelerator is adopted to accelerate a helium ion beam on the one hand for the study of helium embrittlement on fusion reactor envelope material and on the other hand for promoting the conception research and design of the FFAG accelerator and exploring the possibility of developing high power FFAG accelerators.The conventional period focusing unit of the helium ion FFAG accelerator and threedimensional model of the large aperture combinatorial magnet by OPERA-TOSCA are given.For low energy and low revolution frequency,induction acceleration is proposed to replace conventional radio frequency (RF) acceleration for the helium ion FFAG accelerator,which avoids the potential breakdown of the acceleration field caused by the wake field and improves the acceleration repetition frequency to gain higher beam intensity.The main parameters and three-dimensional model of induction cavity are given.Two special constraint waveforms are proposed to refrain from particle accelerating time slip (AT) caused by accelerating voltage drop of flat top and energy deviation.The particle longitudinal motion in two waveforms is simulated.

  14. Acceleration schedules for a recirculating heavy-ion accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Sharp, W.M.; Grote, D.P.

    2002-05-01

    Recent advances in solid-state switches have made it feasible to design programmable, high-repetition-rate pulsers for induction accelerators. These switches could lower the cost of recirculating induction accelerators, such as the ''small recirculator'' at Lawrence Livermore National Laboratory (LLNL), by substantially reducing the number of induction modules. Numerical work is reported here to determine what effects the use of fewer pulsers at higher voltage would have on the beam quality of the LLNL small recirculator. Lattices with different numbers of pulsers are examined using the fluid/envelope code CIRCE, and several schedules for acceleration and compression are compared for each configuration. For selected schedules, the phase-space dynamics is also studied using the particle-in-cell code WARP3d.

  15. VOLTAGE REGULATORS ASYNCHRONOUS GENERATORS

    Directory of Open Access Journals (Sweden)

    Grigorash O. V.

    2015-06-01

    Full Text Available A promising is currently the use of asynchronous generators with capacitive excitation as a source of electricity in stand-alone power systems. Drive asynchronous generators may exercise as a thermal engine and wind wheel wind power plant or turbines of small hydropower plants. The article discusses the structural and schematics of voltage stabilizers and frequency of asynchronous generators with improved operational and technical specifications. Technical novelty of design solutions of the magnetic system and stabilizers asynchronous generator of electricity parameters confirmed by the patents for the invention of the Russian Federation. The proposed technical solution voltage stabilizer asynchronous generators, can reduce the weight of the block capacitors excitation and reactive power compensation, as well as to simplify the control system power circuit which has less power electronic devices. For wind power plants it is an important issue not only to stabilize the voltage of the generator, but also the frequency of the current. Recommend functionality stabilizer schemes parameters of electric power made for direct frequency converters with artificial and natural switching power electronic devices. It is also proposed as part of stabilization systems use single-phase voltage, three-phase transformers with rotating magnetic field, reduce the level of electromagnetic interference generated by power electronic devices for switching, enhance the efficiency and reliability of the stabilizer.

  16. Geomagnetism and Induced Voltage

    Science.gov (United States)

    Abdul-Razzaq, W.; Biller, R. D.

    2010-01-01

    Introductory physics laboratories have seen an influx of "conceptual integrated science" over time in their classrooms with elements of other sciences such as chemistry, biology, Earth science, and astronomy. We describe a laboratory to introduce this development, as it attracts attention to the voltage induced in the human brain as it…

  17. High-voltage picoamperemeter

    Energy Technology Data Exchange (ETDEWEB)

    Bugl, Andrea; Ball, Markus; Boehmer, Michael; Doerheim, Sverre; Hoenle, Andreas; Konorov, Igor [Technische Universitaet Muenchen, Garching (Germany); Ketzer, Bernhard [Technische Universitaet Muenchen, Garching (Germany); Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany)

    2014-07-01

    Current measurements in the nano- and picoampere region on high voltage are an important tool to understand charge transfer processes in micropattern gas detectors like the Gas Electron Multiplier (GEM). They are currently used to e.g. optimize the field configuration in a multi-GEM stack to be used in the ALICE TPC after the upgrade of the experiment during the 2nd long shutdown of the LHC. Devices which allow measurements down to 1pA at high voltage up to 6 kV have been developed at TU Muenchen. They are based on analog current measurements via the voltage drop over a switchable shunt. A microcontroller collects 128 digital ADC values and calculates their mean and standard deviation. This information is sent with a wireless transmitting unit to a computer and stored in a root file. A nearly unlimited number of devices can be operated simultaneously and read out by a single receiver. The results can also be displayed on a LCD directly at the device. Battery operation and the wireless readout are important to protect the user from any contact to high voltage. The principle of the device is explained, and systematic studies of their properties are shown.

  18. Elemental mapping at the atomic scale using low accelerating voltages

    Energy Technology Data Exchange (ETDEWEB)

    Botton, Gianluigi A., E-mail: gbotton@mcmaster.ca [Canadian Centre for Electron Microscopy and Department of Materials Science and Engineering, McMaster University, Main Street West, Hamilton Ontario, Canada L8S 4M1 (Canada); Lazar, Sorin [Canadian Centre for Electron Microscopy and Department of Materials Science and Engineering, McMaster University, Main Street West, Hamilton Ontario, Canada L8S 4M1 (Canada); FEI Electron Optics, 5600 KA Eindhoven (Netherlands); Dwyer, Christian [Monash Centre for Electron Microscopy and Department of Materials Engineering, Monash University, Victoria 3800 (Australia)

    2010-07-15

    Atomic resolved elemental mapping is demonstrated at 80 keV with an aberration-corrected scanning transmission electron microscope on specimens of SrTiO{sub 3} and BaTiO{sub 3}/SrTiO{sub 3}. The maps were acquired with acquisition times as short as 30 ms per pixel (limited by the spectrometer speed), and show very high signal-to-noise ratio and very good detection limits. The features in the elemental maps are interpreted with the help of elastic-inelastic multislice calculations, which show good agreement with experimental images. The elemental maps of Ti, Sr and Ba and their contrast at the interface between BaTiO{sub 3} and SrTiO{sub 3} are discussed, following a comparison with calculations, assuming an atomically sharp interface. The features in the energy-filtered maps and the background intensities, and the influence of the energy position of the integration windows are discussed in terms of the origins of the signals and the features with respect to the details shown in the high-angle annular dark-field images. The benefits of elemental mapping at 80 keV as compared to 200 keV are also discussed in terms of electron beam damage. Finally, applications of elemental mapping to the detection of La atoms in solid solution in Ba{sub 3.25}La{sub 0.75}Ti{sub 3}O{sub 12} films are also shown.

  19. High voltage source control on FODS

    Science.gov (United States)

    Patalakha, D. I.; Kalinin, A. Yu; Kulagin, N. V.

    2017-01-01

    The implementation of the high voltage power supply control system (HVPSCS) for experimental setup FODS (FOcusing Doublearmed Spectrometer) at accelerator U-70 of the Federal State Budgetary Institution State Research Center Of Russia Institute for High Energy Physics of the National Research Centre “Kurchatov Institute” (hereinafter referred to as IHEP) or for the test bench of the detector components is considered. The required set of hardware is defined and the appropriate software to operate HVPSCS is written in C/C++ codes. The date acquisition (DAQ) system [1] makes automatic control on HVPSCS for data taking run. It allows to get the dependence of appropriate detector parameters on the high voltage supply values and choose its optimal values for FODS detectors. The test run results of HVPSCS are presented.

  20. Accelerated Unification

    OpenAIRE

    Arkani-Hamed, Nima; Cohen, Andrew; Georgi, Howard

    2001-01-01

    We construct four dimensional gauge theories in which the successful supersymmetric unification of gauge couplings is preserved but accelerated by N-fold replication of the MSSM gauge and Higgs structure. This results in a low unification scale of $10^{13/N}$ TeV.

  1. Status report on the folded tandem ion accelerator at BARC

    Indian Academy of Sciences (India)

    P Singh; S K Gupta; M J Kansara; A Agarwal; S Santra; Rajesh Kumar; A Basu; P Sapna; S P Sarode; N B V Subrahmanyam; J P Bhatt; P J Raut; S S Pol; P V Bhagwat; S Kailas; B K Jain

    2002-11-01

    The folded tandem ion accelerator (FOTIA) facility set up at BARC has become operational. At present, it is used for elemental analysis studies using the Rutherford backscattering technique. The beams of 1H, 7Li, 12C, 16O and 19F have been accelerated up to terminal voltages of about 3 MV and are available for experiments. The terminal voltage is stable within ± 2 kV. In this paper, present status of the FOTIA and future plans are discussed.

  2. 4个加数的并行加法器及扩展接口的研究%Research on a parallel adder with 4 binary addends and its interface

    Institute of Scientific and Technical Information of China (English)

    刘杰; 易茂祥

    2009-01-01

    算术逻辑运算单元(ALU)决定着中央处理器(CPU)的性能,而加法器又决定着ALU的性能.为了提高CPU的性能,文章提出了一种4个加数的并行加法器及其接口扩展的研究方案,论述了所提新型加法器的工作原理和过程,同时描述了接口扩充思想;最后,采用MAX+PLUSⅡ对设计电路进行了模拟验证,实验结果说明了所提加法器的设计合理性.%The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit (CPU) , while the adder decides that of the ALU. To improve the performance of the CPU, a parallel adder with 4 binary addends and its interface are proposed. The working principle and process of the novel adder are discussed, and its interface extension is described. Finally,the MAX+PLUS II is a-dopted to simulate and validate the proposed adder. Experimental results indicate that the proposed design scheme is not only reasonable, but it can also calculate 4 binary addends faster than a carry look-ahead adder using the serial adding scheme.

  3. Electron bunch structure in energy recovery linac with high-voltage dc photoelectron gun

    Science.gov (United States)

    Saveliev, Y. M.; Jackson, F.; Jones, J. K.; McKenzie, J. W.

    2016-09-01

    The internal structure of electron bunches generated in an injector line with a dc photoelectron gun is investigated. Experiments were conducted on the ALICE (accelerators and lasers in combined experiments) energy recovery linac at Daresbury Laboratory. At a relatively low dc gun voltage of 230 kV, the bunch normally consisted of two beamlets with different electron energies, as well as transverse and longitudinal characteristics. The beamlets are formed at the head and the tail of the bunch. At a higher gun voltage of 325 kV, the beam substructure is much less pronounced and could be observed only at nonoptimal injector settings. Experiments and computer simulations demonstrated that the bunch structure develops during the initial beam acceleration in the superconducting rf booster cavity and can be alleviated either by increasing the gun voltage to the highest possible level or by controlling the beam acceleration from the gun voltage in the first accelerating structure.

  4. Deployment of low-voltage regulator considering existing voltage control in medium-voltage distribution systems

    Directory of Open Access Journals (Sweden)

    Hiroshi Kikusato

    2016-01-01

    Full Text Available Many photovoltaic (PV systems have been installed in distribution systems. This installation complicates the maintenance of all voltages within the appropriate range in all low-voltage distribution systems (LVDSs because the trends in voltage fluctuation differ in each LVDS. The installation of a low-voltage regulator (LVR that can accordingly control the voltage in each LVDS has been studied as a solution to this problem. Voltage control in a medium-voltage distribution system must be considered to study the deployment of LVRs. In this study, we installed LVRs in the LVDSs in which the existing voltage-control scheme cannot prevent voltage deviation and performed a numerical simulation by using a distribution system model with PV to evaluate the deployment of the LVRs.

  5. Particle Accelerators in China

    Science.gov (United States)

    Zhang, Chuang; Fang, Shouxian

    As the special machines that can accelerate charged particle beams to high energy by using electromagnetic fields, particle accelerators have been widely applied in scientific research and various areas of society. The development of particle accelerators in China started in the early 1950s. After a brief review of the history of accelerators, this article describes in the following sections: particle colliders, heavy-ion accelerators, high-intensity proton accelerators, accelerator-based light sources, pulsed power accelerators, small scale accelerators, accelerators for applications, accelerator technology development and advanced accelerator concepts. The prospects of particle accelerators in China are also presented.

  6. Analyzing of Dynamic Voltage Restorer in Series Compensation Voltage

    Directory of Open Access Journals (Sweden)

    Naser Parhizgar

    2012-02-01

    Full Text Available The Dynamic Voltage Restorer (DVR is a series-connected compensator to generate a controllable voltage to against the short-term voltage disturbances. The technique of DVR is an effective and cost competitive approach to improve voltage quality at the load side. This study presents a single-phase and threephase DVR system with reduced switch-count topology to protect the sensitive load against abnormal voltage conditions. Most basic function, the DVR configuration consist of a two level Voltage Source Converter (VSC, a dc energy storage device, a coupling transformer Connected in shunt with the ac system This study presents the application of Dynamic Voltage Restorer (DVR on power distribution systems for mitigation of voltage sag at critical loads. DVR is one of the compensating types of custom power devices. The DVR, which is based on forced-commutated Voltage Source Converter (VSC has been proved suitable for the task of compensating voltage sags/swells. Simulation results are presented to illustrate and understand the performances of DVR in supporting load voltages under voltage sags/swells conditions.

  7. High Voltage Charge Pump

    KAUST Repository

    Emira, Ahmed A.

    2014-10-09

    Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.

  8. Increased voltage photovoltaic cell

    Science.gov (United States)

    Ross, B.; Bickler, D. B.; Gallagher, B. D. (Inventor)

    1985-01-01

    A photovoltaic cell, such as a solar cell, is provided which has a higher output voltage than prior cells. The improved cell includes a substrate of doped silicon, a first layer of silicon disposed on the substrate and having opposite doping, and a second layer of silicon carbide disposed on the first layer. The silicon carbide preferably has the same type of doping as the first layer.

  9. High Voltage Seismic Generator

    Science.gov (United States)

    Bogacz, Adrian; Pala, Damian; Knafel, Marcin

    2015-04-01

    This contribution describes the preliminary result of annual cooperation of three student research groups from AGH UST in Krakow, Poland. The aim of this cooperation was to develop and construct a high voltage seismic wave generator. Constructed device uses a high-energy electrical discharge to generate seismic wave in ground. This type of device can be applied in several different methods of seismic measurement, but because of its limited power it is mainly dedicated for engineering geophysics. The source operates on a basic physical principles. The energy is stored in capacitor bank, which is charged by two stage low to high voltage converter. Stored energy is then released in very short time through high voltage thyristor in spark gap. The whole appliance is powered from li-ion battery and controlled by ATmega microcontroller. It is possible to construct larger and more powerful device. In this contribution the structure of device with technical specifications is resented. As a part of the investigation the prototype was built and series of experiments conducted. System parameter was measured, on this basis specification of elements for the final device were chosen. First stage of the project was successful. It was possible to efficiently generate seismic waves with constructed device. Then the field test was conducted. Spark gap wasplaced in shallowborehole(0.5 m) filled with salt water. Geophones were placed on the ground in straight line. The comparison of signal registered with hammer source and sparker source was made. The results of the test measurements are presented and discussed. Analysis of the collected data shows that characteristic of generated seismic signal is very promising, thus confirms possibility of practical application of the new high voltage generator. The biggest advantage of presented device after signal characteristics is its size which is 0.5 x 0.25 x 0.2 m and weight approximately 7 kg. This features with small li-ion battery makes

  10. MUON ACCELERATION

    Energy Technology Data Exchange (ETDEWEB)

    BERG,S.J.

    2003-11-18

    One of the major motivations driving recent interest in FFAGs is their use for the cost-effective acceleration of muons. This paper summarizes the progress in this area that was achieved leading up to and at the FFAG workshop at KEK from July 7-12, 2003. Much of the relevant background and references are also given here, to give a context to the progress we have made.

  11. Effects of voltage errors caused by gap-voltage and automatic-frequency tuning in an alternating-phase-focused linac

    Science.gov (United States)

    Iwata, Y.; Yamada, S.; Murakami, T.; Fujimoto, T.; Fujisawa, T.; Ogawa, H.; Miyahara, N.; Yamamoto, K.; Hojo, S.; Sakamoto, Y.; Muramatsu, M.; Takeuchi, T.; Mitsumoto, T.; Tsutsui, H.; Watanabe, T.; Ueda, T.

    2008-05-01

    A compact injector for a heavy-ion medical-accelerator complex was developed. It consists of an electron-cyclotron-resonance ion-source (ECRIS) and two linacs, which are a radio-frequency-quadrupole (RFQ) linac and an Interdigital H-mode drift-tube-linac (IH-DTL). Beam acceleration tests of the compact injector were performed, and the designed beam quality was verified by the measured results, as reported earlier. Because the method of alternating-phase-focusing (APF) was used for beam focusing of the IH-DTL, the motion of beam ions would be sensitive to gap-voltage errors, caused during tuning of the gap-voltage distribution and by automatic-frequency tuning in actual operation. To study the effects of voltage errors to beam quality, further measurements were performed during acceleration tests. In this report, the effects of voltage errors for the APF IH-DTL are discussed.

  12. Laser acceleration

    Science.gov (United States)

    Tajima, T.; Nakajima, K.; Mourou, G.

    2017-02-01

    The fundamental idea of Laser Wakefield Acceleration (LWFA) is reviewed. An ultrafast intense laser pulse drives coherent wakefield with a relativistic amplitude robustly supported by the plasma. While the large amplitude of wakefields involves collective resonant oscillations of the eigenmode of the entire plasma electrons, the wake phase velocity ˜ c and ultrafastness of the laser pulse introduce the wake stability and rigidity. A large number of worldwide experiments show a rapid progress of this concept realization toward both the high-energy accelerator prospect and broad applications. The strong interest in this has been spurring and stimulating novel laser technologies, including the Chirped Pulse Amplification, the Thin Film Compression, the Coherent Amplification Network, and the Relativistic Mirror Compression. These in turn have created a conglomerate of novel science and technology with LWFA to form a new genre of high field science with many parameters of merit in this field increasing exponentially lately. This science has triggered a number of worldwide research centers and initiatives. Associated physics of ion acceleration, X-ray generation, and astrophysical processes of ultrahigh energy cosmic rays are reviewed. Applications such as X-ray free electron laser, cancer therapy, and radioisotope production etc. are considered. A new avenue of LWFA using nanomaterials is also emerging.

  13. Mitigation of Voltage Sags in CIGRE Low Voltage Distribution Network

    DEFF Research Database (Denmark)

    Mustafa, Ghullam; Bak-Jensen, Birgitte; Mahat, Pukar;

    2013-01-01

    problems in the distribution system. The voltage problems dealt with in this paper are to show how to mitigate voltage sags in the CIGRE Low Voltage (LV) test network and networks like this. The voltage sags, for the tested cases in the CIGRE LV test network are mainly due to three phase faults....... The compensation of voltage sags in the different parts of CIGRE distribution network is done by using the four STATCOM compensators already existing in the test grid. The simulations are carried out in DIgSILENT power factory software version 15.0....

  14. Advanced Parallel Prefix Adder Based on Kogge-Stone Architecture%一种改进的基于Kogge-Stone结构的并行前缀加法器

    Institute of Scientific and Technical Information of China (English)

    赵翠华; 娄冕; 张洵颖; 沈绪榜

    2011-01-01

    Based on Kogge-Stone architecture of parallel prefix algorithm,an advanced parallel prefix adder by improving the logic circuit of its architecture levels is proposed. Compared with the traditional one, this adder not only can save the area, power dissipation and delay, but also have more preponderant with the operand bits increase, is suitable for parallel prefix adder of multi-bit operands.%基于并行前缀算法的Kogge-Stone结构,通过改进其结构层次上的逻辑电路,提出一种改进的并行前缀加法器.与传统电路相比,该加法器不仅可以减小面积、功耗和延时而且随着位宽的加大其优势更加明显,是适用于宽位的并行前缀加法器.

  15. Voltage Controlled Dynamic Demand Response

    DEFF Research Database (Denmark)

    Bhattarai, Bishnu Prasad; Bak-Jensen, Birgitte; Mahat, Pukar

    2013-01-01

    . An adaptive dynamic model has been developed to determine composite voltage dependency of an aggregated load on feeder level. Following the demand dispatch or control signal, optimum voltage setting at the LV substation is determined based on the voltage dependency of the load. Furthermore, a new technique...

  16. Charge-pump voltage converter

    Science.gov (United States)

    Brainard, John P.; Christenson, Todd R.

    2009-11-03

    A charge-pump voltage converter for converting a low voltage provided by a low-voltage source to a higher voltage. Charge is inductively generated on a transfer rotor electrode during its transit past an inductor stator electrode and subsequently transferred by the rotating rotor to a collector stator electrode for storage or use. Repetition of the charge transfer process leads to a build-up of voltage on a charge-receiving device. Connection of multiple charge-pump voltage converters in series can generate higher voltages, and connection of multiple charge-pump voltage converters in parallel can generate higher currents. Microelectromechanical (MEMS) embodiments of this invention provide a small and compact high-voltage (several hundred V) voltage source starting with a few-V initial voltage source. The microscale size of many embodiments of this invention make it ideally suited for MEMS- and other micro-applications where integration of the voltage or charge source in a small package is highly desirable.

  17. Transient voltage sharing in series-coupled high voltage switches

    Directory of Open Access Journals (Sweden)

    Editorial Office

    1992-07-01

    Full Text Available For switching voltages in excess of the maximum blocking voltage of a switching element (for example, thyristor, MOSFET or bipolar transistor such elements are often coupled in series - and additional circuitry has to be provided to ensure equal voltage sharing. Between each such series element and system ground there is a certain parasitic capacitance that may draw a significant current during high-speed voltage transients. The "open" switch is modelled as a ladder network. Analy­sis reveals an exponential progression in the distribution of the applied voltage across the elements. Overstressing thus oc­curs in some of the elements at levels of the total voltage that are significantly below the design value. This difficulty is overcome by grading the voltage sharing circuitry, coupled in parallel with each element, in a prescribed manner, as set out here.

  18. Accelerators and the Accelerator Community

    Energy Technology Data Exchange (ETDEWEB)

    Malamud, Ernest; Sessler, Andrew

    2008-06-01

    In this paper, standing back--looking from afar--and adopting a historical perspective, the field of accelerator science is examined. How it grew, what are the forces that made it what it is, where it is now, and what it is likely to be in the future are the subjects explored. Clearly, a great deal of personal opinion is invoked in this process.

  19. Design of Carry Look-ahead Adder Based on Logical Structure%基于逻辑结构的超前进位加法器的设计

    Institute of Scientific and Technical Information of China (English)

    白首华; 胡天彤

    2012-01-01

    通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。%Through the research of computer adder, from the standard delay model of a gate and mainly considering the premise of speed, the paper gives the carry advance adder design scheme of the logic circuit. It mainly makes the analysis of the circuit design to the 16, 32-bit adder, through calculating the delay time to compare carry look-ahead adder with the traditional serial binary adder chain, and drawing a conclusion: the advanced carry algorithm makes adder operation speed to achieve the most optimal condition in the practical circuit.

  20. accelerating cavity

    CERN Multimedia

    On the inside of the cavity there is a layer of niobium. Operating at 4.2 degrees above absolute zero, the niobium is superconducting and carries an accelerating field of 6 million volts per metre with negligible losses. Each cavity has a surface of 6 m2. The niobium layer is only 1.2 microns thick, ten times thinner than a hair. Such a large area had never been coated to such a high accuracy. A speck of dust could ruin the performance of the whole cavity so the work had to be done in an extremely clean environment.

  1. Impact accelerations

    Science.gov (United States)

    Vongierke, H. E.; Brinkley, J. W.

    1975-01-01

    The degree to which impact acceleration is an important factor in space flight environments depends primarily upon the technology of capsule landing deceleration and the weight permissible for the associated hardware: parachutes or deceleration rockets, inflatable air bags, or other impact attenuation systems. The problem most specific to space medicine is the potential change of impact tolerance due to reduced bone mass and muscle strength caused by prolonged weightlessness and physical inactivity. Impact hazards, tolerance limits, and human impact tolerance related to space missions are described.

  2. Optimized Design on Carry Look-ahead Adder%超前进位加法器的优化设计

    Institute of Scientific and Technical Information of China (English)

    袁浩; 唐建; 方毅

    2014-01-01

    This paper introduces a novel design method based on the analysis of CLA( Carry Look-ahead) logic algorithm. The wide adder adopts the multilayer CLA block technique between groups,with four bits as a group,to reduce the hardware delay and achieve the parallel and high-speed purpose. The key point is to optimize the design of full adder at the transistor level,and thus to reduce the circuit delay, area and power consumption. Simulation result indicates that compared with the traditional structure, the delay, area and power consumption of the 16 bit CLA could be significantly improved,and the optimized effect in the environment of SMIC65nm thus be achieved.%在对超前加法器逻辑算法分析的基础上,介绍了一种优化设计方法。宽位加法器采用多层CLA( Carry Look-ahead Adder)块技术,按四位为一组进行组间超前进位,减小硬件延时,达到并行、高速的目的。并在晶体管级重点对全加器进行优化设计,从而降低整个电路的延时、面积和功耗。仿真结果表明,在SMIC65 nm工艺下,设计出的16位超前进位加法器,其延时,面积,功耗相比传统结构都有了明显的改善,达到了优化的效果。

  3. No-Voltage Meter

    Science.gov (United States)

    1976-02-01

    VW- IKft, 1/4 H4 -Wv- IK!1, I/4W INTERNAL VOLTAGE NOTE ALL TRANSISTORS ARE 2N43A OR EQUIVALENT GERMANIUM ALLOY PNP AA ALKALINE BATTERY...D-,, regardless of polarity. This signal is then full-wave rectified by the diode-connected Germanium transistor bridge, T,, T-,, T3, and T4... Transistor T5 acts as a second current limiter. Resistor R2 was selected to give 90 f# of full-scale meter deflection with an input signal of 115 volts

  4. Benchmarking of Voltage Sag Generators

    DEFF Research Database (Denmark)

    Yang, Yongheng; Blaabjerg, Frede; Zou, Zhixiang

    2012-01-01

    The increased penetration of renewable energy systems, like photovoltaic and wind power systems, rises the concern about the power quality and stability of the utility grid. Some regulations for Low Voltage Ride-Through (LVRT) for medium voltage or high voltage applications, are coming into force...... to guide these grid-connected distributed power generation systems. In order to verify the response of such systems for voltage disturbance, mainly for evaluation of voltage sags/dips, a Voltage Sag Generator (VSG) is needed. This paper evaluates such sag test devices according to IEC 61000 in order...... to provide cheaper solutions to test against voltage sags. Simulation and experimental results demonstrate that the shunt impedance based VSG solution is the easiest and cheapest one for laboratory test applications. The back-to-back fully controlled converter based VSG is the most flexible solution...

  5. Coordinated Voltage Control of Distributed PV Inverters for Voltage Regulation in Low Voltage Distribution Networks

    DEFF Research Database (Denmark)

    Nainar, Karthikeyan; Pokhrel, Basanta Raj; Pillai, Jayakrishnan Radhakrishna

    2017-01-01

    This paper reviews and analyzes the existing voltage control methods of distributed solar PV inverters to improve the voltage regulation and thereby the hosting capacity of a low-voltage distribution network. A novel coordinated voltage control method is proposed based on voltage sensitivity...... analysis, which is simple for computation and requires moderate automation and communication infrastructure. The proposed method is suitable for a hierarchical control structure where a supervisory controller has the provision to adapt the settings of local PV inverter controllers for overall system...

  6. Heat-pump performance: voltage dip/sag, under-voltage and over-voltage

    Directory of Open Access Journals (Sweden)

    William J.B. Heffernan

    2014-12-01

    Full Text Available Reverse cycle air-source heat-pumps are an increasingly significant load in New Zealand and in many other countries. This has raised concern over the impact wide-spread use of heat-pumps may have on the grid. The characteristics of the loads connected to the power system are changing because of heat-pumps. Their performance during under-voltage events such as voltage dips has the potential to compound the event and possibly cause voltage collapse. In this study, results from testing six heat-pumps are presented to assess their performance at various voltages and hence their impact on voltage stability.

  7. First high-voltage measurements using Ca{sup +} ions at the ALIVE experiment

    Energy Technology Data Exchange (ETDEWEB)

    König, K., E-mail: kkoenig@ikp.tu-darmstadt.de [Technische Universität Darmstadt, Institut für Kernphysik (Germany); Geppert, Ch. [Universität Mainz, Institut für Kernchemie (Germany); Krämer, J.; Maaß, B. [Technische Universität Darmstadt, Institut für Kernphysik (Germany); Otten, E. W. [Universität Mainz, Institut für Physik (Germany); Ratajczyk, T.; Nörtershäuser, W. [Technische Universität Darmstadt, Institut für Kernphysik (Germany)

    2017-11-15

    Many physics experiments depend on accurate high-voltage measurements to determine for example the exact retardation potential of an electron spectrometer as in the KATRIN experiment or the acceleration voltage of the ions at ISOL facilities. Until now only precision high-voltage dividers can be used to measure voltages up to 65 kV with an accuracy of 1 ppm. However, these dividers need frequent calibration and cross-checking and the direct traceability is not given. In this article we will describe the status of an experiment which aims to measure high voltages using collinear laser spectroscopy and which has the potential to provide a high-voltage standard and hence, a calibration source for precision high-voltage dividers on the 1 ppm level.

  8. Voltage Swells Improvement in Low Voltage Network Using Dynamic Voltage Restorer

    Directory of Open Access Journals (Sweden)

    R. Omar

    2011-01-01

    Full Text Available Problem statement: Voltage disturbances are the most common power quality problem due to the increased use of a large numbers of sophisticated electronic equipment in industrial distribution system. The voltage disturbances such as voltage sags, swells, harmonics, unbalance and flickers. High quality in the power supply is needed, since failures due to such disturbances usually have a high impact on production cost. There are many different solutions to compensate voltage disturbances but the use of a DVR is considered to be the most cost effective method. The objective of this study is to propose a new topology of a DVR in order to mitigate voltage swells using a powerful power custom device namely the Dynamic Voltage Restorer (DVR. Approach: New configuration of a DVR with an improvement of a controller based on direct-quadrature-zero method has been introduced to compensate voltage swells in the network. Results: The effectiveness of the DVR with its controller were verify using Matlab/Simulinks SimPower Toolbox and then implemented using 5KVA DVR experimental setup. Simulations and experimental results demonstrate the effective dynamic performance of the proposed configuration. Conclusion: The implimentation of the proposed DVR validate the capabilities in mitigating of voltage swells effectiveness.During voltage swells, the DVR injects an appropriate voltage to maintain the load voltage at its nominal value.

  9. Compact RF ion source for industrial electrostatic ion accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Kwon, Hyeok-Jung, E-mail: hjkwon@kaeri.re.kr; Park, Sae-Hoon; Kim, Dae-Il; Cho, Yong-Sub [Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute, Gyeongsangbukdo 38180 (Korea, Republic of)

    2016-02-15

    Korea Multi-purpose Accelerator Complex is developing a single-ended electrostatic ion accelerator to irradiate gaseous ions, such as hydrogen and nitrogen, on materials for industrial applications. ELV type high voltage power supply has been selected. Because of the limited space, electrical power, and robust operation, a 200 MHz RF ion source has been developed. In this paper, the accelerator system, test stand of the ion source, and its test results are described.

  10. Isomerically Pure Tetramethylrhodamine Voltage Reporters.

    Science.gov (United States)

    Deal, Parker E; Kulkarni, Rishikesh U; Al-Abdullatif, Sarah H; Miller, Evan W

    2016-07-27

    We present the design, synthesis, and application of a new family of fluorescent voltage indicators based on isomerically pure tetramethylrhodamines. These new Rhodamine Voltage Reporters, or RhoVRs, use photoinduced electron transfer (PeT) as a trigger for voltage sensing, display excitation and emission profiles in the green to orange region of the visible spectrum, demonstrate high sensitivity to membrane potential changes (up to 47% ΔF/F per 100 mV), and employ a tertiary amide derived from sarcosine, which aids in membrane localization and simultaneously simplifies the synthetic route to the voltage sensors. The most sensitive of the RhoVR dyes, RhoVR 1, features a methoxy-substituted diethylaniline donor and phenylenevinylene molecular wire at the 5'-position of the rhodamine aryl ring, exhibits the highest voltage sensitivity to date for red-shifted PeT-based voltage sensors, and is compatible with simultaneous imaging alongside green fluorescent protein-based indicators. The discoveries that sarcosine-based tertiary amides in the context of molecular-wire voltage indicators prevent dye internalization and 5'-substituted voltage indicators exhibit improved voltage sensitivity should be broadly applicable to other types of PeT-based voltage-sensitive fluorophores.

  11. High voltage switch triggered by a laser-photocathode subsystem

    Science.gov (United States)

    Chen, Ping; Lundquist, Martin L.; Yu, David U. L.

    2013-01-08

    A spark gap switch for controlling the output of a high voltage pulse from a high voltage source, for example, a capacitor bank or a pulse forming network, to an external load such as a high gradient electron gun, laser, pulsed power accelerator or wide band radar. The combination of a UV laser and a high vacuum quartz cell, in which a photocathode and an anode are installed, is utilized as triggering devices to switch the spark gap from a non-conducting state to a conducting state with low delay and low jitter.

  12. Transient demonstration of exciton behaviours in solid state cathodoluminescence under different driving voltage

    Institute of Scientific and Technical Information of China (English)

    Zhang Fu-Jun; Zhao Su-Ling; Xu Zheng; Huang Jin-Zhao; Xu Xu-Rong

    2007-01-01

    In the solid state cathodoluminescence (SSCL), organic materials were excited by hot electrons accelerated in silicon oxide (SiO2) layer under alternating current (AC). In this paper exciton behaviours were analysed by using transient spectra under different driving voltages. The threshold voltages of SSCL and exciton ionization were obtained from the transient spectra. The recombination radiation occurred when the driving voltage went beyond the threshold voltage of exciton ionization. Prom the transient spectrum of two kinds of luminescence (exciton emission and recombination radiation), it was demonstrated that recombination radiation should benefit from the exciton ionization.

  13. Development of a terminal voltage stabilization system for the FOTIA at BARC

    Indian Academy of Sciences (India)

    M J Kansara; P Sapna; N B V Subrahmanyam; J P Bhatt; P Singh

    2002-11-01

    A terminal voltage stabilization system for the folded tandem ion accelerator (FOTIA) was developed and is in continuous use. The system achieves good voltage stabilization, eliminates ground loops and noise interference. It incorporates a correcting circuit for compensating the mains frequency variations in the GVM amplifier circuit. The present system has two modes of operation namely GVM control mode and slit control mode. A voltage stability of about ± 2 kV has been achieved. In this paper, some of the salient features of the voltage stabilization system are discussed.

  14. Cloacal aerobic bacterial flora and absence of viruses in free-living slow worms (Anguis fragilis), grass snakes (Natrix natrix) and European Adders (Vipera berus) from Germany.

    Science.gov (United States)

    Schmidt, Volker; Mock, Ronja; Burgkhardt, Eileen; Junghanns, Anja; Ortlieb, Falk; Szabo, Istvan; Marschang, Rachel; Blindow, Irmgard; Krautwald-Junghanns, Maria-Elisabeth

    2014-12-01

    Disease problems caused by viral or bacterial pathogens are common in reptiles kept in captivity. There is no information available on the incidence of viral pathogens or the physiological cloacal bacterial flora of common free-living reptiles in Germany. Therefore, 56 free-living reptiles including 23 European adders (Vipera berus), 12 grass snakes (Natrix natrix) and 21 slow worms (Anguis fragilis) were investigated on the island Hiddensee in northeastern Germany. Pharyngeal and cloacal swabs were taken immediately after capture. Bacteriological examination was performed from the cloacal swabs to study the aerobic cloacal flora. Molecular biological examination included amplification of DNA or RNA from adeno-, rana- and ferlaviruses as well as culturing on Russell's viper heart cells for virus isolation. Salmonella spp. were isolated from European adders but not from the other reptiles examined. The minimal inhibitory concentration was determined from the isolated Salmonella spp. However, some potentially human pathogenic bacteria, such as Proteus vulgaris, Aeromonas hydrophila, Klebsiella pneumoniae and Escherichia coli were isolated. Viruses were not detected in any of the examined reptiles. To the authors' best knowledge, the present study is the first survey of viral pathogens in free-living snakes and slow worms in Germany and the first survey of cloacal aerobic bacterial flora of slow worms.

  15. Voltage Dependence of Supercapacitor Capacitance

    Directory of Open Access Journals (Sweden)

    Szewczyk Arkadiusz

    2016-09-01

    Full Text Available Electronic Double-Layer Capacitors (EDLC, called Supercapacitors (SC, are electronic devices that are capable to store a relatively high amount of energy in a small volume comparing to other types of capacitors. They are composed of an activated carbon layer and electrolyte solution. The charge is stored on electrodes, forming the Helmholtz layer, and in electrolyte. The capacitance of supercapacitor is voltage- dependent. We propose an experimental method, based on monitoring of charging and discharging a supercapacitor, which enables to evaluate the charge in an SC structure as well as the Capacitance-Voltage (C-V dependence. The measurement setup, method and experimental results of charging/discharging commercially available supercapacitors in various voltage and current conditions are presented. The total charge stored in an SC structure is proportional to the square of voltage at SC electrodes while the charge on electrodes increases linearly with the voltage on SC electrodes. The Helmholtz capacitance increases linearly with the voltage bias while a sublinear increase of total capacitance was found. The voltage on SC increases after the discharge of electrodes due to diffusion of charges from the electrolyte to the electrodes. We have found that the recovery voltage value is linearly proportional to the initial bias voltage value.

  16. 一种高速低功耗MOS电流模逻辑加法器的设计%Design of a High-Speed and Low-Power MOS Current Mode Logic Adder

    Institute of Scientific and Technical Information of China (English)

    梁蓓; 马奎; 杨发顺; 傅兴华

    2013-01-01

    MOS current mode logic (MCML) circuits with different input terminal were analyzed,and a 4-bit carry-look-ahead adder was designed using MCML circuit.The adder was simulated based on SMIC's 0.13 μm CMOS process.Simulation results showed that the adder had a lower delay,compared to conventional CMOS circuit.The adder is applicable for high-speed and low-power Boolean calculation units.%对具有不同输入端的MOS电流模逻辑(MCML)门电路进行了设计分析,应用MCML单元逻辑电路,设计了一个4位超前进位加法器.基于SMIC 0.13 μm CMOS工艺平台,对设计的加法器进行仿真.结果表明,该加法器的延迟比传统CMOS电路小,可广泛用于高速低功耗逻辑运算单元.

  17. 6加数并行加法器及扩展接口的研究%Research on a Parallel Adder with 6 Binary Addends and Its Interface

    Institute of Scientific and Technical Information of China (English)

    刘杰; 易茂祥

    2009-01-01

    A parallel adder with 6 binary addends and its interface are proposed. Working principle and process of the novel adder are discussed, and its interface extension is described. Finally, MAX+ PLUS II is exploited to simulate and validate the proposed adder. Experimental results indicate that the proposed design scheme is not only reasonable, but also can faster calculate 6 binary addends than a carry look-ahead adder using the serial adding scheme.%提出了一种6个加数的并行加法器及其接口扩展的研究方案.论述了所提新型加法器的工作原理和过程,同时描述了接口扩充思想.最后,采用MAX+PLUSⅡ对设计电路进行了模拟验证.实验结果说明了所提加法器的设计合理性,也证明了该加法器对6个加数的计算比采用串行累加更快.

  18. A New Design of 1-bit Full Adder Based on Majority Function%基于多数决定逻辑的一位全加器设计

    Institute of Scientific and Technical Information of China (English)

    周大鹏; 张自友; 何光普

    2012-01-01

    1-bit Full Adder is a elementary unit in arithmetic operation,A new low power one bit full adder cell Based on Majority Function is presented in this paper after studying and analyzing those published,which is composed of input capacitors and CMOS inverters.the full adder was simulated by PSPICE,The results shows that the new design can realize the logic function of a fall adder successfully.%一位全加器是组成二进制加法器的基本组成单元,在对现有全加器电路研究分析的基础上,提出了基于多数决定逻辑的全加器电路设计.该全加器仅由输入电容和CMOS反向器组成,用PSpice进行了晶体管级模拟.结果显示,这种新的全加器能正确完成加法器的逻辑功能.

  19. Harmonic ratcheting for fast acceleration

    Science.gov (United States)

    Cook, N.; Brennan, J. M.; Peggs, S.

    2014-04-01

    A major challenge in the design of rf cavities for the acceleration of medium-energy charged ions is the need to rapidly sweep the radio frequency over a large range. From low-power medical synchrotrons to high-power accelerator driven subcritical reactor systems, and from fixed focus alternating gradient accelerators to rapid cycling synchrotrons, there is a strong need for more efficient, and faster, acceleration of protons and light ions in the semirelativistic range of hundreds of MeV/u. A conventional way to achieve a large, rapid frequency sweep (perhaps over a range of a factor of 6) is to use custom-designed ferrite-loaded cavities. Ferrite rings enable the precise tuning of the resonant frequency of a cavity, through the control of the incremental permeability that is possible by introducing a pseudoconstant azimuthal magnetic field. However, rapid changes over large permeability ranges incur anomalous behavior such as the "Q-loss" and "f-dot" loss phenomena that limit performance while requiring high bias currents. Notwithstanding the incomplete understanding of these phenomena, they can be ameliorated by introducing a "harmonic ratcheting" acceleration scheme in which two or more rf cavities take turns accelerating the beam—one turns on when the other turns off, at different harmonics—so that the radio frequency can be constrained to remain in a smaller range. Harmonic ratcheting also has straightforward performance advantages, depending on the particular parameter set at hand. In some typical cases it is possible to halve the length of the cavities, or to double the effective gap voltage, or to double the repetition rate. This paper discusses and quantifies the advantages of harmonic ratcheting in general. Simulation results for the particular case of a rapid cycling medical synchrotron ratcheting from harmonic number 9 to 2 show that stability and performance criteria are met even when realistic engineering details are taken into consideration.

  20. 低功耗CMOS三值四输入全加器设计及其应用%Design of low power CMOS ternary 4-input full adder and its application

    Institute of Scientific and Technical Information of China (English)

    雷路路; 沈继忠

    2011-01-01

    Considering that the traditional ternary full adder does not make full use of the carry signal, a novel ternary CMOS 4-input full adder is proposed, which increases data inputs from three to four and makes carry input from binary to ternary compared with conventional ternary 3-input full adder. The number of MOSFET and the chip area can be reduced in the large circuit design by using the proposed ternary 4-input full adder which can process more information and improve the utilization rate of carry signal. A ternary serial carry-propagation adder for three four-bit addends is proposed based on the novel full adder. Hspice simulation shows that the designed circuit has correct logical function. Compared with conventional design, it has lower power dissipation in the circuit design of processing more information based on the novel ternary 4-input full adder.%针对传统三值全加器没有充分利用进位的不足,提出一种新型的三值四输入全加器电路结构,并用CMOS设计这种全加器,与传统的三值三输入全加器相比,将原有的输入由3个增加到4个,将原有的进位由二值信号变为三值信号.所提出的三值四输入全加器增加了处理的信息量,提高了进位端的利用率,在较大电路设计中能减少所用加法器模块的数量,并减少所用管子数和降低芯片面积.基于该新型全加器,设计了3个四位三值数串行加法电路.经Hspice模拟,所设计的电路有正确的逻辑功能,与基于传统三值三输入全加器的设计相比,在处理信息量较大的电路设计中具有很好的低功耗特性.

  1. Design of High-Performance 32 bit Adder with Semi-Dynamic Circuit%基于半动态电路的32位高性能加法器设计

    Institute of Scientific and Technical Information of China (English)

    刘志哲; 仲顺安; 袁家芬

    2011-01-01

    描述了一种采用半动态电路的32位高性能加法器的设计.设计中改进了现有稀疏树结构中的输出进位逻辑,在此基础上,设计了一种容偏斜多米诺和静态电路相结合的半动态电路,以及相应的多个控制时钟的时序策略.根据几种不同的加法器负载驱动情况,分别设计出不同的电路尺寸.采用SMIC 1.8 V 0.18 μm CMOS工艺,在不同条件下的仿真结果表明,加法器电路取得了良好的性能.%This paper presents a programme of designing 32 bit high-performance adder with semidynamic circuit. With modified output carry logic in sparse-tree structure, the semi-dynamic adder circuit, which includes skew-tolerant dynamic domino-circuit and static circuit, and its multiple clocks timing scheme were designed. The different transistor's sizes of adder were designed to fit the different loads and drive conditions of the adder. In SMIC 1.8 V 0. 18 μm technology, the simulation results under different conditions show that the designed adder has a high performance.

  2. SPS RF Accelerating Cavity

    CERN Multimedia

    1979-01-01

    This picture shows one of the 2 new cavities installed in 1978-1979. The main RF-system of the SPS comprises four cavities: two of 20 m length and two of 16.5 m length. They are all installed in one long straight section (LSS 3). These cavities are of the travelling-wave type operating at a centre frequency of 200.2 MHz. They are wideband, filling time about 700 ns and untuned. The power amplifiers, using tetrodes are installed in a surface building 200 m from the cavities. Initially only two cavities were installed, a third cavity was installed in 1978 and a forth one in 1979. The number of power amplifiers was also increased: to the first 2 MW plant a second 2 MW plant was added and by end 1979 there were 8 500 kW units combined in pairs to feed each of the 4 cavities with up to about 1 MW RF power, resulting in a total accelerating voltage of about 8 MV. See also 7412016X, 7412017X, 7411048X

  3. Digital measurement system for the LHC klystron high voltage modulator.

    CERN Document Server

    Mikkelsen, Anders

    Accelerating voltage in the Large Hadron Collider (LHC) is created by a means of 16 superconducting standing wave RF cavities, each fed by a 400MHz/300kW continuous wave klystron amplifier. Part of the upgrade program for the LHC long shutdown one is to replace the obsolete analogue current and voltage measurement circuitry located in the high voltage bunkers by a new, digital system, using ADCs and optical fibres. A digital measurement card is implemented and integrated into the current HV modulator oil tank (floating at -58kV) and interfaced to the existing digital VME boards collecting the data for several klystrons at the ground potential. Measured signals are stored for the logging, diagnostics and post-mortem analysis purposes.

  4. Programmable differential capacitance-to-voltage converter for MEMS accelerometers

    Science.gov (United States)

    Royo, G.; Sánchez-Azqueta, C.; Gimeno, C.; Aldea, C.; Celma, S.

    2017-05-01

    Capacitive MEMS sensors exhibit an excellent noise performance, high sensitivity and low power consumption. They offer a huge range of applications, being the accelerometer one of its main uses. In this work, we present the design of a capacitance-to-voltage converter in CMOS technology to measure the acceleration from the capacitance variations. It is based on a low-power, fully-differential transimpedance amplifier with low input impedance and a very low input noise.

  5. Classification of electrical discharges in DC Accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Banerjee, Srutarshi, E-mail: sruban.stephens@gmail.com [Accelerator and Pulse Power Division, Bhabha Atomic Research Centre, Trombay, Mumbai 400085 (India); Deb, A.K. [Department of Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302 (India); Rajan, Rehim N. [Accelerator and Pulse Power Division, Bhabha Atomic Research Centre, Trombay, Mumbai 400085 (India); Kishore, N.K. [Department of Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302 (India)

    2016-08-11

    Controlled electrical discharge aids in conditioning of the system while uncontrolled discharges damage its electronic components. DC Accelerator being a high voltage system is no exception. It is useful to classify electrical discharges according to the severity. Experimental prototypes of the accelerator discharges are developed. Photomultiplier Tubes (PMTs) are used to detect the signals from these discharges. Time and Frequency domain characteristics of the detected discharges are used to extract features. Machine Learning approaches like Fuzzy Logic, Neural Network and Least Squares Support Vector Machine (LSSVM) are employed to classify the discharges. This aids in detecting the severity of the discharges.

  6. Classification of electrical discharges in DC Accelerators

    Science.gov (United States)

    Banerjee, Srutarshi; Deb, A. K.; Rajan, Rehim N.; Kishore, N. K.

    2016-08-01

    Controlled electrical discharge aids in conditioning of the system while uncontrolled discharges damage its electronic components. DC Accelerator being a high voltage system is no exception. It is useful to classify electrical discharges according to the severity. Experimental prototypes of the accelerator discharges are developed. Photomultiplier Tubes (PMTs) are used to detect the signals from these discharges. Time and Frequency domain characteristics of the detected discharges are used to extract features. Machine Learning approaches like Fuzzy Logic, Neural Network and Least Squares Support Vector Machine (LSSVM) are employed to classify the discharges. This aids in detecting the severity of the discharges.

  7. Preinjector for Linac 1, accelerating column

    CERN Multimedia

    1974-01-01

    For a description of the Linac 1 preinjector, please see first 7403070X. High up on the wall of the Faraday cage (7403073X) is this drum-shaped container of the ion source (7403083X). It is mounted at the HV end of the accelerating column through which the ions (usually protons; many other types of ions in the course of its long history) proceed through the Faraday cage wall to the low-energy end (at ground potential) of Linac 1. The 520 kV accelerating voltage was supplied by a SAMES generator (7403074X).

  8. Design of Optimized Conditional Speculative Decimal Adders%条件推测性十进制加法器的优化设计

    Institute of Scientific and Technical Information of China (English)

    崔晓平; 王书敏; 刘伟强; 董文雯

    2016-01-01

    There are increasing interests in hardware support for decimal arithmetic due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications. New specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard. In this paper, the algorithm and architecture of decimal addition is studied comprehensively. A decimal adder is designed by using the parallel-prefix/carry-select architecture. The parallel-prefix unit is used to optimize the decimal carry select adder. The decimal adder has been realized by Verilog HDL and simulated with ModelSim. The synthesis results of this design by Design Compiler is also given and analyzed under Nangate Open Cell 45nm library. The results show that the delay performance of the proposed circuit can be improved by up to 12.3%.%随着商业计算和金融分析等高精度计算应用领域的高速发展,提供硬件支持十进制算术运算变得越来越重要,新的IEEE 754-2008浮点运算标准也添加了十进制算术运算规范。该文采用目前最佳的条件推测性算法设计十进制加法电路,给出了基于并行前缀/进位选择结构的条件推测性十进制加法器的设计过程,并通过并行前缀单元对十进制进位选择加法器进行优化设计。采用Verilog HDL对32 bit,64 bit和128 bit十进制加法器进行描述并在ModelSim平台上进行了仿真验证,在Nangate Open Cell 45nm标准工艺库下,通过Synopsys公司综合工具Design Compiler进行了综合。与现有的条件推测性十进制加法器相比较,综合结果显示该文所提出的十进制加法器可以提升12.3%的速度性能。

  9. Voltage Sensors Monitor Harmful Static

    Science.gov (United States)

    2009-01-01

    A tiny sensor, small enough to be worn on clothing, now monitors voltage changes near sensitive instruments after being created to alert Agency workers to dangerous static buildup near fuel operations and avionics. San Diego s Quasar Federal Systems received a Small Business Innovation Research (SBIR) contract from Kennedy Space Center to develop its remote voltage sensor (RVS), a dime-sized electrometer designed to measure triboelectric changes in the environment. One of the unique qualities of the RVS is that it can detect static at greater distances than previous devices, measuring voltage changes from a few centimeters to a few meters away, due to its much-improved sensitivity.

  10. Low Voltage Power Supply Incorporating Ceramic Transformer

    CERN Document Server

    Imori, M

    2007-01-01

    A low voltage power supply provides the regulated output voltage of 1 V from the supply voltage around 48 V. The low voltage power supply incorporates a ceramic transformer which utilizes piezoelectric effect to convert voltage. The ceramic transformer isolates the secondary from the primary, thus providing the ground isolation between the supply and the output voltages. The ceramic transformer takes the place of the conventional magnetic transformer. The ceramic transformer is constructed from a ceramic bar and does not include any magnetic material. So the low voltage power supply can operate under a magnetic field. The output voltage is stabilized by feedback. A feedback loop consists of an error amplifier, a voltage controlled oscillator and a driver circuit. The amplitude ratio of the transformer has dependence on the frequency, which is utilized to stabilize the output voltage. The low voltage power supply is investigated on the analogy of the high voltage power supply similarly incorporating the cerami...

  11. Modular High Voltage Power Supply

    Energy Technology Data Exchange (ETDEWEB)

    Newell, Matthew R. [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

    2017-05-18

    The goal of this project is to develop a modular high voltage power supply that will meet the needs of safeguards applications and provide a modular plug and play supply for use with standard electronic racks.

  12. Reliability criteria for voltage stability

    Energy Technology Data Exchange (ETDEWEB)

    Taylor, Carson W.; Silverstein, Brian L. [Bonneville Power Administration, Portland, OR (United States)

    1994-12-31

    In face of costs pressures, there is need to allocate scare resources more effectively in order to achieve voltage stability. This naturally leads to development of probabilistic criteria and notions of rick management. In this paper it is presented a discussion about criteria for long term voltage stability limited to the case in which the time frames are topically several minutes. (author) 14 refs., 1 fig.

  13. A Voltage Quality Detection Method

    DEFF Research Database (Denmark)

    Chen, Zhe; Wei, Mu

    2008-01-01

    This paper presents a voltage quality detection method based on a phase-locked loop (PLL) technique. The technique can detect the voltage magnitude and phase angle of each individual phase under both normal and fault power system conditions. The proposed method has the potential to evaluate vario...... power quality disturbances, such as interruptions, sags and imbalances. Simulation studies have been performed. The effectiveness of the proposed method has been demonstrated under the simulated typical power disturbances....

  14. A matter of quantum voltages.

    Science.gov (United States)

    Sellner, Bernhard; Kathmann, Shawn M

    2014-11-14

    Voltages inside matter are relevant to crystallization, materials science, biology, catalysis, and aqueous chemistry. The variation of voltages in matter can be measured by experiment, however, modern supercomputers allow the calculation of accurate quantum voltages with spatial resolutions of bulk systems well beyond what can currently be measured provided a sufficient level of theory is employed. Of particular interest is the Mean Inner Potential (V(o))--the spatial average of these quantum voltages referenced to the vacuum. Here we establish a protocol to reliably evaluate V(o) from quantum calculations. Voltages are very sensitive to the distribution of electrons and provide metrics to understand interactions in condensed phases. In the present study, we find excellent agreement with measurements of V(o) for vitrified water and salt crystals and demonstrate the impact of covalent and ionic bonding as well as intermolecular/atomic interactions. Certain aspects in this regard are highlighted making use of simple model systems/approximations. Furthermore, we predict V(o) as well as the fluctuations of these voltages in aqueous NaCl electrolytes and characterize the changes in their behavior as the resolution increases below the size of atoms.

  15. Study of the Performance of an All-Optical Half-Adder Based on Three-Core Non-Linear Directional Fiber Coupler Under Delayed and Instantaneous Non-Linear Kerr Responses

    Science.gov (United States)

    Menezes, J. W. M.; Fraga, W. B.; Lima, F. T.; Guimarães, G. F.; Ferreira, A. C.; Lyra, M. L.; Sombra, A. S. B.

    2011-06-01

    Recently, much attention has been given to the influence of the relaxation process of the non-linear response, because the usual assumption of instantaneous non-linear response fails for ultra-short pulses, and additional contributions coming from non-linear dispersion and delayed non-linearity have to be taken into account. This article presents a numerical analysis of the symmetric planar and asymmetric planar three-core non-linear directional fiber couplers operating with a soliton pulse, where effects of both delayed and instantaneous non-linear Kerr responses are analyzed for implementation of an all-optical half-adder. To implement this all-optical half-adder, eight configurations were analyzed for the non-linear directional fiber coupler, with two symmetric and six asymmetric configurations. The half-adder is the key building block for many digital processing functions, such as shift register, binary counter, and serial parallel data converters. The optical coupler is an important component for applications in optical-fiber telecommunication systems and all integrated optical circuit because of its very high switching speeds. In this numerical simulation, the symmetric/asymmetric planar presents a structure with three cores in a parallel equidistant arrangement, three logical inputs, and two output energy. To prove the effectiveness of the theoretical model for generation of the all-optical half-adder, the best phase to be applied to the control pulse was sought, and a study was done of the extinction ratio level as a function of the Δ > parameter, the normalized time duration, and the Sum and Carry outputs of the (symmetric planar/asymmetric planar) non-linear directional fiber coupler. In this article, the interest is in transmission characteristics, extinction ratio level, normalized time duration, and pulse evolution along the non-linear directional fiber coupler. To compare the performance of the all-optical half-adders, the figure of merit of the

  16. VOLTAGE COMPENSATION USING ARTIFICIAL NEURAL NETWORK

    African Journals Online (AJOL)

    VOLTAGE COMPENSATION USING ARTIFICIAL NEURAL NETWORK: A CASE STUDY OF RUMUOLA DISTRIBUTION NETWORK. ... The artificial neural networks controller engaged to controlling the dynamic voltage ... Article Metrics.

  17. Piezoelectric particle accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Kemp, Mark A.; Jongewaard, Erik N.; Haase, Andrew A.; Franzi, Matthew

    2017-08-29

    A particle accelerator is provided that includes a piezoelectric accelerator element, where the piezoelectric accelerator element includes a hollow cylindrical shape, and an input transducer, where the input transducer is disposed to provide an input signal to the piezoelectric accelerator element, where the input signal induces a mechanical excitation of the piezoelectric accelerator element, where the mechanical excitation is capable of generating a piezoelectric electric field proximal to an axis of the cylindrical shape, where the piezoelectric accelerator is configured to accelerate a charged particle longitudinally along the axis of the cylindrical shape according to the piezoelectric electric field.

  18. Acceleration without Horizons

    CERN Document Server

    Doria, Alaric

    2015-01-01

    We derive the metric of an accelerating observer moving with non-constant proper acceleration in flat spacetime. With the exception of a limiting case representing a Rindler observer, there are no horizons. In our solution, observers can accelerate to any desired terminal speed $v_{\\infty} < c$. The motion of the accelerating observer is completely determined by the distance of closest approach and terminal velocity or, equivalently, by an acceleration parameter and terminal velocity.

  19. Fast Differential Adder

    Science.gov (United States)

    Arditti, Mort A.; Silva, Rosemary

    1993-01-01

    Differential adding circuit (or, equivalently, subtracting circuit) faster and consumes less power because it contains only one differential amplifier. Suitable for use in high-frequency-switching, high power-regulating circuit.

  20. Accelerating flight: Edge with arbitrary acceleration

    CSIR Research Space (South Africa)

    Gledhill, Irvy MA

    2011-11-01

    Full Text Available ? temporal scales ? Euler ? convection ? Reynolds ? translational viscous ? Ekman ? rotational viscous ? Translational acceleration ? related to g ? Rotational accleration ? Rossby ? Coriolis ? Centrifugal ? Gravitational ? CSIR 2009...

  1. Operation of the accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Pardo, R.C.; Batzka, B.; Billquist, P.J. [and others

    1995-08-01

    Fiscal Year 1994 was the first year of seven-day operation since ATLAS became a national user facility in 1985. ATLAS made the most of the opportunity this year by providing 5200 hours of beam on-target to the research program. A record number of 60 experiments were completed and the {open_quotes}facility reliability{close_quotes} remained near the 90% level. Seven-day operation was made possible with the addition to the staff of two operator positions providing single-operator coverage during the weekend period. The normally scheduled coverage was augmented by an on-call list of system experts who respond to emergencies with phone-in advice and return to the Laboratory when necessary. This staffing approach continues but we rearranged our staffing patterns so that we now have one cryogenics engineer working a shift pattern which includes 8-hour daily coverage during the weekend. ATLAS provided a beam mix to users consisting of 26 different isotopic species, 23% of which were for A>100 in FY 1994. Approximately 60% of the beam time was provided by the Positive Ion Injector, slightly less than the usage rate of FY 1993. Experiments using uranium or lead beams accounted for 16.4% of the total beam time. The ECR ion source and high-voltage platform functioned well throughout the year. A new technique for solid material production in the source was developed which uses a sputtering process wherein the sample of material placed near the plasma chamber wall is biased negatively. Plasma ions are accelerated into the sample and material is sputtered from the surface into the plasma. This technique is now used routinely for many elements. Runs of calcium, germanium, nickel, lead, tellurium, and uranium were carried out with this technique.

  2. Influence of pulse line switch inductance on output characteristics of high-current nanosecond accelerators

    Science.gov (United States)

    Mashchenko, A. I.; Vintizenko, I. I.

    2016-06-01

    Various types of high-current nanosecond accelerators are simulated numerically using an equivalent circuit representation. The influence of pulse forming line switch inductance on the amplitude and waveform of output voltage and current pulses is analyzed.

  3. Electrode voltage fall and total voltage of a transient arc

    Science.gov (United States)

    Valensi, F.; Ratovoson, L.; Razafinimanana, M.; Masquère, M.; Freton, P.; Gleizes, A.

    2016-06-01

    This paper deals with an experimental study of the components of a transient arc total voltage with duration of a few tens of ms and a current peak close to 1000 A. The cathode tip is made of graphite whereas the flat anode is made either of copper or of graphite; the electrodes gap is a few mm. The analysis of the electrical parameters is supported and validated by fast imaging and by two models: the first one is a 2D physical model of the arc allowing to calculate both the plasma temperature field and the arc voltage; the second model is able to estimate the transient heating of the graphite electrode. The main aim of the study was to detect the possible change of the cathode voltage fall (CVF) during the first instants of the arc. Indeed it is expected that during the first ms the graphite cathode is rather cool and the main mechanism of the electron emission should be the field effect emission, whereas after several tens of ms the cathode is strongly heated and thermionic emission should be predominant. We have observed some change in the apparent CVF but we have shown that this apparent change can be attributed to the variation of the solid cathode resistance. On the other hand, the possible change of CVF corresponding to the transition between a ‘cold’ and a ‘hot’ cathode should be weak and could not be characterized considering our measurement uncertainty of about 2 V. The arc column voltage (ACV) was estimated by subtracting the electrode voltage fall from the total arc voltage. The experimental transient evolution of the ACV is in very good agreement with the theoretical variation predicted by the model, showing the good ability of the model to study this kind of transient arc.

  4. "Super-acceleration" of ions in a stationary plasma discharge

    Science.gov (United States)

    Bardakov, Vladimir; Ivanov, Sergey; Kazantsev, Alexander; Strokin, Nikolay; Stupin, Aleksey

    2016-10-01

    We report on the detection of the acceleration effect of the bulk of ions in a stationary plasma E × B discharge to energies exceeding considerably the value equivalent to the discharge voltage. We determined the conditions necessary for the generation of high-energy ions, and ascertained the influence exerted on the value of the ion energies by pressure (flow rate) and the kind of plasma-producing gas, and by the value of discharge current. The possible acceleration mechanism is suggested.

  5. Unbalanced Voltage Compensation in Low Voltage Residential AC Grids

    DEFF Research Database (Denmark)

    Trintis, Ionut; Douglass, Philip; Munk-Nielsen, Stig

    2016-01-01

    This paper describes the design and test of a control algorithm for active front-end rectifiers that draw power from a residential AC grid to feed heat pump loads. The control algorithm is able to control the phase to neutral or phase to phase RMS voltages at the point of common coupling....... The voltage control was evaluated with either active or reactive independent phase load current control. The control performance in field operation in a residential grid situated in Bornholm, Denmark was investigated for different use cases....

  6. Protection of Accelerator Hardware: RF systems

    CERN Document Server

    Kim, S-H

    2016-01-01

    The radio-frequency (RF) system is the key element that generates electric fields for beam acceleration. To keep the system reliable, a highly sophisticated protection scheme is required, which also should be designed to ensure a good balance between beam availability and machine safety. Since RF systems are complex, incorporating high-voltage and high-power equipment, a good portion of machine downtime typically comes from RF systems. Equipment and component damage in RF systems results in long and expensive repairs. Protection of RF system hardware is one of the oldest machine protection concepts, dealing with the protection of individual high-power RF equipment from breakdowns. As beam power increases in modern accelerators, the protection of accelerating structures from beam-induced faults also becomes a critical aspect of protection schemes. In this article, an overview of the RF system is given, and selected topics of failure mechanisms and examples of protection requirements are introduced.

  7. Reliability of High-Voltage Tantalum Capacitors. Parts 3 and 4)

    Science.gov (United States)

    Teverovsky, Alexander

    2010-01-01

    Weibull grading test is a powerful technique that allows selection and reliability rating of solid tantalum capacitors for military and space applications. However, inaccuracies in the existing method and non-adequate acceleration factors can result in significant, up to three orders of magnitude, errors in the calculated failure rate of capacitors. This paper analyzes deficiencies of the existing technique and recommends more accurate method of calculations. A physical model presenting failures of tantalum capacitors as time-dependent-dielectric-breakdown is used to determine voltage and temperature acceleration factors and select adequate Weibull grading test conditions. This model is verified by highly accelerated life testing (HALT) at different temperature and voltage conditions for three types of solid chip tantalum capacitors. It is shown that parameters of the model and acceleration factors can be calculated using a general log-linear relationship for the characteristic life with two stress levels.

  8. Development of a New Cascade Voltage-Doubler for Voltage Multiplication

    OpenAIRE

    Arash Toudeshki; Norman Mariun; Hashim Hizam; Noor Izzri Abdul Wahab

    2014-01-01

    For more than eight decades, cascade voltage-doubler circuits are used as a method to produce DC output voltage higher than the input voltage. In this paper, the topological developments of cascade voltage-doublers are reviewed. A new circuit configuration for cascade voltage-doubler is presented. This circuit can produce a higher value of the DC output voltage and better output quality compared to the conventional cascade voltage-doubler circuits, with the same number of stages.

  9. Low-Energy Real-Time OS Using Voltage Scheduling Algorithm for Variable Voltage Processors

    OpenAIRE

    Okuma, Takanori; Yasuura, Hiroto

    2001-01-01

    This paper presents a real-time OS based on $ mu $ITRON using proposed voltage scheduling algorithm for variable voltage processors which can vary supply voltage dynamically. The proposed voltage scheduling algorithms assign voltage level for each task dynamically in order to minimize energy consumption under timing constraints. Using the presented real-time OS, running tasks with low supply voltage leads to drastic energy reduction. In addition, the presented voltage scheduling algorithm is ...

  10. Simple buck/boost voltage regulator

    Science.gov (United States)

    Paulkovich, J.; Rodriguez, G. E.

    1980-01-01

    Circuit corrects low or high supply voltage, produces regulated output voltage. Circuit has fewer components because inductory/transformer combination and pulse-width modulator serve double duty. Regulator handles input voltage variation from as low as one half output voltage to as high as input transistor rating. Solar arrays, fuel cells, and thermionic generators might use this regulator.

  11. 30 CFR 18.47 - Voltage limitation.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Voltage limitation. 18.47 Section 18.47 Mineral... § 18.47 Voltage limitation. (a) A tool or switch held in the operator's hand or supported against his... particular voltage(s) are provided in the design and construction of the equipment, its wiring,...

  12. 基于电路三要素理论的三值绝热加法器设计%Design of Ternary Adiabatic Adder Based on Theory of Three Essential Circuit Elements

    Institute of Scientific and Technical Information of China (English)

    汪鹏君; 李昆鹏

    2011-01-01

    通过对加法器和绝热电路工作原理及结构的研究,本文提出一种三值绝热加法器设计方案.该方案首先以电路三要素理论为指导,推导出一位三值绝热全加器的元件级函数式,并利用自举的NMOS管实现相应的电路结构,完成对电路的能量注入和恢复.然后在此基础上,进一步得到四位三值绝热加法器.最后 PSPICE模拟验证所设计的电路具有正确的逻辑功能和明显的低功耗特性.%Through the research on working principle and structure of adder and adiabatic circuits, a design of ternary adiabatic adder was presented in this paper.First,the component-level function expressions of one bit ternary adiabatic full-adder were derived under the guidance of the theory of three essential circuit elements, and the corresponding circuit structure were realizing by using the bootstapped NMOS FET, which enable the circuit to accomplish the energy injection and recovery. Then, the four bits ternary adiabatic adder was realized based on this circuit. Finally, PSPICE simulation results indicate that the proposed circuit has correct logic function and the obvious low power characteristics.

  13. Cavity Voltage Phase Modulation MD

    CERN Document Server

    Mastoridis, Themistoklis; Molendijk, John; Timko, Helga; CERN. Geneva. ATS Department

    2016-01-01

    The LHC RF/LLRF system is currently configured for extremely stable RF voltage to minimize transient beam loading effects. The present scheme cannot be extended beyond nominal beam current since the demanded power would exceed the peak klystron power and lead to saturation. A new scheme has therefore been proposed: for beam currents above nominal (and possibly earlier), the cavity phase modulation by the beam will not be corrected (transient beam loading), but the strong RF feedback and One-Turn Delay feedback will still be active for loop and beam stability in physics. To achieve this, the voltage set point will be adapted for each bunch. The goal of this MD was to test a new algorithm that would adjust the voltage set point to achieve the cavity phase modulation that would minimize klystron forward power.

  14. Portable High Voltage Impulse Generator

    Directory of Open Access Journals (Sweden)

    S. Gómez

    2011-07-01

    Full Text Available This paper presents a portable high voltage impulse generator which was designed and built with insulation up to 20 kV. This design was based on previous work in which simulation software for standard waves was developed. Commercial components and low-cost components were used in this work; however, these particular elements are not generally used for high voltage applications. The impulse generators used in industry and laboratories are usually expensive; they are built to withstand extra high voltage and they are big, making them impossible to transport. The proposed generator is portable, thereby allowing tests to be made on devices that cannot be moved from their location. The results obtained with the proposed impulse generator were satisfactory in terms of time and waveforms compared to other commercial impulse generators and the standard impulse wave simulator.

  15. 2014 CERN Accelerator Schools: Plasma Wake Acceleration

    CERN Multimedia

    2014-01-01

    A specialised school on Plasma Wake Acceleration will be held at CERN, Switzerland from 23-29 November, 2014.   This course will be of interest to staff and students in accelerator laboratories, university departments and companies working in or having an interest in the field of new acceleration techniques. Following introductory lectures on plasma and laser physics, the course will cover the different components of a plasma wake accelerator and plasma beam systems. An overview of the experimental studies, diagnostic tools and state of the art wake acceleration facilities, both present and planned, will complement the theoretical part. Topical seminars and a visit of CERN will complete the programme. Further information can be found at: http://cas.web.cern.ch/cas/PlasmaWake2014/CERN-advert.html http://indico.cern.ch/event/285444/

  16. Hybrid-PIC Modeling of a High-Voltage, High-Specific-Impulse Hall Thruster

    Science.gov (United States)

    Smith, Brandon D.; Boyd, Iain D.; Kamhawi, Hani; Huang, Wensheng

    2013-01-01

    The primary life-limiting mechanism of Hall thrusters is the sputter erosion of the discharge channel walls by high-energy propellant ions. Because of the difficulty involved in characterizing this erosion experimentally, many past efforts have focused on numerical modeling to predict erosion rates and thruster lifespan, but those analyses were limited to Hall thrusters operating in the 200-400V discharge voltage range. Thrusters operating at higher discharge voltages (V(sub d) >= 500 V) present an erosion environment that may differ greatly from that of the lower-voltage thrusters modeled in the past. In this work, HPHall, a well-established hybrid-PIC code, is used to simulate NASA's High-Voltage Hall Accelerator (HiVHAc) at discharge voltages of 300, 400, and 500V as a first step towards modeling the discharge channel erosion. It is found that the model accurately predicts the thruster performance at all operating conditions to within 6%. The model predicts a normalized plasma potential profile that is consistent between all three operating points, with the acceleration zone appearing in the same approximate location. The expected trend of increasing electron temperature with increasing discharge voltage is observed. An analysis of the discharge current oscillations shows that the model predicts oscillations that are much greater in amplitude than those measured experimentally at all operating points, suggesting that the differences in oscillation amplitude are not strongly associated with discharge voltage.

  17. A low voltage CMOS low drop-out voltage regulator

    Science.gov (United States)

    Bakr, Salma Ali; Abbasi, Tanvir Ahmad; Abbasi, Mohammas Suhaib; Aldessouky, Mohamed Samir; Abbasi, Mohammad Usaid

    2009-05-01

    A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2μs. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20μA. The total power consumption of this LDO (excluding bandgap reference) is only 80μW.

  18. Implementation of Dynamic Voltage Restorer for Mitigation of Voltage Sag

    Directory of Open Access Journals (Sweden)

    K.Vinod Kumar

    2013-07-01

    Full Text Available Power quality is one of major concerns in the present. It has become important, especially with the introduction of sophisticated devices, whose performance is very sensitive to the quality of power supply. The dynamic voltage restorer (DVR is one of the modern devices used in distribution systems to improve the power quality. In this paper, emergency control in distribution systems is discussed by using the proposed multifunctional DVR control strategy.Also, themultiloop controller using the Posicast and P+Resonant controllers is proposed in order to improve the transient response and eliminate the steady state error in DVR response,respectively.The proposed process is applied to some riots in load voltage effected by induction motors starting, and a three-phase short circuit fault. The three-phase short circuits, and the large induction motors are suddenly started then voltage sags areoccurred.The innovation here is that by using the Multifunctional Dynamic Voltage Restorer, improve the power quality in distribution side. Simulation results show the capability of the DVR to control the emergency conditions of the distribution systems by using MATLAB/Simulink software.

  19. The high voltage homopolar generator

    Science.gov (United States)

    Price, J. H.; Gully, J. H.; Driga, M. D.

    1986-11-01

    System and component design features of proposed high voltage homopolar generator (HVHPG) are described. The system is to have an open circuit voltage of 500 V, a peak output current of 500 kA, 3.25 MJ of stored inertial energy and possess an average magnetic-flux density of 5 T. Stator assembly components are discussed, including the stator, mount structure, hydrostatic bearings, main and motoring brushgears and rotor. Planned operational procedures such as monitoring the rotor to full speed and operation with a superconducting field coil are delineated.

  20. Design and implementation of 24-bit parallel prefix adder based on Sklansky structure%基于Sklansky结构的24位并行前缀加法器的设计与实现

    Institute of Scientific and Technical Information of China (English)

    姚若河; 马廷俊; 苏少妍

    2015-01-01

    针对串行进位加法器存在的延时问题,采用一种基于Sklansky结构的并行前缀加法器,通过对并行前缀加法器各个模块进行优化,设计实现了一个24位并行前缀加法器.通过与24位串行进位加法器进行延时比较,结果表明,Sklansky并行前缀结构的加法器,能有效提高运算速度.%Aiming at the delay problem of serial carry adder(SCA),a parallel prefix adder(PPA)based on Sklansky was adopted. A 24-bit PPA was designed and realized on the basis of optimizing the various modules of PPA. By comparing the delay of 24-bit PPA with that of 24-bit SCA,the results show that the parallel prefix adder based on Sklansky can increase the com-puting speed effectively.

  1. 基于改进五输入择多门的QCA全加器设计及应用%The Design and Application of QCA Full Adder Based on Improved Five-Input Majority Gate

    Institute of Scientific and Technical Information of China (English)

    刘帅; 解光军; 张永强; 项云龙; 吕洪君

    2015-01-01

    Quantum-dot cellular automata (QCA) is an emerging nanotechnology .A full adder based on improved five-input majority gate is proposed .The full adder keeps correct logic function and dominates the previous results .Then it is applied to imple-ment adder and multiplier .Results illustrate that they improve significantly in some performance .%量子元胞自动机(Quantum-dot cellular automata ,QCA )是一种新兴的纳米技术。本文基于改进的五输入择多门,设计出一个全加器,在保持正确逻辑功能的基础上较以往的全加器有一定优势。应用该全加器设计加法器和乘法器,结果表明在某些性能上有显著提高。

  2. Resilient architecture design for voltage variation

    CERN Document Server

    Reddi, Vijay Janapa

    2013-01-01

    Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe

  3. Stator insulation systems for medium voltage PWM drives fed motors

    Energy Technology Data Exchange (ETDEWEB)

    Gao, G.; Chen, W. [TECO-Westinghouse Motor Co., Round Rock, TX (United States)

    2005-07-01

    Adjustable speed drives (ASD) are commonly used in power electronics and control systems. It is estimated that more than 15 per cent of medium voltage motors are currently fed by such drives worldwide. A research project was conducted to examine the influence of medium voltage pulse width modulated (PWM) ASD on motor stator insulation systems. The findings, based on accelerated laboratory tests, have helped designers to improve the capabilities of the insulation system used for ASD-fed motors. Repetitive, high magnitude voltage spikes with fast rise time create significant stress on insulation systems. Gradual deterioration and premature failure of the motor insulation can result from surge voltages which generate surface discharges between phase windings/end windings, or partial discharges between stator turns. However, there is no industrial standard to evaluate motor insulation life under ASD-cable-motor conditions. Several material manufacturers have developed their own version of corona resistant material. However, the insulation life of ASD-fed motors does not depend solely on the raw materials. Rather, it depends on the complete insulation system, including the stator manufacturing process. In order to address this problem, TECO-Westinghouse Motor Company has developed special design criteria and manufacturing practices in order to reduce winding insulation temperature and to compensate for the additional heat generated by high frequency contents in the PWM voltage waveform. A patent pending new cooling system should reduce winding temperature by 15 to 20 degrees C. This paper presented design considerations for turn insulation, groundwall insulation, and a voltage stress grading system. A new thermal class H insulation system was also described. 6 refs., 2 tabs., 5 figs.

  4. High Energy Particle Accelerators

    CERN Multimedia

    Audio Productions, Inc, New York

    1960-01-01

    Film about the different particle accelerators in the US. Nuclear research in the US has developed into a broad and well-balanced program.Tour of accelerator installations, accelerator development work now in progress and a number of typical experiments with high energy particles. Brookhaven, Cosmotron. Univ. Calif. Berkeley, Bevatron. Anti-proton experiment. Negative k meson experiment. Bubble chambers. A section on an electron accelerator. Projection of new accelerators. Princeton/Penn. build proton synchrotron. Argonne National Lab. Brookhaven, PS construction. Cambridge Electron Accelerator; Harvard/MIT. SLAC studying a linear accelerator. Other research at Madison, Wisconsin, Fixed Field Alternate Gradient Focusing. (FFAG) Oakridge, Tenn., cyclotron. Two-beam machine. Comments : Interesting overview of high energy particle accelerators installations in the US in these early years. .

  5. Improved plasma accelerator

    Science.gov (United States)

    Cheng, D. Y.

    1971-01-01

    Converging, coaxial accelerator electrode configuration operates in vacuum as plasma gun. Plasma forms by periodic injections of high pressure gas that is ionized by electrical discharges. Deflagration mode of discharge provides acceleration, and converging contours of plasma gun provide focusing.

  6. Accelerator Technology Division

    Science.gov (United States)

    1992-04-01

    In fiscal year (FY) 1991, the Accelerator Technology (AT) division continued fulfilling its mission to pursue accelerator science and technology and to develop new accelerator concepts for application to research, defense, energy, industry, and other areas of national interest. This report discusses the following programs: The Ground Test Accelerator Program; APLE Free-Electron Laser Program; Accelerator Transmutation of Waste; JAERI, OMEGA Project, and Intense Neutron Source for Materials Testing; Advanced Free-Electron Laser Initiative; Superconducting Super Collider; The High-Power Microwave Program; (Phi) Factory Collaboration; Neutral Particle Beam Power System Highlights; Accelerator Physics and Special Projects; Magnetic Optics and Beam Diagnostics; Accelerator Design and Engineering; Radio-Frequency Technology; Free-Electron Laser Technology; Accelerator Controls and Automation; Very High-Power Microwave Sources and Effects; and GTA Installation, Commissioning, and Operations.

  7. Accelerators, Colliders, and Snakes

    Science.gov (United States)

    Courant, Ernest D.

    2003-12-01

    The author traces his involvement in the evolution of particle accelerators over the past 50 years. He participated in building the first billion-volt accelerator, the Brookhaven Cosmotron, which led to the introduction of the "strong-focusing" method that has in turn led to the very large accelerators and colliders of the present day. The problems of acceleration of spin-polarized protons are also addressed, with discussions of depolarizing resonances and "Siberian snakes" as a technique for mitigating these resonances.

  8. Low Beam Voltage, 10 MW, L-Band Cluster Klystron

    Energy Technology Data Exchange (ETDEWEB)

    Teryaev, V.; /Novosibirsk, IYF; Yakovlev, V.P.; /Fermilab; Kazakov, S.; /KEK, Tsukuba; Hirshfield, J.L.; /Yale U. /Omega-P, New Haven

    2009-05-01

    Conceptual design of a multi-beam klystron (MBK) for possible ILC and Project X applications is presented. The chief distinction between this MBK design and existing 10-MW MBK's is the low operating voltage of 60 kV. There are at least four compelling reasons that justify development at this time of a low-voltage MBK, namely (1) no pulse transformer; (2) no oil tank for high-voltage components and for the tube socket; (3) no high-voltage cables; and (4) modulator would be a compact 60-kV IGBT switching circuit. The proposed klystron consists of four clusters containing six beams each. The tube has common input and output cavities for all 24 beams, and individual gain cavities for each cluster. A closely related optional configuration, also for a 10 MW tube, would involve four totally independent cavity clusters with four independent input cavities and four 2.5 MW output ports, all within a common magnetic circuit. This option has appeal because the output waveguides would not require a controlled atmosphere, and because it would be easier to achieve phase and amplitude stability as required in individual SC accelerator cavities.

  9. VOLTAGE REGULATORS OF SYNCHRONOUS GENERATORS

    Directory of Open Access Journals (Sweden)

    Grigorash O. V.

    2015-06-01

    Full Text Available Synchronous generators are the primary source of electrical power autonomous electrosupply systems, including backup systems. They are also used in a structure of rotating electricity converters and are widely used in renewable energy as part of wind power plants of small, mini and micro hydroelectric plants. Increasing the speed and the accuracy of the system of the voltage regulation of synchronous generators is possible due to the development of combined systems containing more stabilizers. The article illustrates the functional schemes of circuit voltage stabilizers and frequency synchronous generators (with electromagnetic excitation and permanent magnet excitation and describes the features of their work, including two and three-aggregate rotating converters of electricity used in uninterruptible power supply systems. To improve the technical characteristics of the system of stabilization we have proposed functional solutions for stabilizers of synchronous generators made on the base of direct frequency converters and using a transformer with a rotating magnetic field. To improve the reliability of and to improve the operational characteristics of the autonomous independent sources of electricity we suggest creating the main functional blocks and the elements of the stabilization system in a modular way. The functional circuit solutions of voltage regulators of synchronous generators and the characteristics of their work considered in the article, are able to improve the efficiency of pre-design work in the development of new technical solutions for stabilizing the voltage and the frequency in synchronous generators of electrosupply autonomous systems

  10. Frequency-controlled voltage regulator

    Science.gov (United States)

    Mclyman, W. T.

    1980-01-01

    Converting input ac to higher frequency reduce size and weight and makes possible unique kind of regulation. Since conversion frequency is above range of human hearing, supply generated on audible noise. It also exploits highfrequency conversion features to regulate its output voltage in novel way. Circuit is inherently short-circuit proof.

  11. The CERN Accelerator School

    CERN Multimedia

    2016-01-01

    Introduction to accelerator physics The CERN Accelerator School: Introduction to Accelerator Physics, which should have taken place in Istanbul, Turkey, later this year has now been relocated to Budapest, Hungary.  Further details regarding the new hotel and dates will be made available as soon as possible on a new Indico site at the end of May.

  12. Accelerators and Dinosaurs

    CERN Multimedia

    Turner, Michael Stanley

    2003-01-01

    Using naturally occuring particles on which to research might have made accelerators become extinct. But in fact, results from astrophysics have made accelerator physics even more important. Not only are accelerators used in hospitals but they are also being used to understand nature's inner workings by searching for Higgs bosons, CP violation, neutrino mass and dark matter (2 pages)

  13. Far field acceleration

    Energy Technology Data Exchange (ETDEWEB)

    Fernow, R.C.

    1995-07-01

    Far fields are propagating electromagnetic waves far from their source, boundary surfaces, and free charges. The general principles governing the acceleration of charged particles by far fields are reviewed. A survey of proposed field configurations is given. The two most important schemes, Inverse Cerenkov acceleration and Inverse free electron laser acceleration, are discussed in detail.

  14. Acceleration: It's Elementary

    Science.gov (United States)

    Willis, Mariam

    2012-01-01

    Acceleration is one tool for providing high-ability students the opportunity to learn something new every day. Some people talk about acceleration as taking a student out of step. In actuality, what one is doing is putting a student in step with the right curriculum. Whole-grade acceleration, also called grade-skipping, usually happens between…

  15. Performance Theory of Diagonal Conducting Wall MHD Accelerators

    Science.gov (United States)

    Litchford, R. J.

    2003-01-01

    The theoretical performance of diagonal conducting wall crossed field accelerators is examined on the basis of an infinite segmentation assumption using a cross-plane averaged generalized Ohm's law for a partially ionized gas, including ion slip. The desired accelerator performance relationships are derived from the cross-plane averaged Ohm's law by imposing appropriate configuration and loading constraints. A current dependent effective voltage drop model is also incorporated to account for cold-wall boundary layer effects including gasdynamic variations, discharge constriction, and electrode falls. Definition of dimensionless electric fields and current densities lead to the construction of graphical performance diagrams, which further illuminate the rudimentary behavior of crossed field accelerator operation.

  16. Voltage-gated Proton Channels

    Science.gov (United States)

    DeCoursey, Thomas E.

    2014-01-01

    Voltage-gated proton channels, HV1, have vaulted from the realm of the esoteric into the forefront of a central question facing ion channel biophysicists, namely the mechanism by which voltage-dependent gating occurs. This transformation is the result of several factors. Identification of the gene in 2006 revealed that proton channels are homologues of the voltage-sensing domain of most other voltage-gated ion channels. Unique, or at least eccentric, properties of proton channels include dimeric architecture with dual conduction pathways, perfect proton selectivity, a single-channel conductance ~103 smaller than most ion channels, voltage-dependent gating that is strongly modulated by the pH gradient, ΔpH, and potent inhibition by Zn2+ (in many species) but an absence of other potent inhibitors. The recent identification of HV1 in three unicellular marine plankton species has dramatically expanded the phylogenetic family tree. Interest in proton channels in their own right has increased as important physiological roles have been identified in many cells. Proton channels trigger the bioluminescent flash of dinoflagellates, facilitate calcification by coccolithophores, regulate pH-dependent processes in eggs and sperm during fertilization, secrete acid to control the pH of airway fluids, facilitate histamine secretion by basophils, and play a signaling role in facilitating B-cell receptor mediated responses in B lymphocytes. The most elaborate and best-established functions occur in phagocytes, where proton channels optimize the activity of NADPH oxidase, an important producer of reactive oxygen species. Proton efflux mediated by HV1 balances the charge translocated across the membrane by electrons through NADPH oxidase, minimizes changes in cytoplasmic and phagosomal pH, limits osmotic swelling of the phagosome, and provides substrate H+ for the production of H2O2 and HOCl, reactive oxygen species crucial to killing pathogens. PMID:23798303

  17. Ion accelerator system mounting design and operating characteristics for a 5 kW 30-cm xenon ion engine

    Science.gov (United States)

    Aston, Graeme; Brophy, John R.

    1987-01-01

    Results from a series of experiments to determine the effect of accelerator grid mount geometry on the performance of the J-series ion optics assembly are described. Three mounting schemes, two flexible and one rigid, are compared for their relative ion extraction capability over a range of total accelerating voltages. The largest ion beam current, for the maximum total voltage investigated, is shown to occur using one of the flexible grid mounting geometries. However, at lower total voltages and reduced engine input power levels, the original rigid J-series ion optics accelerator grid mounts result in marginally better grid system performance at the same cold interelectrode gap.

  18. The Accelerator Reliability Forum

    CERN Document Server

    Lüdeke, Andreas; Giachino, R

    2014-01-01

    A high reliability is a very important goal for most particle accelerators. The biennial Accelerator Reliability Workshop covers topics related to the design and operation of particle accelerators with a high reliability. In order to optimize the over-all reliability of an accelerator one needs to gather information on the reliability of many different subsystems. While a biennial workshop can serve as a platform for the exchange of such information, the authors aimed to provide a further channel to allow for a more timely communication: the Particle Accelerator Reliability Forum [1]. This contribution will describe the forum and advertise it’s usage in the community.

  19. Industrial Application of Accelerators

    CERN Document Server

    CERN. Geneva

    2017-01-01

    At CERN, we are very familiar with large, high energy particle accelerators. However, in the world outside CERN, there are more than 35000 accelerators which are used for applications ranging from treating cancer, through making better electronics to removing harmful micro-organisms from food and water. These are responsible for around $0.5T of commerce each year. Almost all are less than 20 MeV and most use accelerator types that are somewhat different from what is at CERN. These lectures will describe some of the most common applications, some of the newer applications in development and the accelerator technology used for them. It will also show examples of where technology developed for particle physics is now being studied for these applications. Rob Edgecock is a Professor of Accelerator Science, with a particular interest in the medical applications of accelerators. He works jointly for the STFC Rutherford Appleton Laboratory and the International Institute for Accelerator Applications at the Univer...

  20. Industrial Application of Accelerators

    CERN Document Server

    CERN. Geneva

    2017-01-01

    At CERN, we are very familiar with large, high energy particle accelerators. However, in the world outside CERN, there are more than 35000 accelerators which are used for applications ranging from treating cancer, through making better electronics to removing harmful micro-organisms from food and water. These are responsible for around $0.5T of commerce each year. Almost all are less than 20 MeV and most use accelerator types that are somewhat different from what is at CERN. These lectures will describe some of the most common applications, some of the newer applications in development and the accelerator technology used for them. It will also show examples of where technology developed for particle physics is now being studied for these applications. Rob Edgecock is a Professor of Accelerator Science, with a particular interest in the medical applications of accelerators. He works jointly for the STFC Rutherford Appleton Laboratory and the International Institute for Accelerator Applications at the Uni...