Advanced symbolic analysis for VLSI systems methods and applications

CERN Document Server

Shi, Guoyong; Tlelo Cuautle, Esteban

2014-01-01

This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

Design of two easily-testable VLSI array multipliers

Energy Technology Data Exchange (ETDEWEB)

Ferguson, J.; Shen, J.P.

1983-01-01

Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

Using Software Technology to Specify Abstract Interfaces in VLSI Design.

Science.gov (United States)

1985-01-01

with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

Wavelength-encoded OCDMA system using opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Wavelength-encoded OCDMA system using opto-VLSI processors

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

VLSI Design of Trusted Virtual Sensors

Directory of Open Access Journals (Sweden)

Macarena C. Martínez-Rodríguez

2018-01-01

Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

VLSI Design of Trusted Virtual Sensors.

Science.gov (United States)

Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

2018-01-25

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

National Research Council Canada - National Science Library

Horiuchi, Timothy K; Krishnaprasad, P. S

2007-01-01

.... This includes multiple efforts related to a VLSI-based echolocation system being developed in one of our laboratories from algorithm development, bat flight data analysis, to VLSI circuit design...

VLSI top-down design based on the separation of hierarchies

NARCIS (Netherlands)

Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

1986-01-01

Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

Directory of Open Access Journals (Sweden)

Fazal NOORBASHA

2012-08-01

Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

CERN Document Server

Williams, John

2008-01-01

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Directory of Open Access Journals (Sweden)

Urard Pascal

2006-01-01

Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Directory of Open Access Journals (Sweden)

Rachmad Vidya Wicaksana Putra

2016-06-01

Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

2008-01-21

In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

VLSI architecture and design for the Fermat Number Transform implementation

Energy Technology Data Exchange (ETDEWEB)

Pajayakrit, A.

1987-01-01

A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

A second generation 50 Mbps VLSI level zero processing system prototype

Science.gov (United States)

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

VLSI signal processing technology

CERN Document Server

Swartzlander, Earl

1994-01-01

This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

The VLSI handbook

CERN Document Server

Chen, Wai-Kai

2007-01-01

Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

Design of a VLSI Decoder for Partially Structured LDPC Codes

Directory of Open Access Journals (Sweden)

Fabrizio Vacca

2008-01-01

of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

VLSI in medicine

CERN Document Server

Einspruch, Norman G

1989-01-01

VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

CERN Document Server

Shirur, Yasha; Prasad, Rekha

2013-01-01

This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

VLSI electronics microstructure science

CERN Document Server

1982-01-01

VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

Directory of Open Access Journals (Sweden)

Jen-Chih Kuo

2003-12-01

Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

An analog VLSI real time optical character recognition system based on a neural architecture

International Nuclear Information System (INIS)

Bo, G.; Caviglia, D.; Valle, M.

1999-01-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

An analog VLSI real time optical character recognition system based on a neural architecture

Energy Technology Data Exchange (ETDEWEB)

Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

1999-03-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

High performance VLSI telemetry data systems

Science.gov (United States)

Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

1990-01-01

NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

VLSI implementations for image communications

CERN Document Server

Pirsch, P

1993-01-01

The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-06-01

Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

Science.gov (United States)

Brouwer, Randall Jay

1991-01-01

The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

VLSI 'smart' I/O module development

Science.gov (United States)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

Science.gov (United States)

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

Hybrid VLSI/QCA Architecture for Computing FFTs

Science.gov (United States)

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam

2011-12-01

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

Plasma processing for VLSI

CERN Document Server

Einspruch, Norman G

1984-01-01

VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

Energy Technology Data Exchange (ETDEWEB)

Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

National Research Council Canada - National Science Library

Altmeyer, Ronald

2002-01-01

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

Science.gov (United States)

Shi, Cong; Luo, Gang

2018-04-01

This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

Synthesis of on-chip control circuits for mVLSI biochips

DEFF Research Database (Denmark)

Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

2017-01-01

them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

Science.gov (United States)

2010-10-01

spatial navigation in mammals. We have designed, fabricated, and are now testing a neuromorphic VLSI chip that implements a spike-based, attractor...Control Laws and Neuromorphic VLSI 5a. CONTRACT NUMBER 070402-7705 5b. GRANT NUMBER FA9550-07-1-0446 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S...implementations (custom Neuromorphic VLSI and robotics) we will apply important practical constraints that can lead to deeper insight into how and why efficient

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

Science.gov (United States)

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Directory of Open Access Journals (Sweden)

Sergio Saponara

2004-09-01

Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

VLSI architectures for modern error-correcting codes

CERN Document Server

Zhang, Xinmiao

2015-01-01

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

A VLSI image processor via pseudo-mersenne transforms

International Nuclear Information System (INIS)

Sei, W.J.; Jagadeesh, J.M.

1986-01-01

The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Directory of Open Access Journals (Sweden)

HOO, C.-S.

2013-02-01

Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

Directory of Open Access Journals (Sweden)

Horiuchi Timothy

2003-01-01

Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

Science.gov (United States)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

Science.gov (United States)

Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

1991-01-01

A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

CERN Document Server

Hu, Kai; Ho, Tsung-Yi

2017-01-01

This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

CERN Document Server

Williams, John Michael

2014-01-01

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

Lithography for VLSI

CERN Document Server

Einspruch, Norman G

1987-01-01

VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

Trace-based post-silicon validation for VLSI circuits

CERN Document Server

Liu, Xiao

2014-01-01

This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

Surface and interface effects in VLSI

CERN Document Server

Einspruch, Norman G

1985-01-01

VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Directory of Open Access Journals (Sweden)

I. Hameem Shanavas

2014-01-01

Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

BioCMOS Interfaces and Co-Design

CERN Document Server

Carrara, Sandro

2013-01-01

The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

Science.gov (United States)

Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

1984-01-01

Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

International Nuclear Information System (INIS)

Jian Haifang; Shi Yin

2009-01-01

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

Energy Technology Data Exchange (ETDEWEB)

Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2009-07-15

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

Science.gov (United States)

Makhijani, Vinod B.; Przekwas, Andrzej J.

2002-10-01

This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

Science.gov (United States)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

Parallel computation of nondeterministic algorithms in VLSI

Energy Technology Data Exchange (ETDEWEB)

Hortensius, P D

1987-01-01

This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Directory of Open Access Journals (Sweden)

T. Kalavathi Devi

2015-01-01

Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

Electro-optic techniques for VLSI interconnect

Science.gov (United States)

Neff, J. A.

1985-03-01

A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

Development of Radhard VLSI electronics for SSC calorimeters

International Nuclear Information System (INIS)

Dawson, J.W.; Nodulman, L.J.

1989-01-01

A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

Science.gov (United States)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1985-01-01

The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

2011-01-01

-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

VLSI structures for track finding

International Nuclear Information System (INIS)

Dell'Orso, M.

1989-01-01

We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

Science.gov (United States)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Parallel VLSI Architecture

Science.gov (United States)

Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

1985-01-01

Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

Science.gov (United States)

Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

2012-01-01

Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

Emergent auditory feature tuning in a real-time neuromorphic VLSI system

Directory of Open Access Journals (Sweden)

Sadique eSheik

2012-02-01

Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

International Nuclear Information System (INIS)

Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

1993-01-01

An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

Science.gov (United States)

Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

2017-12-01

Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

A Knowledge Based Approach to VLSI CAD

Science.gov (United States)

1983-09-01

Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

Opto-VLSI-based reconfigurable free-space optical interconnects architecture

DEFF Research Database (Denmark)

Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

2007-01-01

is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

Carbon nanotube based VLSI interconnects analysis and design

CERN Document Server

Kaushik, Brajesh Kumar

2015-01-01

The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

International Nuclear Information System (INIS)

Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

1995-01-01

A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

A multi coding technique to reduce transition activity in VLSI circuits

International Nuclear Information System (INIS)

Vithyalakshmi, N.; Rajaram, M.

2014-01-01

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

Multi-net optimization of VLSI interconnect

CERN Document Server

Moiseev, Konstantin; Wimer, Shmuel

2015-01-01

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

Integration of SPICE with TEK LV500 ASIC Design Verification System

Directory of Open Access Journals (Sweden)

A. Srivastava

1996-01-01

Full Text Available The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in ‘C’ language in UNIX ‘solaris 1.x’ environment has been developed between SPICE and the testing tools (TekWAVES and LV500. The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor.

Heavy ion tests on programmable VLSI

International Nuclear Information System (INIS)

Provost-Grellier, A.

1989-11-01

The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

Memory Based Machine Intelligence Techniques in VLSI hardware

OpenAIRE

James, Alex Pappachen

2012-01-01

We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

A neuromorphic VLSI device for implementing 2-D selective attention systems.

Science.gov (United States)

Indiveri, G

2001-01-01

Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

Applications of VLSI circuits to medical imaging

International Nuclear Information System (INIS)

O'Donnell, M.

1988-01-01

In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

Nano lasers in photonic VLSI

NARCIS (Netherlands)

Hill, M.T.; Oei, Y.S.; Smit, M.K.

2007-01-01

We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

Science.gov (United States)

Pin, Francois G.; Watanabe, Yutaka

1993-01-01

Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

The AMchip: A VLSI associative memory for track finding

International Nuclear Information System (INIS)

Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

1992-01-01

An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

Fast-prototyping of VLSI

International Nuclear Information System (INIS)

Saucier, G.; Read, E.

1987-01-01

Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

Las Vegas is better than determinism in VLSI and distributed computing

DEFF Research Database (Denmark)

Mehlhorn, Kurt; Schmidt, Erik Meineche

1982-01-01

In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

Point DCT VLSI Architecture for Emerging HEVC Standard

OpenAIRE

Ahmed, Ashfaq; Shahid, Muhammad Usman; Rehman, Ata ur

2012-01-01

This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into ...

Lithography requirements in complex VLSI device fabrication

International Nuclear Information System (INIS)

Wilson, A.D.

1985-01-01

Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

VLSI micro- and nanophotonics science, technology, and applications

CERN Document Server

Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

2011-01-01

Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

Science.gov (United States)

Dante, V; Del Giudice, P; Mattia, M

2001-01-01

We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

A novel configurable VLSI architecture design of window-based image processing method

Science.gov (United States)

Zhao, Hui; Sang, Hongshi; Shen, Xubang

2018-03-01

Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

Science.gov (United States)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

Science.gov (United States)

Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

1989-01-01

The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

Directory of Open Access Journals (Sweden)

V. I. Romanov

2016-01-01

Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

An efficient interpolation filter VLSI architecture for HEVC standard

Science.gov (United States)

Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

2015-12-01

The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

PLA realizations for VLSI state machines

Science.gov (United States)

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

CERN Document Server

Pop, Paul; Madsen, Jan

2016-01-01

This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

Synthesis algorithm of VLSI multipliers for ASIC

Science.gov (United States)

Chua, O. H.; Eldin, A. G.

1993-01-01

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

Science.gov (United States)

2007-03-31

IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

Energy Technology Data Exchange (ETDEWEB)

Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

1992-01-01

The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

Design and Implementation of a Sort-Free K-Best Sphere Decoder

KAUST Repository

Mondal, Sudip

2012-10-18

This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as quantized metrics result in a high throughput VLSI architecture with lower power and area consumption compared to state of the art published systems. Functionality is confirmed via an FPGA implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized ASIC implementation in a 65nm CMOS technology.

Three-dimensional design methodologies for tree-based FPGA architecture

CERN Document Server

Pangracious, Vinod; Mehrez, Habib

2015-01-01

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

Emerging Applications for High K Materials in VLSI Technology

Science.gov (United States)

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Emerging Applications for High K Materials in VLSI Technology

Directory of Open Access Journals (Sweden)

Robert D. Clark

2014-04-01

Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Point DCT VLSI Architecture for Emerging HEVC Standard

Directory of Open Access Journals (Sweden)

Ashfaq Ahmed

2012-01-01

Full Text Available This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

Power efficient and high performance VLSI architecture for AES algorithm

Directory of Open Access Journals (Sweden)

K. Kalaiselvi

2015-09-01

Full Text Available Advanced encryption standard (AES algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay.

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

Science.gov (United States)

Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

2014-05-01

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

Built-in self-repair of VLSI memories employing neural nets

Science.gov (United States)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Numerical analysis of electromigration in thin film VLSI interconnections

NARCIS (Netherlands)

Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

1995-01-01

Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

Modeling selective attention using a neuromorphic analog VLSI device.

Science.gov (United States)

Indiveri, G

2000-12-01

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

An electron undulating ring for VLSI lithography

International Nuclear Information System (INIS)

Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

1985-01-01

The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

Convolving optically addressed VLSI liquid crystal SLM

Science.gov (United States)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

Flip-flop design in nanometer CMOS from high speed to low energy

CERN Document Server

Alioto, Massimo; Palumbo, Gaetano

2015-01-01

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gai...

Automated Design of Board and MCM Level Digital Systems.

Science.gov (United States)

1997-10-01

Object- Oriented Programming, 7(6):39-49, October 1994. 46 December 14, 1994 33 [3] Stephen J. Garland, John V. Guttag, and James J. Horning...of Digital Circuits. Mc Graw Hill, 1994. 15 APPENDIX G: ... 93 Multicomponent Partitioning for VLSI System Synthesis Nand Kumar and Ranga Vemuri

VLSI-based video event triggering for image data compression

Science.gov (United States)

Williams, Glenn L.

1994-02-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Controlling Underwater Robots with Electronic Nervous Systems

Directory of Open Access Journals (Sweden)

Joseph Ayers

2010-01-01

Full Text Available We are developing robot controllers based on biomimetic design principles. The goal is to realise the adaptive capabilities of the animal models in natural environments. We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration electronic neuron (aVLSI networks. DTM networks are realised using neurons based on a 1-D or 2-D Map with two additional parameters that define silent, spiking and bursting regimes. Electronic neurons (ENs based on Hindmarsh–Rose (HR dynamics can be instantiated in analogue VLSI and exhibit similar behaviour to those based on discrete components. We have constructed locomotor central pattern generators (CPGs with aVLSI networks that can be modulated to select different behaviours on the basis of selective command input. The two technologies can be fused by interfacing the signals from the DTM circuits directly to the aVLSI CPGs. Using DTMs, we have been able to simulate complex sensory fusion for rheotaxic behaviour based on both hydrodynamic and optical flow senses. We will illustrate aspects of controllers for ambulatory biomimetic robots. These studies indicate that it is feasible to fabricate an electronic nervous system controller integrating both aVLSI CPGs and layered DTM exteroceptive reflexes.

Design automation, languages, and simulations

CERN Document Server

Chen, Wai-Kai

2003-01-01

As the complexity of electronic systems continues to increase, the micro-electronic industry depends upon automation and simulations to adapt quickly to market changes and new technologies. Compiled from chapters contributed to CRC's best-selling VLSI Handbook, this volume covers a broad range of topics relevant to design automation, languages, and simulations. These include a collaborative framework that coordinates distributed design activities through the Internet, an overview of the Verilog hardware description language and its use in a design environment, hardware/software co-design, syst

New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

Energy Technology Data Exchange (ETDEWEB)

Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

1983-07-01

This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

DEFF Research Database (Denmark)

Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

1991-01-01

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required....... The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2....... The interconnection network occupies 32% of the area.>...

Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

Directory of Open Access Journals (Sweden)

Andres Takach

2006-07-01

Full Text Available Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.

Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

Directory of Open Access Journals (Sweden)

Cavallaro JosephR

2006-01-01

Full Text Available Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.

FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems

Directory of Open Access Journals (Sweden)

Sanjay Singh

2016-03-01

Full Text Available Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576 resolution video streams directly coming from the camera.

Drift chamber tracking with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-10-01

We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

Design and demonstration of a multitechnology FPGA for photonic information processing

Science.gov (United States)

Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

2003-11-01

We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

High-energy heavy ion testing of VLSI devices for single event ...

Indian Academy of Sciences (India)

Unknown

per describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) ... The experimental set up employed to produce low flux of heavy ions viz. silicon ... through which they pass, leaving behind a wake of elec- ... for use in Bus Management Unit (BMU) and bulk CMOS ... was scheduled.

A novel VLSI processor for high-rate, high resolution spectroscopy

CERN Document Server

Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

2000-01-01

A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

CERN Document Server

Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

2003-01-01

Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

Single-chip serial channel enhances multi-processor systems

Energy Technology Data Exchange (ETDEWEB)

Millar, J.

1982-01-01

In this paper multiprocessor systems are described and explained. The impact that VLSI advancements are having on multiprocessor design is pointed out. The TMS 7041 single-chip microcomputer is described briefly, highlighting its multiprocessor communication capability. And finally, a typical multiprocessor system is shown, implementing the TMS 7041.

Adaptive WTA with an analog VLSI neuromorphic learning chip.

Science.gov (United States)

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

Hardware/software co-design and optimization for cyberphysical integration in digital microfluidic biochips

CERN Document Server

Luo, Yan; Ho, Tsung-Yi

2015-01-01

This book describes a comprehensive framework for hardware/software co-design, optimization, and use of robust, low-cost, and cyberphysical digital microfluidic systems. Readers with a background in electronic design automation will find this book to be a valuable reference for leveraging conventional VLSI CAD techniques for emerging technologies, e.g., biochips or bioMEMS. Readers from the circuit/system design community will benefit from methods presented to extend design and testing techniques from microelectronics to mixed-technology microsystems. For readers from the microfluidics domain,

VLSI Architecture and Design

OpenAIRE

Johnsson, Lennart

1980-01-01

Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible....

CAPCAL, 3-D Capacitance Calculator for VLSI Purposes

International Nuclear Information System (INIS)

Seidl, Albert; Klose, Helmut; Svoboda, Mildos

2004-01-01

1 - Description of program or function: CAPCAL is devoted to the calculation of capacitances of three-dimensional wiring configurations are typically used in VLSI circuits. Due to analogies in the mathematical description also conductance and heat transport problems can be treated by CAPCAL. To handle the problem using CAPCAL same approximations have to be applied to the structure under investigation: - the overall geometry has to be confined to a finite domain by using symmetry-properties of the problem - Non-rectangular structures have to be simplified into an artwork of multiple boxes. 2 - Method of solution: The electrical field is described by the Laplace-equation. The differential equation is discretized by using the finite difference method. NEA-1327/01: The linear equation system is solved by using a combined ADI-multigrid method. NEA-1327/04: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. NEA-1327/05: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. 3 - Restrictions on the complexity of the problem: NEA-1327/01: Certain restrictions of use may arise from the dimensioning of arrays. Field lengths are defined via PARAMETER-statements which can easily by modified. If the geometry of the problem is defined such that Neumann boundaries are dominating the convergence of the iterative equation system solver is affected

VLSI Technology for Cognitive Radio

Science.gov (United States)

VIJAYALAKSHMI, B.; SIDDAIAH, P.

2017-08-01

One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

Directory of Open Access Journals (Sweden)

Di Wu

2010-01-01

Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

DEFF Research Database (Denmark)

Paaske, Erik; Pedersen, Steen; Sparsø, Jens

1991-01-01

Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

First results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

1986-01-01

A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

International Nuclear Information System (INIS)

Jones, W.F.; Byars, L.G.; Casey, M.E.

1988-01-01

A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

A High Performance VLSI Computer Architecture For Computer Graphics

Science.gov (United States)

Chin, Chi-Yuan; Lin, Wen-Tai

1988-10-01

A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

Science.gov (United States)

Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

2005-06-01

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

Energy Technology Data Exchange (ETDEWEB)

Zhang, B

1999-07-01

This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

Science.gov (United States)

Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

1990-01-01

The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

Science.gov (United States)

Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

1982-01-01

A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

International Nuclear Information System (INIS)

Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

1992-01-01

Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

DEFF Research Database (Denmark)

Saini, Rishita; Bansal, Neha; Bansal, Meenakshi

2015-01-01

Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient...

Operation of a Fast-RICH Prototype with VLSI readout electronics

Energy Technology Data Exchange (ETDEWEB)

Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

1994-04-01

We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

The effects of advanced digital signal processing concepts on VLSIC/VHSIC design

Science.gov (United States)

Jankowski, C.

Implementations of sophisticated mathematical techniques in advanced digital signal processors can significantly improve performance. Future VLSI and VHSI circuit designs must include the practical realization of these algorithms. A structured design approach is described and illustrated with examples from a RNS FIR filter processor development project. The CAE hardware and software required to support tasks of this complexity are also discussed. An EWS is recommended for controlling essential functions such as logic optimization, simulation and verification. The total IC design system is illustrated with the implementation of a new high performance algorithm for computing complex magnitude.

Design of delay insensitive circuits using multi-ring structures

DEFF Research Database (Denmark)

Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

1992-01-01

The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...

Development of real-time software environments for NASA's modern telemetry systems

Science.gov (United States)

Horner, Ward; Sabia, Steve

1989-01-01

An effort has been made to maintain maximum performance and flexibility for NASA-Goddard's VLSI telemetry system elements through the development of two real-time systems: (1) the Base System Environment, which supports generic system integration and furnishes the basic porting of various manufacturers' cards, and (2) the Modular Environment for Data Systems, which supports application-specific developments and furnishes designers with a set of tested generic library functions that can be employed to speed up the development of such application-specific real-time codes. The performance goals and design rationale for these two systems are discussed.

DESIGN AND IMPLEMENTATION OF A VHDL PROCESSOR FOR DCT BASED IMAGE COMPRESSION

Directory of Open Access Journals (Sweden)

Md. Shabiul Islam

2017-11-01

Full Text Available This paper describes the design and implementation of a VHDL processor meant for performing 2D-Discrete Cosine Transform (DCT to use in image compression applications. The design flow starts from the system specification to implementation on silicon and the entire process is carried out using an advanced workstation based design environment for digital signal processing. The software allows the bit-true analysis to ensure that the designed VLSI processor satisfies the required specifications. The bit-true analysis is performed on all levels of abstraction (behavior, VHDL etc.. The motivation behind the work is smaller size chip area, faster processing, reducing the cost of the chip

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Science.gov (United States)

McEwan, Alistair; van Schaik, André

2003-12-01

The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

Vlsi implementation of flexible architecture for decision tree classification in data mining

Science.gov (United States)

Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

2017-07-01

The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

Algorithms, architectures and information systems security

CERN Document Server

Sur-Kolay, Susmita; Nandy, Subhas C; Bagchi, Aditya

2008-01-01

This volume contains articles written by leading researchers in the fields of algorithms, architectures, and information systems security. The first five chapters address several challenging geometric problems and related algorithms. These topics have major applications in pattern recognition, image analysis, digital geometry, surface reconstruction, computer vision and in robotics. The next five chapters focus on various optimization issues in VLSI design and test architectures, and in wireless networks. The last six chapters comprise scholarly articles on information systems security coverin

Scalable System Design for Covert MIMO Communications

Science.gov (United States)

2014-06-01

Vehicles US United States VHDL VHSIC Hardware Description Language VLSI Very Large Scale Integration WARP Wireless open-Access Research Platform WLAN ...communications, satellite radio and Wireless Local Area Network ( WLAN ) OFDM has been utilized for its multi-path resistance. OFDM relies on the...develop hardware specific to the application provides faster computation times, making FPGA development a very powerful tool. 2.5.1 MIMO Receiver Latency

Global floor planning approach for VLSI design

International Nuclear Information System (INIS)

LaPotin, D.P.

1986-01-01

Within a hierarchical design environment, initial decisions regarding the partitioning and choice of module attributes greatly impact the quality of the resulting IC in terms of area and electrical performance. This dissertation presents a global floor-planning approach which allows designers to quickly explore layout issues during the initial stages of the IC design process. In contrast to previous efforts, which address the floor-planning problem from a strict module placement point of view, this approach considers floor-planning from an area planning point of view. The approach is based upon a combined min-cut and slicing paradigm, which ensures routability. To provide flexibility, modules may be specified as having a number of possible dimensions and orientations, and I/O pads as well as layout constraints are considered. A slicing-tree representation is employed, upon which a sequence of traversal operations are applied in order to obtain an area efficient layout. An in-place partitioning technique, which provides an improvement over previous min-cut and slicing-based efforts, is discussed. Global routing and module I/O pin assignment are provided for floor-plan evaluation purposes. A computer program, called Mason, has been developed which efficiently implements the approach and provides an interactive environment for designers to perform floor-planning. Performance of this program is illustrated via several industrial examples

The Retinal Readout System: a status report A Status Report

CERN Document Server

Litke, A M

1999-01-01

The 'Retinal Readout System' is being developed to study the language the eye uses to send information about the visual world to the brain. Its architecture is based on that of silicon microstrip detectors. An array of 512 microscopic electrodes picks up the signals generated by the output neurons of live retinal tissue in response to a dynamic image focused on the input neurons. These signals are amplified, filtered and multiplexed by a set of eight custom-designed VLSI readout chips, and digitized and recorded by a data acquisition system. This report describes the goals, design, and status of the system. (author)

On the impact of communication complexity in the design of parallel numerical algorithms

Science.gov (United States)

Gannon, D.; Vanrosendale, J.

1984-01-01

This paper describes two models of the cost of data movement in parallel numerical algorithms. One model is a generalization of an approach due to Hockney, and is suitable for shared memory multiprocessors where each processor has vector capabilities. The other model is applicable to highly parallel nonshared memory MIMD systems. In the second model, algorithm performance is characterized in terms of the communication network design. Techniques used in VLSI complexity theory are also brought in, and algorithm independent upper bounds on system performance are derived for several problems that are important to scientific computation.

VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

Directory of Open Access Journals (Sweden)

Georgios Passas

2012-01-01

Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

Initial beam test results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Adolphsen, C.; Litke, A.; Schwarz, A.

1986-01-01

Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

Circuit design for reliability

CERN Document Server

Cao, Yu; Wirth, Gilson

2015-01-01

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

Neuromorphic VLSI vision system for real-time texture segregation.

Science.gov (United States)

Shimonomura, Kazuhiro; Yagi, Tetsuya

2008-10-01

The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Directory of Open Access Journals (Sweden)

Alistair McEwan

2003-06-01

Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

Designing the next generation (fifth generation computers)

International Nuclear Information System (INIS)

Wallich, P.

1983-01-01

A description is given of the designs necessary to develop fifth generation computers. An analysis is offered of problems and developments in parallelism, VLSI, artificial intelligence, knowledge engineering and natural language processing. Software developments are outlined including logic programming, object-oriented programming and exploratory programming. Computer architecture is detailed including concurrent computer architecture

Neuromorphic neural interfaces: from neurophysiological inspiration to biohybrid coupling with nervous systems

Science.gov (United States)

Broccard, Frédéric D.; Joshi, Siddharth; Wang, Jun; Cauwenberghs, Gert

2017-08-01

Objective. Computation in nervous systems operates with different computational primitives, and on different hardware, than traditional digital computation and is thus subjected to different constraints from its digital counterpart regarding the use of physical resources such as time, space and energy. In an effort to better understand neural computation on a physical medium with similar spatiotemporal and energetic constraints, the field of neuromorphic engineering aims to design and implement electronic systems that emulate in very large-scale integration (VLSI) hardware the organization and functions of neural systems at multiple levels of biological organization, from individual neurons up to large circuits and networks. Mixed analog/digital neuromorphic VLSI systems are compact, consume little power and operate in real time independently of the size and complexity of the model. Approach. This article highlights the current efforts to interface neuromorphic systems with neural systems at multiple levels of biological organization, from the synaptic to the system level, and discusses the prospects for future biohybrid systems with neuromorphic circuits of greater complexity. Main results. Single silicon neurons have been interfaced successfully with invertebrate and vertebrate neural networks. This approach allowed the investigation of neural properties that are inaccessible with traditional techniques while providing a realistic biological context not achievable with traditional numerical modeling methods. At the network level, populations of neurons are envisioned to communicate bidirectionally with neuromorphic processors of hundreds or thousands of silicon neurons. Recent work on brain-machine interfaces suggests that this is feasible with current neuromorphic technology. Significance. Biohybrid interfaces between biological neurons and VLSI neuromorphic systems of varying complexity have started to emerge in the literature. Primarily intended as a

CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

International Nuclear Information System (INIS)

Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

1996-01-01

In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Directory of Open Access Journals (Sweden)

Ying-Lun Chen

2015-08-01

Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-08-13

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-01-01

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

Identification and sensitivity analysis of a correlated ground rule system (design arc)

Science.gov (United States)

Eastman, Eric; Chidambarrao, Dureseti; Rausch, Werner; Topaloglu, Rasit O.; Shao, Dongbing; Ramachandran, Ravikumar; Angyal, Matthew

2017-04-01

We demonstrate a tool which can function as an interface between VLSI designers and process-technology engineers throughout the Design-Technology Co-optimization (DTCO) process. This tool uses a Monte Carlo algorithm on the output of lithography simulations to model the frequency of fail mechanisms on wafer. Fail mechanisms are defined according to process integration flow: by Boolean operations and measurements between original and derived shapes. Another feature of this design rule optimization methodology is the use of a Markov-Chain-based algorithm to perform a sensitivity analysis, the output of which may be used by process engineers to target key process-induced variabilities for improvement. This tool is used to analyze multiple Middle-Of-Line fail mechanisms in a 10nm inverter design and identify key process assumptions that will most strongly affect the yield of the structures. This tool and the underlying algorithm are also shown to be scalable to arbitrarily complex geometries in three dimensions. Such a characteristic which is becoming more important with the introduction of novel patterning technologies and more complex 3-D on-wafer structures.

VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

Directory of Open Access Journals (Sweden)

B. SENTHILKUMAR

2015-05-01

Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

Directory of Open Access Journals (Sweden)

N.R. Divya

2014-08-01

Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

A Near-Lossless Image Compression Algorithm Suitable for Hardware Design in Wireless Endoscopy System

Directory of Open Access Journals (Sweden)

Xie Xiang

2007-01-01

Full Text Available In order to decrease the communication bandwidth and save the transmitting power in the wireless endoscopy capsule, this paper presents a new near-lossless image compression algorithm based on the Bayer format image suitable for hardware design. This algorithm can provide low average compression rate ( bits/pixel with high image quality (larger than dB for endoscopic images. Especially, it has low complexity hardware overhead (only two line buffers and supports real-time compressing. In addition, the algorithm can provide lossless compression for the region of interest (ROI and high-quality compression for other regions. The ROI can be selected arbitrarily by varying ROI parameters. In addition, the VLSI architecture of this compression algorithm is also given out. Its hardware design has been implemented in m CMOS process.

Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

CERN Document Server

Annovi, A; The ATLAS collaboration; Beretta, M; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Hoff, J; Liu, T; Liberali, V; Sacco, I; Schoening, A; Soltveit, H K; Stabile, A; Tripiccione, R

2011-01-01

We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution patt...

Real-time qualitative reasoning for telerobotic systems

Science.gov (United States)

Pin, Eancois G.

1993-01-01

This paper discusses the sensor-based telerobotic driving of a car in a-priori unknown environments using 'human-like' reasoning schemes implemented on custom-designed VLSI fuzzy inferencing boards. These boards use the Fuzzy Set theoretic framework to allow very vast (30 kHz) processing of full sets of information that are expressed in qualitative form using membership functions. The sensor-based and fuzzy inferencing system was incorporated on an outdoor test-bed platform to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously to a goal specified by the operator, while in the second mode, the system acts as a telerobotic driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right, speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Indoor and outdoor experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented that illustrate the feasibility of developing autonomous navigation modules and robust, safety-enhancing driver's aids for telerobotic systems using the new fuzzy inferencing VLSI hardware and 'human-like' reasoning schemes.

Flow-Based Biochips: Fault-Tolerant Design and Error Recovery

DEFF Research Database (Denmark)

Pop, Paul

2015-01-01

VLSI). Biochips are currently being designed manually using tools such as AutoCAD. Physical defects can be introduced during the fabrication process, which reduces the yield, and may lead to the failure of the biochemical application. Failure is costly because of the need to redo lengthy experiments, using...

A VLSI System-on-Chip for Particle Detectors

CERN Document Server

AUTHOR|(CDS)2078019

In this thesis I present a System-on-Chip (SoC) I designed to oer a self- contained, compact data acquisition platform for micromegas detector mon- itoring. I carried on my work within the RD-51 collab oration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electro de, pro cess the data and p erform monitoring tests. The SoC is built around on a custom 8-bit micropro cessor with internal mem- ory resources and emb eds the p eripherals to b e interf...

The scientific data acquisition system of the GAMMA-400 space project

Science.gov (United States)

Bobkov, S. G.; Serdin, O. V.; Gorbunov, M. S.; Arkhangelskiy, A. I.; Topchiev, N. P.

2016-02-01

The description of scientific data acquisition system (SDAS) designed by SRISA for the GAMMA-400 space project is presented. We consider the problem of different level electronics unification: the set of reliable fault-tolerant integrated circuits fabricated on Silicon-on-Insulator 0.25 mkm CMOS technology and the high-speed interfaces and reliable modules used in the space instruments. The characteristics of reliable fault-tolerant very large scale integration (VLSI) technology designed by SRISA for the developing of computation systems for space applications are considered. The scalable net structure of SDAS based on Serial RapidIO interface including real-time operating system BAGET is described too.

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

Directory of Open Access Journals (Sweden)

T. Tharaneeswaran

2012-06-01

Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

Computers start to think with expert systems

Energy Technology Data Exchange (ETDEWEB)

1983-03-21

A growing number of professionals-notably in oil and mineral exploration, plasma research, medicine, VLSI circuit design, drug design and robotics-are beginning to use computerised expert systems. A computer program uses knowledge and inference procedures to solve problems which are sufficiently difficult to require significant human expertise for their solution. The facts constitute a body of information that is widely shared, publicly available and generally agreed upon by experts in the field. The heuristics are mostly private, and little discussed, rules of good judgement (rules of plausible reasoning, rules of good guessing, etc.) that characterise expert-level decision making in the field.

VLSI systems energy management from a software perspective – A literature survey

Directory of Open Access Journals (Sweden)

Prasada Kumari K.S.

2016-09-01

Full Text Available The increasing demand for ultra-low power electronic systems has motivated research in device technology and hardware design techniques. Experimental studies have proved that the hardware innovations for power reduction are fully exploited only with the proper design of upper layer software. Also, the software power and energy modelling and analysis – the first step towards energy reduction is complex due to the inter and intra dependencies of processors, operating systems, application software, programming languages and compilers. The subject is too vast; the paper aims to give a consolidated view to researchers in arriving at solutions to power optimization problems from a software perspective. The review emphasizes the fact that software design and implementation is to be viewed from system energy conservation angle rather than as an isolated process. After covering a global view of end to end software based power reduction techniques for micro sensor nodes to High Performance Computing systems, specific design aspects related to battery powered Embedded computing for mobile and portable systems are addressed in detail. The findings are consolidated into 2 major categories – those related to research directions and those related to existing industry practices. The emerging concept of Green Software with specific focus on mainframe computing is also discussed in brief. Empirical results on power saving are included wherever available. The paper concludes that only with the close co-ordination between hardware architect, software architect and system architect low energy systems can be realized.

Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design

DEFF Research Database (Denmark)

Araci, Ismail Emre; Pop, Paul; Chakrabarty, Krishnendu

2015-01-01

of this paper is on continuous-flow biochips, where the basic building block is a microvalve. By combining these microvalves, more complex units such as mixers, switches, multiplexers can be built, hence the name of the technology, “microfluidic Very Large-Scale Integration” (mVLSI). A roadblock......Microfluidic biochips are replacing the conventional biochemical analyzers by integrating all the necessary functions for biochemical analysis using microfluidics. Biochips are used in many application areas, such as, in vitro diagnostics, drug discovery, biotech and ecology. The focus...... presents the state-of-the-art in the mVLSI platforms and emerging research challenges in the area of continuous-flow microfluidics, focusing on testing techniques and fault-tolerant design....

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

Transformational VLSI Design

DEFF Research Database (Denmark)

Rasmussen, Ole Steen

constructed. It contains a semantical embedding of Ruby in Zermelo-Fraenkel set theory (ZF) implemented in the Isabelle theorem prover. A small subset of Ruby, called Pure Ruby, is embedded as a conservative extension of ZF and characterised by an inductive definition. Many useful structures used...

A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

Directory of Open Access Journals (Sweden)

C. Wu

2011-06-01

Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.

Principles of VLSI RTL design a practical guide

CERN Document Server

Churiwala, Sanjay; Gianfagna, Mike

2011-01-01

This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

DESIGN OF LOW EPI AND HIGH THROUGHPUT CORDIC CELL TO IMPROVE THE PERFORMANCE OF MOBILE ROBOT

Directory of Open Access Journals (Sweden)

P. VELRAJKUMAR

2014-04-01

Full Text Available This paper mainly focuses on pass logic based design, which gives an low Energy Per Instruction (EPI and high throughput COrdinate Rotation Digital Computer (CORDIC cell for application of robotic exploration. The basic components of CORDIC cell namely register, multiplexer and proposed adder is designed using pass transistor logic (PTL design. The proposed adder is implemented in bit-parallel iterative CORDIC circuit whereas designed using DSCH2 VLSI CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The propagation delay, area and power dissipation are calculated from the simulated results for proposed adder based CORDIC cell. The EPI, throughput and effect of temperature are calculated from generated layout. The output parameter of generated layout is analysed using BSIM4 advanced analyzer. The simulated result of the proposed adder based CORDIC circuit is compared with other adder based CORDIC circuits. From the analysis of these simulated results, it was found that the proposed adder based CORDIC circuit dissipates low power, gives faster response, low EPI and high throughput.

Design and Implementation of a New Real-Time Frequency Sensor Used as Hardware Countermeasure

Directory of Open Access Journals (Sweden)

Manuel Pedro-Carrasco

2013-09-01

Full Text Available A new digital countermeasure against attacks related to the clock frequency is presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC, and the implementation has been verified and characterized with an integrated design using a 0.35 mm standard Complementary Metal Oxide Semiconductor (CMOS technology (Very Large Scale Implementation—VLSI implementation. The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack.

Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

Science.gov (United States)

Carvajal, Gonzalo; Figueroa, Miguel

2014-07-01

Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

Practical guide to organic field effect transistor circuit design

CERN Document Server

Sou, Antony

2016-01-01

The field of organic electronics spans a very wide range of disciplines from physics and chemistry to hardware and software engineering. This makes the field of organic circuit design a daunting prospect full of intimidating complexities, yet to be exploited to its true potential. Small focussed research groups also find it difficult to move beyond their usual boundaries and create systems-on-foil that are comparable with the established silicon world.This book has been written to address these issues, intended for two main audiences; firstly, physics or materials researchers who have thus far designed circuits using only basic drawing software; and secondly, experienced silicon CMOS VLSI design engineers who are already knowledgeable in the design of full custom transistor level circuits but are not familiar with organic devices or thin film transistor (TFT) devices.In guiding the reader through the disparate and broad subject matters, a concise text has been written covering the physics and chemistry of the...

Multi-operation cryptographic engine: VLSI design and implementation

International Nuclear Information System (INIS)

Selimis, George; Koufopavlou, Odysseas

2005-01-01

The environment of smart card lacks of system resources but the commercial and economic transactions via smart cards demand the use of certificated and secure cryptographic methods. In this paper a cryptographic approach in hardware for smart cards is proposed. The proposed system supports two basic operations of cryptography, authentication and encryption. The basic component of system is the one round of DES algorithm which supports the DES, Triple DES and the ANSI X9.17 standards. The proposed system is efficient in terms of area resources and techniques for low power consumption have applied. Due to the fact that the system is for smart card applications the overall throughput outperforms the typical smart card throughput standards

International Conference on Nano-electronics, Circuits & Communication Systems

CERN Document Server

2017-01-01

This volume comprises select papers from the International Conference on Nano-electronics, Circuits & Communication Systems(NCCS). The conference focused on the frontier issues and their applications in business, academia, industry, and other allied areas. This international conference aimed to bring together scientists, researchers, engineers from academia and industry. The book covers technological developments and current trends in key areas such as VLSI design, IC manufacturing, and applications such as communications, ICT, and hybrid electronics. The contents of this volume will prove useful to researchers, professionals, and students alike.

DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC

Directory of Open Access Journals (Sweden)

A. KISHORE KUMAR

2014-12-01

Full Text Available Static Random Access Memory (SRAM has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST logic is proposed. The main intention of this paper is to design a new SRAM cell architecture to reduce the power consumption during both read / write operations and to improve SRAM access stability. The proposed design is simulated using 0.18 µm process technology and compared with conventional 6T cell. Simulation results show that the proposed memory cell achieves significant improvements in power consumption during read and write operations. It can retain data at a lower supply voltage of 300 mV. This new type of SRAM design can operate at a maximum frequency of 1 GHz at 1 V supply voltage. These qualities of the proposed design make it a best choice for high performance memory chips in the semiconductor industry where reliability and power consumption are of great interest.

Challenge for knowledge information processing systems (preliminary report on Fifth Generation Computer Systems)

Energy Technology Data Exchange (ETDEWEB)

Moto-oka, T

1982-01-01

The author explains the reasons, aims and strategies for the Fifth Generation Computer Project in Japan. The project aims to introduce a radical new breed of computer by 1990. This article outlines the economic and social reasons for the project. It describes the impacts and effects that these computers are expected to have. The areas of technology which will form the contents of the research and development are highlighted. These are areas such as VLSI technology, speech and image understanding systems, artificial intelligence and advanced architecture design. Finally a schedule for completion of research is given which aims for a completed project by 1990.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

Science.gov (United States)

Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

2016-12-07

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Real time track finding in a drift chamber with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-01-01

In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

Electronic shift register memory based on molecular electron-transfer reactions

Science.gov (United States)

Hopfield, J. J.; Onuchic, Jose Nelson; Beratan, David N.

1989-01-01

The design of a shift register memory at the molecular level is described in detail. The memory elements are based on a chain of electron-transfer molecules incorporated on a very large scale integrated (VLSI) substrate, and the information is shifted by photoinduced electron-transfer reactions. The design requirements for such a system are discussed, and several realistic strategies for synthesizing these systems are presented. The immediate advantage of such a hybrid molecular/VLSI device would arise from the possible information storage density. The prospect of considerable savings of energy per bit processed also exists. This molecular shift register memory element design solves the conceptual problems associated with integrating molecular size components with larger (micron) size features on a chip.

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

Science.gov (United States)

Yu, Theodore; Cauwenberghs, Gert

2009-01-01

We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Directory of Open Access Journals (Sweden)

Yuan-Jyun Chang

2016-12-01

Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

Science.gov (United States)

Yu, T; Sejnowski, T J; Cauwenberghs, G

2011-10-01

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

Design and Implementation of a linear-phase equalizer in digital audio signal processing

NARCIS (Netherlands)

Slump, Cornelis H.; van Asma, C.G.M.; Barels, J.K.P.; Barels, J.K.P.; Brunink, W.J.A; Drenth, F.B.; Pol, J.V.; Schouten, D.S.; Samsom, M.M.; Samsom, M.M.; Herrmann, O.E.

1992-01-01

This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

Low-Power Differential SRAM design for SOC Based on the 25-um Technology

Science.gov (United States)

Godugunuri, Sivaprasad; Dara, Naveen; Sambasiva Nayak, R.; Nayeemuddin, Md; Singh, Yadu, Dr.; Veda, R. N. S. Sunil

2017-08-01

In recent, the SOC styles area unit the vast complicated styles in VLSI these SOC styles having important low-power operations problems, to comprehend this we tend to enforced low-power SRAM. However these SRAM Architectures critically affects the entire power of SOC and competitive space. To beat the higher than disadvantages, during this paper, a low-power differential SRAM design is planned. The differential SRAM design stores multiple bits within the same cell, operates at minimum in operation low-tension and space per bit. The differential SRAM design designed supported the 25-um technology using Tanner-EDA Tool.

10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

Science.gov (United States)

Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

1985-02-01

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

CERN Document Server

Liberali, Valentino; The ATLAS collaboration

2016-01-01

We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparis...

Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques

Directory of Open Access Journals (Sweden)

Nikos Sklavos

2002-01-01

Full Text Available An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6 μm CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently in Wireless Encryption Protocols and high speed networks.

VLSI implementation of a fairness ATM buffer system

DEFF Research Database (Denmark)

Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

1996-01-01

that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

Designing information systems

CERN Document Server

Blethyn, Stanley G

2014-01-01

Designing Information Systems focuses on the processes, methodologies, and approaches involved in designing information systems. The book first describes systems, management and control, and how to design information systems. Discussions focus on documents produced from the functional construction function, users, operators, analysts, programmers and others, process management and control, levels of management, open systems, design of management information systems, and business system description, partitioning, and leveling. The text then takes a look at functional specification and functiona

Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-05-01

Full Text Available The design of smart video surveillance systems is an active research field among the computer vision community because of their ability to perform automatic scene analysis by selecting and tracking the objects of interest. In this paper, we present the design and implementation of an FPGA-based standalone working prototype system for real-time tracking of an object of interest in live video streams for such systems. In addition to real-time tracking of the object of interest, the implemented system is also capable of providing purposive automatic camera movement (pan-tilt in the direction determined by movement of the tracked object. The complete system, including camera interface, DDR2 external memory interface controller, designed object tracking VLSI architecture, camera movement controller and display interface, has been implemented on the Xilinx ML510 (Virtex-5 FX130T FPGA Board. Our proposed, designed and implemented system robustly tracks the target object present in the scene in real time for standard PAL (720 × 576 resolution color video and automatically controls camera movement in the direction determined by the movement of the tracked object.

The CDF Silicon Vertex Detector

International Nuclear Information System (INIS)

Tkaczyk, S.; Carter, H.; Flaugher, B.

1993-01-01

A silicon strip vertex detector was designed, constructed and commissioned at the CDF experiment at the Tevatron collider at Fermilab. The mechanical design of the detector, its cooling and monitoring are presented. The front end electronics employing a custom VLSI chip, the readout electronics and various components of the SVX system are described. The system performance and the experience with the operation of the

Hardware Descriptive Languages: An Efficient Approach to Device ...

African Journals Online (AJOL)

Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog ...

Missileborne Artificial Vision System (MAVIS)

Science.gov (United States)

Andes, David K.; Witham, James C.; Miles, Michael D.

1994-01-01

Several years ago when INTEL and China Lake designed the ETANN chip, analog VLSI appeared to be the only way to do high density neural computing. In the last five years, however, digital parallel processing chips capable of performing neural computation functions have evolved to the point of rough equality with analog chips in system level computational density. The Naval Air Warfare Center, China Lake, has developed a real time, hardware and software system designed to implement and evaluate biologically inspired retinal and cortical models. The hardware is based on the Adaptive Solutions Inc. massively parallel CNAPS system COHO boards. Each COHO board is a standard size 6U VME card featuring 256 fixed point, RISC processors running at 20 MHz in a SIMD configuration. Each COHO board has a companion board built to support a real time VSB interface to an imaging seeker, a NTSC camera, and to other COHO boards. The system is designed to have multiple SIMD machines each performing different corticomorphic functions. The system level software has been developed which allows a high level description of corticomorphic structures to be translated into the native microcode of the CNAPS chips. Corticomorphic structures are those neural structures with a form similar to that of the retina, the lateral geniculate nucleus, or the visual cortex. This real time hardware system is designed to be shrunk into a volume compatible with air launched tactical missiles. Initial versions of the software and hardware have been completed and are in the early stages of integration with a missile seeker.

Reactor System Design

International Nuclear Information System (INIS)

Chi, S. K.; Kim, G. K.; Yeo, J. W.

2006-08-01

SMART NPP(Nuclear Power Plant) has been developed for duel purpose, electricity generation and energy supply for seawater desalination. The objective of this project IS to design the reactor system of SMART pilot plant(SMART-P) which will be built and operated for the integrated technology verification of SMART. SMART-P is an integral reactor in which primary components of reactor coolant system are enclosed in single pressure vessel without connecting pipes. The major components installed within a vessel includes a core, twelve steam generator cassettes, a low-temperature self pressurizer, twelve control rod drives, and two main coolant pumps. SMART-P reactor system design was categorized to the reactor coe design, fluid system design, reactor mechanical design, major component design and MMIS design. Reactor safety -analysis and performance analysis were performed for developed SMART=P reactor system. Also, the preparation of safety analysis report, and the technical support for licensing acquisition are performed

Control system design guide

Energy Technology Data Exchange (ETDEWEB)

Sellers, David; Friedman, Hannah; Haasl, Tudi; Bourassa, Norman; Piette, Mary Ann

2003-05-01

The ''Control System Design Guide'' (Design Guide) provides methods and recommendations for the control system design process and control point selection and installation. Control systems are often the most problematic system in a building. A good design process that takes into account maintenance, operation, and commissioning can lead to a smoothly operating and efficient building. To this end, the Design Guide provides a toolbox of templates for improving control system design and specification. HVAC designers are the primary audience for the Design Guide. The control design process it presents will help produce well-designed control systems that achieve efficient and robust operation. The spreadsheet examples for control valve schedules, damper schedules, and points lists can streamline the use of the control system design concepts set forth in the Design Guide by providing convenient starting points from which designers can build. Although each reader brings their own unique questions to the text, the Design Guide contains information that designers, commissioning providers, operators, and owners will find useful.

Computer System Design System-on-Chip

CERN Document Server

Flynn, Michael J

2011-01-01

The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

Digital Systems Validation Handbook. Volume 2. Chapter 18. Avionic Data Bus Integration Technology

Science.gov (United States)

1993-11-01

interaction between a digital data bus and an avionic system. Very Large Scale Integration (VLSI) ICs and multiversion software, which make up digital...1984, the Sperry Corporation developed a fault tolerant system which employed multiversion programming, voting, and monitoring for error detection and...formulate all the significant behavior of a system. MULTIVERSION PROGRAMMING. N-version programming. N-VERSION PROGRAMMING. The independent coding of a

Design of two-terminal PNPN diode for high-density and high-speed memory applications

International Nuclear Information System (INIS)

Tong Xiaodong; Wu Hao; Liang Qingqing; Zhong Huicai; Zhu Huilong; Zhao Chao; Ye Tianchun

2014-01-01

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLSI applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability. (semiconductor devices)

Optical system design

CERN Document Server

Fischer, Robert F

2008-01-01

Honed for more than 20 years in an SPIE professional course taught by renowned optical systems designer Robert E. Fischer, Optical System Design, Second Edition brings you the latest cutting-edge design techniques and more than 400 detailed diagrams that clearly illustrate every major procedure in optical design. This thoroughly updated resource helps you work better and faster with computer-aided optical design techniques, diffractive optics, and the latest applications, including digital imaging, telecommunications, and machine vision. No need for complex, unnecessary mathematical derivations-instead, you get hundreds of examples that break the techniques down into understandable steps. For twenty-first century optical design without the mystery, the authoritative Optical Systems Design, Second Edition features: Computer-aided design use explained through sample problems Case studies of third-millennium applications in digital imaging, sensors, lasers, machine vision, and more New chapters on optomechanic...

Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

Directory of Open Access Journals (Sweden)

Massimiliano eGiulioni

2012-02-01

Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

Science.gov (United States)

Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

2011-01-01

We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

Compact Interconnection Networks Based on Quantum Dots

Science.gov (United States)

Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

2003-01-01

Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

DEFF Research Database (Denmark)

Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

2015-01-01

standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

Smart AD and DA Converters

NARCIS (Netherlands)

Roermund, van A.H.M.; Hegt, J.A.; Harpe, P.J.A.; Radulov, G.I.; Zanikopoulos, A.; Doris, K.; Quinn, P.J.

2005-01-01

In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance

A multichannel compact readout system for single photon detection: Design and performances

Energy Technology Data Exchange (ETDEWEB)

Argentieri, A.G. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Cisbani, E.; Colilli, S.; Cusanno, F. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy); De Leo, R. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy); Marra, M. [Istituto Nazionale di Fisica Nucleare, via E. Orabona 4, 70126 Bari (Italy); Musico, Paolo, E-mail: Paolo.Musico@ge.infn.i [Istituto Nazionale di Fisica Nucleare, via Dodecaneso 33, 16146 Genova (Italy); Santavenere, F.; Torrioli, S. [Istituto Superiore di Sanita, viale Regina Elena 299, 00161 Roma (Italy)

2010-05-21

Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested . The system can handle up to 4096 independent channels, covering an area of about 20x20cm{sup 2} with pixel size of 3x3mm{sup 2}, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3x3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

A multichannel compact readout system for single photon detection: Design and performances

Science.gov (United States)

Argentieri, A. G.; Cisbani, E.; Colilli, S.; Cusanno, F.; De Leo, R.; Fratoni, R.; Garibaldi, F.; Giuliani, F.; Gricia, M.; Lucentini, M.; Marra, M.; Musico, Paolo; Santavenere, F.; Torrioli, S.

2010-05-01

Optimal exploitation of Multi Anode PhotoMultiplier Tubes (MAPMT) as imaging devices requires the acquisition of a large number of independent channels; despite the rather wide demand, on-the-shelf electronics for this purpose does not exist. A compact independent channel readout system for an array of MAPMTs has been developed and tested [1,2]. The system can handle up to 4096 independent channels, covering an area of about 20×20 cm2 with pixel size of 3×3 mm2, using Hamamatsu H-9500 devices. The front-end is based on a 64 channels VLSI custom chip called MAROC, developed by IN2P3 Orsay (France) group, controlled by means of a Field Programmable Gate Array (FPGA) which implements configuration, triggering and data conversion controls. Up to 64 front-end cards can be housed in four backplanes and a central unit collects data from all of them, communicating with a control Personal Computer (PC) using an high speed USB 2.0 connection. A complete system has been built and tested. Eight Flat MAPMTs (256 anodes Hamamatsu H-9500) have been arranged on a boundary of a 3×3 matrix for a grand total of 2048 channels. This detector has been used to verify the performances of a focusing aerogel RICH prototype using an electron beam at the Frascati (Rome) INFN National Laboratory Beam Test Facility (BTF) during the last week of January 2009. Data analysis is ongoing: the first results are encouraging, showing that the Cherenkov rings are well identified by this system.

A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

Directory of Open Access Journals (Sweden)

Jian (Denny Lin

2014-05-01

Full Text Available With the advanced technology used to design VLSI (Very Large Scale Integration circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.

HDL to verification logic translator

Science.gov (United States)

Gambles, J. W.; Windley, P. J.

1992-01-01

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Directory of Open Access Journals (Sweden)

Mauro Olivieri

2013-01-01

Full Text Available Synchronous early-completion-prediction adders (ECPAs are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

A Framework for Systemic Design

Directory of Open Access Journals (Sweden)

Alex Ryan

2014-12-01

Full Text Available As designers move upstream from traditional product and service design to engage with challenges characterised by complexity, uniqueness, value conflict, and ambiguity over objectives, they have increasingly integrated systems approaches into their practice. This synthesis of systems thinking with design thinking is forming a distinct new field of systemic design. This paper presents a framework for systemic design as a mindset, methodology, and set of methods that together enable teams to learn, innovate, and adapt to a complex and dynamic environment. We suggest that a systemic design mindset is inquiring, open, integrative, collaborative, and centred. We propose a systemic design methodology composed of six main activities: framing, formulating, generating, reflecting, inquiring, and facilitating. We view systemic design methods as a flexible and open-ended set of procedures for facilitating group collaboration that are both systemic and designerly.  

Designing Deliberation Systems

DEFF Research Database (Denmark)

Rose, Jeremy; Sæbø, Øystein

2010-01-01

the potential to revitalize and transform citizen engagement in democracy.  Although the majority of web 2.0 systems enable these discourses to some extent, government institutions commission and manage specialized deliberation systems (information systems designed to support participative discourse) intended...... to promote citizen engagement.  The most common examples of these are political discussion forums.  Though usually considered trivial adaptations of well-known technologies, these types of deliberative systems are often unsuccessful, and present a distinct set of design and management challenges.......  In this article we analyze the issues involved in establishing political deliberation systems under four headings: stakeholder engagement, web platform design, service management, political process re-shaping and evaluation and improvement.  We review the existing literature and present a longitudinal case study...

Structural design by CAD system

International Nuclear Information System (INIS)

Kim, Jhin Wung; Shim, Jae Ku; Kim, Sun Hoon; Kim, Dae Hong; Lee, Kyung Jin; Choi, Kyu Sup; Choi, In Kil; Lee, Dong Yong

1988-12-01

CAD systems are now widely used for the design of many engineering problems involving static, dynamic and thermal stress analyses of structures. In order to apply CAD systems to the structural analysis and design, the function of hardwares and softwares necessary for the CAD systems must be understood. The purpose of this study is to introduce the basic elements that are indispensible in the application of CAD systems to the analysis and design of structures and to give a thorough understanding of CAD systems to design engineers, so as to participate in the further technological developments of CAD systems. Due to the complexity and variety of the shape and size of the nowa-days structures, the need of new design technologies is growing for more efficient, accurate and economical design of structures. The application of CAD systems to structural engineering fields enables to improve structural engineering analysis and design technologies and also to obtain the standardization of the design process. An active introduction of rapidly developing CAD technologies will contribute to analyzing and designing structures more efficiently and reliably. Based on this report of the current status of the application of CAD systems to the structural analysis and design, the next goal is to develop the expert system which enables to perform the design of structures by CAD systems from the preliminary conceptual design to the final detail drawings automatically. (Author)

An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

Science.gov (United States)

Karaki, Nobuo; Nanmoto, Takashi; Inoue, Satoshi

This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

Systems engineering agile design methodologies

CERN Document Server

Crowder, James A

2013-01-01

This book examines the paradigm of the engineering design process. The authors discuss agile systems and engineering design. The book captures the entire design process (functionbases), context, and requirements to affect real reuse. It provides a methodology for an engineering design process foundation for modern and future systems design. This book captures design patterns with context for actual Systems Engineering Design Reuse and contains a new paradigm in Design Knowledge Management.

Rectenna system design

Science.gov (United States)

Brown, W. C.; Dickinson, R. M.; Nalos, E. J.; Ott, J. H.

1980-01-01

The function of the rectenna in the solar power satellite system is described and the basic design choices based on the desired microwave field concentration and ground clearance requirements are given. One important area of concern, from the EMI point of view, harmonic reradiation and scattering from the rectenna is also designed. An optimization of a rectenna system design to minimize costs was performed. The rectenna cost breakdown for a 56 w installation is given as an example.

Human Systems Design Criteria

DEFF Research Database (Denmark)

Rasmussen, Jens

1982-01-01

This paper deals with the problem of designing more humanised computer systems. This problem can be formally described as the need for defining human design criteria, which — if used in the design process - will secure that the systems designed get the relevant qualities. That is not only...... the necessary functional qualities but also the needed human qualities. The author's main argument is, that the design process should be a dialectical synthesis of the two points of view: Man as a System Component, and System as Man's Environment. Based on a man's presentation of the state of the art a set...... of design criteria is suggested and their relevance discussed. The point is to focus on the operator rather than on the computer. The crucial question is not to program the computer to work on its own conditions, but to “program” the operator to function on human conditions....

Licensing management system prototype system design

International Nuclear Information System (INIS)

Immerman, W.H.; Arcuni, A.A.; Elliott, J.M.; Chapman, L.D.

1983-11-01

This report is a design document for a prototype implementation of a licensing management system (LMS) as defined in SAND83-7080. It describes the concept of operations for full implementation of an LMS in accordance with the previously defined functional requirements. It defines a subset of a full LMS suitable for meeting prototype implementation goals, and proposes a system design for this subset. The report describes overall system design considerations consistent with, but more explicit than the general characteristics required by the LMS functional definition. A high level design is presented for just those functions selected for prototype implementation. The report also provides a data element dictionary describing the structured logical data elements required to implement the selected functions

HVAC systems design handbook

CERN Document Server

Haines, Roger W

2010-01-01

Thoroughly updated with the latest codes, technologies, and practices, this all-in-one resource provides details, calculations, and specifications for designing efficient and effective residential, commercial, and industrial HVAC systems. HVAC Systems Design Handbook, Fifth Edition, features new information on energy conservation and computer usage for design and control, as well as the most recent International Code Council (ICC) Mechanical Code requirements. Detailed illustrations, tables, and essential HVAC equations are also included. This comprehensive guide contains everything you need to design, operate, and maintain peak-performing HVAC systems.

Robust Bioinformatics Recognition with VLSI Biochip Microsystem

Science.gov (United States)

Lue, Jaw-Chyng L.; Fang, Wai-Chi

2006-01-01

A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

System 80+trademark Standard Design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report, entitled Combustion Engineering Standard Safety Analysis Report -- Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describe the Combustion Engineering, Inc. System 80 + trademark Standard Design. This volume 9 discusses Electric Power and Auxiliary Systems

Sadhana | Indian Academy of Sciences

Indian Academy of Sciences (India)

This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead ...

Practical RF system design

CERN Document Server

Egan, William F

2003-01-01

he ultimate practical resource for today's RF system design professionals Radio frequency components and circuits form the backbone of today's mobile and satellite communications networks. Consequently, both practicing and aspiring industry professionals need to be able to solve ever more complex problems of RF design. Blending theoretical rigor with a wealth of practical expertise, Practical RF System Design addresses a variety of complex, real-world problems that system engineers are likely to encounter in today's burgeoning communications industry with solutions that are not easily available in the existing literature. The author, an expert in the field of RF module and system design, provides powerful techniques for analyzing real RF systems, with emphasis on some that are currently not well understood. Combining theoretical results and models with examples, he challenges readers to address such practical issues as: * How standing wave ratio affects system gain * How noise on a local oscillator will affec...

Airport Information Retrieval System (AIRS) System Design

Science.gov (United States)

1974-07-01

This report presents the system design for a prototype air traffic flow control automation system developed for the FAA's Systems Command Center. The design was directed toward the immediate automation of airport data for use in traffic load predicti...

Systematic configuration and automatic tuning of neuromorphic systems

OpenAIRE

Sheik Sadique; Stefanini Fabio; Neftci Emre; Chicca Elisabetta; Indiveri Giacomo

2011-01-01

In the past recent years several research groups have proposed neuromorphic Very Large Scale Integration (VLSI) devices that implement event-based sensors or biophysically realistic networks of spiking neurons. It has been argued that these devices can be used to build event-based systems, for solving real-world applications in real-time, with efficiencies and robustness that cannot be achieved with conventional computing technologies. In order to implement complex event-based neuromorphic sy...

System level ESD co-design

CERN Document Server

Gossner, Harald

2015-01-01

An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from ‘hard’ to ‘soft’ types are considered to review simulation and tool applications that can be used. The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance. With contributions from Robert Asht...

System Design for Telecommunication Gateways

CERN Document Server

Bachmutsky, Alexander

2010-01-01

System Design for Telecommunication Gateways provides a thorough review of designing telecommunication network equipment based on the latest hardware designs and software methods available on the market. Focusing on high-end efficient designs that challenge all aspects of the system architecture, this book helps readers to understand a broader view of the system design, analyze all its most critical components, and select the parts that best fit a particular application. In many cases new technology trends, potential future developments, system flexibility and capability extensions are outline

System 80+trademark Standard Design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report, entitled Combustion Engineering Standard Safety Analysis Report -- Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describe the Combustion Engineering, Inc. System 80 + trademark Standard Design. This volume 10 discusses the Steam and Power Conversion System and Radioactive Waste Management

Applied Control Systems Design

CERN Document Server

Mahmoud, Magdi S

2012-01-01

Applied Control System Design examines several methods for building up systems models based on real experimental data from typical industrial processes and incorporating system identification techniques. The text takes a comparative approach to the models derived in this way judging their suitability for use in different systems and under different operational circumstances. A broad spectrum of control methods including various forms of filtering, feedback and feedforward control is applied to the models and the guidelines derived from the closed-loop responses are then composed into a concrete self-tested recipe to serve as a check-list for industrial engineers or control designers. System identification and control design are given equal weight in model derivation and testing to reflect their equality of importance in the proper design and optimization of high-performance control systems. Readers’ assimilation of the material discussed is assisted by the provision of problems and examples. Most of these e...

Entropy coders of the H.264/AVC standard

CERN Document Server

Tian, Xiaohua; Lian, Yong

2010-01-01

This book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from

Bio-Inspired Microsystem for Robust Genetic Assay Recognition

Directory of Open Access Journals (Sweden)

Jaw-Chyng Lue

2008-01-01

Full Text Available A compact integrated system-on-chip (SoC architecture solution for robust, real-time, and on-site genetic analysis has been proposed. This microsystem solution is noise-tolerable and suitable for analyzing the weak fluorescence patterns from a PCR prepared dual-labeled DNA microchip assay. In the architecture, a preceding VLSI differential logarithm microchip is designed for effectively computing the logarithm of the normalized input fluorescence signals. A posterior VLSI artificial neural network (ANN processor chip is used for analyzing the processed signals from the differential logarithm stage. A single-channel logarithmic circuit was fabricated and characterized. A prototype ANN chip with unsupervised winner-take-all (WTA function was designed, fabricated, and tested. An ANN learning algorithm using a novel sigmoid-logarithmic transfer function based on the supervised backpropagation (BP algorithm is proposed for robustly recognizing low-intensity patterns. Our results show that the trained new ANN can recognize low-fluorescence patterns better than an ANN using the conventional sigmoid function.

Computer-aided system design

Science.gov (United States)

Walker, Carrie K.

1991-01-01

A technique has been developed for combining features of a systems architecture design and assessment tool and a software development tool. This technique reduces simulation development time and expands simulation detail. The Architecture Design and Assessment System (ADAS), developed at the Research Triangle Institute, is a set of computer-assisted engineering tools for the design and analysis of computer systems. The ADAS system is based on directed graph concepts and supports the synthesis and analysis of software algorithms mapped to candidate hardware implementations. Greater simulation detail is provided by the ADAS functional simulator. With the functional simulator, programs written in either Ada or C can be used to provide a detailed description of graph nodes. A Computer-Aided Software Engineering tool developed at the Charles Stark Draper Laboratory (CSDL CASE) automatically generates Ada or C code from engineering block diagram specifications designed with an interactive graphical interface. A technique to use the tools together has been developed, which further automates the design process.

Rendering Systems Visible for Design: Synthesis Maps as Constructivist Design Narratives

Directory of Open Access Journals (Sweden)

Peter Jones

Full Text Available Synthesis maps integrate research evidence, system expertise, and design proposals into visual narratives. These narratives support communication and decision-making among stakeholders. Synthesis maps evolved from earlier visualization tools in systemics and design. They help stakeholders to understand design options for complex sociotechnical systems. Other visual approaches map complexity for effective collaboration across perspectives and knowledge domains. These help stakeholder groups to work in higher-order design contexts for sociotechnical or human-ecological systems. This article describes a constructivist pedagogy for collaborative learning in small teams of mixed-discipline designers. Synthesis mapping enables these teams to learn systems methods for design research in complex problem domains. Synthesis maps integrate knowledge from research cycles and iterative sensemaking to define a coherent design narrative. While synthesis maps may include formal system modeling techniques, they do not require them. Synthesis maps tangibly render research observations and design choices. As a hybrid system design method, synthesis maps are a contribution to the design genre of visual systems thinking.

Product System Design – to Household Massage Design as An Example

Directory of Open Access Journals (Sweden)

Wang Huabin

2016-01-01

Full Text Available Explain what is the system design and the applications of System design in the product design process. Using The whole idea and systems design methods to analyze the design of household hand massage，Use a chart image to explain that Household hand massage products in the influence of user and the environment, the influence of large system environment for the product. The use of components of the system to anatomy product design. Each system components has a link between and mutual correlation.

MOD/R : A knowledge assisted approach towards top-down only CMOS VLSI design

NARCIS (Netherlands)

Spaanenburg, L.; Beunder, M.; Beune, F.A.; Gerez, Sabih H.; Holstein, B.; Luchtmeyer, R.C.C.; Smit, Jaap; van der Werf, A.; Willems, H.

1985-01-01

MOD/R models all views on the design space in relations. This is achieved by eliminating the package constraints, as are apparent in PCB oriented hardware description languages. Assisted by knowledge engineering it allows for a top-down, mostly hierarchical decomposition, virtually eliminating the

Resilient computer system design

CERN Document Server

Castano, Victor

2015-01-01

This book presents a paradigm for designing new generation resilient and evolving computer systems, including their key concepts, elements of supportive theory, methods of analysis and synthesis of ICT with new properties of evolving functioning, as well as implementation schemes and their prototyping. The book explains why new ICT applications require a complete redesign of computer systems to address challenges of extreme reliability, high performance, and power efficiency. The authors present a comprehensive treatment for designing the next generation of computers, especially addressing safety-critical, autonomous, real time, military, banking, and wearable health care systems.   §  Describes design solutions for new computer system - evolving reconfigurable architecture (ERA) that is free from drawbacks inherent in current ICT and related engineering models §  Pursues simplicity, reliability, scalability principles of design implemented through redundancy and re-configurability; targeted for energy-,...

Switched-capacitor techniques for high-accuracy filter and ADC design

NARCIS (Netherlands)

Quinn, P.J.; Roermund, van A.H.M.

2007-01-01

Switched capacitor (SC) techniques are well proven to be excellent candidates for implementing critical analogue functions with high accuracy, surpassing other analogue techniques when embedded in mixed-signal CMOS VLSI. Conventional SC circuits are primarily limited in accuracy by a) capacitor

Fundamentals of electronic systems design

CERN Document Server

Lienig, Jens

2017-01-01

This textbook covers the design of electronic systems from the ground up, from drawing and CAD essentials to recycling requirements. Chapter by chapter, it deals with the challenges any modern system designer faces: the design process and its fundamentals, such as technical drawings and CAD, electronic system levels, assembly and packaging issues and appliance protection classes, reliability analysis, thermal management and cooling, electromagnetic compatibility (EMC), all the way to recycling requirements and environmental-friendly design principles. Enables readers to face various challenges of designing electronic systems, including coverage from various engineering disciplines; Written to be accessible to readers of varying backgrounds; Uses illustrations extensively to reinforce fundamental concepts; Organized to follow essential design process, although chapters are self-contained and can be read in any order.

A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

Science.gov (United States)

Zou, Liang; Fu, Zhuang; Zhao, YanZheng; Yang, JunYan

2010-07-01

This paper proposes a kind of pipelined electric circuit architecture implemented in FPGA, a very large scale integrated circuit (VLSI), which efficiently deals with the real time non-uniformity correction (NUC) algorithm for infrared focal plane arrays (IRFPA). Dual Nios II soft-core processors and a DSP with a 64+ core together constitute this image system. Each processor undertakes own systematic task, coordinating its work with each other's. The system on programmable chip (SOPC) in FPGA works steadily under the global clock frequency of 96Mhz. Adequate time allowance makes FPGA perform NUC image pre-processing algorithm with ease, which has offered favorable guarantee for the work of post image processing in DSP. And at the meantime, this paper presents a hardware (HW) and software (SW) co-design in FPGA. Thus, this systematic architecture yields an image processing system with multiprocessor, and a smart solution to the satisfaction with the performance of the system.

Integrated design for space transportation system

CERN Document Server

Suresh, B N

2015-01-01

The book addresses the overall integrated design aspects of a space transportation system involving several disciplines like propulsion, vehicle structures, aerodynamics, flight mechanics, navigation, guidance and control systems, stage auxiliary systems, thermal systems etc. and discusses the system approach for design, trade off analysis, system life cycle considerations, important aspects in mission management, the risk assessment, etc. There are several books authored to describe the design aspects of various areas, viz., propulsion, aerodynamics, structures, control, etc., but there is no book which presents space transportation system (STS) design in an integrated manner. This book attempts to fill this gap by addressing systems approach for STS design, highlighting the integrated design aspects, interactions between various subsystems and interdependencies. The main focus is towards the complex integrated design to arrive at an optimum, robust and cost effective space transportation system. The orbit...

The VLSI design of the sub-band filterbank in MP3 decoding

Science.gov (United States)

Liu, Jia-Xin; Luo, Li

2018-03-01

The sub-band filterbank is one of the most important modules which has the largest amount of calculation in MP3 decoding. In order to save CPU resources and integrate the sub-band filterbank part into MP3 IP core, the hardware circuit of the sub-band filterbank module is designed in this paper. A fast algorithm suit for hardware implementation is proposed and achieved on FPGA development board. The results show that the sub-band filterbank function is correct in the case of using very few registers and the amount of calculation and ROM resources are reduced greatly.

FPGA-based multimodal embedded sensor system integrating low- and mid-level vision.

Science.gov (United States)

Botella, Guillermo; Martín H, José Antonio; Santos, Matilde; Meyer-Baese, Uwe

2011-01-01

Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI) using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments) in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms.

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints

Science.gov (United States)

Yu, Thomas Edison; Yoneda, Tomokazu; Zhao, Danella; Fujiwara, Hideo

The rapid advancement of VLSI technology has made it possible for chip designers and manufacturers to embed the components of a whole system onto a single chip, called System-on-Chip or SoC. SoCs make use of pre-designed modules, called IP-cores, which provide faster design time and quicker time-to-market. Furthermore, SoCs that operate at multiple clock domains and very low power requirements are being utilized in the latest communications, networking and signal processing devices. As a result, the testing of SoCs and multi-clock domain embedded cores under power constraints has been rapidly gaining importance. In this research, a novel method for designing power-aware test wrappers for embedded cores with multiple clock domains is presented. By effectively partitioning the various clock domains, we are able to increase the solution space of possible test schedules for the core. Since previous methods were limited to concurrently testing all the clock domains, we effectively remove this limitation by making use of bandwidth conversion, multiple shift frequencies and properly gating the clock signals to control the shift activity of various core logic elements. The combination of the above techniques gains us greater flexibility when determining an optimal test schedule under very tight power constraints. Furthermore, since it is computationally intensive to search the entire expanded solution space for the possible test schedules, we propose a heuristic 3-D bin packing algorithm to determine the optimal wrapper architecture and test schedule while minimizing the test time under power and bandwidth constraints.

Internet based remote cooperative engineering system for NSSS system design

International Nuclear Information System (INIS)

Kim, Y. S.; Lee, S. L.

2000-01-01

Implementation of information technology system through the nuclear power plant life cycle which covers site selection, design, construction, operation and decommission has been suggested continually by the reports or guidelines from NIRMA, INPO, NUMARC, USNRC and EPRI since late 1980's, and some of it has been actually implemented and applied partially to the practical design process. However, for the NSSS system design, a high level activity of nuclear power plant design phase, none of the effects has been reported with regard to implementing the information system. In Korea, KAERI studied NuIDEAS(Nuclear Integrated Database and Design Advancement System) in 1995, and KAERI (Korea Electric Power Research Institute) worked with CENP (Combustion Engineering Nuclear Power) for KNGR IMS(Information Management System) in 1997 as trials to adopt information system for NSSS system design. In this paper, after reviewing the pre-studied two information system, we introduce implementation of the information system for NSSS system design which is compatible with the on-going design works and can be used as means of concurrent engineering through internet. With this electronic design system, we expect increase of the design efficiency and productivity by switching from hard copy based design flow to internet based system. In addition, reliability and traceability of the design data is highly elevated by containing the native document file together with all the review, comment and resolution history in one database

CHICSi--a compact ultra-high vacuum compatible detector system for nuclear reaction experiments at storage rings. III. readout system

Energy Technology Data Exchange (ETDEWEB)

Carlen, L.; Foerre, G.; Golubev, P.; Jakobsson, B. E-mail: bo.jakobsson@kosufy.lu.se; Kolozhvari, A.; Marciniewski, P.; Siwek, A.; Veldhuizen, E.J. van; Westerberg, L.; Whitlow, H.J.; Oestby, J.M

2004-01-11

(CHICSi) Celsius Heavy Ion Collaboration Si detector system is a high granularity, modular detector telescope array for operation around the cluster-jet target/circulating beam intersection of the CELSIUS storage ring at the The. Svedberg Laboratory in Uppsala, Sweden. It is able to provide identity and momentum vector of up to 100 charged particles and fragments from proton-nucleus and nucleus-nucleus collisions at intermediate energies, 50-1000A MeV. All detector telescopes as well as the major part of electronic readout system are placed inside the target chamber in ultra-high vacuum (UHV, 10{sup -9}-10{sup -7} Pa). This requires Very Large Scale Integrated (VLSI) microchip for the spectroscopic signal processing and the generation and transport of digital control signals. Eighteen telescopes, read out with chip-on-board technique by ceramics Mother Boards (MB) and corresponding 18 microchips are mounted on a 450x45 mm{sup 2} Grand Mother Board (GMB), processed on FR4 glass-fibre material. Each of these 28 GMB units contains a daisy-chain organisation of the VLSI chips and associated protection circuits. Analogue-to-digital conversion of the spectroscopic signals is performed on a board outside the chamber which is connected on one side to a power distribution board, directly attached to a UHV mounting flange, and on the other side to the VME-based data acquisition system (CHICSiDAQ). This in its turn is connected via a fibre-optic link to the general TSL acquisition system (SVEDAQ), and in this way data from auxiliary detector systems, read out in CAMAC mode, can be stored in coincidence with CHICSi data.

CHICSi--a compact ultra-high vacuum compatible detector system for nuclear reaction experiments at storage rings. III. readout system

International Nuclear Information System (INIS)

Carlen, L.; Foerre, G.; Golubev, P.; Jakobsson, B.; Kolozhvari, A.; Marciniewski, P.; Siwek, A.; Veldhuizen, E.J. van; Westerberg, L.; Whitlow, H.J.; Oestby, J.M.

2004-01-01

(CHICSi) Celsius Heavy Ion Collaboration Si detector system is a high granularity, modular detector telescope array for operation around the cluster-jet target/circulating beam intersection of the CELSIUS storage ring at the The. Svedberg Laboratory in Uppsala, Sweden. It is able to provide identity and momentum vector of up to 100 charged particles and fragments from proton-nucleus and nucleus-nucleus collisions at intermediate energies, 50-1000A MeV. All detector telescopes as well as the major part of electronic readout system are placed inside the target chamber in ultra-high vacuum (UHV, 10 -9 -10 -7 Pa). This requires Very Large Scale Integrated (VLSI) microchip for the spectroscopic signal processing and the generation and transport of digital control signals. Eighteen telescopes, read out with chip-on-board technique by ceramics Mother Boards (MB) and corresponding 18 microchips are mounted on a 450x45 mm 2 Grand Mother Board (GMB), processed on FR4 glass-fibre material. Each of these 28 GMB units contains a daisy-chain organisation of the VLSI chips and associated protection circuits. Analogue-to-digital conversion of the spectroscopic signals is performed on a board outside the chamber which is connected on one side to a power distribution board, directly attached to a UHV mounting flange, and on the other side to the VME-based data acquisition system (CHICSiDAQ). This in its turn is connected via a fibre-optic link to the general TSL acquisition system (SVEDAQ), and in this way data from auxiliary detector systems, read out in CAMAC mode, can be stored in coincidence with CHICSi data

Unattended Monitoring System Design Methodology

International Nuclear Information System (INIS)

Drayer, D.D.; DeLand, S.M.; Harmon, C.D.; Matter, J.C.; Martinez, R.L.; Smith, J.D.

1999-01-01

A methodology for designing Unattended Monitoring Systems starting at a systems level has been developed at Sandia National Laboratories. This proven methodology provides a template that describes the process for selecting and applying appropriate technologies to meet unattended system requirements, as well as providing a framework for development of both training courses and workshops associated with unattended monitoring. The design and implementation of unattended monitoring systems is generally intended to respond to some form of policy based requirements resulting from international agreements or domestic regulations. Once the monitoring requirements are established, a review of the associated process and its related facilities enables identification of strategic monitoring locations and development of a conceptual system design. The detailed design effort results in the definition of detection components as well as the supporting communications network and data management scheme. The data analyses then enables a coherent display of the knowledge generated during the monitoring effort. The resultant knowledge is then compared to the original system objectives to ensure that the design adequately addresses the fundamental principles stated in the policy agreements. Implementation of this design methodology will ensure that comprehensive unattended monitoring system designs provide appropriate answers to those critical questions imposed by specific agreements or regulations. This paper describes the main features of the methodology and discusses how it can be applied in real world situations

Embedded systems design with special arithmetic and number systems

CERN Document Server

Sousa, Leonel; Chang, Chip-Hong

2017-01-01

This book introduces readers to alternative approaches to designing efficient embedded systems using unconventional number systems. The authors describe various systems that can be used for designing efficient embedded and application-specific processors, such as Residue Number System, Logarithmic Number System, Redundant Binary Number System Double-Base Number System, Decimal Floating Point Number System and Continuous Valued Number System. Readers will learn the strategies and trade-offs of using unconventional number systems in application-specific processors and be able to apply and design appropriate arithmetic operations from these number systems to boost the performance of digital systems. • Serves as a single-source reference to designing embedded systems with unconventional number systems • Covers theory as well as implementation on application-specific processors • Explains mathematical concepts in a manner accessible to readers with diverse backgrounds.

Increasing Update Rates in the Building Walkthrough System with Automatic Model-Space Subdivision and Potentially Visible Set Calculations

Science.gov (United States)

1990-07-01

34 ACM Computing Surveys. 6(1): 1- 55. [Syzmanski85] Syzmanski, T. G. and C. J. V. Wyk. (1985). " GOALIE : A Space Efficient System for VLSI Artwork...this. Essentially we initialize a stack with the root. We then pull an element of this stack and if it is a cell we run the occlusion operation on the

Issues in holistic system design

DEFF Research Database (Denmark)

Lawall, Julia L.; Probst, Christian W.; Schultz, Ulrik Pagh

2006-01-01

The coordination of layers in computer and software systems is one of the main challenges in designing such systems today. In this paper we consider Holistic System Design as a way of integrating requirements and facilities of different system layers. We also discuss some of the challenges...

The data acquisition system for SLD

International Nuclear Information System (INIS)

Sherden, D.J.

1986-10-01

This paper describes the data acquisition system planned for the SLD detector, which is being constructed for use with the SLAC Linear Collider (SLC). Analog electronics, heavily incorporating hybrid and custom VLSI circuitry, is mounted on the detector itself. Extensive use is made of multiplexing through optical fibers to a FASTBUS readout system. The low repetition rate of the SLC allows a relatively simple software-based trigger. Hardware and software processors within the acquisition modules are used to reduce the large volume of data per event and to calibrate the electronics. A farm of microprocessors is used for full reconstruction of a sample of events prior to transmission to the host

An intelligent interlock design support system

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Kamiyama, Masahiko

1990-01-01

This paper presents an intelligent interlock design support system, called Handy. BWR plant interlocks have been designed on a conventional CAD system operating on a mini-computer based time sharing system. However, its ability to support interlock designers is limited, mainly due to the system not being capable of manipulating the interlock logic. Handy improves the design efficiency with consistent manipulation of the logic and drawings, interlock simulation, versatile database management, object oriented user interface, high resolution high speed graphics, and automatic interlock outlining with a design support expert system. Handy is now being tested by designers, and is expected to greatly contribute to their efficiency. (author)

Distributed System Design Checklist

Science.gov (United States)

Hall, Brendan; Driscoll, Kevin

2014-01-01

This report describes a design checklist targeted to fault-tolerant distributed electronic systems. Many of the questions and discussions in this checklist may be generally applicable to the development of any safety-critical system. However, the primary focus of this report covers the issues relating to distributed electronic system design. The questions that comprise this design checklist were created with the intent to stimulate system designers' thought processes in a way that hopefully helps them to establish a broader perspective from which they can assess the system's dependability and fault-tolerance mechanisms. While best effort was expended to make this checklist as comprehensive as possible, it is not (and cannot be) complete. Instead, we expect that this list of questions and the associated rationale for the questions will continue to evolve as lessons are learned and further knowledge is established. In this regard, it is our intent to post the questions of this checklist on a suitable public web-forum, such as the NASA DASHLink AFCS repository. From there, we hope that it can be updated, extended, and maintained after our initial research has been completed.

Remote Systems Design & Deployment

Energy Technology Data Exchange (ETDEWEB)

Bailey, Sharon A.; Baker, Carl P.; Valdez, Patrick LJ

2009-08-28

The Pacific Northwest National Laboratory (PNNL) was tasked by Washington River Protection Solutions, LLC (WRPS) to provide information and lessons learned relating to the design, development and deployment of remote systems, particularly remote arm/manipulator systems. This report reflects PNNL’s experience with remote systems and lays out the most important activities that need to be completed to successfully design, build, deploy and operate remote systems in radioactive and chemically contaminated environments. It also contains lessons learned from PNNL’s work experiences, and the work of others in the national laboratory complex.

Systems design for remote healthcare

CERN Document Server

Bonfiglio, Silvio

2014-01-01

This book provides a multidisciplinary overview of the design and implementation of systems for remote patient monitoring and healthcare. Readers are guided step-by-step through the components of such a system and shown how they could be integrated in a coherent framework for deployment in practice. The authors explain planning from subsystem design to complete integration and deployment, given particular application constraints. Readers will benefit from descriptions of the clinical requirements underpinning the entire application scenario, physiological parameter sensing techniques, information processing approaches and overall, application dependent system integration. Each chapter ends with a discussion of practical design challenges and two case studies are included to provide practical examples and design methods for two remote healthcare systems with different needs. ·         Provides a multi-disciplinary overview of next-generation mobile healthcare system design; ·         Includes...

Embedded Systems Design with FPGAs

CERN Document Server

Pnevmatikatos, Dionisios; Sklavos, Nicolas

2013-01-01

This book presents methodologies for modern applications of embedded systems design, using field programmable gate array (FPGA) devices.  Coverage includes state-of-the-art research from academia and industry on a wide range of topics, including advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration and applications. Describes a variety of methodologies for modern embedded systems design;  Implements methodologies presented on FPGAs; Covers a wide variety of applications for reconfigurable embedded systems, including Bioinformatics, Communications and networking, Application acceleration, Medical solutions, Experiments for high energy physics, Astronomy, Aerospace, Biologically inspired systems and Computational fluid dynamics (CFD).

A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory.

Science.gov (United States)

Chicca, E; Badoni, D; Dante, V; D'Andreagiovanni, M; Salina, G; Carota, L; Fusi, S; Del Giudice, P

2003-01-01

Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in the electronic network.

System 80+trademark Standard Design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report, entitled Combustion Engineering Standard Safety Analysis Report - Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describe the Combustion Engineering, Inc. System 80+trademark Standard Design. This Volume 16 details the application of Human Factors Engineering in the design process

Modular system design and evaluation

CERN Document Server

Levin, Mark Sh

2015-01-01

This book examines seven key combinatorial engineering frameworks (composite schemes consisting of algorithms and/or interactive procedures) for hierarchical modular (composite) systems. These frameworks are based on combinatorial optimization problems (e.g., knapsack problem, multiple choice problem, assignment problem, morphological clique problem), with the author’s version of morphological design approach – Hierarchical Morphological Multicritieria Design (HMMD) – providing a conceptual lens with which to elucidate the examples discussed. This approach is based on ordinal estimates of design alternatives for systems parts/components, however, the book also puts forward an original version of HMMD that is based on new interval multiset estimates for the design alternatives with special attention paid to the aggregation of modular solutions (system versions). The second part of ‘Modular System Design and Evaluation’ provides ten information technology case studies that enriches understanding of th...

Preliminary System Design of the SWRL Financial System.

Science.gov (United States)

Ikeda, Masumi

The preliminary system design of the computer-based Southwest Regional Laboratory's (SWRL) Financial System is outlined. The system is designed to produce various management and accounting reports needed to maintain control of SWRL operational and financial activities. Included in the document are descriptions of the various types of system…

Physical protection system design and evaluation

International Nuclear Information System (INIS)

Williams, J.D.

1997-01-01

The design of an effective physical protection system includes the determination of physical protection system objectives, initial design of a physical protection system, design evaluation, and probably a redesign or refinement. To develop the objectives, the designer must begin by gathering information about facility operation and conditions, such as a comprehensive description of the facility, operating conditions, and the physical protection requirements. The designer then needs to define the threat. This involves considering factors about potential adversaries: class of adversary, adversary's capabilities, and range of adversary's tactics. Next, the designer should identify targets. Determination of whether or not the materials being protected are attractive targets is based mainly on the ease or difficulty of acquisition and desirability of the material. The designer now knows the objectives of the physical protection system, that is, open-quotes what to protect against whom.close quotes The next step is to design the system by determining how best to combine such elements as fences, vaults, sensors and assessment devices, entry control elements, procedures, communication devices, and protective forces personnel to meet the objectives of the system. Once a physical protection system is designed, it must be analyzed and evaluated to ensure it meets the physical protection objectives. Evaluation must allow for features working together to ensure protection rather than regarding each feature separately. Due to the complexity of the protection systems, an evaluation usually requires modeling techniques. If any vulnerabilities are found, the initial system must be redesigned to correct the vulnerabilities and a reevaluation conducted. This paper reviews the physical protection system design and methodology mentioned above. Examples of the steps required and a brief introduction to some of the technologies used in modem physical protections system are given

Selective Attention in Multi-Chip Address-Event Systems

Directory of Open Access Journals (Sweden)

Giacomo Indiveri

2009-06-01

Full Text Available Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the “Selective Attention Chip” (SAC, which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

Selective attention in multi-chip address-event systems.

Science.gov (United States)

Bartolozzi, Chiara; Indiveri, Giacomo

2009-01-01

Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the "Selective Attention Chip" (SAC), which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

Process of system design and analysis

International Nuclear Information System (INIS)

Gardner, B.

1995-01-01

The design of an effective physical protection system includes the determination of the physical protection system objectives, the initial design of a physical protection system, the evaluation of the design, and, probably, a redesign or refinement of the system. To develop the objectives, the designer must begin by gathering information about facility operations and conditions, such as a comprehensive description of the facility, operating states, and the physical protection requirements. The designer then needs to define the threat. This involves considering factors about potential adversaries: Class of adversary, adversary's capabilities, and range of adversary's tactics. Next, the designer should identify targets. Determination of whether or not nuclear materials are attractive targets is based mainly on the ease or difficulty of acquisition and desirability of the materiaL The designer now knows the objectives of the physical protection system, that is, ''What to protect against whom.'' The next step is to design the system by determining how best to combine such elements as fences, vaults, sensors, procedures, communication devices, and protective force personnel to meet the objectives of the system. Once a physical protection system is designed, it must be analyzed and evaluated to ensure it meets the physical protection objectives. Evaluation must allow for features working together to assure protection rather than regarding each feature separately. Due to the complexity of protection systems, an evaluation usually requires modeling techniques. If any vulnerabilities are found, the initial system must be redesigned to correct the vulnerabilities and a reevaluation conducted

Clothing Systems Design Lab

Data.gov (United States)

Federal Laboratory Consortium — The Clothing Systems Design Lab houses facilities for the design and rapid prototyping of military protective apparel.Other focuses include: creation of patterns and...

Preliminary design review: Brayton Isotope Power System

International Nuclear Information System (INIS)

The design aspects covered include flight system design, design criteria/margins/reliability, GDS design, system analysis, materials, system assembly procedure, and government furnished equipment-BTPS

Multidisciplinary systems engineering architecting the design process

CERN Document Server

Crowder, James A; Demijohn, Russell

2016-01-01

This book presents Systems Engineering from a modern, multidisciplinary engineering approach, providing the understanding that all aspects of systems design, systems, software, test, security, maintenance and the full life-cycle must be factored in to any large-scale system design; up front, not factored in later. It lays out a step-by-step approach to systems-of-systems architectural design, describing in detail the documentation flow throughout the systems engineering design process. It provides a straightforward look and the entire systems engineering process, providing realistic case studies, examples, and design problems that will enable students to gain a firm grasp on the fundamentals of modern systems engineering.  Included is a comprehensive design problem that weaves throughout the entire text book, concluding with a complete top-level systems architecture for a real-world design problem.

System 80+trademark Standard Design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report, entitled Combustion Engineering Standard Safety Analysis Report -- Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describe the Combustion Engineering, Inc. System 80+trademark Standard Design. This Volume 18 provides Appendix B, Probabilistic Risk Assessment

System 80+trademark Standard Design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report, entitled Combustion Engineering Standard Safety Analysis Report -- Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describe the Combustion Engineering, Inc. System 80 + trademark Standard Design. This volume 8 provides a description of instrumentation and controls

Design Process-System and Methodology of Design Research

Science.gov (United States)

Bashier, Fathi

2017-10-01

Studies have recognized the failure of the traditional design approach both in practice and in the studio. They showed that design problems today are too complex for the traditional approach to cope with and reflected a new interest in a better quality design services in order to meet the challenges of our time. In the mid-1970s and early 1980s, there has been a significant shift in focus within the field of design research towards the aim of creating a ‘design discipline’. The problem, as will be discussed, is the lack of an integrated theory of design knowledge that can explicitly describe the design process in a coherent way. As a consequence, the traditional approach fails to operate systematically, in a disciplinary manner. Addressing this problem is the primary goal of the research study in the design process currently being conducted in the research-based master studio at Wollega University, Ethiopia. The research study seeks to make a contribution towards a disciplinary approach, through proper understanding the mechanism of knowledge development within design process systems. This is the task of the ‘theory of design knowledge’. In this article the research project is introduced, and a model of the design process-system is developed in the studio as a research plan and a tool of design research at the same time. Based on data drawn from students’ research projects, the theory of design knowledge is developed and empirically verified through the research project.

System 80+trademark standard design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report has been prepared in support of the industry effort to standardize nuclear plant designs. The documents in this series describe the Combustion Engineering, Inc. System 80+ TM Standard Design

System analysis and design

International Nuclear Information System (INIS)

Son, Seung Hui

2004-02-01

This book deals with information technology and business process, information system architecture, methods of system development, plan on system development like problem analysis and feasibility analysis, cases for system development, comprehension of analysis of users demands, analysis of users demands using traditional analysis, users demands analysis using integrated information system architecture, system design using integrated information system architecture, system implementation, and system maintenance.

SUBSURFACE REPOSITORY INTEGRATED CONTROL SYSTEM DESIGN

International Nuclear Information System (INIS)

Randle, D.C.

2000-01-01

The primary purpose of this document is to develop a preliminary high-level functional and physical control system architecture for the potential repository at Yucca Mountain. This document outlines an overall control system concept that encompasses and integrates the many diverse process and communication systems being developed for the subsurface repository design. This document presents integrated design concepts for monitoring and controlling the diverse set of subsurface operations. The Subsurface Repository Integrated Control System design will be composed of a series of diverse process systems and communication networks. The subsurface repository design contains many systems related to instrumentation and control (I andC) for both repository development and waste emplacement operations. These systems include waste emplacement, waste retrieval, ventilation, radiological and air monitoring, rail transportation, construction development, utility systems (electrical, lighting, water, compressed air, etc.), fire protection, backfill emplacement, and performance confirmation. Each of these systems involves some level of I andC and will typically be integrated over a data communications network throughout the subsurface facility. The subsurface I andC systems will also interface with multiple surface-based systems such as site operations, rail transportation, security and safeguards, and electrical/piped utilities. In addition to the I andC systems, the subsurface repository design also contains systems related to voice and video communications. The components for each of these systems will be distributed and linked over voice and video communication networks throughout the subsurface facility. The scope and primary objectives of this design analysis are to: (1) Identify preliminary system-level functions and interfaces (Section 6.2). (2) Examine the overall system complexity and determine how and on what levels the engineered process systems will be monitored

Investigating how to design for systems through designing a group music improvisation system.

NARCIS (Netherlands)

Hengeveld, B.J.; Frens, J.W.; Funk, M.

2013-01-01

Abstract: In this paper we describe one of our studies aimed at gaining insight in how to design for systems, which we see as the current challenge in industrial design. We observe that the methods, tools and techniques that were developed for ‘traditional’ industrial design and, more recently,

System 80+trademark Standard Design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report, entitled Combustion Engineering Standard Safety Analysis Report -- Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describe the Combustion Engineering, Inc. System 80 + trademark Standard Design. This volume 11 discusses Radiation Protection, Conduct of Operations, and the Initial Test Program

Business System Planning Project, Preliminary System Design

International Nuclear Information System (INIS)

EVOSEVICH, S.

2000-01-01

CH2M HILL Hanford Group, Inc. (CHG) is currently performing many core business functions including, but not limited to, work control, planning, scheduling, cost estimating, procurement, training, and human resources. Other core business functions are managed by or dependent on Project Hanford Management Contractors including, but not limited to, payroll, benefits and pension administration, inventory control, accounts payable, and records management. In addition, CHG has business relationships with its parent company CH2M HILL, U.S. Department of Energy, Office of River Protection and other River Protection Project contractors, government agencies, and vendors. The Business Systems Planning (BSP) Project, under the sponsorship of the CH2M HILL Hanford Group, Inc. Chief Information Officer (CIO), have recommended information system solutions that will support CHG business areas. The Preliminary System Design was developed using the recommendations from the Alternatives Analysis, RPP-6499, Rev 0 and will become the design base for any follow-on implementation projects. The Preliminary System Design will present a high-level system design, providing a high-level overview of the Commercial-Off-The-Shelf (COTS) modules and identify internal and external relationships. This document will not define data structures, user interface components (screens, reports, menus, etc.), business rules or processes. These in-depth activities will be accomplished at implementation planning time

System 80+trademark Standard Design: CESSAR design certification

International Nuclear Information System (INIS)

1990-01-01

This report, entitled Combustion Engineering Standard Safety Analysis Report -- Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describes the Combustion Engineering, Inc. System 80+trademark Standard Design. This Volume 17 provides Appendix A of this report, closure of unresolved and Genetic Safety Issues

System Design and the Safety Basis

International Nuclear Information System (INIS)

Ellingson, Darrel

2008-01-01

The objective of this paper is to present the Bechtel Jacobs Company, LLC (BJC) Lessons Learned for system design as it relates to safety basis documentation. BJC has had to reconcile incomplete or outdated system description information with current facility safety basis for a number of situations in recent months. This paper has relevance in multiple topical areas including documented safety analysis, decontamination and decommissioning (D and D), safety basis (SB) implementation, safety and design integration, potential inadequacy of the safety analysis (PISA), technical safety requirements (TSR), and unreviewed safety questions. BJC learned that nuclear safety compliance relies on adequate and well documented system design information. A number of PIS As and TSR violations occurred due to inadequate or erroneous system design information. As a corrective action, BJC assessed the occurrences caused by systems design-safety basis interface problems. Safety systems reviewed included the Molten Salt Reactor Experiment (MSRE) Fluorination System, K-1065 fire alarm system, and the K-25 Radiation Criticality Accident Alarm System. The conclusion was that an inadequate knowledge of system design could result in continuous non-compliance issues relating to nuclear safety. This was especially true with older facilities that lacked current as-built drawings coupled with the loss of 'historical knowledge' as personnel retired or moved on in their careers. Walkdown of systems and the updating of drawings are imperative for nuclear safety compliance. System design integration with safety basis has relevance in the Department of Energy (DOE) complex. This paper presents the BJC Lessons Learned in this area. It will be of benefit to DOE contractors that manage and operate an aging population of nuclear facilities

A CONCEPT OF SOLAR TRACKER SYSTEM DESIGN

OpenAIRE

Meita Rumbayan *, Muhamad Dwisnanto Putro

2017-01-01

Improvement of solar panel efficiency is an ongoing research work recently. Maximizing the output power by integrating with the solar tracker system becomes a interest point of the research. This paper presents the concept in designing a solar tracker system applied to solar panel. The development of solar panel tracker system design that consist of system display prototype design, hardware design, and algorithm design. This concept is useful as the control system for solar tracker to improve...

Physical protection system design and evaluation

International Nuclear Information System (INIS)

Williams, J.D.

1997-11-01

The design of an effective physical protection system (PPS) includes the determination of the PPS objectives, the initial design of a PPS, the evaluation of the design, and probably, the redesign or refinement of the system. To develop the objectives, the designer must begin by gathering information about facility operation and conditions, such as a comprehensive description of the facility, operating conditions, and the physical protection requirements. The designer then needs to define the threat. This involves considering factors about potential adversaries: class of adversary, adversary's capabilities, and range of adversary's tactics. Next, the designer should identify targets. Determination of whether or not the materials being protected are attractive targets is based mainly on the ease or difficulty of acquisition and desirability of the material. The designer now knows the objectives of the PPS, that is, ''what to protect against whom.'' The next step is to design the system by determining how best to combine such elements as fences, vaults, sensors and assessment devices, entry control devices, communication devices, procedures, and protective force personnel to meet the objectives of the system. Once a PPS is designed, it must be analyzed and evaluated to ensure it meets the PPS objectives. Evaluation must allow for features working together to ensure protection rather than regarding each feature separately. Due to the complexity of the protection systems, an evaluation usually requires modeling techniques. If any vulnerabilities are found, the initial system must be redesigned to correct the vulnerabilities and a reevaluation conducted. After the system is installed, the threat and system parameters may change with time. If they do, the analysis must be performed periodically to ensure the system objectives are still being met

Application and design of solar photovoltaic system

International Nuclear Information System (INIS)

Li Tianze; Lu Hengwei; Jiang Chuan; Hou Luan; Zhang Xia

2011-01-01

Solar modules, power electronic equipments which include the charge-discharge controller, the inverter, the test instrumentation and the computer monitoring, and the storage battery or the other energy storage and auxiliary generating plant make up of the photovoltaic system which is shown in the thesis. PV system design should follow to meet the load supply requirements, make system low cost, seriously consider the design of software and hardware, and make general software design prior to hardware design in the paper. To take the design of PV system for an example, the paper gives the analysis of the design of system software and system hardware, economic benefit, and basic ideas and steps of the installation and the connection of the system. It elaborates on the information acquisition, the software and hardware design of the system, the evaluation and optimization of the system. Finally, it shows the analysis and prospect of the application of photovoltaic technology in outer space, solar lamps, freeways and communications.

Design Rules for Life Support Systems

Science.gov (United States)

Jones, Harry

2002-01-01

This paper considers some of the common assumptions and engineering rules of thumb used in life support system design. One general design rule is that the longer the mission, the more the life support system should use recycling and regenerable technologies. A more specific rule is that, if the system grows more than half the food, the food plants will supply all the oxygen needed for the crew life support. There are many such design rules that help in planning the analysis of life support systems and in checking results. These rules are typically if-then statements describing the results of steady-state, "back of the envelope," mass flow calculations. They are useful in identifying plausible candidate life support system designs and in rough allocations between resupply and resource recovery. Life support system designers should always review the design rules and make quick steady state calculations before doing detailed design and dynamic simulation. This paper develops the basis for the different assumptions and design rules and discusses how they should be used. We start top-down, with the highest level requirement to sustain human beings in a closed environment off Earth. We consider the crew needs for air, water, and food. We then discuss atmosphere leakage and recycling losses. The needs to support the crew and to make up losses define the fundamental life support system requirements. We consider the trade-offs between resupplying and recycling oxygen, water, and food. The specific choices between resupply and recycling are determined by mission duration, presence of in-situ resources, etc., and are defining parameters of life support system design.

Ares I Flight Control System Design

Science.gov (United States)

Jang, Jiann-Woei; Alaniz, Abran; Hall, Robert; Bedrossian, Nazareth; Hall, Charles; Ryan, Stephen; Jackson, Mark

2010-01-01

The Ares I launch vehicle represents a challenging flex-body structural environment for flight control system design. This paper presents a design methodology for employing numerical optimization to develop the Ares I flight control system. The design objectives include attitude tracking accuracy and robust stability with respect to rigid body dynamics, propellant slosh, and flex. Under the assumption that the Ares I time-varying dynamics and control system can be frozen over a short period of time, the flight controllers are designed to stabilize all selected frozen-time launch control systems in the presence of parametric uncertainty. Flex filters in the flight control system are designed to minimize the flex components in the error signals before they are sent to the attitude controller. To ensure adequate response to guidance command, step response specifications are introduced as constraints in the optimization problem. Imposing these constraints minimizes performance degradation caused by the addition of the flex filters. The first stage bending filter design achieves stability by adding lag to the first structural frequency to phase stabilize the first flex mode while gain stabilizing the higher modes. The upper stage bending filter design gain stabilizes all the flex bending modes. The flight control system designs provided here have been demonstrated to provide stable first and second stage control systems in both Draper Ares Stability Analysis Tool (ASAT) and the MSFC 6DOF nonlinear time domain simulation.

Designing a Secure Point-of-Sale System

DEFF Research Database (Denmark)

Sharp, Robin; Pedersen, Allan; Hedegaard, Anders

2006-01-01

This paper describes some experiences with using the ''Common Criteria for Information Security Evaluation'' as the basis for a design methodology when designing secure systems. As an example, the design process for a Point-of-Sale (POS) system is described.......This paper describes some experiences with using the ''Common Criteria for Information Security Evaluation'' as the basis for a design methodology when designing secure systems. As an example, the design process for a Point-of-Sale (POS) system is described....

Design space pruning through hybrid analysis in system-level design space exploration

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2012-01-01

System-level design space exploration (DSE), which is performed early in the design process, is of eminent importance to the design of complex multi-processor embedded system archi- tectures. During system-level DSE, system parameters like, e.g., the number and type of processors, the type and size

Cost Optimal System Identification Experiment Design

DEFF Research Database (Denmark)

Kirkegaard, Poul Henning

A structural system identification experiment design method is formulated in the light of decision theory, structural reliability theory and optimization theory. The experiment design is based on a preposterior analysis, well-known from the classical decision theory. I.e. the decisions concerning...... reflecting the cost of the experiment and the value of obtained additional information. An example concerning design of an experiment for parametric identification of a single degree of freedom structural system shows the applicability of the experiment design method....... the experiment design are not based on obtained experimental data. Instead the decisions are based on the expected experimental data assumed to be obtained from the measurements, estimated based on prior information and engineering judgement. The design method provides a system identification experiment design...

Assessing the 'system' in safe systems-based road designs: using cognitive work analysis to evaluate intersection designs.

Science.gov (United States)

Cornelissen, M; Salmon, P M; Stanton, N A; McClure, R

2015-01-01

While a safe systems approach has long been acknowledged as the underlying philosophy of contemporary road safety strategies, systemic applications are sparse. This article argues that systems-based methods from the discipline of Ergonomics have a key role to play in road transport design and evaluation. To demonstrate, the Cognitive Work Analysis framework was used to evaluate two road designs - a traditional Melbourne intersection and a cut-through design for future intersections based on road safety safe systems principles. The results demonstrate that, although the cut-through intersection appears different in layout from the traditional intersection, system constraints are not markedly different. Furthermore, the analyses demonstrated that redistribution of constraints in the cut-through intersection resulted in emergent behaviour, which was not anticipated and could prove problematic. Further, based on the lack of understanding of emergent behaviour, similar design induced problems are apparent across both intersections. Specifically, incompatibilities between infrastructure, vehicles and different road users were not dealt with by the proposed design changes. The importance of applying systems methods in the design and evaluation of road transport systems is discussed. Copyright © 2013 Elsevier Ltd. All rights reserved.

Turbo decoder architecture for beyond-4G applications

CERN Document Server

Wong, Cheng-Chi

2013-01-01

This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respec

Nonfunctional requirements in systems analysis and design

CERN Document Server

Adams, Kevin MacG

2015-01-01

This book will help readers gain a solid understanding of non-functional requirements inherent in systems design endeavors. It contains essential information for those who design, use, and maintain complex engineered systems, including experienced designers, teachers of design, system stakeholders, and practicing engineers. Coverage approaches non-functional requirements in a novel way by presenting a framework of four systems concerns into which the 27 major non-functional requirements fall: sustainment, design, adaptation, and viability. Within this model, the text proceeds to define each non-functional requirement, to specify how each is treated as an element of the system design process, and to develop an associated metric for their evaluation. Systems are designed to meet specific functional needs. Because non-functional requirements are not directly related to tasks that satisfy these proposed needs, designers and stakeholders often fail to recognize the importance of such attributes as availability, su...

Pressurized water reactor system model for control system design and analysis

International Nuclear Information System (INIS)

Cooper, K.F.; Cain, J.T.

1975-01-01

Satisfactory operation of present generation Pressurized Water Reactor (PWR) Nuclear Power systems requires that several independent and interactive control systems be designed. Since it is not practical to use an actual PWR system as a design tool, a mathematical model of the system must be developed as a design and analysis tool. The model presented has been developed to be used as an aid in applying optimal control theory to design and implement new control systems for PWR plants. To be applicable, the model developed must represent the PWR system in its normal operating range. For safety analysis the operating conditions of the system are usually abnormal and, therefore, the system modeling requirements are different from those for control system design and analysis

Mission-Critical Systems Design Framework

Directory of Open Access Journals (Sweden)

Kyriakos Houliotis

2018-03-01

Full Text Available Safety-critical systems are well documented and standardized (e.g. IEC 61508, RTCA DO-178B within system design cycles. However in Defence and Security, systems that are critical to the success of a Mission are not defined within the literature nor are there any guidelines in defining criticality in their design or operational capabilities. When it comes to Vetronics (Vehicle Electronics, a mission-critical system, is a system with much complexity and mixed criticality levels that is a part of the overall platform (military vehicle offering integrated system capabilities. In this paper, a framework is presented, providing guidelines in designing efficiently and effectively mission-critical systems considering principles of Interoperable Open Architectures (IOA, mission-critical integrity levels and following new standardization activities such as NATO Generic Vehicle Architecture (NGVA. A Defensive Aid Suite (DAS system is used as a case study to illustrate how this framework can be exploited. The indention of this extension is to provide an approach to precisely estimate threats in order to de-risk missions in the very early stages.

Design Technology for Heterogeneous Embedded Systems

CERN Document Server

O'Connor, Ian; Piguet, Christian

2012-01-01

Designing technology to address the problem of heterogeneous embedded systems, while remaining compatible with standard “More Moore” flows, i.e. capable of handling simultaneously both silicon complexity and system complexity, represents one of the most important challenges facing the semiconductor industry today. While the micro-electronics industry has built its own specific design methods to focus mainly on the management of complexity through the establishment of abstraction levels, the emergence of device heterogeneity requires new approaches enabling the satisfactory design of physically heterogeneous embedded systems for the widespread deployment of such systems. This book, compiled largely from a set of contributions from participants of past editions of the Winter School on Heterogeneous Embedded Systems Design Technology (FETCH), proposes a broad and holistic overview of design techniques used to tackle the various facets of heterogeneity in terms of technology and opportunities at the physical ...

Design of object processing systems

NARCIS (Netherlands)

Grigoras, D.R.; Hoede, C.

Object processing systems are met rather often in every day life, in industry, tourism, commerce, etc. When designing such a system, many problems can be posed and considered, depending on the scope and purpose of design. We give here a general approach which involves graph theory, and which can

Design of low noise imaging system

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for low noise imaging system under the mode of global shutter, a complete imaging system is designed based on the SCMOS (Scientific CMOS) image sensor CIS2521F. The paper introduces hardware circuit and software system design. Based on the analysis of key indexes and technologies about the imaging system, the paper makes chips selection and decides SCMOS + FPGA+ DDRII+ Camera Link as processing architecture. Then it introduces the entire system workflow and power supply and distribution unit design. As for the software system, which consists of the SCMOS control module, image acquisition module, data cache control module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The imaging experimental results show that the imaging system exhibits a 2560*2160 pixel resolution, has a maximum frame frequency of 50 fps. The imaging quality of the system satisfies the requirement of the index.

Design Flaws and Service System Breakdowns: Learning from Systems Thinking

Directory of Open Access Journals (Sweden)

David Ing

2014-12-01

Full Text Available In what ways might systems thinking be helpful to designers?  In the 21st century, the types of project with which designers have become engaged has expanded to include service systems.  Service systems are typically composites of mechanisms, organisms, human beings and ecologies.  Systems thinking is a perspective with theories, methods and practices that enables transcending disciplinary boundaries.  Application of systems thinking in designing a service system can aid in surfacing potential flaws and/or anticipating future breakdowns in functions, structures and/or processes. Designers and systems thinkers should work together to improve the nature of service systems.  As a starter set into these conversations, seven conditions are proposed as a starting context.  These conditions are presented neither as rigourously defined nor as exhaustive, but as an entry point into future joint engagement.

Communicating embedded systems software and design

CERN Document Server

Jard, Claude

2013-01-01

The increased complexity of embedded systems coupled with quick design cycles to accommodate faster time-to-market requires increased system design productivity that involves both model-based design and tool-supported methodologies. Formal methods are mathematically-based techniques and provide a clean framework in which to express requirements and models of the systems, taking into account discrete, stochastic and continuous (timed or hybrid) parameters with increasingly efficient tools. This book deals with these formal methods applied to communicating embedded systems by presenting the

Princeton VLSI Project.

Science.gov (United States)

1983-01-01

for otherwise, since sc = xs2 . we would ELIE system. This algorithm also applies to SL) systems have been able to compute zec without looking at block...Prof. Peter R. Cappello of the CompuLer Science Department, University of California, Santa Barbara, I I Im i Ii - 19 - Caiifo:nia. Some of the work...multiple pro- cessors will not be as simple as the MMM ones. Acknowledgments. Several useful ideas and suggestions were made by Jim Gray, Peter Honneyman

Design and qualification of HPD based designs for safety systems

International Nuclear Information System (INIS)

Sharma, Mukesh Kr.; Chavan, Madhavi A.; Sawhney, Pratibha A.; Mohanty, Ashutos; John, Ajith K.; Ganesh, G.

2014-01-01

Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) are increasingly being used in C and I system of NPPs. The function of such an integrated circuit is not defined by the supplier of the physical component or micro-electronic technology but by the C and I designer. The hardware subsystems implemented in these devices typically use Hardware Description Language (HDL) like VHDL or Verilog to describe the functionality at the design entry level. These circuits are commonly known as 'HDL-Programmed Devices', (HPD). RCnD has developed a set of hardware boards to be used in next generation C and I systems. The boards have been designed based on present day technology and components. The intelligence of these boards has been implemented in HPDs (FPGA/CPLD) using VHDL. Since these boards are used in the safety and safety related systems, they have undergone a rigorous V and V process and qualification tests. This paper discusses the design attributes and qualification of these HPD based designs for nuclear class safety systems. (author)

Designing Systems for E-Commerce

OpenAIRE

Shona Leitch; Matthew Warren

2003-01-01

Ethics is an important element in all aspects of computing, but proves to be a real problem in the development and delivery of E-Commerce systems. There are many aspects of ethics that can affect E-Commerce systems, but often research is focused on the ethics after the E-Commerce system has been implemented, focusing on issues such as trust, privacy and disclosure. This paper will discuss how ethical matters can affect the design of E-Commerce systems and how a framework designed for E-Com...

Development of a computer design system for HVAC

International Nuclear Information System (INIS)

Miyazaki, Y.; Yotsuya, M.; Hasegawa, M.

1993-01-01

The development of a computer design system for HVAC (Heating, Ventilating and Air Conditioning) system is presented in this paper. It supports the air conditioning design for a nuclear power plant and a reprocessing plant. This system integrates various computer design systems which were developed separately for the various design phases of HVAC. the purposes include centralizing the HVAC data, optimizing design, and reducing the designing time. The centralized HVAC data are managed by a DBMS (Data Base Management System). The DBMS separates the computer design system into a calculation module and the data. The design system can thus be expanded easily in the future. 2 figs

Software Design Methods for Real-Time Systems

Science.gov (United States)

1989-12-01

This module describes the concepts and methods used in the software design of real time systems . It outlines the characteristics of real time systems , describes...the role of software design in real time system development, surveys and compares some software design methods for real - time systems , and

Designing Systems for E-Commerce

Directory of Open Access Journals (Sweden)

Shona Leitch

2003-05-01

Full Text Available Ethics is an important element in all aspects of computing, but proves to be a real problem in the development and delivery of E-Commerce systems. There are many aspects of ethics that can affect E-Commerce systems, but often research is focused on the ethics after the E-Commerce system has been implemented, focusing on issues such as trust, privacy and disclosure. This paper will discuss how ethical matters can affect the design of E-Commerce systems and how a framework designed for E-Commerce can be used to create and deliver effective, ethical E-Commerce systems.

Introduction to thermo-fluids systems design

CERN Document Server

Garcia McDonald, André

2012-01-01

A fully comprehensive guide to thermal systems design covering fluid dynamics, thermodynamics, heat transfer and thermodynamic power cycles Bridging the gap between the fundamental concepts of fluid mechanics, heat transfer and thermodynamics, and the practical design of thermo-fluids components and systems, this textbook focuses on the design of internal fluid flow systems, coiled heat exchangers and performance analysis of power plant systems. The topics are arranged so that each builds upon the previous chapter to convey to the reader that topics are not stand-alone i

Parametric design and off-design analysis of organic Rankine cycle (ORC) system

International Nuclear Information System (INIS)

Song, Jian; Gu, Chun-wei; Ren, Xiaodong

2016-01-01

Highlights: • A one-dimensional analysis method for ORC system is proposed. • The system performance under both design and off-design conditions are analyzed. • The working fluid selection is based on both design and off-design performance. • The system parameter determination are based on both design and off-design performance. - Abstract: A one-dimensional analysis method has been proposed for the organic Rankine cycle (ORC) system in this paper. The method contains two main parts: a one-dimensional aerodynamic analysis model of the radial-inflow turbine and a performance prediction model of the heat exchanger. Based on the present method, an ORC system for the industrial waste heat recovery is designed and analyzed. The net power output of the ORC system is 534 kW, and the thermal efficiency reaches 13.5%. System performance under off-design conditions is simulated and considered. The results show that the inlet temperatures of the heat source and the cooling water have a significant influence on the system. With the increment of the heat source inlet temperature, the mass flow rate of the working fluid, the net power output and the heat utilization ratio of the ORC system increase. While, the system thermal efficiency decreases with increasing cooling water inlet temperature. In order to maintain the condensation pressure at a moderate value, the heat source inlet temperature considered in this analysis should be kept within the range of 443.15–468.15 K, while the optimal temperature range of the cooling water is between 283.15 K and 303.15 K.

Conceptual design of small-sized HTGR system (1). Major specifications and system designs

International Nuclear Information System (INIS)

Ohashi, Hirofumi; Sato, Hiroyuki; Tazawa, Yujiro; Yan, Xing L.; Tachibana, Yukio

2011-06-01

Japan Atomic Energy Agency (JAEA) has started a conceptual design of a 50MWt small-sized high temperature gas cooled reactor (HTGR) for steam supply and electricity generation (HTR50S), which is a first-of-kind of the commercial plant or a demonstration plant of a small-sized HTGR system for steam supply to the industries and district heating and electricity generation by a steam turbine, to deploy in developing countries in the 2030s. The design philosophy is that the HTR50S is a high advanced reactor, which is reducing the R and D risk based on the HTTR design, upgrading the performance and reducing the cost for commercialization by utilizing the knowledge obtained by the HTTR operation and the GTHTR300 design. The major specifications of the HTR50S were determined and targets of the technology demonstration using the HTR50S (e.g., the increasing the power density, reduction of the number of uranium enrichment in the fuel, increasing the burn up, side-by-side arrangement between the reactor pressure vessel and the steam generator) were identified. In addition, the system design of HTR50S, which offers the capability of electricity generation, cogeneration of electricity and steam for a district heating and industries, was performed. Furthermore, a market size of small-sized HTGR systems was investigated. (author)

Real-time systems design and analysis

CERN Document Server

Laplante, Phillip A

2004-01-01

"Real-Time Systems Design and Analysis, Third Edition is essential for students and practicing software engineers who want improved designs, faster computation, and ultimate cost savings. Chapters discuss hardware considerations and software requirements, software systems design, the software production process, performance estimation and optimization, and engineering considerations."--Jacket.

Accelerating Science Driven System Design With RAMP

Energy Technology Data Exchange (ETDEWEB)

Wawrzynek, John [Univ. of California, Berkeley, CA (United States)

2015-05-01

Researchers from UC Berkeley, in collaboration with the Lawrence Berkeley National Lab, are engaged in developing an Infrastructure for Synthesis with Integrated Simulation (ISIS). The ISIS Project was a cooperative effort for “application-driven hardware design” that engages application scientists in the early parts of the hardware design process for future generation supercomputing systems. This project served to foster development of computing systems that are better tuned to the application requirements of demanding scientific applications and result in more cost-effective and efficient HPC system designs. In order to overcome long conventional design-cycle times, we leveraged reconfigurable devices to aid in the design of high-efficiency systems, including conventional multi- and many-core systems. The resulting system emulation/prototyping environment, in conjunction with the appropriate intermediate abstractions, provided both a convenient user programming experience and retained flexibility, and thus efficiency, of a reconfigurable platform. We initially targeted the Berkeley RAMP system (Research Accelerator for Multiple Processors) as that hardware emulation environment to facilitate and ultimately accelerate the iterative process of science-driven system design. Our goal was to develop and demonstrate a design methodology for domain-optimized computer system architectures. The tangible outcome is a methodology and tools for rapid prototyping and design-space exploration, leading to highly optimized and efficient HPC systems.

46 CFR 153.280 - Piping system design.

Science.gov (United States)

2010-10-01

... 46 Shipping 5 2010-10-01 2010-10-01 false Piping system design. 153.280 Section 153.280 Shipping... BULK LIQUID, LIQUEFIED GAS, OR COMPRESSED GAS HAZARDOUS MATERIALS Design and Equipment Piping Systems and Cargo Handling Equipment § 153.280 Piping system design. (a) Each cargo piping system must meet...

CHICSi - a compact ultra-high vacuum compatible detector system for nuclear reaction experiments at storage rings. I. General structure, mechanics and UHV compatibility

International Nuclear Information System (INIS)

Westerberg, L.; Avdeichikov, V.; Carlen, L.; Golubev, P.; Jakobsson, B.; Rouki, C.; Siwek, A.; Veldhuizen, E.J. van; Whitlow, H.J.

2003-01-01

CELSIUS Heavy-Ion Collision Silicon detector system (CHICSi) is a large solid angle, barrel-shaped detector system, housing up to 600 detector telescopes arranged in rotational symmetry around the beam axis. CHICSi measures charged particles and fragments from nuclear reactions. It operates at internal targets of storage rings. In order to optimize space and momentum-space coverage and minimize the low-energy detection limits, CHICSi is designed for use in ultra-high vacuum (UHV, ∼10 -8 Pa) inside a cluster-jet target chamber. This calls for materials in mechanical support, detectors, Very Large Scale Integrated (VLSI) electronics, connectors, cables and other signal transport devices with very low outgassing. Two auxiliary detector systems, which will operate in coincidence with CHICSi, a heavy-recoil, time-of-flight system (HR-TOF) also placed inside the target chamber and a projectile fragmentation wall (PF-WALL) located outside the chamber, have also been constructed. In total, this combined system registers more than 80% of all charged particles and fragments from typical heavy-ion reactions at energies of a few hundreds of MeV per nucleon

CHICSi - a compact ultra-high vacuum compatible detector system for nuclear reaction experiments at storage rings. I. General structure, mechanics and UHV compatibility

Energy Technology Data Exchange (ETDEWEB)

Westerberg, L.; Avdeichikov, V.; Carlen, L.; Golubev, P.; Jakobsson, B. E-mail: bo.jakobsson@kosufy.lu.se; Rouki, C.; Siwek, A.; Veldhuizen, E.J. van; Whitlow, H.J

2003-03-11

CELSIUS Heavy-Ion Collision Silicon detector system (CHICSi) is a large solid angle, barrel-shaped detector system, housing up to 600 detector telescopes arranged in rotational symmetry around the beam axis. CHICSi measures charged particles and fragments from nuclear reactions. It operates at internal targets of storage rings. In order to optimize space and momentum-space coverage and minimize the low-energy detection limits, CHICSi is designed for use in ultra-high vacuum (UHV, {approx}10{sup -8} Pa) inside a cluster-jet target chamber. This calls for materials in mechanical support, detectors, Very Large Scale Integrated (VLSI) electronics, connectors, cables and other signal transport devices with very low outgassing. Two auxiliary detector systems, which will operate in coincidence with CHICSi, a heavy-recoil, time-of-flight system (HR-TOF) also placed inside the target chamber and a projectile fragmentation wall (PF-WALL) located outside the chamber, have also been constructed. In total, this combined system registers more than 80% of all charged particles and fragments from typical heavy-ion reactions at energies of a few hundreds of MeV per nucleon.

Introduction of circuit design on RFID system

International Nuclear Information System (INIS)

Pak, Sunho

2007-06-01

This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

Introduction of circuit design on RFID system

Energy Technology Data Exchange (ETDEWEB)

Pak, Sunho

2007-06-15

This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

Design of man-machine-communication-systems

International Nuclear Information System (INIS)

Zimmermann, R.

1975-04-01

This paper shows some fundamentals of man-machine-communication and deduces demands and recommendations for the design of communication systems. The main points are the directives for the design of optic display systems with details for visual perception and resolution, luminance and contrast, as well as discernibility and coding of displayed information. The most important rules are recommendations for acoustic information systems, control devices and for design of consoles are also given. (orig.) [de

New developments in double sided silicon strip detectors

International Nuclear Information System (INIS)

Becker, H.; Boulos, T.; Cattaneo, P.; Dietl, H.; Hauff, D.; Holl, P.; Lange, E.; Lutz, G.; Moser, H.G.; Schwarz, A.S.; Settles, R.; Struder, L.; Kemmer, J.; Buttler, W.

1990-01-01

A new type of double sided silicon strip detector has been built and tested using highly density VLSI readout electronics connected to both sides. Capacitive coupling of the strips to the readout electronics has been achieved by integrating the capacitors into the detector design, which was made possible by introducing a new detector biasing concept. Schemes to simplify the technology of the fabrication of the detectors are discussed. The static performance properties of the devices as well as implications of the use of VLSI electronics in their readout are described. Prototype detectors of the described design equipped with high density readout electronics have been installed in the ALEPH detector at LEP. Test results on the performance are given

Axiomatic Design of Space Life Support Systems

Science.gov (United States)

Jones, Harry W.

2017-01-01

Systems engineering is an organized way to design and develop systems, but the initial system design concepts are usually seen as the products of unexplained but highly creative intuition. Axiomatic design is a mathematical approach to produce and compare system architectures. The two axioms are:- Maintain the independence of the functional requirements.- Minimize the information content (or complexity) of the design. The first axiom generates good system design structures and the second axiom ranks them. The closed system human life support architecture now implemented in the International Space Station has been essentially unchanged for fifty years. In contrast, brief missions such as Apollo and Shuttle have used open loop life support. As mission length increases, greater system closure and increased recycling become more cost-effective.Closure can be gradually increased, first recycling humidity condensate, then hygiene wastewater, urine, carbon dioxide, and water recovery brine. A long term space station or planetary base could implement nearly full closure, including food production. Dynamic systems theory supports the axioms by showing that fewer requirements, fewer subsystems, and fewer interconnections all increase system stability. If systems are too complex and interconnected, reliability is reduced and operations and maintenance become more difficult. Using axiomatic design shows how the mission duration and other requirements determine the best life support system design including the degree of closure.

Conventional RF system design

International Nuclear Information System (INIS)

Puglisi, M.

1994-01-01

The design of a conventional RF system is always complex and must fit the needs of the particular machine for which it is planned. It follows that many different design criteria should be considered and analyzed, thus exceeding the narrow limits of a lecture. For this reason only the fundamental components of an RF system, including the generators, are considered in this short seminar. The most common formulas are simply presented in the text, while their derivations are shown in the appendices to facilitate, if desired, a more advanced level of understanding. (orig.)

System Design of the SWRL Financial System.

Science.gov (United States)

Ikeda, Masumi

To produce various management and accounting reports in order to maintain control of SWRL (Southwest Regional Laboratory) operational and financial activities, a computer-based SWRL financial system was developed. The system design is outlined, and various types of system inputs described. The kinds of management and accounting reports generated…

A compact readout system for multi-pixel hybrid photodiodes

International Nuclear Information System (INIS)

Datema, C.P.; Meng, L.J.; Ramsden, D.

1999-01-01

Although the first Multi-pixel Hybrid Photodiode (M-HPD) was developed in the early 1990s by Delft Electronic Products, the main obstacle to its application has been the lack of availability of a compact read-out system. A fast, parallel readout system has been constructed for use with the earlier 25-pixel tube with High-energy Physics applications in mind. The excellent properties of the recently developed multi-pixel hybrid photodiodes (M-HPD) will be easier to exploit following the development of the new hybrid read-out circuits described in this paper. This system will enable all of the required read-out functions to be accommodate on a single board into which the M-HPD is plugged. The design and performance of a versatile system is described in which a trigger-signal, derived from the common-side of the silicon anode in the M-HPD, is used to trigger the readout of the 60-anode pixels in the M-HPD. The multi-channel amplifier section is based on the use of a new, commercial VLSI chip, whilst the read-out sequencer uses a chip of its own design. The common anode signal is processed by a fast amplifier and discriminator to provide a trigger signal when a single event is detected. In the prototype version, the serial analogue output data-stream is processed using a PC-mounted, high speed ADC. Results obtained using the new read-out system in a compact gamma-camera and with a small muon tracking-chamber demonstrate the low-noise performance of the system. The application of this read-out system in other position-sensitive or multi-anode photomultiplier tube applications are also described

Overview of NSSS Fluid System Design of PGSFR

Energy Technology Data Exchange (ETDEWEB)

Han, Ji-Woong; Choi, Seok-Ki; Kim, Seong-O; Kim, Eui-Kwang; Kim, Dehee; Hong, Jonggan; Ye, Huee-Youl; Yeom, Sujin; Ryu, Seungho; Yoon, Jung; Choi, Sun Rock; Park, Jin-Seok; Lee, Tae-Ho Lee [KAERI, Daejeon (Korea, Republic of)

2016-05-15

In this paper an overview on the NSSS fluid system design of PGSFR is described based on the issued design documents. System concepts and major components design concepts for PHTS, IHTS, DHRS and SWRPRS were developed. Thermal-hydraulic characteristics were analyzed based on CFD simulation. The design bases and concepts for auxiliary systems were also developed. The upstream design requirements of fluid system such as system design requirements, component design requirements, I and C design requirements, BOP interface design requirements, design guides and P and IDs were produced. The control logic and computer code for the analysis for operational characteristics is under progress. The protection system consists of a safety grade PPS and a non-safety grade DPS (Diverse Protection System). The DPS provides a diverse method to trip the reactor to satisfy the requirements relative to ATWS (Anticipated Transients Without Scram) as well as Defense-In-Depth and Diversity.

SMART core protection system design

International Nuclear Information System (INIS)

Lee, J. K.; Park, H. Y.; Koo, I. S.; Park, H. S.; Kim, J. S.; Son, C. H.

2003-01-01

SMART COre Protection System(SCOPS) is designed with real-tims Digital Signal Processor(DSP) board and Network Interface Card(NIC) board. SCOPS has a Control Rod POSition (CRPOS) software module while Core Protection Calculator System(CPCS) consists of Core Protection Calculators(CPCs) and Control Element Assembly(CEA) Calculators(CEACs) in the commercial nuclear plant. It's not necessary to have a independent cabinets for SCOPS because SCOPS is physically very small. Then SCOPS is designed to share the cabinets with Plant Protection System(PPS) of SMART. Therefor it's very easy to maintain the system because CRPOS module is used instead of the computer with operating system

Design study on advanced nuclear fuel recycle system. Conceptual design study of recycle system using molten salt

International Nuclear Information System (INIS)

Kasai, Y.; Kakehi, I.; Moro, T.; Higashi, T.; Tobe, K.; Kawamura, F.; Yonezawa, S.; Yoshiuji, T.

1998-10-01

Advanced recycle system engineering group of OEC (Oarai Engineering Center) has being carried out a design study of the advanced nuclear fuel recycle system using molten salt (electro-metallurgical process). This system is aiming for improvements of fuel cycle economy and reduction of environmental burden (MA recycles, Minimum of radioactive waste disposal), and also improvement of safety and nuclear non-proliferation. This report describes results of the design study that has been continued since December 1996. (1) A design concept of the advanced nuclear fuel recycle system, that is a module type recycles system of pyrochemical reprocessing and fuel re-fabrication was studied. The module system has advantage in balance of Pu recycle where modules are constructed in coincidence with the construction plan of nuclear power plants, and also has flexibility for technology progress. A demonstration system, minimum size of the above module, was studies. This system has capacity of 10 tHM/y and is able to demonstrate recycle technology of MOX fuel, metal fuel and nitride fuel. (2) Each process of the system, which are pyrochemical electrorefining system, cathode processor, de-cladding system, waste disposal system, etc., were studied. In this study, capacity of an electrorefiner was discussed, and vitrification experiment of molten salt using lead-boric acid glass was conducted. (3) A hot cell system and material handling system of the demonstration system was studied. A robot driven by linear motor was studied for the handling system, and an arrangement plan of the cell system was made. Criticality analysis in the cell system and investigation of material accountancy system of the recycle plant were also made. This design study will be continued in coincidence with design study of reactor and fuel, aiming to establish the concept of FBR recycle system. (author)

DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

NARCIS (Netherlands)

Stefanov, T.; Pimentel, A.; Nikolov, H.; Ha, S.; Teich, J.

2017-01-01

The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design

Modularly Integrated MEMS Technology

National Research Council Canada - National Science Library

Eyoum, Marie-Angie N

2006-01-01

Process design, development and integration to fabricate reliable MEMS devices on top of VLSI-CMOS electronics without damaging the underlying circuitry have been investigated throughout this dissertation...

Designing automatic resupply systems.

Science.gov (United States)

Harding, M L

1999-02-01

This article outlines the process for designing and implementing autoresupply systems. The planning process includes determination of goals and appropriate participation. Different types of autoresupply mechanisms include kanban, breadman, consignment, systems contracts, and direct shipping from an MRP schedule.

Design study of a low-power, low-noise front-end for multianode silicon drift detectors

International Nuclear Information System (INIS)

Caponetto, L.; Presti, D. Lo; Randazzo, N.; Russo, G.V.; Leonora, E.; Lo Nigro, L.; Petta, C.; Reito, S.; Sipala, V.

2005-01-01

The read-out for Silicon Drift Detectors in the form of a VLSI chip is presented, with a view to applications in High Energy Physics and space experiments. It is characterised by extremely low power dissipation, small noise and size

Space Launch Systems Block 1B Preliminary Navigation System Design

Science.gov (United States)

Oliver, T. Emerson; Park, Thomas; Anzalone, Evan; Smith, Austin; Strickland, Dennis; Patrick, Sean

2018-01-01

NASA is currently building the Space Launch Systems (SLS) Block 1 launch vehicle for the Exploration Mission 1 (EM-1) test flight. In parallel, NASA is also designing the Block 1B launch vehicle. The Block 1B vehicle is an evolution of the Block 1 vehicle and extends the capability of the NASA launch vehicle. This evolution replaces the Interim Cryogenic Propulsive Stage (ICPS) with the Exploration Upper Stage (EUS). As the vehicle evolves to provide greater lift capability, increased robustness for manned missions, and the capability to execute more demanding missions so must the SLS Integrated Navigation System evolved to support those missions. This paper describes the preliminary navigation systems design for the SLS Block 1B vehicle. The evolution of the navigation hard-ware and algorithms from an inertial-only navigation system for Block 1 ascent flight to a tightly coupled GPS-aided inertial navigation system for Block 1B is described. The Block 1 GN&C system has been designed to meet a LEO insertion target with a specified accuracy. The Block 1B vehicle navigation system is de-signed to support the Block 1 LEO target accuracy as well as trans-lunar or trans-planetary injection accuracy. Additionally, the Block 1B vehicle is designed to support human exploration and thus is designed to minimize the probability of Loss of Crew (LOC) through high-quality inertial instruments and robust algorithm design, including Fault Detection, Isolation, and Recovery (FDIR) logic.

Participatory simulation in hospital work system design

DEFF Research Database (Denmark)

Andersen, Simone Nyholm

When ergonomic considerations are integrated into the design of work systems, both overall system performance and employee well-being improve. A central part of integrating ergonomics in work system design is to benefit from emplo y-ees’ knowledge of existing work systems. Participatory simulation...... (PS) is a method to access employee knowledge; namely employees are involved in the simulation and design of their own future work systems through the exploration of models representing work system designs. However, only a few studies have investigated PS and the elements of the method. Yet...... understanding the elements is essential when analyzing and planning PS in research and practice. This PhD study investigates PS and the method elements in the context of the Danish hospital sector, where PS is applied in the renewal and design of public hospitals and the work systems within the hospitals...

Psychology of system design

CERN Document Server

Meister, D

2014-01-01

This is a book about systems, including: systems in which humans control machines; systems in which humans interact with humans and the machine component is relatively unimportant; systems which are heavily computerized and those that are not; and governmental, industrial, military and social systems. The book deals with both traditional systems like farming, fishing and the military, and with systems just now tentatively emerging, like the expert and the interactive computer system. The emphasis is on the system concept and its implications for analysis, design and evaluation of these many di

KALIMER fuel system preliminary design description

International Nuclear Information System (INIS)

Hwang, Woan; Lee, B.O.; Nam, C.; Paek, S.K.

1998-10-01

This document provides general design concepts, design basis, preliminary design specification and design technologies which are needed for designing the fuel/non-fuel rods and assembly ducts of the KALIMER fuel system. The core of LMFBR consists of driver fuel assembly, blanket assembly, reflector assembly, shielding assembly, control assembly and GEM (Gas Expansion Module) as well as USS, dummy assembly, detector assembly. These core components must be designed to withstand the high temperature, high flux for a long irradiation exposure time. Due to the high temperature and high flux, irradiation creep and swelling as well as thermal-mechanical deformation are occurred at the fuel/non-fuel system and cause the deformations of materials and the geometric deflections at fuel/non-fuel rods, assembly ducts and components. In order to overcome these intricate phenomena through the engineering design, the design basis including theoretical analysis methodologies and design considerations, material characteristics of fuel system, and the specifications and drawings of fuel/non-fuel rods and assembly ducts, respectively, are presented. This document is preliminary design description which is produced in the conceptual design stage, and does not present the detailed and finalized design data which can be for the manufacturing. (author). 22 refs

Design of underwater work systems

International Nuclear Information System (INIS)

Lovelace, R.B.

1980-01-01

In the near future, underwater vehicles will replace divers as the principal means for inspection and maintenance work. These vehicles will provide a maneuverable work platform for an underwater viewing system and manipulator/tool package. Some of the problems faced by the underwater designer, and some areas to consider in the design of an integrated underwater work system, are considered

How system designers think: a study of design thinking in human factors engineering.

Science.gov (United States)

Papantonopoulos, Sotiris

2004-11-01

The paper presents a descriptive study of design thinking in human factors engineering. The objective of the study is to analyse the role of interpretation in design thinking and the role of design practice in guiding interpretation. The study involved 10 system designers undertaking the allocation of cognitive functions in three production planning and control task scenarios. Allocation decisions were recorded and verbal protocols of the design process were collected to elicit the subjects' thought processes. Verbal protocol analysis showed that subjects carried out the design of cognitive task allocation as a problem of applying a selected automation technology from their initial design deliberations. This design strategy stands in contrast to the predominant view of system design that stipulates that user requirements should be thoroughly analysed prior to making any decisions about technology. Theoretical frameworks from design research and ontological design showed that the system design process may be better understood by recognizing the role of design hypotheses in system design, as well as the diverse interactions between interpretation and practice, means and ends, and design practice and the designer's pre-understanding which shape the design process. Ways to balance the bias exerted on the design process were discussed.

Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

Science.gov (United States)

Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

2016-01-01

A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

General Systems Theory and Instructional Systems Design.

Science.gov (United States)

Salisbury, David F.

1990-01-01

Describes basic concepts in the field of general systems theory (GST) and identifies commonalities that exist between GST and instructional systems design (ISD). Models and diagrams that depict system elements in ISD are presented, and two matrices that show how GST has been used in ISD literature are included. (11 references) (LRW)

Future Smart Cooking Machine System Design

Directory of Open Access Journals (Sweden)

Dewi Agushinta R.

2013-11-01

Full Text Available There are many tools make human task get easier. Cooking has become a basic necessity for human beings, since food is one of basic human needs. Until now, the cooking equipment being used is still a hand tool. However everyone has slightly high activity. The presence of cooking tools that can do the cooking work by itself is now necessary. Future Smart Cooking Machine is an artificial intelligence machine that can do cooking work automatically. With this system design, the time is minimized and the ease of work is expected to be achieved. The development of this system is carried out with System Development Life Cycle (SDLC methods. Prototyping method used in this system is a throw-away prototyping approach. At the end of this research there will be produced a cooking machine system design including physical design engine and interface design.

Research on design connotation of hair drier system

Science.gov (United States)

Li, Yongchuan; Wu, Qiong

2018-04-01

After the analysis and summary of the research on the design of hair drier system, the system design is focused on. Product system design is not only to study its entity, but also is recognized as the part, element and component with a systematic feature to deeply analyze the innovation way of product system design, which is taken as its concept to carry out the association analysis on the component elements of hair driers and the overall analysis and study on the system design process of hair dryers. The product life cycle is taken as the main goal, through system analysis, system synthesis and system optimization, to solve the problems of product design. It is of great practical significance.

Integrated CAE system for nuclear power plants. Development of piping design check system

International Nuclear Information System (INIS)

Narikawa, Noboru; Sato, Teruaki

1994-01-01

Toshiba Corporation has developed and operated the integrated CAE system for nuclear power plants, the core of which is the engineering data base to manage accurately and efficiently enormous amount of data on machinery, equipment and piping. As the first step of putting knowledge base system to practical use, piping design check system has been developed. By automatically checking up piping design, this system aims at the prevention of overlooking mistakes, efficient design works and the overall quality improvement of design. This system is based on the thought that it supports designers, and final decision is made by designers. This system is composed of the integrated data base, a two-dimensional CAD system and three-dimensional CAD system. The piping design check system is one of the application systems of the integrated CAE system. Object-oriented programming is the base of the piping design check system, and design knowledge and CAD data are necessary. As to the method of realizing the check system, the flow of piping design, the checkup functions, the checkup of interference and attribute base, and the integration of the system are explained. (K.I)

Control system design method

Science.gov (United States)

Wilson, David G [Tijeras, NM; Robinett, III, Rush D.

2012-02-21

A control system design method and concomitant control system comprising representing a physical apparatus to be controlled as a Hamiltonian system, determining elements of the Hamiltonian system representation which are power generators, power dissipators, and power storage devices, analyzing stability and performance of the Hamiltonian system based on the results of the determining step and determining necessary and sufficient conditions for stability of the Hamiltonian system, creating a stable control system based on the results of the analyzing step, and employing the resulting control system to control the physical apparatus.

System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip

DEFF Research Database (Denmark)

Virk, Kashif Munir

2008-01-01

is the first such attempt in the published literature. The second part of the thesis deals with the issues related to the development of system-level design methodologies for networked multiprocessor systems-on-chip at various levels of design abstraction with special focus on the modeling and design...... at the system-level. The multiprocessor modeling framework is then extended to include models of networked multiprocessor systems-on-chip which is then employed to model wireless sensor networks both at the sensor node level as well as the wireless network level. In the third and the final part, the thesis...... to the transaction-level model. The thesis, as a whole makes contributions by describing a design methodology for networked multiprocessor embedded systems at three layers of abstraction from system-level through transaction-level to the cycle accurate level as well as demonstrating it practically by implementing...

Ergonomics: an aid to system design

International Nuclear Information System (INIS)

McCafferty, D.B.

1990-01-01

In recent years, the engineering community has recognized that ergonomics can make significant contributions to system design. Working together engineers and ergonomists can create designs that effectively meet system goals. By considering the role of humans and technology in the context of systems and by reducing the potential for errors, gains can be made in overall system reliability. Such efforts can reduce the need for costly backfits and increase system efficiency. (author)

Design of an integrated I and C system

International Nuclear Information System (INIS)

Lee, C. K.; Oh, I. S.; Kim, D. H.

2004-08-01

The final goal of this project is to develop an integrated I and C systems, and through this project the localized equipment and systems being developed should secure the safety, the reliability, their applicability and technical competitiveness. As well, the technical interfaces among sub-projects should be maintained for integration. The results of this project are as following ; 1. Development of an integrated I and C system architecture: Development of the design concepts for KNICS and the design requirements for each I and C system, Development of the design requirements of control systems based on DCS, Design of the communication systems, Design of the interface signals among systems and analysis of traffic load for networks, Conceptual design of measuring and monitoring systems, Review of the structure of computer systems for information processing, Development of architectures for each system and KOICS 2. Technological integration and management of projects: Development of evaluation criteria for DCS and network systems, Evaluation of the DCS prototype, Design review of KNICS protection system, Review of the functions and design requirements of I and C systems in NPP, Analysis of the I and C system H/W in NPP and the APR1400 I and C system design, Review of the technology criteria and the regulatory trend for licensing issues, Extracting items for preparing the technical description of I and C systems, a part of proposal to invitation to bid (ITB), Planning for KNICS to be of practical use The results of this project will be applied as design bases during the development of 2nd phase KNICS. As well it is expected that the results of this project will be finally applied for the technical self-reliance of component design and manufacturing of NPP I and C systems

Design of a Construction Safety Training System using Contextual Design Methodology

OpenAIRE

Baldev, Darshan H.

2006-01-01

In the U.S., the majority of construction companies are small companies with 10 or fewer employees (BLS, 2004). The fatality rate in the construction industry is high, indicating a need for implementing safety training to a greater extent. This research addresses two main goals: to make recommendations and design a safety training system for small construction companies, and to use Contextual Design to design the training system. Contextual Design was developed by Holtzblatt (Beyer and Holtzb...

SSD as position detector for ASTROMAG

International Nuclear Information System (INIS)

Tanimori, Tohru

1987-01-01

Astromag is designed to be used in space stations. A reduction in the size of an apparatus will decrease the costs for satelite launching and concenquently increase the feasibility of the program. Compared to a wire chamber, a silicon strip detector (SSD) can be smaller in volume by more than 90 percent than a wire chamber. The energy available will by largely limited in a space station, but a circuit for wire chamber requires a power of several W-CH. The power consumption, on the other hand, will be about 1 mW-CH if CMOS VLSI is used in the readout circuits. Furthermore, a wire chamber consists of a large number of components while SSD is basically a simple pile of Si plates, leading to a low frequency of troubles. Since each stripe and VLSI is an independent module, it is not likely that malfunction of the entite system will be caused by a small trouble in a module. Techniques required for developing SSD or other components such as VLSI devices can serve for various purposes in the field of semiconductor industries. The existence of an industrial basis to support their development is advantageous not only in technical aspects but also for cost reduction. Their structures, major features and problems remaining to be solved are also briefly outlined. (Nogami, K.)

Design Specifications for Adaptive Real-Time Systems

Science.gov (United States)

1991-12-01

TICfl \\ E CT E Design Specifications for JAN’\\ 1992 Adaptive Real - Time Systems fl Randall W. Lichota U, Alice H. Muntz - December 1991 \\ \\\\/ 0 / r...268-2056 Technical Report CMU/SEI-91-TR-20 ESD-91-TR-20 December 1991 Design Specifications for Adaptive Real - Time Systems Randall W. Lichota Hughes...Design Specifications for Adaptive Real - Time Systems Abstract: The design specification method described in this report treats a software

Planning and design of information systems

CERN Document Server

Blokdijk, André

1991-01-01

Planning and Design of Information Systems provides a theoretical base and a practical method of executing the planning of computerized information systems, and the planning and design of individual applications. The book is organized into five parts, covering the non-technical and nonimplementational part of information systems planning, design, and development. Part I gives the theoretical base for the subsequent parts of the book. It discusses modeling, techniques, notations, boundaries, quality issues and aspects, and decomposition techniques and problems. Part II discusses the needs, prob

SUBSURFACE REPOSITORY INTEGRATED CONTROL SYSTEM DESIGN

International Nuclear Information System (INIS)

C.J. Fernado

1998-01-01

The purpose of this document is to develop preliminary high-level functional and physical control system architectures for the proposed subsurface repository at Yucca Mountain. This document outlines overall control system concepts that encompass and integrate the many diverse systems being considered for use within the subsurface repository. This document presents integrated design concepts for monitoring and controlling the diverse set of subsurface operations. The subsurface repository design will be composed of a series of diverse systems that will be integrated to accomplish a set of overall functions and objectives. The subsurface repository contains several Instrumentation and Control (I andC) related systems including: waste emplacement systems, ventilation systems, communication systems, radiation monitoring systems, rail transportation systems, ground control monitoring systems, utility monitoring systems (electrical, lighting, water, compressed air, etc.), fire detection and protection systems, retrieval systems, and performance confirmation systems. Each of these systems involve some level of I andC and will typically be integrated over a data communication network. The subsurface I andC systems will also integrate with multiple surface-based site-wide systems such as emergency response, health physics, security and safeguards, communications, utilities and others. The scope and primary objectives of this analysis are to: (1) Identify preliminary system level functions and interface needs (Presented in the functional diagrams in Section 7.2). (2) Examine the overall system complexity and determine how and on what levels these control systems will be controlled and integrated (Presented in Section 7.2). (3) Develop a preliminary subsurface facility-wide design for an overall control system architecture, and depict this design by a series of control system functional block diagrams (Presented in Section 7.2). (4) Develop a series of physical architectures

SUBSURFACE REPOSITORY INTEGRATED CONTROL SYSTEM DESIGN

Energy Technology Data Exchange (ETDEWEB)

C.J. Fernado

1998-09-17

The purpose of this document is to develop preliminary high-level functional and physical control system architectures for the proposed subsurface repository at Yucca Mountain. This document outlines overall control system concepts that encompass and integrate the many diverse systems being considered for use within the subsurface repository. This document presents integrated design concepts for monitoring and controlling the diverse set of subsurface operations. The subsurface repository design will be composed of a series of diverse systems that will be integrated to accomplish a set of overall functions and objectives. The subsurface repository contains several Instrumentation and Control (I&C) related systems including: waste emplacement systems, ventilation systems, communication systems, radiation monitoring systems, rail transportation systems, ground control monitoring systems, utility monitoring systems (electrical, lighting, water, compressed air, etc.), fire detection and protection systems, retrieval systems, and performance confirmation systems. Each of these systems involve some level of I&C and will typically be integrated over a data communication network. The subsurface I&C systems will also integrate with multiple surface-based site-wide systems such as emergency response, health physics, security and safeguards, communications, utilities and others. The scope and primary objectives of this analysis are to: (1) Identify preliminary system level functions and interface needs (Presented in the functional diagrams in Section 7.2). (2) Examine the overall system complexity and determine how and on what levels these control systems will be controlled and integrated (Presented in Section 7.2). (3) Develop a preliminary subsurface facility-wide design for an overall control system architecture, and depict this design by a series of control system functional block diagrams (Presented in Section 7.2). (4) Develop a series of physical architectures that

CC-based Design of Secure Application Systems

DEFF Research Database (Denmark)

Sharp, Robin

2009-01-01

This paper describes some experiences with using the Common Criteria for Information Security Evaluation as the basis for a design methodology for secure application systems. The examples considered include a Point-of-Sale (POS) system, a wind turbine park monitoring and control system and a secu...... an effective and secure design, starting with the formulation of a Protection Profile and ending with a concrete design, within the project timeframe.......This paper describes some experiences with using the Common Criteria for Information Security Evaluation as the basis for a design methodology for secure application systems. The examples considered include a Point-of-Sale (POS) system, a wind turbine park monitoring and control system and a secure...

Algal Supply System Design - Harmonized Version

Energy Technology Data Exchange (ETDEWEB)

Jared Abodeely; Daniel Stevens; Allison Ray; Debor

2013-03-01

The objective of this design report is to provide an assessment of current technologies used for production, dewatering, and converting microalgae cultivated in open-pond systems to biofuel. The original draft design was created in 2011 and has subsequently been brought into agreement with the DOE harmonized model. The design report extends beyond this harmonized model to discuss some of the challenges with assessing algal production systems, including the ability to (1) quickly assess alternative algal production system designs, (2) assess spatial and temporal variability, and (3) perform large-scale assessments considering multiple scenarios for thousands of potential sites. The Algae Logistics Model (ALM) was developed to address each of these limitations of current modeling efforts to enable assessment of the economic feasibility of algal production systems across the United States. The (ALM) enables (1) dynamic assessments using spatiotemporal conditions, (2) exploration of algal production system design configurations, (3) investigation of algal production system operating assumptions, and (4) trade-off assessments with technology decisions and operating assumptions. The report discusses results from the ALM, which is used to assess the baseline design determined by harmonization efforts between U.S. DOE national laboratories. Productivity and resource assessment data is provided by coupling the ALM with the Biomass Assessment Tool developed at PNNL. This high-fidelity data is dynamically passed to the ALM and used to help better understand the impacts of spatial and temporal constraints on algal production systems by providing a cost for producing extracted algal lipids annually for each potential site.

ELEC-2002: Electronics in HEP

CERN Multimedia

Davide Vitè

2002-01-01

ELEC-2002 is a 15-session modern electronic course, given by CERN physicists and engineers, in a new format within the framework of the Technical Training Programme. This course is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2002 is composed of two terms: sessions take place on Tuesdays and Thursdays from 14h00 to 16h30. Spring term: Integrated circuits and VLSI technology for physics (April 2002) Introduction to VLSI (Paulo Moreira, 9 April) Basic digital design (Paulo Moreira, 11 April) Analogue design technologies (Francis Anghinolfi, 16 April) Radiation effects in electronics devices and circuits (Federico Faccio, 18 April) Digital design: design methodology and tools (Jorgen Christiansen, 23 April) Digital design: production (Jorgen Christiansen, 25 Apr...

Design status of Hyper system

International Nuclear Information System (INIS)

Park, Won S.; Hwang, Woan; Kom, Yong G.; Tak, Nam Il; Song, Tae T.

2000-01-01

Korea Atomic Energy Research Institute (KAERI) has been performing accelerator driven system related research and development (Rid) called Hyper for the transmutation of nuclear waste and energy production through the transmutation process. Hyper program is within the frame work of the national mid and long-term nuclear research plan. KAERI is aiming to develop the system concept and a type of road map by the year of 2001 and complete the conceptual design of HYPER system by the year of 2006. Some major design features of HYPER system have been developed. On-power fueling concepts are employed to compensate for the rapid drop of core reactivity. In order to increase the proliferation resistance, whole TRU without any actinide separation will be transmuted in the HYPER system. The long-lived fission products such as Tc-99 and I-129 will be destroyed using the localized thermal neutrons separately in the HYPER. A hollow cylinder-type metal fuel (TRU-Zr) has been chosen because of its high compatibility with pyro-chemical process. Pb-Bi is adopted as a coolant and spallation target material. The heat removal system is designed based on 3 loop concept. 1Gev 6mA proton beam is designed to be provided for HYPER. HYPER is to transmute about 380 kg of TRU a year and produce 1000MWth power. The support ratio of HYPER is believed to be 5 - 6. (author)

Mechatronic Systems Analysis, Design and Implementation

CERN Document Server

Boukas, El-Kébir

2012-01-01

This book deals with the analysis, the design and the implementation of the mechatronic systems. Classical and modern tools are developed for the analysis and the design for such systems. Robust control, H-Infinity and guaranteed cost control theory are also used for analysis and design of mechatronic systems. Different controller such as state feedback, static output feedback and dynamic output feedback controllers are used to stabilize mechatronic systems. Heuristic algorithms are provided to solve the design of the classical controller such as PID, phase lead, phase lag and phase lead-lag controllers while linear matrix inequalities (LMI) algorithms are provided for finding solutions to the state feedback, static output feedback and dynamic output feedback controllers. The theory presented in the different chapters of the volume is applied to numerical examples to show the usefulness of the theoretical results. Some case studies are also provided to show how the developed concepts apply for real system. Em...

System 80+{trademark} Standard Design: CESSAR design certification. Volume 3: Amendment I

Energy Technology Data Exchange (ETDEWEB)

1990-12-21

This report, entitled Combustion Engineering Standard Safety Analysis Report - Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These documents describe the Combustion Engineering, Inc. System 80+{sup TM} Standard Design. This report, Volume 3, in conjunction with Volume 2, provides the design of structures, components, equipment and systems.

Design of biomass district heating systems

International Nuclear Information System (INIS)

Vallios, Ioannis; Tsoutsos, Theocharis; Papadakis, George

2009-01-01

The biomass exploitation takes advantage of the agricultural, forest, and manure residues and in extent, urban and industrial wastes, which under controlled burning conditions, can generate heat and electricity, with limited environmental impacts. Biomass can - significantly - contribute in the energy supplying system, if the engineers will adopt the necessary design changes to the traditional systems and become more familiar with the design details of the biomass heating systems. The aim of this paper is to present a methodology of the design of biomass district heating systems taking into consideration the optimum design of building structure and urban settlement around the plant. The essential energy parameters are presented for the size calculations of a biomass burning-district heating system, as well as for the environmental (i.e. Greenhouse Gas Emissions) and economic evaluation (i.e. selectivity and viability of the relevant investment). Emphasis has been placed upon the technical parameters of the biomass system, the economic details of the boiler, the heating distribution network, the heat exchanger and the Greenhouse Gas Emissions

Cask system design guidance for robotic handling

International Nuclear Information System (INIS)

Griesmeyer, J.M.; Drotning, W.D.; Morimoto, A.K.; Bennett, P.C.

1990-10-01

Remote automated cask handling has the potential to reduce both the occupational exposure and the time required to process a nuclear waste transport cask at a handling facility. The ongoing Advanced Handling Technologies Project (AHTP) at Sandia National Laboratories is described. AHTP was initiated to explore the use of advanced robotic systems to perform cask handling operations at handling facilities for radioactive waste, and to provide guidance to cask designers regarding the impact of robotic handling on cask design. The proof-of-concept robotic systems developed in AHTP are intended to extrapolate from currently available commercial systems to the systems that will be available by the time that a repository would be open for operation. The project investigates those cask handling operations that would be performed at a nuclear waste repository facility during cask receiving and handling. The ongoing AHTP indicates that design guidance, rather than design specification, is appropriate, since the requirements for robotic handling do not place severe restrictions on cask design but rather focus on attention to detail and design for limited dexterity. The cask system design features that facilitate robotic handling operations are discussed, and results obtained from AHTP design and operation experience are summarized. The application of these design considerations is illustrated by discussion of the robot systems and their operation on cask feature mock-ups used in the AHTP project. 11 refs., 11 figs

TFTR neutral beam systems conceptual design

International Nuclear Information System (INIS)

1976-03-01

The functions, design requirements, and design descriptions of the injection system are described. Cost summaries are given for each system and subsystem. The costs presented are for: materials procurement; and shipping, assembly, and installation at the Princeton site

Design of MHD generator systems

International Nuclear Information System (INIS)

Buende, R.; Raeder, J.

1975-01-01

By assessment of the influence of the combustion efficiency on the electric output of the MHD generator, it can be shown that the construction and efficiency of the generator strongly depend on these parameters. The solutions of this system of equations are discussed. Following a derivation of criteria and boundary conditions of the design and a determination of the specific construction costs of individual system components, it is shown how the single design parameters influence the operational characteristics of such a system, especially the output, efficiency and energy production costs. (GG/LH) [de

Design Requirements for Designing Responsive Modular Manufacturing Systems

DEFF Research Database (Denmark)

Jørgensen, Steffen; Madsen, Ole; Nielsen, Kjeld

2011-01-01

Customers demand the newest technologies, newest designs, the ability to customise, high quality, and all this at a low cost. These are trends which challenge the traditional way of operating manufacturing companies, especially in regard to product development and manufacturing. Research...... the needed flexibility and responsiveness, but such systems are not yet fully achieved. From related theory it is known that achieving modular benefits depend on the modular architecture; a modular architecture which must be developed according to the customer needs. This makes production needs a design...... requirement in order to achieve responsiveness and other benefits of modular manufacturing systems (MMS). Due to the complex and interrelated nature of a production system and its surroundings these production needs are complex to identify. This paper presents an analysis framework for identification...

VLSI Design Tools, Reference Manual, Release 2.0.

Science.gov (United States)

1984-08-01

eder. 2.3 ITACV: Libary ofC readne. far oesumdg a layoit 1-,, tiling. V ~2.4 "QUILT: CeinS"Wbesa-i-M-8euar ray f atwok til 2.5 "TIL: Tockmeleff...8217patterns package was added so that complex and repetitive digital waveforms could be generated far more easily. The recently written program MTP (Multiple...circuit model to estimate timing delays through digital circuits. It also has a mode that allows it to be used as a switch (gate) level simulator

Operation and maintenance requirements of system design bases

International Nuclear Information System (INIS)

Banerjee, A.K.; Hanley, N.E.

1989-01-01

All system designs make assumptions about system operation testing, inspection, and maintenance. Existing industry codes and standards explicitly address design requirements of new systems, while issues related to system and plant reliability, life, design margins, effects of service conditions, operation, maintenance, etc., usually are implicit. However, system/component design documents of existing power plants often address the code requirements without considering the operation, maintenance, inspection, and testing (OMIT) requirements. The nuclear industry is expending major efforts at most nuclear power plants to reassemble and/or reconstitute system design bases. Stone ampersand Webster Engineering Corporation (SWEC) recently addressed the OMIT requirements of system/component design as an integral part of a utility's preventive maintenance program. For each component, SWEC reviewed vendor recommendations, NPRDS data/industry experience, the existing maintenance program, component service conditions, and actual plant experience. A maintenance program that considers component service conditions and plant experience ensures a connection between maintenance and design basis. Root cause analysis of failure and engineering evaluation of service condition are part of the program. System/component OMIT requirements also are compared against system design, service condition, degradation mechanism, etc., through system/component life-cycle evaluation

Development of intellectual reactor design system IRDS

International Nuclear Information System (INIS)

Kugo, T.; Tsuchihashi, K.; Nakagawa, M.; Mori, T.

1993-01-01

An intellectual reactor design system IRDS has been developed to support feasibility study and conceptual design of new type reactors in the fields of reactor core design including neutronics, thermal-hydraulics and fuel design. IRDS is an integrated software system in which a variety of computer codes in the different fields are installed. An integration of simulation modules are performed by the information transfer between modules through design model in which the design information of the current design work is stored. An object oriented architecture is realized in frame representation of core configuration in a design data base. The knowledge relating to design tasks to be performed are encapsulated, to support the conceptual design work. The system is constructed on an engineering workstation, and supports efficiently design work through man-machine interface adopting the advanced information processing technologies. Optimization methods for design parameters with use of the artificial intelligence technique are now under study, to reduce the parametric study work. A function to search design window in which design is feasible is realized in the fuel pin design. (orig.)

A Road Map for Knowledge Management Systems Design Using Axiomatic Design Approach

Directory of Open Access Journals (Sweden)

Houshmand Mahmoud

2017-01-01

Full Text Available Successful design and implementation of knowledge management systems have been the main concern of many researchers. It has been reported that more than 50% of knowledge management systems have failed, therefore, it is required to seek for a new and comprehensive scientific approach to design and implement it. In the design and implementation of a knowledge management system, it is required to know ’what we want to achieve’ and ’how and by what processes we will achieve it’. A literature review conducted and axiomatic design theory selected for this purpose. For the first time, this paper develops a conceptual design of knowledge management systems by means of a hierarchical structure, composed of ’Functional Requirements’ (FRs, ’Design Parameters’ (DPs, and ’Process Variables’ (PVs. The intersection of several studies conducted in the field of knowledge management systems has been used to design the knowledge management model. It reveals that six essential bases of knowledge management are organizational culture, organizational structure, human resources, management and leadership, information technology, and the external environment of the organization; that are represented as top DPs in the structure of the model. These essential factors are decomposed to lower levels by means of zigzagging. The model implemented in Tehran Urban and Suburban Railway Operation Corporation (TUSROC and the results were very promising. The most important result of this study is a roadmap to design successful and efficient knowledge management systems.

Signal Processing in Medical Ultrasound B-mode Imaging

International Nuclear Information System (INIS)

Song, Tai Kyong

2000-01-01

Ultrasonic imaging is the most widely used modality among modern imaging device for medical diagnosis and the system performance has been improved dramatically since early 90's due to the rapid advances in DSP performance and VLSI technology that made it possible to employ more sophisticated algorithms. This paper describes 'main stream' digital signal processing functions along with the associated implementation considerations in modern medical ultrasound imaging systems. Topics covered include signal processing methods for resolution improvement, ultrasound imaging system architectures, roles and necessity of the applications of DSP and VLSI technology in the development of the medical ultrasound imaging systems, and array signal processing techniques for ultrasound focusing

Design of Chebychev’s Low Pass Filters Using Nonuniform Transmission Lines

Directory of Open Access Journals (Sweden)

Said Attamimi

2016-03-01

Full Text Available Transmission lines are utilized in many applications to convey energy as well as information. Nonuniform transmission lines (NTLs are obtained through variation of the characteristic quantities along the axial direction. Such NTLs can be used to design network elements, like matching circuits, delay equalizers, filters, VLSI interconnections, etc. In this work, NTLs were analyzed with a numerical method based on the implementation of method of moment. In order to approximate the voltage and current distribution along the transmission line, a sum of basis functions with unknown amplitudes was introduced. As basis function, a constant function was used. In this work, we observed several cases such as lossless and lossy uniform transmission lines with matching and arbitrary load. These cases verified the algorithm developed in this work. The second example consists of nonuniform transmission lines in the form of abruptly changing transmission lines. This structure was used to design a Chebychev’s low pass filter. The calculated reflection and transmission factors of the filters showed some coincidences with the measurements.

From Autonomous Systems to Sociotechnical Systems: Designing Effective Collaborations

Directory of Open Access Journals (Sweden)

Kyle J. Behymer

Full Text Available Effectiveness in sociotechnical systems often depends on coordination among multiple agents (including both humans and autonomous technologies. This means that autonomous technologies must be designed to function as collaborative systems, or team players. In many complex work domains, success is beyond the capabilities of humans unaided by technologies. However, at the same time, human capabilities are often critical to ultimate success, as all automated control systems will eventually face problems their designers did not anticipate. Unfortunately, there is often an either/or attitude with respect to humans and technology that tends to focus on optimizing the separate human and autonomous components, with the design of interfaces and team processes as an afterthought. The current paper discusses the limitations of this approach and proposes an alternative where the goal of design is a seamless integration of human and technological capabilities into a well-functioning sociotechnical system. Drawing lessons from both the academic (SRK Framework and commercial (IBM’s Watson, video games worlds, suggestions for enriching the coupling between the human and automated systems by considering both technical and social aspects are discussed.

Thermal energy systems design and analysis

CERN Document Server

Penoncello, Steven G

2015-01-01

IntroductionThermal Energy Systems Design and AnalysisSoftwareThermal Energy System TopicsUnits and Unit SystemsThermophysical PropertiesEngineering DesignEngineering EconomicsIntroductionCommon Engineering Economics NomenclatureEconomic Analysis Tool: The Cash Flow DiagramTime Value of MoneyTime Value of Money ExamplesUsing Software to Calculate Interest FactorsEconomic Decision MakingDepreciation and TaxesProblemsAnalysis of Thermal Energy SystemsIntroductionNomenclatureThermophysical Properties of SubstancesSuggested Thermal Energy Systems Analysis ProcedureConserved and Balanced QuantitiesConservation of MassConservation of Energy (The First Law of Thermodynamics)Entropy Balance (The Second Law of Thermodynamics)Exergy Balance: The Combined LawEnergy and Exergy Analysis of Thermal Energy CyclesDetailed Analysis of Thermal Energy CyclesProblemsFluid Transport in Thermal Energy SystemsIntroductionPiping and Tubing StandardsFluid Flow FundamentalsValves and FittingsDesign and Analysis of Pipe NetworksEconomi...

Design and analysis for piping systems

International Nuclear Information System (INIS)

Sterkel, H.-P.; Cutrim, J.H.C.

1981-01-01

The procedure and the typical techniques that are used in NUCLEN for the design and the calculation of the piping of Nuclear Plants. The classification system are generically described and the analysis techniques which are used for the design and verification of the piping systems, i.e. pressure design for the dimensioning of the wallthicknesses, temperature and dead weight analysis together with determination of support points, are shown. The techniques of dynamic design and analyses are described for earthquake and pressure impulse loadings. (Author) [pt

Technique of design on CCTV system

International Nuclear Information System (INIS)

Won, Song Heui

1996-04-01

This book deals with design of CCTV system, which consists of nine chapters and goes as follows base of CCTV system, basic direction of system design on system element, choice of purpose and method of system choice for condition of equipment and check lists, some examples like TV system in shops, surveillance system in markets and watching system of vehicle, road and traffic, imaging unit such as CCTV camera, lens, subject, camera housing, camera support device, transmission with transmission device, transmission by wireless or wire, monitor, special monitor and VTR, system about video distribution amplifier and synchronizing signal generator, control of camera and construction and maintenance of CCTV.

Planetary Sample Caching System Design Options

Science.gov (United States)

Collins, Curtis; Younse, Paulo; Backes, Paul

2009-01-01

Potential Mars Sample Return missions would aspire to collect small core and regolith samples using a rover with a sample acquisition tool and sample caching system. Samples would need to be stored in individual sealed tubes in a canister that could be transfered to a Mars ascent vehicle and returned to Earth. A sample handling, encapsulation and containerization system (SHEC) has been developed as part of an integrated system for acquiring and storing core samples for application to future potential MSR and other potential sample return missions. Requirements and design options for the SHEC system were studied and a recommended design concept developed. Two families of solutions were explored: 1)transfer of a raw sample from the tool to the SHEC subsystem and 2)transfer of a tube containing the sample to the SHEC subsystem. The recommended design utilizes sample tool bit change out as the mechanism for transferring tubes to and samples in tubes from the tool. The SHEC subsystem design, called the Bit Changeout Caching(BiCC) design, is intended for operations on a MER class rover.

Design of Thermal Systems Using Topology Optimization

DEFF Research Database (Denmark)

Haertel, Jan Hendrik Klaas

printeddry-cooled power plant condensers using a simpliffed thermouid topology optimizationmodel is presented in another study. A benchmarking of the optimized geometriesagainst a conventional heat exchanger design is conducted and the topologyoptimized designs show a superior performance. A thermouid......The goalof this thesis is to apply topology optimization to the design of differentthermal systems such as heat sinks and heat exchangers in order to improve thethermal performance of these systems compared to conventional designs. Thedesign of thermal systems is a complex task that has...... of optimized designs are presentedwithin this thesis.  The maincontribution of the thesis is the development of several numerical optimizationmodels that are applied to different design challenges within thermalengineering.  Topology optimization isapplied in an industrial project to design the heat rejection...

Dynamic Systems Modeling in Educational System Design & Policy

Science.gov (United States)

Groff, Jennifer Sterling

2013-01-01

Over the last several hundred years, local and national educational systems have evolved from relatively simple systems to incredibly complex, interdependent, policy-laden structures, to which many question their value, effectiveness, and direction they are headed. System Dynamics is a field of analysis used to guide policy and system design in…

System 80+{trademark} Standard Design: CESSAR design certification. Volume 9: Amendment I

Energy Technology Data Exchange (ETDEWEB)

1990-12-21

This report, entitled Combustion Engineering Standard Safety Analysis Report -- Design Certification (CESSAR-DC), has been prepared in support of the industry effort to standardize nuclear plant designs. These volumes describe the Combustion Engineering, Inc. System 80{sup +}{trademark} Standard Design. This volume 9 discusses Electric Power and Auxiliary Systems.

Mars oxygen production system design

Science.gov (United States)

Cotton, Charles E.; Pillow, Linda K.; Perkinson, Robert C.; Brownlie, R. P.; Chwalowski, P.; Carmona, M. F.; Coopersmith, J. P.; Goff, J. C.; Harvey, L. L.; Kovacs, L. A.

1989-01-01

The design and construction phase is summarized of the Mars oxygen demonstration project. The basic hardware required to produce oxygen from simulated Mars atmosphere was assembled and tested. Some design problems still remain with the sample collection and storage system. In addition, design and development of computer compatible data acquisition and control instrumentation is ongoing.

Automatic seismic support design of piping system by an object oriented expert system

International Nuclear Information System (INIS)

Nakatogawa, T.; Takayama, Y.; Hayashi, Y.; Fukuda, T.; Yamamoto, Y.; Haruna, T.

1990-01-01

The seismic support design of piping systems of nuclear power plants requires many experienced engineers and plenty of man-hours, because the seismic design conditions are very severe, the bulk volume of the piping systems is hyge and the design procedures are very complicated. Therefore we have developed a piping seismic design expert system, which utilizes the piping design data base of a 3 dimensional CAD system and automatically determines the piping support locations and support styles. The data base of this system contains the maximum allowable seismic support span lengths for straight piping and the span length reduction factors for bends, branches, concentrated masses in the piping, and so forth. The system automatically produces the support design according to the design knowledge extracted and collected from expert design engineers, and using design information such as piping specifications which give diameters and thickness and piping geometric configurations. The automatic seismic support design provided by this expert system achieves in the reduction of design man-hours, improvement of design quality, verification of design result, optimization of support locations and prevention of input duplication. In the development of this system, we had to derive the design logic from expert design engineers and this could not be simply expressed descriptively. Also we had to make programs for different kinds of design knowledge. For these reasons we adopted the object oriented programming paradigm (Smalltalk-80) which is suitable for combining programs and carrying out the design work

Blindness in designing intelligent systems

Science.gov (United States)

Denning, Peter J.

1988-01-01

New investigations of the foundations of artificial intelligence are challenging the hypothesis that problem solving is the cornerstone of intelligence. New distinctions among three domains of concern for humans--description, action, and commitment--have revealed that the design process for programmable machines, such as expert systems, is based on descriptions of actions and induces blindness to nonanalytic action and commitment. Design processes focusing in the domain of description are likely to yield programs like burearcracies: rigid, obtuse, impersonal, and unable to adapt to changing circumstances. Systems that learn from their past actions, and systems that organize information for interpretation by human experts, are more likely to be successful in areas where expert systems have failed.