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Sample records for vhsic hardware description

  1. Specification of photonic circuits using quantum hardware description language.

    Science.gov (United States)

    Tezak, Nikolas; Niederberger, Armand; Pavlichin, Dmitri S; Sarma, Gopal; Mabuchi, Hideo

    2012-11-28

    Following the simple observation that the interconnection of a set of quantum optical input-output devices can be specified using structural mode VHSIC hardware description language, we demonstrate a computer-aided schematic capture workflow for modelling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.

  2. The VMTG Hardware Description

    CERN Document Server

    Puccio, B

    1998-01-01

    The document describes the hardware features of the CERN Master Timing Generator. This board is the common platform for the transmission of General Timing Machine required by the CERN accelerators. In addition, the paper shows the various jumper options to customise the card which is compliant to the VMEbus standard.

  3. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  4. Hardware Interface Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio Ssystem (STRS) Radio

    Science.gov (United States)

    Shalkhauser, Mary Jo W.; Roche, Rigoberto

    2017-01-01

    The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

  5. Hardware Trojans - Prevention, Detection, Countermeasures (A Literature Review)

    Science.gov (United States)

    2011-07-01

    manufacturing process in-house is infeasible for all but the smallest Application Specific Integrated Circuit (ASIC) designs. Our reliance on the globalisation ...UNCLASSIFIED THIS PAGE IS INTENTIONALLY BLANK vi UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 Contents Glossary ix 1 Introduction 1 2 Threats 3 2.1 Insertion...System on Chip TCB trusted Computing Base VHDL VHSIC Hardware Description Language x UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 1 Introduction Electronic

  6. Very High Speed Integrated Circuits (VHSIC).

    Science.gov (United States)

    1987-12-31

    basis. The workshops provided comprehensive training and education in VHSIC technology for defense contractor personnel for the purpose of...lrit (VHSJC) -’-TheA CoRScj ivclude appontdact the submitted to ONO~ foe review under Tecnology Security pw ti fo DAtCuclicld ru~lclause section 1504

  7. Hardware prototype with component specification and usage description

    NARCIS (Netherlands)

    Azam, Tre; Aswat, Soyeb; Klemke, Roland; Sharma, Puneet; Wild, Fridolin

    2017-01-01

    Following on from D3.1 and the final selection of sensors, in this D3.2 report we present the first version of the experience capturing hardware prototype design and API architecture taking into account the current limitations of the Hololens not being available until early next month in time for

  8. Hiding State in CλaSH Hardware Descriptions

    NARCIS (Netherlands)

    Gerards, Marco Egbertus Theodorus; Baaij, C.P.R.; Kuper, Jan; Kooijman, Matthijs

    Synchronous hardware can be modelled as a mapping from input and state to output and a new state, such mappings are referred to as transition functions. It is natural to use a functional language to implement transition functions. The CaSH compiler is capable of translating transition functions to

  9. Hardware Descriptive Languages: An Efficient Approach to Device ...

    African Journals Online (AJOL)

    Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog ...

  10. Hardware Description of Mass Weather Dissemination System Exploratory Engineering Model.

    Science.gov (United States)

    1982-09-01

    SEQUENTIAL MESSAGE COMPOSER/PLAYERS TELCO BARGE-IN TLOSSE LOCAL TELCO BARGE-IN i • TELCO SYSTEM EQUIPMENT NORTH ROUTES TELCO BARGE-IN’ ’ RE-I...34 TELCO SYSTEM EQUIPMENT SOUTH/WEST ROUTES 81- FIGURE 1. FUNCTIONAL DESCRIPTION OF THE TRIAL PATWAS OPERATION 2 f . .... " I’, ." The New York City PATWAS...actually utilized by the Mass Weather Dissemination:1 System. 24 TWENTY TELCO VOICE LINES VOICE LINES 48 VOLTS FOUR SPECIALISTP O T I S ua I 20 BY 8

  11. The SIFT hardware/software systems. Volume 1: A detailed description

    Science.gov (United States)

    Palumbo, Daniel L.

    1985-01-01

    This report contains a detailed description of the software implemented fault-tolerant computer's operating system and hardware subsystems. The Software Implemented Fault-Tolerant (SIFT) computer system was developed as an experimental vehicle for fault-tolerant systems research. The SIFT effort began with broad, in-depth studies stating the reliability and processing requirements for digital computers which would, in the aircraft of the 1990's, control flight-critical functions.

  12. Very High Speed Integrated Circuits - VHSIC - Final Program Repoort

    Science.gov (United States)

    1990-09-30

    contracts. The descriptions delivered by IBM contained non-standard, VI-DL ANSI/iEEE- 1076 code; therefore, simulations were not run. 76 CHAPI E~R 3 1 I...advanced systerrs d-,ign when VHDL came about. Design tools applied to problems above the gate (implementation) level require hardware 215 CHAPi ,.R / I

  13. DESCRIPCIÓN MODULAR DE UN ESQUEMA DE CODIFICACIÓN CONCATENADO PARA CORRECCIÓN DE ERRORES CON PROGRAMACIÓN DE HARDWARE MODULAR DESIGN OF SCHEME CODING CONCATENATED FOR CORRECTION ERROR WITH PROGRAMMING OF HARDWARE

    Directory of Open Access Journals (Sweden)

    Cecilia E Sandoval Ruiz

    2008-09-01

    Full Text Available Las comunicaciones inalámbricas requieren el empleo de métodos de corrección de errores sobre los datos transmitidos, usándose generalmente técnicas de codificación Reed-Solomon & Viterbi, por razones de desempeño y seguridad es preferible implementarlos sobre hardware. En este trabajo se presenta el diseño modular de la etapa de codificación de éstos códigos para su concatenación usando VHDL (VHSIC Hardware Descriptor Language, orientado a la implementación sobre tecnología de matriz de compuertas programadas por campo (FPGA, Se inicia con una revisión de los conceptos asociados a la definición de los componentes, y el modelo, descripción del comportamiento, luego la arquitectura es diseñada usando la sintaxis en VHDL y es capturado el diseño de hardware, finalmente se presentan los resultados de síntesis.The wireless communication medium require employing forward error correction methods on the data transferred, where Reed-Solomon & Viterbi coding techniques are utilized, because of performance and security reaso. In this paper we present a modular design of phase encoding these codes for concatenation using VHDL (VHSIC Hardware Descriptor Language and oriented to implementation with field programmable gate arrays (FPGA. The work besing with a review of code concept and the definition of the components and the model and the description of the behavioral. Later, the architecture is designed and captures using syntax in VHDL, and finally presents the results of synthesis.

  14. A Field Programmable Gate Array Based Software Defined Radio Design for the Space Environment

    Science.gov (United States)

    2009-12-01

    CFTP Configurable Fault-Tolerant Processor CRL Communications Research Laboratory DC Direct Current DFT Discrete Fourier Transform DSP Digital...Single Event Upset TMR Triple Modular Redundancy VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit XOR Exclusive Or...The System Generator interface is used to generate the design in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language ( VHDL

  15. Internal interface: I/O communication with FPGA circuits and hardware description standard for applications in HEP and FEL electronics ver. 1.0

    Energy Technology Data Exchange (ETDEWEB)

    Pozniak, K.T. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems ELHEP Laboratory

    2005-07-01

    The work describes hardware layer of the universal, parameterized communication interface for application in the FPGA chips. The interface is called in this work as the ''Internal Interface'' or in short the ''II''. The paper shows how to automatically create the address and data space, according to the user declarations. The methods to standardize the I/O communication with FPGA chips are described. The communication uses library functions and standardized, parametric components in VHDL. Theoretical background and technical description of the Internal Interface are illustrated with a few easy examples of simple interfaces. (orig.)

  16. Hardly Hardware

    Science.gov (United States)

    Lott, Debra

    2007-01-01

    In a never-ending search for new and inspirational still-life objects, the author discovered that home improvement retailers make great resources for art teachers. Hardware and building materials are inexpensive and have interesting and variable shapes. She especially liked the dryer-vent coils and the electrical conduit. These items can be…

  17. High-Speed Numeric Function Generator Using Piecewise Quadratic Approximations

    Science.gov (United States)

    2007-09-01

    125 1. VHDL ................................................................................................125...Logic Device DSP Digital Signal Processing ECS Engineering Capture System EVBDD Edge-Valued Binary Decision Diagram FPGA Field Programmable Gate...Memory xvi ROM Read Only Memory SRC Seymour R Cray USN United States Navy Verilog A C-Based HDL VHDL VHSIC Hardware Description Language VHSIC

  18. Neural Network Design on the SRC-6 Reconfigurable Computer

    Science.gov (United States)

    2006-12-01

    FUNCTION VHDL FILES ....................................................79 SIGFOUR.VHD...Projects Agency DEL Direct Execution Logic DLD Dense Logic Device DSP Digital Signal Processing EA Electronic Attack EM Electromagnetic FPGA... VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit XOR Exclusive-Or xvi

  19. Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

    Science.gov (United States)

    2013-12-01

    49 Figure 29. A comparison of Verilog and VHDL considering capability and level of abstraction required...inline package DSP digital signal processing DTMR distributed TMR EAR Export Administration Regulation EEPROM electrically erasable PROM EHP...current VHDL VHSIC hardware description language VHSIC very-high-speed integrated circuits VLSI very-large-scale integration VQFP very

  20. Hardware malware

    CERN Document Server

    Krieg, Christian

    2013-01-01

    In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

  1. DCSP hardware maintenance system

    Energy Technology Data Exchange (ETDEWEB)

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  2. VHSIC/VHSIC-Like Reliability Prediction Modeling

    Science.gov (United States)

    1989-10-01

    OXIDE AREA AND SHAING FACMIR S =.01, 1., 5 i x LIST OF FIGURES (CONT’D) Page FIGURE 5-18: LOGNORMAL PLOT OF FAILURES DUE TO HOT 103 CARRIER DEGRADATION...PhilliMp Resa boratoris (Weere 28) of which some aspects ,re prviously discu d M model is desreiba below. Petaps te nust unique aspect af the Phillips

  3. Introduction to Hardware Security

    Directory of Open Access Journals (Sweden)

    Yier Jin

    2015-10-01

    Full Text Available Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area.

  4. Open Hardware Business Models

    Directory of Open Access Journals (Sweden)

    Edy Ferreira

    2008-04-01

    Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  5. Improving Hardware Reusability: Software Defined Hardware

    Science.gov (United States)

    2017-03-01

    performance improvements over software, specialization is likely the future of hardware design. This trend will manifest in an increased demand for chip ...design methodologies is critical to meeting the incoming demand for chip diversity. Acknowledgements Research partially funded by DARPA Award Number...DARPA; and ASPIRE Lab industrial sponsors and affiliates Intel, Google, HPE, Huawei, LGE, Nokia, NVIDIA, Oracle, and Samsung. References [1

  6. Hardware protection through obfuscation

    CERN Document Server

    Bhunia, Swarup; Tehranipoor, Mark

    2017-01-01

    This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange o...

  7. Hardware removal - extremity

    Science.gov (United States)

    ... enable JavaScript. Surgeons use hardware such as pins, plates, or screws to help fix a broken bone ... SW, Hotchkiss RN, Pederson WC, Kozin SH, Cohen MS, eds. Green's Operative Hand Surgery . 7th ed. Philadelphia, ...

  8. Open Hardware at CERN

    CERN Multimedia

    CERN Knowledge Transfer Group

    2015-01-01

    CERN is actively making its knowledge and technology available for the benefit of society and does so through a variety of different mechanisms. Open hardware has in recent years established itself as a very effective way for CERN to make electronics designs and in particular printed circuit board layouts, accessible to anyone, while also facilitating collaboration and design re-use. It is creating an impact on many levels, from companies producing and selling products based on hardware designed at CERN, to new projects being released under the CERN Open Hardware Licence. Today the open hardware community includes large research institutes, universities, individual enthusiasts and companies. Many of the companies are actively involved in the entire process from design to production, delivering services and consultancy and even making their own products available under open licences.

  9. NASA HUNCH Hardware

    Science.gov (United States)

    Hall, Nancy R.; Wagner, James; Phelps, Amanda

    2014-01-01

    What is NASA HUNCH? High School Students United with NASA to Create Hardware-HUNCH is an instructional partnership between NASA and educational institutions. This partnership benefits both NASA and students. NASA receives cost-effective hardware and soft goods, while students receive real-world hands-on experiences. The 2014-2015 was the 12th year of the HUNCH Program. NASA Glenn Research Center joined the program that already included the NASA Johnson Space Flight Center, Marshall Space Flight Center, Langley Research Center and Goddard Space Flight Center. The program included 76 schools in 24 states and NASA Glenn worked with the following five schools in the HUNCH Build to Print Hardware Program: Medina Career Center, Medina, OH; Cattaraugus Allegheny-BOCES, Olean, NY; Orleans Niagara-BOCES, Medina, NY; Apollo Career Center, Lima, OH; Romeo Engineering and Tech Center, Washington, MI. The schools built various parts of an International Space Station (ISS) middeck stowage locker and learned about manufacturing process and how best to build these components to NASA specifications. For the 2015-2016 school year the schools will be part of a larger group of schools building flight hardware consisting of 20 ISS middeck stowage lockers for the ISS Program. The HUNCH Program consists of: Build to Print Hardware; Build to Print Soft Goods; Design and Prototyping; Culinary Challenge; Implementation: Web Page and Video Production.

  10. Computer hardware fault administration

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  11. CERN Neutrino Platform Hardware

    CERN Document Server

    Nelson, Kevin

    2017-01-01

    My summer research was broadly in CERN's neutrino platform hardware efforts. This project had two main components: detector assembly and data analysis work for ICARUS. Specifically, I worked on assembly for the ProtoDUNE project and monitored the safety of ICARUS as it was transported to Fermilab by analyzing the accelerometer data from its move.

  12. Hardware Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  13. Sterilization of space hardware.

    Science.gov (United States)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  14. COMPUTER HARDWARE MARKING

    CERN Multimedia

    Groupe de protection des biens

    2000-01-01

    As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

  15. Foundations of hardware IP protection

    CERN Document Server

    Torres, Lionel

    2017-01-01

    This book provides a comprehensive and up-to-date guide to the design of security-hardened, hardware intellectual property (IP). Readers will learn how IP can be threatened, as well as protected, by using means such as hardware obfuscation/camouflaging, watermarking, fingerprinting (PUF), functional locking, remote activation, hidden transmission of data, hardware Trojan detection, protection against hardware Trojan, use of secure element, ultra-lightweight cryptography, and digital rights management. This book serves as a single-source reference to design space exploration of hardware security and IP protection. · Provides readers with a comprehensive overview of hardware intellectual property (IP) security, describing threat models and presenting means of protection, from integrated circuit layout to digital rights management of IP; · Enables readers to transpose techniques fundamental to digital rights management (DRM) to the realm of hardware IP security; · Introduce designers to the concept of salutar...

  16. Open hardware for open science

    CERN Multimedia

    CERN Bulletin

    2011-01-01

    Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

  17. Space hardware microbial contamination

    Science.gov (United States)

    Baker, A.; Kern, R.; Mancinelli, R.; Venkateswaren, K.; Wainwright, N.

    Planetary Protection (PP) requirements imposed on unmanned planetary missions require that the spacecraft undergo rigorous bioload reduction prior to launch. The ability to quantitate bioburden on such spacecraft is dependent on developing new analytical methodologies that can be used to identify and trace biological contamination on flight hardware. The focus of new method development is to move forward and to augment the current spore analysis method which was first used on Viking. The ultimate goal of the new techniques is not to increase the cleanliness requirement currently levied on various missions, b ut instead to better understand the nature of the bioburden through the use of well-characterized standard methods. Subsequently an array of standard techniques is needed to provide various analytical methodologies that can be used to access bioburden, depending upon mission specifications. This poster will provide information on two workshops that have been held to review the status of the development of new quantitative techniques for determining the bioload on spacecraft at the time of launch. The purpose of the workshops was to review and revise NASA Standard Operation Procedure NPG:5340.1C "Microbiological Examination of Space Hardware and Associated Environments" to incorporate improvements in the procedure and to reflect current field practices. I addition the paneln reviewed the status of new analytical methods currently under study for planetary protection applications, defining expected research that would bring the individual methods to a point where they can be drafted for submittal to the NASA standard procedure process. The poster will highlight changes to current standard procedures as well as review the status of new methods currently being studied. Methods included Polymerase Chain Reaction (PCR), Epifluorescence Techniques, Live/Dead Cell Analysis, Capillary Electrophoresis of Amino Acids and Ionic Contaminants, High Sensitivity Assay for

  18. Hardware Support for Embedded Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2012-01-01

    The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

  19. Hardware for soft computing and soft computing for hardware

    CERN Document Server

    Nedjah, Nadia

    2014-01-01

    Single and Multi-Objective Evolutionary Computation (MOEA),  Genetic Algorithms (GAs), Artificial Neural Networks (ANNs), Fuzzy Controllers (FCs), Particle Swarm Optimization (PSO) and Ant colony Optimization (ACO) are becoming omnipresent in almost every intelligent system design. Unfortunately, the application of the majority of these techniques is complex and so requires a huge computational effort to yield useful and practical results. Therefore, dedicated hardware for evolutionary, neural and fuzzy computation is a key issue for designers. With the spread of reconfigurable hardware such as FPGAs, digital as well as analog hardware implementations of such computation become cost-effective. The idea behind this book is to offer a variety of hardware designs for soft computing techniques that can be embedded in any final product. Also, to introduce the successful application of soft computing technique to solve many hard problem encountered during the design of embedded hardware designs. Reconfigurable em...

  20. LHCb: Hardware Data Injector

    CERN Multimedia

    Delord, V; Neufeld, N

    2009-01-01

    The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid. The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. This means speeding up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or technologies and might also need new networking protocols: a customized TCP or proprietary solutions. A test module is being presented, which integrates in the existing LHCb infrastructure. It is a 10-Gigabit traffic generator, flexible enough to generate LHCb's raw data packets using dummy data or simulated data. These data are seen as real data coming from sub-detectors by the DAQ. The implementation is based on an FPGA using 10 Gigabit Ethernet interface. This module is integrated in the experiment control system. The architecture, ...

  1. Hardware Removal in Craniomaxillofacial Trauma

    Science.gov (United States)

    Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

    2015-01-01

    Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

  2. BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

    DEFF Research Database (Denmark)

    2010-01-01

    Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...

  3. Secure coupling of hardware components

    NARCIS (Netherlands)

    Hoepman, J.H.; Joosten, H.J.M.; Knobbe, J.W.

    2011-01-01

    A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and,

  4. Hardware for dynamic quantum computing.

    Science.gov (United States)

    Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

    2017-10-01

    We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

  5. Hardware for dynamic quantum computing

    Science.gov (United States)

    Ryan, Colm A.; Johnson, Blake R.; Ristè, Diego; Donovan, Brian; Ohki, Thomas A.

    2017-10-01

    We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

  6. NDAS Hardware Translation Layer Development

    Science.gov (United States)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  7. CHeCS (Crew Health Care Systems): International Space Station (ISS) Medical Hardware Catalog. Version 10.0

    Science.gov (United States)

    2011-01-01

    The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

  8. Signal Analysis Van Hardware Operation General Description. Volume 1.

    Science.gov (United States)

    1981-12-01

    for operation with inter- active graphics software. Hard copy printouts of the 4014 display are produced using the Versatec line printer in a hard-copy...initiated during an output operation to the printer, the hard copy process will begin only after the current computer direction transmission is...Linearity: 25 vpm/°C max. (40 C/LSB) Warmup Time 5 min Control Controlled by programmed instructions, clock counter overflow, or external input Output

  9. Hardware Descriptive Languages: An Efficient Approach to Device ...

    African Journals Online (AJOL)

    AFRREV STECH: An International Journal of Science and Technology. Journal Home · ABOUT · Advanced Search · Current Issue · Archives · Journal Home > Vol 1, No 2 (2012) >. Log in or Register to get access to full text downloads. Username, Password, Remember me, or Register · Download this PDF file. The PDF file ...

  10. Precontoured plating of clavicle fractures: decreased hardware-related complications?

    Science.gov (United States)

    VanBeek, Corinne; Boselli, Karen J; Cadet, Edwin R; Ahmad, Christopher S; Levine, William N

    2011-12-01

    Operative treatment of displaced midshaft clavicle fractures reportedly decreases the risk of symptomatic malunion, nonunion, and residual shoulder disability. Plating these fractures, however, may trade these complications for hardware-related problems. Low-profile anatomically precontoured plates may reduce the rates of plate prominence and hardware removal. We compared the outcomes after precontoured and noncontoured superior plating of acute displaced midshaft clavicle fractures. Primary outcomes were rate of plate prominence, rate of hardware removal, and rate of complications. Secondary outcomes were ROM and pain and function scores. We retrospectively reviewed 52 patients with 52 acute, displaced midshaft clavicle fractures treated with either noncontoured or precontoured superior clavicle plate fixation. Fourteen patients with noncontoured plates and 28 with precontoured plates were available for followup at a minimum of 1 year postoperatively. Postoperative assessment included ROM, radiographs, and subjective scores including visual analog scale for pain, American Shoulder and Elbow Surgeons questionnaire, and Simple Shoulder Test. Patients complained of prominent hardware in nine of 14 in the noncontoured group and nine of 28 in the precontoured group. Hardware removal rates were three of 14 in the noncontoured group and three of 28 in the precontoured group. Postoperative ROM and postoperative subjective scores were similar in the two groups. Precontoured plating versus noncontoured plating of displaced midshaft clavicle fractures results in a lower rate of plate prominence in patients who do not undergo hardware removal. Level III, therapeutic study. See Guidelines for Authors for a complete description of levels of evidence.

  11. Raspberry Pi hardware projects 1

    CERN Document Server

    Robinson, Andrew

    2013-01-01

    Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

  12. 16 CFR 1508.6 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial... FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner that eliminates from any hardware accessible to a child within the crib the possibility of the hardware's...

  13. Design and Implementation of Digital Signal Processing Hardware for a Software Radio Reciever

    OpenAIRE

    Talbot, Jake

    2008-01-01

    This pro ject summarizes the design and implementation of field programmable gate array (FPGA) based digital signal processing (DSP) hardware meant to be used in a software radio system. The filters and processing were first designed in MATLAB and then implemented using very high speed integrated circuit hardware description language (VHDL). Since this hardware is meant for a software radio system, making the hardware flexible was the main design goal. Flexibility in the FPGA design was reached u...

  14. Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system

    Directory of Open Access Journals (Sweden)

    Daniel Brüderle

    2009-06-01

    Full Text Available Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

  15. Establishing a Novel Modeling Tool: A Python-Based Interface for a Neuromorphic Hardware System

    Science.gov (United States)

    Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

    2008-01-01

    Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated. PMID:19562085

  16. Efficient BinDCT hardware architecture exploration and implementation on FPGA.

    Science.gov (United States)

    Ben Abdelali, Abdessalem; Chatti, Ichraf; Hannachi, Marwa; Mtibaa, Abdellatif

    2016-11-01

    This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

  17. Hardware-Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  18. The principles of computer hardware

    CERN Document Server

    Clements, Alan

    2000-01-01

    Principles of Computer Hardware, now in its third edition, provides a first course in computer architecture or computer organization for undergraduates. The book covers the core topics of such a course, including Boolean algebra and logic design; number bases and binary arithmetic; the CPU; assembly language; memory systems; and input/output methods and devices. It then goes on to cover the related topics of computer peripherals such as printers; the hardware aspects of the operating system; and data communications, and hence provides a broader overview of the subject. Its readable, tutorial-based approach makes it an accessible introduction to the subject. The book has extensive in-depth coverage of two microprocessors, one of which (the 68000) is widely used in education. All chapters in the new edition have been updated. Major updates include: powerful software simulations of digital systems to accompany the chapters on digital design; a tutorial-based introduction to assembly language, including many exam...

  19. Hardware and software reliability estimation using simulations

    Science.gov (United States)

    Swern, Frederic L.

    1994-01-01

    The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

  20. Scan image compression-encryption hardware system

    Science.gov (United States)

    Bourbakis, Nikolaos G.; Brause, R.; Alexopoulos, C.

    1995-04-01

    This paper deals with the hardware design of an image compression/encryption scheme called SCAN. The scheme is based on the principles and ideas reflected by the specification of the SCAN language. SCAN is a fractal based context-free language which accesses sequentially the data of a 2D array, by describing and generating a wide range (near (nxn)) of space filling curves (or SCAN patterns) from a short set of simple ones. The SCAN method uses the algorithmic description of each 2D image as SCAN patterns combinations for the compression and encryption of the image data. Note that each SCAN letter or word accesses the image data with a different order (or sequence), thus the application of a variety of SCAN words associated with the compression scheme will produce various compressed versions of the same image. The compressed versions are compared in memory size and the best of them with the smallest size in bits could be used for the image compression/encryption. Note that the encryption of the image data is a result of the great number of possible space filling curves which could be generated by SCAN. Since the software implementation of the SCAN compression/encryption scheme requires some time, the hardware design and implementation of the SCAN scheme is necessary in order to reduce the image compression/encryption time to the real-time one. The development of such an image compression encryption system will have a significant impact on the transmission and storage of images. It will be applicable in multimedia and transmission of images through communication lines.

  1. 16 CFR 1509.7 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1509.7 Section 1509.7 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be...

  2. GENI: Grid Hardware and Software

    Energy Technology Data Exchange (ETDEWEB)

    None

    2012-01-09

    GENI Project: The 15 projects in ARPA-E’s GENI program, short for “Green Electricity Network Integration,” aim to modernize the way electricity is transmitted in the U.S. through advances in hardware and software for the electric grid. These advances will improve the efficiency and reliability of electricity transmission, increase the amount of renewable energy the grid can utilize, and provide energy suppliers and consumers with greater control over their power flows in order to better manage peak power demand and cost.

  3. Introduction to co-simulation of software and hardware in embedded processor systems

    Energy Technology Data Exchange (ETDEWEB)

    Dreike, P.L.; McCoy, J.A.

    1996-09-01

    From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

  4. Travel Software using GPU Hardware

    CERN Document Server

    Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

    2015-01-01

    Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

  5. Hardware complications in scoliosis surgery

    Energy Technology Data Exchange (ETDEWEB)

    Bagchi, Kaushik; Mohaideen, Ahamed [Department of Orthopaedic Surgery and Musculoskeletal Services, Maimonides Medical Center, Brooklyn, NY (United States); Thomson, Jeffrey D. [Connecticut Children' s Medical Center, Department of Orthopaedics, Hartford, CT (United States); Foley, Christopher L. [Department of Radiology, Connecticut Children' s Medical Center, Hartford, Connecticut (United States)

    2002-07-01

    Background: Scoliosis surgery has undergone a dramatic evolution over the past 20 years with the advent of new surgical techniques and sophisticated instrumentation. Surgeons have realized scoliosis is a complex multiplanar deformity that requires thorough knowledge of spinal anatomy and pathophysiology in order to manage patients afflicted by it. Nonoperative modalities such as bracing and casting still play roles in the treatment of scoliosis; however, it is the operative treatment that has revolutionized the treatment of this deformity that affects millions worldwide. As part of the evolution of scoliosis surgery, newer implants have resulted in improved outcomes with respect to deformity correction, reliability of fixation, and paucity of complications. Each technique and implant has its own set of unique complications, and the surgeon must appreciate these when planning surgery. Materials and methods: Various surgical techniques and types of instrumentation typically used in scoliosis surgery are briefly discussed. Though scoliosis surgery is associated with a wide variety of complications, only those that directly involve the hardware are discussed. The current literature is reviewed and several illustrative cases of patients treated for scoliosis at the Connecticut Children's Medical Center and the Newington Children's Hospital in Connecticut are briefly presented. Conclusion: Spine surgeons and radiologists should be familiar with the different types of instrumentation in the treatment of scoliosis. Furthermore, they should recognize the clinical and roentgenographic signs of hardware failure as part of prompt and effective treatment of such complications. (orig.)

  6. Imaging of current spinal hardware: lumbar spine.

    Science.gov (United States)

    Ha, Alice S; Petscavage-Thomas, Jonelle M

    2014-09-01

    The purposes of this article are to review the indications for and the materials and designs of hardware more commonly used in the lumbar spine; to discuss alternatives for each of the types of hardware; to review normal postoperative imaging findings; to describe the appropriateness of different imaging modalities for postoperative evaluation; and to show examples of hardware complications. Stabilization and fusion of the lumbar spine with intervertebral disk replacement, artificial ligaments, spinous process distraction devices, plate-and-rod systems, dynamic posterior fusion devices, and newer types of material incorporation are increasingly more common in contemporary surgical practice. These spinal hardware devices will be seen more often in radiology practice. Successful postoperative radiologic evaluation of this spinal hardware necessitates an understanding of fundamental hardware design, physiologic objectives, normal postoperative imaging appearances, and unique complications. Radiologists may have little training and experience with the new and modified types of hardware used in the lumbar spine.

  7. Hardware realization of an SVM algorithm implemented in FPGAs

    Science.gov (United States)

    Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

    2017-08-01

    The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

  8. TreeBASIS Feature Descriptor and Its Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Spencer Fowers

    2014-01-01

    Full Text Available This paper presents a novel feature descriptor called TreeBASIS that provides improvements in descriptor size, computation time, matching speed, and accuracy. This new descriptor uses a binary vocabulary tree that is computed using basis dictionary images and a test set of feature region images. To facilitate real-time implementation, a feature region image is binary quantized and the resulting quantized vector is passed into the BASIS vocabulary tree. A Hamming distance is then computed between the feature region image and the effectively descriptive basis dictionary image at a node to determine the branch taken and the path the feature region image takes is saved as a descriptor. The TreeBASIS feature descriptor is an excellent candidate for hardware implementation because of its reduced descriptor size and the fact that descriptors can be created and features matched without the use of floating point operations. The TreeBASIS descriptor is more computationally and space efficient than other descriptors such as BASIS, SIFT, and SURF. Moreover, it can be computed entirely in hardware without the support of a CPU for additional software-based computations. Experimental results and a hardware implementation show that the TreeBASIS descriptor compares well with other descriptors for frame-to-frame homography computation while requiring fewer hardware resources.

  9. A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.

    Science.gov (United States)

    Brüderle, Daniel; Petrovici, Mihai A; Vogginger, Bernhard; Ehrlich, Matthias; Pfeil, Thomas; Millner, Sebastian; Grübl, Andreas; Wendt, Karsten; Müller, Eric; Schwartz, Marc-Olivier; de Oliveira, Dan Husmann; Jeltsch, Sebastian; Fieres, Johannes; Schilling, Moritz; Müller, Paul; Breitwieser, Oliver; Petkov, Venelin; Muller, Lyle; Davison, Andrew P; Krishnamurthy, Pradeep; Kremkow, Jens; Lundqvist, Mikael; Muller, Eilif; Partzsch, Johannes; Scholze, Stefan; Zühl, Lukas; Mayr, Christian; Destexhe, Alain; Diesmann, Markus; Potjans, Tobias C; Lansner, Anders; Schüffny, René; Schemmel, Johannes; Meier, Karlheinz

    2011-05-01

    In this article, we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results.

  10. Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware

    Directory of Open Access Journals (Sweden)

    Andreas Stöckel

    2017-08-01

    Full Text Available Large-scale neuromorphic hardware platforms, specialized computer systems for energy efficient simulation of spiking neural networks, are being developed around the world, for example as part of the European Human Brain Project (HBP. Due to conceptual differences, a universal performance analysis of these systems in terms of runtime, accuracy and energy efficiency is non-trivial, yet indispensable for further hard- and software development. In this paper we describe a scalable benchmark based on a spiking neural network implementation of the binary neural associative memory. We treat neuromorphic hardware and software simulators as black-boxes and execute exactly the same network description across all devices. Experiments on the HBP platforms under varying configurations of the associative memory show that the presented method allows to test the quality of the neuron model implementation, and to explain significant deviations from the expected reference output.

  11. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Madsen, Jan; Knudsen, Peter Voigt

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search...

  12. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search....

  13. Projecto de hardware digital orientado por objectos

    OpenAIRE

    Fernandes, João M.; Machado, Ricardo J.

    1997-01-01

    Os limites entre os domínios do software e do hardware são cada vez mais ténues, pelo que técnicas inicialmente experimentadas no software têm vindo a ser gradualmente aplicadas no hardware. Este artigo pretende descrever o estado actual da utilização da tecnologia de programação orientada por objectos no projecto de hardware digital. São analisadas as vantagens e implicações quando se introduzem conceitos ligados à tecnologia orientada por objectos em projectos de hardware e é apresent...

  14. Open-source hardware for medical devices.

    Science.gov (United States)

    Niezen, Gerrit; Eslambolchilar, Parisa; Thimbleby, Harold

    2016-04-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device.

  15. Thermal Hardware for the Thermal Analyst

    Science.gov (United States)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  16. Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

    NARCIS (Netherlands)

    Pham-Quoc Cuong, P.

    2015-01-01

    Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and

  17. Relational Algebra as formalism for Hardware Design

    NARCIS (Netherlands)

    ten Berg, A.J.W.M.; ten Berg, A.J.W.M.; Huijs, C.; Krol, Th.

    1993-01-01

    This paper introduces relational algebra as an elegant formalism to describe hardware behaviour. Hardware behaviour is modelled by functions that are represented by sets of tables. Relational algebra, developed for designing large and consistent databases is capable to operate on sets of tables and

  18. JPL multipolarization workstation - Hardware, software and examples of data analysis

    Science.gov (United States)

    Burnette, Fred; Norikane, Lynne

    1987-01-01

    A low-cost stand-alone interactive image processing workstation has been developed for operations on multipolarization JPL aircraft SAR data, as well as data from future spaceborne imaging radars. A recently developed data compression technique is used to reduce the data volume to 10 Mbytes, for a typical data set, so that interactive analysis may be accomplished in a timely and efficient manner on a supermicrocomputer. In addition to presenting a hardware description of the work station, attention is given to the software that has been developed. Three illustrative examples of data analysis are presented.

  19. Comparative Modal Analysis of Sieve Hardware Designs

    Science.gov (United States)

    Thompson, Nathaniel

    2012-01-01

    The CMTB Thwacker hardware operates as a testbed analogue for the Flight Thwacker and Sieve components of CHIMRA, a device on the Curiosity Rover. The sieve separates particles with a diameter smaller than 150 microns for delivery to onboard science instruments. The sieving behavior of the testbed hardware should be similar to the Flight hardware for the results to be meaningful. The elastodynamic behavior of both sieves was studied analytically using the Rayleigh Ritz method in conjunction with classical plate theory. Finite element models were used to determine the mode shapes of both designs, and comparisons between the natural frequencies and mode shapes were made. The analysis predicts that the performance of the CMTB Thwacker will closely resemble the performance of the Flight Thwacker within the expected steady state operating regime. Excitations of the testbed hardware that will mimic the flight hardware were recommended, as were those that will improve the efficiency of the sieving process.

  20. Hardware removal after osseous free flap reconstruction.

    Science.gov (United States)

    Day, Kristine E; Desmond, Renee; Magnuson, J Scott; Carroll, William R; Rosenthal, Eben L

    2014-01-01

    Identifying risk factors for hardware removal in patients undergoing mandibular reconstruction with vascularized osseous free flaps remains a challenge. The purpose of this study is to identify potential risk factors, including osteocutaneous radial forearm versus fibular flap, for need for removal and to describe the fate of implanted hardware. Case series with chart review Setting Academic tertiary care medical center. Two hundred thirteen patients undergoing 227 vascularized osseous mandibular reconstructions between the years 2004 and 2012. Data were compiled through a manual chart review, and patients incurring hardware removals were identified. Thirty-four of 213 evaluable vascularized osseous free flaps (16%) underwent surgical removal of hardware. The average length of time to removal was 16.2 months (median 10 months), with the majority of removals occurring within the first year. Osteocutaneous radial forearm free flaps (OCRFFF) incurred a slightly higher percentage of hardware removals (9.9%) compared to fibula flaps (6.1%). Partial removal was performed in 8 of 34 cases, and approximately 38% of these required additional surgery for removal. Hardware removal was associated with continued tobacco use after mandibular reconstruction (P = .03). Removal of the supporting hardware most commonly occurs from infection or exposure in the first year. In the majority of cases the bone is well healed and the problem resolves with removal.

  1. Field Programmable Gate Array (FPGA) Based Software Defined Radio (SDR) Design

    Science.gov (United States)

    2009-03-01

    processing ( DSP ) technology create an ongoing requirement for research and development (R&D), which is both costly and time consuming. These factors...As a result, advances in communications techniques and digital signals processing ( DSP ) technology create an ongoing requirement for research and...HDLs: Verilog and Very High Speed Integrated Circuit (VHSIC) Hardware Description Language ( VHDL ). There are advantages to each, but that discussion

  2. Design of a 6-bit CMOS digital radio frequency memory

    Science.gov (United States)

    Kranz, Gordon M.; Mehalic, Mark

    The authors describe the implementation of a digital radio frequency memory (DRFM) on a single integrated circuit. A VHSIC Hardware Description Language (VHDL) model of the DRFM was completed and used to design the VLSI components of the DRFM architecture. The model performed the specified time and frequency shift functions. A DRFM, with a 1K memory, a control unit, and a digital single-sideband modulator (DSSM) has been placed onto a silicon single chip layout design.

  3. MM&T for VHSIC Multichip Packages

    Science.gov (United States)

    1989-09-20

    Industrial Park New Bedford, MA 02745 2. HI-Rel Products Incorporated (062590) 16 Plains Road Essex, CT 06426 MANUFACTURER’S PART NO. PLATING PART...Connector Pin No. vss 4 51 56 6 53 57 11 S 24 26 30 LL VCC B 55 43 7 9 U Y 27 29 35 All 18 57 18 A12 V 59 19 DQ0 /DQ9 31 61 11/12 A DQIIDQIO KK 63 13/14 DQ2...data. VI. THE R-L-C LABCOM PACKAGE CHARACTERIZATION - MODEL A. Model transformation 1. The distributed element model as described in paragraph II will be

  4. A Hardware Filesystem Implementation with Multidisk Support

    National Research Council Canada - National Science Library

    Mendon, Ashwin A; Schmidt, Andrew G; Sass, Ron

    2009-01-01

    .... This article describes one such innovation: a filesystem implemented in hardware. This has the potential of improving the performance of data-intensive applications by connecting secondary storage directly to FPGA compute accelerators...

  5. Hardware device binding and mutual authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  6. Hardware-in-the-Loop Testing

    Data.gov (United States)

    Federal Laboratory Consortium — RTC has a suite of Hardware-in-the Loop facilities that include three operational facilities that provide performance assessment and production acceptance testing of...

  7. Movie Description

    OpenAIRE

    Rohrbach, A; A Torabi; Rohrbach, M.; Tandon, N.; C.; Pal; Larochelle, H; Courville, A.; Schiele, B.

    2017-01-01

    Audio Description (AD) provides linguistic descriptions of movies and allows visually impaired people to follow a movie along with their peers. Such descriptions are by design mainly visual and thus naturally form an interesting data source for computer vision and computational linguistics. In this work we propose a novel dataset which contains transcribed ADs, which are temporally aligned to full length movies. In addition we also collected and aligned movie scripts used in prior work and co...

  8. IDD Archival Hardware Architecture and Workflow

    Energy Technology Data Exchange (ETDEWEB)

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  9. Implementation of Hardware Accelerators on Zynq

    OpenAIRE

    Toft, Jakob Kenn; Nannarelli, Alberto

    2016-01-01

    In the recent years it has become obvious that the performance of general purpose processors are having trouble meeting the requirements of high performance computing applications of today. This is partly due to the relatively high power consumption, compared to the performance, of general purpose processors, which has made hardware accelerators an essential part of several datacentres and the worlds fastest super-computers. In this work, two different hardware accelerators were implemented o...

  10. Cooperative communications hardware, channel and PHY

    CERN Document Server

    Dohler, Mischa

    2010-01-01

    Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

  11. Software for Managing Inventory of Flight Hardware

    Science.gov (United States)

    Salisbury, John; Savage, Scott; Thomas, Shirman

    2003-01-01

    The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

  12. Multi-channel hardware and software complex for monitoring and analysing vibrosignals

    OpenAIRE

    Grenke, V. V.; Shakirov, I. V.; Samoylov, А. М.

    2007-01-01

    The description of complex construction and operation principles for vibrosignal analysis is presented. The distinguishing feature of the complex is application of the wavelet analysis method. Peculiarities of wavelet transformation when solving the problems of mechanical system vibrodiagnostics in comparison with the Fourier analysis are shown. Hardware and software model of measuring complex has been created; its tests have been carries out.

  13. A two step hardware design method using CλaSH

    NARCIS (Netherlands)

    Wester, Rinse; Baaij, C.P.R.; Kuper, Jan

    2012-01-01

    In order to effectively utilize the growing number of resources available on FPGAs, higher level abstraction mechanisms are needed to deal with increasing complexity resulting from large designs. Functional hardware description languages, like the CλaSH HDL, offer adequate abstraction mechanisms

  14. Descriptive Research

    DEFF Research Database (Denmark)

    Wigram, Anthony Lewis

    2003-01-01

    starts will allow effect size calculations to be made in order to evaluate effect over time. Given the difficulties in undertaking controlled experimental studies in the creative arts therapies, descriptive research methods offer a way of quantifying effect through descriptive statistical analysis...

  15. Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters

    Energy Technology Data Exchange (ETDEWEB)

    Goebel, J

    2004-02-27

    Without stable hardware any program will fail. The frustration and expense of supporting bad hardware can drain an organization, delay progress, and frustrate everyone involved. At Stanford Linear Accelerator Center (SLAC), we have created a testing method that helps our group, SLAC Computer Services (SCS), weed out potentially bad hardware and purchase the best hardware at the best possible cost. Commodity hardware changes often, so new evaluations happen periodically each time we purchase systems and minor re-evaluations happen for revised systems for our clusters, about twice a year. This general framework helps SCS perform correct, efficient evaluations. This article outlines SCS's computer testing methods and our system acceptance criteria. We expanded the basic ideas to other evaluations such as storage, and we think the methods outlined in this article has helped us choose hardware that is much more stable and supportable than our previous purchases. We have found that commodity hardware ranges in quality, so systematic method and tools for hardware evaluation were necessary. This article is based on one instance of a hardware purchase, but the guidelines apply to the general problem of purchasing commodity computer systems for production computational work.

  16. Digital Hardware Realization of Forward and Inverse Kinematics for a Five-Axis Articulated Robot Arm

    Directory of Open Access Journals (Sweden)

    Bui Thi Hai Linh

    2015-01-01

    Full Text Available When robot arm performs a motion control, it needs to calculate a complicated algorithm of forward and inverse kinematics which consumes much CPU time and certainty slows down the motion speed of robot arm. Therefore, to solve this issue, the development of a hardware realization of forward and inverse kinematics for an articulated robot arm is investigated. In this paper, the formulation of the forward and inverse kinematics for a five-axis articulated robot arm is derived firstly. Then, the computations algorithm and its hardware implementation are described. Further, very high speed integrated circuits hardware description language (VHDL is applied to describe the overall hardware behavior of forward and inverse kinematics. Additionally, finite state machine (FSM is applied for reducing the hardware resource usage. Finally, for verifying the correctness of forward and inverse kinematics for the five-axis articulated robot arm, a cosimulation work is constructed by ModelSim and Simulink. The hardware of the forward and inverse kinematics is run by ModelSim and a test bench which generates stimulus to ModelSim and displays the output response is taken in Simulink. Under this design, the forward and inverse kinematics algorithms can be completed within one microsecond.

  17. Quantitative hardware prediction modeling for hardware/software co-design

    NARCIS (Netherlands)

    Meeuws, R.J.

    2012-01-01

    Hardware estimation is an important factor in Hardware/Software Co-design. In this dissertation, we present the Quipu Modeling Approach, a high-level quantitative prediction model for HW/SW Partitioning using statistical methods. Our approach uses linear regression between software complexity

  18. Descriptive statistics.

    Science.gov (United States)

    Shi, Runhua; McLarty, Jerry W

    2009-10-01

    In this article, we introduced basic concepts of statistics, type of distributions, and descriptive statistics. A few examples were also provided. The basic concepts presented herein are only a fraction of the concepts related to descriptive statistics. Also, there are many commonly used distributions not presented herein, such as Poisson distributions for rare events and exponential distributions, F distributions, and logistic distributions. More information can be found in many statistics books and publications.

  19. Hardware Acceleration of Adaptive Neural Algorithms.

    Energy Technology Data Exchange (ETDEWEB)

    James, Conrad D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-11-01

    As tradit ional numerical computing has faced challenges, researchers have turned towards alternative computing approaches to reduce power - per - computation metrics and improve algorithm performance. Here, we describe an approach towards non - conventional computing that strengthens the connection between machine learning and neuroscience concepts. The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) project ha s develop ed neural machine learning algorithms and hardware for applications in image processing and cybersecurity. While machine learning methods are effective at extracting relevant features from many types of data, the effectiveness of these algorithms degrades when subjected to real - world conditions. Our team has generated novel neural - inspired approa ches to improve the resiliency and adaptability of machine learning algorithms. In addition, we have also designed and fabricated hardware architectures and microelectronic devices specifically tuned towards the training and inference operations of neural - inspired algorithms. Finally, our multi - scale simulation framework allows us to assess the impact of microelectronic device properties on algorithm performance.

  20. A Hardware Abstraction Layer in Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas

    2011-01-01

    Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access...... to devices, direct memory access, and interrupt handling to some underlying operating system or kernel, but in the embedded systems domain resources are scarce and a Java Virtual Machine (JVM) without an underlying middleware is an attractive architecture. The contribution of this article is a proposal...... for Java packages with hardware objects and interrupt handlers that interface to such a JVM. We provide implementations of the proposal directly in hardware, as extensions of standard interpreters, and finally with an operating system middleware. The latter solution is mainly seen as a migration path...

  1. Economic impact of syndesmosis hardware removal.

    Science.gov (United States)

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system

  2. Quantum neuromorphic hardware for quantum artificial intelligence

    Science.gov (United States)

    Prati, Enrico

    2017-08-01

    The development of machine learning methods based on deep learning boosted the field of artificial intelligence towards unprecedented achievements and application in several fields. Such prominent results were made in parallel with the first successful demonstrations of fault tolerant hardware for quantum information processing. To which extent deep learning can take advantage of the existence of a hardware based on qubits behaving as a universal quantum computer is an open question under investigation. Here I review the convergence between the two fields towards implementation of advanced quantum algorithms, including quantum deep learning.

  3. Human Centered Hardware Modeling and Collaboration

    Science.gov (United States)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  4. Hardware Accelerated Sequence Alignment with Traceback

    Directory of Open Access Journals (Sweden)

    Scott Lloyd

    2009-01-01

    in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

  5. Introduction to 6800/6802 microprocessor systems hardware, software and experimentation

    CERN Document Server

    Simpson, Robert J

    1987-01-01

    Introduction to 6800/6802 Microprocessor Systems: Hardware, Software and Experimentation introduces the reader to the features, characteristics, operation, and applications of the 6800/6802 microprocessor and associated family of devices. Many worked examples are included to illustrate the theoretical and practical aspects of the 6800/6802 microprocessor.Comprised of six chapters, this book begins by presenting several aspects of digital systems before introducing the concepts of fetching and execution of a microprocessor instruction. Details and descriptions of hardware elements (MPU, RAM, RO

  6. Design considerations for space flight hardware

    Science.gov (United States)

    Glover, Daniel

    1990-01-01

    The environmental and design constraints are reviewed along with some insight into the established design and quality assurance practices that apply to low earth orbit (LEO) space flight hardware. It is intended as an introduction for people unfamiliar with space flight considerations. Some basic data and a bibliography are included.

  7. Enabling Open Hardware through FOSS tools

    CERN Multimedia

    CERN. Geneva

    2016-01-01

    Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

  8. Remote hardware-reconfigurable robotic camera

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

    2001-10-01

    In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

  9. QCE : A Simulator for Quantum Computer Hardware

    NARCIS (Netherlands)

    Michielsen, Kristel; Raedt, Hans De

    2003-01-01

    The Quantum Computer Emulator (QCE) described in this paper consists of a simulator of a generic, general purpose quantum computer and a graphical user interface. The latter is used to control the simulator, to define the hardware of the quantum computer and to debug and execute quantum algorithms.

  10. Proof Carrying Hardware based IP Protection

    Science.gov (United States)

    2017-03-01

    service to the hardware. Note that in this paper, we only consider Trojans which can be activated by a specific digital input vector. Further, we...acquisition,” IEEE Transactions on Information Forensics and Security, vol. 7, no. 1, pp. 25–40, 2012. [7] Y. Jin, B. Yang, and Y. Makris, “Cycle-accurate

  11. Efficient Runtime Management of Reconfigurable Hardware Resources

    NARCIS (Netherlands)

    Marconi, T.

    2011-01-01

    Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford

  12. Environmental Control System Software & Hardware Development

    Science.gov (United States)

    Vargas, Daniel Eduardo

    2017-01-01

    ECS hardware: (1) Provides controlled purge to SLS Rocket and Orion spacecraft. (2) Provide mission-focused engineering products and services. ECS software: (1) NASA requires Compact Unique Identifiers (CUIs); fixed-length identifier used to identify information items. (2) CUI structure; composed of nine semantic fields that aid the user in recognizing its purpose.

  13. Hardware Accelerated Point Rendering of Isosurfaces

    DEFF Research Database (Denmark)

    Bærentzen, Jakob Andreas; Christensen, Niels Jørgen

    2003-01-01

    and that the advantage of rendering points as opposed to triangles increases with the size and complexity of the volumes. To gauge the visual quality of future hardware accelerated point rendering schemes, we have implemented a software based point rendering method and compare the quality to both MC and our OpenGL based...

  14. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  15. Computer hardware for radiologists: Part I

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  16. Advanced hardware design for error correcting codes

    CERN Document Server

    Coussy, Philippe

    2015-01-01

    This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

  17. HARDWARE AND SOFTWARE STATUS OF QCDOC.

    Energy Technology Data Exchange (ETDEWEB)

    BOYLE,P.A.; CHEN,D.; CHRIST,N.H.; PETROV.K.; ET AL.

    2003-07-15

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  18. The hardware accelerator array for logic simulation

    Energy Technology Data Exchange (ETDEWEB)

    Hansen, N H [Washington State Univ., Pullman, WA (USA)

    1991-05-01

    Hardware acceleration exploits the parallelism inherent in large circuit simulations to achieve significant increases in performance. Simulation accelerators have been developed based on the compiled code algorithm or the event-driven algorithm. The greater flexibility of the event-driven algorithm has resulted in several important developments in hardware acceleration architecture. Some popular commercial products have been developed based on the event-driven algorithm and data-flow architectures. Conventional data-flow architectures require complex switching networks to distribute operands among processing elements resulting in considerable overhead. An accelerator array architecture based on a nearest-neighbor communication has been developed in this thesis. The design is simulated in detail at the behavioral level. Its performance is evaluated and shown to be superior to that of a conventional data-flow accelerator. 14 refs., 48 figs., 5 tabs.

  19. [Descriptive statistics].

    Science.gov (United States)

    Rendón-Macías, Mario Enrique; Villasís-Keever, Miguel Ángel; Miranda-Novales, María Guadalupe

    2016-01-01

    Descriptive statistics is the branch of statistics that gives recommendations on how to summarize clearly and simply research data in tables, figures, charts, or graphs. Before performing a descriptive analysis it is paramount to summarize its goal or goals, and to identify the measurement scales of the different variables recorded in the study. Tables or charts aim to provide timely information on the results of an investigation. The graphs show trends and can be histograms, pie charts, "box and whiskers" plots, line graphs, or scatter plots. Images serve as examples to reinforce concepts or facts. The choice of a chart, graph, or image must be based on the study objectives. Usually it is not recommended to use more than seven in an article, also depending on its length.

  20. Particle Transport Simulation on Heterogeneous Hardware

    CERN Multimedia

    CERN. Geneva

    2014-01-01

    CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

  1. Hex-Chrome Free Hardware - BAE Experience

    Science.gov (United States)

    2010-06-01

    Trane S 3201063A1 • TRW TS 2-25-60, Class A • Volkswagen TL 233 • Volvo VCS5737.29, .19 6/23/2010 Magni is one of several coatings, others such...installation and part must be revised. • Example: Panther FOV identified approximately 500 fasteners/ hardware that are being updated to “clean” within...particular program require coordination and funding to revise/ update (ex: MMPV common with MRAP) COTS, Government furnished, proprietary items and

  2. Instrumentation Hardware Abstraction Language (IHAL) Handbook

    Science.gov (United States)

    2017-01-01

    guidelines and thereby eliminating any misinterpretations that may exist. The RCC IRIG 106 sets forth standards for various aspects of telemetry (TM... community . At the time the task was initiated, IHAL had been shown to support configuration of analog signal conditioning hardware and pulse code...configurations were displayed in a single view. The settings on each device were then changed and immediately communicated to the appropriate vendor

  3. A hardware implementation of neural network with modified HANNIBAL architecture

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Bum youb; Chung, Duck Jin [Inha University, Inchon (Korea, Republic of)

    1996-03-01

    A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). 14 refs., 10 figs., 3 tabs.

  4. A Hardware Lab Anywhere At Any Time

    Directory of Open Access Journals (Sweden)

    Tobias Schubert

    2004-12-01

    Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

  5. Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

    Science.gov (United States)

    Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

    2001-01-01

    Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the

  6. Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property

    Science.gov (United States)

    2015-05-22

    hardware intellectual property (PCHIP) framework, which aims to ensure the trustworthiness of third-party hardware IPs utilizing formal methods. We...published in non peer-reviewed journals: Final Report: Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property Report Title By...borrowing ideas from the proof carrying code (PCC) in software domain, in this project we introduced the proof carrying hardware intellectual property

  7. The Impact of Flight Hardware Scavenging on Space Logistics

    Science.gov (United States)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  8. Safe to Fly: Certifying COTS Hardware for Spaceflight

    Science.gov (United States)

    Fichuk, Jessica L.

    2011-01-01

    Providing hardware for the astronauts to use on board the Space Shuttle or International Space Station (ISS) involves a certification process that entails evaluating hardware safety, weighing risks, providing mitigation, and verifying requirements. Upon completion of this certification process, the hardware is deemed safe to fly. This process from start to finish can be completed as quickly as 1 week or can take several years in length depending on the complexity of the hardware and whether the item is a unique custom design. One area of cost and schedule savings that NASA implements is buying Commercial Off the Shelf (COTS) hardware and certifying it for human spaceflight as safe to fly. By utilizing commercial hardware, NASA saves time not having to develop, design and build the hardware from scratch, as well as a timesaving in the certification process. By utilizing COTS hardware, the current detailed certification process can be simplified which results in schedule savings. Cost savings is another important benefit of flying COTS hardware. Procuring COTS hardware for space use can be more economical than custom building the hardware. This paper will investigate the cost savings associated with certifying COTS hardware to NASA s standards rather than performing a custom build.

  9. Is Hardware Removal Recommended after Ankle Fracture Repair?

    Directory of Open Access Journals (Sweden)

    Hong-Geun Jung

    2016-01-01

    Full Text Available The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients’ daily activities. This study was conducted on 80 consecutive cases (78 patients treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6 and decreased to 1.3 (range 0 to 6 after removal. 58 (72.5% patients experienced improved ankle stiffness and 65 (81.3% less discomfort while walking on uneven ground and 63 (80.8% patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal.

  10. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on...

  11. Unifying Approach to Software and Hardware Design for Scientific Calculations

    OpenAIRE

    Litvinov, G. L.; Maslov, V. P.; Rodionov, A. Ya.

    1999-01-01

    A unifying approach to software and hardware design generated by ideas of Idempotent Mathematics is discussed. The so-called idempotent correspondence principle for algorithms, programs and hardware units is described. A software project based on this approach is presented. Key words: universal algorithms, idempotent calculus, software design, hardware design, object oriented programming

  12. Is Hardware Removal Recommended after Ankle Fracture Repair?

    Science.gov (United States)

    Jung, Hong-Geun; Kim, Jin-Il; Park, Jae-Yong; Park, Jong-Tae; Eom, Joon-Sang; Lee, Dong-Oh

    2016-01-01

    The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients' daily activities. This study was conducted on 80 consecutive cases (78 patients) treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6) and decreased to 1.3 (range 0 to 6) after removal. 58 (72.5%) patients experienced improved ankle stiffness and 65 (81.3%) less discomfort while walking on uneven ground and 63 (80.8%) patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal.

  13. Computer hardware for radiologists: Part 2

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

  14. Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

    Directory of Open Access Journals (Sweden)

    Ikbel Belaid

    2011-01-01

    Full Text Available Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.

  15. Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

    Science.gov (United States)

    Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

    2008-01-01

    This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  16. VHDL 101 everything you need to know to get started

    CERN Document Server

    Kafig, William

    2011-01-01

    VHDL (VHSIC Hardware Description Language) is a hardware programming language commonly used for FPGA or ASIC designs. FPGAs and the like are often found within larger applications such as cell phones, medical imagers, and personal media devices. As these devices are becoming more ubiquitous so the need for engineers fluent in VHDL design grows. Engineers commonly face an immediate need to learn a language or technique quickly and this book can answer that requirement. Bill Kafig, Xilinx, swiftly brings the reader up to speed on techniques and functions commonly used as well as commands and dat

  17. Methodology for Assessing Reusability of Spaceflight Hardware

    Science.gov (United States)

    Childress-Thompson, Rhonda; Thomas, L. Dale; Farrington, Phillip

    2017-01-01

    In 2011 the Space Shuttle, the only Reusable Launch Vehicle (RLV) in the world, returned to earth for the final time. Upon retirement of the Space Shuttle, the United States (U.S.) no longer possessed a reusable vehicle or the capability to send American astronauts to space. With the National Aeronautics and Space Administration (NASA) out of the RLV business and now only pursuing Expendable Launch Vehicles (ELV), not only did companies within the U.S. start to actively pursue the development of either RLVs or reusable components, but entities around the world began to venture into the reusable market. For example, SpaceX and Blue Origin are developing reusable vehicles and engines. The Indian Space Research Organization is developing a reusable space plane and Airbus is exploring the possibility of reusing its first stage engines and avionics housed in the flyback propulsion unit referred to as the Advanced Expendable Launcher with Innovative engine Economy (Adeline). Even United Launch Alliance (ULA) has announced plans for eventually replacing the Atlas and Delta expendable rockets with a family of RLVs called Vulcan. Reuse can be categorized as either fully reusable, the situation in which the entire vehicle is recovered, or partially reusable such as the National Space Transportation System (NSTS) where only the Space Shuttle, Space Shuttle Main Engines (SSME), and Solid Rocket Boosters (SRB) are reused. With this influx of renewed interest in reusability for space applications, it is imperative that a systematic approach be developed for assessing the reusability of spaceflight hardware. The partially reusable NSTS offered many opportunities to glean lessons learned; however, when it came to efficient operability for reuse the Space Shuttle and its associated hardware fell short primarily because of its two to four-month turnaround time. Although there have been several attempts at designing RLVs in the past with the X-33, Venture Star and Delta Clipper

  18. List search hardware for interpretive software

    CERN Document Server

    Altaber, Jacques; Mears, B; Rausch, R

    1979-01-01

    Interpreted languages, e.g. BASIC, are simple to learn, easy to use, quick to modify and in general 'user-friendly'. However, a critically time consuming process during interpretation is that of list searching. A special microprogrammed device for fast list searching has therefore been developed at the SPS Division of CERN. It uses bit- sliced hardware. Fast algorithms perform search, insert and delete of a six-character name and its value in a list of up to 1000 pairs. The prototype shows retrieval times of the order of 10-30 microseconds. (11 refs).

  19. Development of Hardware Dual Modality Tomography System

    Directory of Open Access Journals (Sweden)

    R. M. Zain

    2009-06-01

    Full Text Available The paper describes the hardware development and performance of the Dual Modality Tomography (DMT system. DMT consists of optical and capacitance sensors. The optical sensors consist of 16 LEDs and 16 photodiodes. The Electrical Capacitance Tomography (ECT electrode design use eight electrode plates as the detecting sensor. The digital timing and the control unit have been developing in order to control the light projection of optical emitters, switching the capacitance electrodes and to synchronize the operation of data acquisition. As a result, the developed system is able to provide a maximum 529 set data per second received from the signal conditioning circuit to the computer.

  20. Hardware Trigger Processor for the MDT System

    CERN Document Server

    Costa De Paiva, Thiago; The ATLAS collaboration

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the ATLAS Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  1. Introduction to Hardware Security and Trust

    CERN Document Server

    Wang, Cliff

    2012-01-01

    The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

  2. ISS Logistics Hardware Disposition and Metrics Validation

    Science.gov (United States)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  3. ARM assembly language with hardware experiments

    CERN Document Server

    Elahi, Ata

    2015-01-01

    This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

  4. Locating hardware faults in a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  5. Communication Estimation for Hardware/Software Codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus......This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended...... it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill...

  6. Hardware codec for digital HDTV recording

    Science.gov (United States)

    Stammnitz, Peter; Boettcher, K.; Grueneberg, Kirsten A.; Hoefker, U.; Klein, H.

    1993-11-01

    For the purpose of digital recording of HDTV signals (EUREKA standard, 1250/50/2:1) a codec has been realized (HDI-codec) which can reduce the initial data rate from 1,152 GBit/s down to one fifth. According to the desired reduction, the playtime of a digital VCR (Video Cassette Recorder) can be increased from about 40 - 60 minutes up to at least the length of a feature film. This paper describes the hardware realization of the data rate reduction codec. Algorithms utilized for data rate reduction are adaptive intraframe/intrafield discrete cosine transform (DCT), adaptive quantization and variable length encoding (VLC). Interframe editing, multiple copy and shuttle mode are supported by a special codec architecture.

  7. Theorem Proving in Intel Hardware Design

    Science.gov (United States)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  8. Compressive Sensing Image Sensors-Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Shahram Shirani

    2013-04-01

    Full Text Available The compressive sensing (CS paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.

  9. Handbook of hardware/software codesign

    CERN Document Server

    Teich, Jürgen

    2017-01-01

    This handbook presents fundamental knowledge on the hardware/software (HW/SW) codesign methodology. Contributing expert authors look at key techniques in the design flow as well as selected codesign tools and design environments, building on basic knowledge to consider the latest techniques. The book enables readers to gain real benefits from the HW/SW codesign methodology through explanations and case studies which demonstrate its usefulness. Readers are invited to follow the progress of design techniques through this work, which assists readers in following current research directions and learning about state-of-the-art techniques. Students and researchers will appreciate the wide spectrum of subjects that belong to the design methodology from this handbook. .

  10. Current conveyors variants, applications and hardware implementations

    CERN Document Server

    Senani, Raj; Singh, A K

    2015-01-01

    This book serves as a single-source reference to Current Conveyors and their use in modern Analog Circuit Design. The authors describe the various types of current conveyors discovered over the past 45 years, details of all currently available, off-the-shelf integrated circuit current conveyors, and implementations of current conveyors using other, off-the-shelf IC building blocks. Coverage includes prominent bipolar/CMOS/Bi-CMOS architectures of current conveyors, as well as all varieties of starting from third generation current conveyors to universal current conveyors, their implementations and applications. •Describes all commercially available off-the-shelf IC current conveyors, as well as hardware implementations of current conveyors using other off-the-shelf ICs; • Describes numerous variants of current conveyors evolved over the past forty five years; • Describes a number of Bipolar/CMOS/Bi-CMOS architectures of current conveyors, along with their characteristic features; • Includes a comprehe...

  11. Protection of Accelerator Hardware: RF systems

    CERN Document Server

    Kim, S.-H.

    2016-01-01

    The radio-frequency (RF) system is the key element that generates electric fields for beam acceleration. To keep the system reliable, a highly sophisticated protection scheme is required, which also should be designed to ensure a good balance between beam availability and machine safety. Since RF systems are complex, incorporating high-voltage and high-power equipment, a good portion of machine downtime typically comes from RF systems. Equipment and component damage in RF systems results in long and expensive repairs. Protection of RF system hardware is one of the oldest machine protection concepts, dealing with the protection of individual high-power RF equipment from breakdowns. As beam power increases in modern accelerators, the protection of accelerating structures from beam-induced faults also becomes a critical aspect of protection schemes. In this article, an overview of the RF system is given, and selected topics of failure mechanisms and examples of protection requirements are introduced.

  12. Perspectives in Simulation Hardware and Software Architecture

    Directory of Open Access Journals (Sweden)

    W.O. Grierson

    1985-10-01

    Full Text Available Historically, analog and hybrid computer systems have provided effective real-time solutions for the simulation of large dynamic systems. In the mid 1970s, ADI concluded that these systems were no longer adequate to meet the demands of larger, more complex models and the demand for greater simulation accuracy. The decision was to design an all-digital system to satisfy these growing requirements (see Gilbert and Howe, (1978. This all-digital approach was called the SYSTEM 10. The SYSTEM 10 has been effective in solving time-critical simulation problems and in replacing the previous approach of utilizing hybrid computers. Recent advances in 100 K emitter coupled logic (ECL now make it possible to support a new generation of equipment that expands modeling capabilities to serve simulation needs. The hardware and software concepts of this system, called the SYSTEM 100, are the subject of this paper.

  13. Extravehicular Activity (EVA) Hardware & Operations Overview

    Science.gov (United States)

    Moore, Sandra; Marmolejo, Jose

    2014-01-01

    The objectives of this presentation are to: Define Extravehicular Activity (EVA), identify the reasons for conducting an EVA, and review the role that EVA has played in the space program; Identify the types of EVAs that may be performed; Describe some of the U.S. Space Station equipment and tools that are used during an EVA, such as the Extravehicular Mobility Unit (EMU), the Simplified Aid For EVA Rescue (SAFER), the International Space Station (ISS) Joint Airlock and Russian Docking Compartment 1 (DC-1), and EVA Tools & Equipment; Outline the methods and procedures of EVA Preparation, EVA, and Post-EVA operations; Describe the Russian spacesuit used to perform an EVA; Provide a comparison between U.S. and Russian spacesuit hardware and EVA support; and Define the roles that different training facilities play in EVA training.

  14. Microprocessors & their operating systems a comprehensive guide to 8, 16 & 32 bit hardware, assembly language & computer architecture

    CERN Document Server

    Holland, R C

    1989-01-01

    Provides a comprehensive guide to all of the major microprocessor families (8, 16 and 32 bit). The hardware aspects and software implications are described, giving the reader an overall understanding of microcomputer architectures. The internal processor operation of each microprocessor device is presented, followed by descriptions of the instruction set and applications for the device. Software considerations are expanded with descriptions and examples of the main high level programming languages (BASIC, Pascal and C). The book also includes detailed descriptions of the three main operatin

  15. Algorithm validation and hardware design interactive approach

    OpenAIRE

    Lazarescu, Mihai Teodor; M. Sartori

    1996-01-01

    In this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplification

  16. PACE: A dynamic programming algorithm for hardware/software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper presents the PACE partitioning algorithm which is used in the LYCOS co-synthesis system for partitioning control/dataflow graphs into hardware and software parts. The algorithm is a dynamic programming algorithm which solves both the problem of minimizing system execution time...... communication model and thus attempts to minimize communication overhead. The time-complexity of the algorithm is O(n2·𝒜) and the space-complexity is O(n·𝒜) where 𝒜 is the total area of the hardware chip and n the number of code fragments which may be placed in either hardware or software...... with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic...

  17. Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

    Energy Technology Data Exchange (ETDEWEB)

    Williamson, Douglas Alan [Univ. of Florida, Gainesville, FL (United States)

    1991-01-01

    Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas & Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States` utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste.

  18. Implementation of Karp-Rabin string matching algorithm in reconfigurable hardware for network intrusion prevention system

    Science.gov (United States)

    Botwicz, Jakub; Buciak, Piotr; Sapiecha, Piotr

    2006-03-01

    Intrusion Prevention Systems (IPSs) have become widely recognized as a powerful tool and an important element of IT security safeguards. The essential feature of network IPSs is searching through network packets and matching multiple strings, that are fingerprints of known attacks. String matching is highly resource consuming and also the most significant bottleneck of IPSs. In this article an extension of the classical Karp-Rabin algorithm and its implementation architectures were examined. The result is a software, which generates a source code of a string matching module in hardware description language, that could be easily used to create an Intrusion Prevention System implemented in reconfigurable hardware. The prepared module matches the complete set of Snort IPS signatures achieving throughput of over 2 Gbps on an Altera Stratix I1 evaluation board. The most significant advantage of the proposed architecture is that the update of the patterns database does not require reconfiguration of the circuitry.

  19. ANNarchy: a code generation approach to neural simulations on parallel hardware

    Directory of Open Access Journals (Sweden)

    Julien eVitay

    2015-07-01

    Full Text Available Many modern neural simulators focus on the simulation of networks of spiking neurons on parallel hardware. Another important framework in computational neuroscience, rate-coded neural networks, is mostly difficult or impossible to implement using these simulators. We present here the ANNarchy (Artificial Neural Networks architect neural simulator, which allows to easily define and simulate rate-coded and spiking networks, as well as combinations of both. The interface in Python has been designed to be close to the PyNN interface, while the definition of neuron and synapse models can be specified using an equation-oriented mathematical description similar to the Brian neural simulator. This information is used to generate C++ code that will efficiently perform the simulation on the chosen parallel hardware (multi-core system or graphical processing unit. Several numerical methods are available to transform ordinary differential equations into an efficient C++ code. We compare the parallel performance of the simulator to existing solutions.

  20. Why Open Source Hardware matters and why you should care

    OpenAIRE

    Gürkaynak, Frank K.

    2017-01-01

    Open source hardware is currently where open source software was about 30 years ago. The idea is well received by enthusiasts, there is interest and the open source hardware has gained visible momentum recently, with several well-known universities including UC Berkeley, Cambridge and ETH Zürich actively working on large projects involving open source hardware, attracting the attention of companies big and small. But it is still not quite there yet. In this talk, based on my experience on the...

  1. Hardware-Enabled Security Through On-Chip Reconfigurable Fabric

    Science.gov (United States)

    2016-02-05

    SECURITY CLASSIFICATION OF: The goal of this project was to enable hardware -based security techniques on future microprocessors in a way that they...can be added and updated after fabrication, similar to software, while maintaining the efficiency and the security of hardware . For this purpose, the...Mar-2011 31-May-2014 Approved for Public Release; Distribution Unlimited Final Report: Hardware -Enabled Security Through On-Chip Reconfigurable Fabric

  2. Reliable software for unreliable hardware a cross layer perspective

    CERN Document Server

    Rehman, Semeen; Henkel, Jörg

    2016-01-01

    This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

  3. An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

    Science.gov (United States)

    Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

    2015-01-01

    One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

  4. Hardware-and-software-based collective communication on the Quadrics network.

    Energy Technology Data Exchange (ETDEWEB)

    Petrini, F. (Fabrizio); Coll, S. (Salvador); Frachtemberg, E. (Eitan); Hoisie, A. (Adolfy)

    2001-01-01

    The efficient implementation of collective communication patterns in a parallel machine is a challenging design effort, that requires the solution of many problems. In this paper we present an in-depth description of how the Quadrics network supports both hardware- and software-based collectives. We describe the main features of the two building blocks of this network, a network interface that can perform zero-copy user-level communication and a wormhole switch. We also focus our attention on the routing and $ow control algorithms, deadlock avoidance and on how the processing nodes are integrated in a global, virtual shared memory. Experimental results conducted on 64-node AlphaServer cluster indicate that the time to complete the hardware-based barrier synchronization on the whole network is as low as 6 ps, with veiy good scalability. Good latency and scalability are also achieved with the software-based synchronization, which takes about 15 ps. With the broadcast, similar performance is achieved by the hardware- and software-based implementations, which can deliver messages of up to 256 b,ytes in 13 ps and can get a sustained bandwidth of 288 Mbyteshec on all the nodes, with wressages larger than 64KB. The hardware-based barrier is almost insensitive to the network congestion, with 93% of the synchronizations taking less than 20 ps. On the other hand, the software based implementation suflers from a signif cant performance degradation. In high load environments the hardware broadcast maintains a reasonably good performance, delivering messages up to 2KB in 200 ps, while the software broadcast suffers from slightly higher latencies inherited by the synchronization mechanism.

  5. A Hardware Track Finder for ATLAS Trigger

    CERN Document Server

    Volpi, G; The ATLAS collaboration; Andreazza, A; Citterio, M; Favareto, A; Liberali, V; Meroni, C; Riva, M; Sabatini, F; Stabile, A; Annovi, A; Beretta, M; Castegnaro, A; Bevacqua, V; Crescioli, F; Francesco, C; Dell'Orso, M; Giannetti, P; Magalotti, D; Piendibene, M; Roda, C; Sacco, I; Tripiccione, R; Fabbri, L; Franchini, M; Giorgi, F; Giannuzzi, F; Lasagni, F; Sbarra, C; Valentinetti, S; Villa, M; Zoccoli, A; Lanza, A; Negri, A; Vercesi, V; Bogdan, M; Boveia, A; Canelli, F; Cheng, Y; Dunford, M; Li, H L; Kapliy, A; Kim, Y K; Melachrinos, C; Shochet, M; Tang, F; Tang, J; Tuggle, J; Tompkins, L; Webster, J; Atkinson, M; Cavaliere, V; Chang, P; Kasten, M; McCarn, A; Neubauer, M; Hoff, J; Liu, T; Okumura, Y; Olsen, J; Penning, B; Todri, A; Wu, J; Drake, G; Proudfoot, J; Zhang, J; Blair, R; Anderson, J; Auerbach, B; Blazey, G; Kimura, N; Yorita, K; Sakurai, Y; Mitani, T; Iizawa, T

    2012-01-01

    The existing three level ATLAS trigger system is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to ~400 Hz for permanent storage at the LHC design luminosity of 10^34 cm^-2 s^-1. When the LHC reaches beyond the design luminosity, the load on the Level-2 trigger system will significantly increase due to both the need for more sophisticated algorithms to suppress background and the larger event sizes. The Fast TracKer (FTK) is a custom electronics system that will operate at the full Level-1 accepted rate of 100 KHz and provide high quality tracks at the beginning of processing in the Level-2 trigger, by performing track reconstruction in hardware with massive parallelism of associative memories and FPGAs. The performance in important physics areas including b-tagging, tau-tagging and lepton isolation will be demonstrated with the ATLAS MC simulation at different LHC luminosities. The system design will be overviewed. The latest R&D progress of individual components...

  6. Mechanics of Granular Materials labeled hardware

    Science.gov (United States)

    2000-01-01

    Mechanics of Granular Materials (MGM) flight hardware takes two twin double locker assemblies in the Space Shuttle middeck or the Spacehab module. Sand and soil grains have faces that can cause friction as they roll and slide against each other, or even cause sticking and form small voids between grains. This complex behavior can cause soil to behave like a liquid under certain conditions such as earthquakes or when powders are handled in industrial processes. MGM experiments aboard the Space Shuttle use the microgravity of space to simulate this behavior under conditions that carnot be achieved in laboratory tests on Earth. MGM is shedding light on the behavior of fine-grain materials under low effective stresses. Applications include earthquake engineering, granular flow technologies (such as powder feed systems for pharmaceuticals and fertilizers), and terrestrial and planetary geology. Nine MGM specimens have flown on two Space Shuttle flights. Another three are scheduled to fly on STS-107. The principal investigator is Stein Sture of the University of Colorado at Boulder. (Credit: NASA/MSFC).

  7. Hardware platform for multiple mobile robots

    Science.gov (United States)

    Parzhuber, Otto; Dolinsky, D.

    2004-12-01

    This work is concerned with software and communications architectures that might facilitate the operation of several mobile robots. The vehicles should be remotely piloted or tele-operated via a wireless link between the operator and the vehicles. The wireless link will carry control commands from the operator to the vehicle, telemetry data from the vehicle back to the operator and frequently also a real-time video stream from an on board camera. For autonomous driving the link will carry commands and data between the vehicles. For this purpose we have developed a hardware platform which consists of a powerful microprocessor, different sensors, stereo- camera and Wireless Local Area Network (WLAN) for communication. The adoption of IEEE802.11 standard for the physical and access layer protocols allow a straightforward integration with the internet protocols TCP/IP. For the inspection of the environment the robots are equipped with a wide variety of sensors like ultrasonic, infrared proximity sensors and a small inertial measurement unit. Stereo cameras give the feasibility of the detection of obstacles, measurement of distance and creation of a map of the room.

  8. Open Hardware For CERN's Accelerator Control Systems

    CERN Document Server

    van der Bij, E; Ayass, M; Boccardi, A; Cattin, M; Gil Soriano, C; Gousiou, E; Iglesias Gonsálvez, S; Penacoba Fernandez, G; Serrano, J; Voumard, N; Wlostowski, T

    2011-01-01

    The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its ...

  9. Nanorobot Hardware Architecture for Medical Defense.

    Science.gov (United States)

    Cavalcanti, Adriano; Shirinzadeh, Bijan; Zhang, Mingjun; Kretly, Luiz C

    2008-05-06

    This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  10. Nanorobot Hardware Architecture for Medical Defense

    Directory of Open Access Journals (Sweden)

    Luiz C. Kretly

    2008-05-01

    Full Text Available This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  11. Employing ISRU Models to Improve Hardware Design

    Science.gov (United States)

    Linne, Diane L.

    2010-01-01

    An analytical model for hydrogen reduction of regolith was used to investigate the effects of several key variables on the energy and mass performance of reactors for a lunar in-situ resource utilization oxygen production plant. Reactor geometry, reaction time, number of reactors, heat recuperation, heat loss, and operating pressure were all studied to guide hardware designers who are developing future prototype reactors. The effects of heat recuperation where the incoming regolith is pre-heated by the hot spent regolith before transfer was also investigated for the first time. In general, longer reaction times per batch provide a lower overall energy, but also result in larger and heavier reactors. Three reactors with long heat-up times results in similar energy requirements as a two-reactor system with all other parameters the same. Three reactors with heat recuperation results in energy reductions of 20 to 40 percent compared to a three-reactor system with no heat recuperation. Increasing operating pressure can provide similar energy reductions as heat recuperation for the same reaction times.

  12. Flow testing rear face hardware combinations

    Energy Technology Data Exchange (ETDEWEB)

    Haun, F.E. Jr.

    1962-06-01

    The purpose of these tests is to provide necessary laboratory data in support of an R,PEO program in determining the energy loss associated with various hardware size combinations on the rear face of the B-D-F reactors. The original method used to check for critical flow was determined to be faulty. A revised method demonstrated critical flow did occur in the 5/8-inch inconel connector and combination 1 fittings. The remaining fitting combinations with the 5/8-inch inconel and 3/4-inch aluminum connector were not rechecked because of the reaming of the I.D. to permit the continuation of the original tests. During test number 6, audible cavitation was heard with the highest severity at a point midway between pressure points 3 and 4 on the connector. This condition appeared again in tests 6A, 7, and 7A, with incipient cavitation at approximately 40 gpm in each test, regardless of the rear header pressure and/or temperature.

  13. Ultrasound and clinical evaluation of soft-tissue versus hardware biceps tenodesis: is hardware tenodesis worth the cost?

    Science.gov (United States)

    Elkousy, Hussein; Romero, Jose A; Edwards, T Bradley; Gartsman, Gary M; O'Connor, Daniel P

    2014-02-01

    This study assesses the failure rate of soft-tissue versus hardware fixation of biceps tenodesis by ultrasound to determine if the expense of a hardware tenodesis technique is warranted. Seventy-two patients that underwent arthroscopic biceps tenodesis over a 3-year period were evaluated using postoperative ultrasonography and clinical examination. The tenodesis technique employed was either a soft-tissue technique with sutures or an interference screw technique using hardware based on surgeon preference. Patient age was 57.9 years on average with ultrasound and clinical examination done at an average of 9.3 months postoperatively. Thirty-one patients had a hardware technique and 41 a soft-tissue technique. Overall, 67.7% of biceps tenodesis done with hardware were intact, compared with 75.6% for the soft-tissue technique by ultrasound (P = .46). Clinical evaluation indicated that 80.7% of hardware techniques and 78% of soft-tissue techniques were intact. Average material cost to the hospital for the hardware technique was $514.32, compared with $32.05 for the soft-tissue technique. Biceps tenodesis success, as determined by clinical deformity and ultrasound, was not improved using hardware as compared to soft-tissue techniques. Soft-tissue techniques are equally efficacious and more cost effective than hardware techniques.

  14. Hardware packet pacing using a DMA in a parallel computer

    Science.gov (United States)

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  15. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    Science.gov (United States)

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  16. The role of the visual hardware system in rugby performance ...

    African Journals Online (AJOL)

    This study explores the importance of the 'hardware' factors of the visual system in the game of rugby. A group of professional and club rugby players were tested and the results compared. The results were also compared with the established norms for elite athletes. The findings indicate no significant difference in hardware ...

  17. The role of the visual hardware system in rugby performance ...

    African Journals Online (AJOL)

    This suggests that in the game of rugby the hardware skills may be of less importance and that visual enhancement programmes should focus more on improving the players' software skills. Key words: Vision, hardware, rugby, sports performance. (Af. J. Physical, Health Education, Recreation and Dance: 2003 Special ...

  18. [Hardware and software for X-ray therapy planning].

    Science.gov (United States)

    Zhizniakov, A L; Semenov, S I; Sushkova, L T; Troitskii, D P; Chirkov, K V

    2007-01-01

    Hardware, circuitry, and software suggested in this work make it possible to use the SLS-9 X-ray simulator for classical and computer tomographic imaging. The suggested hardware and software can be used as a basis for designing special-purpose tomographic systems.

  19. Monitoring Particulate Matter with Commodity Hardware

    Science.gov (United States)

    Holstius, David

    Health effects attributed to outdoor fine particulate matter (PM 2.5) rank it among the risk factors with the highest health burdens in the world, annually accounting for over 3.2 million premature deaths and over 76 million lost disability-adjusted life years. Existing PM2.5 monitoring infrastructure cannot, however, be used to resolve variations in ambient PM2.5 concentrations with adequate spatial and temporal density, or with adequate coverage of human time-activity patterns, such that the needs of modern exposure science and control can be met. Small, inexpensive, and portable devices, relying on newly available off-the-shelf sensors, may facilitate the creation of PM2.5 datasets with improved resolution and coverage, especially if many such devices can be deployed concurrently with low system cost. Datasets generated with such technology could be used to overcome many important problems associated with exposure misclassification in air pollution epidemiology. Chapter 2 presents an epidemiological study of PM2.5 that used data from ambient monitoring stations in the Los Angeles basin to observe a decrease of 6.1 g (95% CI: 3.5, 8.7) in population mean birthweight following in utero exposure to the Southern California wildfires of 2003, but was otherwise limited by the sparsity of the empirical basis for exposure assessment. Chapter 3 demonstrates technical potential for remedying PM2.5 monitoring deficiencies, beginning with the generation of low-cost yet useful estimates of hourly and daily PM2.5 concentrations at a regulatory monitoring site. The context (an urban neighborhood proximate to a major goods-movement corridor) and the method (an off-the-shelf sensor costing approximately USD $10, combined with other low-cost, open-source, readily available hardware) were selected to have special significance among researchers and practitioners affiliated with contemporary communities of practice in public health and citizen science. As operationalized by

  20. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  1. A Practical Introduction to HardwareSoftware Codesign

    CERN Document Server

    Schaumont, Patrick R

    2013-01-01

    This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

  2. The Art of Space Flight Exercise Hardware: Design and Implementation

    Science.gov (United States)

    Beyene, Nahom M.

    2004-01-01

    The design of space flight exercise hardware depends on experience with crew health maintenance in a microgravity environment, history in development of flight-quality exercise hardware, and a foundation for certifying proper project management and design methodology. Developed over the past 40 years, the expertise in designing exercise countermeasures hardware at the Johnson Space Center stems from these three aspects of design. The medical community has steadily pursued an understanding of physiological changes in humans in a weightless environment and methods of counteracting negative effects on the cardiovascular and musculoskeletal system. The effects of weightlessness extend to the pulmonary and neurovestibular system as well with conditions ranging from motion sickness to loss of bone density. Results have shown losses in water weight and muscle mass in antigravity muscle groups. With the support of university-based research groups and partner space agencies, NASA has identified exercise to be the primary countermeasure for long-duration space flight. The history of exercise hardware began during the Apollo Era and leads directly to the present hardware on the International Space Station. Under the classifications of aerobic and resistive exercise, there is a clear line of development from the early devices to the countermeasures hardware used today. In support of all engineering projects, the engineering directorate has created a structured framework for project management. Engineers have identified standards and "best practices" to promote efficient and elegant design of space exercise hardware. The quality of space exercise hardware depends on how well hardware requirements are justified by exercise performance guidelines and crew health indicators. When considering the microgravity environment of the device, designers must consider performance of hardware separately from the combined human-in-hardware system. Astronauts are the caretakers of the hardware

  3. Projeto e desenvolvimento de um hardware reconfigurável de criptografia para a transmissão segura de dados

    Directory of Open Access Journals (Sweden)

    Otávio Souza Martins Gomes

    2015-01-01

    Full Text Available Neste trabalho serão mostradas algumas conclusões prévias e escolhas realizadas para o desenvolvimento de uma interface de criptografia simétrica, utilizando hardware reconfigurável para a transmissão segura de dados. Os dispositivos reconfiguráveis permitem o desenvolvimento deste hardware de maneira segura e com uma grande flexibilidade, além da possibilidade de realizar algumas alterações com um mínimo de custo e tempo adicionais. Até o momento foram desenvolvidos os modelos para a implementação. O próximo passo será iniciar o desenvolvimento do hardware, que utilizará linguagens de descrição de hardware e Field Programmable Gate Arrays (FPGAs.Palavras-chave: Segurança. FPGA. PSoC. 3DES. VHDL. Design and development of an cryptography reconfigurable hardware for secure data trasmissionABSTRACTThis paper presents some conclusions and choices about the development of a symmetric cryptography reconfigurable hardware interface to allow a safe data communication. Reconfigurable hardwares allow the development of this kind of device with safety and flexibility, and offer the possibility to change some features with low cost and in a fast way. So far, the hardware models and functionalities were developed. The next step is to start the hardware implementation, which will use hardware description languages and FPGAs.Keywords: Security. FPGA. PSoC. 3DES. VHDL.

  4. Hardware Realization of Chaos Based Symmetric Image Encryption

    KAUST Repository

    Barakat, Mohamed L.

    2012-06-01

    This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

  5. Routing Aware Switch Hardware Customization for Networks on Chips

    OpenAIRE

    Meloni, Paolo; Murali, Srinivasan; Carta, Salvatore; Camplani, Massimo; Raffo, Luigi; Micheli, Giovanni,

    2006-01-01

    Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the app...

  6. Hardware support for collecting performance counters directly to memory

    Science.gov (United States)

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  7. Hardware Implementation of Serially Concatenated PPM Decoder

    Science.gov (United States)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  8. Hardware locks for a real-time Java chip multiprocessor

    DEFF Research Database (Denmark)

    Strøm, Torur Biskopstø; Puffitsch, Wolfgang; Schoeberl, Martin

    2016-01-01

    A software locking mechanism commonly protects shared resources for multithreaded applications. This mechanism can, especially in chip-multiprocessor systems, result in a large synchronization overhead. For real-time systems in particular, this overhead increases the worst-case execution time...... and may void a task set's schedulability. This paper presents 2 hardware locking mechanisms to reduce the worst-case time required to acquire and release synchronization locks. These solutions are implemented for the chip-multiprocessor version of the Java Optimized Processor. The 2 hardware locking...... mechanisms are compared with a software locking solution as well as the original locking system of the processor. The hardware cost and performance are evaluated for all presented locking mechanisms. The performance of the better-performing hardware locks is comparable with that of the original single global...

  9. A versatile hardware platform for brain computer interfaces.

    Science.gov (United States)

    Garcia, Pablo A; Haberman, Marcelo; Spinelli, Enrique M

    2010-01-01

    This article presents the development of a versatile hardware platform for brain computer interfaces (BCI). The aim of this work is to produce a small, autonomous and configurable BCI platform adaptable to the user's needs.

  10. Scientific Computing Using Consumer Video-Gaming Hardware Devices

    CERN Document Server

    Volkema, Glenn

    2016-01-01

    Commodity video-gaming hardware (consoles, graphics cards, tablets, etc.) performance has been advancing at a rapid pace owing to strong consumer demand and stiff market competition. Gaming hardware devices are currently amongst the most powerful and cost-effective computational technologies available in quantity. In this article, we evaluate a sample of current generation video-gaming hardware devices for scientific computing and compare their performance with specialized supercomputing general purpose graphics processing units (GPGPUs). We use the OpenCL SHOC benchmark suite, which is a measure of the performance of compute hardware on various different scientific application kernels, and also a popular public distributed computing application, Einstein@Home in the field of gravitational physics for the purposes of this evaluation.

  11. Combining hardware and simulation for datacenter scaling studies

    DEFF Research Database (Denmark)

    Ruepp, Sarah Renée; Pilimon, Artur; Thrane, Jakob

    2017-01-01

    Datacenter networks are becoming crucial foundations for our information technology based society. However, commercial datacenter infrastructure is often unavailable to researchers for conducting experiments. In this work, we therefore elaborate on the possibility of combining commercial hardware...

  12. Hardware device to physical structure binding and authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  13. Hardware problems encountered in solar heating and cooling systems

    Science.gov (United States)

    Cash, M.

    1978-01-01

    Numerous problems in the design, production, installation, and operation of solar energy systems are discussed. Described are hardware problems, which range from simple to obscure and complex, and their resolution.

  14. Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware

    NARCIS (Netherlands)

    Rauwerda, G.K.; Jha, N.K.; Heysters, P.M.; Smit, Gerardus Johannes Maria

    Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance, and efficiency to enable the implementation of these devices. The implementation of a wideband

  15. Towards hardware-intrinsic security foundations and practice

    CERN Document Server

    Sadeghi, Ahmad-Reza; Tuyls, Pim

    2010-01-01

    Hardware-intrinsic security is a young field dealing with secure secret key storage. This book features contributions from researchers and practitioners with backgrounds in physics, mathematics, cryptography, coding theory and processor theory.

  16. Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps

    DEFF Research Database (Denmark)

    Bonnichsen, Lars Frydendal; Probst, Christian W.; Karlsson, Sven

    2015-01-01

    synchronization method scales well. Recently, hardware transactional memory was introduced, which allows threads to use transactions instead of locks. So far, applying hardware transactional memory has shown mixed results. We believe this is because transactions are different from locks, and using them...... efficiently requires reasoning about those differences. In this paper we present 5 guidelines for applying hardware transactional memory efficiently, and apply the guidelines to BT-trees, a concurrent ordered map. Evaluating BT-trees on standard benchmarks shows that they are up to 5.3 times faster than...... traditional maps using hardware transactional memory, and up to 3.9 times faster than state of the art concurrent ordered maps....

  17. A Survey on Hardware Implementations of Visual Object Trackers

    OpenAIRE

    El-Shafie, Al-Hussein A.; Habib, S. E. D.

    2017-01-01

    Visual object tracking is an active topic in the computer vision domain with applications extending over numerous fields. The main sub-tasks required to build an object tracker (e.g. object detection, feature extraction and object tracking) are computation-intensive. In addition, real-time operation of the tracker is indispensable for almost all of its applications. Therefore, complete hardware or hardware/software co-design approaches are pursued for better tracker implementations. This pape...

  18. Top Down Approach: SIMULINK Mixed Hardware / Software Design

    OpenAIRE

    Atat, Youssef; Rizk, Mostafa

    2012-01-01

    System-level design methodologies have been introduced as a solution to handle the design complexity of mixed Hardware / Software systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: System Simulink model, Transaction Simulink model, Macro architecture, and micro architecture. We used the MP3 CodeC application, to validate our approach and m...

  19. The aerospace energy systems laboratory: Hardware and software implementation

    Science.gov (United States)

    Glover, Richard D.; Oneil-Rood, Nora

    1989-01-01

    For many years NASA Ames Research Center, Dryden Flight Research Facility has employed automation in the servicing of flight critical aircraft batteries. Recently a major upgrade to Dryden's computerized Battery Systems Laboratory was initiated to incorporate distributed processing and a centralized database. The new facility, called the Aerospace Energy Systems Laboratory (AESL), is being mechanized with iAPX86 and iAPX286 hardware running iRMX86. The hardware configuration and software structure for the AESL are described.

  20. Hardware And Software For Development Of Robot Arms

    Science.gov (United States)

    Usikov, Daniel

    1995-01-01

    System of modular, reusable hardware and software assembled for use in developing remotely controlled robotic arms. Includes (1) central computer and peripheral equipment at control and monitoring station and (2) remote mechanical platform that supports robotic arm. Central computer controls motor drives of robotic arm, but optically, platform holds on-board computer for autonomous operation. Consists mostly of commercial hardware and software. Simulated results of commands viewed in three dimensions.

  1. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  2. Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

    Directory of Open Access Journals (Sweden)

    Ali Akbar Zarezadeh

    2012-01-01

    Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

  3. Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs

    Directory of Open Access Journals (Sweden)

    Prasanna ViktorK

    2006-01-01

    Full Text Available By allowing parts of the applications to be executed either on soft processors (as software programs or on customized hardware peripherals attached to the processors, FPGAs have made traditional energy estimation techniques inefficient for evaluating various design tradeoffs. In this paper, we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs. In the first step, a high-level hardware-software cosimulation technique is applied to simulate both the hardware and software components of the target application. High-level simulation results of both software programs running on the processors and the customized hardware peripherals are gathered during the cosimulation process. In the second step, the high-level simulation results of the customized hardware peripherals are used to estimate the switching activities of their corresponding register-transfer/gate level ("low-level" implementations. We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application. A Matlab/Simulink-based implementation of our approach and two numerical computation applications show that the proposed energy estimation technique can achieve more than 6000x speedup over low-level simulation-based techniques while sacrificing less than 10% estimation accuracy. Compared with the measured results, our experimental results show that the proposed technique achieves an average estimation error of less than 12%.

  4. On the use of inexact, pruned hardware in atmospheric modelling.

    Science.gov (United States)

    Düben, Peter D; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V; Palmer, T N

    2014-06-28

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz '96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models.

  5. Implementing a Description Grammar Interpreter : A Notation for Descriptions and Description Rules

    NARCIS (Netherlands)

    Stouffs, R.M.F.

    2015-01-01

    Description grammars represent a formalism for generating verbal descriptions of designs, used in conjunction with shape grammars. A description grammar constitutes a set of description rules that define a language of descriptions. A description grammar interpreter implements the mechanisms to

  6. Spent fuel disassembly hardware and other non-fuel bearing components: characterization, disposal cost estimates, and proposed repository acceptance requirements

    Energy Technology Data Exchange (ETDEWEB)

    Luksic, A.T.; McKee, R.W.; Daling, P.M.; Konzek, G.J.; Ludwick, J.D.; Purcell, W.L.

    1986-10-01

    There are two categories of waste considered in this report. The first is the spent fuel disassembly (SFD) hardware. This consists of the hardware remaining after the fuel pins have been removed from the fuel assembly. This includes end fittings, spacer grids, water rods (BWR) or guide tubes (PWR) as appropriate, and assorted springs, fasteners, etc. The second category is other non-fuel-bearing (NFB) components the DOE has agreed to accept for disposal, such as control rods, fuel channels, etc., under Appendix E of the standard utiltiy contract (10 CFR 961). It is estimated that there will be approximately 150 kg of SFD and NFB waste per average metric ton of uranium (MTU) of spent uranium. PWR fuel accounts for approximately two-thirds of the average spent-fuel mass but only 50 kg of the SFD and NFB waste, with most of that being spent fuel disassembly hardware. BWR fuel accounts for one-third of the average spent-fuel mass and the remaining 100 kg of the waste. The relatively large contribution of waste hardware in BWR fuel, will be non-fuel-bearing components, primarily consisting of the fuel channels. Chapters are devoted to a description of spent fuel disassembly hardware and non-fuel assembly components, characterization of activated components, disposal considerations (regulatory requirements, economic analysis, and projected annual waste quantities), and proposed acceptance requirements for spent fuel disassembly hardware and other non-fuel assembly components at a geologic repository. The economic analysis indicates that there is a large incentive for volume reduction.

  7. Hardware failure in patients with metastatic cancer to the spine.

    Science.gov (United States)

    Pedreira, Rachel; Abu-Bonsrah, Nancy; Karim Ahmed, A; De la Garza-Ramos, Rafael; Rory Goodwin, C; Gokaslan, Ziya L; Sacks, Justin; Sciubba, Daniel M

    2017-11-01

    The spine is the most common site of skeletal metastases, affecting approximately 30% of individuals with cancer. The aim of surgical treatment for metastatic spine disease is generally palliative to address pain and/or neurologic compromise, significantly improving patients' quality of life. Patients with metastatic spine disease, however, represent a vulnerable cohort and may have comorbidities or previous treatments that impair the structural integrity of spinal hardware. As such, identifying factors that may contribute to hardware failure is an essential component in treating individuals with metastatic spine disease. The aim of this study was to identify pre-operative risk factors associated with hardware failure in patients undergoing surgical treatment for metastatic spine disease. A retrospective cohort study was conducted to include patients surgically treated for metastatic spine tumors between 2003 and 2013, at a single institution. A univariate analysis was initially performed to identify associated factors. Any associated factor with a p-value failure of the spine instrumentation. 1 patient had metastatic prostate cancer, and 2 had metastatic breast cancer. Patient demographics, co-morbidities, tumor location, and primary tumor etiology were not found to be statistically significant, with respect to hardware failure. Predictive factors included in the multivariate model were other bone metastasis, visceral metastasis, brain metastasis, Modified Rankin scale, previous systemic chemotherapy, previous radiation to the spine, and mean survival. Previous radiation to the spine was the only factor to be significantly associated (p=0.029), present in all three patients with hardware failure. Of note, there was a trend indicating that patients with longer life expectancies were more likely to experience hardware failure (mean survival of 16.7months in non-failure cohort vs. 33months in failure cohort), though this did not achieve statistical significance due

  8. GOSH! A roadmap for open-source science hardware

    CERN Multimedia

    Stefania Pandolfi

    2016-01-01

    The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

  9. Color science demonstration kit from open source hardware and software

    Science.gov (United States)

    Zollers, Michael W.

    2014-09-01

    Color science is perhaps the most universally tangible discipline within the optical sciences for people of all ages. Excepting a small and relatively well-understood minority, we can see that the world around us consists of a multitude of colors; yet, describing the "what", "why", and "how" of these colors is not an easy task, especially without some sort of equally colorful visual aids. While static displays (e.g., poster boards, etc.) serve their purpose, there is a growing trend, aided by the recent permeation of small interactive devices into our society, for interactive and immersive learning. However, for the uninitiated, designing software and hardware for this purpose may not be within the purview of all optical scientists and engineers. Enter open source. Open source "anything" are those tools and designs -- hardware or software -- that are available and free to use, often without any restrictive licensing. Open source software may be familiar to some, but the open source hardware movement is relatively new. These are electronic circuit board designs that are provided for free and can be implemented in physical hardware by anyone. This movement has led to the availability of some relatively inexpensive, but quite capable, computing power for the creation of small devices. This paper will showcase the design and implementation of the software and hardware that was used to create an interactive demonstration kit for color. Its purpose is to introduce and demonstrate the concepts of color spectra, additive color, color rendering, and metamers.

  10. OS friendly microprocessor architecture: Hardware level computer security

    Science.gov (United States)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  11. Acquisition of teleological descriptions

    Science.gov (United States)

    Franke, David W.

    1992-03-01

    Teleology descriptions capture the purpose of an entity, mechanism, or activity with which they are associated. These descriptions can be used in explanation, diagnosis, and design reuse. We describe a technique for acquiring teleological descriptions expressed in the teleology language TeD. Acquisition occurs during design by observing design modifications and design verification. We demonstrate the acquisition technique in an electronic circuit design.

  12. The appropriateness of XML for diagnostic description

    Energy Technology Data Exchange (ETDEWEB)

    Neto, A. [Associacao Euratom/IST, Centro de Fusao Nuclear, Av. Rovisco Pais, P-1049-001 Lisboa (Portugal)], E-mail: andre.neto@cfn.ist.utl.pt; Lister, J.B. [CRPP-EPFL, Association EURATOM-Confederation Suisse, 1015 Lausanne (Switzerland); Fernandes, H. [Associacao Euratom/IST, Centro de Fusao Nuclear, Av. Rovisco Pais, P-1049-001 Lisboa (Portugal); Yonekawa, I. [JAEA, Japan Atomic Energy Agency Naka (Japan); Varandas, C.A.F. [Associacao Euratom/IST, Centro de Fusao Nuclear, Av. Rovisco Pais, P-1049-001 Lisboa (Portugal)

    2007-10-15

    A standard for the self-description of fusion plasma diagnostics will be required in the near future. The motivation is to maintain and organize the information on all the components of a laboratory experiment, from the hardware to the access security, to save time and money. Since there is no existing standard to organize this kind of information, every EU Association stores and organizes each experiment in different ways. This can lead to severe problems when the particular organization schema is poorly documented. Standardization is the key to solve these problems. From the commercial information on the diagnostic (component supplier; component price) to the hardware description (component specifications; drawings) to the operation of the equipment (finite state machines) through change control (who changed what and when) and internationalization (information at least in English and a local language). This problem will be met on the ITER project, for which a solution is essential. A strong candidate solution is the Extensible Markup Language (XML). In this paper, a review of the current status of XML related technologies will be presented.

  13. Hardware Realization of Chaos-based Symmetric Video Encryption

    KAUST Repository

    Ibrahim, Mohamad A.

    2013-05-01

    This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

  14. XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Gaurav Purohit

    2016-01-01

    Full Text Available This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW implementation of new architecture uses Lookup Table (LUT for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

  15. Bringing the power of dynamic languages to hardware control systems

    CERN Document Server

    Caicedo, J M; Neufeld, N

    2009-01-01

    Hardware control systems are normally programmed using high-performance languages like C or C++ and increasingly also Java. All these languages are strongly typed and compiled which brings usually good performance but at the cost of a longer development and testing cycle and the need for more programming expertise. Dynamic languages which were long thought to be too slow and not powerful enough for control purposes are, thanks to modern powerful computers and advanced implementation techniques, fast enough for many of these tasks. We present examples from the LHCb Experiment Control System (ECS), which is based on a commercial SCADA software. We have successfully used Python to integrate hardware devices into the ECS. We present the necessary lightweight middle-ware we have developed, including examples for controlling hardware and software devices. We also discuss the development cycle, tools used and compare the effort to traditional solutions.

  16. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  17. Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

    KAUST Repository

    Javed, Sidrah

    2017-02-22

    This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

  18. Mapping of topological quantum circuits to physical hardware.

    Science.gov (United States)

    Paler, Alexandru; Devitt, Simon J; Nemoto, Kae; Polian, Ilia

    2014-04-11

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.

  19. Hardware Architecture Study for NASA's Space Software Defined Radios

    Science.gov (United States)

    Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

    2008-01-01

    This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  20. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    Science.gov (United States)

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  1. Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

    DEFF Research Database (Denmark)

    Nistor, Maricica; Lucani Rötter, Daniel Enrique; Barros, joao

    2014-01-01

    The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware...... specifications of common sensors reveals, however, that other equally important culprits exist, such as the reception and processing energy. Hence, there is a need for a more complete hardware abstraction of a sensor node to reduce effectively the total energy consumption of the network by designing energy......-efficient protocols that use such an abstraction, as well as mechanisms to optimize a communication protocol in terms of energy consumption. The problem is modeled for different feedback-based techniques, where sensors are connected to a base station, either directly or through relays. We show that for four example...

  2. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00372086; The ATLAS collaboration

    2016-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  3. Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs

    Directory of Open Access Journals (Sweden)

    Viktor K. Prasanna

    2006-09-01

    Full Text Available By allowing parts of the applications to be executed either on soft processors (as software programs or on customized hardware peripherals attached to the processors, FPGAs have made traditional energy estimation techniques inefficient for evaluating various design tradeoffs. In this paper, we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs. In the first step, a high-level hardware-software cosimulation technique is applied to simulate both the hardware and software components of the target application. High-level simulation results of both software programs running on the processors and the customized hardware peripherals are gathered during the cosimulation process. In the second step, the high-level simulation results of the customized hardware peripherals are used to estimate the switching activities of their corresponding register-transfer/gate level (“low-level” implementations. We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application. A Matlab/Simulink-based implementation of our approach and two numerical computation applications show that the proposed energy estimation technique can achieve more than 6000x speedup over low-level simulation-based techniques while sacrificing less than 10% estimation accuracy. Compared with the measured results, our experimental results show that the proposed technique achieves an average estimation error of less than 12%.

  4. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  5. Hardware Evaluation of the Horizontal Exercise Fixture with Weight Stack

    Science.gov (United States)

    Newby, Nate; Leach, Mark; Fincke, Renita; Sharp, Carwyn

    2009-01-01

    HEF with weight stack seems to be a very sturdy and reliable exercise device that should function well in a bed rest training setting. A few improvements should be made to both the hardware and software to improve usage efficiency, but largely, this evaluation has demonstrated HEF's robustness. The hardware offers loading to muscles, bones, and joints, potentially sufficient to mitigate the loss of muscle mass and bone mineral density during long-duration bed rest campaigns. With some minor modifications, the HEF with weight stack equipment provides the best currently available means of performing squat, heel raise, prone row, bench press, and hip flexion/extension exercise in a supine orientation.

  6. Computer organization and design the hardware/software interface

    CERN Document Server

    Hennessy, John L

    1994-01-01

    Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

  7. Towards Shop Floor Hardware Reconfiguration for Industrial Collaborative Robots

    DEFF Research Database (Denmark)

    Schou, Casper; Madsen, Ole

    2016-01-01

    In this paper we propose a roadmap for hardware reconfiguration of industrial collaborative robots. As a flexible resource, the collaborative robot will often need transitioning to a new task. Our goal is, that this transitioning should be done by the shop floor operators, not highly specialized...... engineers. The hard- ware reconfiguration framework adopts a modular architecture for the collabo- rative robot which dictates a clear segmentation of the robot into well-defined exchangeable modules. Four main objectives for the hardware reconfiguration framework; 1) Modular architecture, 2) Module...

  8. Electrical, electronics, and digital hardware essentials for scientists and engineers

    CERN Document Server

    Lipiansky, Ed

    2012-01-01

    A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

  9. Nios II hardware acceleration of the epsilon quadratic sieve algorithm

    Science.gov (United States)

    Meyer-Bäse, Uwe; Botella, Guillermo; Castillo, Encarnacion; García, Antonio

    2010-04-01

    The quadratic sieve (QS) algorithm is one of the most powerful algorithms to factor large composite primes used to break RSA cryptographic systems. The hardware structure of the QS algorithm seems to be a good fit for FPGA acceleration. Our new ɛ-QS algorithm further simplifies the hardware architecture making it an even better candidate for C2H acceleration. This paper shows our design results in FPGA resource and performance when implementing very long arithmetic on the Nios microprocessor platform with C2H acceleration for different libraries (GMP, LIP, FLINT, NRMP) and QS architecture choices for factoring 32-2048 bit RSA numbers.

  10. Hardware-assisted software clock synchronization for homogeneous distributed systems

    Science.gov (United States)

    Ramanathan, P.; Kandlur, Dilip D.; Shin, Kang G.

    1990-01-01

    A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

  11. On Issues of Precision for Hardware-based Volume Visualization

    Energy Technology Data Exchange (ETDEWEB)

    LaMar, E C

    2003-04-11

    This paper discusses issues with the limited precision of hardware-based volume visualization. We will describe the compositing OVER operator and how fixed-point arithmetic affects it. We propose two techniques to improve the precision of fixed-point compositing and the accuracy of hardware-based volume visualization. The first technique is to perform dithering of color and alpha values. The second technique we call exponent-factoring, and captures significantly more numeric resolution than dithering, but can only produce monochromatic images.

  12. A Computer Scientist’s Evaluation of Publically Available Hardware Trojan Benchmarks

    Science.gov (United States)

    2015-09-01

    in, design for trust, hardware intellectual property cores, Hardware Oriented Security and Trust, hardware synthesis, hardware Trojans, HDL...that this XOR gate also handles multiple bits, but that no visual cue is given. ...................................................16 Figure 4. Part...1-bit input clk is represented by graphical lows and highs, but multi-bit inputs are represented by numerical values. For clarity, we have edited

  13. Hardware Implementation of LMS-Based Adaptive Noise Cancellation Core with Low Resource Utilization

    Directory of Open Access Journals (Sweden)

    Omid Sharifi Tehrani

    2011-10-01

    Full Text Available A hardware implementation of adaptive noise cancellation (ANC core is proposed. Adaptive filters are widely used in different applications such as adaptive noise cancellation, prediction, equalization, inverse modeling and system identification. FIR adaptive filters are mostly used because of their low computation costs and their linear phase. Least mean squared algorithm (LMS is used to train FIR adaptive filter weights. Advances in semiconductor technology especially in digital signal processors (DSP and field programmable gate arrays (FPGA with hundreds of mega hertz in speed, will allow digital designers to embed essential digital signal processing units in small chips. But designing a synthesizable core on an FPGA is not always as simple as DSP chips due to complexity and limitations of FPGAs. In this paper we design anLMS-based FIR adaptive filter for adaptive noise cancellation based on VHDL97 hardware description language (HDL and Xilinx SPARTAN3E (XC3S500E which utilizes low resources and is high performance and FPGA-brand independent so can be implemented on different FPGA brands (Xilinx, ALTERA, ACTEL. Simulations are done in MODELSIM and MATLAB and implementation is done with Xilinx ISE. Finally, result are compared with other papers for better judgment.

  14. Towards automated construction of dependable software/hardware systems

    Energy Technology Data Exchange (ETDEWEB)

    Yakhnis, A.; Yakhnis, V. [Pioneer Technologies & Rockwell Science Center, Albuquerque, NM (United States)

    1997-11-01

    This report contains viewgraphs on the automated construction of dependable computer architecture systems. The outline of this report is: examples of software/hardware systems; dependable systems; partial delivery of dependability; proposed approach; removing obstacles; advantages of the approach; criteria for success; current progress of the approach; and references.

  15. Use of Heritage Hardware on MPCV Exploration Flight Test One

    Science.gov (United States)

    Rains, George Edward; Cross, Cynthia D.

    2011-01-01

    Due to an aggressive schedule for the first orbital test flight of an unmanned Orion capsule, known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the Shuttle Ground Support Equipment Heat Exchanger (GSE Hx) and the MPLM cabin Positive Pressure Relief Assembly (PPRA). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be significantly more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE Hx had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the certification of the use of heritage hardware for EFT1.

  16. Hardware Approach for Real Time Machine Stereo Vision

    Directory of Open Access Journals (Sweden)

    Michael Tornow

    2006-02-01

    Full Text Available Image processing is an effective tool for the analysis of optical sensor information for driver assistance systems and controlling of autonomous robots. Algorithms for image processing are often very complex and costly in terms of computation. In robotics and driver assistance systems, real-time processing is necessary. Signal processing algorithms must often be drastically modified so they can be implemented in the hardware. This task is especially difficult for continuous real-time processing at high speeds. This article describes a hardware-software co-design for a multi-object position sensor based on a stereophotogrammetric measuring method. In order to cover a large measuring area, an optimized algorithm based on an image pyramid is implemented in an FPGA as a parallel hardware solution for depth map calculation. Object recognition and tracking are then executed in real-time in a processor with help of software. For this task a statistical cluster method is used. Stabilization of the tracking is realized through use of a Kalman filter. Keywords: stereophotogrammetry, hardware-software co-design, FPGA, 3-d image analysis, real-time, clustering and tracking.

  17. Visual basic application in computer hardware control and data ...

    African Journals Online (AJOL)

    Speech Recognition Technology enables text acquisition via users' dictation and knowledge gain through system dictation. In this paper the application of speech recognition technology in hardware device control and data acquisition is experimented using Visual Basic and the Speech Application Programming Interface ...

  18. Security Primitives for Reconfigurable Hardware-Based Systems

    Science.gov (United States)

    2010-05-01

    based architectures. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS ’07). FIORIN, L...and System Synthesis (CODES+ ISSS ’07). Received April 2008; revised October 2008; accepted March 2009 ACM Transactions on Reconfigurable Technology and Systems, Vol. 3, No. 2, Article 10, Pub. date: May 2010.

  19. Graph based communication analysis for hardware/software codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1999-01-01

    In this paper we present a coarse grain CDFG (Control/Data Flow Graph) model suitable for hardware/software partitioning of single processes and demonstrate how it is necessary to perform various transformations on the graph structure before partitioning in order to achieve a structure that allows...

  20. Detecting System of Nested Hardware Virtual Machine Monitor

    Directory of Open Access Journals (Sweden)

    Artem Vladimirovich Iuzbashev

    2015-03-01

    Full Text Available Method of nested hardware virtual machine monitor detection was proposed in this work. The method is based on HVM timing attack. In case of HVM presence in system, the number of different instruction sequences execution time values will increase. We used this property as indicator in our detection.

  1. Know Your Personal Computer The Personal Computer Hardware

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 1; Issue 2. Know Your Personal Computer The Personal Computer Hardware. Siddhartha Kumar ... Author Affiliations. Siddhartha Kumar Ghoshal1. Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore 560 012, India.

  2. Smart Home Hardware-in-the-Loop Testing

    Energy Technology Data Exchange (ETDEWEB)

    Pratt, Annabelle

    2017-07-12

    This presentation provides a high-level overview of NREL's smart home hardware-in-the-loop testing. It was presented at the Fourth International Workshop on Grid Simulator Testing of Energy Systems and Wind Turbine Powertrains, held April 25-26, 2017, hosted by NREL and Clemson University at the Energy Systems Integration Facility in Golden, Colorado.

  3. Foundations of digital signal processing theory, algorithms and hardware design

    CERN Document Server

    Gaydecki, Patrick

    2005-01-01

    An excellent introductory text, this book covers the basic theoretical, algorithmic and real-time aspects of digital signal processing (DSP). Detailed information is provided on off-line, real-time and DSP programming and the reader is effortlessly guided through advanced topics such as DSP hardware design, FIR and IIR filter design and difference equation manipulation.

  4. Hardware-in-the-loop testing of marine control system

    Directory of Open Access Journals (Sweden)

    Roger Skjetne

    2006-10-01

    Full Text Available Hardware-in-the-Loop (HIL testing is proposed as a new methodology for verification and certification of marine control systems. Formalizing such testing necessitates the development of a vocabulary and set of definitions. This paper treats these issues by constructing a framework suitable for industrial HIL test applications and certification of marine systems.

  5. Implementing Strategic Management of Producibility in Military Hardware Design

    Science.gov (United States)

    1985-05-01

    APPROVAL L~og No. OF TECHNICAL ARTICLE, PAPER OR SPEECH TO BE PRESENTED OR PUBLISH ED SubmIt 4 bcop" of Clearance Request and 2 copies of * spech or paper...in many free world nations. The common denominator is recognition that the development and acquisition process of military hardware mandates a team

  6. RDV77 VLBA Hardware/Software Correlator Comparisons

    Science.gov (United States)

    Gordon, David

    2010-01-01

    Results of a hardware vs. software correlation of the RDV77 session are presented. Group delays are found to agree (WRMS differences) at an average level of 4.2 psec and with a noise floor of 2.5 psec. These RDV77 comparisons agree well with several previous correlator comparison studies.

  7. An Integrated Hardware Array for Very High Speed Logic Simulation

    Directory of Open Access Journals (Sweden)

    E. Scott Fehr

    1996-01-01

    boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

  8. Leveraging Information Technology. Track VI: Hardware/Software Strategies.

    Science.gov (United States)

    CAUSE, Boulder, CO.

    Seven papers from the 1987 CAUSE conference's Track VI, Hardware/Software Strategies, are presented. They include: "Integrated Systems--The Next Steps" (Morris A. Hicks); "Administrative Microcomputing--Roads Traveled, Lessons Learned" (David L. Smallen); "Murphy's First Law and Its Application to Administrative…

  9. Efficient architecture for spike sorting in reconfigurable hardware.

    Science.gov (United States)

    Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

    2013-11-01

    This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

  10. Aspects of system modelling in Hardware/Software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows...

  11. 3D IBFV : Hardware-Accelerated 3D Flow Visualization

    NARCIS (Netherlands)

    Telea, Alexandru; Wijk, Jarke J. van

    2003-01-01

    We present a hardware-accelerated method for visualizing 3D flow fields. The method is based on insertion, advection, and decay of dye. To this aim, we extend the texture-based IBFV technique for 2D flow visualization in two main directions. First, we decompose the 3D flow visualization problem in a

  12. Alternate Protocol for Detecting Biological Contamination on Sensitive Hardware

    Science.gov (United States)

    Berlin, David; Lalime, Erin; Carosso, Nancy

    2015-01-01

    The purpose of this project is to develop a sterile water based rapid bioburden test. Contamination engineers use two tests to assess the level of biological contamination on hardware: the rapid five minute bioburden test, which is a molecular screening for Adenosine triphosphate (ATP), a molecule found in all cells on the hardware, and a slower colony growth test, which is used to give a more accurate representation of the amount of microbes on the hardware. However, the rapid bioburden test has limited application because it leaves a residue that can be detrimental to sensitive hardware. This can cause project delays while waiting for the results from the three day colony growth test. We address this problem by adapting the commercial germicide based ATP system to a sterile water based system. The test works by reacting ATP with D-Luciferin and Luciferase protein to yield light. The light is then detected by a luminometer that outputs a Relative Light Unit (RLU) amount depending on how much ATP is present. To analyze the effectiveness of the new test, we developed a correlation between amounts of ATP and the RLU produced using the germicide based system. From these experiments, we've generated a consistent relationship between the two in the form of a power curve. From there, we developed a correlation curve between the amount of colonies and the RLU they produced. Initial tests of the new protocol have shown that the water based system isn't as sensitive as the germicide based test.

  13. Osseodensification for enhancement of spinal surgical hardware fixation.

    Science.gov (United States)

    Lopez, Christopher D; Alifarag, Adham M; Torroni, Andrea; Tovar, Nick; Diaz-Siso, J Rodrigo; Witek, Lukasz; Rodriguez, Eduardo D; Coelho, Paulo G

    2017-05-01

    Integration between implant and bone is an essential concept for osseous healing requiring hardware placement. A novel approach to hardware implantation, termed osseodensification, is described here as an effective alternative. 12 sheep averaging 65kg had fixation devices installed in their C2, C3, and C4 vertebral bodies; each device measured 4mm diameter×10mm length. The left-sided vertebral body devices were implanted using regular surgical drilling (R) while the right-sided devices were implanted using osseodensification drilling (OD). The C2 and C4 vertebra provided the t=0 in vivo time point, while the C3 vertebra provided the t=3 and t=6 week time points, in vivo. Structural competence of hardware was measured using biomechanical testing of pullout strength, while the quality and degree of new bone formation and remodeling was assessed via histomorphometry. Pullout strength demonstrated osseodensification drilling to provide superior anchoring when compared to the control group collapsed over time with statistical significance (phardware implantation encourages assessment of current surgical approaches to hardware implantation. Copyright © 2017 Elsevier Ltd. All rights reserved.

  14. Hardware Location and Clinical Outcome in Ulna Shortening Osteotomy.

    Science.gov (United States)

    Megerle, Kai; Hellmich, Susanne; Germann, Günter; Sauerbier, Michael

    2015-10-01

    The purpose of this study was to investigate the influence of plate location during ulna shortening osteotomy on the incidence of hardware irritation and clinical outcome. Forty patients (17 women, 23 men; mean age, 47 years) who underwent a shortening osteotomy of the ulna due to idiopathic ulna impaction syndrome were examined after a mean of 36 months. All complications and secondary procedures were extracted from the patients' records. The rate of hardware removal was higher in patients who had a dorsal placement of the plate in comparison with ulnar or palmar placements, although this difference was not statistically significant. Apart from hardware irritation, there were 4 nonunions, 1 secondary osteoarthritis of the distal radioulnar joint, and 1 case of chronic irritation of the dorsal branch of the ulnar nerve, which required secondary surgery. The incidence of secondary surgery other than hardware removal was not significantly related to the original location of the plate. Secondary surgery after ulnar shortening osteotomy is common. However, we found no difference in clinical outcomes based on plate location.

  15. A Cache-Based Hardware Accelerator for Memory Data Movements

    NARCIS (Netherlands)

    Duarte, F.

    2008-01-01

    This dissertation presents a hardware accelerator that is able to accelerate large (including non-parallel) memory data movements, in particular memory copies, performed traditionally by the processors. As todays processors are tied with or have integrated caches with varying sizes (from several

  16. Cache-based memory copy hardware accelerator for multicore systems

    NARCIS (Netherlands)

    Duarte, F.; Wong, S.

    2010-01-01

    In this paper, we present a new architecture of the cache-based memory copy hardware accelerator in a multicore system supporting message passing. The accelerator is able to accelerate memory data movements, in particular memory copies. We perform an analytical analysis based on open-queuing theory

  17. Chip-Multiprocessor Hardware Locks for Safety-Critical Java

    DEFF Research Database (Denmark)

    Strøm, Torur Biskopstø; Puffitsch, Wolfgang; Schoeberl, Martin

    2013-01-01

    and may void a task set's schedulability. In this paper we present a hardware locking mechanism to reduce the synchronization overhead. The solution is implemented for the chip-multiprocessor version of the Java Optimized Processor in the context of safety-critical Java. The implementation is compared...

  18. Integrated Hardware and Software for No-Loss Computing

    Science.gov (United States)

    James, Mark

    2007-01-01

    When an algorithm is distributed across multiple threads executing on many distinct processors, a loss of one of those threads or processors can potentially result in the total loss of all the incremental results up to that point. When implementation is massively hardware distributed, then the probability of a hardware failure during the course of a long execution is potentially high. Traditionally, this problem has been addressed by establishing checkpoints where the current state of some or part of the execution is saved. Then in the event of a failure, this state information can be used to recompute that point in the execution and resume the computation from that point. A serious problem arises when one distributes a problem across multiple threads and physical processors is that one increases the likelihood of the algorithm failing due to no fault of the scientist but as a result of hardware faults coupled with operating system problems. With good reason, scientists expect their computing tools to serve them and not the other way around. What is novel here is a unique combination of hardware and software that reformulates an application into monolithic structure that can be monitored in real-time and dynamically reconfigured in the event of a failure. This unique reformulation of hardware and software will provide advanced aeronautical technologies to meet the challenges of next-generation systems in aviation, for civilian and scientific purposes, in our atmosphere and in atmospheres of other worlds. In particular, with respect to NASA s manned flight to Mars, this technology addresses the critical requirements for improving safety and increasing reliability of manned spacecraft.

  19. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    Science.gov (United States)

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  20. Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

    Science.gov (United States)

    Harper, R. E.; Alger, L. S.; Babikyan, C. A.; Butler, B. P.; Friend, S. A.; Ganska, R. J.; Lala, J. H.; Masotto, T. K.; Meyer, A. J.; Morton, D. P.

    1992-01-01

    Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions.

  1. Description logics of context

    CSIR Research Space (South Africa)

    Klarman, S

    2013-05-01

    Full Text Available We introduce Description Logics of Context (DLCs) - an extension of Description Logics (DLs) for context-based reasoning. Our approach descends from J. McCarthy's tradition of treating contexts as formal objects over which one can quantify...

  2. Descriptive set theory

    CERN Document Server

    Moschovakis, YN

    1987-01-01

    Now available in paperback, this monograph is a self-contained exposition of the main results and methods of descriptive set theory. It develops all the necessary background material from logic and recursion theory, and treats both classical descriptive set theory and the effective theory developed by logicians.

  3. Ignoring Grounded Description

    Directory of Open Access Journals (Sweden)

    Barney G. Glaser, PhD, Hon. PhD

    2016-12-01

    Full Text Available Why is there so much grounded description? The simplest, direct answer is that to many a researcher this is GT. This view is supported by several factors. It is easy and natural to describe accurately. So slipping into grounded description comes naturally and is ok as GT. Also departmental support for description is strongly supported by perspective and academic rewards and history and routine QDA. Also many researchers and readers of research cannot conceptualize very well if at all. They want accurate description about the data in the study. They are not into taking a core category as a general category applicable to general implications applicable to much data elsewhere. Their study is about explaining processes the data, NOT in studying the implications of core and sub-core categories as they are integrated into an explanatory theory. I trust the reader can think of other sources of letting GT research slip into conceptual description.

  4. Hardware emulation of Memristor based Ternary Content Addressable Memory

    KAUST Repository

    Bahloul, Mohamed A.

    2017-12-13

    MTCAM (Memristor Ternary Content Addressable Memory) is a special purpose storage medium in which data could be retrieved based on the stored content. Using Memristors as the main storage element provides the potential of achieving higher density and more efficient solutions than conventional methods. A key missing item in the validation of such approaches is the wide spread availability of hardware emulation platforms that can provide reliable and repeatable performance statistics. In this paper, we present a hardware MTCAM emulation based on 2-Transistors-2Memristors (2T2M) bit-cell. It builds on a bipolar memristor model with storing and fetching capabilities based on the actual current-voltage behaviour. The proposed design offers a flexible verification environment with quick design revisions, high execution speeds and powerful debugging techniques. The proposed design is modeled using VHDL and prototyped on Xilinx Virtex® FPGA.

  5. Advances in neuromorphic hardware exploiting emerging nanoscale devices

    CERN Document Server

    2017-01-01

    This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

  6. Hardware support for CSP on a Java chip multiprocessor

    DEFF Research Database (Denmark)

    Gruian, Flavius; Schoeberl, Martin

    2013-01-01

    Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded...... applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on-chip...... communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were...

  7. Verification of OpenSSL version via hardware performance counters

    Science.gov (United States)

    Bruska, James; Blasingame, Zander; Liu, Chen

    2017-05-01

    Many forms of malware and security breaches exist today. One type of breach downgrades a cryptographic program by employing a man-in-the-middle attack. In this work, we explore the utilization of hardware events in conjunction with machine learning algorithms to detect which version of OpenSSL is being run during the encryption process. This allows for the immediate detection of any unknown downgrade attacks in real time. Our experimental results indicated this detection method is both feasible and practical. When trained with normal TLS and SSL data, our classifier was able to detect which protocol was being used with 99.995% accuracy. After the scope of the hardware event recording was enlarged, the accuracy diminished greatly, but to 53.244%. Upon removal of TLS 1.1 from the data set, the accuracy returned to 99.905%.

  8. Fast and Reliable Mouse Picking Using Graphics Hardware

    Directory of Open Access Journals (Sweden)

    Hanli Zhao

    2009-01-01

    Full Text Available Mouse picking is the most commonly used intuitive operation to interact with 3D scenes in a variety of 3D graphics applications. High performance for such operation is necessary in order to provide users with fast responses. This paper proposes a fast and reliable mouse picking algorithm using graphics hardware for 3D triangular scenes. Our approach uses a multi-layer rendering algorithm to perform the picking operation in linear time complexity. The objectspace based ray-triangle intersection test is implemented in a highly parallelized geometry shader. After applying the hardware-supported occlusion queries, only a small number of objects (or sub-objects are rendered in subsequent layers, which accelerates the picking efficiency. Experimental results demonstrate the high performance of our novel approach. Due to its simplicity, our algorithm can be easily integrated into existing real-time rendering systems.

  9. Follow-the-Leader Control for the PIPS Prototype Hardware

    Science.gov (United States)

    Williams, Robert L. II; Lippitt, Thimas

    1996-01-01

    This report describes the payload inspection and processing system (PIPS), an automated system programmed off-line for inspection of space shuttle payloads after integration and prior to launch. PIPS features a hyper-redundant 18-degree of freedom (DOF) serpentine truss manipulator capable of snake like motions to avoid obstacles. During the summer of 1995, the author worked on the same project, developing a follow-the-leader (FTL) algorithm in graphical simulation which ensures whole arm collision avoidance by forcing ensuing links to follow the same tip trajectory. The summer 1996 work was to control the prototype PIPS hardware in follow-the-leader mode. The project was successful in providing FTL control in hardware. The STS-82 payload mockup was used in the laboratory to demonstrate serpentine motions to avoid obstacles in a realistic environment.

  10. Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

    Science.gov (United States)

    Soditus, Sharon M.

    2006-01-01

    Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

  11. The LISA Pathfinder interferometry-hardware and system testing

    Energy Technology Data Exchange (ETDEWEB)

    Audley, H; Danzmann, K; MarIn, A Garcia; Heinzel, G; Monsky, A; Nofrarias, M; Steier, F; Bogenstahl, J [Albert-Einstein-Institut, Max-Planck-Institut fuer Gravitationsphysik und Universitaet Hannover, 30167 Hannover (Germany); Gerardi, D; Gerndt, R; Hechenblaikner, G; Johann, U; Luetzow-Wentzky, P; Wand, V [EADS Astrium GmbH, Friedrichshafen (Germany); Antonucci, F [Dipartimento di Fisica, Universita di Trento and INFN, Gruppo Collegato di Trento, 38050 Povo, Trento (Italy); Armano, M [European Space Astronomy Centre, European Space Agency, Villanueva de la Canada, 28692 Madrid (Spain); Auger, G; Binetruy, P [APC UMR7164, Universite Paris Diderot, Paris (France); Benedetti, M [Dipartimento di Ingegneria dei Materiali e Tecnologie Industriali, Universita di Trento and INFN, Gruppo Collegato di Trento, Mesiano, Trento (Italy); Boatella, C, E-mail: antonio.garcia@aei.mpg.de [CNES, DCT/AQ/EC, 18 Avenue Edouard Belin, 31401 Toulouse, Cedex 9 (France)

    2011-05-07

    Preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model (EM) of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on an optical system level. The results and test procedures of these campaigns will be utilized directly in the ground-based flight hardware tests, and subsequently during in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MATLAB-based LTP data analysis toolbox. This paper presents an overview of the results from the EM test campaign that was successfully completed in December 2009.

  12. Hardware and software fault tolerance - A unified architectural approach

    Science.gov (United States)

    Lala, Jaynarayan H.; Alger, Linda S.

    1988-01-01

    The loss of hardware fault tolerance which often arises when design diversity is used to improve the fault tolerance of computer software is considered analytically, and a unified design approach is proposed to avoid the problem. The fundamental theory of fault-tolerant (FT) architectures is reviewed; the current status of design-diversity software development is surveyed; and the FT-processor/attached-processor (FTP/AP) architecture developed by Lala et al. (1986) is described in detail and illustrated with diagrams. FTP/AP is shown to permit efficient implementation of N-version FT software while still tolerating random hardware failures with very high coverage; the reliability is found to be significantly higher than that of conventional majority-vote N-version software.

  13. Reconfigurable hardware-software codesign methodology for protein identification.

    Science.gov (United States)

    Gudur, Venkateshwarlu Y; Thallada, Sandeep; Deevi, Abhinay R; Gande, Venkata Krishna; Acharyya, Amit; Bhandari, Vasundhra; Sharma, Paresh; Khursheed, Saqib; Naik, Ganesh R

    2016-08-01

    In this paper we propose an on-the-fly reconfigurable hardware-software codesign based reconfigurable solution for real-time protein identification. Reconfigurable string matching is performed in the disciplines of protein identification and biomarkers discovery. With the generation of plethora of sequenced data and number of biomarkers for several diseases, it is becoming necessary to have an accelerated processing and on-the-fly reconfigurable system design methodology to bring flexibility to its usage in the medical science community without the need of changing the entire hardware every time with the advent of new biomarker or protein. The proteome database of human at UniProtKB (Proteome ID up000005640) comprising of 42132 canonical and isoform proteins with variable database-size are used for testing the proposed design and the performance of the proposed system has been found to compare favorably with the state-of-the-art approaches with the additional advantage of real-time reconfigurability.

  14. Cumulative Measurement Errors for Dynamic Testing of Space Flight Hardware

    Science.gov (United States)

    Winnitoy, Susan

    2012-01-01

    Located at the NASA Johnson Space Center in Houston, TX, the Six-Degree-of-Freedom Dynamic Test System (SDTS) is a real-time, six degree-of-freedom, short range motion base simulator originally designed to simulate the relative dynamics of two bodies in space mating together (i.e., docking or berthing). The SDTS has the capability to test full scale docking and berthing systems utilizing a two body dynamic docking simulation for docking operations and a Space Station Remote Manipulator System (SSRMS) simulation for berthing operations. The SDTS can also be used for nonmating applications such as sensors and instruments evaluations requiring proximity or short range motion operations. The motion base is a hydraulic powered Stewart platform, capable of supporting a 3,500 lb payload with a positional accuracy of 0.03 inches. The SDTS is currently being used for the NASA Docking System testing and has been also used by other government agencies. The SDTS is also under consideration for use by commercial companies. Examples of tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility integrates a dynamic simulation of on-orbit spacecraft mating or de-mating using flight-like mechanical interface hardware. A force moment sensor is used for input during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents unique challenges, one particular area of interest involves the use of external measurement systems to ensure accurate feedback of dynamic contact. The measurement systems for the test facility have two separate functions. The first is to take static measurements of facility and test hardware to determine both the static and moving frames used in the simulation and control system. The test hardware must be measured after each configuration change to determine both sets of reference frames. The second function is to take dynamic

  15. Reliable Event Detectors for Constrained Resources Wireless Sensor Node Hardware

    Directory of Open Access Journals (Sweden)

    López Trinidad MarcoAntonio

    2009-01-01

    Full Text Available Abstract A novel event detector algorithm, which points out in-door acoustic human activities, for constrained wireless sensor node hardware is proposed in the present paper. In our approach, event detections are computed from the signal energy statistics change rate at two instants separated by an samples interval. The experimentation is run in two phases: (i the detector characterisation and tuning seek detector configurations that enable event detections from three acoustic human activities: closing a door, dropping a plastic bottle, and clapping;(ii event detector validation tests measure the reliability to signal events from general acoustic activities, people talking particularly. The test results, which included emulated node hardware, actual sensor node, and a one-hop WSN, demonstrate the detector implementations signaled successfully events. And for the WSN, we found that event detections decay in a nonlinear fashion as the distance , between the acoustic signal source and the sensor, is increased.

  16. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

  17. New Techniques for Implementation of Hardware Algorithms inside FPGA Circuits

    Directory of Open Access Journals (Sweden)

    IOAN, A. D.

    2010-05-01

    Full Text Available This work presents a less known theoretical method for the synthesis of complex hardware automata by using the transition matrix, together with a new practical method for visual implementation inside FPGA circuits, with library schematic symbols from the "Altium Designer" software environment. Because these techniques need to be presented by example, the classical shift and add unsigned multiply algorithm was chosen for review. Obviously, this is not the most efficient algorithm, but it serves the declared purpose and it can still be used in a real system when the hardware must be minimal. Furthermore, an essential correction to the optimal version of this algorithm was made. The techniques are exemplified by doing an original implementation: starting from the initial organigram, passing through transition matrix synthesis stage and reaching to the final fully functional system on a "Digilent Spartan-3" FPGA development board, which includes the user interface too.

  18. Computer organization and design the hardware/software interface

    CERN Document Server

    Patterson, David A

    2013-01-01

    The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with updated content featuring tablet computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures. Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, "Going Faster," used throughout the text to demonstrate extremely effective optimization techniques. Also new to this edition is discussion of the "Eight Great Ideas" of computer architecture. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Optimization techniques featured throughout the text. It covers parallelism in depth with...

  19. Summary of multi-core hardware and programming model investigations

    Energy Technology Data Exchange (ETDEWEB)

    Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

    2008-05-01

    This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

  20. Object oriented hardware-software test bench for OMTF diagnosis

    Science.gov (United States)

    Drabik, Pawel; Pozniak, Krzysztof T.; Bunkowski, Karol; Zawistowski, Krystian; Byszuk, Adrian; Bluj, Michał; Doroba, Krzysztof; Górski, Maciej; Kalinowski, Artur; Kierzkowski, Krzysztof; Konecki, Marcin; Królikowski, Jan; Oklinski, Wojciech; Olszewski, Michał; Skala, Aleksander; Zabołotny, Wojciech M.

    2015-09-01

    In this paper the object oriented hardware-software model and its sample implementation of diagnostics for the Overlap Muon Track Finder trigger for the CMS experiment in CERN is described. It presents realization of test-bench for control and diagnosis class of multichannel, distributed measurement systems based on FPGA chips. The test-bench fulfills requirements for system's rapid changes, configurability and efficiency. This ability is very significant and desirable by expanded electronic systems. The solution described is a software model based on a method of address space management called the Component Internal Interface (CII). Establishment of stable link between hardware and software, as a purpose of designed and realized programming environment, is presented. The test-bench implementation and example of OMTF algorithm test is presented.

  1. Software and Hardware for Suborbital Telepresence: UAVs on the Web

    Science.gov (United States)

    Sorenson, C. E.; Freudinger, L. C.; Yarbrough, S. K.; Jennison, C. D.; Miller, M. J.; Friets, E. M.; Blakeslee, R. J.; Mach, D. M.; Bateman, M. G.; Bailey, J. C.; Hall, J. M.

    2005-12-01

    A NASA Dryden project creating prototype sensor web tools has resulted in software and hardware for implementing network telemetry, telepresence, and other data system functions for platforms including UAVs. The Research Environment for Vehicle-Embedded Analysis on Linux (REVEAL) software is a self-configuring/verifying/documenting framework for realtime embedded and distributed data systems based on open standards XML. With interfaces for instruments, avionics, and networking, using small PC/104 hardware with one or more Iridium modems, REVEAL systems are well suited to long endurance UAVs. These systems serve as a telemetry and communications gateway for internet-based experimenters. REVEAL systems also provide traditional Earth Science platform data system services, configured by and for each experimenter in a secure manner. On the ground segment, buffering middleware enables efficient data distribution across the internet. The innovative REVEAL architecture and its use by experimenters on recent missions using NASA's ER-2 and General Atomics Altair aircraft is described.

  2. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  3. Corrosion Testing of Stainless Steel Fuel Cell Hardware

    Energy Technology Data Exchange (ETDEWEB)

    Wilson, M.S.; Zawodzinski, C.; Gottesfeld, S.

    1998-11-01

    Metal hardware is gaining increasing interest in polymer electrolyte fuel cell (PEFC) development as a possible alternative to machined graphite hardware because of its potential for low-cost manufacturing combined with its intrinsic high conductivity, minimal permeability and advantageous mechanical properties. A major barrier to more widespread use of metal hardware has been the susceptibility of various metals to corrosion. Few pure metals can withstand the relatively aggressive environment of a fuel cell and thus the choices for hardware are quite limited. Precious metals such as platinum or gold are prohibitively expensive and so tend to be utilized as coatings on inexpensive substrates such as aluminum or stainless steel. The main challenge with coatings has been to achieve pin-hole free surfaces that will remain so after years of use. Titanium has been used to some extent and though it is very corrosion-resistant, it is also relatively expensive and often still requires some manner of surface coating to prevent the formation of a poorly conducting oxide layer. In contrast, metal alloys may hold promise as potentially low-cost, corrosion-resistant materials for bipolar plates. The dozens of commercially available stainless steel and nickel based alloys have been specifically formulated to offer a particular advantage depending upon their application. In the case of austenitic stainless steels, for example, 316 SS contains molybdenum and a higher chromium content than its more common counterpart, 304 SS, that makes it more noble and increases its corrosion resistance. Likewise, 316L SS contains less carbon than 316 SS to make it easier to weld. A number of promising corrosion-resistant, highly noble alloys such as Hastelloy{trademark} or Duplex{trademark} (a stainless steel developed for seawater service) are available commercially, but are expensive and difficult to obtain in various forms (i.e. wire screen, foil, etc.) or in small amounts for R and D

  4. Spinal fusion-hardware construct: Basic concepts and imaging review

    National Research Council Canada - National Science Library

    Mohamed Ragab Nouh

    2012-01-01

    ...篙嚣篙。…岫。。~”…一“””‘““doi:lD4329/wjr v4i5193…“。“。。嚣%善£芜高嚣@2012 Bm5kd。≈All r‘ghts Tes~edSpinal fusion-hardware construct:Basic concepts andimaging reviewHohamed...

  5. Hardware-Assisted Large-Scale Neuroevolution for Multiagent Learning

    Science.gov (United States)

    2014-12-30

    timize the performance of our probabilistic convolver, we developed four novel hardware techniques—Segmented Memory Swapping , Stochastic Mixing Scheme...Phone Currency Brian Michael Sargent 407/823-3304 USD Ship To: See Detail Below Bill To: 12424 Research Parkway, Suite 300 Orlando FL 32826-3249 United...2013-04-08 Freight Terms Ship VIa Destination, Freight Best Way Preoav Phone Currency 407/823-534 7 USD Vendor:0000071428 BEEcube Inc 39465 Paseo

  6. Implementation of a Hardware Ray Tracer for digital design education

    OpenAIRE

    Eggen, Jonas Agentoft

    2017-01-01

    Digital design is a large and complex field of electronic engineering, and learning digital design requires maturing over time. The learning process can be facilitated by making use of a single learning platform throughout a whole course. A learning platform built around a hardware ray tracer can be used in illustrating many important aspects of digital design. A unified learning platform allows students to delve into intricate details of digital design while still seeing the bigger pictur...

  7. ONMCGP: Orthogonal Neighbourhood Mutation Cartesian Genetic Programming for Evolvable Hardware

    Science.gov (United States)

    I, Fuchuan N.; I, Yuanxiang L.; E, Peng K.

    2014-03-01

    Evolvable Hardware is facing the problems of scalability and stalling effect. This paper proposed a novel Orthogonal Neighbourhood Mutation (ONM) operator in Cartesian genetic programming (CGP), to reduce the stalling effect in CGP and improve the efficiency of the algorithms.The method incorporates with Differential Evolution strategy. Demonstrated by experiments on benchmark, the proposed Orthogonal Neighbourhood Search can jump out of Local optima, reduce the stalling effect in CGP and the algorithm convergence faster.

  8. Hardware realization of chaos based block cipher for image encryption

    KAUST Repository

    Barakat, Mohamed L.

    2011-12-01

    Unlike stream ciphers, block ciphers are very essential for parallel processing applications. In this paper, the first hardware realization of chaotic-based block cipher is proposed for image encryption applications. The proposed system is tested for known cryptanalysis attacks and for different block sizes. When implemented on Virtex-IV, system performance showed high throughput and utilized small area. Passing successfully in all tests, our system proved to be secure with all block sizes. © 2011 IEEE.

  9. A Methodology for Formal Hardware Verification, with Application to Microprocessors.

    Science.gov (United States)

    1993-08-29

    Sekar and Srivas verified a simplified version of Wirth’s Lilith . Tamarack Mike Gordon illustrated his early ideas on hardware verification using a...include FM8501 [137, 86] and related designs [136, 239], simplified versions of Cayuga [227] and Lilith [2131, Tamarack [150], Viper [77], SECD [119, 120...techniques in a different proof system, called SBL, to verify a simplified version of Wirth’s LILITH processor. Their model included a simplified form

  10. Hardware implementation of machine vision systems: image and video processing

    Science.gov (United States)

    Botella, Guillermo; García, Carlos; Meyer-Bäse, Uwe

    2013-12-01

    This contribution focuses on different topics covered by the special issue titled `Hardware Implementation of Machine vision Systems' including FPGAs, GPUS, embedded systems, multicore implementations for image analysis such as edge detection, segmentation, pattern recognition and object recognition/interpretation, image enhancement/restoration, image/video compression, image similarity and retrieval, satellite image processing, medical image processing, motion estimation, neuromorphic and bioinspired vision systems, video processing, image formation and physics based vision, 3D processing/coding, scene understanding, and multimedia.

  11. FY16 ISCP Nuclear Counting Facility Hardware Expansion Summary

    Energy Technology Data Exchange (ETDEWEB)

    Church, Jennifer A. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Kashgarian, Michaele [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Wooddy, Todd [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Haslett, Bob [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Torretto, Phil [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

    2016-09-15

    Hardware expansion and detector calibrations were the focus of FY 16 ISCP efforts in the Nuclear Counting Facility. Work focused on four main objectives: 1) Installation, calibration, and validation of 4 additional HPGe gamma spectrometry systems; including two Low Energy Photon Spectrometers (LEPS). 2) Re-Calibration and validation of 3 previously installed gamma-ray detectors, 3) Integration of the new systems into the NCF IT infrastructure, and 4) QA/QC and maintenance of current detector systems.

  12. S-1 project. Volume II. Hardware. 1979 annual report

    Energy Technology Data Exchange (ETDEWEB)

    1979-01-01

    This volume includes highlights of the design of the Mark IIA uniprocessor (SMI-2), and the SCALD II user's manual. SCALD (structured computer-aided logic design system) cuts the cost and time required to design logic by letting the logic designer express ideas as naturally as possible, and by eliminating as many errors as possible - through consistency checking, simulation, and timing verification - before the hardware is built. (GHT)

  13. IDEAS and App Development Internship in Hardware and Software Design

    Science.gov (United States)

    Alrayes, Rabab D.

    2016-01-01

    In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

  14. Reliable Event Detectors for Constrained Resources Wireless Sensor Node Hardware

    OpenAIRE

    López Trinidad MarcoAntonio; Valle Maurizio

    2009-01-01

    Abstract A novel event detector algorithm, which points out in-door acoustic human activities, for constrained wireless sensor node hardware is proposed in the present paper. In our approach, event detections are computed from the signal energy statistics change rate at two instants separated by an samples interval. The experimentation is run in two phases: (i) the detector characterisation and tuning seek detector configurations that enable event detections from three acoustic human activi...

  15. Perforating the atretic pulmonary valve with CTO hardware: Technical aspects.

    Science.gov (United States)

    Patil, Nilkanth C; Saxena, Anita; Gupta, Saurabh K; Juneja, Rajnish; Mishra, Sundeep; Ramakrishnan, Sivasubramanian; Kothari, Shyam S

    2016-11-01

    To review the success and technical aspects of pulmonary valve (PV) perforation using chronic total occlusion (CTO) hardware in patients with pulmonary atresia and intact ventricular septum (PA-IVS). Interventional therapy is possible in selected patients with PA-IVS. Among the various interventional options available, radiofrequency and laser assisted perforation may be more successful, but require expertise and may be substantially costly. We describe the technique of mechanical catheter PV perforation using currently available coronary hardware meant for coronary CTO in nine cases with PA-IVS. After complete echocardiographic evaluation and informed parental consent was obtained, patients were electively intubated, mechanically ventilated, adequately heparinized and were placed on intravenous prostaglandin infusion. Basic steps involved were-localizing the atretic segment and accomplishing coaxial alignment of catheters using biplane fluoroscopy, crossing the atretic segment with the soft end of perforating guidewire, stabilizing the assembly and performing graded balloon dilatation with the balloon size never exceeding 130% of pulmonary annulus diameter. For crossing the atretic PV, a retrograde approach was used in one patient where the antegrade approach was not possible. The procedure was successful in 8/9 cases (89%). Valve opening was achieved in all eight patients with immediate fall in right ventricular (RV) systolic pressures. One neonate died following surgery after catheter induced RV perforation. All surviving cases were discharged from the hospital in good general condition with no evidence of heart failure and a room air oxygen saturation of >85%. No patient required an additional pulmonary irrigation procedure. With appropriate patient and hardware selection, PV perforation using readily available coronary hardware is feasible in PA-IVS. © 2014 Wiley Periodicals, Inc. © 2014 Wiley Periodicals, Inc.

  16. The technological future of 7 T MRI hardware.

    Science.gov (United States)

    Webb, A G; Van de Moortele, P F

    2016-09-01

    In this article we present our projections of future hardware developments on 7 T human MRI systems. These include compact cryogen-light magnets, improved gradient performance, integrated RF-receive and direct current shimming coil arrays, new RF technology with adaptive impedance matching, patient-specific specific absorption rate estimation and monitoring, and increased integration of physiological monitoring systems. Copyright © 2015 John Wiley & Sons, Ltd. Copyright © 2015 John Wiley & Sons, Ltd.

  17. Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

    Directory of Open Access Journals (Sweden)

    Liang Ying-Chang

    2005-01-01

    Full Text Available This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP -based communication systems, including orthogonal frequency-division multiplexing (OFDM, single-carrier cyclic-prefix (SCCP system, multicarrier (MC code-division multiple access (MC-CDMA, MC direct-sequence CDMA (MC-DS-CDMA, CP-based CDMA (CP-CDMA, and CP-based direct-sequence CDMA (CP-DS-CDMA. A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.

  18. 2D neural hardware versus 3D biological ones

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-12-31

    This paper will present important limitations of hardware neural nets as opposed to biological neural nets (i.e. the real ones). The author starts by discussing neural structures and their biological inspirations, while mentioning the simplifications leading to artificial neural nets. Going further, the focus will be on hardware constraints. The author will present recent results for three different alternatives of implementing neural networks: digital, threshold gate, and analog, while the area and the delay will be related to neurons' fan-in and weights' precision. Based on all of these, it will be shown why hardware implementations cannot cope with their biological inspiration with respect to their power of computation: the mapping onto silicon lacking the third dimension of biological nets. This translates into reduced fan-in, and leads to reduced precision. The main conclusion is that one is faced with the following alternatives: (1) try to cope with the limitations imposed by silicon, by speeding up the computation of the elementary silicon neurons; (2) investigate solutions which would allow one to use the third dimension, e.g. using optical interconnections.

  19. Hardware demonstration of high-speed networks for satellite applications.

    Energy Technology Data Exchange (ETDEWEB)

    Donaldson, Jonathon W.; Lee, David S.

    2008-09-01

    This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

  20. Using Innovative Technologies for Manufacturing and Evaluating Rocket Engine Hardware

    Science.gov (United States)

    Betts, Erin M.; Hardin, Andy

    2011-01-01

    Many of the manufacturing and evaluation techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing and evaluating hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) and white light scanning are being adopted and evaluated for their use on J-2X, with hopes of employing both technologies on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powdered metal manufacturing process in order to produce complex part geometries. The white light technique is a non-invasive method that can be used to inspect for geometric feature alignment. Both the DMLS manufacturing method and the white light scanning technique have proven to be viable options for manufacturing and evaluating rocket engine hardware, and further development and use of these techniques is recommended.

  1. Secure Hardware Performance Analysis in Virtualized Cloud Environment

    Directory of Open Access Journals (Sweden)

    Chee-Heng Tan

    2013-01-01

    Full Text Available The main obstacle in mass adoption of cloud computing for database operations is the data security issue. In this paper, it is shown that IT services particularly in hardware performance evaluation in virtual machine can be accomplished effectively without IT personnel gaining access to real data for diagnostic and remediation purposes. The proposed mechanisms utilized TPC-H benchmark to achieve 2 objectives. First, the underlying hardware performance and consistency is supervised via a control system, which is constructed using a combination of TPC-H queries, linear regression, and machine learning techniques. Second, linear programming techniques are employed to provide input to the algorithms that construct stress-testing scenarios in the virtual machine, using the combination of TPC-H queries. These stress-testing scenarios serve 2 purposes. They provide the boundary resource threshold verification to the first control system, so that periodic training of the synthetic data sets for performance evaluation is not constrained by hardware inadequacy, particularly when the resources in the virtual machine are scaled up or down which results in the change of the utilization threshold. Secondly, they provide a platform for response time verification on critical transactions, so that the expected Quality of Service (QoS from these transactions is assured.

  2. Hardware Synchronization for Embedded Multi-Core Processors

    DEFF Research Database (Denmark)

    Stoif, Christian; Schoeberl, Martin; Liccardi, Benito

    2011-01-01

    Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establi...... single-ported memory if the multiple cores use inherent parallelism by locking shared memory more intelligently using an address-sensitive method......., establishing coherence and consistency for different types of shared memory by hardware means. Also support for point-to-point synchronization between the processor cores is realized implementing different hardware barriers. The practical examinations focus on the logical first step from single- to dual......-core systems, using an FPGA-development board with two hard PowerPC processor cores. Best- and worst-case results, together with intensive benchmarking of all synchronization primitives implemented, show the expected superiority of the hardware solutions. It is also shown that dual-ported memory outperforms...

  3. Weight and the Future of Space Flight Hardware Cost Modeling

    Science.gov (United States)

    Prince, Frank A.

    2003-01-01

    Weight has been used as the primary input variable for cost estimating almost as long as there have been parametric cost models. While there are good reasons for using weight, serious limitations exist. These limitations have been addressed by multi-variable equations and trend analysis in models such as NAFCOM, PRICE, and SEER; however, these models have not be able to address the significant time lags that can occur between the development of similar space flight hardware systems. These time lags make the cost analyst's job difficult because insufficient data exists to perform trend analysis, and the current set of parametric models are not well suited to accommodating process improvements in space flight hardware design, development, build and test. As a result, people of good faith can have serious disagreement over the cost for new systems. To address these shortcomings, new cost modeling approaches are needed. The most promising approach is process based (sometimes called activity) costing. Developing process based models will require a detailed understanding of the functions required to produce space flight hardware combined with innovative approaches to estimating the necessary resources. Particularly challenging will be the lack of data at the process level. One method for developing a model is to combine notional algorithms with a discrete event simulation and model changes to the total cost as perturbations to the program are introduced. Despite these challenges, the potential benefits are such that efforts should be focused on developing process based cost models.

  4. Efficient Hardware Implementation of the Lightweight Block Encryption Algorithm LEA

    Directory of Open Access Journals (Sweden)

    Donggeon Lee

    2014-01-01

    Full Text Available Recently, due to the advent of resource-constrained trends, such as smartphones and smart devices, the computing environment is changing. Because our daily life is deeply intertwined with ubiquitous networks, the importance of security is growing. A lightweight encryption algorithm is essential for secure communication between these kinds of resource-constrained devices, and many researchers have been investigating this field. Recently, a lightweight block cipher called LEA was proposed. LEA was originally targeted for efficient implementation on microprocessors, as it is fast when implemented in software and furthermore, it has a small memory footprint. To reflect on recent technology, all required calculations utilize 32-bit wide operations. In addition, the algorithm is comprised of not complex S-Box-like structures but simple Addition, Rotation, and XOR operations. To the best of our knowledge, this paper is the first report on a comprehensive hardware implementation of LEA. We present various hardware structures and their implementation results according to key sizes. Even though LEA was originally targeted at software efficiency, it also shows high efficiency when implemented as hardware.

  5. On Meanings and Descriptions

    Directory of Open Access Journals (Sweden)

    Mieke Bal

    1981-09-01

    Full Text Available Although descriptive passages would appear to be of marginal importance in narrative texts, they are, in fact, of both logical and semantic necessity. Narratology, therefore, must take these segments into account. In this article, I shall survey the present situation in this field and compare rival points of view. I shall also offer several suggestions for analyzing descriptions. The following topics will be discussed: the nature of description as a specific type of discourse which makes it recognizable as such; the internal structure of description; the place and function of descriptions in the text as a whole. In the latter section, the semantic impact of descriptions in the overall meaning of narrative texts will be accounted for. This article is intended as a contribution to the theory of description as a part of narratology. It also has a didactic purpose, since it proposes a model for the analysis of texts which can be used for systematic text-study, both in a historical and a comparative perspective.

  6. Open Coding Descriptions

    Directory of Open Access Journals (Sweden)

    Barney G. Glaser, PhD, Hon PhD

    2016-12-01

    Full Text Available Open coding is a big source of descriptions that must be managed and controlled when doing GT research. The goal of generating a GT is to generate an emergent set of concepts and their properties that fit and work with relevancy to be integrated into a theory. To achieve this goal, the researcher begins his research with open coding, that is coding all his data in every possible way. The consequence of this open coding is a multitude of descriptions for possible concepts that often do not fit in the emerging theory. Thus in this case the researcher ends up with many irrelevant descriptions for concepts that do not apply. To dwell on descriptions for inapplicable concepts ruins the GT theory as it starts. It is hard to stop. Confusion easily sets in. Switching the study to a QDA is a simple rescue. Rigorous focusing on emerging concepts is vital before being lost in open coding descriptions. It is important, no matter how interesting the description may become. Once a core is possible, selective coding can start which will help control against being lost in multiple descriptions.

  7. Description of vegetation types

    Data.gov (United States)

    US Fish and Wildlife Service, Department of the Interior — This document provides descriptions of five vegetation types found in Iowa- oak savannah, mature hardwoods, floodplain woods, scrub woods, and riparian woods. Oak...

  8. Descriptive sensory evaluations

    DEFF Research Database (Denmark)

    Dehlholm, Christian

    . The new methods were compared to the Flash Profile, Napping and conventional descriptive profiling. Furthermore, an approach for applying confidence ellipses to Multiple Factor Analysis (MFA) results from the statistical package R were suggested for the graphical validation and comparisons. PN allowed...... descriptive methodology is proposed and, based on the findings and evaluations of the studies, a concept scale that combines holistic and analytic assessor responses is proposed for future evaluations....

  9. NCERA-101 STATION REPORT - KENNEDY SPACE CENTER: Large Plant Growth Hardware for the International Space Station

    Science.gov (United States)

    Massa, Gioia D.

    2013-01-01

    This is the station report for the national controlled environments meeting. Topics to be discussed will include the Veggie and Advanced Plant Habitat ISS hardware. The goal is to introduce this hardware to a potential user community.

  10. Analysis of Systems Hardware Flown on LDEF-Results of the Systems Special Investigation Group

    National Research Council Canada - National Science Library

    Dursch, H

    1992-01-01

    .... The Systems Special Investigation Group (Systems SIG) was formed to investigate the effects of the long term exposure to LEO on systems related hardware and to coordinate and collate all systems analysis of LDEF hardware...

  11. Imaging current spine hardware: part 1, cervical spine and fracture fixation.

    Science.gov (United States)

    Petscavage-Thomas, Jonelle M; Ha, Alice S

    2014-08-01

    The goals of this article are to review the indications for use, the materials, and the designs of hardware more commonly used in the cervical spine; to discuss alternatives for each of the different types of hardware; to review normal postoperative imaging findings; to describe the appropriateness of different imaging modalities for postoperative evaluation; and to illustrate examples of hardware complications. This article will also review vertebral body fracture fixation. Stabilization and fusion of the spine with intervertebral disk replacement, artificial ligaments, spinous process distraction devices, plate-and-rod systems, dynamic posterior fusion devices, and implants composed of new types of material are increasingly more common in the contemporary surgical practice. These spinal hardware devices will be seen more often in radiology practice. Successful postoperative radiologic evaluation of spinal hardware necessitates an understanding of the fundamental design of the hardware, the physiologic objective of the hardware, normal and abnormal postoperative imaging appearances, and complications unique to the hardware.

  12. Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.

    Science.gov (United States)

    Rast, Alexander; Galluppi, Francesco; Davies, Sergio; Plana, Luis; Patterson, Cameron; Sharp, Thomas; Lester, David; Furber, Steve

    2011-11-01

    Dedicated hardware is becoming increasingly essential to simulate emerging very-large-scale neural models. Equally, however, it needs to be able to support multiple models of the neural dynamics, possibly operating simultaneously within the same system. This may be necessary either to simulate large models with heterogeneous neural types, or to simplify simulation and analysis of detailed, complex models in a large simulation by isolating the new model to a small subpopulation of a larger overall network. The SpiNNaker neuromimetic chip is a dedicated neural processor able to support such heterogeneous simulations. Implementing these models on-chip uses an integrated library-based tool chain incorporating the emerging PyNN interface that allows a modeller to input a high-level description and use an automated process to generate an on-chip simulation. Simulations using both LIF and Izhikevich models demonstrate the ability of the SpiNNaker system to generate and simulate heterogeneous networks on-chip, while illustrating, through the network-scale effects of wavefront synchronisation and burst gating, methods that can provide effective behavioural abstractions for large-scale hardware modelling. SpiNNaker's asynchronous virtual architecture permits greater scope for model exploration, with scalable levels of functional and temporal abstraction, than conventional (or neuromorphic) computing platforms. The complete system illustrates a potential path to understanding the neural model of computation, by building (and breaking) neural models at various scales, connecting the blocks, then comparing them against the biology: computational cognitive neuroscience. Copyright © 2011 Elsevier Ltd. All rights reserved.

  13. 49 CFR 238.105 - Train electronic hardware and software safety.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions in...

  14. 34 CFR 464.42 - What limit applies to purchasing computer hardware and software?

    Science.gov (United States)

    2010-07-01

    ... computer hardware and software? Not more than ten percent of funds received under any grant under this part may be used to purchase computer hardware or software. (Authority: 20 U.S.C. 1208aa(f)) ... 34 Education 3 2010-07-01 2010-07-01 false What limit applies to purchasing computer hardware and...

  15. Using Innovative Technologies for Manufacturing Rocket Engine Hardware

    Science.gov (United States)

    Betts, E. M.; Eddleman, D. E.; Reynolds, D. C.; Hardin, N. A.

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As the United States enters into the next space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, rapid manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on NASA s Space Launch System (SLS) upper stage engine, J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator (GG) discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using a workhorse gas generator (WHGG) test fixture at MSFC's East Test Area, the duct was subjected to extreme J-2X hot gas environments during 7 tests for a total of 537 seconds of hot-fire time. The duct underwent extensive post-test evaluation and showed no signs of degradation. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  16. Hardware simulation of fuel cell/gas turbine hybrids

    Science.gov (United States)

    Smith, Thomas Paul

    Hybrid solid oxide fuel cell/gas turbine (SOFC/GT) systems offer high efficiency power generation, but face numerous integration and operability challenges. This dissertation addresses the application of hardware-in-the-loop simulation (HILS) to explore the performance of a solid oxide fuel cell stack and gas turbine when combined into a hybrid system. Specifically, this project entailed developing and demonstrating a methodology for coupling a numerical SOFC subsystem model with a gas turbine that has been modified with supplemental process flow and control paths to mimic a hybrid system. This HILS approach was implemented with the U.S. Department of Energy Hybrid Performance Project (HyPer) located at the National Energy Technology Laboratory. By utilizing HILS the facility provides a cost effective and capable platform for characterizing the response of hybrid systems to dynamic variations in operating conditions. HILS of a hybrid system was accomplished by first interfacing a numerical model with operating gas turbine hardware. The real-time SOFC stack model responds to operating turbine flow conditions in order to predict the level of thermal effluent from the SOFC stack. This simulated level of heating then dynamically sets the turbine's "firing" rate to reflect the stack output heat rate. Second, a high-speed computer system with data acquisition capabilities was integrated with the existing controls and sensors of the turbine facility. In the future, this will allow for the utilization of high-fidelity fuel cell models that infer cell performance parameters while still computing the simulation in real-time. Once the integration of the numeric and the hardware simulation components was completed, HILS experiments were conducted to evaluate hybrid system performance. The testing identified non-intuitive transient responses arising from the large thermal capacitance of the stack that are inherent to hybrid systems. Furthermore, the tests demonstrated the

  17. Parameter Validation for Evaluation of Spaceflight Hardware Reusability

    Science.gov (United States)

    Childress-Thompson, Rhonda; Dale, Thomas L.; Farrington, Phillip

    2017-01-01

    Within recent years, there has been an influx of companies around the world pursuing reusable systems for space flight. Much like NASA, many of these new entrants are learning that reusable systems are complex and difficult to acheive. For instance, in its first attempts to retrieve spaceflight hardware for future reuse, SpaceX unsuccessfully tried to land on a barge at sea, resulting in a crash-landing. As this new generation of launch developers continues to develop concepts for reusable systems, having a systematic approach for determining the most effective systems for reuse is paramount. Three factors that influence the effective implementation of reusability are cost, operability and reliability. Therefore, a method that integrates these factors into the decision-making process must be utilized to adequately determine whether hardware used in space flight should be reused or discarded. Previous research has identified seven features that contribute to the successful implementation of reusability for space flight applications, defined reusability for space flight applications, highlighted the importance of reusability, and presented areas that hinder successful implementation of reusability. The next step is to ensure that the list of reusability parameters previously identified is comprehensive, and any duplication is either removed or consolidated. The characteristics to judge the seven features as good indicators for successful reuse are identified and then assessed using multiattribute decision making. Next, discriminators in the form of metrics or descriptors are assigned to each parameter. This paper explains the approach used to evaluate these parameters, define the Measures of Effectiveness (MOE) for reusability, and quantify these parameters. Using the MOEs, each parameter is assessed for its contribution to the reusability of the hardware. Potential data sources needed to validate the approach will be identified.

  18. Advances in metered dose inhaler technology: hardware development.

    Science.gov (United States)

    Stein, Stephen W; Sheth, Poonam; Hodson, P David; Myrdal, Paul B

    2014-04-01

    Pressurized metered dose inhalers (MDIs) were first introduced in the 1950s and they are currently widely prescribed as portable systems to treat pulmonary conditions. MDIs consist of a formulation containing dissolved or suspended drug and hardware needed to contain the formulation and enable efficient and consistent dose delivery to the patient. The device hardware includes a canister that is appropriately sized to contain sufficient formulation for the required number of doses, a metering valve capable of delivering a consistent amount of drug with each dose delivered, an actuator mouthpiece that atomizes the formulation and serves as a conduit to deliver the aerosol to the patient, and often an indicating mechanism that provides information to the patient on the number of doses remaining. This review focuses on the current state-of-the-art of MDI hardware and includes discussion of enhancements made to the device's core subsystems. In addition, technologies that aid the correct use of MDIs will be discussed. These include spacers, valved holding chambers, and breath-actuated devices. Many of the improvements discussed in this article increase the ability of MDI systems to meet regulatory specifications. Innovations that enhance the functionality of MDIs continue to be balanced by the fact that a key advantage of MDI systems is their low cost per dose. The expansion of the health care market in developing countries and the increased focus on health care costs in many developed countries will ensure that MDIs remain a cost-effective crucial delivery system for treating pulmonary conditions for many years to come.

  19. Parallel Processing with Digital Signal Processing Hardware and Software

    Science.gov (United States)

    Swenson, Cory V.

    1995-01-01

    The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

  20. Hardware evaluation platform based on GNU Radio and the USRP

    OpenAIRE

    Ingemarsson, Carl

    2009-01-01

    GNU Radio is a software framework allowing easy creation of digital signal processing applications on a regular PC. The Universal Software Radio Peripheral (USRP) is a hardware component that can be used as a radio front-end and that is connected to a PC using USB. GNU Radio and the USRP together form a system for software-defined radio. The purpose of this thesis project have been to insert a large programmable logic circuit into the system that GNU Radio and the USRP together form. The goal...

  1. Computer organization and design the hardware/software interface

    CERN Document Server

    Patterson, David A

    2009-01-01

    The classic textbook for computer systems analysis and design, Computer Organization and Design, has been thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies with examples highlighting the latest processor designs, benchmarking standards, languages and tools. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, compu

  2. Technology Corner: Dating of Electronic Hardware for Prior Art Investigations

    Directory of Open Access Journals (Sweden)

    Sellam Ismail

    2012-03-01

    Full Text Available In many legal matters, specifically patent litigation, determining and authenticating the date of computer hardware or other electronic products or components is often key to establishing the item as legitimate evidence of prior art. Such evidence can be used to buttress claims of technologies available or of events transpiring by or at a particular date.In 1945, the Electronics Industry Association published a standard, EIA 476-A, standardized in the reference Source and Date Code Marking (Electronic Industries Association, 1988.(see PDF for full tech corner

  3. Monitoring and Hardware Management for Critical Fusion Plasma Instrumentation

    Science.gov (United States)

    Carvalho, Paulo F.; Santos, Bruno; Correia, Miguel; Combo, Álvaro M.; Rodrigues, AntÓnio P.; Pereira, Rita C.; Fernandes, Ana; Cruz, Nuno; Sousa, Jorge; Carvalho, Bernardo B.; Batista, AntÓnio J. N.; Correia, Carlos M. B. A.; Gonçalves, Bruno

    2018-01-01

    Controlled nuclear fusion aims to obtain energy by particles collision confined inside a nuclear reactor (Tokamak). These ionized particles, heavier isotopes of hydrogen, are the main elements inside of plasma that is kept at high temperatures (millions of Celsius degrees). Due to high temperatures and magnetic confinement, plasma is exposed to several sources of instabilities which require a set of procedures by the control and data acquisition systems throughout fusion experiments processes. Control and data acquisition systems often used in nuclear fusion experiments are based on the Advanced Telecommunication Computer Architecture (AdvancedTCA®) standard introduced by the Peripheral Component Interconnect Industrial Manufacturers Group (PICMG®), to meet the demands of telecommunications that require large amount of data (TB) transportation at high transfer rates (Gb/s), to ensure high availability including features such as reliability, serviceability and redundancy. For efficient plasma control, systems are required to collect large amounts of data, process it, store for later analysis, make critical decisions in real time and provide status reports either from the experience itself or the electronic instrumentation involved. Moreover, systems should also ensure the correct handling of detected anomalies and identified faults, notify the system operator of occurred events, decisions taken to acknowledge and implemented changes. Therefore, for everything to work in compliance with specifications it is required that the instrumentation includes hardware management and monitoring mechanisms for both hardware and software. These mechanisms should check the system status by reading sensors, manage events, update inventory databases with hardware system components in use and maintenance, store collected information, update firmware and installed software modules, configure and handle alarms to detect possible system failures and prevent emergency scenarios

  4. Use of Hardware Battery Drill in Orthopedic Surgery.

    Science.gov (United States)

    Satish, Bhava R J; Shahdi, Masood; Ramarao, Duddupudi; Ranganadham, Atmakuri V; Kalamegam, Sundaresan

    2017-03-01

    Among the power drills (Electrical/Pneumatic/Battery) used in Orthopedic surgery, battery drill has got several advantages. Surgeons in low resource settings could not routinely use Orthopedic battery drills (OBD) due to the prohibitive cost of good drills or poor quality of other drills. "Hardware" or Engineering battery drill (HBD) is a viable alternative to OBD. HBD is easy to procure, rugged in nature, easy to maintain, durable, easily serviceable and 70 to 75 times cheaper than the standard high end OBD. We consider HBD as one of the cost effective equipment in Orthopedic operation theatres.

  5. Computer, Network, Software, and Hardware Engineering with Applications

    CERN Document Server

    Schneidewind, Norman F

    2012-01-01

    There are many books on computers, networks, and software engineering but none that integrate the three with applications. Integration is important because, increasingly, software dominates the performance, reliability, maintainability, and availability of complex computer and systems. Books on software engineering typically portray software as if it exists in a vacuum with no relationship to the wider system. This is wrong because a system is more than software. It is comprised of people, organizations, processes, hardware, and software. All of these components must be considered in an integr

  6. SYNTHESIS OF INFORMATION SYSTEM FOR SMART HOUSE HARDWARE MANAGEMENT

    Directory of Open Access Journals (Sweden)

    Vikentyeva Olga Leonidovna

    2017-10-01

    Full Text Available Subject: smart house maintenance requires taking into account a number of factors: resource-saving, reduction of operational expenditures, safety enhancement, providing comfortable working and leisure conditions. Automation of the corresponding engineering systems of illumination, climate control, security as well as communication systems and networks via utilization of contemporary technologies (e.g., IoT - Internet of Things poses a significant challenge related to storage and processing of the overwhelmingly massive volume of data whose utilization extent is extremely low nowadays. Since a building’s lifespan is large enough and exceeds the lifespan of codes and standards that take into account the requirements of safety, comfort, energy saving, etc., it is necessary to consider management aspects in the context of rational use of large data at the stage of information modeling. Research objectives: increase the efficiency of managing the subsystems of smart buildings hardware on the basis of a web-based information system that has a flexible multi-level architecture with several control loops and an adaptation model. Materials and methods: since a smart house belongs to man-machine systems, the cybernetic approach is considered as the basic method for design and research of information management system. Instrumental research methods are represented by set-theoretical modelling, automata theory and architectural principles of organization of information management systems. Results: a flexible architecture of information system for management of smart house hardware subsystems has been synthesized. This architecture encompasses several levels: client level, application level and data level as well as three layers: presentation level, actuating device layer and analytics layer. The problem of growing volumes of information processed by realtime message controller is attended by employment of sensors and actuating mechanisms with configurable

  7. Hardware support for software controlled fast reconfiguration of performance counters

    Science.gov (United States)

    Salapura, Valentina; Wisniewski, Robert W.

    2013-06-18

    Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.

  8. Configurable Hardware And Software For Multiple Related Uses

    Science.gov (United States)

    Uhrlaub, David R.; Gaines, James M.; Snoddy, William E.; Bard, Richard D.; Robinson, Lawrence W.

    1996-01-01

    Control Monitor Unit (CMU) is system of configurable hardware and software undergoing development for use in controlling and monitoring complex systems of equipment. Provides comprehensive array of capabilities for such functions as processing equipment-test data for calibration and diagnosis, controlling operation of equipment in real time, simulating operation of equipment, and processing large streams of scientific-measurement data. Automates many of ground operations involved in preparing and testing spacecraft prior to launch. Also useful in variety of similar applications; for example, testing aircraft, ships, power plants, and automated production lines.

  9. Data storage technology: Hardware and software, Appendix B

    Science.gov (United States)

    Sable, J. D.

    1972-01-01

    This project involves the development of more economical ways of integrating and interfacing new storage devices and data processing programs into a computer system. It involves developing interface standards and a software/hardware architecture which will make it possible to develop machine independent devices and programs. These will interface with the machine dependent operating systems of particular computers. The development project will not be to develop the software which would ordinarily be the responsibility of the manufacturer to supply, but to develop the standards with which that software is expected to confirm in providing an interface with the user or storage system.

  10. Study of hardware implementations of fast tracking algorithms

    Science.gov (United States)

    Song, Z.; De Lentdecker, G.; Dong, J.; Huang, G.; Léonard, A.; Robert, F.; Wang, D.; Yang, Y.

    2017-02-01

    Real-time track reconstruction at high event rates is a major challenge for future experiments in high energy physics. To perform pattern-recognition and track fitting, artificial retina or Hough transformation methods have been introduced in the field which have to be implemented in FPGA firmware. In this note we report on a case study of a possible FPGA hardware implementation approach of the retina algorithm based on a Floating-Point core. Detailed measurements with this algorithm are investigated. Retina performance and capabilities of the FPGA are discussed along with perspectives for further optimization and applications.

  11. Verification Challenges of Dynamic Testing of Space Flight Hardware

    Science.gov (United States)

    Winnitoy, Susan

    2010-01-01

    The Six Degree-of-Freedom Dynamic Test System (SDTS) is a test facility at the National Aeronautics and Space Administration (NASA) Johnson Space Center in Houston, Texas for performing dynamic verification of space structures and hardware. Some examples of past and current tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility is able to integrate a dynamic simulation of on-orbit spacecraft mating or demating using flight-like mechanical interface hardware. A force moment sensor is utilized for input to the simulation during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents many unique challenges, one particular area of interest is with respect to the use of external measurement systems to ensure accurate feedback of dynamic contact. There are many commercial off-the-shelf (COTS) measurement systems available on the market, and the test facility measurement systems have evolved over time to include two separate COTS systems. The first system incorporates infra-red sensing cameras, while the second system employs a laser interferometer to determine position and orientation data. The specific technical challenges with the measurement systems in a large dynamic environment include changing thermal and humidity levels, operational area and measurement volume, dynamic tracking, and data synchronization. The facility is located in an expansive high-bay area that is occasionally exposed to outside temperature when large retractable doors at each end of the building are opened. The laser interferometer system, in particular, is vulnerable to the environmental changes in the building. The operational area of the test facility itself is sizeable, ranging from seven meters wide and five meters deep to as much as seven meters high. Both facility measurement systems have desirable measurement volumes and the accuracies vary

  12. Deployment Testing of the De-Orbit Sail Flight Hardware

    OpenAIRE

    Hillebrandt, Martin; Meyer, Sebastian; Zander, Martin; Hühne, Christian

    2015-01-01

    The paper describes the results of the deployment testing of the De-Orbit Sail flight hardware, a drag sail for de-orbiting applications, performed by DLR. It addresses in particular the deployment tests of the fullscale sail subsystem and deployment force tests performed on the boom deployment module. For the fullscale sail testing a gravity compensation device is used which is described in detail. It allows observations of the in-plane interaction of the booms with the sail membrane and the...

  13. Resolution-independent surface rendering using programmable graphics hardware

    Science.gov (United States)

    Loop, Charles T.; Blinn, James Frederick

    2008-12-16

    Surfaces defined by a Bezier tetrahedron, and in particular quadric surfaces, are rendered on programmable graphics hardware. Pixels are rendered through triangular sides of the tetrahedra and locations on the shapes, as well as surface normals for lighting evaluations, are computed using pixel shader computations. Additionally, vertex shaders are used to aid interpolation over a small number of values as input to the pixel shaders. Through this, rendering of the surfaces is performed independently of viewing resolution, allowing for advanced level-of-detail management. By individually rendering tetrahedrally-defined surfaces which together form complex shapes, the complex shapes can be rendered in their entirety.

  14. Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA

    Directory of Open Access Journals (Sweden)

    Christoph Starke

    2012-01-01

    Full Text Available The hardware structure of a processing element used for optimization of an investment strategy for financial markets is presented. It is shown how this processing element can be multiply implemented on the massively parallel FPGA-machine RIVYERA. This leads to a speedup of a factor of about 17,000 in comparison to one single high-performance PC, while saving more than 99% of the consumed energy. Furthermore, it is shown for a special security and different time periods that the optimized investment strategy delivers an outperformance between 2 and 14 percent in relation to a buy and hold strategy.

  15. Benchmarking and Hardware-In-The-Loop Operation of a ...

    Science.gov (United States)

    Engine Performance evaluation in support of LD MTE. EPA used elements of its ALPHA model to apply hardware-in-the-loop (HIL) controls to the SKYACTIV engine test setup to better understand how the engine would operate in a chassis test after combined with future leading edge technologies, advanced high-efficiency transmission, reduced mass, and reduced roadload. Predict future vehicle performance with Atkinson engine. As part of its technology assessment for the upcoming midterm evaluation of the 2017-2025 LD vehicle GHG emissions regulation, EPA has been benchmarking engines and transmissions to generate inputs for use in its ALPHA model

  16. Reliability of semiology description.

    Science.gov (United States)

    Heo, Jae-Hyeok; Kim, Dong Wook; Lee, Seo-Young; Cho, Jinwhan; Lee, Sang-Kun; Nam, Hyunwoo

    2008-01-01

    Seizure semiology is important for classifying patients' epilepsy. Physicians usually get most of the seizure information from observers though there have been few reports on the reliability of the observers' description. This study aims at determining the reliability of observers' description of the semiology. We included 92 patients who had their habitual seizures recorded during video-EEG monitoring. We compared the semiology described by the observers with that recorded on the videotape, and reviewed which characteristics of the observers affected the reliability of their reported data. The classification of seizures and the individual components of the semiology based only on the observer-description was somewhat discordant compared with the findings from the videotape (correct classification, 85%). The descriptions of some ictal behaviors such as oroalimentary automatism, tonic/dystonic limb posturing, and head versions were relatively accurate, but those of motionless staring and hand automatism were less accurate. The specified directions by the observers were relatively correct. The accuracy of the description was related to the educational level of the observers. Much of the information described by well-educated observers is reliable. However, every physician should keep in mind the limitations of this information and use this information cautiously.

  17. THE PROCEDURE AND HARDWARE OF A PREPARATION MOVEMENT TRAJECTORY DEFINITION AND TIME AND FREQUENCY PARAMETERS OF ITS INTERACTION WITH A SAWING DISK AT THE MESSAGE TO IT OF TWO-DIMENSIONAL PERIODIC CIRCULATING MOVEMENT

    Directory of Open Access Journals (Sweden)

    M. G. Kiselev

    2012-01-01

    Full Text Available The procedure for parameters definition of sawing preparations two-dimensional circulating movement, including the form of a trajectory and a direction of circulating movement is submitted. The procedure and hardware description for time measurement of the cutting tool and processable preparation contact interaction in conditions of its periodic circulating movement is given.

  18. Team Leader System description

    Energy Technology Data Exchange (ETDEWEB)

    Evans, B.J.; Lundeen, T.F.; Moon, B.D.

    1996-10-01

    Purpose of the project is to design, develop, and demonstrate an advanced, prototype computer system to support on-site inspections. The system is a highly portable field computer with on-line access to facilities information, real-time communications, positioning information, and an electronic notebook for data capture. The Team Leader System provides an inspection team with a suite of advanced communication, data gathering, and data analysis tools and can be implemented on many PC-based hardware platforms. The suitcase unit is a transportable system for on-site support in a vehicle or at a stationary location at an inspection site; the personal unit is a wearable computer for in-facility or on-foot inspections.

  19. Career Path Descriptions

    CERN Document Server

    Charkiewicz, A

    2000-01-01

    Before the Career Path system, jobs were classified according to grades with general statutory definitions, guided by the "Job Catalogue" which defined 6 evaluation criteria with example illustrations in the form of "typical" job descriptions. Career Paths were given concise statutory definitions necessitating a method of description and evaluation adapted to their new wider-band salary concept. Evaluations were derived from the same 6 criteria but the typical descriptions became unusable. In 1999, a sub-group of the Standing Concertation Committee proposed a new guide for describing Career Paths, adapted to their wider career concept by expanding the 6 evaluation criteria into 9. For each criterion several levels were established tracing the expected evolution of job level profiles and personal competencies over their longer salary ranges. While providing more transparency to supervisors and staff, the Guide's official use would be by services responsible for vacancy notices, Career Path evaluations and rela...

  20. Olkiluoto site description 2011

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2012-12-15

    This fourth version of the Olkiluoto Site Report, produced by the OMTF (Olkiluoto Modelling Task Force), updates the Olkiluoto Site Report 2008 with the data and knowledge obtained up to December 2010. A descriptive model of the site (the Site Descriptive Model, SDM), i.e. a model describing the geological and hydrogeological structure of the site, properties of the bedrock and the groundwater and its flow, and the associated interacting processes and mechanisms. The SDM is divided into six parts: surface system, geology, rock mechanics, hydrogeology, hydrogeochemistry and transport properties.

  1. CRAC2 model description

    Energy Technology Data Exchange (ETDEWEB)

    Ritchie, L.T.; Alpert, D.J.; Burke, R.P.; Johnson, J.D.; Ostmeyer, R.M.; Aldrich, D.C.; Blond, R.M.

    1984-03-01

    The CRAC2 computer code is a revised version of CRAC (Calculation of Reactor Accident Consequences) which was developed for the Reactor Safety Study. This document provides an overview of the CRAC2 code and a description of each of the models used. Significant improvements incorporated into CRAC2 include an improved weather sequence sampling technique, a new evacuation model, and new output capabilities. In addition, refinements have been made to the atmospheric transport and deposition model. Details of the modeling differences between CRAC2 and CRAC are emphasized in the model descriptions.

  2. Interfacing Hardware Accelerators to a Time-Division Multiplexing Network-on-Chip

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Sørensen, Rasmus Bo; Schoeberl, Martin

    2015-01-01

    This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors...... in the platform. Our design takes a different approach and connects the hardware accelerators to the network-on-chip in the same way as processor cores. Each processor that uses a hardware accelerator is assigned a virtual channel for sending instructions to the hardware accelerator and a virtual channel...

  3. Hybrid Modeling for Scenario-Based Evaluation of Failure Effects in Advanced Hardware-Software Designs

    Science.gov (United States)

    Malin, Jane T.; Fleming, Land; Throop, David

    2001-01-01

    This paper describes an incremental scenario-based simulation approach to evaluation of intelligent software for control and management of hardware systems. A hybrid continuous/discrete event simulation of the hardware dynamically interacts with the intelligent software in operations scenarios. Embedded anomalous conditions and failures in simulated hardware can lead to emergent software behavior and identification of missing or faulty software or hardware requirements. An approach is described for extending simulation-based automated incremental failure modes and effects analysis, to support concurrent evaluation of intelligent software and the hardware controlled by the software

  4. Effect of spine hardware on small spinal stereotactic radiosurgery dosimetry

    Science.gov (United States)

    Wang, Xin; Yang, James N.; Li, Xiaoqiang; Tailor, Ramesh; Vassilliev, Oleg; Brown, Paul; Rhines, Laurence; Chang, Eric

    2013-10-01

    Monte Carlo (MC) modeling of a 6 MV photon beam was used to study the dose perturbation from a titanium rod 5 mm in diameter in various small fields range from 2 × 2 to 5 × 5 cm2. The results showed that the rod increased the dose to water by ˜6% at the water-rod interface because of electron backscattering and decreased the dose by ˜7% in the shadow of the rod because of photon attenuation. The Pinnacle3 treatment planning system calculations matched the MC results at the depths more than 1 cm past the rod when the correct titanium density of 4.5 g cm-3 was used, but significantly underestimated the backscattering dose at the water-rod interface. A CT-density table with a top density of 1.82 g cm-3 (cortical bone) is a practical way to reduce the dosimetric error from the artifacts by preventing high density assignment to them, but can underestimates the attenuation by the titanium rod by 6%. However, when multi-beam with intensity modulation is used in actual patient spinal stereotactic radiosurgery treatment, the dosimetric effect of assigning 4.5 instead of 1.82 g cm-3 to titanium implants is complicated. It ranged from minimal effect to 2% dose difference affecting 15% target volume in the study. When hardware is in the beam path, density override to the titanium hardware is recommended.

  5. Advances in flexible optrode hardware for use in cybernetic insects

    Science.gov (United States)

    Register, Joseph; Callahan, Dennis M.; Segura, Carlos; LeBlanc, John; Lissandrello, Charles; Kumar, Parshant; Salthouse, Christopher; Wheeler, Jesse

    2017-08-01

    Optogenetic manipulation is widely used to selectively excite and silence neurons in laboratory experiments. Recent efforts to miniaturize the components of optogenetic systems have enabled experiments on freely moving animals, but further miniaturization is required for freely flying insects. In particular, miniaturization of high channel-count optical waveguides are needed for high-resolution interfaces. Thin flexible waveguide arrays are needed to bend light around tight turns to access small anatomical targets. We present the design of lightweight miniaturized optogentic hardware and supporting electronics for the untethered steering of dragonfly flight. The system is designed to enable autonomous flight and includes processing, guidance sensors, solar power, and light stimulators. The system will weigh less than 200mg and be worn by the dragonfly as a backpack. The flexible implant has been designed to provide stimuli around nerves through micron scale apertures of adjacent neural tissue without the use of heavy hardware. We address the challenges of lightweight optogenetics and the development of high contrast polymer waveguides for this purpose.

  6. Software and Hardware Developments For a Mobile Manipulator Control

    Directory of Open Access Journals (Sweden)

    F. Abdessemed

    2008-12-01

    Full Text Available In this paper, we present the hardware and software architectures of an experimental real time control system of a mobile manipulator that performs tasks of manipulating objects in an environment of a large space. The mechanical architecture is a manipulator arm mounted on a mobile platform. In this work we show how one can implement an imbedded system, which includes the hardware and the software. The system makes use of a PC as the host and constitutes the high level layer. It is configured in such a way that it performs all the input-output interface operations; and is composed of different modules that constitute the software making up the required operations to be executed in a scheduling manner in order to meet the requirements of the real time control. In this paper, we also focus on the development of the generalized trajectory generation for the case of tasks where only one subsystem is considered to move and when the whole system is in permanent movement to achieve a particular task either in a free environment, or in presence of obstacles.

  7. A fast hardware tracker for the ATLAS trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Asbah, Nedaa [DESY, Hamburg (Germany); Collaboration: ATLAS-Collaboration

    2015-07-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to less than 1 kHz for a designed LHC luminosity of 10{sup 34} cm{sup -2} s{sup -1}. The LHC has successfully ran from 2010 to early 2013, routinely exceeding the design luminosity. The LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer upgrade project is a hardware processor that will provide full scan tracking after every level-1 accept down to a p{sub T} threshold of 1 GeV. The Fast TracKer will exploit hardware with massive parallelism combining Associative Memory ASICs, FPGAs and high speed communication links. The Fast TracKer will provide the High Level Trigger system with extensive access to tracking information.

  8. The FTK: A Hardware Track Finder for the ATLAS Trigger

    CERN Document Server

    Alison, J; Anderson, J; Andreani, A; Andreazza, A; Annovi, A; Antonelli, M; Atkinson, M; Auerbach, B; Baines, J; Barberio, E; Beccherle, R; Beretta, M; Biesuz, N V; Blair, R; Blazey, G; Bogdan, M; Boveia, A; Britzger, D; Bryant, P; Burghgrave, B; Calderini, G; Cavaliere, V; Cavasinni, V; Chakraborty, D; Chang, P; Cheng, Y; Cipriani, R; Citraro, S; Citterio, M; Crescioli, F; Dell'Orso, M; Donati, S; Dondero, P; Drake, G; Gadomski, S; Gatta, M; Gentsos, C; Giannetti, P; Giulini, M; Gkaitatzis, S; Howarth, J W; Iizawa, T; Kapliy, A; Kasten, M; Kim, Y K; Kimura, N; Klimkovich, T; Kordas, K; Korikawa, T; Krizka, K; Kubota, T; Lanza, A; Lasagni, F; Liberali, V; Li, H L; Love, J; Luciano, P; Luongo, C; Magalotti, D; Melachrinos, C; Meroni, C; Mitani, T; Negri, A; Neroutsos, P; Neubauer, M; Nikolaidis, S; Okumura, Y; Pandini, C; Penning, B; Petridou, C; Piendibene, M; Proudfoot, J; Rados, P; Roda, C; Rossi, E; Sakurai, Y; Sampsonidis, D; Sampsonidou, D; Schmitt, S; Schoening, A; Shochet, M; Shojaii, S; Soltveit, H; Sotiropoulou, C L; Stabile, A; Tang, F; Testa, M; Tompkins, L; Vercesi, V; Villa, M; Volpi, G; Webster, J; Wu, X; Yorita, K; Yurkewicz, A; Zeng, J C; Zhang, J

    2014-01-01

    The ATLAS experiment trigger system is designed to reduce the event rate, at the LHC design luminosity of 1034 cm-2 s-1, from the nominal bunch crossing rate of 40 MHz to less than 1 kHz for permanent storage. During Run 1, the LHC has performed exceptionally well, routinely exceeding the design luminosity. From 2015 the LHC is due to operate with higher still luminosities. This will place a significant load on the High Level Trigger system, both due to the need for more sophisticated algorithms to reject background, and from the larger data volumes that will need to be processed. The Fast TracKer is a hardware upgrade for Run 2, consisting of a custom electronics system that will operate at the full rate for Level-1 accepted events of 100 kHz and provide high quality tracks at the beginning of processing in the High Level Trigger. This will perform track reconstruction using hardware with massive parallelism using associative memories and FPGAs. The availability of the full tracking information will enable r...

  9. SPANNER: A Self-Repairing Spiking Neural Network Hardware Architecture.

    Science.gov (United States)

    Liu, Junxiu; Harkin, Jim; Maguire, Liam P; McDaid, Liam J; Wade, John J

    2017-03-06

    Recent research has shown that a glial cell of astrocyte underpins a self-repair mechanism in the human brain, where spiking neurons provide direct and indirect feedbacks to presynaptic terminals. These feedbacks modulate the synaptic transmission probability of release (PR). When synaptic faults occur, the neuron becomes silent or near silent due to the low PR of synapses; whereby the PRs of remaining healthy synapses are then increased by the indirect feedback from the astrocyte cell. In this paper, a novel hardware architecture of Self-rePAiring spiking Neural NEtwoRk (SPANNER) is proposed, which mimics this self-repairing capability in the human brain. This paper demonstrates that the hardware can self-detect and self-repair synaptic faults without the conventional components for the fault detection and fault repairing. Experimental results show that SPANNER can maintain the system performance with fault densities of up to 40%, and more importantly SPANNER has only a 20% performance degradation when the self-repairing architecture is significantly damaged at a fault density of 80%.

  10. Health Maintenance System (HMS) Hardware Research, Design, and Collaboration

    Science.gov (United States)

    Gonzalez, Stefanie M.

    2010-01-01

    The Space Life Sciences division (SLSD) concentrates on optimizing a crew member's health. Developments are translated into innovative engineering solutions, research growth, and community awareness. This internship incorporates all those areas by targeting various projects. The main project focuses on integrating clinical and biomedical engineering principles to design, develop, and test new medical kits scheduled for launch in the Spring of 2011. Additionally, items will be tagged with Radio Frequency Interference Devices (RFID) to keep track of the inventory. The tags will then be tested to optimize Radio Frequency feed and feed placement. Research growth will occur with ground based experiments designed to measure calcium encrusted deposits in the International Space Station (ISS). The tests will assess the urine calcium levels with Portable Clinical Blood Analyzer (PCBA) technology. If effective then a model for urine calcium will be developed and expanded to microgravity environments. To support collaboration amongst the subdivisions of SLSD the architecture of the Crew Healthcare Systems (CHeCS) SharePoint site has been redesigned for maximum efficiency. Community collaboration has also been established with the University of Southern California, Dept. of Aeronautical Engineering and the Food and Drug Administration (FDA). Hardware disbursements will transpire within these communities to support planetary surface exploration and to serve as an educational tool demonstrating how ground based medicine influenced the technological development of space hardware.

  11. TileCal ROD Hardware and Software Requirements

    CERN Document Server

    Castelo, J; Cuenca, C; Ferrer, A; Fullana, E; Higón, E; Iglesias, C; Munar, A; Poveda, J; Ruiz-Martínez, A; Salvachúa, B; Solans, C; Valls, J A

    2005-01-01

    In this paper we present the specific hardware and firmware requirements and modifications to operate the Liquid Argon Calorimeter (LiArg) ROD motherboard in the Hadronic Tile Calorimeter (TileCal) environment. Although the use of the board is similar for both calorimeters there are still some differences in the operation of the front-end associated to both detectors which make the use of the same board incompatible. We review the evolution of the design of the ROD from the early prototype stages (ROD based on commercial and Demonstrator boards) to the production phases (ROD final board based on the LiArg design), with emphasis on the different operation modes for the TileCal detector. We start with a short review of the TileCal ROD system functionality and then we detail the different ROD hardware requirements for options, the baseline (ROD Demo board) and the final (ROD final high density board). We also summarize the performance parameters of the ROD motherboard based on the final high density option and s...

  12. First Light with the NRAO Transient Event Capture Hardware

    Science.gov (United States)

    Langston, Glen; Rumberg, B.; Brandt, P.

    2007-12-01

    The design, implementation and testing of the first NRAO Event Capture data acquisition system is presented. The NRAO in Green Bank is developing a set of new data acquisition systems based on the U.C. Berkeley CASPER IBOB/ADC/BEE2 hardware. We describe the hardware configuration and initial experiences with the development system. We present first astronomical tests of the Event Capture system, using the 43m telescope (140ft). These observations were carried out at 900 MHz. The observations were made on 2007 July 8 and 9 towards the Crab pulsar, the galactic center, the Moon and two test observations while the 43m was pointed at Zenith (straight up). The Event Capture is one of several on-going FPGA based data acquisition projects being implemented for the Robert C. Byrd Green Bank Telescope (GBT) and for the 43m telescopes. The NRAO Configurable Instrument Collaboration for Agile Data Acquisition (CICADA) program is described at: http://wikio.nrao.edu/bin/view/CICADA

  13. Hardware-Assisted System for Program Execution Security of SOC

    Directory of Open Access Journals (Sweden)

    Wang Xiang

    2016-01-01

    Full Text Available With the rapid development of embedded systems, the systems’ security has become more and more important. Most embedded systems are at the risk of series of software attacks, such as buffer overflow attack, Trojan virus. In addition, with the rapid growth in the number of embedded systems and wide application, followed embedded hardware attacks are also increasing. This paper presents a new hardware assisted security mechanism to protect the program’s code and data, monitoring its normal execution. The mechanism mainly monitors three types of information: the start/end address of the program of basic blocks; the lightweight hash value in basic blocks and address of the next basic block. These parameters are extracted through additional tools running on PC. The information will be stored in the security module. During normal program execution, the security module is designed to compare the real-time state of program with the information in the security module. If abnormal, it will trigger the appropriate security response, suspend the program and jump to the specified location. The module has been tested and validated on the SOPC with OR1200 processor. The experimental analysis shows that the proposed mechanism can defence a wide range of common software and physical attacks with low performance penalties and minimal overheads.

  14. Space hardware compatibility tests with hydrogen peroxide gas plasma sterilization

    Science.gov (United States)

    Faye, Delphine; Aguila, Alexandre; Debus, Andre; Remaury, Stephanie; Nabarra, Pascale; Darbord, Jacques C.; Soufflet, Caroline; Destrez, Philippe; Coll, Patrice; Coscia, David

    The exploration of the Solar System shall comply with planetary protection requirements handled presently by the Committee of Space Research (COSPAR). The goal of planetary protection is to protect celestial bodies from terrestrial contamination and also to protect the Earth environment from an eventual contamination carried by return samples or by space systems. For project teams, avoiding the biological contamination of other Solar System bodies such as Mars imposes to perform unusual tasks at technical and operational constraints point of view. The main are the reduction of bioburden on space hardware, the sterile integration of landers, the control of the biological cleanliness and the limitation of crash probability. In order to reduce the bioburden on spacecraft, the use of qualified sterilization processes may be envisaged. Since 1992 now, with the Mars96 mission, one of the most often used is the Sterrad(R) process working with hydrogen peroxide gas plasma. In the view of future Mars exploration programs, after tests performed in the frame of previous missions, a new test campaign has been performed on thermal coatings and miscellaneous materials coming from an experiment in order to assess the compatibility of space hardware and material with this sterilization process.

  15. Optimizing memory-bound SYMV kernel on GPU hardware accelerators

    KAUST Repository

    Abdelfattah, Ahmad

    2013-01-01

    Hardware accelerators are becoming ubiquitous high performance scientific computing. They are capable of delivering an unprecedented level of concurrent execution contexts. High-level programming language extensions (e.g., CUDA), profiling tools (e.g., PAPI-CUDA, CUDA Profiler) are paramount to improve productivity, while effectively exploiting the underlying hardware. We present an optimized numerical kernel for computing the symmetric matrix-vector product on nVidia Fermi GPUs. Due to its inherent memory-bound nature, this kernel is very critical in the tridiagonalization of a symmetric dense matrix, which is a preprocessing step to calculate the eigenpairs. Using a novel design to address the irregular memory accesses by hiding latency and increasing bandwidth, our preliminary asymptotic results show 3.5x and 2.5x fold speedups over the similar CUBLAS 4.0 kernel, and 7-8% and 30% fold improvement over the Matrix Algebra on GPU and Multicore Architectures (MAGMA) library in single and double precision arithmetics, respectively. © 2013 Springer-Verlag.

  16. Integrating reconfigurable hardware-based grid for high performance computing.

    Science.gov (United States)

    Dondo Gazzano, Julio; Sanchez Molina, Francisco; Rincon, Fernando; López, Juan Carlos

    2015-01-01

    FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

  17. A Hardware Track Trigger (FTK) for the ATLAS Trigger

    CERN Document Server

    Zhang, J; The ATLAS collaboration

    2014-01-01

    The design and studies of the performance for the ATLAS hardware Fast TracKer (FTK) are presented. The existing trigger system of the ATLAS experiment is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to < 1 KHz for permanent storage at the LHC design luminosity of 10^34 cm^-2 s^-1. The LHC has performed exceptionally well and routinely exceeds the design luminosity and from 2015 is due to operate with higher still luminosities. This will place a significant load on the High Level trigger (HLT) system, both due to the need for more sophisticated algorithms to reject background, and from the larger data volumes that will need to be processed. The Fast TracKer is a custom electronics system that will operate at the full Level-1 accepted rate of 100 KHz and provide high quality tracks at the beginning of processing in the HLT. This will be performing by track reconstruction using hardware with massive parallelism using associative memories (AM) and FPGAs. The availability of the full...

  18. Spinal fusion-hardware construct: Basic concepts and imaging review

    Science.gov (United States)

    Nouh, Mohamed Ragab

    2012-01-01

    The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging. PMID:22761979

  19. Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

    Science.gov (United States)

    Dondo Gazzano, Julio; Sanchez Molina, Francisco; Rincon, Fernando; López, Juan Carlos

    2015-01-01

    FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process. PMID:25874241

  20. The Evolution of Exercise Hardware on ISS: Past, Present, and Future

    Science.gov (United States)

    Buxton, R. E.; Kalogera, K. L.; Hanson, A. M.

    2017-01-01

    During 16 years in low-Earth orbit, the suite of exercise hardware aboard the International Space Station (ISS) has matured significantly. Today, the countermeasure system supports an array of physical-training protocols and serves as an extensive research platform. Future hardware designs are required to have smaller operational envelopes and must also mitigate known physiologic issues observed in long-duration spaceflight. Taking lessons learned from the long history of space exercise will be important to successful development and implementation of future, compact exercise hardware. The evolution of exercise hardware as deployed on the ISS has implications for future exercise hardware and operations. Key lessons learned from the early days of ISS have helped to: 1. Enhance hardware performance (increased speed and loads). 2. Mature software interfaces. 3. Compare inflight exercise workloads to pre-, in-, and post-flight musculoskeletal and aerobic conditions. 4. Improve exercise comfort. 5. Develop complimentary hardware for research and operations. Current ISS exercise hardware includes both custom and commercial-off-the-shelf (COTS) hardware. Benefits and challenges to this approach have prepared engineering teams to take a hybrid approach when designing and implementing future exercise hardware. Significant effort has gone into consideration of hardware instrumentation and wearable devices that provide important data to monitor crew health and performance.

  1. Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework

    Science.gov (United States)

    Butt, Shahzad Ahmad; Mancini, Stéphane; Rousseau, Frédéric; Lavagno, Luciano

    2014-09-01

    The pseudo-log image transform belongs to a class of image processing kernels that generate memory references which are nonlinear functions of loop indices. Due to the nonlinearity of the memory references, the usual design methodologies do not allow efficient hardware implementation for nonlinear kernels. For optimized hardware implementation, these kernels require the creation of a customized memory hierarchy and efficient data/memory management strategy. We present the design and real-time hardware implementation of a pseudo-log image transform IP (hardware image processing engine) using a memory management framework. The framework generates a controller which efficiently manages input data movement in the form of tiles between off-chip main memory, on-chip memory, and the core processing unit. The framework can jointly optimize the memory hierarchy and the tile computation schedule to reduce on-chip memory requirements, to maximize throughput, and to increase data reuse for reducing off-chip memory bandwidth requirements. The algorithmic C++ description of the pseudo-log kernel is profiled in the framework to generate an enhanced description with a customized memory hierarchy. The enhanced description of the kernel is then used for high-level synthesis (HLS) to perform architectural design space exploration in order to find an optimal implementation under given performance constraints. The optimized register transfer level implementation of the IP generated after HLS is used for performance estimation. The performance estimation is done in a simulation framework to characterize the IP with different external off-chip memory latencies and a variety of data transfer policies. Experimental results show that the designed IP can be used for real-time implementation and that the generated memory hierarchy is capable of feeding the IP with a sufficiently high bandwidth even in the presence of long external memory latencies.

  2. Plot Description (PD)

    Science.gov (United States)

    Robert E. Keane

    2006-01-01

    The Plot Description (PD) form is used to describe general characteristics of the FIREMON macroplot to provide ecological context for data analyses. The PD data characterize the topographical setting, geographic reference point, general plant composition and cover, ground cover, fuels, and soils information. This method provides the general ecological data that can be...

  3. A descriptive study

    African Journals Online (AJOL)

    Complementary medicine use among Moroccan patients with cancer: A descriptive study. ... Complementary medicine must benefit, as well as conventional medicine, from scientific studies to evaluate potential benefits, toxicity and interactions with the conventional treatment to enable the oncologist better inform his patients ...

  4. Generalizing: The descriptive struggle

    Directory of Open Access Journals (Sweden)

    Barney G. Glaser, Ph.D.; Hon Ph.D.

    2006-11-01

    Full Text Available The literature is not kind to the use of descriptive generalizations. Authors struggle and struggle to find and rationalize a way to use them and then fail in spite of trying a myriad of work-arounds. And then we have Lincoln and Guba’s famous statement: “The only generalization is: there is no generalization” in referring to qualitative research. (op cit, p. 110 They are referring to routine QDA yielding extensive descriptions, but which tacitly include conceptual generalizations without any real thought of knowledge about them. In this chapter I wish to explore this struggle for the purpose of explaining that the various contra arguments to using descriptive generalizations DO NOT apply to the ease of using conceptual generalizations yielded in SGT and especially FGT. I will not argue for the use of descriptive generalization. I agree with Lincoln and Guba with respect to QDA, “the only generalization is: there is no generalization.” It is up to the QDA methodologists, of whom there are many; to continue the struggle and I wish them well.

  5. Emplacement Drift System Description Document

    Energy Technology Data Exchange (ETDEWEB)

    Eric Loros

    2001-07-31

    The Emplacement Drift System is part of the Engineered Barrier System and provides the interface between the various waste package (WP) systems and the Ground Control System. In conjunction with the various WPs, the Emplacement Drift System limits the release and transport of radionuclides from the WP to the Natural Barrier following waste emplacement. Collectively, the Emplacement Drift System consists of the structural support hardware (emplacement drift invert and WP emplacement pallet) and any performance-enhancing barriers (drip shields and invert ballast) installed or placed in the emplacement drifts. The Emplacement Drift System is entirely located within the emplacement drifts in the subsurface portion of the Monitored Geologic Repository (MGR); specifically, it is physically bounded by the Subsurface Facility System, the Ground Support System, and the Natural Barrier. The Emplacement Drift System supports the key MGR functions of limiting radionuclide release to the Natural Barrier, minimizing the likelihood of a criticality external to the WPs, limiting natural and induced environmental effects, and providing WP support. The Emplacement Drift System limits radionuclide release to the Natural Barrier by controlling the movement of radionuclides within the emplacement drift and to the Natural Barrier, and by limiting water contact with the WPs. The Emplacement Drift System provides physical support and barriers for emplaced WPs that reduce water contact. The Emplacement Drift WP spacing supports the thermal loading performance by complimenting drift layout and orientation as described in the system description document for the Subsurface Facility System. The Emplacement Drift System supports the WP and also provides an environment that aids in enhancing WP confinement performance. As part of the Engineered Barrier System, the Emplacement Drift System interfaces with the WP systems. The Emplacement Drift System also interfaces with the Natural Barrier

  6. Ultra-low noise miniaturized neural amplifier with hardware averaging.

    Science.gov (United States)

    Dweiri, Yazan M; Eggers, Thomas; McCallum, Grant; Durand, Dominique M

    2015-08-01

    Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (noise of less than 1 μVrms for a useful signal-to-noise ratio (SNR). Flat interface nerve electrode (FINE) contacts alone generate thermal noise of at least 0.5 μVrms therefore the amplifier should add as little noise as possible. Since mainstream neural amplifiers have a baseline noise of 2 μVrms or higher, novel designs are required. Here we apply the concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating noise when connected to a FINE placed on the sciatic nerve of an awake animal. An algorithm was introduced to find the value of N that can minimize both the power consumption and the noise in order to design a miniaturized ultralow-noise neural amplifier. These results demonstrate the efficacy of hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the presence of high source impedances that are associated with the miniaturized contacts and the high channel count in electrode arrays. This

  7. Ultra-low noise miniaturized neural amplifier with hardware averaging

    Science.gov (United States)

    Dweiri, Yazan M.; Eggers, Thomas; McCallum, Grant; Durand, Dominique M.

    2015-08-01

    Objective. Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (noise of less than 1 μVrms for a useful signal-to-noise ratio (SNR). Flat interface nerve electrode (FINE) contacts alone generate thermal noise of at least 0.5 μVrms therefore the amplifier should add as little noise as possible. Since mainstream neural amplifiers have a baseline noise of 2 μVrms or higher, novel designs are required. Approach. Here we apply the concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. Main results. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating noise when connected to a FINE placed on the sciatic nerve of an awake animal. An algorithm was introduced to find the value of N that can minimize both the power consumption and the noise in order to design a miniaturized ultralow-noise neural amplifier. Significance. These results demonstrate the efficacy of hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the presence of high source impedances that are associated with the miniaturized contacts and

  8. Accelerating epistasis analysis in human genetics with consumer graphics hardware

    Directory of Open Access Journals (Sweden)

    Cancare Fabio

    2009-07-01

    Full Text Available Abstract Background Human geneticists are now capable of measuring more than one million DNA sequence variations from across the human genome. The new challenge is to develop computationally feasible methods capable of analyzing these data for associations with common human disease, particularly in the context of epistasis. Epistasis describes the situation where multiple genes interact in a complex non-linear manner to determine an individual's disease risk and is thought to be ubiquitous for common diseases. Multifactor Dimensionality Reduction (MDR is an algorithm capable of detecting epistasis. An exhaustive analysis with MDR is often computationally expensive, particularly for high order interactions. This challenge has previously been met with parallel computation and expensive hardware. The option we examine here exploits commodity hardware designed for computer graphics. In modern computers Graphics Processing Units (GPUs have more memory bandwidth and computational capability than Central Processing Units (CPUs and are well suited to this problem. Advances in the video game industry have led to an economy of scale creating a situation where these powerful components are readily available at very low cost. Here we implement and evaluate the performance of the MDR algorithm on GPUs. Of primary interest are the time required for an epistasis analysis and the price to performance ratio of available solutions. Findings We found that using MDR on GPUs consistently increased performance per machine over both a feature rich Java software package and a C++ cluster implementation. The performance of a GPU workstation running a GPU implementation reduces computation time by a factor of 160 compared to an 8-core workstation running the Java implementation on CPUs. This GPU workstation performs similarly to 150 cores running an optimized C++ implementation on a Beowulf cluster. Furthermore this GPU system provides extremely cost effective

  9. Tuple spaces in hardware for accelerated implicit routing

    Energy Technology Data Exchange (ETDEWEB)

    Baker, Zachary Kent [Los Alamos National Laboratory; Tripp, Justin [Los Alamos National Laboratory

    2010-12-01

    Organizing and optimizing data objects on networks with support for data migration and failing nodes is a complicated problem to handle as systems grow. The goal of this work is to demonstrate that high levels of speedup can be achieved by moving responsibility for finding, fetching, and staging data into an FPGA-based network card. We present a system for implicit routing of data via FPGA-based network cards. In this system, data structures are requested by name, and the network of FPGAs finds the data within the network and relays the structure to the requester. This is acheived through successive examination of hardware hash tables implemented in the FPGA. By avoiding software stacks between nodes, the data is quickly fetched entirely through FPGA-FPGA interaction. The performance of this system is orders of magnitude faster than software implementations due to the improved speed of the hash tables and lowered latency between the network nodes.

  10. Hardware-in-the-loop grid simulator system and method

    Science.gov (United States)

    Fox, John Curtiss; Collins, Edward Randolph; Rigas, Nikolaos

    2017-05-16

    A hardware-in-the-loop (HIL) electrical grid simulation system and method that combines a reactive divider with a variable frequency converter to better mimic and control expected and unexpected parameters in an electrical grid. The invention provides grid simulation in a manner to allow improved testing of variable power generators, such as wind turbines, and their operation once interconnected with an electrical grid in multiple countries. The system further comprises an improved variable fault reactance (reactive divider) capable of providing a variable fault reactance power output to control a voltage profile, therein creating an arbitrary recovery voltage. The system further comprises an improved isolation transformer designed to isolate zero-sequence current from either a primary or secondary winding in a transformer or pass the zero-sequence current from a primary to a secondary winding.

  11. Impact of Improper Gaussian Signaling on Hardware Impaired Systems

    KAUST Repository

    Javed, Sidrah

    2016-12-18

    In this paper, we accurately model the hardware impairments (HWI) as improper Gaussian signaling (IGS) which can characterize the asymmetric characteristics of different HWI sources. The proposed model encourages us to adopt IGS scheme for transmitted signal that represents a general study compared with the conventional scheme, proper Gaussian signaling (PGS). First, we express the achievable rate of HWI systems when both PGS and IGS schemes are used when the aggregate effect of HWI is modeled as IGS. Moreover, we tune the IGS statistical characteristics to maximize the achievable rate. Then, we analyze the outage probability for both schemes and derive closed form expressions. Finally, we validate the analytic expressions through numerical and simulation results. In addition, we quantify through the numerical results the performance degradation in the absence of ideal transceivers and the gain reaped from adopting IGS scheme compared with PGS scheme.

  12. Hardware and Initial Beam Commissioning of the LHC RF Systems

    CERN Document Server

    Linnecar, T; Arnaudon, L; Baudrenghien, P; Bohl, T; Brunner, O; Butterworth, A; Ciapala, Edmond; Dubouchet, F; Ferreira-Bento, J; Glenat, D; Hagmann, G; Höfle, Wolfgang; Julie, C; Killing, F; Kotzian, G; Landre, D; Louwerse, R; Maesen, P; Martinez-Yanez, P; Molendijk, J; Montesinos, E; Nicou, C; Noirjean, J; Papotti, G; Pashnin, A; Pechaud, G; Pradier, J; Rossi, V; Sanchez-Quesada, J; Schokker, M; Shaposhnikova, E; Sorokoletev, R; Stellfeld, D; Tückmantel, Joachim; Valuch, D; Wehrle, U; Weierud, F

    2008-01-01

    Hardware commissioning of the LHC RF Systems, the ACS Superconducting RF systems, ADT Transverse Dampers and APWL Wideband Longitudinal Monitors, started in late 2007 and was completed in time for the first LHC beams in 2008. The RF inter-machine synchroni-sation systems were in place and operational for the LHC synchronization tests in August 2008. The very first beams through IP4 were observed on the RF monitors and beam 2 was captured on 11th September. Measurements with beam on the damper systems were also pos-sible, preparing the way for closing the damper loop with beam. Major milestones during commissioning the ACS and ADT systems and results obtained during first capture tests are presented. Preparatory work for acceleration and multi-bunch operation is described as are the beam tests foreseen for 2009.

  13. Programming languages and compiler design for realistic quantum hardware

    Science.gov (United States)

    Chong, Frederic T.; Franklin, Diana; Martonosi, Margaret

    2017-09-01

    Quantum computing sits at an important inflection point. For years, high-level algorithms for quantum computers have shown considerable promise, and recent advances in quantum device fabrication offer hope of utility. A gap still exists, however, between the hardware size and reliability requirements of quantum computing algorithms and the physical machines foreseen within the next ten years. To bridge this gap, quantum computers require appropriate software to translate and optimize applications (toolflows) and abstraction layers. Given the stringent resource constraints in quantum computing, information passed between layers of software and implementations will differ markedly from in classical computing. Quantum toolflows must expose more physical details between layers, so the challenge is to find abstractions that expose key details while hiding enough complexity.

  14. Plasma arc welding repair of space flight hardware

    Science.gov (United States)

    Hoffman, David S.

    1993-01-01

    Repair and refurbishment of flight and test hardware can extend the useful life of very expensive components. A technique to weld repair the main combustion chamber of space shuttle main engines has been developed. The technique uses the plasma arc welding process and active cooling to seal cracks and pinholes in the hot-gas wall of the main combustion chamber liner. The liner hot-gas wall is made of NARloyZ, a copper alloy previously thought to be unweldable using conventional arc welding processes. The process must provide extensive heat input to melt the high conductivity NARloyZ while protecting the delicate structure of the surrounding material. The higher energy density of the plasma arc process provides the necessary heat input while active water cooling protects the surrounding structure. The welding process is precisely controlled using a computerized robotic welding system.

  15. 4273π: bioinformatics education on low cost ARM hardware.

    Science.gov (United States)

    Barker, Daniel; Ferrier, David Ek; Holland, Peter Wh; Mitchell, John Bo; Plaisier, Heleen; Ritchie, Michael G; Smart, Steven D

    2013-08-12

    Teaching bioinformatics at universities is complicated by typical computer classroom settings. As well as running software locally and online, students should gain experience of systems administration. For a future career in biology or bioinformatics, the installation of software is a useful skill. We propose that this may be taught by running the course on GNU/Linux running on inexpensive Raspberry Pi computer hardware, for which students may be granted full administrator access. We release 4273π, an operating system image for Raspberry Pi based on Raspbian Linux. This includes minor customisations for classroom use and includes our Open Access bioinformatics course, 4273π Bioinformatics for Biologists. This is based on the final-year undergraduate module BL4273, run on Raspberry Pi computers at the University of St Andrews, Semester 1, academic year 2012-2013. 4273π is a means to teach bioinformatics, including systems administration tasks, to undergraduates at low cost.

  16. Simple Approach For Induction Motor Control Using Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    József VÁSÁRHELYI

    2002-12-01

    Full Text Available The paper deals with rotor-field-oriented vector control structures for the induction motor drives fed by the so-called tandem frequency converter. It is composed of two different types of DC-link converters connected in parallel arrangement. The larger-power one has current-source character and is operating synchronized in time and in amplitude with the stator currents. The other one has voltage-source character and it is the actuator of the motor control system. The drive is able to run also with partial-failed tandem converter, if the control strategy corresponds to the actual operating mode. A reconfigurable hardware implemented in configurable logic cells ensures the changing of the vector-control structure. The proposed control schemes were tested by simulation based on Matlab-Simulink model.

  17. Variable length data formats. [in hardware-software engineering

    Science.gov (United States)

    Brakefield, J. C.; Quinn, M. J.

    1978-01-01

    The purpose of this paper is to discuss a number of variable length floating point and integer formats and to give the various advantages and disadvantages of their use. Often it is known in advance that a given integer will not exceed a certain magnitude or that a particular floating point number is accurate to only 'n' places of accuracy. Faced with this, it is good engineering to choose variable length floating point and integer formats which require the least amount of hardware or the minimum amount of software or which have some other dominant advantage. The formats discussed have the advantage that length change algorithms are invariant with respect to data types (unsigned, signed, floating point, integers, and complex numbers). The STARAN associative array processor, which uses a completely variable fixed point and floating point formats, is described.

  18. Hardware/Software Expansion of Display Terminal and CPU

    Science.gov (United States)

    Adams, B. R.

    1986-01-01

    IBM PC coupling used to expand capabilities of expensive specialpurpose system. IBM PC was interfaced to Tektronix CP1151 computer through teletype port of Tektronix 4010-1 computer display terminal. Electronic interface built to provide isolation, level shifting, and signal inversion between IBM PC RS-232 port and 4010-1 terminal teletype port. Modifications to 4010-1 terminal made to increase teletype rate from 110 to 9,600 baud. Software for both computers developed to give control of DPO system to IBM PC and provide data/program file exchange between two computers. Coupling demonstrates utilization of low-cost microcomputer hardware and software to expand capabilities of expensive special-purpose computer systems.

  19. Design-to-fabricate: maker hardware requires maker software.

    Science.gov (United States)

    Schmidt, Ryan; Ratto, Matt

    2013-01-01

    As a result of consumer-level 3D printers' increasing availability and affordability, the audience for 3D-design tools has grown considerably. However, current tools are ill-suited for these users. They have steep learning curves and don't take into account that the end goal is a physical object, not a digital model. A new class of "maker"-level design tools is needed to accompany this new commodity hardware. However, recent examples of such tools achieve accessibility primarily by constraining functionality. In contrast, the meshmixer project is building tools that provide accessibility and expressive power by leveraging recent computer graphics research in geometry processing. The project members have had positive experiences with several 3D-design-to-print workshops and are exploring several design-to-fabricate problems. This article is part of a special issue on 3D printing.

  20. Programming languages and compiler design for realistic quantum hardware.

    Science.gov (United States)

    Chong, Frederic T; Franklin, Diana; Martonosi, Margaret

    2017-09-13

    Quantum computing sits at an important inflection point. For years, high-level algorithms for quantum computers have shown considerable promise, and recent advances in quantum device fabrication offer hope of utility. A gap still exists, however, between the hardware size and reliability requirements of quantum computing algorithms and the physical machines foreseen within the next ten years. To bridge this gap, quantum computers require appropriate software to translate and optimize applications (toolflows) and abstraction layers. Given the stringent resource constraints in quantum computing, information passed between layers of software and implementations will differ markedly from in classical computing. Quantum toolflows must expose more physical details between layers, so the challenge is to find abstractions that expose key details while hiding enough complexity.

  1. An Overview of Reconfigurable Hardware in Embedded Systems

    Directory of Open Access Journals (Sweden)

    Wenyin Fu

    2006-09-01

    Full Text Available Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption.

  2. An Overview of Reconfigurable Hardware in Embedded Systems

    Directory of Open Access Journals (Sweden)

    Garcia Philip

    2006-01-01

    Full Text Available Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption.

  3. Hardware authentication using transmission spectra modified optical fiber.

    Energy Technology Data Exchange (ETDEWEB)

    Grubbs, Robert K.; Romero, Juan A.

    2010-09-01

    The ability to authenticate the source and integrity of data is critical to the monitoring and inspection of special nuclear materials, including hardware related to weapons production. Current methods rely on electronic encryption/authentication codes housed in monitoring devices. This always invites the question of implementation and protection of authentication information in an electronic component necessitating EMI shielding, possibly an on board power source to maintain the information in memory. By using atomic layer deposition techniques (ALD) on photonic band gap (PBG) optical fibers we will explore the potential to randomly manipulate the output spectrum and intensity of an input light source. This randomization could produce unique signatures authenticating devices with the potential to authenticate data. An external light source projected through the fiber with a spectrometer at the exit would 'read' the unique signature. No internal power or computational resources would be required.

  4. HARDWARE IMPLEMENTATION OF SECURE AODV FOR WIRELESS SENSOR NETWORKS

    Directory of Open Access Journals (Sweden)

    S. Sharmila

    2010-12-01

    Full Text Available Wireless Sensor Networks are extremely vulnerable to any kind of routing attacks due to several factors such as wireless transmission and resource-constrained nodes. In this respect, securing the packets is of great importance when designing the infrastructure and protocols of sensor networks. This paper describes the hardware architecture of secure routing for wireless sensor networks. The routing path is selected using Ad-hoc on demand distance vector routing protocol (AODV. The data packets are converted into digest using hash functions. The functionality of the proposed method is modeled using Verilog HDL in MODELSIM simulator and the performance is compared with various target devices. The results show that the data packets are secured and defend against the routing attacks with minimum energy consumption.

  5. Experimental evaluation of small-scale erectable truss hardware

    Science.gov (United States)

    Mcgowan, David M.; Lake, Mark S.

    1987-01-01

    To aid in the prediction of the dynamic behavior of the space station, a one-tenth scale dynamic test model is to be constructed of commercially available, small scale truss hardware. Tests have been performed to determine the axial stiffness characteristics and failure loads of the truss joint. A parametric study has shown that the stiffness of the joint increases as the attachment bolt torque value is increased. Furthermore, at torque values equal to or higher than 250 in-lbs, hysteresis in the load-deflection curve is essentially eliminated. Also, the joint stiffness remained relatively constant between specimens. The effective stiffness of a joint subassembly tested is 76 percent that of the strut. Tensile and compressive failure occurred in the region of the bonded plug, with lower failure loads corresponding to compressive loadings.

  6. Molecular Dynamics Simulations of Clathrate Hydrates on Specialised Hardware Platforms

    Directory of Open Access Journals (Sweden)

    Christian R. Trott

    2012-09-01

    Full Text Available Classical equilibrium molecular dynamics (MD simulations have been performed to investigate the computational performance of the Simple Point Charge (SPC and TIP4P water models applied to simulation of methane hydrates, and also of liquid water, on a variety of specialised hardware platforms, in addition to estimation of various equilibrium properties of clathrate hydrates. The FPGA-based accelerator MD-GRAPE 3 was used to accelerate substantially the computation of non-bonded forces, while GPU-based platforms were also used in conjunction with CUDA-enabled versions of the LAMMPS MD software packages to reduce computational time dramatically. The dependence of molecular system size and scaling with number of processors was also investigated. Considering performance relative to power consumption, it is seen that GPU-based computing is quite attractive.

  7. Implementing early vision algorithms in analog hardware: an overview

    Science.gov (United States)

    Koch, Christof

    1991-07-01

    In the last ten years, significant progress has been made in understanding the first steps in visual processing. Thus, a large number of algorithms exist that locate edges, compute disparities, estimate motion fields and find discontinuities in depth, motion, color and intensity. However, the application of these algorithms to real-life vision problems has been less successful, mainly because the associated computational cost prevents real-time machine vision implementations on anything but large-scale expensive digital computers. We here review the use of analog, special-purpose vision hardware, integrating image acquisition with early vision algorithms on a single VLSI chip. Such circuits have been designed and successfully tested for edge detection, surface interpolation, computing optical flow and sensor fusion. Thus, it appears that real-time, small, power-lean and robust analog computers are making a limited comeback in the form of highly dedicated, smart vision chips.

  8. An open-hardware platform for optogenetics and photobiology.

    Science.gov (United States)

    Gerhardt, Karl P; Olson, Evan J; Castillo-Hair, Sebastian M; Hartsough, Lucas A; Landry, Brian P; Ekness, Felix; Yokoo, Rayka; Gomez, Eric J; Ramakrishnan, Prabha; Suh, Junghae; Savage, David F; Tabor, Jeffrey J

    2016-11-02

    In optogenetics, researchers use light and genetically encoded photoreceptors to control biological processes with unmatched precision. However, outside of neuroscience, the impact of optogenetics has been limited by a lack of user-friendly, flexible, accessible hardware. Here, we engineer the Light Plate Apparatus (LPA), a device that can deliver two independent 310 to 1550 nm light signals to each well of a 24-well plate with intensity control over three orders of magnitude and millisecond resolution. Signals are programmed using an intuitive web tool named Iris. All components can be purchased for under $400 and the device can be assembled and calibrated by a non-expert in one day. We use the LPA to precisely control gene expression from blue, green, and red light responsive optogenetic tools in bacteria, yeast, and mammalian cells and simplify the entrainment of cyanobacterial circadian rhythm. The LPA dramatically reduces the entry barrier to optogenetics and photobiology experiments.

  9. Optical calibration hardware for the Sudbury Neutrino Observatory

    CERN Document Server

    Moffat, B A; Duncan, F A; Graham, K; Hallin, A L; Hearns, C A W; Maneira, J; Skensved, P; Grant, D R

    2005-01-01

    The optical properties of the Sudbury Neutrino Observatory (SNO) heavy water Cherenkov neutrino detector are measured in situ using a light diffusing sphere ("laserball"). This diffuser is connected to a pulsed nitrogen/dye laser via specially developed underwater optical fibre umbilical cables. The umbilical cables are designed to have a small bending radius, and can be easily adapted for a variety of calibration sources in SNO. The laserball is remotely manipulated to many positions in the D2O and H2O volumes, where data at six different wavelengths are acquired. These data are analysed to determine the absorption and scattering of light in the heavy water and light water, and the angular dependence of the response of the detector's photomultiplier tubes. This paper gives details of the physical properties, construction, and optical characteristics of the laserball and its associated hardware.

  10. Veggie Hardware Validation Test Preliminary Results and Lessons Learned

    Science.gov (United States)

    Massa, Gioia D.; Dufour, Nicole F.; Smith, T. M.

    2014-01-01

    The Veggie hardware validation test, VEG-01, was conducted on the International Space Station during Expeditions 39 and 40 from May through June of 2014. The Veggie hardware and the VEG-01 experiment payload were launched to station aboard the SpaceX-3 resupply mission in April, 2014. Veggie was installed in an Expedite-the-Processing-of-Experiments-to-Space-Station (ExPRESS) rack in the Columbus module, and the VEG-01 validation test was initiated. Veggie installation was successful, and power was supplied to the unit. The hardware was programmed and the root mat reservoir and plant pillows were installed without issue. As expected, a small amount of growth media was observed in the sealed bags which enclosed the plant pillows when they were destowed. Astronaut Steve Swanson used the wet/dry vacuum to clean up the escaped particles. Water insertion or priming the first plant pillow was unsuccessful as an issue prevented water movement through the quick disconnect. All subsequent pillows were successfully primed, and the initial pillow was replaced with a backup pillow and successfully primed. Six pillows were primed, but only five pillows had plants which germinated. After about a week and a half it was observed that plants were not growing well and that pillow wicks were dry. This indicated that the reservoir was not supplying sufficient water to the pillows via wicking, and so the team reverted to an operational fix which added water directly to the plant pillows. Direct watering of the pillows led to a recovery in several of the stressed plants; a couple of which did not recover. An important lesson learned involved Veggie's bellows. The bellows tended to float and interfere with operations when opened, so Steve secured them to the baseplate during plant tending operations. Due to the perceived intensity of the LED lights, the crew found it challenging to both work under the lights and read crew procedures on their computer. Although the lights are not a safety

  11. 2D to 3D conversion implemented in different hardware

    Science.gov (United States)

    Ramos-Diaz, Eduardo; Gonzalez-Huitron, Victor; Ponomaryov, Volodymyr I.; Hernandez-Fragoso, Araceli

    2015-02-01

    Conversion of available 2D data for release in 3D content is a hot topic for providers and for success of the 3D applications, in general. It naturally completely relies on virtual view synthesis of a second view given by original 2D video. Disparity map (DM) estimation is a central task in 3D generation but still follows a very difficult problem for rendering novel images precisely. There exist different approaches in DM reconstruction, among them manually and semiautomatic methods that can produce high quality DMs but they demonstrate hard time consuming and are computationally expensive. In this paper, several hardware implementations of designed frameworks for an automatic 3D color video generation based on 2D real video sequence are proposed. The novel framework includes simultaneous processing of stereo pairs using the following blocks: CIE L*a*b* color space conversions, stereo matching via pyramidal scheme, color segmentation by k-means on an a*b* color plane, and adaptive post-filtering, DM estimation using stereo matching between left and right images (or neighboring frames in a video), adaptive post-filtering, and finally, the anaglyph 3D scene generation. Novel technique has been implemented on DSP TMS320DM648, Matlab's Simulink module over a PC with Windows 7, and using graphic card (NVIDIA Quadro K2000) demonstrating that the proposed approach can be applied in real-time processing mode. The time values needed, mean Similarity Structural Index Measure (SSIM) and Bad Matching Pixels (B) values for different hardware implementations (GPU, Single CPU, and DSP) are exposed in this paper.

  12. Loads and Structural Dynamics Requirements for Spaceflight Hardware

    Science.gov (United States)

    Schultz, Kenneth P.

    2011-01-01

    The purpose of this document is to establish requirements relating to the loads and structural dynamics technical discipline for NASA and commercial spaceflight launch vehicle and spacecraft hardware. Requirements are defined for the development of structural design loads and recommendations regarding methodologies and practices for the conduct of load analyses are provided. As such, this document represents an implementation of NASA STD-5002. Requirements are also defined for structural mathematical model development and verification to ensure sufficient accuracy of predicted responses. Finally, requirements for model/data delivery and exchange are specified to facilitate interactions between Launch Vehicle Providers (LVPs), Spacecraft Providers (SCPs), and the NASA Technical Authority (TA) providing insight/oversight and serving in the Independent Verification and Validation role. In addition to the analysis-related requirements described above, a set of requirements are established concerning coupling phenomena or other interaction between structural dynamics and aerodynamic environments or control or propulsion system elements. Such requirements may reasonably be considered structure or control system design criteria, since good engineering practice dictates consideration of and/or elimination of the identified conditions in the development of those subsystems. The requirements are included here, however, to ensure that such considerations are captured in the design space for launch vehicles (LV), spacecraft (SC) and the Launch Abort Vehicle (LAV). The requirements in this document are focused on analyses to be performed to develop data needed to support structural verification. As described in JSC 65828, Structural Design Requirements and Factors of Safety for Spaceflight Hardware, implementation of the structural verification requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each

  13. Software and hardware infrastructure for research in electrophysiology.

    Science.gov (United States)

    Mouček, Roman; Ježek, Petr; Vařeka, Lukáš; Rondík, Tomáš; Brůha, Petr; Papež, Václav; Mautner, Pavel; Novotný, Jiří; Prokop, Tomáš; Stěbeták, Jan

    2014-01-01

    As in other areas of experimental science, operation of electrophysiological laboratory, design and performance of electrophysiological experiments, collection, storage and sharing of experimental data and metadata, analysis and interpretation of these data, and publication of results are time consuming activities. If these activities are well organized and supported by a suitable infrastructure, work efficiency of researchers increases significantly. This article deals with the main concepts, design, and development of software and hardware infrastructure for research in electrophysiology. The described infrastructure has been primarily developed for the needs of neuroinformatics laboratory at the University of West Bohemia, the Czech Republic. However, from the beginning it has been also designed and developed to be open and applicable in laboratories that do similar research. After introducing the laboratory and the whole architectural concept the individual parts of the infrastructure are described. The central element of the software infrastructure is a web-based portal that enables community researchers to store, share, download and search data and metadata from electrophysiological experiments. The data model, domain ontology and usage of semantic web languages and technologies are described. Current data publication policy used in the portal is briefly introduced. The registration of the portal within Neuroscience Information Framework is described. Then the methods used for processing of electrophysiological signals are presented. The specific modifications of these methods introduced by laboratory researches are summarized; the methods are organized into a laboratory workflow. Other parts of the software infrastructure include mobile and offline solutions for data/metadata storing and a hardware stimulator communicating with an EEG amplifier and recording software.

  14. Hierarchical Simulation to Assess Hardware and Software Dependability

    Science.gov (United States)

    Ries, Gregory Lawrence

    1997-01-01

    This thesis presents a method for conducting hierarchical simulations to assess system hardware and software dependability. The method is intended to model embedded microprocessor systems. A key contribution of the thesis is the idea of using fault dictionaries to propagate fault effects upward from the level of abstraction where a fault model is assumed to the system level where the ultimate impact of the fault is observed. A second important contribution is the analysis of the software behavior under faults as well as the hardware behavior. The simulation method is demonstrated and validated in four case studies analyzing Myrinet, a commercial, high-speed networking system. One key result from the case studies shows that the simulation method predicts the same fault impact 87.5% of the time as is obtained by similar fault injections into a real Myrinet system. Reasons for the remaining discrepancy are examined in the thesis. A second key result shows the reduction in the number of simulations needed due to the fault dictionary method. In one case study, 500 faults were injected at the chip level, but only 255 propagated to the system level. Of these 255 faults, 110 shared identical fault dictionary entries at the system level and so did not need to be resimulated. The necessary number of system-level simulations was therefore reduced from 500 to 145. Finally, the case studies show how the simulation method can be used to improve the dependability of the target system. The simulation analysis was used to add recovery to the target software for the most common fault propagation mechanisms that would cause the software to hang. After the modification, the number of hangs was reduced by 60% for fault injections into the real system.

  15. Software and Hardware Infrastructure for Research in Electrophysiology

    Directory of Open Access Journals (Sweden)

    Roman eMouček

    2014-03-01

    Full Text Available As in other areas of experimental science, operation of electrophysiological laboratory, design and performance of electrophysiological experiments, collection, storage and sharing of experimental data and metadata, analysis and interpretation of these data, and publication of results are time consuming activities. If these activities are well organized and supported by a suitable infrastructure, work efficiency of researchers increases significantly.This article deals with the main concepts, design, and development of software and hardware infrastructure for research in electrophysiology. The described infrastructure has been primarily developed for the needs of neuroinformatics laboratory at the University of West Bohemia, the Czech Republic. However, from the beginning it has been also designed and developed to be open and applicable in laboratories that do similar research.After introducing the laboratory and the whole architectural concept the individual parts of the infrastructure are described. The central element of the software infrastructure is a web-based portal that enables community researchers to store, share, download and search data and metadata from electrophysiological experiments. The data model, domain ontology and usage of semantic web languages and technologies are described. Current data publication policy used in the portal is briefly introduced. The registration of the portal within Neuroscience Information Framework is described. Then the methods used for processing of electrophysiological signals are presented. The specific modifications of these methods introduced by laboratory researches are summarized; the methods are organized into a laboratory workflow. Other parts of the software infrastructure include mobile and offline solutions for data/metadata storing and a hardware stimulator communicating with an EEG amplifier and recording software.

  16. Polemic and Descriptive Negations

    DEFF Research Database (Denmark)

    Horslund, Camilla Søballe

    2011-01-01

    to semantics and pragmatics, negations can be used in three different ways, which gives rise to a typology of three different types of negations: 1) the descriptive negation, 2) the polemic negation, and 3) the meta-linguistic negation (Nølke 1999, 4). This typology illuminates the fact that the negation...... as such may be more or less central to the meaning of the utterance. The present paper investigates the role of morphosyntactic and prosodic prominence as well as register and social setting on the interpretation of negations. It seems plausible to expect that if the negation as such is central to the meaning...... of the utterance (as in polemic negations), the negation will be articulated prominently in order to emphasise this importance. Likewise, if the negation is not central to the meaning of the utterance, it should not be articulated prominently. Moreover, it is plausible to expect descriptive negations to be more...

  17. Multidimensional nonlinear descriptive analysis

    CERN Document Server

    Nishisato, Shizuhiko

    2006-01-01

    Quantification of categorical, or non-numerical, data is a problem that scientists face across a wide range of disciplines. Exploring data analysis in various areas of research, such as the social sciences and biology, Multidimensional Nonlinear Descriptive Analysis presents methods for analyzing categorical data that are not necessarily sampled randomly from a normal population and often involve nonlinear relations. This reference not only provides an overview of multidimensional nonlinear descriptive analysis (MUNDA) of discrete data, it also offers new results in a variety of fields. The first part of the book covers conceptual and technical preliminaries needed to understand the data analysis in subsequent chapters. The next two parts contain applications of MUNDA to diverse data types, with each chapter devoted to one type of categorical data, a brief historical comment, and basic skills peculiar to the data types. The final part examines several problems and then concludes with suggestions for futu...

  18. Factors associated with failed hardware salvage in high-risk patients after microsurgical lower extremity reconstruction.

    Science.gov (United States)

    Patel, Ketan M; Seruya, Mitchel; Franklin, Brenton; Attinger, Christopher E; Ducic, Ivica

    2012-10-01

    Lower extremity hardware salvage remains challenging in patients with complex comorbidities. The purpose of this study was to identify factors associated with failed hardware salvage after microsurgical lower extremity reconstruction. A retrospective, institutional review board-approved review was performed of patients who underwent lower extremity hardware salvage via free tissue transfer from 2004 to 2010. Outcomes were binarized into successful versus failed hardware salvage, with failure defined as nonelective removal. Patient demographics, wound characteristics, microbiology, and pathology were compared. Thirty-four patients underwent lower extremity hardware salvage via free tissue transfer, with an average follow-up of 3.2 years (range, 0.3-7.0 years). Of these patients, 15 (44.1%) had successful hardware salvage and 19 (55.9%) required hardware removal. By demographics, a higher prevalence of multiple comorbidities was found in patients with failed hardware salvage. Wound characteristics revealed a significantly longer time to hardware coverage and longer duration of intravenous antibiotics in failed versus successful hardware salvage patients (38.9 vs 9.3 weeks, P=0.02; 6.5 vs 4.1 weeks, P=0.03, respectively). Initial wound cultures demonstrated a significantly higher frequency of positive growth in patients with failed versus successful hardware salvage (100.0% vs 57.1%, P=0.003). Initial pathology revealed a borderline-significantly higher frequency of chronic osteomyelitis in failed versus successful salvage patients (66.7% vs 33.3%, P=0.08). In this retrospective review of microsurgical lower extremity reconstruction, factors associated with failed hardware salvage included multiple comorbidities, longer time to hardware coverage, increased duration of intravenous antibiotics, positive initial wound cultures, and chronic osteomyelitis on initial pathology.

  19. The SIFT hardware/software systems. Volume 2: Software listings

    Science.gov (United States)

    Palumbo, Daniel L.

    1985-01-01

    This document contains software listings of the SIFT operating system and application software. The software is coded for the most part in a variant of the Pascal language, Pascal*. Pascal* is a cross-compiler running on the VAX and Eclipse computers. The output of Pascal* is BDX-390 assembler code. When necessary, modules are written directly in BDX-390 assembler code. The listings in this document supplement the description of the SIFT system found in Volume 1 of this report, A Detailed Description.

  20. A HARDWARE IMPLEMENTATION OF PUNCTURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

    Directory of Open Access Journals (Sweden)

    E. García,

    2005-08-01

    Full Text Available This paper presents a VLSI (Very Large Scale Integration implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

  1. Combining Topological Hardware and Topological Software: Color-Code Quantum Computing with Topological Superconductor Networks

    Directory of Open Access Journals (Sweden)

    Daniel Litinski

    2017-09-01

    Full Text Available We present a scalable architecture for fault-tolerant topological quantum computation using networks of voltage-controlled Majorana Cooper pair boxes and topological color codes for error correction. Color codes have a set of transversal gates which coincides with the set of topologically protected gates in Majorana-based systems, namely, the Clifford gates. In this way, we establish color codes as providing a natural setting in which advantages offered by topological hardware can be combined with those arising from topological error-correcting software for full-fledged fault-tolerant quantum computing. We provide a complete description of our architecture, including the underlying physical ingredients. We start by showing that in topological superconductor networks, hexagonal cells can be employed to serve as physical qubits for universal quantum computation, and we present protocols for realizing topologically protected Clifford gates. These hexagonal-cell qubits allow for a direct implementation of open-boundary color codes with ancilla-free syndrome read-out and logical T gates via magic-state distillation. For concreteness, we describe how the necessary operations can be implemented using networks of Majorana Cooper pair boxes, and we give a feasibility estimate for error correction in this architecture. Our approach is motivated by nanowire-based networks of topological superconductors, but it could also be realized in alternative settings such as quantum-Hall–superconductor hybrids.

  2. Understanding descriptive statistics.

    Science.gov (United States)

    Fisher, Murray J; Marshall, Andrea P

    2009-05-01

    There is an increasing expectation that critical care nurses use clinical research when making decisions about patient care. This article is the second in a series which addresses statistics for clinical nursing practice. In this article we provide an introduction to the use of descriptive statistics. Concepts such as levels of measurement, measures of central tendency and dispersion are described and their use in clinical practice is illustrated.

  3. Integrated conception of hardware/software mixed systems used in nuclear instrumentation; Concepcao integrada de sistemas mistos hardware/software utilizados em instrumentacao nuclear

    Energy Technology Data Exchange (ETDEWEB)

    Dias, Ailton F. [Comissao Nacional de Energia Nuclear (CNEN), Rio de Janeiro, RJ (Brazil). Coordenacao Geral de Informatica; Sorel, Yves [Institut National de Recherches en Informatique et en Automatique (INRIA), Le Chesnay Cedex (France). Projet SOSSO; Akil, Mohamed [Ecole Superieure en Electrotechnique et Electronique, Noisy-le-Grand Cedex (France). Lab. Algorithmique et Architecture des Systemes Informatiques

    2002-07-01

    Hardware/software codesign carries out the design of systems composed by a hardware portion, with specific components, and a software portion, with microprocessor based architecture. This paper describes the Algorithm Architecture Adequation (AAA) design methodology - originally oriented to programmable multicomponent architectures, its extension to reconfigurable circuits and its application to design and development of nuclear instrumentation systems composed by programmable and configurable circuits. AAA methodology uses an unified model to describe algorithm, architecture and implementation, based on graph theory. The great advantage of AAA methodology is the utilization of a same model from the specification to the implementation of hardware/software systems, reducing the complexity and design time. (author)

  4. Desenvolvimento de hardware reconfigurável de criptografia assimétrica

    Directory of Open Access Journals (Sweden)

    Otávio Souza Martins Gomes

    2015-01-01

    Full Text Available Este artigo apresenta o resultado parcial do desenvolvimento de uma interface de hardware reconfigurável para criptografia assimétrica que permite a troca segura de dados. Hardwares reconfiguráveis permitem o desenvolvimento deste tipo de dispositivo com segurança e flexibilidade e possibilitam a mudança de características no projeto com baixo custo e de forma rápida.Palavras-chave: Criptografia. Hardware. ElGamal. FPGA. Segurança. Development of an asymmetric cryptography reconfigurable harwadre ABSTRACTThis paper presents some conclusions and choices about the development of an asymmetric cryptography reconfigurable hardware interface to allow a safe data communication. Reconfigurable hardwares allows the development of this kind of device with safety and flexibility, and offer the possibility to change some features with low cost and in a fast way.Keywords: Cryptography. Hardware. ElGamal. FPGAs. Security.

  5. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

    Science.gov (United States)

    Asaad, Sameth W.; Kapur, Mohit

    2016-01-05

    A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

  6. Hardware complications in oromandibular defects: Comparing scapular and fibular based free flap reconstructions.

    Science.gov (United States)

    Tsang, Gordon F Z; Zhang, Han; Yao, Christopher; Kolarski, Mirko; Gullane, Patrick J; Irish, Jonathan C; Brown, Dale H; Chepeha, Douglas B; Goldstein, David P; Gilbert, Ralph W; de Almeida, John R

    2017-08-01

    Despite improvements in surgical technique and technology, hardware complications occur relatively frequently. This study analyzes hardware complications in patients undergoing oromandibular reconstruction using scapular (SFF) or fibular (FFF) free flaps. Retrospective data for 178 patients was obtained (1999-2014) at University Hospital Network (Toronto, Canada). Univariable and multivariable analyses were performed to identify risk factors for hardware complications. Patients with FFF reconstruction (n=129) had significantly more hardware complications than those with SFF (n=49) (16% vs. 2%;p=0.01). Surgical site infection (SSI) (OR=7.05; phardware complications on univariable analysis. Flap type (OR=0.12; p=0.04) was an independent predictor of plate complication after adjusting for SSI. A subgroup analysis suggested a trend towards fewer hardware complications with SFF stratified by mandibular defect type. Scapular free flaps are associated with a lower rate of hardware-related complications in oromandibular reconstruction. Copyright © 2017 Elsevier Ltd. All rights reserved.

  7. Compact hardware liquid state machines on FPGA for real-time speech recognition.

    Science.gov (United States)

    Schrauwen, Benjamin; D'Haene, Michiel; Verstraeten, David; Campenhout, Jan Van

    2008-01-01

    Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic neural networks. This work presents an application driven digital hardware exploration where we implement real-time, isolated digit speech recognition using a Liquid State Machine. The Liquid State Machine is a recurrent neural network of spiking neurons where only the output layer is trained. First we test two existing hardware architectures which we improve and extend, but that appears to be too fast and thus area consuming for this application. Next, we present a scalable, serialized architecture that allows a very compact implementation of spiking neural networks that is still fast enough for real-time processing. All architectures support leaky integrate-and-fire membranes with exponential synaptic models. This work shows that there is actually a large hardware design space of Spiking Neural Network hardware that can be explored. Existing architectures have only spanned part of it.

  8. A Systematic Software, Firmware, and Hardware Codesign Methodology for Digital Signal Processing

    Science.gov (United States)

    2014-03-01

    Requirements The requirements and design activities must be iterative. Gestalt round-trip design , introduced by Grady Booch [18] in 1994, emphasizes the...schedule goals is a software-and- hardware codesign problem, since the design of the software and hardware components influence each other. The traditional... design methodology is sequential, with hardware designed first and then software. The lack of a unified and unbiased approach can lead to suboptimal

  9. Electronic Warfare Closed Loop Laboratory (EWCLL) Antenna Motor Software and Hardware Development

    Science.gov (United States)

    2016-09-01

    Electronic Warfare Closed Loop Laboratory (EWCLL) Antenna Motor Software and Hardware Development by Neal Tesny Sensors and Electron Devices Directorate...TITLE AND SUBTITLE Electronic Warfare Closed Loop Laboratory (EWCLL) Antenna Motor Software and Hardware Development 5a. CONTRACT NUMBER 5b...14. ABSTRACT Software and hardware were developed to control the rotation of the 6 double-ridged waveguide horn antennas that are used in the

  10. A systematic software, firmware, and hardware codesign methodology for digital signal processing

    OpenAIRE

    Chang, Daniel Y.

    2014-01-01

    Approved for public release; distribution is unlimited. Creating an embedded system that meets its functional, performance, cost, and schedule goals is a software-and-hardware codesign problem, since the design of the software and hardware components influence each other. The traditional design methodology is sequential, with hardware designed first and then software. The lack of a unified and unbiased approach can lead to suboptimal design and incompatibilities across the software and har...

  11. Hardware based redundant multi-threading inside a GPU for improved reliability

    Science.gov (United States)

    Sridharan, Vilas; Gurumurthi, Sudhanva

    2015-05-05

    A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output.

  12. Enforcing Hardware-Assisted Integrity for Secure Transactions from Commodity Operating Systems

    Science.gov (United States)

    2015-08-17

    14-Jan-2011 13-Jul-2011 Approved for Public Release; Distribution Unlimited Final Report: Enforcing Hardware -Assisted Integrity for Secure...AND ADDRESS (ES) U.S. Army Research Office P.O. Box 12211 Research Triangle Park, NC 27709-2211 Tailor Trusted Spaces, Hardware -Assisted...published in non peer-reviewed journals: Final Report: Enforcing Hardware -Assisted Integrity for Secure Transactions from Commodity Operating Systems

  13. Experiment Design Regularization-Based Hardware/Software Codesign for Real-Time Enhanced Imaging in Uncertain Remote Sensing Environment

    Directory of Open Access Journals (Sweden)

    Castillo Atoche A

    2010-01-01

    Full Text Available A new aggregated Hardware/Software (HW/SW codesign approach to optimization of the digital signal processing techniques for enhanced imaging with real-world uncertain remote sensing (RS data based on the concept of descriptive experiment design regularization (DEDR is addressed. We consider the applications of the developed approach to typical single-look synthetic aperture radar (SAR imaging systems operating in the real-world uncertain RS scenarios. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale SAR image enhancement tasks. The innovative algorithmic idea is to incorporate into the DEDR-optimized fixed-point iterative reconstruction/enhancement procedure the convex convergence enforcement regularization via constructing the proper multilevel projections onto convex sets (POCS in the solution domain. The hardware design is performed via systolic array computing based on a Xilinx Field Programmable Gate Array (FPGA XC4VSX35-10ff668 and is aimed at implementing the unified DEDR-POCS image enhancement/reconstruction procedures in a computationally efficient multi-level parallel fashion that meets the (near real-time image processing requirements. Finally, we comment on the simulation results indicative of the significantly increased performance efficiency both in resolution enhancement and in computational complexity reduction metrics gained with the proposed aggregated HW/SW co-design approach.

  14. Description logic rules

    CERN Document Server

    Krötzsch, M

    2010-01-01

    Ontological modelling today is applied in many areas of science and technology,including the Semantic Web. The W3C standard OWL defines one of the most important ontology languages based on the semantics of description logics. An alternative is to use rule languages in knowledge modelling, as proposed in the W3C's RIF standard. So far, it has often been unclear how to combine both technologies without sacrificing essential computational properties. This book explains this problem and presents new solutions that have recently been proposed. Extensive introductory chapters provide the necessary

  15. W-026 acceptance test report plant control system hardware (submittal {number_sign} 220.C)

    Energy Technology Data Exchange (ETDEWEB)

    Watson, T.L., Fluor Daniel Hanford

    1997-02-14

    Acceptance Testing of the WRAP1 Plant Control System Hardware was conducted throughout the construction of WRAPI with the final testing on the Process Area hardware being completed in November 1996. The hardware tests were broken out by the following functional areas; Local Control Units, Operator Control Stations in the WRAP Control Room, DMS Server, PCS Server, Operator Interface Units, printers, DMS terminals, WRAP Local Area Network/Communications, and bar code equipment. This document contains a completed copy of each of the hardware tests along with the applicable test logs and completed test exception reports.

  16. Hardware and Software Integration to Support Real-Time Space-Link Emulation

    Science.gov (United States)

    Murawski, Robert; Bhasin, Kul; Bittner, David

    2012-01-01

    Prior to operational use, communications hardware and software must be thoroughly tested and verified. In space-link communications, field testing equipment can be prohibitively expensive and cannot test to non-ideal situations. In this paper, we show how software and hardware emulation tools can be used to accurately model the characteristics of a satellite communication channel in a lab environment. We describe some of the challenges associated with developing an emulation lab and present results to demonstrate the channel modeling. We then show how network emulation software can be used to extend a hardware emulation model without requiring additional network and channel simulation hardware.

  17. Hardware and Software Integration to Support Real-Time Space Link Emulation

    Science.gov (United States)

    Murawski, Robert; Bhasin, Kul; Bittner, David; Sweet, Aaron; Coulter, Rachel; Schwab, Devin

    2012-01-01

    Prior to operational use, communications hardware and software must be thoroughly tested and verified. In space-link communications, field testing equipment can be prohibitively expensive and cannot test to non-ideal situations. In this paper, we show how software and hardware emulation tools can be used to accurately model the characteristics of a satellite communication channel in a lab environment. We describe some of the challenges associated with developing an emulation lab and present results to demonstrate the channel modeling. We then show how network emulation software can be used to extend a hardware emulation model without requiring additional network and channel simulation hardware.

  18. W-026 acceptance test plan plant control system hardware (submittal {number_sign} 216)

    Energy Technology Data Exchange (ETDEWEB)

    Watson, T.L., Fluor Daniel Hanford

    1997-02-14

    Acceptance Testing of the WRAP 1 Plant Control System Hardware will be conducted throughout the construction of WRAP I with the final testing on the Process Area hardware being completed in November 1996. The hardware tests will be broken out by the following functional areas; Local Control Units, Operator Control Stations in the WRAP Control Room, DMS Server, PCS Server, Operator Interface Units, printers, DNS terminals, WRAP Local Area Network/Communications, and bar code equipment. This document will contain completed copies of each of the hardware tests along with the applicable test logs and completed test exception reports.

  19. Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

    Science.gov (United States)

    Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

    2000-01-01

    The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

  20. 15 MW HArdware-in-the-loop Grid Simulation Project

    Energy Technology Data Exchange (ETDEWEB)

    Rigas, Nikolaos [Clemson Univ., SC (United States); Fox, John Curtiss [Clemson Univ., SC (United States); Collins, Randy [Clemson Univ., SC (United States); Tuten, James [Clemson Univ., SC (United States); Salem, Thomas [Clemson Univ., SC (United States); McKinney, Mark [Clemson Univ., SC (United States); Hadidi, Ramtin [Clemson Univ., SC (United States); Gislason, Benjamin [Clemson Univ., SC (United States); Boessneck, Eric [Clemson Univ., SC (United States); Leonard, Jesse [Clemson Univ., SC (United States)

    2014-10-31

    The 15MW Hardware-in-the-loop (HIL) Grid Simulator project was to (1) design, (2) construct and (3) commission a state-of-the-art grid integration testing facility for testing of multi-megawatt devices through a ‘shared facility’ model open to all innovators to promote the rapid introduction of new technology in the energy market to lower the cost of energy delivered. The 15 MW HIL Grid Simulator project now serves as the cornerstone of the Duke Energy Electric Grid Research, Innovation and Development (eGRID) Center. This project leveraged the 24 kV utility interconnection and electrical infrastructure of the US DOE EERE funded WTDTF project at the Clemson University Restoration Institute in North Charleston, SC. Additionally, the project has spurred interest from other technology sectors, including large PV inverter and energy storage testing and several leading edge research proposals dealing with smart grid technologies, grid modernization and grid cyber security. The key components of the project are the power amplifier units capable of providing up to 20MW of defined power to the research grid. The project has also developed a one of a kind solution to performing fault ride-through testing by combining a reactive divider network and a large power converter into a hybrid method. This unique hybrid method of performing fault ride-through analysis will allow for the research team at the eGRID Center to investigate the complex differences between the alternative methods of performing fault ride-through evaluations and will ultimately further the science behind this testing. With the final goal of being able to perform HIL experiments and demonstration projects, the eGRID team undertook a significant challenge with respect to developing a control system that is capable of communicating with several different pieces of equipment with different communication protocols in real-time. The eGRID team developed a custom fiber optical network that is based upon FPGA

  1. Life sciences flight hardware development for the International Space Station

    Science.gov (United States)

    Kern, V. D.; Bhattacharya, S.; Bowman, R. N.; Donovan, F. M.; Elland, C.; Fahlen, T. F.; Girten, B.; Kirven-Brooks, M.; Lagel, K.; Meeker, G. B.; Santos, O.

    During the construction phase of the International Space Station (ISS), early flight opportunities have been identified (including designated Utilization Flights, UF) on which early science experiments may be performed. The focus of NASA's and other agencies' biological studies on the early flight opportunities is cell and molecular biology; with UF-1 scheduled to fly in fall 2001, followed by flights 8A and UF-3. Specific hardware is being developed to verify design concepts, e.g., the Avian Development Facility for incubation of small eggs and the Biomass Production System for plant cultivation. Other hardware concepts will utilize those early research opportunities onboard the ISS, e.g., an Incubator for sample cultivation, the European Modular Cultivation System for research with small plant systems, an Insect Habitat for support of insect species. Following the first Utilization Flights, additional equipment will be transported to the ISS to expand research opportunities and capabilities, e.g., a Cell Culture Unit, the Advanced Animal Habitat for rodents, an Aquatic Facility to support small fish and aquatic specimens, a Plant Research Unit for plant cultivation, and a specialized Egg Incubator for developmental biology studies. Host systems (Figure 1A, B), e.g., a 2.5 m Centrifuge Rotor (g-levels from 0.01-g to 2-g) for direct comparisons between μg and selectable g levels, the Life Sciences Glove☐ for contained manipulations, and Habitat Holding Racks (Figure 1B) will provide electrical power, communication links, and cooling to the habitats. Habitats will provide food, water, light, air and waste management as well as humidity and temperature control for a variety of research organisms. Operators on Earth and the crew on the ISS will be able to send commands to the laboratory equipment to monitor and control the environmental and experimental parameters inside specific habitats. Common laboratory equipment such as microscopes, cryo freezers, radiation

  2. AER synthetic generation in hardware for bio-inspired spiking systems

    Science.gov (United States)

    Linares-Barranco, Alejandro; Linares-Barranco, Bernabe; Jimenez-Moreno, Gabriel; Civit-Balcells, Anton

    2005-06-01

    Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) convert conventional frame-based video stream in the computer into AER and inject it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. This paper addresses the problem of converting, in a computer, a conventional frame-based video stream into the spike event based representation AER. There exist several proposed software methods for synthetic generation of AER for bio-inspired systems. This paper presents a hardware implementation for one method, which is based on Linear-Feedback-Shift-Register (LFSR) pseudo-random number generation. The sequence of events generated by this hardware, which follows a Poisson distribution like a biological neuron, has been reconstructed using two AER integrator cells. The error of reconstruction for a set of images that produces different traffic loads of event in the AER bus is used as evaluation criteria. A VHDL description of the method, that includes the Xilinx PCI Core, has been implemented and tested using a general purpose PCI-AER board. This PCI-AER board has been developed by authors, and uses

  3. A Hardware Fast Tracker for the ATLAS trigger

    CERN Document Server

    Asbah, Nedaa; The ATLAS collaboration

    2015-01-01

    The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10^{34} cm^{-2}s^{-1}. After a successful period of data taking from 2010 to early 2013, the LHC restarted with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide, at every level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondar...

  4. Facilitating preemptive hardware system design using partial reconfiguration techniques.

    Science.gov (United States)

    Dondo Gazzano, Julio; Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

    2014-01-01

    In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.

  5. What Scientific Applications can Benefit from Hardware Transactional Memory?

    Energy Technology Data Exchange (ETDEWEB)

    Schindewolf, M; Bihari, B; Gyllenhaal, J; Schulz, M; Wang, A; Karl, W

    2012-06-04

    Achieving efficient and correct synchronization of multiple threads is a difficult and error-prone task at small scale and, as we march towards extreme scale computing, will be even more challenging when the resulting application is supposed to utilize millions of cores efficiently. Transactional Memory (TM) is a promising technique to ease the burden on the programmer, but only recently has become available on commercial hardware in the new Blue Gene/Q system and hence the real benefit for realistic applications has not been studied, yet. This paper presents the first performance results of TM embedded into OpenMP on a prototype system of BG/Q and characterizes code properties that will likely lead to benefits when augmented with TM primitives. We first, study the influence of thread count, environment variables and memory layout on TM performance and identify code properties that will yield performance gains with TM. Second, we evaluate the combination of OpenMP with multiple synchronization primitives on top of MPI to determine suitable task to thread ratios per node. Finally, we condense our findings into a set of best practices. These are applied to a Monte Carlo Benchmark and a Smoothed Particle Hydrodynamics method. In both cases an optimized TM version, executed with 64 threads on one node, outperforms a simple TM implementation. MCB with optimized TM yields a speedup of 27.45 over baseline.

  6. Towards Batched Linear Solvers on Accelerated Hardware Platforms

    Energy Technology Data Exchange (ETDEWEB)

    Haidar, Azzam [University of Tennessee (UT); Dong, Tingzing Tim [University of Tennessee (UT); Tomov, Stanimire [University of Tennessee (UT); Dongarra, Jack J [ORNL

    2015-01-01

    As hardware evolves, an increasingly effective approach to develop energy efficient, high-performance solvers, is to design them to work on many small and independent problems. Indeed, many applications already need this functionality, especially for GPUs, which are known to be currently about four to five times more energy efficient than multicore CPUs for every floating-point operation. In this paper, we describe the development of the main one-sided factorizations: LU, QR, and Cholesky; that are needed for a set of small dense matrices to work in parallel. We refer to such algorithms as batched factorizations. Our approach is based on representing the algorithms as a sequence of batched BLAS routines for GPU-contained execution. Note that this is similar in functionality to the LAPACK and the hybrid MAGMA algorithms for large-matrix factorizations. But it is different from a straightforward approach, whereby each of GPU's symmetric multiprocessors factorizes a single problem at a time. We illustrate how our performance analysis together with the profiling and tracing tools guided the development of batched factorizations to achieve up to 2-fold speedup and 3-fold better energy efficiency compared to our highly optimized batched CPU implementations based on the MKL library on a two-sockets, Intel Sandy Bridge server. Compared to a batched LU factorization featured in the NVIDIA's CUBLAS library for GPUs, we achieves up to 2.5-fold speedup on the K40 GPU.

  7. Space station common module network topology and hardware development

    Science.gov (United States)

    Anderson, P.; Braunagel, L.; Chwirka, S.; Fishman, M.; Freeman, K.; Eason, D.; Landis, D.; Lech, L.; Martin, J.; Mccorkle, J.

    1990-01-01

    Conceptual space station common module power management and distribution (SSM/PMAD) network layouts and detailed network evaluations were developed. Individual pieces of hardware to be developed for the SSM/PMAD test bed were identified. A technology assessment was developed to identify pieces of equipment requiring development effort. Equipment lists were developed from the previously selected network schematics. Additionally, functional requirements for the network equipment as well as other requirements which affected the suitability of specific items for use on the Space Station Program were identified. Assembly requirements were derived based on the SSM/PMAD developed requirements and on the selected SSM/PMAD network concepts. Basic requirements and simplified design block diagrams are included. DC remote power controllers were successfully integrated into the DC Marshall Space Flight Center breadboard. Two DC remote power controller (RPC) boards experienced mechanical failure of UES 706 stud-mounted diodes during mechanical installation of the boards into the system. These broken diodes caused input to output shorting of the RPC's. The UES 706 diodes were replaced on these RPC's which eliminated the problem. The DC RPC's as existing in the present breadboard configuration do not provide ground fault protection because the RPC was designed to only switch the hot side current. If ground fault protection were to be implemented, it would be necessary to design the system so the RPC switched both the hot and the return sides of power.

  8. A Fast hardware tracker for the ATLAS Trigger

    CERN Document Server

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. To achieve high background rejection while maintaining good efficiency for interesting physics signals, sophisticated algorithms are needed which require extensive use of tracking information. The Fast TracKer (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform track-finding at 100 kHz and based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGA) form an important part of the system architecture, and the combinatorial problem of pattern recognition is solved by ~8000 standard-cell ASICs named Associative Memories. The availability of the tracking and subsequent vertex information within a short latency ensures robust selections and allows improved trigger performance for the most difficult sign...

  9. A Fast hardware Tracker for the ATLAS Trigger system

    CERN Document Server

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. After a very successful data taking run the LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals, which requires a more extensive use of tracking information. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful, Field Programmable Gate Arrays form an important part of the system architecture, and the combinatorial problem of pattern r...

  10. Hardware-in-the-Loop emulator for a hydrokinetic turbine

    Science.gov (United States)

    Rat, C. L.; Prostean, O.; Filip, I.

    2018-01-01

    Hydroelectric power has proven to be an efficient and reliable form of renewable energy, but its impact on the environment has long been a source of concern. Hydrokinetic turbines are an emerging class of renewable energy technology designed for deployment in small rivers and streams with minimal environmental impact on the local ecosystem. Hydrokinetic technology represents a truly clean source of energy, having the potential to become a highly efficient method of harvesting renewable energy. However, in order to achieve this goal, extensive research is necessary. This paper presents a Hardware-in-the-Loop emulator for a run-of-the-river type hydrokinetic turbine. The HIL system uses an ABB ACS800 drive to control an induction machine as a significant means of replicating the behavior of the real turbine. The induction machine is coupled to a permanent magnet synchronous generator and the corresponding load. The ACS800 drive is controlled through the software system, which comprises of the hydrokinetic turbine real-time simulation through mathematical modeling in the LabVIEW programming environment running on a NI CompactRIO (cRIO) platform. The advantages of this method are that it can provide a means for testing many control configurations without requiring the presence of the real turbine. This paper contains the basic principles of a hydrokinetic turbine, particularly the run-of-the-river configurations along with the experimental results obtained from the HIL system.

  11. Hardware Accelerator for the Multifractal Analysis of DNA Sequences.

    Science.gov (United States)

    Duarte-Sanchez, Jorge E; Velasco-Medina, Jaime; Moreno, Pedro A

    2017-07-24

    The multifractal analysis has allowed to quantify the genetic variability and non-linear stability along the human genome sequence. It has some implications in explaining several genetic diseases given by some chromosome abnormalities, among other genetic particularities. The multifractal analysis of a genome is carried out by dividing the complete DNA sequence in smaller fragments and calculating the generalized dimension spectrum of each fragment using the chaos game representation and the box-counting method. This is a time consuming process because it involves the processing of large data sets using floating-point representation. In order to reduce the computation time, we designed an application-specific processor, here called multifractal processor, which is based on our proposed hardware-oriented algorithm for calculating efficiently the generalized dimension spectrum of DNA sequences. The multifractal processor was implemented on a low-cost SoC-FPGA and was verified by processing a complete human genome. The execution time and numeric results of the Multifractal processor were compared with the results obtained from the software implementation executed in a 20-core workstation, achieving a speed up of 2.6x and an average error of 0.0003%.

  12. Demonstrating Hybrid Learning in a Flexible Neuromorphic Hardware System.

    Science.gov (United States)

    Friedmann, Simon; Schemmel, Johannes; Grubl, Andreas; Hartel, Andreas; Hock, Matthias; Meier, Karlheinz

    2017-02-01

    We present results from a new approach to learning and plasticity in neuromorphic hardware systems: to enable flexibility in implementable learning mechanisms while keeping high efficiency associated with neuromorphic implementations, we combine a general-purpose processor with full-custom analog elements. This processor is operating in parallel with a fully parallel neuromorphic system consisting of an array of synapses connected to analog, continuous time neuron circuits. Novel analog correlation sensor circuits process spike events for each synapse in parallel and in real-time. The processor uses this pre-processing to compute new weights possibly using additional information following its program. Therefore, to a certain extent, learning rules can be defined in software giving a large degree of flexibility. Synapses realize correlation detection geared towards Spike-Timing Dependent Plasticity (STDP) as central computational primitive in the analog domain. Operating at a speed-up factor of 1000 compared to biological time-scale, we measure time-constants from tens to hundreds of micro-seconds. We analyze variability across multiple chips and demonstrate learning using a multiplicative STDP rule. We conclude that the presented approach will enable flexible and efficient learning as a platform for neuroscientific research and technological applications.

  13. Accelerating Popular Tomographic Reconstruction Algorithms on Commodity PC Graphics Hardware

    Science.gov (United States)

    Xu, Fang; Mueller, K.

    2005-06-01

    The task of reconstructing an object from its projections via tomographic methods is a time-consuming process due to the vast complexity of the data. For this reason, manufacturers of equipment for medical computed tomography (CT) rely mostly on special application specified integrated circuits (ASICs) to obtain the fast reconstruction times required in clinical settings. Although modern CPUs have gained sufficient power in recent years to be competitive for two-dimensional (2D) reconstruction, this is not the case for three-dimensional (3D) reconstructions, especially not when iterative algorithms must be applied. The recent evolution of commodity PC computer graphics boards (GPUs) has the potential to change this picture in a very dramatic way. In this paper we will show how the new floating point GPUs can be exploited to perform both analytical and iterative reconstruction from X-ray and functional imaging data. For this purpose, we decompose three popular three-dimensional (3D) reconstruction algorithms (Feldkamp filtered backprojection, the simultaneous algebraic reconstruction technique, and expectation maximization) into a common set of base modules, which all can be executed on the GPU and their output linked internally. Visualization of the reconstructed object is easily achieved since the object already resides in the graphics hardware, allowing one to run a visualization module at any time to view the reconstruction results. Our implementation allows speedups of over an order of magnitude with respect to CPU implementations, at comparable image quality.

  14. "Hardware breakage in spine surgery (A retrospective clinical study "

    Directory of Open Access Journals (Sweden)

    "Sadat MM

    2001-11-01

    Full Text Available This was a retrospective review of a consecutive series of patients with spinal disease in year 2000, who underwent posterior fusion and instrumentation with Harrington distraction and Cotrel-Dobousset system to evaluate causes of hardware failure. Many cases of clinical failure has been observed in spinal instrumentation used in spinal disorder like spondylolisthesis, fractures, deformities, … . Thirty six cases that were operated because of spinal disorders like spondylolisthesis, fractures, deformities, …, were included in this study. Seventeen of this cases had breakage of device. Factors like age at surgery, type of instrumentation, angles before and after surgery and …, were compared in two groups of patients. The most common instrument breakage was pedicle screw breakage. Pseudoarthrosis was the main factor that was presented in failure group (P value<0.001. Other important causes were, age of patient at surgery (P value=0.04, pedicle screw placement off center in the sagittal or coronal plane of the pedicle (P value=0.04. Instrumentation loads increased significantly as a direct result of variations in surgical technique that produce pseudoarthrosis, pedicle screw placement off center in the sagittal plane of the pedicle, or using less than 6 mm diameter screw. This factor can be prevented with meticulous surgical technique and using proper devices.

  15. Surveys of ISS Returned Hardware for MMOD Impacts

    Science.gov (United States)

    Hyde, James; Christiansen, E.; Lear, D.; Nagy, K.

    2017-01-01

    Since February 2001, the Hypervelocity Impact Technology (HVIT) group at the Johnson Space Center in Houston has performed 26 post-flight inspections on space exposed hardware that have been returned from the International Space Station. Data on 1,024 observations of MMOD damage have been collected from these inspections. Survey documentation typically includes impact feature location and size measurements as well as microscopic photography (25-200x). Sampling of impacts sites for projectile residue was performed for the largest features. Results of Scanning Electron Microscopy (SEM) analysis to discern impactor source is included in the database. This paper will summarize the post-flight MMOD inspections, and focus on two inspections in particular: (1) Pressurized Mating Adapter-2 (PMA-2) cover returned in 2015 after 1.6 years exposure with 26 observed damages, and (2) Airlock shield panels returned in 2010 after 8.7 years exposure with 58 MMOD damages. Feature sizes from the observed data are compared to predictions using the Bumper risk assessment code.

  16. Surveys of Returned ISS Hardware for MMMOD Impacts

    Science.gov (United States)

    Hyde, J. L.; Christiansen, E. L.; Lear, D. M.; Nagy, K.; Berger, E. L.

    2017-01-01

    Since February 2001, the Hypervelocity Impact Technology (HVIT) group at the Johnson Space Center (JSC) in Houston has performed 35 post-flight inspections on space exposed hardware returned from the International Space Station (ISS). Data on 1,188 observations of micrometeoroid and orbital debris (MMOD) damage have been collected from these inspections. Survey documentation typically includes impact feature location and size measurements as well as microscopic photography (25-200x). Sampling of impacts sites for projectile residue was performed for the largest features. Results of energy dispersive X-ray spectroscopic analysis to discern impactor source are included in the database when available. This paper will focus on two inspections, the Pressurized Mating Adapter 2 (PMA-2) cover returned in 2015 after 1.6 years exposure with 26 observed impact features, and two Airlock shield panels returned in 2010 after 8.75 years exposure with 58 MMOD impacts. Feature sizes from the observed data are compared to predictions using the Bumper 3 risk assessment code.

  17. The Hardware Topological Trigger of ATLAS: Commissioning and Operations

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00226165; The ATLAS collaboration

    2018-01-01

    The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. To improve the physics potential reach in ATLAS, during the LHC shutdown after Run 1, the Level-1 trigger system was upgraded at hardware, firmware and software level. In particular, a new electronics sub-system was introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. For individual blades, real-time information from calorimeter and muon Level-1 trigger systems, is processed by four individual state-of-the-art FPGAs. It needs to deal with a large input bandwidth of up to 6 Tb/s, optical connectivity and low processing latency on the real-time data path. The L1Topo firmware apply measurements of angles between jets and/or leptons and several...

  18. Hardware Removal in Craniomaxillofacial Trauma: A Systematic Review of the Literature and Management Algorithm.

    Science.gov (United States)

    Cahill, Thomas J; Gandhi, Rikesh; Allori, Alexander C; Marcus, Jeffrey R; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T; Levinson, Howard

    2015-11-01

    Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article's reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases, there was no report as to hardware

  19. Metaphorical descriptions of wrongdoers

    Directory of Open Access Journals (Sweden)

    Dryll Ewa Marta

    2017-10-01

    Full Text Available What is a metaphoric picture of an evil person made of? In a study devoted to the development of the ability to use metaphorical descriptions of humans, the semantic fields of four target metaphors - Human-Swamp, Human-Snake, Human-Knife, and Human-Nettle - were established and compared. Subjects (365 young adults were asked to decipher the metaphors’ meanings. The results were obtained mainly by qualitative analysis, with frequency analysis of clusters containing synonymous meanings. The results indicate that when creating imaginary characteristics of evil people, young adults seem to be more concerned about the possibility of suffering verbal harassment (most commonly: vulgarity, mockery, gossip, jeering than the threat of actual physical assault. The results may prove useful for developmental comparisons.

  20. From description to prescription

    DEFF Research Database (Denmark)

    McQuaid, Sara Dybris

    with official policy documents makes for an interesting intertextual site of conflict interpretation and the dis/connections between these discourses in approaching diversity. Through an analysis of three seminal works which categorises theoretical interpretations of the conflict (Lijphart: The Northern Ireland......From Description to Prescription: Politics of Recognition, Consociational Theory and the Conflict in Northern Ireland. Within academic discourses on Northern Ireland the politics of recognition and particularly the theory of consociational democracy has made a profound impact. First introduced...... Problem: cases, theories and solutions (1975); Whyte: Interpreting Northern Ireland (1990); McGarry and O’Leary Explaining Northern Ireland (1995)), the paper will trace the historical development of intellectual understandings of the conflict as well as the propelling of consociational theory to its...

  1. Task Description Language

    Science.gov (United States)

    Simmons, Reid; Apfelbaum, David

    2005-01-01

    Task Description Language (TDL) is an extension of the C++ programming language that enables programmers to quickly and easily write complex, concurrent computer programs for controlling real-time autonomous systems, including robots and spacecraft. TDL is based on earlier work (circa 1984 through 1989) on the Task Control Architecture (TCA). TDL provides syntactic support for hierarchical task-level control functions, including task decomposition, synchronization, execution monitoring, and exception handling. A Java-language-based compiler transforms TDL programs into pure C++ code that includes calls to a platform-independent task-control-management (TCM) library. TDL has been used to control and coordinate multiple heterogeneous robots in projects sponsored by NASA and the Defense Advanced Research Projects Agency (DARPA). It has also been used in Brazil to control an autonomous airship and in Canada to control a robotic manipulator.

  2. YUCCA MOUNTAIN SITE DESCRIPTION

    Energy Technology Data Exchange (ETDEWEB)

    A.M. Simmons

    2004-04-16

    The ''Yucca Mountain Site Description'' summarizes, in a single document, the current state of knowledge and understanding of the natural system at Yucca Mountain. It describes the geology; geochemistry; past, present, and projected future climate; regional hydrologic system; and flow and transport within the unsaturated and saturated zones at the site. In addition, it discusses factors affecting radionuclide transport, the effect of thermal loading on the natural system, and tectonic hazards. The ''Yucca Mountain Site Description'' is broad in nature. It summarizes investigations carried out as part of the Yucca Mountain Project since 1988, but it also includes work done at the site in earlier years, as well as studies performed by others. The document has been prepared under the Office of Civilian Radioactive Waste Management quality assurance program for the Yucca Mountain Project. Yucca Mountain is located in Nye County in southern Nevada. The site lies in the north-central part of the Basin and Range physiographic province, within the northernmost subprovince commonly referred to as the Great Basin. The basin and range physiography reflects the extensional tectonic regime that has affected the region during the middle and late Cenozoic Era. Yucca Mountain was initially selected for characterization, in part, because of its thick unsaturated zone, its arid to semiarid climate, and the existence of a rock type that would support excavation of stable openings. In 1987, the United States Congress directed that Yucca Mountain be the only site characterized to evaluate its suitability for development of a geologic repository for high-level radioactive waste and spent nuclear fuel.

  3. Use of CCSDS Packets Over SpaceWire to Control Hardware

    Science.gov (United States)

    Haddad, Omar; Blau, Michael; Haghani, Noosha; Yuknis, William; Albaijes, Dennis

    2012-01-01

    For the Lunar Reconnaissance Orbiter, the Command and Data Handling subsystem consisted of several electronic hardware assemblies that were connected with SpaceWire serial links. Electronic hardware would be commanded/controlled and telemetry data was obtained using the SpaceWire links. Prior art focused on parallel data buses and other types of serial buses, which were not compatible with the SpaceWire and the core flight executive (CFE) software bus. This innovation applies to anything that utilizes both SpaceWire networks and the CFE software. The CCSDS (Consultative Committee for Space Data Systems) packet contains predetermined values in its payload fields that electronic hardware attached at the terminus of the SpaceWire node would decode, interpret, and execute. The hardware s interpretation of the packet data would enable the hardware to change its state/configuration (command) or generate status (telemetry). The primary purpose is to provide an interface that is compatible with the hardware and the CFE software bus. By specifying the format of the CCSDS packet, it is possible to specify how the resulting hardware is to be built (in terms of digital logic) that results in a hardware design that can be controlled by the CFE software bus in the final application

  4. Round Girls in Square Computers: Feminist Perspectives on the Aesthetics of Computer Hardware.

    Science.gov (United States)

    Carr-Chellman, Alison A.; Marra, Rose M.; Roberts, Shari L.

    2002-01-01

    Considers issues related to computer hardware, aesthetics, and gender. Explores how gender has influenced the design of computer hardware and how these gender-driven aesthetics may have worked to maintain, extend, or alter gender distinctions, roles, and stereotypes; discusses masculine media representations; and presents an alternative model.…

  5. Hardware Realization of an FPGA Processor - Operating System Call Offload and Experiences

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Karlsson, Sven

    2014-01-01

    on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor...

  6. A Unified Component Modeling Approach for Performance Estimation in Hardware/Software Codesign

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Madsen, Jan

    1998-01-01

    This paper presents an approach for abstract modeling of hardware/software architectures using Hierarchical Colored Petri Nets. The approach is able to capture complex behavioral characteristics often seen in software and hardware architectures, thus it is suitable for high level codesign issues...

  7. [Software and hardware design for the temperature control system of quantitative polymerase chain reaction].

    Science.gov (United States)

    Qiu, Xian-bo; Yuan, Jing-qi; Li, Qi

    2005-07-01

    A temperature control system for quantitive polymerase chain reaction (PCR) is presented in the paper with both software and hardware configuration. The performance of the control system has been improved by optimizing the software and hardware design according to the system's properties. The control system has been proven to have a good repeatability and reliability as well as high control precision.

  8. The priority queue as an example of hardware/software codesign

    DEFF Research Database (Denmark)

    Høeg, Flemming; Mellergaard, Niels; Staunstrup, Jørgen

    1994-01-01

    The paper identifies a number of issues that are believed to be important for hardware/software codesign. The issues are illustrated by a small comprehensible example: a priority queue. Based on simulations of a real application, we suggest a combined hardware/software realization of the priority...

  9. Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks

    DEFF Research Database (Denmark)

    Bogdanov, Andrey; Kavun, Elif Bilge; Tischhauser, Elmar

    2012-01-01

    in a vast range of parameters. The new hardware architecture allows us to verify the existing theoretical models for the complexity estimation in linear cryptanalysis. The designed hardware architecture is realized on two Xilinx Virtex-6 XC6VLX240T FPGAs for smaller block lengths, and on RIVYERA platform...... with 128 Xilinx Spartan-3 XC3S5000 FPGAs for larger block lengths....

  10. FSL-based Hardware Implementation for Parallel Computation of cDNA Microarray Image Segmentation

    OpenAIRE

    Bogdan Bot; Simina Emerich; Sorin Martoiu; Bogdan Belean

    2015-01-01

    The present paper proposes a FPGA based hardware implementations for microarray image processing algorithms in order eliminate the shortcomings of the existing software platforms: user intervention, increased computation time and cost. The proposed image processing algorithms exclude user intervention from processing. An application-specific architecture is designed aiming microarray image processing algorithms parallelization in order to speed up computation. Hardware architectures for logar...

  11. Rapid Non-Cartesian Parallel Imaging Reconstruction on Commodity Graphics Hardware

    DEFF Research Database (Denmark)

    Sørensen, Thomas Sangild; Atkinson, David; Boubertakh, Redha

    2008-01-01

    This presentation describes an implementation of non-Cartesian SENSE and kt-SENSE accelerated on commodity graphics hardware. This inexpensive hardware platform is now fully programmable and very suited for solving reconstruction problems. We show that for both SENSE and kt-SENSE the reconstruction...

  12. A Model-Driven Framework for Hardware-Software Co-design of Dataflow Applications

    NARCIS (Netherlands)

    Berger, Christian; Ahmad, W.; Yildiz, Bugra Mehmet; Reza Mousavi, Mohammad; Rensink, Arend; Wisniewski, Rafael; Stoelinga, Mariëlle Ida Antoinette

    2017-01-01

    Hardware-software (HW-SW) co-design allows to meet system-level objectives by exploiting the synergy of hardware and software. Current tools and approaches for HW-SW co-design face difficulties coping with the increasing complexity of modern-day application due to, e.g., concurrency and energy

  13. Hardware Technology for Computers in Education: One of the Soluble Problems.

    Science.gov (United States)

    Seidel, R. J.

    The state-of-the-art of hardware technology for computers in education is discussed. The choices that are available to the user, and the questions the user must ask himself before making a choice of computer hardware, are explored. An example of the costs of a central computer system for educational use is presented. (Author)

  14. A new hardware-efficient algorithm and reconfigurable architecture for image contrast enhancement.

    Science.gov (United States)

    Huang, Shih-Chia; Chen, Wen-Chieh

    2014-10-01

    Contrast enhancement is crucial when generating high quality images for image processing applications, such as digital image or video photography, liquid crystal display processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyzes. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 frames/s at high definition resolution 1920 × 1080.

  15. Alternative, Green Processes for the Precision Cleaning of Aerospace Hardware

    Science.gov (United States)

    Maloney, Phillip R.; Grandelli, Heather Eilenfield; Devor, Robert; Hintze, Paul E.; Loftin, Kathleen B.; Tomlin, Douglas J.

    2014-01-01

    Precision cleaning is necessary to ensure the proper functioning of aerospace hardware, particularly those systems that come in contact with liquid oxygen or hypergolic fuels. Components that have not been cleaned to the appropriate levels may experience problems ranging from impaired performance to catastrophic failure. Traditionally, this has been achieved using various halogenated solvents. However, as information on the toxicological and/or environmental impacts of each came to light, they were subsequently regulated out of use. The solvent currently used in Kennedy Space Center (KSC) precision cleaning operations is Vertrel MCA. Environmental sampling at KSC indicates that continued use of this or similar solvents may lead to high remediation costs that must be borne by the Program for years to come. In response to this problem, the Green Solvents Project seeks to develop state-of-the-art, green technologies designed to meet KSCs precision cleaning needs.Initially, 23 solvents were identified as potential replacements for the current Vertrel MCA-based process. Highly halogenated solvents were deliberately omitted since historical precedents indicate that as the long-term consequences of these solvents become known, they will eventually be regulated out of practical use, often with significant financial burdens for the user. Three solvent-less cleaning processes (plasma, supercritical carbon dioxide, and carbon dioxide snow) were also chosen since they produce essentially no waste stream. Next, experimental and analytical procedures were developed to compare the relative effectiveness of these solvents and technologies to the current KSC standard of Vertrel MCA. Individually numbered Swagelok fittings were used to represent the hardware in the cleaning process. First, the fittings were cleaned using Vertrel MCA in order to determine their true cleaned mass. Next, the fittings were dipped into stock solutions of five commonly encountered contaminants and were

  16. RESEARCH PROGRESS AND HARDWARE SYSTEMS AT DIII-D

    Energy Technology Data Exchange (ETDEWEB)

    PETERSEN,P.I; THE DIII-D TEAM

    2003-10-01

    OAK-B135 During the last two years significant progress has been made in the scientific understanding of DIII-D plasmas. Much of this progress has been enabled by the addition of new hardware systems. The electron cyclotron (EC) system has been upgraded from 3 MW to 6 MW, by adding three 1 MW gyrotrons with diamond windows and three steerable launchers (PPPL). The new gyrotrons have been tested to 1.0 MW for 5 s. The system has been used to control the 3/2 and 2/1 neoclassical tearing modes and to locally heat the plasma and thereby indirectly control the current density. Electron cyclotron current drive ECCD has been used to directly affect the current density. A Li-beam diagnostic has been brought on-line for measuring the edge current density using Zeeman splitting. A set of 12 coils (1-coils), consisting of six picture frame coils each above and below the midplane, with a capability of 7 kA for 10 s has been installed inside the DIII-D vessel. These coils, along with the existing six C-coils, are used to apply non-axisymmetric fields to the plasma for both exciting and controlling plasma instabilities. The DIII-D digital plasma control system is now used to not just control the shape and location of the plasma but also the electron temperature, density, the NTMs, RWMs, plasma beta and disruption mitigation. Plasma disruption experiments are extended to mitigation of real time detected disruptions on DIII-D.

  17. Implementing the lattice Boltzmann model on commodity graphics hardware

    Science.gov (United States)

    Kaufman, Arie; Fan, Zhe; Petkov, Kaloian

    2009-06-01

    Modern graphics processing units (GPUs) can perform general-purpose computations in addition to the native specialized graphics operations. Due to the highly parallel nature of graphics processing, the GPU has evolved into a many-core coprocessor that supports high data parallelism. Its performance has been growing at a rate of squared Moore's law, and its peak floating point performance exceeds that of the CPU by an order of magnitude. Therefore, it is a viable platform for time-sensitive and computationally intensive applications. The lattice Boltzmann model (LBM) computations are carried out via linear operations at discrete lattice sites, which can be implemented efficiently using a GPU-based architecture. Our simulations produce results comparable to the CPU version while improving performance by an order of magnitude. We have demonstrated that the GPU is well suited for interactive simulations in many applications, including simulating fire, smoke, lightweight objects in wind, jellyfish swimming in water, and heat shimmering and mirage (using the hybrid thermal LBM). We further advocate the use of a GPU cluster for large scale LBM simulations and for high performance computing. The Stony Brook Visual Computing Cluster has been the platform for several applications, including simulations of real-time plume dispersion in complex urban environments and thermal fluid dynamics in a pressurized water reactor. Major GPU vendors have been targeting the high performance computing market with GPU hardware implementations. Software toolkits such as NVIDIA CUDA provide a convenient development platform that abstracts the GPU and allows access to its underlying stream computing architecture. However, software programming for a GPU cluster remains a challenging task. We have therefore developed the Zippy framework to simplify GPU cluster programming. Zippy is based on global arrays combined with the stream programming model and it hides the low-level details of the

  18. Hardware architecture design of a fast global motion estimation method

    Science.gov (United States)

    Liang, Chaobing; Sang, Hongshi; Shen, Xubang

    2015-12-01

    VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

  19. Industrial hardware and software verification with ACL2.

    Science.gov (United States)

    Hunt, Warren A; Kaufmann, Matt; Moore, J Strother; Slobodova, Anna

    2017-10-13

    The ACL2 theorem prover has seen sustained industrial use since the mid-1990s. Companies that have used ACL2 regularly include AMD, Centaur Technology, IBM, Intel, Kestrel Institute, Motorola/Freescale, Oracle and Rockwell Collins. This paper introduces ACL2 and focuses on how and why ACL2 is used in industry. ACL2 is well-suited to its industrial application to numerous software and hardware systems, because it is an integrated programming/proof environment supporting a subset of the ANSI standard Common Lisp programming language. As a programming language ACL2 permits the coding of efficient and robust programs; as a prover ACL2 can be fully automatic but provides many features permitting domain-specific human-supplied guidance at various levels of abstraction. ACL2 specifications and models often serve as efficient execution engines for the modelled artefacts while permitting formal analysis and proof of properties. Crucially, ACL2 also provides support for the development and verification of other formal analysis tools. However, ACL2 did not find its way into industrial use merely because of its technical features. The core ACL2 user/development community has a shared vision of making mechanized verification routine when appropriate and has been committed to this vision for the quarter century since the Computational Logic, Inc., Verified Stack. The community has focused on demonstrating the viability of the tool by taking on industrial projects (often at the expense of not being able to publish much).This article is part of the themed issue 'Verified trustworthy software systems'. © 2017 The Author(s).

  20. Hardware Design and Implementation of Fixed-Width Standard and Truncated 4×4, 6×6, 8×8 and 12×12-BIT Multipliers Using Fpga

    Science.gov (United States)

    Rais, Muhammad H.

    2010-06-01

    This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT). Remarkable reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The truncated multipliers show significant improvement as compared to standard multipliers. Results show that the anomaly in Spartan-3 AN average connection and maximum pin delay have been efficiently reduced in Virtex-4 device.

  1. A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

    Science.gov (United States)

    Zhang, Xiangyu; An, Fengwei; Nakashima, Ikki; Luo, Aiwen; Chen, Lei; Ishii, Idaku; Jürgen Mattausch, Hans

    2017-04-01

    A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

  2. Treatment of subtrochanteric nonunion of the femur: whether to leave or to exchange the previous hardware.

    Science.gov (United States)

    Kang, Soo Hwan; Han, Suk Ku; Kim, Yong Sik; Kim, Myung Jin

    2013-01-01

    Our aim was to compare the clinical results of two different methods for treatment of subtrochanteric nonunion: an additional fixation to the previous hardware, and exchange of previous hardware. We retrospectively analyzed 19 cases of subtrochanteric nonunion, and compared clinical results from 10 cases (Group 1) with exchange of the previous hardware, and 9 cases (Group 2) with retained previous hardware and an additional fixation. Autogenous bone grafting were performed for all cases. The mean age of the patients was 49.1 years in Group 1, and 48.2 years in Group 2. The mean follow-up period was 19.3 months. The union rate was 100% in Group 1, and 77.8% in Group 2 (phardware was better than in those with retained hardware in the treatment of subtrochanteric nonunion by complete removal of the interposed fibrous tissue and meticulous bone grafting leading to a biological environment to achieve bony union.

  3. The reconstructive management of hardware-related scalp erosion in deep brain stimulation for Parkinson disease.

    Science.gov (United States)

    Gómez, Raúl; Hontanilla, Bernardo

    2014-09-01

    The presence of foreign material in deep brain stimulation is a risk factor for infection, and hardware-related pressure under the scalp may cause skin erosion. The aim of this article is to present our experience in the coverage of scalp in relation to underlying hardware. We analyzed 21 patients with Parkinson disease who had undergone deep brain stimulation surgery and developed scalp erosion with hardware exposition during follow-up. Nine patients were programmed for a scalp rotation flap, whereas free tisue transfer was performed in the rest of the patients. Minimum follow-up was 2 years. A hardware-related ulcer appeared in 5 of 9 rotation flap patients. No ulceration or major complications were observed in free flap patients. Free flaps are probably the best option for stable coverage in hardware-related scalp erosion with a high rate of success.

  4. LIDAR TS for ITER core plasma. Part I: layout & hardware

    Science.gov (United States)

    Salzmann, H.; Gowers, C.; Nielsen, P.

    2017-12-01

    The original time-of-flight design of the Thomson scattering diagnostic for the ITER core plasma has been shown up by ITER. This decision was justified by insufficiencies of some of the components. In this paper we show that with available, present day technology a LIDAR TS system is feasible which meets all the ITER specifications. As opposed to the conventional TS system the LIDAR TS also measures the high field side of the plasma. The optical layout of the front end has been changed only little in comparison with the latest one considered by ITER. The main change is that it offers an optical collection without any vignetting over the low field side. The throughput of the system is defined only by the size and the angle of acceptance of the detectors. This, in combination with the fact that the LIDAR system uses only one set of spectral channels for the whole line of sight, means that no absolute calibration using Raman or Rayleigh scattering from a non-hydrogen isotope gas fill of the vessel is needed. Alignment of the system is easy since the collection optics view the footprint of the laser on the inner wall. In the described design we use, simultaneously, two different wavelength pulses from a Nd:YAG laser system. Its fundamental wavelength ensures measurements of 2 keV up to more than 40 keV, whereas the injection of the second harmonic enables measurements of low temperatures. As it is the purpose of this paper to show the technological feasibility of the LIDAR system, the hardware is considered in Part I of the paper. In Part II we demonstrate by numerical simulations that the accuracy of the measurements as required by ITER is maintained throughout the given plasma parameter range. The effect of enhanced background radiation in the wavelength range 400 nm–500 nm is considered. In Part III the recovery of calibration in case of changing spectral transmission of the front end is treated. We also investigate how to improve the spatial resolution at the

  5. Current status of plasma emission electronics: II. Hardware

    Science.gov (United States)

    Bugaev, A. S.; Vizir, A. V.; Gushenets, V. I.; Nikolaev, A. G.; Oks, E. M.; Yushkov, G. Yu.; Burachevsky, Yu. A.; Burdovitsin, V. A.; Osipov, I. V.; Rempe, N. G.

    2003-04-01

    This paper is devoted to the engineering embodiment of the modern methods for producing charged ion and electron beams by extracting them from the plasma of a discharge. Electron beams use to execute electron-beam welding, annealing, and surface heating of materials and to realize plasmochemical reactions stimulated by fast electrons. Ion beams allow realization of technologies of ion implantation or ion-assisted deposition of coatings thereby opening new prospects for the creation of compounds and alloys by the method that makes it possible to obtain desired parameters and functional properties of the surface. A detailed description is given to the performance and design of devices producing beams of this type: the ion and electron sources being developed at the laboratory of plasma sources of the Institute of High-Current Electronics of the Russian Academy of Sciences and the laboratory of plasma electronics of Tomsk State University of Control Systems and Radioelectronics.

  6. Cell-based hardware architecture for full-parallel generation algorithm of digital holograms.

    Science.gov (United States)

    Seo, Young-Ho; Choi, Hyun-Jun; Yoo, Ji-Sang; Kim, Dong-Wook

    2011-04-25

    This paper proposes a new hardware architecture to speed-up the digital hologram calculation by parallel computation. To realize it, we modify the computer-generated hologram (CGH) equation and propose a cell-based very large scale integrated circuit architecture. We induce a new equation to calculate the horizontal or vertical hologram pixel values in parallel, after finding the calculation regularity in the horizontal or vertical direction from the basic CGH equation. We also propose the architecture of the computer-generated hologram cell consisting of an initial parameter calculator and update-phase calculators based on the equation, and then implement them in hardware. Modifying the equation could simplify the hardware, and approximating the cosine function could optimize the hardware. In addition, we show the hardware architecture to parallelize the calculation in the horizontal direction by extending computer-generated holograms. In the experiments, we analyze hardware resource usage and the performance-capability characteristics of the look-up table used in the computer-generated hologram cell. These analyses make it possible to select the amount of hardware to the precision of the results. Here, we used the platform from our previous work for the computer-generated hologram kernel and the structure of the processor.

  7. Software-Controlled Dynamically Swappable Hardware Design in Partially Reconfigurable Systems

    Directory of Open Access Journals (Sweden)

    Huang Chun-Hsian

    2008-01-01

    Full Text Available Abstract We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.

  8. New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

    Directory of Open Access Journals (Sweden)

    Ikbel Belaid

    2010-01-01

    Full Text Available Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for efficient management of hardware tasks and hardware resources. The scheduling of hardware tasks is highly dependent on placement. Placement focuses on allocation of hardware resources required by the scheduled hardware tasks. In this paper, we propose novel three-level resource management that investigates enhancement of placement quality by reducing task rejection, configuration overheads, and by optimizing resource utilization. Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA. Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method. The obtained results of an application of heterogeneous hardware tasks show an average resource utilization of 36% of the available resources on the reconfigurable region and an overall overhead of 11% of total application running time, and we have eliminated the issue of task rejection. Compared to static implementation, the gain in resource utilization within the reconfigurable region achieves up to 43%.

  9. Arthroscopy combined with hardware removal for chronic pain after ankle fracture.

    Science.gov (United States)

    Kim, Hyong-Nyun; Park, Yoo-Jung; Kim, Gab-Lae; Park, Yong-Wook

    2013-06-01

    The purpose of this study was to evaluate the effectiveness of arthroscopy combined with hardware removal for chronic pain after satisfactory healing of an ankle fracture. We hypothesized that combining hardware removal with arthroscopy for the intra-articular pathology would improve residual complaints more so than hardware removal alone. The outcomes of the 53 young male patients with chronic pain after healed ankle fracture treated with two different therapeutic plans: (1) conservative treatment after hardware removal (group A) and (2) arthroscopic intervention with hardware removal (group B) were prospectively studied. Patients were reviewed preoperatively and 6 and 12 months postoperatively using American Foot and Ankle Society (AOFAS) scale. Median AOFAS scores improved from 74 (66-80) points to 76 (73-92) points in group A and from 75 (64-80) points to 85 (72-100) points in group B, and this improvement was significantly higher for patients in group B (p = 0.001). This study supports the notion that when there is a definite diagnosis such as loose body, bony impingement, or anterolateral soft-tissue impingement causing chronic pain after healed ankle fracture, arthroscopic treatment with hardware removal is a better treatment option than hardware removal and conservative treatment.

  10. Hardware Removal Due to Infection after Open Reduction and Internal Fixation: Trends and Predictors.

    Science.gov (United States)

    Rasouli, Mohammad R; Viola, Jessica; Maltenfort, Mitchell G; Shahi, Alisina; Parvizi, Javad; Krieg, James C

    2015-07-01

    Little is known about trends and predictors of hardware related infection following open reduction and internal fixation (ORIF) of extremity fractures, one of the major causes of failure following ORIF. The present study was designed and conducted to determine trends and predictors of infection-related hardware removal following ORIF of extremities using a nationally representative database. We used Nationwide Inpatient Sample data from 2002 to 2011 to identify cases of ORIF following upper and lower extremity fractures, as well as cases that underwent infection-related hardware removal following ORIF. Multivariate analysis was performed to identify independent predictors of infection-related hardware removal, controlling for patient demographics and comorbidities, hospital characteristics, site of fracture, and year. For all ORIF procedures, the highest rate of hardware removal related to infection was observed in tarsal fractures (5.56%), followed by tibial (3.65%) and carpal (3.37%) fractures. Hardware removal rates due to infection increased in all fractures except radial/ulnar fractures. Tarsal fractures(odds ratio (OR)=1.06, 95% confidence interval (CI): 1.04-1.09, PHardware removal rates due to infection increased in all fractures except radial/ulnar fractures. Diabetes, liver disease, and rheumatoid arthritis were important predictors of infection-related hardware removal. The study identified some risk factors for hardwarerelated infection following ORIF, such as diabetes, liver disease, and rheumatoid arthritis, that should be studied further in an attempt to implement strategies to reduce rate of infection following ORIF.

  11. No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

    Science.gov (United States)

    Zaghloul, A. R. M.; Zaghloul, Y. A.

    2014-06-01

    We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

  12. Desenvolvimento de hardware reconfigurável de criptografia assimétrica

    OpenAIRE

    Otávio Souza Martins Gomes; João Paulo Fernandes de Cerqueira César

    2015-01-01

    Este artigo apresenta o resultado parcial do desenvolvimento de uma interface de hardware reconfigurável para criptografia assimétrica que permite a troca segura de dados. Hardwares reconfiguráveis permitem o desenvolvimento deste tipo de dispositivo com segurança e flexibilidade e possibilitam a mudança de características no projeto com baixo custo e de forma rápida.Palavras-chave: Criptografia. Hardware. ElGamal. FPGA. Segurança. Development of an asymmetric cryptography reconfigurable harw...

  13. MLAA-based attenuation correction of flexible hardware components in hybrid PET/MR imaging.

    Science.gov (United States)

    Heußer, Thorsten; Rank, Christopher M; Berker, Yannick; Freitag, Martin T; Kachelrieß, Marc

    2017-12-01

    Accurate PET quantification demands attenuation correction (AC) for both patient and hardware attenuation of the 511 keV annihilation photons. In hybrid PET/MR imaging, AC for stationary hardware components such as patient table and MR head coil is straightforward, employing CT-derived attenuation templates. AC for flexible hardware components such as MR-safe headphones and MR radiofrequency (RF) surface coils is more challenging. Registration-based approaches, aligning CT-based attenuation templates with the current patient position, have been proposed but are not used in clinical routine. Ignoring headphone or RF coil attenuation has been shown to result in regional activity underestimation values of up to 18%. We propose to employ the maximum-likelihood reconstruction of attenuation and activity (MLAA) algorithm to estimate the attenuation of flexible hardware components. Starting with an initial attenuation map not including flexible hardware components, the attenuation update of MLAA is applied outside the body outline only, allowing to estimate hardware attenuation without modifying the patient attenuation map. Appropriate prior expectations on the attenuation coefficients are incorporated into MLAA. The proposed method is investigated for non-TOF PET phantom and 18F-FDG patient data acquired with a clinical PET/MR device, using headphones or RF surface coils as flexible hardware components. Although MLAA cannot recover the exact physical shape of the hardware attenuation maps, the overall attenuation of the hardware components is accurately estimated. Therefore, the proposed algorithm significantly improves PET quantification. Using the phantom data, local activity underestimation when neglecting hardware attenuation was reduced from up to 25% to less than 3% under- or overestimation as compared to reference scans without hardware present or to CT-derived AC. For the patient data, we found an average activity underestimation of 7.9% evaluated in the full

  14. The technology of electromagnetic radiation danger estimation using the hardware-software module

    Directory of Open Access Journals (Sweden)

    Titov Eugene

    2017-01-01

    Full Text Available The article describes the principles of functioning of the hardware-software module, whose purpose is the estimation of a danger level of the combined electromagnetic field influence on a human organism. The module consists of the hardware and the software parts. The hardware part is an array of electromagnetic parameter detectors; the software part is an electromagnetic field modelling program based on OpenEMS. The module creates so-called images of electromagnetic environment danger. The results show practical applicability of the technological module for the stated purpose.

  15. Preparing the hardware of the CMS Electromagnetic Calorimeter control and safety systems for LHC Run 2

    CERN Document Server

    AUTHOR|(CDS)2068025; Di Calafiori, D.; Cirkovic, P.; Dissertori, G.; Djambazov, L.; Jovanovic, D.; Lustermann, W.; Zelepoukine, S.

    2016-01-01

    The Detector Control System of the CMS Electromagnetic Calorimeter has undergone significant improvements during the first LHC Long Shutdown. Based on the experience acquired during the first period of physics data taking of the LHC, several hardware projects were carried out to improve data accuracy, to minimise the impact of failures and to extend remote control possibilities in order to accelerate recovery from problematic situations. This paper outlines the hardware of the detector control and safety systems and explains in detail the requirements, design and commissioning of the new hardware projects.

  16. Beyond Open Source Software: Solving Common Library Problems Using the Open Source Hardware Arduino Platform

    Directory of Open Access Journals (Sweden)

    Jonathan Younker

    2013-06-01

    Full Text Available Using open source hardware platforms like the Arduino, libraries have the ability to quickly and inexpensively prototype custom hardware solutions to common library problems. The authors present the Arduino environment, what it is, what it does, and how it was used at the James A. Gibson Library at Brock University to create a production portable barcode-scanning utility for in-house use statistics collection as well as a prototype for a service desk statistics tabulation program’s hardware interface.

  17. An interactive audio-visual installation using ubiquitous hardware and web-based software deployment

    Directory of Open Access Journals (Sweden)

    Tiago Fernandes Tavares

    2015-05-01

    Full Text Available This paper describes an interactive audio-visual musical installation, namely MOTUS, that aims at being deployed using low-cost hardware and software. This was achieved by writing the software as a web application and using only hardware pieces that are built-in most modern personal computers. This scenario implies in specific technical restrictions, which leads to solutions combining both technical and artistic aspects of the installation. The resulting system is versatile and can be freely used from any computer with Internet access. Spontaneous feedback from the audience has shown that the provided experience is interesting and engaging, regardless of the use of minimal hardware.

  18. Pictorial Review and Basic Principles of Foot and Ankle Hardware Extraction.

    Science.gov (United States)

    Wagoner, Matthew R; Creech, Corine L; Nolan, Christine K; Meyr, Andrew J

    2015-08-01

    This pictorial review presents basic principles of the types of hardware extraction commonly encountered in foot and ankle surgical practice. We review the indications, contraindications and complications of hardware removal including pain, intra-articular fixation, and carcinogenesis, as well as special considerations in pediatric patients and in the setting of infection. Figures are then used to describe the appropriate techniques for use of the screwdriver shafts, conical extraction screws, extraction bolts, hollow reamers, and other instruments found in most hardware extraction sets. Therapeutic, Level V: Expert opinion. © 2015 The Author(s).

  19. Descriptive approaches to landscape analysis

    Science.gov (United States)

    R. Burton Litton Jr.

    1979-01-01

    Descriptive landscape analyses include various procedures used to document visual/scenic resources. Historic and regional examples of landscape description represent desirable insight for contemporary professional inventory work. Routed and areal landscape inventories are discussed as basic tools. From them, qualitative and quantitative evaluations can be developed...

  20. Design and implementation of embedded hardware accelerator for diagnosing HDL-CODE in assertion-based verification environment

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2013-08-01

    Full Text Available The use of assertions for monitoring the designer’s intention in hardware description language (HDL model is gaining popularity as it helps the designer to observe internal errors at the output ports of the device under verification. During verification assertions are synthesised and the generated data are represented in a tabular forms. The amount of data generated can be enormous depending on the size of the code and the number of modules that constitute the code. Furthermore, to manually inspect these data and diagnose the module with functional violation is a time consuming process which negatively affects the overall product development time. To locate the module with functional violation within acceptable diagnostic time, the data processing and analysis procedure must be accelerated. In this paper a multi-array processor (hardware accelerator was designed and implemented in Virtex6 field programmable gate array (FPGA and it can be integrated into verification environment. The design was captured in very high speed integrated circuit HDL (VHDL. The design was synthesised with Xilinx design suite ISE 13.1 and simulated with Xilinx ISIM. The multi-array processor (MAP executes three logical operations (AND, OR, XOR and a one’s compaction operation on array of data in parallel. An improvement in processing and analysis time was recorded as compared to the manual procedure after the multi-array processor was integrated into the verification environment. It was also found that the multi-array processor which was developed as an Intellectual Property (IP core can also be used in applications where output responses and golden model that are represented in the form of matrices can be compared for searching, recognition and decision-making.

  1. A probability-based approach for assessment of roadway safety hardware.

    Science.gov (United States)

    2017-03-14

    This report presents a general probability-based approach for assessment of roadway safety hardware (RSH). It was achieved using a reliability : analysis method and computational techniques. With the development of high-fidelity finite element (FE) m...

  2. Hardware in the loop simulation of arbitrary magnitude shaped correlated radar clutter

    CSIR Research Space (South Africa)

    Strydom, JJ

    2014-10-01

    Full Text Available This paper describes a simple process for the generation of arbitrary probability distributions of complex data with correlation from sample to sample, optimized for hardware in the loop radar environment simulation. Measured radar clutter is used...

  3. RADIATION RESISTANT LED POWER SUPPLY RELEASED UNDER CERN OPEN HARDWARE LICENSE

    CERN Multimedia

    2016-01-01

    As part of the design of a new emergency lighting system for the CERN accelerator complex a new design for a radiation resistant power supply has been produced. The design is available from the Open Hardware Repository.

  4. [Elamed CP-01 capnographic hardware-software system for general practitioners].

    Science.gov (United States)

    Bialovskiĭ, Iu Iu; Konobeeva, T N; Solomakha, V N

    2007-01-01

    The diagnostic capabilities of the Elamed CP-01 capnographic hardware-software system are described. Original engineering solutions and software of the system make it highly useful for general practitioners.

  5. Open source hardware and software platform for robotics and artificial intelligence applications

    Science.gov (United States)

    Liang, S. Ng; Tan, K. O.; Lai Clement, T. H.; Ng, S. K.; Mohammed, A. H. Ali; Mailah, Musa; Azhar Yussof, Wan; Hamedon, Zamzuri; Yussof, Zulkifli

    2016-02-01

    Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots.

  6. Object and Facial Recognition in Augmented and Virtual Reality: Investigation into Software, Hardware and Potential Uses

    Science.gov (United States)

    Schulte, Erin

    2017-01-01

    As augmented and virtual reality grows in popularity, and more researchers focus on its development, other fields of technology have grown in the hopes of integrating with the up-and-coming hardware currently on the market. Namely, there has been a focus on how to make an intuitive, hands-free human-computer interaction (HCI) utilizing AR and VR that allows users to control their technology with little to no physical interaction with hardware. Computer vision, which is utilized in devices such as the Microsoft Kinect, webcams and other similar hardware has shown potential in assisting with the development of a HCI system that requires next to no human interaction with computing hardware and software. Object and facial recognition are two subsets of computer vision, both of which can be applied to HCI systems in the fields of medicine, security, industrial development and other similar areas.

  7. Sonographic assessment of orthopedic hardware impingement on soft tissues of the limbs.

    Science.gov (United States)

    Guillin, R; Bianchi, S

    2012-02-01

    Ultrasonography allows high-resolution imaging with real-time correlation to patients' pain, and it is an indispensable tool for assessing disorders associated with soft tissue impingement by orthopedic hardware. The sonographic examination in these cases begins with static studies, and images are then obtained during active and passive joint mobilization designed to reproduce the conflict with the orthopedic hardware. Ultrasonography is particularly useful for documenting hardware-induced injury to tendons and synovial bursae, but also those of muscles and vascular structures. The frequency of hardware-soft tissue conflict varies with the site and type of surgical procedure, but in all cases ultrasonography plays an essential role in identifying this type of conflict and assessing the soft tissue lesions it causes.

  8. A photovoltaic source I/U model suitable for hardware in the loop application

    Directory of Open Access Journals (Sweden)

    Stala Robert

    2017-12-01

    Full Text Available This paper presents a novel, low-complexity method of simulating PV source characteristics suitable for real-time modeling and hardware implementation. The application of the suitable model of the PV source as well as the model of all the PV system components in a real-time hardware gives a safe, fast and low cost method of testing PV systems. The paper demonstrates the concept of the PV array model and the hardware implementation in FPGAs of the system which combines two PV arrays. The obtained results confirm that the proposed model is of low complexity and can be suitable for hardware in the loop (HIL tests of the complex PV system control, with various arrays operating under different conditions.

  9. 76 FR 11511 - In the Matter of Certain Set-Top Boxes, and Hardware and Software Components Thereof; Notice of...

    Science.gov (United States)

    2011-03-02

    ... COMMISSION In the Matter of Certain Set-Top Boxes, and Hardware and Software Components Thereof; Notice of... States after importation of certain set-top boxes, and hardware and software components thereof by reason... importation of certain set-top boxes, and hardware and software components thereof that infringe one or more...

  10. 75 FR 38129 - Freescale Semiconductor, Inc., Hardware/Software Design and Manufacturing A Including On-Site...

    Science.gov (United States)

    2010-07-01

    ... Employment and Training Administration Freescale Semiconductor, Inc., Hardware/Software Design and... Freescale Semiconductor, Inc., Hardware/Software Design and Manufacturing A, Austin, Texas. The notice was...., Hardware/ Software Design and Manufacturing A. The Department has determined that these workers were...

  11. 78 FR 18366 - Baldwin Hardware Corporation, a Subsidiary of Spectrum Brands, Formerly Known as a Subsidiary of...

    Science.gov (United States)

    2013-03-26

    ... Employment and Training Administration Baldwin Hardware Corporation, a Subsidiary of Spectrum Brands..., 2011, applicable to workers of Baldwin Hardware Corporation, a Subsidiary of Stanley Black & Decker..., Reading, Pennsylvania. The workers are engaged in the production of decorative hardware. The Notice was...

  12. 48 CFR 1812.7000 - Prohibition on guaranteed customer bases for new commercial space hardware or services.

    Science.gov (United States)

    2010-10-01

    ... customer bases for new commercial space hardware or services. 1812.7000 Section 1812.7000 Federal... PLANNING ACQUISITION OF COMMERCIAL ITEMS Commercial Space Hardware or Services 1812.7000 Prohibition on guaranteed customer bases for new commercial space hardware or services. Public Law 102-139, title III...

  13. Evaluation of GNU Radio Platform Enhanced for Hardware Accelerated Radio Design

    OpenAIRE

    Karve, Mrudula Prabhakar

    2010-01-01

    The advent of software radio technology has enabled radio developers to design and imple- ment radios with great ease and flexibility. Software radios are effective in experimentation and development of radio designs. However, they have limitations when it comes to high- speed, high-throughput designs. This limitation can be overcome by introducing a hardware element to the software radio platform. Enhancing GNU Radio for Hardware Accelerated Radio Design project implements suc...

  14. A new project to address run-time reconfigurable hardware systems

    OpenAIRE

    Torresen, Jim; Koch, Dirk

    2010-01-01

    Last autumn, we started a new project named Context Switching Reconfigurable Hardware for Communication Systems (COSRECOS). In this talk, I would like to present how we plan to address the challenge of changing hardware configurations while a system is in operation. The overall goal of the project is to contribute in making run-time reconfigurable systems more feasible in general. This includes introducing architectures for reducing reconfiguration time as well as undertaking tool develo...

  15. Hardware accelerator of convolution with exponential function for image processing applications

    Science.gov (United States)

    Panchenko, Ivan; Bucha, Victor

    2015-12-01

    In this paper we describe a Hardware Accelerator (HWA) for fast recursive approximation of separable convolution with exponential function. This filter can be used in many Image Processing (IP) applications, e.g. depth-dependent image blur, image enhancement and disparity estimation. We have adopted this filter RTL implementation to provide maximum throughput in constrains of required memory bandwidth and hardware resources to provide a power-efficient VLSI implementation.

  16. Principles for Soft-Hardware Complex Development to Increase Efficiency of Power Transformers

    Directory of Open Access Journals (Sweden)

    A. L. Trushnikov

    2007-01-01

    Full Text Available The paper reveals principles for development and operation of soft-hardware complex which is designed to control transformer substations of industrial enterprisers. Purpose of soft-hardware components of the complex is considered in the paper.Development and application of such complex allow to increase an efficiency of power transformer resource and decrease electric power losses in the elements of power-supply system at industrial enterprisers.

  17. A Framework for Assessing the Reusability of Hardware (Reusable Rocket Engines)

    Science.gov (United States)

    Childress-Thompson, Rhonda; Thomas, Dale; Farrington, Phillip

    2016-01-01

    Within the space flight community, reusability has taken center stage as the new buzzword. In order for reusable hardware to be competitive with its expendable counterpart, two major elements must be closely scrutinized. First, recovery and refurbishment costs must be lower than the development and acquisition costs. Additionally, the reliability for reused hardware must remain the same (or nearly the same) as "first use" hardware. Therefore, it is imperative that a systematic approach be established to enhance the development of reusable systems. However, before the decision can be made on whether it is more beneficial to reuse hardware or to replace it, the parameters that are needed to deem hardware worthy of reuse must be identified. For reusable hardware to be successful, the factors that must be considered are reliability (integrity, life, number of uses), operability (maintenance, accessibility), and cost (procurement, retrieval, refurbishment). These three factors are essential to the successful implementation of reusability while enabling the ability to meet performance goals. Past and present strategies and attempts at reuse within the space industry will be examined to identify important attributes of reusability that can be used to evaluate hardware when contemplating reusable versus expendable options. This paper will examine why reuse must be stated as an initial requirement rather than included as an afterthought in the final design. Late in the process, changes in the overall objective/purpose of components typically have adverse effects that potentially negate the benefits. A methodology for assessing the viability of reusing hardware will be presented by using the Space Shuttle Main Engine (SSME) to validate the approach. Because reliability, operability, and costs are key drivers in making this critical decision, they will be used to assess requirements for reuse as applied to components of the SSME.

  18. A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams

    Directory of Open Access Journals (Sweden)

    Christophe Bobda

    2006-10-01

    Full Text Available This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.

  19. A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams

    Directory of Open Access Journals (Sweden)

    Mühlbauer Felix

    2006-01-01

    Full Text Available This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.

  20. Software and Critical Technology Protection Against Side-Channel Analysis Through Dynamic Hardware Obfuscation

    Science.gov (United States)

    2011-03-01

    processors in smart cards, decryption keys for pay TV, lottery ticket vending machines, and mobile-phone systems. For all these crypto-processors...Connection to SCIO Bus. To connect these new math hardware units to the JOP hardware was done through the SimpCon Input/Output (SCIO) bus. A central... math ” driver was created and connected to the SCIO bus. This central driver allowed for one central point for the JVM to go to when performing math