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Sample records for very-large-scale integration vlsi

  1. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  2. Analog very large-scale integrated (VLSI) implementation of a model of amplitude-modulation sensitivity in the auditory brainstem.

    Science.gov (United States)

    van Schaik, A; Meddis, R

    1999-02-01

    An analog very large-scale integrated (VLSI) implementation of a model of signal processing in the auditory brainstem is presented and evaluated. The implementation is based on a model of amplitude-modulation sensitivity in the central nucleus of the inferior colliculus (CNIC) previously described by Hewitt and Meddis [J. Acoust. Soc. Am. 95, 2145-2159 (1994)]. A single chip is used to implement the three processing stages of the model; the inner-hair cell (IHC), cochlear nucleus sustained-chopper, and CNIC coincidence-detection stages. The chip incorporates two new circuits: an IHC circuit and a neuron circuit. The input to the chip is taken from a "silicon cochlea" consisting of a cascade of filters that simulate basilar membrane mechanical frequency selectivity. The chip which contains 142 neurons was evaluated using amplitude-modulated pure tones. Individual cells in the CNIC stage demonstrate bandpass rate-modulation responses using these stimuli. The frequency of modulation is represented spatially in an array of these cells as the location of the cell generating the highest rate of action potentials. The chip processes acoustic signals in real time and demonstrates the feasibility of using analog VLSI to build and test auditory models that use large numbers of component neurons.

  3. Piecewise Linear Approach for Timing Simulation of VLSI (Very-Large-Scale-Integrated) Circuits on Serial and Parallel Computers.

    Science.gov (United States)

    1987-12-01

    328 S % 33880E ° PIECEWISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS Ongky Tejayadi UNIVE,’RSITY OF ILL...APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS 12. PERSONAL AUTHOR(S) Tejayadi, Ongky 13a. TYPE OF REPO~Z J,..-13b...PIECE’WISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS BY ONGKY TEJAYADI B.S., University of Illinois

  4. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  5. Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design

    DEFF Research Database (Denmark)

    Araci, Ismail Emre; Pop, Paul; Chakrabarty, Krishnendu

    2015-01-01

    Microfluidic biochips are replacing the conventional biochemical analyzers by integrating all the necessary functions for biochemical analysis using microfluidics. Biochips are used in many application areas, such as, in vitro diagnostics, drug discovery, biotech and ecology. The focus of this pa......Microfluidic biochips are replacing the conventional biochemical analyzers by integrating all the necessary functions for biochemical analysis using microfluidics. Biochips are used in many application areas, such as, in vitro diagnostics, drug discovery, biotech and ecology. The focus...... of this paper is on continuous-flow biochips, where the basic building block is a microvalve. By combining these microvalves, more complex units such as mixers, switches, multiplexers can be built, hence the name of the technology, “microfluidic Very Large-Scale Integration” (mVLSI). A roadblock...... presents the state-of-the-art in the mVLSI platforms and emerging research challenges in the area of continuous-flow microfluidics, focusing on testing techniques and fault-tolerant design....

  6. VLSI (Very Large Scale Integrated Circuits) Device Reliability Models.

    Science.gov (United States)

    1984-12-01

    Arrhenius relationship is as follows; b=Ae ( -j Tr where . A normalization constant for a specific technology cea = equivalent activation energy (as a...ln(Xp) = nA - cea (l/KT) This relationship is shown for two different activation energies in Figure 6.1. The example depicted in...W.E., "Microcircuit Device Reliability: Memory/Digital LSI", RAC Publication MDR -18, Winter 1981/82. 16. MIL-HDBK-217D, Military Handbook

  7. Theoretical Aspects of VLSI (Very Large Scale Integration) Circuit Design.

    Science.gov (United States)

    1986-01-01

    Problems," J. Computer and System Sciences, Vol. 28, No. 2, April 1984, pp. 300-343. 4. T. Llui, S. Cliaudhuri, F.T. Leighton and N1. Sipser , "Graph...Formulas," Proc. 26th IEEL’ Symp. on Foundations of Computer Science, October 1985, pp. 20-29. *4. T. Bui, S. Chaudhuri, F.T. Leighton and i. Sipser ...Collections of hkter\\.l.," Pruc. 16th ACM Symposium on Theory of Computing, April 1984, pp. 167-174. 8. A. Goldberg and Ni. Sipser , "Compression and

  8. System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Very Large Scale Integration Biochips

    DEFF Research Database (Denmark)

    Minhass, Wajid Hassan

    -level details in electronic integrated circuits). Since mVLSI chips can easily have thousands of valves, the manual process can be very time-consuming, error-prone and result in inefficient designs and mappings. We propose, for the first time to our knowledge, a top-down modeling and synthesis methodology...... for the mVLSI biochips. We propose a modeling frame-work for the components and the biochip architecture. Using these models, we present an architectural synthesis methodology (covering steps from the schematic design to the physical synthesis), generating an application-specific mVLSI biochip. We also...... approaches using real-life case studies and synthetic benchmarks. The proposed framework is expected to facilitate programmability and automation, enabling the emergence of a large biochip market....

  9. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    Science.gov (United States)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  10. An Engineering Methodology for Implementing and Testing VLSI (Very Large Scale Integrated) Circuits

    Science.gov (United States)

    1989-03-01

    Test Facilities i 9-AMstract I cew. tue cen rcierse if tic cssarv aund idcn;ify bv- block nuotter I The engineernu2 methodology for producing a full...5n04 6. Profos, or 11. Loomis. Jr.. Code 621.mn Nava.l Pos tg-raduate School NI ontcre%. C. 3 4-5l Profesor NI. Cotton. C’ode 62CcI Na’. a

  11. A Fast Turn-Around Facility for Very Large Scale Integration (VLSI)

    Science.gov (United States)

    1981-07-01

    electron beam lithography system. We have selected the ETEC MEBES system for reasons which are detailed in the electron beam lithography section of this...report. Initially, the MEBES system will be used as a high quality mask generation system; however, we ultimately plan to use this system for directly...feature size of 1/8 micron. The MEBES system has been constructed and has successfully written patterns in resist at the ETEC factory in Hayward

  12. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    with eqntott, see PLA(5) for details. Tpla does not handle split and folded PLAs. Tpla is a program written with the Tpack system. STYLES OF PLAs...more options from Tpack (CAD). FlLVE cad/bin/tpla - executable cad/src/tpla/* - source cad/lib/tpla/po.ip -- standard templates for PLAs SE ALSO eqntott...CAD), presto(CAD), plasort(CAD), pla(CADS), tpla(CAD). tpack (CAD), mkpla(CAD) AUTHOR Robert N. Mayo BUGS The defaults for the -G and -S options have

  13. Automatic VLSI (Very Large Scale Integration) Routing Using 2-Layer Metal.

    Science.gov (United States)

    1983-12-01

    at / Adn ",vchan[i].center); exit( 1); c-> done = TRUE; /* this channel is ready to route 2/ int vtracks needed(i) mt i, /I channel index/ 9 FUNCTION...leftend.yloc; else if (vyloc arn Wi-> rightend.yloc) vxlocs wi-> leftendxloc; vyloc w1-> leftend.yloc; elme viloc a wi-> rightend.xloc; vyloc a wi

  14. VLSI (Very Large Scale Integrated Circuits) Design with the MacPitts Silicon Compiler.

    Science.gov (United States)

    1985-09-01

    fulfillment of the (. requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL September 1985... Electrical and Computer Engineering So ’ohfn7N. Dyer, Dean of Science and Engineering V0 ABSTRACT An analysis of the MacPitts silicon compiler is presented...size, and power comsumption . 4 K: Ui Ii Chapter VI is a design example. A design cycle for MacPitts is developed, and illustrated with the Hamming 15/4

  15. Extraction of MOS VLSI (Very-Large-Scale-Integrated) Circuit Models Including Critical Interconnect Parasitics.

    Science.gov (United States)

    1987-09-01

    147 REFERENCES .. . . . . . . . . . . . .12 VI A. . ....................... ............ .......... . ..... 157 VITA I CHAPI -ER 1. INTRODUCFION As the...the one proposed by Mori and Wilmore in [20] is studied. By applying this technique. we use analytical formulas fitted from numerical data rather than...artwork verification system." Digest of Technical Papers, ICCAD. pp. 266-268, 1984. [20] S. Mori and J. Wilmore, ’Resistance extraction in a hierarchical

  16. Computer Aided Fast Turnaround Laboratory for Research in VLSI (Very Large Scale Integrated).

    Science.gov (United States)

    1987-05-31

    PubliO relecsel D12?btuio IONSATits Principal Investigator: Project Leader: Professor James D. Meindl Dr. John Shott CIS 105 CIS 211 Stanford University...simulation. Much of this work has been performed under the leadership of Profs. R. WV. Dutton and J. D. Plummer under DARPA sponsorship. Significant...for the paper authored by D. Gardner, T. Michalka, K. Saraswat, J. McVittie, T. Barbee and J. Meindl . "Aluminum Alloys with Titanium, Tungsten and

  17. The piezoelectronic stress transduction switch for very large-scale integration, low voltage sensor computation, and radio frequency applications

    Science.gov (United States)

    Magdǎu, I.-B.; Liu, X.-H.; Kuroda, M. A.; Shaw, T. M.; Crain, J.; Solomon, P. M.; Newns, D. M.; Martyna, G. J.

    2015-08-01

    The piezoelectronic transduction switch is a device with potential as a post-CMOS transistor due to its predicted multi-GHz, low voltage performance on the VLSI-scale. However, the operating principle of the switch has wider applicability. We use theory and simulation to optimize the device across a wide range of length scales and application spaces and to understand the physics underlying its behavior. We show that the four-terminal VLSI-scale switch can operate at a line voltage of 115 mV while as a low voltage-large area device, ≈200 mV operation at clock speeds of ≈2 GHz can be achieved with a desirable 104 On/Off ratio—ideal for on-board computing in sensors. At yet larger scales, the device is predicted to operate as a fast (≈250 ps) radio frequency (RF) switch exhibiting high cyclability, low On resistance and low Off capacitance, resulting in a robust switch with a RF figure of merit of ≈4 fs. These performance benchmarks cannot be approached with CMOS which has reached fundamental limits. In detail, a combination of finite element modeling and ab initio calculations enables prediction of switching voltages for a given design. A multivariate search method then establishes a set of physics-based design rules, discovering the key factors for each application. The results demonstrate that the piezoelectronic transduction switch can offer fast, low power applications spanning several domains of the information technology infrastructure.

  18. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  19. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  20. Application of a Silicon Compiler to VLSI (Very Large Scale Integrated Circuits) Design of Digital Pipelined Multipliers.

    Science.gov (United States)

    1984-06-01

    cif (Rename cif file to Iroclaim that it is a 5 micron design.) ctrl-D (Sto; the recording session.) Frint typescript (Get bardcopy of compiler...C for details.) S script 0 % esim eultir8c5.sim sultip8c.sacrol (Perform event simulation of chip.) S ctrl-D 0., p rint typescript % vi multipecS.cif...ctrl-D p rint typescript I.. 70 | - cif2ca aultip8c4.cif (Convert citf to caesar format. Benign warnings are issued when user extension 0 lines

  1. The Systematic Integration of Very Large Scale Integrated Circuit Computer-Aided Design Tools into a Toolkit Optimized for Academic Applications.

    Science.gov (United States)

    1984-12-01

    line (DIP) IC package. 1965: Robert Widlar, a designer with Fairchild, develops the first practical integrated circuit operational amplifier ( opamp ...the uA709. Widlar also designed the uA702, uA710, and the uA741 11-2 .*~~~~ .* . . . . . . . .. .* . . . ... . . . . - opamps . 1966: Autonetics...There was resistance to the implementa- tion of automated design aids [17,40]. The reluctance to use CAD programs was partly due to numerous software fail

  2. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  3. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  4. Proceedings of USC (University of Southern California) Workshop on VLSI (Very Large Scale Integration) & Modern Signal Processing, held at Los Angeles, California on 1-3 November 1982

    Science.gov (United States)

    1983-11-15

    Technology; P. Losleben, DARPA; J. Meindl , Stanford University; L. Sumney, Semiconductor Research Corp. VI "The Microelectronics Center - A New...signal processing be maximized so as to enhance the leadership position that we now enjoy. ■■» -j> mm »;■—7~ś~ T-—r™i W^-WJWJ^W |-- I-- i AUTHOR

  5. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  6. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  7. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  8. FMC cameras, high resolution films and very large scale mapping

    Science.gov (United States)

    Tachibana, Kikuo; Hasegawa, Hiroyuki

    1988-06-01

    Very large scale mapping (1/250) was experimented on the basis of FMC camera, high resolution film and total station surveying. The future attractive combination of precision photogrammetry and personal computer assisted terrestrial surveying was investigated from the point of view of accuracy, time effectiveness and total procedures control.

  9. Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

    Science.gov (United States)

    2015-10-13

    oxide was σ = 2%, where σ is standard deviation (normalized to the mean value). Photolithography was done using a Canon FPA-3000 EX4 stepper with 248...Advances in Cryogenic Engineering Materials, vol. 32, ch. 80, R.P Reed and A.F Clark, Eds. Springer, 1986, pp. 671-678. [19] Y.H. Shi, B.R. Zhao

  10. Very-large-scale coherent motions in open channel flows

    Science.gov (United States)

    Zhong, Qiang; Hussain, Fazle; Li, Dan-Xun

    2016-11-01

    Very-large-scale coherent structures (VLSSs) - whose characteristic length is of the order of 10 h (h is the water depth) - are found to exist in the log and outer layers near the bed of open channel flows. For decades researchers have speculated that large coherent structures may exist in open channel flows. However, conclusive evidence is still lacking. The present study employed pre-multiplied velocity power spectral and co-spectral analyses of time-resolved PIV data obtained in open channel flows. In all cases, two modes - large-scale structures (of the order of h) and VLSSs - dominate the log and outer layers of the turbulent boundary layer. More than half of TKE and 40% of the Reynolds shear stress in the log and outer layers are contributed by VLSSs. The strength difference of VLSSs between open and closed channel flows leads to pronounced redistribution of TKE near the free surface of open channel flows, which is a unique phenomenon that sets the open channel flows apart from other wall-bounded turbulent flows. Funded by China Postdoctoral Science Foundation (No.2015M580105), National Natural Science Foundation of China (No.51127006).

  11. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  12. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  13. Use of polyimides in VLSI fabrication

    Science.gov (United States)

    Wilson, A. M.

    The functional requirements of overcoats and multilevel insulators for very large scale integrated circuits (VLSI) are outlined. The moisture barrier properties of polyimide films are reviewed. Polyimide performance vs plasma enhanced chemically vapor deposited (CVD) silicon nitride overcoats are compared. The topological and via forming advantages of polyimides vs plasma enhanced CVD silicon oxide as a multilevel insulator are cited. The temperature and voltage field induced electronic charge transport and trapping at oxide interfaces is cited as the most serious limitation to the use of polyimides as multilevel insulators on VLSI chips.

  14. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  15. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  16. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    OpenAIRE

    T. Kalavathi Devi; Sakthivel Palaniappan

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the powe...

  17. Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits

    OpenAIRE

    Georgiev, Zdravko

    2013-01-01

    The negative-bias temperature instability (NBTI) is one of the dominant aging degradation mechanisms in today Very Large Scale Integration (VLSI) Integrated Circuits (IC). With the further decreasing of the transistor dimensions and reduction of supply voltage, the NBTI degradation may become a critical reliability threat. Nevertheless, most of the EDA tools lack in the ability to predict and analyse the impact of the NBTI. Other tools able to analyse the NBTI, are often on very low design le...

  18. A parallel VLSI architecture for a digital filter using a number theoretic transform

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1983-01-01

    The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

  19. INTERNAL MEASUREMENTS FOR FAILURE ANALYSIS AND CHIP VERIFICATION OF VLSI CIRCUITS

    OpenAIRE

    KÖlzer, J.; Otto, J.

    1989-01-01

    Chip verification and failure analysis during the design evaluation of very large scale integrated (VLSI) devices call for highly accurate internal analysis methods. After having characterized the first silicon by automated functional testing, classification and statistical analysis can be carried out : In this way a rough electrical evaluation of the material under investigation can be made. Further clues to a faulty device behavior can only be obtained by internal measurements. Serious malf...

  20. Comparison of very-large-scale motions of turbulent pipe and boundary layer simulations

    Science.gov (United States)

    Lee, Jae Hwa; Sung, Hyung Jin

    2013-04-01

    A direct numerical simulation of a fully developed turbulent pipe flow was performed to investigate the similarities and differences of very-large-scale motions (VLSMs) to those of turbulent boundary layer (TBL) flows. The Reynolds number was set to ReD = 35 000, and the computational domain was 30 pipe radii in length. Inspection of instantaneous fields, streamwise two-point correlations, and population trends of the momentum regions showed that the streamwise length of the structures in the pipe flow grew continuously beyond the log layer (y/δ 3δ), and the maximum length of the VLSMs increased up to ˜30δ. Such differences between the TBL and pipe flows arose due to the entrainment of large plumes of the intermittent potential flow in the TBL, creating break-down of the streamwise coherence of the structures above the log layer with the strong swirling strength and Reynolds shear stress. The average streamwise length scale of the pipe flow was approximately 1.5-3.0 times larger than that of the TBL through the log and wake regions. The maximum contribution of the structures to the Reynolds shear stress was observed at approximately 6δ in length, whereas that of the TBL was at 1δ-2δ, indicating a higher contribution of the VLSMs to the Reynolds shear stress in the pipe flow than in the TBL flow.

  1. Very-large-scale production of antibodies in plants: The biologization of manufacturing.

    Science.gov (United States)

    Buyel, J F; Twyman, R M; Fischer, R

    2017-07-01

    Gene technology has facilitated the biologization of manufacturing, i.e. the use and production of complex biological molecules and systems at an industrial scale. Monoclonal antibodies (mAbs) are currently the major class of biopharmaceutical products, but they are typically used to treat specific diseases which individually have comparably low incidences. The therapeutic potential of mAbs could also be used for more prevalent diseases, but this would require a massive increase in production capacity that could not be met by traditional fermenter systems. Here we outline the potential of plants to be used for the very-large-scale (VLS) production of biopharmaceutical proteins such as mAbs. We discuss the potential market sizes and their corresponding production capacities. We then consider available process technologies and scale-down models and how these can be used to develop VLS processes. Finally, we discuss which adaptations will likely be required for VLS production, lessons learned from existing cell culture-based processes and the food industry, and practical requirements for the implementation of a VLS process. Copyright © 2017 The Authors. Published by Elsevier Inc. All rights reserved.

  2. Potential climatic impacts and reliability of very large-scale wind farms

    Science.gov (United States)

    Wang, C.; Prinn, R. G.

    2010-02-01

    Meeting future world energy needs while addressing climate change requires large-scale deployment of low or zero greenhouse gas (GHG) emission technologies such as wind energy. The widespread availability of wind power has fueled substantial interest in this renewable energy source as one of the needed technologies. For very large-scale utilization of this resource, there are however potential environmental impacts, and also problems arising from its inherent intermittency, in addition to the present need to lower unit costs. To explore some of these issues, we use a three-dimensional climate model to simulate the potential climate effects associated with installation of wind-powered generators over vast areas of land or coastal ocean. Using wind turbines to meet 10% or more of global energy demand in 2100, could cause surface warming exceeding 1 °C over land installations. In contrast, surface cooling exceeding 1 °C is computed over ocean installations, but the validity of simulating the impacts of wind turbines by simply increasing the ocean surface drag needs further study. Significant warming or cooling remote from both the land and ocean installations, and alterations of the global distributions of rainfall and clouds also occur. These results are influenced by the competing effects of increases in roughness and decreases in wind speed on near-surface turbulent heat fluxes, the differing nature of land and ocean surface friction, and the dimensions of the installations parallel and perpendicular to the prevailing winds. These results are also dependent on the accuracy of the model used, and the realism of the methods applied to simulate wind turbines. Additional theory and new field observations will be required for their ultimate validation. Intermittency of wind power on daily, monthly and longer time scales as computed in these simulations and inferred from meteorological observations, poses a demand for one or more options to ensure reliability

  3. Potential climatic impacts and reliability of very large-scale wind farms

    Directory of Open Access Journals (Sweden)

    C. Wang

    2010-02-01

    Full Text Available Meeting future world energy needs while addressing climate change requires large-scale deployment of low or zero greenhouse gas (GHG emission technologies such as wind energy. The widespread availability of wind power has fueled substantial interest in this renewable energy source as one of the needed technologies. For very large-scale utilization of this resource, there are however potential environmental impacts, and also problems arising from its inherent intermittency, in addition to the present need to lower unit costs. To explore some of these issues, we use a three-dimensional climate model to simulate the potential climate effects associated with installation of wind-powered generators over vast areas of land or coastal ocean. Using wind turbines to meet 10% or more of global energy demand in 2100, could cause surface warming exceeding 1 °C over land installations. In contrast, surface cooling exceeding 1 °C is computed over ocean installations, but the validity of simulating the impacts of wind turbines by simply increasing the ocean surface drag needs further study. Significant warming or cooling remote from both the land and ocean installations, and alterations of the global distributions of rainfall and clouds also occur. These results are influenced by the competing effects of increases in roughness and decreases in wind speed on near-surface turbulent heat fluxes, the differing nature of land and ocean surface friction, and the dimensions of the installations parallel and perpendicular to the prevailing winds. These results are also dependent on the accuracy of the model used, and the realism of the methods applied to simulate wind turbines. Additional theory and new field observations will be required for their ultimate validation. Intermittency of wind power on daily, monthly and longer time scales as computed in these simulations and inferred from meteorological observations, poses a demand for one or more options to ensure

  4. VLSI architectures for the new (T,L) algorithm

    Science.gov (United States)

    Bengough, P. A.; Simmons, S. J.

    Trellis coding techniques have seen much use in error correction codes for space and satellite applications. When long sequences of data are encoded, the number of possible paths through the trellis becomes great and a trellis search algorithm must be used to determine the path that best matches the received data sequence. The (T,L) algorithm is a new reduced complexity trellis search algorithm, applicable to data sequence estimation in digital communications, that adapts to changing channel conditions. Its simplicity and inherent parallelism suits it well for very large scale integration (VLSI) implementation. A number of alternative VLSI architectures are presented which can be used to realize this algorithm. While one uses a simple nonsorting structure, two other sorting designs based on parallel insertion and weavesorting algorithms are proposed. The area-time performance of the various architectures is compared.

  5. Energy from the desert very large scale PV power : state of the art and into the future

    CERN Document Server

    Komoto, Keiichi; Cunow, Edwin; Megherbi, Karim; Faiman, David; van der Vleuten, Peter

    2013-01-01

    The fourth volume in the established Energy from the Desert series examines and evaluates the potential and feasibility of Very Large Scale Photovoltaic Power Generation (VLS-PV) systems, which have capacities ranging from several megawatts to gigawatts, and to develop practical project proposals toward implementing the VLS-PV systems in the future. It comprehensively analyses all major issues involved in such large scale applications, based on the latest scientific and technological developments by means of close international co-operation with experts from different countries. From t

  6. Towards an automated system for the verification and diagnosis of intelligent VLSI circuits

    Science.gov (United States)

    Velazco, Raoul; Ziade, Haissam

    The main features of a system designed to cope with both the verification and diagnosis of Very Large Scale Integration (VLSI) intelligent circuits are detailed. The system is composed of a validation program generator, the GAPT (French Acronym for automatic generation of test programs) software and a microprocessor dedicated verification system, the TEMAC functional tester. GAPT/TEMAC tools allow an easy implementation of a top down diagnosis procedure. Each diagnosis action is composed of symptom analysis, malfunction hypothesis statement, sequence generation, execution, and result evaluation. It was successfully used in various microprocessor qualification/validation experiments. The system capabilities and the diagnosis procedure are illustrated by an actual 68000 microprocessor diagnosis experiment.

  7. Energy from the desert. Very large scale photovoltaic systems: socio-economic, financial, technical and environmental aspects. Executive summary

    Energy Technology Data Exchange (ETDEWEB)

    Kurokawa, K.; Ito, M.; Komoto, K.; Vleuten, P. van der; Faiman, D. (eds.)

    2009-05-15

    This executive summary report for the International Energy Agency (IEA) summarises the objectives and concepts of very large scale photovoltaic power generation (VLS-PV) systems and takes a look at the socio-economic, financial and technical aspects involved as well as the environmental impact of such systems. Potential benefits for desert communities, agricultural development and desalination of water are topics that are looked at. The potential of VLS-PV, its energy payback time and CO{sub 2} emission rates are discussed. Case studies for the Sahara and the Gobi Dessert areas are discussed. A VLS-PV roadmap is proposed and scenarios are discussed. Finally, conclusions are drawn and recommendations are made.

  8. Very-large-scale spectral solutions for spherical polytropes of index m > 5 and the isothermal sphere

    Science.gov (United States)

    Ito, Yuta; Poje, Andrew; Lancellotti, Carlo

    2018-01-01

    In view of astrophysical applications, we obtain very large scale numerical solutions to the Lane-Emden equations for spherical polytropes of index m > 5 and for the isothermal sphere (m = ∞), by considering ϕ-1 , the inverse function of the gravitational potential. Since the domain of ϕ-1 is bounded, and the asymptotic behavior of its end-point singularities is known, highly accurate solutions can be obtained by spectral collocation methods. This leads to solutions for ϕ that extend accurately to extremely large radii, well beyond those achieved by traditional numerical schemes on [0, ∞). As a reference, we include a table of values for the isothermal sphere (Lane-Emden function of the 2nd kind) spanning r =10-4 through r =10150 with at least nine significant figures. The corresponding semi-analytical asymptotic solution as r → ∞ is

  9. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  10. Avionic Data Bus Integration Technology

    Science.gov (United States)

    1991-12-01

    address the hardware-software interaction between a digital data bus and an avionic system. Very Large Scale Integration (VLSI) ICs and multiversion ...the SCP. In 1984, the Sperry Corporation developed a fault tolerant system which employed multiversion programming, voting, and monitoring for error... MULTIVERSION PROGRAMMING. N-version programming. 226 N-VERSION PROGRAMMING. The independent coding of a number, N, of redundant computer programs that

  11. VLSI Design of Trusted Virtual Sensors

    Directory of Open Access Journals (Sweden)

    Macarena C. Martínez-Rodríguez

    2018-01-01

    Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

  12. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  13. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  14. Application and Integration of Quantum-Effect Devices for Cellular VLSI

    Science.gov (United States)

    Levy, Harold Joseph

    1995-01-01

    Cellular VLSI is that subclass of electronic systems for which small perturbations in a repeated cell design can dramatically influence the cost and performance of the entire system. This thesis presents examples of how the room-temperature quantum effects of tunneling and resonance may be used to condense the functionality of many conventional VLSI devices into a smaller and more efficient subunit, thus yielding tremendous benefits for the system as a whole. In particular, two and three-terminal applications of a complimentary pair of quantum-effect devices, the resonant-tunneling diode and the tunneling-switch diode, are presented. The first example is an image-segmentation network for machine vision, implemented by using resonant-tunneling diodes in one and two-dimensional networks to extract boundaries between regions of constant spatial texture. In this case a single quantum-effect device may replace up to thirty -three CMOS transistors per pixel. The second example is an artificial neural-network processor based on multistate resistors for synaptic conductances. These programmable resistors were produced by combining a vertically -integrated stack of resonant-tunneling diodes with a resistive load and a single MOSFET driven in its ohmic region. This macrostructure has the potential to provide synaptic changes on the picosecond time scale at length scales well below one micron. The third example is a current-mode transistorless memory array based on a two-dimensional network of cells containing only a single tunneling-switch diode and a resistive load. The resulting system has the potential for reaching more than an order-of-magnitude more cell density than state-of-the-art DRAM arrays, while operating at state -of-the-art SRAM speeds and reasonable power consumption.

  15. VLSI design for reliability. Final report, September-November 1989

    Energy Technology Data Exchange (ETDEWEB)

    Hajj, I.N.; Najm, F.N.; Yang, P.

    1990-05-01

    This report contains the results of supplementary work done related to the reliability analysis of Application Specific Very Large Scale Integrated (ASIC VLSI) CMOS circuits. The major work is currently being carried out under Task N-9-5716. The main goal of both tasks is to determine the electromigration susceptibility of VLSI circuits. Electromigration is a major reliability problem caused by the transport of atoms in a metal line due to the electron flow. Under persistent current stress, electromigration can cause deformations of the metal lines which may result in shorts or open circuits. The failure rate due to electromigration depends on the current density in the metal lines and is usually expressed as a median-time-to-failure (MTF). This work focuses on the electromigration problem in the power and ground busses. To estimate the bust MTF, an estimate of the current waveform in each branch of the bus is required. In general, the MTF is dependent on the shape of the current waveform, and not simply on its time-average. However, a very large number of such waveform shapes are possible, depending on what inputs are applied to the circuit. This is especially true for complementary metal oxide semiconductors circuits, which draw current only during switching.

  16. Multilevel VLSI interconnection—an optimum approach?

    Science.gov (United States)

    Srikrishnan, K. V.; Totta, P. A.

    1986-04-01

    The wirability of circuit elements is a key ingredient in the success of the very large scale integration technology. Multilevel wiring eliminates the need to use extensive areas of the silicon surface simply for wiring channels. Increasing the number of wiring planes significantly improves the possibility of achieving the goals of the VLSI, i.e. the interconnection of the maximum number of devices in the smallest possible area. Extensive modeling has shown the need to optimize the wiring pitch, number of wiring planes and electrical properties of the materials used (e.g-low resistivity for conductors and low dielectric constant for insulators). The choice of the interconnection technology is also influenced by other factors. Some of these areas: cost and reliability objectives; in house expertise and practice; new process/equipment availability and a desire to maintain process commonality. The selected strategy is sometimes an optimum approach for an individual situation which is not universally optimum. In IBM, for example, two different but successful multilevel wiring technologies are being used extensively. The first is used for bipolar circuits; it is a three-level metallization design, with sputtered SiO2 as the insulator. The second, for FET devices, has two-levels of metal and polyimide as the insulator. Both technologies use area array input/output terminal connections and lift off line definition. The process/material set of each is reviewed to emphasize the mechanics of reaching an ``optimum'' solution for the individual applications.

  17. Digital Systems Validation Handbook. Volume 2. Chapter 18. Avionic Data Bus Integration Technology

    Science.gov (United States)

    1993-11-01

    interaction between a digital data bus and an avionic system. Very Large Scale Integration (VLSI) ICs and multiversion software, which make up digital...1984, the Sperry Corporation developed a fault tolerant system which employed multiversion programming, voting, and monitoring for error detection and...formulate all the significant behavior of a system. MULTIVERSION PROGRAMMING. N-version programming. N-VERSION PROGRAMMING. The independent coding of a

  18. Very large-scale structures in sintered silica aerogels as evidenced by atomic force microscopy and ultra-small angle X-ray scattering experiments

    CERN Document Server

    Marliere, C; Etienne, P; Woignier, T; Dieudonné, P; Phalippou, J

    2001-01-01

    During the last few years the bulk structure of silica aerogels has been extensively studied mainly by scattering techniques (neutrons, X-rays, light). It has been shown that small silica particles aggregate to constitute a fractal network. Its spatial extension and fractal dimension are strongly dependent on the synthesis conditions (e.g., pH of gelifying solutions). These typical lengths range from 1 to 10 nm. Ultra-small angle X-ray scattering (USAXS) and atomic force microscopy (AFM) experiments have been carried out on aerogels at different steps of densification. The results presented in this paper reveal the existence of a spatial arrangement of the solid part at a very large length scale. The evolution of this very large-scale structure during the densification process has been studied and reveals a contraction of this macro-structure made of aggregates of clusters. (16 refs).

  19. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  20. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    Science.gov (United States)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  1. A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications

    Science.gov (United States)

    Molaei Imen Abadi, Rouzbeh; Saremi, Mehdi

    2018-02-01

    In this paper, the influence of ultra-scaled physical symmetrical contraction on electrical characteristics of ultra-thin silicon-on-insulator nanowires with circular gate-all-around structure is investigated by using a 3D Atlas numerical quantum simulator based on non-equilibrium green's function formalism. It is demonstrated that local cross-section variation in a nanowire transistor results in the establishment of tunnel energy barriers at the source-channel and drain-channel junctions which change device physics and cause a transmission from a quantum wire (1-D) to a floating quantum dot nanowire (0-D) introducing a resonant tunneling nanowire FET (RT-NWFET) as an interesting concept of nanoscale MOSFETs. The barriers construct resonance energy levels in the channel region of nanowires because of the longitudinal confinement in three directions causing some fluctuation in I D- V GS characteristic. In addition, these barriers remarkably improve the subthreshold swing and minimize the ON/OFF-current ratio degradation at a low operation voltage of 0.5 V. As a result, RT-NWFETs are intrinsically preserved from drain-source tunneling and are an interesting candidate for developing the roadmap below 10 nm.

  2. A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications

    Science.gov (United States)

    Molaei Imen Abadi, Rouzbeh; Saremi, Mehdi

    2017-10-01

    In this paper, the influence of ultra-scaled physical symmetrical contraction on electrical characteristics of ultra-thin silicon-on-insulator nanowires with circular gate-all-around structure is investigated by using a 3D Atlas numerical quantum simulator based on non-equilibrium green's function formalism. It is demonstrated that local cross-section variation in a nanowire transistor results in the establishment of tunnel energy barriers at the source-channel and drain-channel junctions which change device physics and cause a transmission from a quantum wire (1-D) to a floating quantum dot nanowire (0-D) introducing a resonant tunneling nanowire FET (RT-NWFET) as an interesting concept of nanoscale MOSFETs. The barriers construct resonance energy levels in the channel region of nanowires because of the longitudinal confinement in three directions causing some fluctuation in I D-V GS characteristic. In addition, these barriers remarkably improve the subthreshold swing and minimize the ON/OFF-current ratio degradation at a low operation voltage of 0.5 V. As a result, RT-NWFETs are intrinsically preserved from drain-source tunneling and are an interesting candidate for developing the roadmap below 10 nm.

  3. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  4. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    Directory of Open Access Journals (Sweden)

    T. Kalavathi Devi

    2015-01-01

    Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  5. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  6. VLSI PARTITIONING ALGORITHM WITH ADAPTIVE CONTROL PARAMETER

    Directory of Open Access Journals (Sweden)

    P. N. Filippenko

    2013-03-01

    Full Text Available The article deals with the problem of very large-scale integration circuit partitioning. A graph is selected as a mathematical model describing integrated circuit. Modification of ant colony optimization algorithm is presented, which is used to solve graph partitioning problem. Ant colony optimization algorithm is an optimization method based on the principles of self-organization and other useful features of the ants’ behavior. The proposed search system is based on ant colony optimization algorithm with the improved method of the initial distribution and dynamic adjustment of the control search parameters. The experimental results and performance comparison show that the proposed method of very large-scale integration circuit partitioning provides the better search performance over other well known algorithms.

  7. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  8. Very Large Scale Distributed Information Processing Systems

    Science.gov (United States)

    1991-09-27

    Modeling Environment, In Proceedings OOPSLA󈨝, New Orleans , LA, 1989. 7 UCLA Computer Science [PGHP91] Thomas W. Page Jr., R. Guy, J Heidemann, G...Data Engineering, February 1986. [PPR83] D. Stott Parker, Jr., Gerald Popek, Gerard Rudisin, Allen Stoughton, Bruce J. Walker, Evelyn Walton, Johanna M

  9. VLSI-distributed architectures for smart cameras

    Science.gov (United States)

    Wolf, Wayne H.

    2001-03-01

    Smart cameras use video/image processing algorithms to capture images as objects, not as pixels. This paper describes architectures for smart cameras that take advantage of VLSI to improve the capabilities and performance of smart camera systems. Advances in VLSI technology aid in the development of smart cameras in two ways. First, VLSI allows us to integrate large amounts of processing power and memory along with image sensors. CMOS sensors are rapidly improving in performance, allowing us to integrate sensors, logic, and memory on the same chip. As we become able to build chips with hundreds of millions of transistors, we will be able to include powerful multiprocessors on the same chip as the image sensors. We call these image sensor/multiprocessor systems image processors. Second, VLSI allows us to put a large number of these powerful sensor/processor systems on a single scene. VLSI factories will produce large quantities of these image processors, making it cost-effective to use a large number of them in a single location. Image processors will be networked into distributed cameras that use many sensors as well as the full computational resources of all the available multiprocessors. Multiple cameras make a number of image recognition tasks easier: we can select the best view of an object, eliminate occlusions, and use 3D information to improve the accuracy of object recognition. This paper outlines approaches to distributed camera design: architectures for image processors and distributed cameras; algorithms to run on distributed smart cameras, and applications of which VLSI distributed camera systems.

  10. Emulated Muscle Spindle and Spiking Afferents Validates VLSI Neuromorphic Hardware as a Testbed for Sensorimotor Function and Disease

    Directory of Open Access Journals (Sweden)

    Chuanxin M. Niu

    2014-12-01

    Full Text Available The lack of multi-scale empirical measurements (e.g. recording simultaneously from neurons, muscles, whole body, etc. complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI technology to provide considerable scalability and high-speed, as much as 365x faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006 and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Matthews, 1964; 1972; Crowe and Matthews, 1964b. Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365x real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  11. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    Science.gov (United States)

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  12. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  13. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  14. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...

  15. TECHNOLOGY MAPPING TOOL FOR VLSI CAD

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2017-01-01

    Full Text Available Technology mapping program implements a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. The structure of the program for solving the technology mapping problem and formats of the source and result data are presented. Models of intermediate representations of the sequential circuit and their conversions are described. Technology mapping is a stage of logic synthesis and it is viewed as the transformation of a functional (i.e., algebraic circuit specification into a gate (i.e., netlist specification. The program is included as project operations in the VLSI CAD system for energy-saving logical synthesis developed in the United Institute of Informatics Problems of NAS of Belarus.

  16. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  17. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  18. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  19. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

  20. FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision

    Science.gov (United States)

    Botella, Guillermo; Martín H., José Antonio; Santos, Matilde; Meyer-Baese, Uwe

    2011-01-01

    Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI) using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments) in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms. PMID:22164069

  1. FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision

    Directory of Open Access Journals (Sweden)

    Uwe Meyer-Baese

    2011-08-01

    Full Text Available Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms.

  2. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  3. Declarative Descriptions for VLSI Generators

    Science.gov (United States)

    1986-06-01

    will review languages in each category. Sheeran [ Sheeran 83] proposes a structured hierarchical design language, IL, FP (a variation of the...IEEE, 1982. [ Sheeran 83] Mary Sheeran . p& FP -An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing Laboratory, November, 1983

  4. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  5. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  6. Hancock: A language for processing very large-scale data

    OpenAIRE

    Bonachea, D; Fisher, K; Rogers, A; Smith, F

    2000-01-01

    A signature is an evolving customer profile computed from call records. AT & T uses signatures to detect fraud and to target marketing. Code to compute signatures can be difficult to write and maintain because of the volume of data. We have designed and implemented Hancock, a C-based domain-specific programming language for describing signatures. Hancock provides data abstraction mechanisms to manage the volume of data and control abstractions to facilitate looping over records. This paper de...

  7. Learning about memory from (very) large scale hippocampal networks

    Science.gov (United States)

    Meshulam, Leenoy; Gauthier, Jeffrey; Brody, Carlos; Tank, David; Bialek, William

    Recent technological progress has dramatically increased our access to the neural activity underlying memory-related tasks. These complex high-dimensional data call for theories that allow us to identify signatures of collective activity in the networks that are crucial for the emergence of cognitive functions. As an example, we study the neural activity in dorsal hippocampus as a mouse runs along a virtual linear track. One of the dominant features of this data is the activity of place cells, which fire when the animal visits particular locations. During the first stage of our work we used a maximum entropy framework to characterize the probability distribution of the joint activity patterns observed across ensembles of up to 100 cells. These models, which are equivalent to Ising models with competing interactions, make surprisingly accurate predictions for the activity of individual neurons given the state of the rest of the network, and this is true both for place cells and for non-place cells. Additionally, the model captures the high-order structure in the data, which cannot be explained by place-related activity alone. For the second stage of our work we study networks of 2000 neurons. To address this much larger system, we are exploring different methods of coarse graining, in the spirit of the renormalization group, searching for simplified models.

  8. VESPA: Very large-scale Evolutionary and Selective Pressure Analyses

    Directory of Open Access Journals (Sweden)

    Andrew E. Webb

    2017-06-01

    Full Text Available Background Large-scale molecular evolutionary analyses of protein coding sequences requires a number of preparatory inter-related steps from finding gene families, to generating alignments and phylogenetic trees and assessing selective pressure variation. Each phase of these analyses can represent significant challenges, particularly when working with entire proteomes (all protein coding sequences in a genome from a large number of species. Methods We present VESPA, software capable of automating a selective pressure analysis using codeML in addition to the preparatory analyses and summary statistics. VESPA is written in python and Perl and is designed to run within a UNIX environment. Results We have benchmarked VESPA and our results show that the method is consistent, performs well on both large scale and smaller scale datasets, and produces results in line with previously published datasets. Discussion Large-scale gene family identification, sequence alignment, and phylogeny reconstruction are all important aspects of large-scale molecular evolutionary analyses. VESPA provides flexible software for simplifying these processes along with downstream selective pressure variation analyses. The software automatically interprets results from codeML and produces simplified summary files to assist the user in better understanding the results. VESPA may be found at the following website: http://www.mol-evol.org/VESPA.

  9. New Approaches for Very Large-Scale Integer Programming

    Science.gov (United States)

    2016-06-24

    existing algorithms. This research has been presented at several conferences and has and will appear in archival journals . 15. SUBJECT TERMS integer...Enter information not included elsewhere such as: prepared in cooperation with; translation of; report supersedes; old edition number, etc. 14...In the context of a single branch-and-bound search, in a first phase, we observe the decisions made by SB, and collect: features that characterize

  10. A Coherent VLSI Design Environment.

    Science.gov (United States)

    1985-03-31

    We would like to acknowledge the contributions by Flavio Rose of MIT when we first studied this problem. The three of us originally produced a O(1V13...Rinehart and Winston, New York, 1976. 18] Charles E. Leiserson, Flavio M. Rose, and James B. Saxe, "Optimizing synchronous circuitry by retiming... Flavio M. Rose, Models for VLSI CircuiLs, Masters Thesis, Department of Electrical En- gineering and Computer Science, Massachusetts Institute of

  11. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  12. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  13. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  14. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  15. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  16. VLSI Technology for Cognitive Radio

    Science.gov (United States)

    VIJAYALAKSHMI, B.; SIDDAIAH, P.

    2017-08-01

    One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

  17. Full custom VLSI - A technology for high performance computing

    Science.gov (United States)

    Maki, Gary K.; Whitaker, Sterling R.

    1990-01-01

    Full custom VLSI is presented as a viable technology for addressing the need for the computing capabilities required for the real-time health monitoring of spacecraft systems. This technology presents solutions that cannot be realized with stored program computers or semicustom VLSI; also, it is not dependent on current IC processes. It is argued that, while design time is longer, full custom VLSI produces the fastest and densest VLSI solution and that high density normally also yields low manufacturing costs.

  18. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  19. Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

    Science.gov (United States)

    Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

    2016-01-01

    A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

  20. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  1. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  2. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  3. NUMERICAL SIMULATION OF DIGITAL VLSI TOTAL DOSE FUNCTIONAL FAILURES

    Directory of Open Access Journals (Sweden)

    O. A. Kalashnikov

    2016-10-01

    Full Text Available The technique for numerical simulation of digital VLSI total dose failures is presented, based on fuzzy logic sets theory. It assumes transfer from boolean logic model of a VLSI with values {0,1} to fuzzy model with continuous interval [0,1], and from boolean logic functions to continuous minimax functions. The technique is realized as a calculation system and allows effective estimating of digital VLSI radiation behavior without experimental investigation.

  4. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  5. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  6. VLSI Architectures For Syntactic Image Analysis

    Science.gov (United States)

    Chiang, Y. P.; Fu, K. S.

    1984-01-01

    Earley's algorithm has been commonly used for the parsing of general context-free languages and error-correcting parsing in syntactic pattern recognition. The time complexity for parsing is 0(n3). In this paper we present a parallel Earley's recognition algorithm in terms of "x*" operation. By restricting the input context-free grammar to be X-free, we are able to implement this parallel algorithm on a triangular shape VLSI array. This system has an efficient way of moving data to the right place at the right time. Simulation results show that this system can recognize a string with length n in 2n+1 system time. We also present an error-correcting recognition algorithm. The parallel error-correcting recognition algorithm has also been im-plemented on a triangular VLSI array. This array recognizes an erroneous string length n in time 2n+1 and gives the correct error count. Applications of the proposed VLSI architectures to image analysis are illus-trated by examples.

  7. A Notation for Describing Multiple Views of VLSI Circuits

    Science.gov (United States)

    1988-06-01

    leaf In the functional programming language pFP cells or abstract objects) and a set of relations among [ Sheeran 83] the behavior specification implies a...A raduate VLSI design class has employed the notation in the design of modules com- [ Sheeran 83] M. Sheeran , "jvFP - An Algebraic VLSI prising a

  8. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  9. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  10. Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

    Science.gov (United States)

    Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

    2017-08-15

    Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~1011 neuron based) large neural networks.

  11. Artwork Analysis Tools for VLSI Circuits.

    Science.gov (United States)

    1980-06-01

    derived frcm the art- work.i~nFo :.- Is zr Code DI t pecal Sculnfv CLA a uPICAT OP T0416 PA*6WM Dine Bftee AMA& -’M Artwork Analysis Tools for VLSI Circuits... code of the program and in pre-generated bit tables. The design rules thcmselves are not input directly into the checker. The rules were interpreted...circuit simulation is swich -level sintulation. In this type, transistors are modeled as switches that are either on or off. Fixed delays are a%.ociated

  12. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  13. Analysis and compensation of the effects of analog VLSI arithmetic on the LMS algorithm.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel; Sbarbaro, Daniel; Valenzuela, Waldo

    2011-07-01

    Analog very large scale integration implementations of neural networks can compute using a fraction of the size and power required by their digital counterparts. However, intrinsic limitations of analog hardware, such as device mismatch, charge leakage, and noise, reduce the accuracy of analog arithmetic circuits, degrading the performance of large-scale adaptive systems. In this paper, we present a detailed mathematical analysis that relates different parameters of the hardware limitations to specific effects on the convergence properties of linear perceptrons trained with the least-mean-square (LMS) algorithm. Using this analysis, we derive design guidelines and introduce simple on-chip calibration techniques to improve the accuracy of analog neural networks with a small cost in die area and power dissipation. We validate our analysis by evaluating the performance of a mixed-signal complementary metal-oxide-semiconductor implementation of a 32-input perceptron trained with LMS.

  14. ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

    Directory of Open Access Journals (Sweden)

    V. I. Romanov

    2016-01-01

    Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

  15. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  16. Etoile Project : Social Intelligent ICT-System for very large scale education in complex systems

    Science.gov (United States)

    Bourgine, P.; Johnson, J.

    2009-04-01

    The project will devise new theory and implement new ICT-based methods of delivering high-quality low-cost postgraduate education to many thousands of people in a scalable way, with the cost of each extra student being negligible (Europe. The project involves every aspect of course production and delivery. Within this the research focused on the creation of a Socially Intelligent Resource Mining system to gather large volumes of high quality educational resources from the internet; new methods to deconstruct these to produce a semantically tagged Learning Object Database; a Living Course Ecology to support the creation and maintenance of evolving course materials; systems to deliver courses; and a ‘socially intelligent assessment system'. The system will be tested on one to ten thousand postgraduate students in Europe working towards the Complex System Society's title of European PhD in Complex Systems. Étoile will have a very high impact both scientifically and socially by (i) the provision of new scalable ICT-based methods for providing very low cost scientific education, (ii) the creation of new mathematical and statistical theory for the multiscale dynamics of complex systems, (iii) the provision of a working example of adaptation and emergence in complex socio-technical systems, and (iv) making a major educational contribution to European complex systems science and its applications.

  17. Very large scale characterization of graphene mechanical devices using a colorimetry technique.

    Science.gov (United States)

    Cartamil-Bueno, Santiago Jose; Centeno, Alba; Zurutuza, Amaia; Steeneken, Peter Gerard; van der Zant, Herre Sjoerd Jan; Houri, Samer

    2017-06-08

    We use a scalable optical technique to characterize more than 21 000 circular nanomechanical devices made of suspended single- and double-layer graphene on cavities with different diameters (D) and depths (g). To maximize the contrast between suspended and broken membranes we used a model for selecting the optimal color filter. The method enables parallel and automatized image processing for yield statistics. We find the survival probability to be correlated with a structural mechanics scaling parameter given by D4/g3. Moreover, we extract a median adhesion energy of Γ = 0.9 J m-2 between the membrane and the native SiO2 at the bottom of the cavities.

  18. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  19. Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

    CERN Document Server

    Shen, Ruijing; Yu, Hao

    2012-01-01

    Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have  become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.  Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and ...

  20. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  1. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  2. Formal Hierarchical Multilevel Verification of Synchronous MOS VLSI Designs,

    Science.gov (United States)

    1987-11-01

    description of digital systems appear in Johnson [Johnson] (though in a much less accessible form). Other researchers, [ Sheeran , Johnson], use the same...Snepscheut, "Hot-Clock nMOS," Proc of the 1985 Chapel Hil Conference on VLSI. Henry Fuchs, Editor. Computer Science Press 1985 [ Sheeran ] Mary Sheeran

  3. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...

  4. Noise-margin limitations on gallium-arsenide VLSI

    Science.gov (United States)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  5. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  6. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  7. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

    Directory of Open Access Journals (Sweden)

    Chen Yang

    2017-06-01

    Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  8. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

    Science.gov (United States)

    Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-06-24

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  9. UW/NW (University of Washington/Northwest) VLSI Consortium

    Science.gov (United States)

    1986-12-10

    structure of the described circuits. One such language is ^ FP (a variation of the Functional Programming language FP) [ Sheeran 83] that describes...86] [Lipton 82] [ Sheeran 83] [Suzuki 85] [UW/NW 84] Bamji, C, Hauck, C. and Allen, J. A Design by Example Regular Structure Generator. In 22nd...Automation Conference, pages 467-474. IEEE, 1982. Mary Sheeran . \\i.FP - An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing La

  10. Using Software Technology to Specify Abstract Interfaces in VLSI Design.

    Science.gov (United States)

    1985-01-01

    and Smoliar [Fran7g], Rowson [Rows80, Gordon [Gord8lJ, Cardelli and Plotkin [Card8l1, Hafer and Parker (Hafe83I, and Sheeran [Shee84] have all suggested...Software 1, 4 (October 1984), pp. 10-26. •.’ Y .. , ;,, ..- , .. r ,- ’..-.... -. -.. ,.:.%.. -. 149 ISbeeS4I. Sheeran , M., "mFP, a Language for VLSI

  11. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  12. Model for EOS caused EF screening in CMOS VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Lisenker, B. [Tower Semiconductor Ltd., Migdal Haemek (Israel); Nevo, Y. [National Semiconductor Ltd., Herzlia B` (Israel)

    1995-12-31

    This paper introduced a Fault Model, capable to elucidate the sensitivity to Electrical Overstress (EOS) and Early Fault (EF) rising nature in CMOS VLSI circuit. The Model based on the general Percolation Theory applied to the CMOS technology. Early Failures screening technique employing this Model, shows strong correlation between rejected devices, EOS faults and EF rate. This technique is recommenced both as an EF screening test and a process reliability monitor.

  13. Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

    Science.gov (United States)

    2013-12-01

    49 Figure 29. A comparison of Verilog and VHDL considering capability and level of abstraction required...inline package DSP digital signal processing DTMR distributed TMR EAR Export Administration Regulation EEPROM electrically erasable PROM EHP...current VHDL VHSIC hardware description language VHSIC very-high-speed integrated circuits VLSI very-large-scale integration VQFP very

  14. Hardware Descriptive Languages: An Efficient Approach to Device ...

    African Journals Online (AJOL)

    Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog ...

  15. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  16. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

  17. Growth and characterization of MMA/SiO2 hybrid low-k thin films for ...

    Indian Academy of Sciences (India)

    The methylmethacrylate (MMA) incorporated SiO2 thin films having low dielectric constant ( = 2.97) were deposited successfully to realize new interlayer material for the enhancement of electrical performance of on-chip wiring in very large scale integrated (VLSI) circuits. We have successfully incorporated MMA monomer ...

  18. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  19. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  20. A programmable analog VLSI neural network processor for communication receivers.

    Science.gov (United States)

    Choi, J; Bang, S H; Sheu, B J

    1993-01-01

    An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

  1. Custom VLSI circuits for high energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  2. Integrating III-V compound semiconductors with silicon using wafer bonding

    Science.gov (United States)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for

  3. Summary of workshop on the application of VLSI for robotic sensing

    Science.gov (United States)

    Brooks, T.; Wilcox, B.

    1984-01-01

    It was one of the objectives of the considered workshop to identify near, mid, and far-term applications of VLSI for robotic sensing and sensor data preprocessing. The workshop was also to indicate areas in which VLSI technology can provide immediate and future payoffs. A third objective is related to the promotion of dialog and collaborative efforts between research communities, industry, and government. The workshop was held on March 24-25, 1983. Conclusions and recommendations are discussed. Attention is given to the need for a pixel correction chip, an image sensor with 10,000 dynamic range, VLSI enhanced architectures, the need for a high-density serpentine memory, an LSI-tactile sensing program, an analog-signal preprocessor chip, a smart strain gage, a protective proximity envelope, a VLSI-proximity sensor program, a robot-net chip, and aspects of silicon micromechanics.

  4. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  5. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  6. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  7. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  8. Spike-driven synaptic plasticity: theory, simulation, VLSI implementation.

    Science.gov (United States)

    Fusi, S; Annunziato, M; Badoni, D; Salamon, A; Amit, D J

    2000-10-01

    We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takacs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (approximately 100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are

  9. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  10. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  11. Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

    Directory of Open Access Journals (Sweden)

    Massimiliano eGiulioni

    2012-02-01

    Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  12. A novel VLSI processor for high-rate, high resolution spectroscopy

    CERN Document Server

    Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

    2000-01-01

    A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

  13. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  14. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  15. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  16. An Integrated Analog Optical Motion Sensor

    OpenAIRE

    Tanner, John; Mead, Carver

    1986-01-01

    This paper describes the theory and implementation of an integrated system that reports the uniform motion of a visual scene. We have built a VLSI circuit that reports the motion of an image focused directly on it. The chip contains an integrated photosensor array to sense the image and has closely coupled custom circuits to perform computation and data extraction.

  17. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  18. VLSI top-down design based on the separation of hierarchies

    NARCIS (Netherlands)

    Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

    1986-01-01

    Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

  19. Single-Electron Transistor (SET) Process and Device Simulation Using SYSNOPSYS TCAD Tools

    OpenAIRE

    Uda Hashim; Amiza Rasmi

    2006-01-01

    Simulation of semiconductor device fabrication and operation is important to the design and manufacture of integrated circuits because it provides insights into complex phenomena that cannot obtained through experimentation or simple analytic models. Process and device simulation is commonly using for the design of new very large scale integration (VLSI) devices and processes. Simulation programs serves as exploratory tools in order to gain better understanding of process and device physics. ...

  20. Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

    Science.gov (United States)

    Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

    1990-01-01

    The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

  1. Способ стабилизации изображения в реальном масштабе времени

    OpenAIRE

    Bibhuti, Bikramaditya; Ohyun, Kwon; SATEESH KUMAR TALAPURI VENKATA SAI; Benjamin, Ryu; Joonki, Paik

    2006-01-01

    This paper proposes reconfigurable VLSI (Very Large Scale Integration) architecture design of real time image stabilization to remove the unwanted displacement due to camera motion and the displacement of the target. This is based on image preprocessing, based many steps (namely light compensation, thresholding, scaling and offset, histogram equalization, LUT operator), followed by sub image phase correlation for motion estimation and kalman filtering for motion correction and stabilization. ...

  2. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture

    Science.gov (United States)

    2009-08-01

    instruction set computer DRAM dynamic random access memory DSP digital signal processor ECAD electronic computer aided design FAME FPGA...performance evaluation corporation VHDL very-high-speed hardware description language VLSI very large scale integration XUP Xilinx university program... VHDL naturally runs in parallel on an FPGA, while a program written in languages like C or Java naturally runs sequentially on a computer. Indeed, the

  3. Advanced OFDM systems for terrestrial multimedia links

    OpenAIRE

    Posega, Renzo; Mlynek, Daniel

    2007-01-01

    Recently, there has been considerable discussion about new wireless technologies and standards able to achieve high data rates. Due to the recent advances of digital signal processing and Very Large Scale Integration (VLSI) technologies, the initial obstacles encountered for the implementation of Orthogonal Frequency Division Multiplexing (OFDM) modulation schemes, such as massive complex multiplications and high speed memory accesses, do not exist anymore. OFDM offers strong multipath protec...

  4. A HARDWARE IMPLEMENTATION OF PUNCTURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

    OpenAIRE

    E. García,; Torres, D.; Guzmán, M.

    2005-01-01

    This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctu...

  5. A VLSI field-programmable mixed-signal array to perform neural signal processing and neural modeling in a prosthetic system.

    Science.gov (United States)

    Bamford, Simeon A; Hogri, Roni; Giovannucci, Andrea; Taub, Aryeh H; Herreros, Ivan; Verschure, Paul F M J; Mintz, Matti; Del Giudice, Paolo

    2012-07-01

    A very-large-scale integration field-programmable mixed-signal array specialized for neural signal processing and neural modeling has been designed. This has been fabricated as a core on a chip prototype intended for use in an implantable closed-loop prosthetic system aimed at rehabilitation of the learning of a discrete motor response. The chosen experimental context is cerebellar classical conditioning of the eye-blink response. The programmable system is based on the intimate mixing of switched capacitor analog techniques with low speed digital computation; power saving innovations within this framework are presented. The utility of the system is demonstrated by the implementation of a motor classical conditioning model applied to eye-blink conditioning in real time with associated neural signal processing. Paired conditioned and unconditioned stimuli were repeatedly presented to an anesthetized rat and recordings were taken simultaneously from two precerebellar nuclei. These paired stimuli were detected in real time from this multichannel data. This resulted in the acquisition of a trigger for a well-timed conditioned eye-blink response, and repetition of unpaired trials constructed from the same data led to the extinction of the conditioned response trigger, compatible with natural cerebellar learning in awake animals.

  6. Current induced annealing and electrical characterization of single layer graphene grown by chemical vapor deposition for future interconnects in VLSI circuits

    Energy Technology Data Exchange (ETDEWEB)

    Prasad, Neetu, E-mail: neetu.prasad@south.du.ac.in, E-mail: neetu23686@gmail.com; Kumari, Anita; Bhatnagar, P. K.; Mathur, P. C. [Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi 110021 (India); Bhatia, C. S. [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore)

    2014-09-15

    Single layer graphene (SLG) grown by chemical vapor deposition (CVD) has been investigated for its prospective application as horizontal interconnects in very large scale integrated circuits. However, the major bottleneck for its successful application is its degraded electronic transport properties due to the resist residual trapped in the grain boundaries and on the surface of the polycrystalline CVD graphene during multi-step lithographic processes, leading to increase in its sheet resistance up to 5 MΩ/sq. To overcome this problem, current induced annealing has been employed, which helps to bring down the sheet resistance to 10 kΩ/sq (of the order of its initial value). Moreover, the maximum current density of ∼1.2 × 10{sup 7 }A/cm{sup 2} has been obtained for SLG (1 × 2.5 μm{sup 2}) on SiO{sub 2}/Si substrate, which is about an order higher than that of conventionally used copper interconnects.

  7. Learning and optimization with cascaded VLSI neural network building-block chips

    Science.gov (United States)

    Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

    1992-01-01

    To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

  8. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  9. Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

    Directory of Open Access Journals (Sweden)

    S. Jayanthy

    2012-01-01

    Full Text Available As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG method based on a modified Fanout Oriented (FAN to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.

  10. A subthreshold aVLSI implementation of the Izhikevich simple neuron model.

    Science.gov (United States)

    Rangan, Venkat; Ghosh, Abhishek; Aparin, Vladimir; Cauwenberghs, Gert

    2010-01-01

    We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human-machine interface applications in neural prostheses and implantable bioelectronics, as well as large-scale neural emulation tools for computational neuroscience.

  11. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  12. A VLSI design for universal noiseless coding. [for spacecraft imaging equipment

    Science.gov (United States)

    Lee, Jun-Ji; Fang, Wai-Chi; Rice, Robert F.

    1988-01-01

    The practical, noiseless and efficient data-compression technique presented involves a conceptual VLSI design which is capable of meeting real-time processing rates and meets low-power, low-weight, and small-volume requirements. This form of data compression is applicable to image data compression aboard future low-budget spaceflight missions, for such instruments as visual-IR mapping spectrometers and high-resolution imaging spectrometers.

  13. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  14. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  15. Specification and Design Methodologies for High-Speed Fault-Tolerant Array Algorithms and Structures for VLSI.

    Science.gov (United States)

    1987-06-01

    Verlag Lecture Notes 201, 1985. [She84] M. Sheeran , "muFP, a language for VLSI design", Proc. 1984 ACM Conference on LISP and Functional Programming...fMeshkinpour8S5 and Sheeran (Sheeran84] extended Backus’ Fl? language with operators to handle sequential circuits. 2 Brief Introduction to vFP vFP...Spring 1913, pp. 274-277. (201 Sheeran , M., "muFP, a Language for VLSI Design." Proc 1984 ACM Conference on LU and Functional Programming. August [4

  16. Microscale Adaptive Optics: Wave-Front Control with a mu-Mirror Array and a VLSI Stochastic Gradient Descent Controller.

    Science.gov (United States)

    Weyrauch, T; Vorontsov, M A; Bifano, T G; Hammer, J A; Cohen, M; Cauwenberghs, G

    2001-08-20

    The performance of adaptive systems that consist of microscale on-chip elements [microelectromechanical mirror (mu-mirror) arrays and a VLSI stochastic gradient descent microelectronic control system] is analyzed. The mu-mirror arrays with 5 x 5 and 6 x 6 actuators were driven with a control system composed of two mixed-mode VLSI chips implementing model-free beam-quality metric optimization by the stochastic parallel perturbative gradient descent technique. The adaptation rate achieved was near 6000 iterations/s. A secondary (learning) feedback loop was used to control system parameters during the adaptation process, further increasing the adaptation rate.

  17. An effective timing characterization method for an accuracy-proved VLSI standard cell library

    Science.gov (United States)

    Jianhua, Jiang; Man, Liang; Lei, Wang; Yumei, Zhou

    2014-02-01

    This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.

  18. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  19. High-performance fault-tolerant VLSI systems using micro rollback

    Science.gov (United States)

    Tamir, Yuval; Tremblay, Marc

    1990-01-01

    A technique called micro rollback, which allows most of the performance penalty for concurrent error detection to be eliminated, is presented. Detection is performed in parallel with the transmission of information between modules, thus removing the delay for detection from the critical path. Erroneous information may thus reach its destination module several clock cycles before an error indication. Operations performed on this erroneous information are undone using a hardware mechanism for fast rollback of a few cycles. The implementation of a VLSI processor capable of micro rollback is discussed, as well as several critical issues related to its use in a complete system.

  20. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  1. VLSI design of universal approximator neuro-fuzzy systems

    OpenAIRE

    Baturone, I.; Sánchez-Solano, Santiago; Barriga, Angel; Jiménez Fernández, Carlos Jesús; Senhadji, Raouf; López, D. R.

    2001-01-01

    Neuro-fuzzy systems can theoretically solve any problem since they are universal approximators. Besides, they combine the advantages of the neuro and fuzzy paradigms. This paper describes and compares the different strategies that can be adopted to implement the learning and inference mechanisms involved in a neuro-fuzzy system. CAD tools, most of them integrated into the fuzzy system development environment Xfuzzy 2.0, have been developed to assist the designer in the implementation of neuro...

  2. Handbook of VLSI microlithography principles, technology and applications

    CERN Document Server

    Glendinning, William B

    1991-01-01

    This handbook gives readers a close look at the entire technology of printing very high resolution and high density integrated circuit (IC) patterns into thin resist process transfer coatings-- including optical lithography, electron beam, ion beam, and x-ray lithography. The book's main theme is the special printing process needed to achieve volume high density IC chip production, especially in the Dynamic Random Access Memory (DRAM) industry. The book leads off with a comparison of various lithography methods, covering the three major patterning parameters of line/space, resolution, line e

  3. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  4. Nanoscale integration is the next frontier for nanotechnology

    Energy Technology Data Exchange (ETDEWEB)

    Picraux, Samuel T [Los Alamos National Laboratory

    2009-01-01

    Nanoscale integration of materials and structures is the next critical step to exploit the promise of nanomaterials. Many novel and fascinating properties have been revealed for nanostructured materials. But if nanotechnology is to live up to its promise we must incorporate these nanoscale building blocks into functional systems that connect to the micro- and macroscale world. To do this we will inevitably need to understand and exploit the resulting combined unique properties of these integrated nanosystems. Much science waits to be discovered in the process. Nanoscale integration extends from the synthesis and fabrication of individual nanoscale building blocks, to the assembly of these building blocks into composite structures, and finally to the formation of complex functional systems. As illustrated in Figure 1, the building blocks may be homogeneous or heterogeneous, the composite materials may be nanocomposite or patterned structures, and the functional systems will involve additional combinations of materials. Nanoscale integration involves assembling diverse nanoscale materials across length scales to design and achieve new properties and functionality. At each stage size-dependent properties, the influence of surfaces in close proximity, and a multitude of interfaces all come into play. Whether the final system involves coherent electrons in a quantum computing approach, the combined flow of phonons and electrons for a high efficiency thermoelectric micro-generator, or a molecular recognition structure for bio-sensing, the combined effects of size, surface, and interface will be critical. In essence, one wants to combine the novel functions available through nanoscale science to achieve unique multi-functionalities not available in bulk materials. Perhaps the best-known example of integration is that of combining electronic components together into very large scale integrated circuits (VLSI). The integrated circuit has revolutionized electronics in many

  5. BLITZEN: A highly integrated massively parallel machine

    Science.gov (United States)

    Blevins, D. W.; Davis, E. W.; Heaton, R. A.; Reif, J. H.

    1988-01-01

    The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

  6. BLITZEN - A highly integrated massively parallel machine

    Science.gov (United States)

    Blevins, D. W.; Davis, E. W.; Heaton, R. A.; Reif, J. H.

    1988-01-01

    The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

  7. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  8. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  9. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  10. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  11. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  12. Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2011-01-01

    Full Text Available Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

  13. VLSI Research

    Science.gov (United States)

    1983-10-31

    Caesar and Mextra and other old programs, as well as several previously-unreleased pro- grams, such as Lyra. Crystal. Peg, and Tpack . The 1983...release was sent to eight beta test sites in January, and began general distribution on April 1. EL1. Tpack : A System for Combining Graphics and Procedures

  14. VLSI Research

    Science.gov (United States)

    1984-04-01

    23,1984 / CONTINENTAL BALLROOMS 6-9 / 9:00 A.M. *T-ś! J SESSION XII: MICROPROCESSORS ANO MICROCONTROLLERS THAM 12.1: A 32b NMOS Microprocessor...roisideration, AlC is insensitive to the interface-wrapt..2 charge. The difference between AVr and Al£, therefore, will be the con- tribution from the...reduction of AVr . Since the degree of impact ionization increases with the substrate bias, the end result is the observed decrease in AVj- with

  15. The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

    Science.gov (United States)

    Xu, Peng; Pan, Zhongliang

    2017-09-01

    With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and ABCD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system. Project supported by the Guangdong Provincial Natural Science Foundation of China (No. 2014A030313441), the Guangzhou Science and Technology Project (No. 201510010169), the Guangdong Province Science and Technology Project (No. 2016B090918071), and the National Natural Science Foundation of China (No. 61072028).

  16. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  17. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  18. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  19. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    Science.gov (United States)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  20. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  1. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  2. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces. Copyright © 2014 Elsevier B.V. All rights reserved.

  3. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  4. Integration

    DEFF Research Database (Denmark)

    Emerek, Ruth

    2004-01-01

    Bidraget diskuterer de forskellige intergrationsopfattelse i Danmark - og hvad der kan forstås ved vellykket integration......Bidraget diskuterer de forskellige intergrationsopfattelse i Danmark - og hvad der kan forstås ved vellykket integration...

  5. Influence of gate tunneling currents on switched capacitor integrators

    OpenAIRE

    W. Kraus; D. Schmitt-Landsiedel

    2009-01-01

    In order to achieve a higher level of integration in modern VLSI systems, not only the lateral geometrical dimensions have to be scaled. Lowering the supply voltage also requires scaling down the oxide thickness of the transistors. While the oxide thickness is scaled down proportionally with the supply voltage, the gate tunneling currents grow exponentially, which results in special issues concerning deviations in charge based analog and mixed signal circuitry. The influence of gate tunneling...

  6. A one-semester course in modeling of VSLI interconnections

    CERN Document Server

    Goel, Ashok

    2015-01-01

    Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits.

  7. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  8. [Integrity].

    Science.gov (United States)

    Gómez Rodríguez, Rafael Ángel

    2014-01-01

    To say that someone possesses integrity is to claim that that person is almost predictable about responses to specific situations, that he or she can prudentially judge and to act correctly. There is a closed interrelationship between integrity and autonomy, and the autonomy rests on the deeper moral claim of all humans to integrity of the person. Integrity has two senses of significance for medical ethic: one sense refers to the integrity of the person in the bodily, psychosocial and intellectual elements; and in the second sense, the integrity is the virtue. Another facet of integrity of the person is la integrity of values we cherish and espouse. The physician must be a person of integrity if the integrity of the patient is to be safeguarded. The autonomy has reduced the violations in the past, but the character and virtues of the physician are the ultimate safeguard of autonomy of patient. A field very important in medicine is the scientific research. It is the character of the investigator that determines the moral quality of research. The problem arises when legitimate self-interests are replaced by selfish, particularly when human subjects are involved. The final safeguard of moral quality of research is the character and conscience of the investigator. Teaching must be relevant in the scientific field, but the most effective way to teach virtue ethics is through the example of the a respected scientist.

  9. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  10. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  11. Modular, Parallel Pulse-Shaping Filter Architectures

    Science.gov (United States)

    Gray, Andrew A.

    2003-01-01

    Novel architectures based on parallel subconvolution frequency-domain filtering methods have been developed for modular processing rate reduction of discrete-time pulse-shaping filters. Such pulse-shaping is desirable and often necessary to obtain bandwidth efficiency in very-high-rate wireless communications systems. In principle, this processing could be implemented in very-large-scale integrated (VLSI) circuits. Whereas other approaches to digital pulse-shaping are based primarily on time-domain processing concepts, the theory and design rules of the architectures presented here are founded on frequency-domain processing that has advantages in certain systems.

  12. Application of parallel distributed processing to space based systems

    Science.gov (United States)

    Macdonald, J. R.; Heffelfinger, H. L.

    1987-01-01

    The concept of using Parallel Distributed Processing (PDP) to enhance automated experiment monitoring and control is explored. Recent very large scale integration (VLSI) advances have made such applications an achievable goal. The PDP machine has demonstrated the ability to automatically organize stored information, handle unfamiliar and contradictory input data and perform the actions necessary. The PDP machine has demonstrated that it can perform inference and knowledge operations with greater speed and flexibility and at lower cost than traditional architectures. In applications where the rule set governing an expert system's decisions is difficult to formulate, PDP can be used to extract rules by associating the information an expert receives with the actions taken.

  13. An introduction to logic circuit testing

    CERN Document Server

    Lala, Parag K

    2008-01-01

    An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)

  14. High density circuit technology, part 1

    Science.gov (United States)

    Wade, T. E.

    The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

  15. Using G4FETs as a Data Router for In-Plane Crossing of Signal Paths

    Science.gov (United States)

    Fijany, Amir; Vatan, Farrokh; Mojarradi, Mohammad; Toomarian, Nikzad; Johnson, Travis; Kolawa, Elizabeth; Blalock, Benjamin; Cristoloveanu, Sorin; Chen, Suheng; Akarvardar, Kerem

    2007-01-01

    Theoretical analysis and some experiments have demonstrated that siliconon- insulator (SOI) 4-gate transistors the type known as G(exp 4)FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G(exp 4)FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design.

  16. A systolic architecture for the correlation and accumulation of digital sequences

    Science.gov (United States)

    Deutsch, L. J.; Lahmeyer, C. R.

    1986-01-01

    A fully systolic architecture for the implementation of digital sequence correlator/accumulators is described. These devices consist of a two-dimensional array of processing elements that are conceived for efficient fabrication in Very Large Scale Integrated (VLSI) circuits. A custom VLSI chip that was implemented using these concepts is described. The chip, which contains a four-lag three-level sequence correlator and four bits of accumulation with overflow detection, was designed using the Integrated UNIX-Based Computer Aided Design (CAD) System. Applications of such devices include the synchronization of coded telemetry data, alignment of both real time and non-real time Very Large Baseline Interferometry (VLBI) signals, and the implementation of digital filters and processes of many types.

  17. Adaptive visual and auditory map alignment in barn owl superior colliculus and its neuromorphic implementation.

    Science.gov (United States)

    Huo, Juan; Murray, Alan; Wei, Dongqing

    2012-09-01

    Adaptation is one of the most important phenomena in biology. A young barn owl can adapt to imposed environmental changes, such as artificial visual distortion caused by wearing a prism. This adjustment process has been modeled mathematically and the model replicates the sensory map realignment of barn owl superior colliculus (SC) through axonogenesis and synaptogenesis. This allows the biological mechanism to be transferred to an artificial computing system and thereby imbue it with a new form of adaptability to the environment. The model is demonstrated in a real-time robot environment. Results of the experiments are compared with and without prism distortion of vision, and show improved adaptability for the robot. However, the computation speed of the embedded system in the robot is slow. A digital and analog mixed signal very-large-scale integration (VLSI) circuit has been fabricated to implement adaptive sensory pathway changes derived from the SC model at higher speed. VLSI experimental results are consistent with simulation results.

  18. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  19. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  20. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Directory of Open Access Journals (Sweden)

    Silvio P. Sabatini

    2003-06-01

    Full Text Available We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth, from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  1. Integrated MOS four-quadrant analogue multiplier using switched-capacitor technique

    Science.gov (United States)

    Yasumoto, M.; Enomoto, T.

    1982-09-01

    A fully integrated four-quadrant analog multiplier based on switched-capacitor technique for realisation of high-speed and high-density analog LSIs was developed using a MOS VLSI process. Excellent characteristics such as low total harmonic distortion of -50 dB for two input signals of 1 Vp-p, large dynamic range of 80 dB and fast operation speed of 2 MHz clock rate were obtained. Application to convolvers and correlators is also demonstrated.

  2. Aceleración de un algoritmo de enfriamiento simulado mediante particionamiento de redes. Aplicación a "placement" de circuitos VLSI

    OpenAIRE

    Aguirre Echanove, Miguel Ángel; Torralba Silgado, Antonio Jesús; García Franquelo, Leopoldo

    1995-01-01

    Se propone un nuevo método de mejora de los resultados del "placement" de un circuito VLSI. El método propuesto utiliza un particionamiento recursivo para obtener una solución de partida para el posterior proceso de enfriamiento simulado. Para preservar los beneficios de esta solución de partida, la temperatura inicial del algoritmo de enfriamiento es seleccionada del espacio intermedio de las temperaturas. Se presentan resultados experimentales sobre diversos circuitos de prueba, demostrando...

  3. A segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics for a PET scanner

    CERN Document Server

    Chesi, Enrico Guido; Joram, C; Mathot, S; Séguinot, Jacques; Weilhammer, P; Ciocia, F; De Leo, R; Nappi, E; Vilardi, I; Argentieri, A; Corsi, F; Dragone, A; Pasqua, D

    2006-01-01

    We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is put on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

  4. A Novel Strategy for Very-Large-Scale Cash-Crop Mapping in the Context of Weather-Related Risk Assessment, Combining Global Satellite Multispectral Datasets, Environmental Constraints, and In Situ Acquisition of Geospatial Data

    Directory of Open Access Journals (Sweden)

    Fabio Dell’Acqua

    2018-02-01

    Full Text Available Cash crops are agricultural crops intended to be sold for profit as opposed to subsistence crops, meant to support the producer, or to support livestock. Since cash crops are intended for future sale, they translate into large financial value when considered on a wide geographical scale, so their production directly involves financial risk. At a national level, extreme weather events including destructive rain or hail, as well as drought, can have a significant impact on the overall economic balance. It is thus important to map such crops in order to set up insurance and mitigation strategies. Using locally generated data—such as municipality-level records of crop seeding—for mapping purposes implies facing a series of issues like data availability, quality, homogeneity, etc. We thus opted for a different approach relying on global datasets. Global datasets ensure homogeneity and availability of data, although sometimes at the expense of precision and accuracy. A typical global approach makes use of spaceborne remote sensing, for which different land cover classification strategies are available in literature at different levels of cost and accuracy. We selected the optimal strategy in the perspective of a global processing chain. Thanks to a specifically developed strategy for fusing unsupervised classification results with environmental constraints and other geospatial inputs including ground-based data, we managed to obtain good classification results despite the constraints placed. The overall production process was composed using “good-enough" algorithms at each step, ensuring that the precision, accuracy, and data-hunger of each algorithm was commensurate to the precision, accuracy, and amount of data available. This paper describes the tailored strategy developed on the occasion as a cooperation among different groups with diverse backgrounds, a strategy which is believed to be profitably reusable in other, similar contexts. The paper presents the problem, the constraints and the adopted solutions; it then summarizes the main findings including that efforts and costs can be saved on the side of Earth Observation data processing when additional ground-based data are available to support the mapping task.

  5. A Novel Strategy for Very-Large-Scale Cash-Crop Mapping in the Context of Weather-Related Risk Assessment, Combining Global Satellite Multispectral Datasets, Environmental Constraints, and In Situ Acquisition of Geospatial Data.

    Science.gov (United States)

    Dell'Acqua, Fabio; Iannelli, Gianni Cristian; Torres, Marco A; Martina, Mario L V

    2018-02-14

    Cash crops are agricultural crops intended to be sold for profit as opposed to subsistence crops, meant to support the producer, or to support livestock. Since cash crops are intended for future sale, they translate into large financial value when considered on a wide geographical scale, so their production directly involves financial risk. At a national level, extreme weather events including destructive rain or hail, as well as drought, can have a significant impact on the overall economic balance. It is thus important to map such crops in order to set up insurance and mitigation strategies. Using locally generated data-such as municipality-level records of crop seeding-for mapping purposes implies facing a series of issues like data availability, quality, homogeneity, etc. We thus opted for a different approach relying on global datasets. Global datasets ensure homogeneity and availability of data, although sometimes at the expense of precision and accuracy. A typical global approach makes use of spaceborne remote sensing, for which different land cover classification strategies are available in literature at different levels of cost and accuracy. We selected the optimal strategy in the perspective of a global processing chain. Thanks to a specifically developed strategy for fusing unsupervised classification results with environmental constraints and other geospatial inputs including ground-based data, we managed to obtain good classification results despite the constraints placed. The overall production process was composed using "good-enough" algorithms at each step, ensuring that the precision, accuracy, and data-hunger of each algorithm was commensurate to the precision, accuracy, and amount of data available. This paper describes the tailored strategy developed on the occasion as a cooperation among different groups with diverse backgrounds, a strategy which is believed to be profitably reusable in other, similar contexts. The paper presents the problem, the constraints and the adopted solutions; it then summarizes the main findings including that efforts and costs can be saved on the side of Earth Observation data processing when additional ground-based data are available to support the mapping task.

  6. Aluminum alloy metallization for integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Ghate, P.B.

    1981-09-11

    Aluminum metallization is most widely used for contacts and interconnections in both bipolar and MOS integrated circuits. Aluminum alloy films, such as Al-Si and Al-Cu films, were introduced to minimize the erosion of silicon from contact windows and to improve the electromigration resistance of interconnections. Recently, magnetron sputter-deposited aluminum, Al-2wt.%Cu and Al-2wt.%Cu-1wt.%Si films were employed to study the stability and contact resistance of Si-(Al alloy film) contacts on devices with shallow junction depths of the order of 0.35 ..mu..m. Test structures were used to determine the leakage currents of 100n/sup +//p/sup +/ diodes as a function of the storage time (up to 1000 h) at 150 C, and the physical nature of the Si-(Al alloy) contacts was examined using scanning electron microscopy. The compatibility of the Al-Cu-Si metallization with the very large scale integrated requirements of interconnection and Si-metal contacts for shallow junction devices is discussed.

  7. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  8. Exploration and Evaluation of Nanometer Low-power Multi-core VLSI Computer Architectures

    Science.gov (United States)

    2015-03-01

    Steven Helmer, Andrea Lapiana, Giuseppe Lapiana, Rich Linderman, Tom Renz, John Rooks, Ross Thompson, Lisa Weyna, and Qing Wu. iii 1...a script-based language that most EDA-vendors support called Tool Command Language (Tcl). John Ousterhout invented Tcl while he was a faculty...Integrated Circuit Technology, 2006. ICSICT 󈧊. 8th International Conference on, 2006, pp. 1610-1613. [11] R. Chau, J. Brask, S. Datta, G. Dewey , M

  9. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    Science.gov (United States)

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  10. DIALOG and SYNC a VLSI chip set for timing of the LHCb Muon detector

    CERN Document Server

    Cadeddu, S; Deplano, C; Lai, A

    2004-01-01

    The Muon detector of the LHCb experiment at CERN plays a fundamental role in the first trigger level. It is mainly realized by means of a MWPC technology and consists of about 126,000 front-end channels. High efficiency is necessary both at detector and front-end level to satisfy the trigger requirement of 5 hits per 5 Muon stations with an overall efficiency of 95%. This corresponds to having a single front- end channel detection efficiency of 99% within a time window of 20 ns and also poses the problem of an accurate time alignment of the whole detector. The problem is addressed by designing two custom integrated circuits, named DIALOG and SYNC, realized in the IBM 0.25 mu m radiation hard technology. (3 refs).

  11. A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

    Science.gov (United States)

    Zhang, Xiangyu; An, Fengwei; Nakashima, Ikki; Luo, Aiwen; Chen, Lei; Ishii, Idaku; Jürgen Mattausch, Hans

    2017-04-01

    A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

  12. Implantable VLSI systems for compression and communication in wireless biosensor recording arrays

    Science.gov (United States)

    Kamboh, Awais Mehmood

    Successful use of microelectrode arrays to record neural activity in the cortex has opened new opportunities for scientists to decode the intricate functionality of the human brain and the behavior of neurons that enable its complex operation. The resulting brain-machine interface devices play a critical role in enabling patients with neural disorders to achieve a better lifestyle. Such interfaces provide a direct interface to the brain and show great promise in many biomedical applications. This thesis explores some of the major obstacles impeding the advance of wireless neural implants and addresses them through development of highly efficient algorithms and implantable hardware. An overwhelming amount of data is generated by the microelectrode arrays, resulting in a data bandwidth bottleneck. To overcome this problem, an implantable system has been devised to enable control over the amount of data that must be transmitted without compromising the information contained in the array of neural signals. Furthermore, the nature of the wireless communication channel across the skin tissue is not well characterized. In this thesis, solutions have been developed to maximize that data throughput and enable unfailing yet low-power communication of bidirectional data between the implanted device and the external world. Finally, a unified energy-efficient, implantable CMOS integrated circuit was developed to address these two critical problems. The resulting integrated solution ensures seamless multi-modal operation, and thus establishes a pathway to the design of next-generation neuroprosthetics devices. Although the motivation for this thesis comes from the field of neuroprosthetics, the solutions devised are pertinent to a wide range of implantable applications.

  13. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    Science.gov (United States)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  14. Analysis and simulation of semiconductor devices

    CERN Document Server

    Selberherr, Siegfried

    1984-01-01

    The invention of semiconductor devices is a fairly recent one, considering classical time scales in human life. The bipolar transistor was announced in 1947, and the MOS transistor, in a practically usable manner, was demonstrated in 1960. From these beginnings the semiconductor device field has grown rapidly. The first integrated circuits, which contained just a few devices, became commercially available in the early 1960s. Immediately thereafter an evolution has taken place so that today, less than 25 years later, the manufacture of integrated circuits with over 400.000 devices per single chip is possible. Coincident with the growth in semiconductor device development, the literature concerning semiconductor device and technology issues has literally exploded. In the last decade about 50.000 papers have been published on these subjects. The advent of so called Very-Large-Scale-Integration (VLSI) has certainly revealed the need for a better understanding of basic device behavior. The miniaturization of the s...

  15. Simulation of a spiking neuron circuit using carbon nanotube transistors

    Energy Technology Data Exchange (ETDEWEB)

    Najari, Montassar, E-mail: malnjar@jazanu.edu.sa [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); IKCE unit, Jazan University, Jazan (Saudi Arabia); El-Grour, Tarek, E-mail: grour-tarek@hotmail.fr [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); Jelliti, Sami, E-mail: sjelliti@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Hakami, Othman Mousa, E-mail: omhakami@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Faculty of Sciences, Jazan University, Jazan (Saudi Arabia)

    2016-06-10

    Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

  16. High-speed 3D imaging using two-wavelength parallel-phase-shift interferometry.

    Science.gov (United States)

    Safrani, Avner; Abdulhalim, Ibrahim

    2015-10-15

    High-speed three dimensional imaging based on two-wavelength parallel-phase-shift interferometry is presented. The technique is demonstrated using a high-resolution polarization-based Linnik interferometer operating with three high-speed phase-masked CCD cameras and two quasi-monochromatic modulated light sources. The two light sources allow for phase unwrapping the single source wrapped phase so that relatively high step profiles having heights as large as 3.7 μm can be imaged in video rate with ±2  nm accuracy and repeatability. The technique is validated using a certified very large scale integration (VLSI) step standard followed by a demonstration from the semiconductor industry showing an integrated chip with 2.75 μm height copper micro pillars at different packing densities.

  17. Thin film device applications

    CERN Document Server

    Kaur, Inderjeet

    1983-01-01

    Two-dimensional materials created ab initio by the process of condensation of atoms, molecules, or ions, called thin films, have unique properties significantly different from the corresponding bulk materials as a result of their physical dimensions, geometry, nonequilibrium microstructure, and metallurgy. Further, these characteristic features of thin films can be drasti­ cally modified and tailored to obtain the desired and required physical characteristics. These features form the basis of development of a host of extraordinary active and passive thin film device applications in the last two decades. On the one extreme, these applications are in the submicron dimensions in such areas as very large scale integration (VLSI), Josephson junction quantum interference devices, magnetic bubbles, and integrated optics. On the other extreme, large-area thin films are being used as selective coatings for solar thermal conversion, solar cells for photovoltaic conver­ sion, and protection and passivating layers. Ind...

  18. Using a single chip FEC for satellite systems

    Science.gov (United States)

    Onotera, L.; Nicholson, R.

    Information transmission over digital satellite communication channels is primarily power-limited, where forward error correction (FEC) codes can significantly improve performance. The use of FEC can reduce the required signal to noise ratio to sustain a given bit error rate. The use of forward error correction has become a standard part of present day digital satellite communication systems. Means of applying a new very large scale integration (VLSI) integrated circuit FEC chip into various kinds of systems is discussed. Specifically, some of the considerations and tradeoffs in continuous single channel per carrier (SCPC), multiple channels per carrier (MCPC), and burst systems are related to the new design. This new chip will provide an effective space and cost advantage by inserting a powerful forward error correction capability into most types of satellite digital communication links.

  19. Ultra-efficient 10 Gb/s hybrid integrated silicon photonic transmitter and receiver.

    Science.gov (United States)

    Zheng, Xuezhe; Patil, Dinesh; Lexau, Jon; Liu, Frankie; Li, Guoliang; Thacker, Hiren; Luo, Ying; Shubin, Ivan; Li, Jieda; Yao, Jin; Dong, Po; Feng, Dazeng; Asghari, Mehdi; Pinguet, Thierry; Mekis, Attila; Amberg, Philip; Dayringer, Michael; Gainsley, Jon; Moghadam, Hesam Fathi; Alon, Elad; Raj, Kannan; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2011-03-14

    Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

  20. Through-Wafer Optical Interconnects For Multi-Wafer Wafer-Scale Integrated Architectures

    Science.gov (United States)

    Hornak, L. A.; Tewksbury, S. K.; Hatamian, M.; Ligtenberg, A.; Sugla, B.; Franzon, P.

    1986-12-01

    Hybrid mounting of optical components, combined perhaps with integrated optical waveguides and lenses on a large area silicon, wafer-scale integrated (WSI) electronic circuit provides one potential approach to combine advanced electronic and photonic functions. The desire to achieve a high degree of parallelism in multi-wafer WSI-based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and. providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While presently it is difficult for optical interconnects to compete with electrical interconnects in the wafer plane, it is appropriate to look at vertical optical interconnections between wafer planes since the corresponding conductive structures would be large in area and may impede system repairability. The ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages for multi-wafer WSI or other dense three-dimensional architectures. However, while optical waveguides are readily fabricated in the plane of the wafer, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one straightforward method of meeting this criterion. Using optical device technology operating at wavelengths beyond the ≍1.1μm Si absorption cutoff, low loss, through-wafer propagation between WSI circuit boards can be achieved over the distances of interest (≍1mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that the transmittance can be raised to ≍77% for n-type and to ≍97% for p-type silicon. Optical interconnect source

  1. Princeton VLSI Project.

    Science.gov (United States)

    1982-01-01

    and having no physical reality in the fabricated circuit. For example, in the program of fig. 2, the declaration vertical :metal specifies that the...can be given a name, provided that the name given has been declared as a rectangle of the standard simple type vitual . The relationship of the

  2. Silicides for VLSI applications

    CERN Document Server

    Murarka, Shyam P

    1983-01-01

    Most of the subject matter of this book has previously been available only in the form of research papers and review articles. I have not attempted to refer to all the published papers. The reader may find it advantageous to refer to the references listed.

  3. Research in VLSI Systems.

    Science.gov (United States)

    1983-04-01

    1Tltratech 900 wafer stepper. 6. Electron Beam Lithography. The Stanford MEBES machine has passed on-site acceptance and has been used to write several...Specifically, we will report on results obtained from the use of a MEBES electron beam lithography system for use in both mask making and direL-write...reticle, alignment, stepping distance, and exposure intensity information from the VAX to the Ultratech 900 Stepper. 4.2 Mlcrollthography MEBES had been

  4. Research in VLSI Systems.

    Science.gov (United States)

    1986-12-01

    This effort involves work both in optimizing compilers (Chow 83, ChowHenn 84], and code scheduling [ Gross 83, McFariing 86]. We are also looking at...which was begun 24 hours earjier. If the initial parametric data from CM1OI are marginal or worse, it is recommended tbat-CM142 be suspended until the...34 (CS412/EE391) is being offered for the first time this fall at Stanford. The course includes lectures on semiconductor manufaturing , existing

  5. Influence of gate tunneling currents on switched capacitor integrators

    Directory of Open Access Journals (Sweden)

    W. Kraus

    2009-05-01

    Full Text Available In order to achieve a higher level of integration in modern VLSI systems, not only the lateral geometrical dimensions have to be scaled. Lowering the supply voltage also requires scaling down the oxide thickness of the transistors. While the oxide thickness is scaled down proportionally with the supply voltage, the gate tunneling currents grow exponentially, which results in special issues concerning deviations in charge based analog and mixed signal circuitry. The influence of gate tunneling currents on this kind of circuits will be demonstrated at a fully differential switched capacitor integrator. The used process data is derived from the International Technology Roadmap for Semiconductors (ITRS Roadmap, 2006. The Parameter sets for the simulations are based on the Predictive Technology Model of the Arizona State University Modelling Group for the 65 nm Technology node (Predictive Technology Model, 2008.

  6. Global Detection of Live Virtual Machine Migration Based on Cellular Neural Networks

    Directory of Open Access Journals (Sweden)

    Kang Xie

    2014-01-01

    Full Text Available In order to meet the demands of operation monitoring of large scale, autoscaling, and heterogeneous virtual resources in the existing cloud computing, a new method of live virtual machine (VM migration detection algorithm based on the cellular neural networks (CNNs, is presented. Through analyzing the detection process, the parameter relationship of CNN is mapped as an optimization problem, in which improved particle swarm optimization algorithm based on bubble sort is used to solve the problem. Experimental results demonstrate that the proposed method can display the VM migration processing intuitively. Compared with the best fit heuristic algorithm, this approach reduces the processing time, and emerging evidence has indicated that this new approach is affordable to parallelism and analog very large scale integration (VLSI implementation allowing the VM migration detection to be performed better.

  7. Cellular Neural Network-Based Methods for Distributed Network Intrusion Detection

    Directory of Open Access Journals (Sweden)

    Kang Xie

    2015-01-01

    Full Text Available According to the problems of current distributed architecture intrusion detection systems (DIDS, a new online distributed intrusion detection model based on cellular neural network (CNN was proposed, in which discrete-time CNN (DTCNN was used as weak classifier in each local node and state-controlled CNN (SCCNN was used as global detection method, respectively. We further proposed a new method for design template parameters of SCCNN via solving Linear Matrix Inequality. Experimental results based on KDD CUP 99 dataset show its feasibility and effectiveness. Emerging evidence has indicated that this new approach is affordable to parallelism and analog very large scale integration (VLSI implementation which allows the distributed intrusion detection to be performed better.

  8. Space station automation study: Automation requirements derived from space manufacturing concepts. Volume 1: Executive summary

    Science.gov (United States)

    1984-01-01

    The electroepitaxial process and the Very Large Scale Integration (VLSI) circuits (chips) facilities were chosen because each requires a very high degree of automation, and therefore involved extensive use of teleoperators, robotics, process mechanization, and artificial intelligence. Both cover a raw materials process and a sophisticated multi-step process and are therfore highly representative of the kinds of difficult operation, maintenance, and repair challenges which can be expected for any type of space manufacturing facility. Generic areas were identified which will require significant further study. The initial design will be based on terrestrial state-of-the-art hard automation. One hundred candidate missions were evaluated on the basis of automation portential and availability of meaning ful knowldege. The design requirements and unconstrained design concepts developed for the two missions are presented.

  9. Optimization of block-matching algorithms using custom instruction-based paradigm on NIOS II microprocessors

    Science.gov (United States)

    González, Diego; Botella, Guillermo; Meyer-Bäse, Anke; Meyer-Bäse, Uwe

    2013-05-01

    This paper focuses on the optimization of video coding standards motion estimation algorithms using Altera Custom Instructions based-paradigm and the combination of SDRAM with On-Chip memory in NIOS II processors. On one hand a complete algorithm profiling is achieved before the optimization, in order to find the code time leaks, afterward is developing a custom instruction set which will be added to the specific embedded design enhancing the original system. On the other hand, all possible permitted memories combinations between On-Chip memory and SDRAM have been tested for achieving the best performance combination. The final performance of the final design (memory optimization and custom instruction acceleration) is shown. This contribution, thus, outlines a low cost system, mapped on a Very Large Scale Integration (VLSI) technology which accelerates software algorithms by converting them to custom hardware logic block and shows the best combination between On-Chip memory and SDRAM for the NIOS II processor.

  10. A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

    Directory of Open Access Journals (Sweden)

    Diego González

    2012-09-01

    Full Text Available This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA and NIOS II microprocessor applying a C to Hardware (C2H acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system.

  11. Method of Real-Time Principal-Component Analysis

    Science.gov (United States)

    Duong, Tuan; Duong, Vu

    2005-01-01

    Dominant-element-based gradient descent and dynamic initial learning rate (DOGEDYN) is a method of sequential principal-component analysis (PCA) that is well suited for such applications as data compression and extraction of features from sets of data. In comparison with a prior method of gradient-descent-based sequential PCA, this method offers a greater rate of learning convergence. Like the prior method, DOGEDYN can be implemented in software. However, the main advantage of DOGEDYN over the prior method lies in the facts that it requires less computation and can be implemented in simpler hardware. It should be possible to implement DOGEDYN in compact, low-power, very-large-scale integrated (VLSI) circuitry that could process data in real time.

  12. Bio-Inspired Neural Model for Learning Dynamic Models

    Science.gov (United States)

    Duong, Tuan; Duong, Vu; Suri, Ronald

    2009-01-01

    A neural-network mathematical model that, relative to prior such models, places greater emphasis on some of the temporal aspects of real neural physical processes, has been proposed as a basis for massively parallel, distributed algorithms that learn dynamic models of possibly complex external processes by means of learning rules that are local in space and time. The algorithms could be made to perform such functions as recognition and prediction of words in speech and of objects depicted in video images. The approach embodied in this model is said to be "hardware-friendly" in the following sense: The algorithms would be amenable to execution by special-purpose computers implemented as very-large-scale integrated (VLSI) circuits that would operate at relatively high speeds and low power demands.

  13. A Thermal Model for Carbon Nanotube Interconnects

    Directory of Open Access Journals (Sweden)

    Clay Mayberry

    2013-04-01

    Full Text Available In this work, we have studied Joule heating in carbon nanotube based very large scale integration (VLSI interconnects and incorporated Joule heating influenced scattering in our previously developed current transport model. The theoretical model explains breakdown in carbon nanotube resistance which limits the current density. We have also studied scattering parameters of carbon nanotube (CNT interconnects and compared with the earlier work. For 1 µm length single-wall carbon nanotube, 3 dB frequency in S12 parameter reduces to ~120 GHz from 1 THz considering Joule heating. It has been found that bias voltage has little effect on scattering parameters, while length has very strong effect on scattering parameters.

  14. Smart Sensors: Why and when the origin was and why and where the future will be

    Science.gov (United States)

    Corsi, C.

    2013-12-01

    Smart Sensors is a technique developed in the 70's when the processing capabilities, based on readout integrated with signal processing, was still far from the complexity needed in advanced IR surveillance and warning systems, because of the enormous amount of noise/unwanted signals emitted by operating scenario especially in military applications. The Smart Sensors technology was kept restricted within a close military environment exploding in applications and performances in the 90's years thanks to the impressive improvements in the integrated signal read-out and processing achieved by CCD-CMOS technologies in FPA. In fact the rapid advances of "very large scale integration" (VLSI) processor technology and mosaic EO detector array technology allowed to develop new generations of Smart Sensors with much improved signal processing by integrating microcomputers and other VLSI signal processors. inside the sensor structure achieving some basic functions of living eyes (dynamic stare, non-uniformity compensation, spatial and temporal filtering). New and future technologies (Nanotechnology, Bio-Organic Electronics, Bio-Computing) are lightning a new generation of Smart Sensors extending the Smartness from the Space-Time Domain to Spectroscopic Functional Multi-Domain Signal Processing. History and future forecasting of Smart Sensors will be reported.

  15. Integration of SPICE with TEK LV500 ASIC Design Verification System

    Directory of Open Access Journals (Sweden)

    A. Srivastava

    1996-01-01

    Full Text Available The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in ‘C’ language in UNIX ‘solaris 1.x’ environment has been developed between SPICE and the testing tools (TekWAVES and LV500. The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor.

  16. An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation.

    Science.gov (United States)

    Shih, Wei-Yeh; Liao, Jui-Chieh; Huang, Kuan-Ju; Fang, Wai-Chi; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2013-01-01

    This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90 nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1 s frame is 0.9763.

  17. Dynamic Neural Fields as a Step Towards Cognitive Neuromorphic Architectures

    Directory of Open Access Journals (Sweden)

    Yulia eSandamirskaya

    2014-01-01

    Full Text Available Dynamic Field Theory (DFT is an established framework for modelling embodied cognition. In DFT, elementary cognitive functions such as memory formation, formation of grounded representations, attentional processes, decision making, adaptation, and learning emerge from neuronal dynamics. The basic computational element of this framework is a Dynamic Neural Field (DNF. Under constraints on the time-scale of the dynamics, the DNF is computationally equivalent to a soft winner-take-all (WTA network, which is considered one of the basic computational units in neuronal processing. Recently, it has been shown how a WTA network may be implemented in neuromorphic hardware, such as analogue Very Large Scale Integration (VLSI device. This paper leverages the relationship between DFT and soft WTA networks to systematically revise and integrate established DFT mechanisms that have previously been spread among different architectures. In addition, I also identify some novel computational and architectural mechanisms of DFT which may be implemented in neuromorphic VLSI devices using WTA networks as an intermediate computational layer. These specific mechanisms include the stabilization of working memory, the coupling of sensory systems to motor dynamics, intentionality, and autonomous learning. I further demonstrate how all these elements may be integrated into a unified architecture to generate behavior and autonomous learning.

  18. Opportunities of CMOS-MEMS integration through LSI foundry and open facility

    Science.gov (United States)

    Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

    2017-06-01

    Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

  19. Smart sensors

    Science.gov (United States)

    Corsi, Carlo

    2006-08-01

    The term "Smart Sensors" refer to sensors which contain both sensing and signal processing capabilities with objectives ranging from simple viewing to sophisticated remote sensing, surveillance, search/track, weapon guidance, robotics, perceptronics and intelligence applications. In a broad sense, they include any sensor systems covering the whole electromagnetic spectrum: this paper deals specifically with a new class of smart sensors in infrared spectral bands whose developments started some years ago, when it was recognized that the rapid advances of "very large scale integration" (VLSI) processor technology and mosaic infrared detector array technology could be combined to develop new generations of infrared smart sensor systems with much improved performance. So, sophisticated signal processing operations have been developed for these new systems by integrating microcomputers and other VLSI signal processors within or next to the sensor arrays on the same focal plane avoiding complex computing located far away from the sensors. Recently this approach is achieving higher goals by a new and revolutionary sensors concept which introduce inside the sensor some of the basic function of living eyes, such as dynamic stare, dishomogenity compensation, spatial and temporal filtering. New objectives and requirements of these new focal plane processors are presented for this type of new infrared smart sensor systems. This paper is concerned with the processing techniques for only the front end of the focal plane processing, namely, the enhancement of target-to-noise ratio by background clutter suppression and the improvement in target detection by "smart" and pattern correlation threshold.

  20. Active processing of spatio-temporal input patterns in silicon dendrites.

    Science.gov (United States)

    Wang, Yingxue; Liu, Shih-Chii

    2013-06-01

    Capturing the functionality of active dendritic processing into abstract mathematical models will help us to understand the role of complex biophysical neurons in neuronal computation and to build future useful neuromorphic analog Very Large Scale Integrated (aVLSI) neuronal devices. Previous work based on an aVLSI multi-compartmental neuron model demonstrates that the compartmental response in the presence of either of two widely studied classes of active mechanisms, is a nonlinear sigmoidal function of the degree of either input temporal synchrony OR input clustering level. Using the same silicon model, this work expounds the interaction between both active mechanisms in a compartment receiving input patterns of varying temporal AND spatial clustering structure and demonstrates that this compartmental response can be captured by a combined sigmoid and radial-basis function over both input dimensions. This paper further shows that the response to input spatio-temporal patterns in a one-dimensional multi-compartmental dendrite, can be described by a radial-basis like function of the degree of temporal synchrony between the inter-compartmental inputs.

  1. Transistor analogs of emergent iono-neuronal dynamics

    Science.gov (United States)

    Rachmuth, Guy; Poon, Chi-Sang

    2008-01-01

    Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications. PMID:19404469

  2. Spiking Neural Classifier with Lumped Dendritic Nonlinearity and Binary Synapses: A Current Mode VLSI Implementation and Analysis.

    Science.gov (United States)

    Bhaduri, Aritra; Banerjee, Amitava; Roy, Subhrajit; Kar, Sougata; Basu, Arindam

    2017-12-08

    We present a neuromorphic current mode implementation of a spiking neural classifier with lumped square law dendritic nonlinearity. It has been shown previously in software simulations that such a system with binary synapses can be trained with structural plasticity algorithms to achieve comparable classification accuracy with fewer synaptic resources than conventional algorithms. We show that even in real analog systems with manufacturing imperfections (CV of 23.5% and 14.4% for dendritic branch gains and leaks respectively), this network is able to produce comparable results with fewer synaptic resources. The chip fabricated in [Formula: see text]m complementary metal oxide semiconductor has eight dendrites per cell and uses two opposing cells per class to cancel common-mode inputs. The chip can operate down to a [Formula: see text] V and dissipates 19 nW of static power per neuronal cell and [Formula: see text] 125 pJ/spike. For two-class classification problems of high-dimensional rate encoded binary patterns, the hardware achieves comparable performance as software implementation of the same with only about a 0.5% reduction in accuracy. On two UCI data sets, the IC integrated circuit has classification accuracy comparable to standard machine learners like support vector machines and extreme learning machines while using two to five times binary synapses. We also show that the system can operate on mean rate encoded spike patterns, as well as short bursts of spikes. To the best of our knowledge, this is the first attempt in hardware to perform classification exploiting dendritic properties and binary synapses.

  3. A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

    Directory of Open Access Journals (Sweden)

    D.Nirmal

    2014-07-01

    Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

  4. Monolithically integrated Si gate-controlled light-emitting device: science and properties

    Science.gov (United States)

    Xu, Kaikai

    2018-02-01

    The motivation of this study is to develop a p–n junction based light emitting device, in which the light emission is conventionally realized using reverse current driving, by voltage driving. By introducing an additional terminal of insulated gate for voltage driving, a novel three-terminal Si light emitting device is described where both the light intensity and spatial light pattern of the device are controlled by the gate voltage. The proposed light emitting device employs injection-enhanced Si in avalanche mode where electric field confinement occurs in the corner of a reverse-biased p+n junction. It is found that, depending on the bias conditions, the light intensity is either a linear or a quadratic function of the applied gate voltage or the reverse-bias. Since the light emission is based on the avalanching mode, the Si light emitting device offers the potential for very large scale integration-compatible light emitters for inter- or intra-chip signal transmission and contactless functional testing of wafers.

  5. Neuromorphic neural interfaces: from neurophysiological inspiration to biohybrid coupling with nervous systems

    Science.gov (United States)

    Broccard, Frédéric D.; Joshi, Siddharth; Wang, Jun; Cauwenberghs, Gert

    2017-08-01

    Objective. Computation in nervous systems operates with different computational primitives, and on different hardware, than traditional digital computation and is thus subjected to different constraints from its digital counterpart regarding the use of physical resources such as time, space and energy. In an effort to better understand neural computation on a physical medium with similar spatiotemporal and energetic constraints, the field of neuromorphic engineering aims to design and implement electronic systems that emulate in very large-scale integration (VLSI) hardware the organization and functions of neural systems at multiple levels of biological organization, from individual neurons up to large circuits and networks. Mixed analog/digital neuromorphic VLSI systems are compact, consume little power and operate in real time independently of the size and complexity of the model. Approach. This article highlights the current efforts to interface neuromorphic systems with neural systems at multiple levels of biological organization, from the synaptic to the system level, and discusses the prospects for future biohybrid systems with neuromorphic circuits of greater complexity. Main results. Single silicon neurons have been interfaced successfully with invertebrate and vertebrate neural networks. This approach allowed the investigation of neural properties that are inaccessible with traditional techniques while providing a realistic biological context not achievable with traditional numerical modeling methods. At the network level, populations of neurons are envisioned to communicate bidirectionally with neuromorphic processors of hundreds or thousands of silicon neurons. Recent work on brain-machine interfaces suggests that this is feasible with current neuromorphic technology. Significance. Biohybrid interfaces between biological neurons and VLSI neuromorphic systems of varying complexity have started to emerge in the literature. Primarily intended as a

  6. Monolithic ionizing particle detector based on active matrix of functionally integrated structures

    Energy Technology Data Exchange (ETDEWEB)

    Murashev, V.N. [National University of Science and Technology “MISIS” (Russian Federation); Legotin, S.A., E-mail: serlego@mail.ru [National University of Science and Technology “MISIS” (Russian Federation); Karmanov, D.E. [Lomonosov Moscow State University, Skobeltsyn Institute of Nuclear Physics (MSU SINP) (Russian Federation); Baryshnikov, F.M.; Didenko, S.I. [National University of Science and Technology “MISIS” (Russian Federation)

    2014-02-15

    Highlights: • A new type of monolithic silicon position detector is presented. • An operating principle, design and technology of the detector are described. • Calculated estimations of the detecting efficiency are carried out. • Experimental results of alpha-particle and electron detection are shown. -- Abstract: An operating principle, design and technology of a new type of the monolithic silicon position detector (MSPD) for registration of ionizing particles and photons are described. The detector represents a specialized monolithic silicon VLSI that contains a two-dimensional detecting matrix of active functionally integrated bipolar structures and peripheral electronic circuitry for signal amplification and processing. This paper presents experimental results of α-particles and electrons detection with position accuracy and operation speed better than 12.5 μm and 1 ns, respectively. The given estimations show the capabilities of this detector and its advantages in comparison with analogs.

  7. Integral or integrated marketing

    Directory of Open Access Journals (Sweden)

    Davčik Nebojša

    2006-01-01

    Full Text Available Marketing theorists and experts try to develop business efficient organization and to get marketing performance at higher, business integrated level since its earliest beginnings. The core issue in this paperwork is the dialectic and practical approach dilemma should we develop integrated or integral marketing approach in the organization. The presented company cases as well as dialectic and functional explanations of this dilemma clearly shows that integrated marketing is narrower approach than integral marketing if we take as focal point new, unique and completed entity. In the integration the essence is in getting different parts together, which do not have to make necessary the new entity. The key elements in the definition of the integral marketing are necessity and holistic, e.g. necessity to develop new, holistic entity.

  8. WINS. Market Simulation Tool for Facilitating Wind Energy Integration

    Energy Technology Data Exchange (ETDEWEB)

    Shahidehpour, Mohammad [Illinois Inst. of Technology, Chicago, IL (United States)

    2012-10-30

    Integrating 20% or more wind energy into the system and transmitting large sums of wind energy over long distances will require a decision making capability that can handle very large scale power systems with tens of thousands of buses and lines. There is a need to explore innovative analytical and implementation solutions for continuing reliable operations with the most economical integration of additional wind energy in power systems. A number of wind integration solution paths involve the adoption of new operating policies, dynamic scheduling of wind power across interties, pooling integration services, and adopting new transmission scheduling practices. Such practices can be examined by the decision tool developed by this project. This project developed a very efficient decision tool called Wind INtegration Simulator (WINS) and applied WINS to facilitate wind energy integration studies. WINS focused on augmenting the existing power utility capabilities to support collaborative planning, analysis, and wind integration project implementations. WINS also had the capability of simulating energy storage facilities so that feasibility studies of integrated wind energy system applications can be performed for systems with high wind energy penetrations. The development of WINS represents a major expansion of a very efficient decision tool called POwer Market Simulator (POMS), which was developed by IIT and has been used extensively for power system studies for decades. Specifically, WINS provides the following superiorities; (1) An integrated framework is included in WINS for the comprehensive modeling of DC transmission configurations, including mono-pole, bi-pole, tri-pole, back-to-back, and multi-terminal connection, as well as AC/DC converter models including current source converters (CSC) and voltage source converters (VSC); (2) An existing shortcoming of traditional decision tools for wind integration is the limited availability of user interface, i.e., decision

  9. Area-Efficient VLSI Computation.

    Science.gov (United States)

    1981-10-01

    1.2 A Simple Systolic Priority Queue Before we begin a formal treatment of systolic systems, it is worthwhile to consider an example. Many...be omput on the right, much as corn gocs through ith: 11N malid. \\ Vih , 1,,1 pir flF’lLk IlCks. 111C pri, ri. (1 ’lcuc ik, r1,cR l’d 1) cC I1.Ic U

  10. A Coherent VLSI Design Environment.

    Science.gov (United States)

    1986-03-31

    Thang Bui completed his Ph.D. thesis on graph-bisection algorithms. Included in the thesis is joint work with Profs. Leighton and Sipser on an algorithm... Sipser , "Graph Bisection Algorithms with Good Average Case Behavior," to appear in Combinatorica, F. Chung, T. Leighton and A. Rosenberg, "Embedding

  11. Analogue and Mixed-Signal Integrated Circuits for Space Applications

    CERN Document Server

    2014-01-01

    The purpose of AMICSA 2014 (organised in collaboration of ESA and CERN) is to provide an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

  12. Heterogeneous integration of epitaxial nanostructures: strategies and application drivers

    Science.gov (United States)

    Chui, Chi On; Shin, Kyeong-Sik; Kina, Jorge; Shih, Kun-Huan; Narayanan, Pritish; Moritz, C. Andras

    2012-10-01

    In order to sustain the historic progress in information processing, transmission, and storage, concurrent integration of heterogeneous functionality and materials with fine granularity is clearly imperative for the best connectivity, system performance, and density metrics. In this paper, we review recent developments in heterogeneous integration of epitaxial nanostructures for their applications toward our envisioned device-level heterogeneity using computing nanofabrics. We first identify the unmet need for heterogeneous integration in modern nanoelectronics and review state-of-the-art assembly approaches for nanoscale computing fabrics. We also discuss the novel circuit application driver, known as Nanoscale Application Specific Integrated Circuits (NASICs), which promises an overall performance-power-density advantage over CMOS and embeds built-in defect and parameter variation resilience. At the device-level, we propose an innovative cross-nanowire field-effect transistor (xnwFET) structure that simultaneously offers high performance, low parasitics, good electrostatic control, ease-of-manufacturability, and resilience to process variation. In addition, we specify technology requirements for heterogeneous integration and present two wafer-scale strategies. The first strategy is based on ex situ assembly and stamping transfer of pre-synthesized epitaxial nanostructures that allows tight control over key nanofabric parameters. The second strategy is based on lithographic definition of epitaxial nanostructures on native substrates followed by their stamping transfer using VLSI foundry processes. Finally, we demonstrate the successful concurrent heterogeneous co-integration of silicon and III-V compound semiconductor epitaxial nanowire arrays onto the same hosting substrate over large area, at multiple locations, with fine granularity, close proximity and high yield.

  13. Integration and Integrity.

    Science.gov (United States)

    Cassano, Paul; Antol, Rayna A.

    2001-01-01

    Explains two middle school teachers' cooperation with integrating regular and gifted students with disabled students. Focuses on disabled students' collaboration with their peers and their social skill development rather than their academic development. (YDS)

  14. Block QCA Fault-Tolerant Logic Gates

    Science.gov (United States)

    Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

    2003-01-01

    Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA

  15. Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT in a Digital Radio Mondiale (DRM and DRM+ Receiver

    Directory of Open Access Journals (Sweden)

    Sheau-Fang Lei

    2013-05-01

    Full Text Available This paper presents a compact structure of recursive discrete Fourier transform (RDFT with prime factor (PF and common factor (CF algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point DFT computation, the results show that the proposed method greatly reduces the number of multiplications/additions/computational cycles by 97.40/94.31/46.50% compared to a recent approach. In chip realization, the core size and chip size are, respectively, 0.84 × 0.84 and 1.38 × 1.38 mm2. The power consumption for the 288- and 256-point DFT computations are, respectively, 10.2 (or 0.1051 and 11.5 (or 0.1176 mW at 25 (or 0.273 MHz simulated by NanoSim. It would be more efficient and more suitable than previous works for DRM and DRM+ applications.

  16. GaAs integrated circuits and heterojunction devices

    Science.gov (United States)

    Fowlis, Colin

    1986-06-01

    The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

  17. Cavalieri integration

    CSIR Research Space (South Africa)

    Ackermann, ER

    2012-09-01

    Full Text Available We use Cavalieri’s principle to develop a novel integration technique which we call Cavalieri integration. Cavalieri integrals differ from Riemann integrals in that non-rectangular integration strips are used. In this way we can use single Cavalieri...

  18. Imbalance aware lithography hotspot detection: a deep learning approach

    Science.gov (United States)

    Yang, Haoyu; Luo, Luyang; Su, Jing; Lin, Chenxi; Yu, Bei

    2017-07-01

    With the advancement of very large scale integrated circuits (VLSI) technology nodes, lithographic hotspots become a serious problem that affects manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with the extreme scaling of transistor feature size and layout patterns growing in complexity, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. We present a deep convolutional neural network (CNN) that targets representative feature learning in lithography hotspot detection. We carefully analyze the impact and effectiveness of different CNN hyperparameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always in the minority in VLSI mask design, the training dataset is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from a high number of false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply hotspot upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

  19. Integral trees and integral graphs

    NARCIS (Netherlands)

    Wang, Ligong

    2005-01-01

    This monograph deals with integral graphs, Laplacian integral regular graphs, cospectral graphs and cospectral integral graphs. The organization of this work, which consists of eight chapters, is as follows.

  20. Stochastic Integrals

    OpenAIRE

    Karal, David

    2014-01-01

    Stochastic Integrals David Karal Abstrakt In this thesis we study the Wiener process and stochastic integrals. The thesis defines the basic objects of stochastic analysis and the existence of the Wiener process and some of its properties are shown. This process is then used to con- struct the Itô stochastic integral, where the Wiener process acts as an integrator. The Itô stochastic integral is first defined for simple processes and subsequently extended to mathcalFt-progressively measurable ...

  1. Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform

    Directory of Open Access Journals (Sweden)

    Priyanka Mekala

    2013-01-01

    Full Text Available Hardware/software (HW/SW cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA technology is presented in this paper. The major contributions of this work are: (1 a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL to reduce memory consumption and load on the processor. (2 The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z. (3 The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.

  2. A HARDWARE IMPLEMENTATION OF PUNCTURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

    Directory of Open Access Journals (Sweden)

    E. García,

    2005-08-01

    Full Text Available This paper presents a VLSI (Very Large Scale Integration implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

  3. Efficient physical embedding of topologically complex information processing networks in brains and computer circuits.

    Directory of Open Access Journals (Sweden)

    Danielle S Bassett

    2010-04-01

    Full Text Available Nervous systems are information processing networks that evolved by natural selection, whereas very large scale integrated (VLSI computer circuits have evolved by commercially driven technology development. Here we follow historic intuition that all physical information processing systems will share key organizational properties, such as modularity, that generally confer adaptivity of function. It has long been observed that modular VLSI circuits demonstrate an isometric scaling relationship between the number of processing elements and the number of connections, known as Rent's rule, which is related to the dimensionality of the circuit's interconnect topology and its logical capacity. We show that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity. We further show that the estimated Rent exponent of human brain networks, derived from MRI data, can explain the allometric scaling relations between gray and white matter volumes across a wide range of mammalian species, again suggesting that these principles of nervous system design are highly conserved. For each of these fractal modular networks, the dimensionality of the interconnect topology was greater than the 2 or 3 Euclidean dimensions of the space in which it was embedded. This relatively high complexity entailed extra cost in physical wiring: although all networks were economically or cost-efficiently wired they did not strictly minimize wiring costs. Artificial and biological information processing systems both may evolve to optimize a trade-off between physical cost and topological complexity, resulting in the emergence of homologous principles of economical, fractal and modular design across many different kinds of nervous and computational networks.

  4. CHICSi-a compact ultra-high vacuum compatible detector system for nuclear reaction experiments at storage rings. III. readout system

    Science.gov (United States)

    Carlén, L.; Førre, G.; Golubev, P.; Jakobsson, B.; Kolozhvari, A.; Marciniewski, P.; Siwek, A.; van Veldhuizen, E. J.; Westerberg, L.; Whitlow, H. J.; Østby, J. M.

    2004-01-01

    (CHICSi) Celsius Heavy Ion Collaboration Si detector system is a high granularity, modular detector telescope array for operation around the cluster-jet target/circulating beam intersection of the CELSIUS storage ring at the The. Svedberg Laboratory in Uppsala, Sweden. It is able to provide identity and momentum vector of up to 100 charged particles and fragments from proton-nucleus and nucleus-nucleus collisions at intermediate energies, 50-1000AMeV. All detector telescopes as well as the major part of electronic readout system are placed inside the target chamber in ultra-high vacuum (UHV, 10-9-10-7Pa). This requires Very Large Scale Integrated (VLSI) microchip for the spectroscopic signal processing and the generation and transport of digital control signals. Eighteen telescopes, read out with chip-on-board technique by ceramics Mother Boards (MB) and corresponding 18 microchips are mounted on a 450×45mm2 Grand Mother Board (GMB), processed on FR4 glass-fibre material. Each of these 28GMB units contains a daisy-chain organisation of the VLSI chips and associated protection circuits. Analogue-to-digital conversion of the spectroscopic signals is performed on a board outside the chamber which is connected on one side to a power distribution board, directly attached to a UHV mounting flange, and on the other side to the VME-based data acquisition system (CHICSiDAQ). This in its turn is connected via a fibre-optic link to the general TSL acquisition system (SVEDAQ), and in this way data from auxiliary detector systems, read out in CAMAC mode, can be stored in coincidence with CHICSi data.

  5. Efficient physical embedding of topologically complex information processing networks in brains and computer circuits.

    Science.gov (United States)

    Bassett, Danielle S; Greenfield, Daniel L; Meyer-Lindenberg, Andreas; Weinberger, Daniel R; Moore, Simon W; Bullmore, Edward T

    2010-04-22

    Nervous systems are information processing networks that evolved by natural selection, whereas very large scale integrated (VLSI) computer circuits have evolved by commercially driven technology development. Here we follow historic intuition that all physical information processing systems will share key organizational properties, such as modularity, that generally confer adaptivity of function. It has long been observed that modular VLSI circuits demonstrate an isometric scaling relationship between the number of processing elements and the number of connections, known as Rent's rule, which is related to the dimensionality of the circuit's interconnect topology and its logical capacity. We show that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity. We further show that the estimated Rent exponent of human brain networks, derived from MRI data, can explain the allometric scaling relations between gray and white matter volumes across a wide range of mammalian species, again suggesting that these principles of nervous system design are highly conserved. For each of these fractal modular networks, the dimensionality of the interconnect topology was greater than the 2 or 3 Euclidean dimensions of the space in which it was embedded. This relatively high complexity entailed extra cost in physical wiring: although all networks were economically or cost-efficiently wired they did not strictly minimize wiring costs. Artificial and biological information processing systems both may evolve to optimize a trade-off between physical cost and topological complexity, resulting in the emergence of homologous principles of economical, fractal and modular design across many different kinds of nervous and computational networks.

  6. A Digital Liquid State Machine With Biologically Inspired Learning and Its Application to Speech Recognition.

    Science.gov (United States)

    Zhang, Yong; Li, Peng; Jin, Yingyezhe; Choe, Yoonsuck

    2015-11-01

    This paper presents a bioinspired digital liquid-state machine (LSM) for low-power very-large-scale-integration (VLSI)-based machine learning applications. To the best of the authors' knowledge, this is the first work that employs a bioinspired spike-based learning algorithm for the LSM. With the proposed online learning, the LSM extracts information from input patterns on the fly without needing intermediate data storage as required in offline learning methods such as ridge regression. The proposed learning rule is local such that each synaptic weight update is based only upon the firing activities of the corresponding presynaptic and postsynaptic neurons without incurring global communications across the neural network. Compared with the backpropagation-based learning, the locality of computation in the proposed approach lends itself to efficient parallel VLSI implementation. We use subsets of the TI46 speech corpus to benchmark the bioinspired digital LSM. To reduce the complexity of the spiking neural network model without performance degradation for speech recognition, we study the impacts of synaptic models on the fading memory of the reservoir and hence the network performance. Moreover, we examine the tradeoffs between synaptic weight resolution, reservoir size, and recognition performance and present techniques to further reduce the overhead of hardware implementation. Our simulation results show that in terms of isolated word recognition evaluated using the TI46 speech corpus, the proposed digital LSM rivals the state-of-the-art hidden Markov-model-based recognizer Sphinx-4 and outperforms all other reported recognizers including the ones that are based upon the LSM or neural networks.

  7. Curriculum Integration.

    Science.gov (United States)

    Gibbons, J. A.

    1979-01-01

    This essay addresses the problem of the nature of curriculum integration, and an attempt is made to lay the basis for a theory of integration. An aspect of the relationship between mathematics and physics is discussed. (Author/MLF)

  8. Gauge Integral

    OpenAIRE

    Coghetto Roland

    2017-01-01

    Some authors have formalized the integral in the Mizar Mathematical Library (MML). The first article in a series on the Darboux/Riemann integral was written by Noboru Endou and Artur Korniłowicz: [6]. The Lebesgue integral was formalized a little later [13] and recently the integral of Riemann-Stieltjes was introduced in the MML by Keiko Narita, Kazuhisa Nakasho and Yasunari Shidama [12].

  9. Gauge Integral

    Directory of Open Access Journals (Sweden)

    Coghetto Roland

    2017-10-01

    Full Text Available Some authors have formalized the integral in the Mizar Mathematical Library (MML. The first article in a series on the Darboux/Riemann integral was written by Noboru Endou and Artur Korniłowicz: [6]. The Lebesgue integral was formalized a little later [13] and recently the integral of Riemann-Stieltjes was introduced in the MML by Keiko Narita, Kazuhisa Nakasho and Yasunari Shidama [12].

  10. Teaching Integrity

    Science.gov (United States)

    Saunders, Sue; Butts, Jennifer Lease

    2011-01-01

    Integrity is one of those essential yet highly ambiguous concepts. For the purpose of this chapter, integrity is defined as that combination of both attributes and actions that makes entities appear to be whole and ethical, as well as consistent. Like the concepts of leadership or wisdom or community or collaboration, integrity is a key element of…

  11. Riemann Integration

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 11; Issue 11. Riemann Integration. Dilip P Patil. General Article Volume 11 Issue 11 November 2006 pp 61-80 ... Keywords. Area; lower and upper sums; Riemann sums; integrable functions; definite integral; derivative; primitive; anti-derivative.

  12. VECTOR INTEGRATION

    NARCIS (Netherlands)

    Thomas, E. G. F.

    2012-01-01

    This paper deals with the theory of integration of scalar functions with respect to a measure with values in a, not necessarily locally convex, topological vector space. It focuses on the extension of such integrals from bounded measurable functions to the class of integrable functions, proving

  13. Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory

    Energy Technology Data Exchange (ETDEWEB)

    Liu, T.; Deptuch, G.; Hoff, J.; Jindariani, S.; Joshi, S.; Olsen, J.; Tran, N.; Trimpl, M.

    2015-02-01

    An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking, in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.

  14. FPGA Implementation of a CORDIC-Based Joint Angle Processor for a Climbing Robot

    Directory of Open Access Journals (Sweden)

    Ying-Shen Juang

    2013-04-01

    Full Text Available This paper presents a novel architecture of a joint angle processor for a robot arm. The objective of the proposed coordinate, rotation, digital computer (CORDIC-based joint angle processor is to provide a hardware solution for computing the inverse kinematic for a robot arm control system. The complicated trigonometry operation is computed by the famous CORDIC algorithm. Simulation results show that the proposed joint angle processor achieves high precision. Moreover, an efficient pipelined architecture for very large scale integration (VLSI and field programmable gate array (FPGA implementation is also proposed, this architecture has the advantage of saving hardware cost and power consumption. As a result, the proposed CORDIC-based joint angle processor provides a high speed inverse kinematic computation that assists the main micro-control-unit (MCU to operate the robot arm in real time. Therefore, the motion of the robot will be very smooth, capable of powering multiple joints at same time and provide smooth walking or climbing motions.

  15. A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

    Directory of Open Access Journals (Sweden)

    Jian (Denny Lin

    2014-05-01

    Full Text Available With the advanced technology used to design VLSI (Very Large Scale Integration circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.

  16. An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

    Science.gov (United States)

    Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2014-01-01

    This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

  17. Hardware architecture and cutting-edge assembly process of a tiny curved compound eye.

    Science.gov (United States)

    Viollet, Stéphane; Godiot, Stéphanie; Leitel, Robert; Buss, Wolfgang; Breugnon, Patrick; Menouni, Mohsine; Juston, Raphaël; Expert, Fabien; Colonnier, Fabien; L'Eplattenier, Géraud; Brückner, Andreas; Kraze, Felix; Mallot, Hanspeter; Franceschini, Nicolas; Pericet-Camara, Ramon; Ruffier, Franck; Floreano, Dario

    2014-11-17

    The demand for bendable sensors increases constantly in the challenging field of soft and micro-scale robotics. We present here, in more detail, the flexible, functional, insect-inspired curved artificial compound eye (CurvACE) that was previously introduced in the Proceedings of the National Academy of Sciences (PNAS, 2013). This cylindrically-bent sensor with a large panoramic field-of-view of 180° × 60° composed of 630 artificial ommatidia weighs only 1.75 g, is extremely compact and power-lean (0.9 W), while it achieves unique visual motion sensing performance (1950 frames per second) in a five-decade range of illuminance. In particular, this paper details the innovative Very Large Scale Integration (VLSI) sensing layout, the accurate assembly fabrication process, the innovative, new fast read-out interface, as well as the auto-adaptive dynamic response of the CurvACE sensor. Starting from photodetectors and microoptics on wafer substrates and flexible printed circuit board, the complete assembly of CurvACE was performed in a planar configuration, ensuring high alignment accuracy and compatibility with state-of-the art assembling processes. The characteristics of the photodetector of one artificial ommatidium have been assessed in terms of their dynamic response to light steps. We also characterized the local auto-adaptability of CurvACE photodetectors in response to large illuminance changes: this feature will certainly be of great interest for future applications in real indoor and outdoor environments.

  18. Visi—A VTK- and QT-Based Open-Source Project for Scientific Data Visualization

    Science.gov (United States)

    Li, Yiming; Chen, Cheng-Kai

    2009-03-01

    In this paper, we present an open-source project, Visi for high-dimensional engineering and scientific data visualization. Visi is with state-of-the-art interactive user interface and graphics kernels based upon Qt (a cross-platform GUI toolkit) and VTK (an object-oriented visualization library). For an initialization of Visi, a preliminary window will be activated by Qt, and the kernel of VTK is simultaneously embedded into the window, where the graphics resources are allocated. Representation of visualization is through an interactive interface so that the data will be rendered according to user's preference. The developed framework possesses high flexibility and extensibility for advanced functions (e.g., object combination, etc) and further applications. Application of Visi to data visualization in various fields, such as protein structure in bioinformatics, 3D semiconductor transistor, and interconnect of very-large scale integration (VLSI) layout is also illustrated to show the performance of Visi. The developed open-source project is available in our project website on the internet [1].

  19. Towards a comprehensive model for a resonant nanoelectromechanical system

    Science.gov (United States)

    Calvert, S. L.; Shen, Y.; Sabater, A. B.; Mohammadi, S.; Rhoads, J. F.

    2015-09-01

    The mass production and very large scale integration (VLSI) of micro/nanoelectromechanical systems (M/NEMS) requires the development and use of accurate models and simulations, which are capable of rapidly evaluating potential designs. Because of the large range of applications that have been proposed for M/NEMS, the most useful models are those that can accurately capture a system’s response under widely varying input and operating conditions. This allows the M/NEMS devices to be treated as well understood circuit components in simulation contexts. It is towards this end that a first-principles based model is proposed for a resonant nanosystem inclusive of an electrostatically-actuated fixed-fixed beam resonator, test equipment and system parasitics. By encoding the algebraic and differential equations which describe the system into circuit components using Verilog-A, an experimental test setup was simulated using Spectre and subsequently compared to experimental results for qualitative validation of the model. The simulation was then used to investigate the behavior of a representative device for a basic input configuration that more closely represents a final-use scenario for the nanoresonator. Discrepancies between the commonly-employed experimental methodology and the practical final-use scenario are discussed and used as a platform to encourage the development of improved experimental methodologies, while also emphasizing the need for robust and accurate system-level models.

  20. Hardware Architecture and Cutting-Edge Assembly Process of a Tiny Curved Compound Eye

    Directory of Open Access Journals (Sweden)

    Stéphane Viollet

    2014-11-01

    Full Text Available The demand for bendable sensors increases constantly in the challenging field of soft and micro-scale robotics. We present here, in more detail, the flexible, functional, insect-inspired curved artificial compound eye (CurvACE that was previously introduced in the Proceedings of the National Academy of Sciences (PNAS, 2013. This cylindrically-bent sensor with a large panoramic field-of-view of \\(180^\\circ\\ \\(\\times\\ \\(60^\\circ\\composed of 630 artificial ommatidia weighs only 1.75 g, is extremely compact and power-lean (0.9 W, while it achieves unique visual motion sensing performance (1950 frames per second in a five-decade range of illuminance. In particular, this paper details the innovative Very Large Scale Integration (VLSI sensing layout, the accurate assembly fabrication process, the innovative, new fast read-out interface, as well as the auto-adaptive dynamic response of the CurvACE sensor. Starting from photodetectors and microoptics on wafer substrates and flexible printed circuit board, the complete assembly of CurvACE was performed in a planar configuration, ensuring high alignment accuracy and compatibility with state-of-the art assembling processes. The characteristics of the photodetector of one artificial ommatidium have been assessed in terms of their dynamic response to light steps. We also characterized the local auto-adaptability of CurvACE photodetectors in response to large illuminance changes: this feature will certainly be of great interest for future applications in real indoor and outdoor environments.

  1. A Review of Current Neuromorphic Approaches for Vision, Auditory, and Olfactory Sensors.

    Science.gov (United States)

    Vanarse, Anup; Osseiran, Adam; Rassau, Alexander

    2016-01-01

    Conventional vision, auditory, and olfactory sensors generate large volumes of redundant data and as a result tend to consume excessive power. To address these shortcomings, neuromorphic sensors have been developed. These sensors mimic the neuro-biological architecture of sensory organs using aVLSI (analog Very Large Scale Integration) and generate asynchronous spiking output that represents sensing information in ways that are similar to neural signals. This allows for much lower power consumption due to an ability to extract useful sensory information from sparse captured data. The foundation for research in neuromorphic sensors was laid more than two decades ago, but recent developments in understanding of biological sensing and advanced electronics, have stimulated research on sophisticated neuromorphic sensors that provide numerous advantages over conventional sensors. In this paper, we review the current state-of-the-art in neuromorphic implementation of vision, auditory, and olfactory sensors and identify key contributions across these fields. Bringing together these key contributions we suggest a future research direction for further development of the neuromorphic sensing field.

  2. Implicit methods for qualitative modeling of gene regulatory networks.

    Science.gov (United States)

    Garg, Abhishek; Mohanram, Kartik; De Micheli, Giovanni; Xenarios, Ioannis

    2012-01-01

    Advancements in high-throughput technologies to measure increasingly complex biological phenomena at the genomic level are rapidly changing the face of biological research from the single-gene single-protein experimental approach to studying the behavior of a gene in the context of the entire genome (and proteome). This shift in research methodologies has resulted in a new field of network biology that deals with modeling cellular behavior in terms of network structures such as signaling pathways and gene regulatory networks. In these networks, different biological entities such as genes, proteins, and metabolites interact with each other, giving rise to a dynamical system. Even though there exists a mature field of dynamical systems theory to model such network structures, some technical challenges are unique to biology such as the inability to measure precise kinetic information on gene-gene or gene-protein interactions and the need to model increasingly large networks comprising thousands of nodes. These challenges have renewed interest in developing new computational techniques for modeling complex biological systems. This chapter presents a modeling framework based on Boolean algebra and finite-state machines that are reminiscent of the approach used for digital circuit synthesis and simulation in the field of very-large-scale integration (VLSI). The proposed formalism enables a common mathematical framework to develop computational techniques for modeling different aspects of the regulatory networks such as steady-state behavior, stochasticity, and gene perturbation experiments.

  3. Performances of photodiode detectors for top and bottom counting detectors of ISS-CREAM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Hyun, H.J. [Kyungpook National University, Daegu 702-701 (Korea, Republic of); Anderson, T. [Pennsylvania State University, University Park, PA 16802 (United States); Angelaszek, D. [University of Maryland, College Park, MD 20740 (United States); Baek, S.J. [Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Copley, M. [University of Maryland, College Park, MD 20740 (United States); Coutu, S. [Pennsylvania State University, University Park, PA 16802 (United States); Han, J.H.; Huh, H.G. [University of Maryland, College Park, MD 20740 (United States); Hwang, Y.S. [Kyungpook National University, Daegu 702-701 (Korea, Republic of); Im, S. [Pennsylvania State University, University Park, PA 16802 (United States); Jeon, H.B.; Kah, D.H.; Kang, K.H.; Kim, H.J. [Kyungpook National University, Daegu 702-701 (Korea, Republic of); Kim, K.C.; Kwashnak, K. [University of Maryland, College Park, MD 20740 (United States); Lee, J. [Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Lee, M.H. [University of Maryland, College Park, MD 20740 (United States); Link, J.T. [NASA GSFC, Greenbelt, MD 20771 (United States); CRESST(USRA), Columbia, MD 21044 (United States); Lutz, L. [University of Maryland, College Park, MD 20740 (United States); and others

    2015-07-01

    The Cosmic Ray Energetics and Mass (CREAM) experiment at the International Space Station (ISS) aims to elucidate the source and acceleration mechanisms of high-energy cosmic rays by measuring the energy spectra from protons to iron. The instrument is planned for launch in 2015 at the ISS, and it comprises a silicon charge detector, a carbon target, top and bottom counting detectors, a calorimeter, and a boronated scintillator detector. The top and bottom counting detectors are developed for separating the electrons from the protons, and each of them comprises a plastic scintillator and a 20×20 silicon photodiode array. Each photodiode is 2.3 cm×2.3 cm in size and exhibits good electrical characteristics. The leakage current is measured to be less than 20 nA/cm{sup 2} at an operating voltage. The signal-to-noise ratio is measured to be better than 70 using commercial electronics, and the radiation hardness is tested using a proton beam. A signal from the photodiode is amplified by VLSI (very-large-scale integration) charge amp/hold circuits, the VA-TA viking chip. Environmental tests are performed using whole assembled photodiode detectors of a flight version. Herein, we present the characteristics of the developed photodiode along with the results of the environmental tests.

  4. A Novel Step-Doping Fully-Depleted Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor for Reliable Deep Sub-micron Devices

    Science.gov (United States)

    Elahipanah, Hossein; Orouji, Ali A.

    2009-11-01

    For first time, we report a novel deep sub-micron fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor (FD SOI MOSFET) where the channel layer consists of two sections with a step doping (SD) region in order to increase performance and reliability of the device. This new structure that called SD FD SOI structure (SDFD-SOI MOSFET), were used for reaching suitable threshold voltage upon device scaling and reliability improvement. We demonstrate that the electric field was modified in the channel and common peak near the source junction have been reduced in the SDFD-SOI structure. The device demonstrates large enhancements in performance areas such as current drive capability, output resistance, hot-carrier reliability and threshold voltage roll-off. It was found that the device performance is very much dependent upon the SD region parameters. Simulation results show that the proposed structure improved on/off current ratio, and saturated output characteristics compared with conventional SOI structure (C-SOI MOSFET). Also, it was shown that substrate current of SDFD-SOI MOSFET is much lower than the C-SOI MOSFET which presented the lower hot-carrier degradation in proposed MOSFET. Results show that the most short-channel problems in very large scale integrated circuits (VLSI) could be solved and the proposed SDFD-SOI MOSFETs can work very well in deep sub-micron and nanoscale regime.

  5. Architectural optimizations for low-power K-best MIMO decoders

    KAUST Repository

    Mondal, Sudip

    2009-09-01

    Maximum-likelihood (ML) detection for higher order multiple-input-multiple-output (MIMO) systems faces a major challenge in computational complexity. This limits the practicality of these systems from an implementation point of view, particularly for mobile battery-operated devices. In this paper, we propose a modified approach for MIMO detection, which takes advantage of the quadratic-amplitude modulation (QAM) constellation structure to accelerate the detection procedure. This approach achieves low-power operation by extending the minimum number of paths and reducing the number of required computations for each path extension, which results in an order-of-magnitude reduction in computations in comparison with existing algorithms. This paper also describes the very-large-scale integration (VLSI) design of the low-power path metric computation unit. The approach is applied to a 4 × 4, 64-QAM MIMO detector system. Results show negligible performance degradation compared with conventional algorithms while reducing the complexity by more than 50%. © 2009 IEEE.

  6. 3D-FBK Pixel sensors: recent beam tests results with irradiated devices

    CERN Document Server

    Micelli, A; Sandaker, H; Stugu, B; Barbero, M; Hugging, F; Karagounis, M; Kostyukhin, V; Kruger, H; Tsung, J W; Wermes, N; Capua, M; Fazio, S; Mastroberardino, A; Susinno, G; Gallrapp, C; Di Girolamo, B; Dobos, D; La Rosa, A; Pernegger, H; Roe, S; Slavicek, T; Pospisil, S; Jakobs, K; Kohler, M; Parzefall, U; Darbo, G; Gariano, G; Gemme, C; Rovani, A; Ruscino, E; Butter, C; Bates, R; Oshea, V; Parker, S; Cavalli-Sforza, M; Grinstein, S; Korokolov, I; Pradilla, C; Einsweiler, K; Garcia-Sciveres, M; Borri, M; Da Via, C; Freestone, J; Kolya, S; Lai, C H; Nellist, C; Pater, J; Thompson, R; Watts, S J; Hoeferkamp, M; Seidel, S; Bolle, E; Gjersdal, H; Sjobaek, K N; Stapnes, S; Rohne, O; Su, D; Young, C; Hansson, P; Grenier, P; Hasi, J; Kenney, C; Kocian, M; Jackson, P; Silverstein, D; Davetak, H; DeWilde, B; Tsybychev, D; Dalla Betta, G F; Gabos, P; Povoli, M; Cobal, M; Giordani, M P; Selmi, L; Cristofoli, A; Esseni, D; Palestri, P; Fleta, C; Lozano, M; Pellegrini, G; Boscardin, M; Bagolini, A; Piemonte, C; Ronchin, S; Zorzi, N; Hansen, T E; Hansen, T; Kok, A; Lietaer, N; Kalliopuska, J; Oja, A

    2011-01-01

    The Pixel detector is the innermost part of the ATLAS experiment tracking device at the Large Hadron Collider (LHC), and plays a key role in the reconstruction of the primary and secondary vertices of short-lived particles. To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology is an innovative combination of very-large-scale integration (VLSI) and Micro-Electro-Mechanical-Systems (MEMS) where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. This paper reports on the 2010 June beam test results for irradi...

  7. Interorganisational Integration

    DEFF Research Database (Denmark)

    Lyngsø, Anne Marie; Godtfredsen, Nina Skavlan; Frølich, Anne

    2016-01-01

    INTRODUCTION: Despite many initiatives to improve coordination of patient pathways and intersectoral cooperation, Danish health care is still fragmented, lacking intra- and interorganisational integration. This study explores barriers to and facilitators of interorganisational integration...... at a university hospital in the Capital Region of Denmark. RESULTS AND DISCUSSION: Our results can be grouped into five influencing areas for interorganisational integration: communication/information transfer, committed leadership, patient engagement, the role and competencies of the general practitioner...... and organisational culture. Proposed solutions to barriers in each area hold the potential to improve care integration as experienced by individuals responsible for supporting and facilitating it. Barriers and facilitators to integrating care relate to clinical, professional, functional and normative integration...

  8. 'Migration & Integration'

    OpenAIRE

    Lisa Pilgram

    2011-01-01

    Migration, Integration : [kommunalpolitische Herausforderungen]. - Augsburg : Geo-Anwenderzentrum, [ca. 2004]. - XVIII, 281 S. - (Angewandte Sozialgeographie ; 49) (GEO-Taschenbuch). - Zugl.: Augsburg, Univ., Diss., 2003

  9. Integral equations

    CERN Document Server

    Moiseiwitsch, B L

    2005-01-01

    Two distinct but related approaches hold the solutions to many mathematical problems--the forms of expression known as differential and integral equations. The method employed by the integral equation approach specifically includes the boundary conditions, which confers a valuable advantage. In addition, the integral equation approach leads naturally to the solution of the problem--under suitable conditions--in the form of an infinite series.Geared toward upper-level undergraduate students, this text focuses chiefly upon linear integral equations. It begins with a straightforward account, acco

  10. Integrability detectors

    Indian Academy of Sciences (India)

    2015-10-29

    Oct 29, 2015 ... Abstract. In this short review, we present some applications and historical facts about the integrability detectors: Painlevé analysis, singularity confinement and algebraic entropy.

  11. Integrated Circuit For Simulation Of Neural Network

    Science.gov (United States)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  12. HOW INTEGRATED IS INTEGRATED LOGISTICS?

    OpenAIRE

    P.J. Pretorius

    2012-01-01

    Industry and academia still have a major problem in grasping the extent and relationships ofall functions involved in integrated logistics. This is because business logistics and logistics engineering developed separately, each with their own following, resulting in the two so-called different -disciplines ignoring each other.

    By analysing the definition of integrated logistic support, it is possible to identify the necessary conditions for an integrated logistics model. From these ne...

  13. Integrated Design

    DEFF Research Database (Denmark)

    Lenau, Torben Anker

    1999-01-01

    A homepage on the internet with course material, lecture plan, student exercises, etc. Continuesly updated during the course Integrated Design (80402, 80403)......A homepage on the internet with course material, lecture plan, student exercises, etc. Continuesly updated during the course Integrated Design (80402, 80403)...

  14. Organising integration

    DEFF Research Database (Denmark)

    Axelsson, Runo

    2013-01-01

    Background: In Sweden, as in many other countries, there has been a succession of trends in the organisation of health care and other welfare services. These trends have had different implications for the integration of services in the health and welfare system. Aims: One aim is to discuss...... the implications of different organisational trends for the integration of health and welfare services. Another aim is to introduce a Swedish model of financial coordination as a flexible way to organise integration. Organisational trends: In the 1960’s there was an expansion of health and welfare services leading...... an increasing lack of integration in the health and welfare system. In the 2000’s, there has been a re-centralisation through mergers of hospitals, regions and state agencies. It has become clear, however, that mergers do not promote integration but rather increase the bureaucratisation of the system. Model...

  15. The integration of immigrants

    OpenAIRE

    Bauböck, Rainer

    1995-01-01

    from the Table of Contents: Migration and integration - Basic concepts and definitions; Immigration and Integration policies; The legal framework for integration; Dimension of social integration; Cultural integration; Conclusions;

  16. Stochastic integrals

    CERN Document Server

    McKean, Henry P

    2005-01-01

    This little book is a brilliant introduction to an important boundary field between the theory of probability and differential equations. -E. B. Dynkin, Mathematical Reviews This well-written book has been used for many years to learn about stochastic integrals. The book starts with the presentation of Brownian motion, then deals with stochastic integrals and differentials, including the famous Itô lemma. The rest of the book is devoted to various topics of stochastic integral equations, including those on smooth manifolds. Originally published in 1969, this classic book is ideal for supplemen

  17. INTEGRATED EDUCATION

    Directory of Open Access Journals (Sweden)

    Lioara-Bianca BUBOIU

    2015-04-01

    Full Text Available Accepting and valuing people with disabilities is a key aspect of social policies promoted worldwide. The implementation of these policies aim normalize the lives of people with disabilities through full integration in the society to which they belong. Removing discrimination and social barriers equates to a maturing of the society, maturing translated by accepting diversity that surrounds us. Each person must be appreciated at its true value regardless of its condition of normality or deviation from it. Valuing individuals can be achieved only through a full acceptance in society, by assigning statuses and fulfilling social roles. School integration of children with special educational needs in mainstream education is a challenge and involves many aspects to be successful. It is the premise of social integration, the basis for future socio-professional insertion. Integrated education is the first step towards a world of equal opportunities, a world without discrimination.

  18. Integral Equations

    CERN Document Server

    Hochstadt, Harry

    2011-01-01

    This classic work is now available in an unabridged paperback edition. Hochstatdt's concise treatment of integral equations represents the best compromise between the detailed classical approach and the faster functional analytic approach, while developing the most desirable features of each. The seven chapters present an introduction to integral equations, elementary techniques, the theory of compact operators, applications to boundary value problems in more than dimension, a complete treatment of numerous transform techniques, a development of the classical Fredholm technique, and applicatio

  19. HOW INTEGRATED IS INTEGRATED LOGISTICS?

    Directory of Open Access Journals (Sweden)

    P.J. Pretorius

    2012-01-01

    Full Text Available Industry and academia still have a major problem in grasping the extent and relationships ofall functions involved in integrated logistics. This is because business logistics and logistics engineering developed separately, each with their own following, resulting in the two so-called different -disciplines ignoring each other.

    By analysing the definition of integrated logistic support, it is possible to identify the necessary conditions for an integrated logistics model. From these necessary conditions, a model of the management functions and technical activities is constructed to suggest the purpose and place of all logistics functions to work in an integrated way towards the goal of the organisation. The model suggests that logistics engineering and business logistics are both required in the organisation and that it is of vital importance that these functions are executed in unison . This model is different to previous models in that it approaches logistics from the organisations viewpoint rather than from a logistics viewpoint.

  20. IRIS (Integrity and Reliability in Integrated Circuits) Test Article Generation (ITAG)

    Science.gov (United States)

    2015-03-31

    memory controller and the system. This article was delivered as synthesizeable, human readable HDL (both Verilog and VHDL) with datasheet and test...block which is supposed to provide limited analog to digital conversion and temperature sensing. The block was implemented in VLSI for the Virtex-4...custom tools such as USC/ISI’s Torc tools, the physi- cal device can be extensively probed and intentionally set into undocumented modes to determine

  1. Integral equations

    CERN Document Server

    Tricomi, Francesco Giacomo

    1957-01-01

    This classic text on integral equations by the late Professor F. G. Tricomi, of the Mathematics Faculty of the University of Turin, Italy, presents an authoritative, well-written treatment of the subject at the graduate or advanced undergraduate level. To render the book accessible to as wide an audience as possible, the author has kept the mathematical knowledge required on the part of the reader to a minimum; a solid foundation in differential and integral calculus, together with some knowledge of the theory of functions is sufficient. The book is divided into four chapters, with two useful

  2. Lebesgue integration

    CERN Document Server

    Williamson, JH

    2014-01-01

    This concise introduction to Lebesgue integration is geared toward advanced undergraduate math majors and may be read by any student possessing some familiarity with real variable theory and elementary calculus. The self-contained treatment features exercises at the end of each chapter that range from simple to difficult. The approach begins with sets and functions and advances to Lebesgue measure, including considerations of measurable sets, sets of measure zero, and Borel sets and nonmeasurable sets. A two-part exploration of the integral covers measurable functions, convergence theorems, co

  3. The Integrated Hazard Analysis Integrator

    Science.gov (United States)

    Morris, A. Terry; Massie, Michael J.

    2009-01-01

    Hazard analysis addresses hazards that arise in the design, development, manufacturing, construction, facilities, transportation, operations and disposal activities associated with hardware, software, maintenance, operations and environments. An integrated hazard is an event or condition that is caused by or controlled by multiple systems, elements, or subsystems. Integrated hazard analysis (IHA) is especially daunting and ambitious for large, complex systems such as NASA s Constellation program which incorporates program, systems and element components that impact others (International Space Station, public, International Partners, etc.). An appropriate IHA should identify all hazards, causes, controls and verifications used to mitigate the risk of catastrophic loss of crew, vehicle and/or mission. Unfortunately, in the current age of increased technology dependence, there is the tendency to sometimes overlook the necessary and sufficient qualifications of the integrator, that is, the person/team that identifies the parts, analyzes the architectural structure, aligns the analysis with the program plan and then communicates/coordinates with large and small components, each contributing necessary hardware, software and/or information to prevent catastrophic loss. As viewed from both Challenger and Columbia accidents, lack of appropriate communication, management errors and lack of resources dedicated to safety were cited as major contributors to these fatalities. From the accident reports, it would appear that the organizational impact of managers, integrators and safety personnel contributes more significantly to mission success and mission failure than purely technological components. If this is so, then organizations who sincerely desire mission success must put as much effort in selecting managers and integrators as they do when designing the hardware, writing the software code and analyzing competitive proposals. This paper will discuss the necessary and

  4. Princeton VLSI Project: Semi-Annual Report.

    Science.gov (United States)

    1982-11-01

    version currently implemented) plus the type virtual, used to name bounding boxes and having no physical reality in the fabricated circuit. For example...type vitual . The relationship of the rectangle bounding a newly * created cell to any other rectangle of the layout can be specified in the standard

  5. VLSI Implementation of Fuzzy Logic Operator Unit

    Science.gov (United States)

    1991-06-01

    Jabatanarah Latih Department Tentera Laut Kementerian Pertahanan 50634 Kuala Lumpur, Malaysia 7. Lt Cdr Ismail bin Dewa 958, Jalan Teratai 12 Taman Marida, Senawang 70450 Seremban, Negeri Sembilan Malaysia 49

  6. Learning in Neural Networks: VLSI Implementation Strategies

    Science.gov (United States)

    Duong, Tuan Anh

    1995-01-01

    Fully-parallel hardware neural network implementations may be applied to high-speed recognition, classification, and mapping tasks in areas such as vision, or can be used as low-cost self-contained units for tasks such as error detection in mechanical systems (e.g. autos). Learning is required not only to satisfy application requirements, but also to overcome hardware-imposed limitations such as reduced dynamic range of connections.

  7. VLSI Implementation of Digital Fourier Transforms.

    Science.gov (United States)

    1982-11-01

    aItkewng 37 5Ŗ.2. M -ulie of the Real and Imagnary POt 3S 5.3. Root S Circuit 39 5.4. Barrel 39ftr 41 55. -rotator 4216 5.5.1. Theary of operatio. 42 5...s is done so that the strings - - - -. ________-----:- -.- r 7 - r -rrr ------------- -7- of operators will match the structures exactly when they...results of the CORDIC cal- culation on a fabricated chip. However, it would be possible to add a register at the output of each adder module and string

  8. DARPA/ISTO Rapid VLSI Implementation

    Science.gov (United States)

    1991-12-01

    Table B. Sun-3 and Sun-4 implementations were run to verify of the 88000 implementation of the Sieve of Eratosthenes . Identical results were produced...development ef- forts that demonstrate methodologies for improved system -erformance. These tech- no!ogy demonstrations, called Collaborative Development...to DARPA by providing an alternative source for hybrids. It is not clear that performance would be improved by assuming more packaging risk because

  9. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  10. ARPA/CSTO Rapid VLSI Implementation

    Science.gov (United States)

    1993-07-01

    T 2 T NETAU TX T~ I TY cw CNAu COLA T WELL CNG 53 ~iZ "PH ou ELL CWP iZZ 2 WHELL CMN IA2Z I I IRCTVECAR ’AS 91m T I SLECTCSG 54 - T MDT PSELECT CSP...project area, as well as on packaging methods. As can be seen from the table, the number of users is determined by the type of lithography employed...mass or volume is very dependent upon existing economic conditions as well as the type of business sought by the IC fabricator. 2.0 TECHNOLOGY ACCESS

  11. VLSI Design, Parallel Computation and Distributed Computing

    Science.gov (United States)

    1991-09-30

    I U1 TA 3 Daniel Mleitman U. :C..( -_. .. .s .. . . . . Tom Leighton David Shmoys . ........A ,~i ;.t , 77 Michael Sipser , Di.,t a-., Eva Tardos...Programming. 53. R. Boppania. MI. Sipser , --The Complexity of Finite Functions," Handbook of Theoretical Computer Science, 1990, 7.59-800. .54. T...Property with Application," IPL. Vol. 35, Sept. 1990, pp. 281- 285. 139. M. Sipser , L. Fortnow, ’Interactive Proof Systems in Log-Space," submit- ted

  12. Graphene-Si heterogeneous nanotechnology

    Science.gov (United States)

    Akinwande, Deji; Tao, Li

    2013-05-01

    It is widely envisioned that graphene, an atomic sheet of carbon that has generated very broad interest has the largest prospects for flexible smart systems and for integrated graphene-silicon (G-Si) heterogeneous very large-scale integrated (VLSI) nanoelectronics. In this work, we focus on the latter and elucidate the research progress that has been achieved for integration of graphene with Si-CMOS including: wafer-scale graphene growth by chemical vapor deposition on Cu/SiO2/Si substrates, wafer-scale graphene transfer that afforded the fabrication of over 10,000 devices, wafer-scalable mitigation strategies to restore graphene's device characteristics via fluoropolymer interaction, and demonstrations of graphene integrated with commercial Si- CMOS chips for hybrid nanoelectronics and sensors. Metrology at the wafer-scale has led to the development of custom Raman processing software (GRISP) now available on the nanohub portal. The metrology reveals that graphene grown on 4-in substrates have monolayer quality comparable to exfoliated flakes. At room temperature, the high-performance passivated graphene devices on SiO2/Si can afford average mobilities 3000cm2/V-s and gate modulation that exceeds an order of magnitude. The latest growth research has yielded graphene with high mobilities greater than 10,000cm2/V-s on oxidized silicon. Further progress requires track compatible graphene-Si integration via wafer bonding in order to translate graphene research from basic to applied research in commercial R and D laboratories to ultimately yield a viable nanotechnology.

  13. Riemann Integration

    Indian Academy of Sciences (India)

    ... of most functions are impossible to determine exactly (although they may be computed to any degree of accuracy desired by calcu- lating lower and upper sums). Nevertheless, the integral of many functions can be computed very easily. -74-----------------------------~~--------R-E-S-O-N-A-N-C-E-I-N-o-v-em--be-r--zo-o-6 ...

  14. Memory integration

    NARCIS (Netherlands)

    Sweegers, C.C.G.

    2014-01-01

    The aim of this thesis was to characterize the neural mechanisms underlying memory integration. In chapter 2, we studied the neural underpinnings of regularity extraction across hippocampus-dependent episodic memories. We found higher connectivity between the hippocampus and the mPFC for the

  15. Integral cryptanalysis

    DEFF Research Database (Denmark)

    Knudsen, Lars Ramkilde; Wagner, David

    2002-01-01

    This paper considers a cryptanalytic approach called integral cryptanalysis. It can be seen as a dual to differential cryptanalysis and applies to ciphers not vulnerable to differential attacks. The method is particularly applicable to block ciphers which use bijective components only....

  16. Integrated nanocatalysts.

    Science.gov (United States)

    Zeng, Hua Chun

    2013-02-19

    Despite significant advancements in catalysis research, the prevailing catalyst technology remains largely an art rather than a science. Rapid development in the fields of nanotechnology and materials chemistry in the past few decades, however, provides us with a new capacity to re-examine existing catalyst design and processing methods. In recent years, "nanocatalysts" has become a term often used by the materials chemistry and catalysis community. It refers to heterogeneous catalysts at nanoscale dimensions. Similar to homogeneous catalysts, freestanding (unsupported) nanocatalysts are difficult to separate after use. Because of their small sizes, they are also likely to be cytotoxic and pose a threat to the environment and therefore may not be practical for industrial use. On the other hand, if they are supported on ordinary catalyst carriers, the nanocatalysts would then revert to act as conventional heterogeneous catalysts, since chemists have known active metal clusters or oxide particles in the nanoscale regime long before the nanotechnology era. To resolve this problem, we need new research directions and synthetic strategies. Important advancements in catalysis research now allow chemists to prepare catalytic materials with greater precision. By controlling particle composition, structure, shape, and dimension, researchers can move into the next phase of catalyst development if they can bridge these old and new technologies. In this regard, one way seems to be to integrate active nanostructured catalysts with boundary-defined catalyst supports that are "not-so-nano" in dimension. However, these supports still have available hierarchical pores and cavity spaces. In principle, these devices keep the essence of traditional "catalyst-plus-support" type systems. They also have the advantages of nanoscale engineering, which involves both high level design and integration processes in their fabrication. Besides this, the active components in these devices are

  17. Integrated Design

    DEFF Research Database (Denmark)

    Jørgensen, Michael; Nielsen, M. W.; Strømann-Andersen, Jakob Bjørn

    2011-01-01

    This paper presents a case study of the implementation of integrated design in an actual architectural competition. The design process was carried out at a highly esteemed architectural office and attended by both engineers and architects working towards mutual goals of architectural excellence......, low-energy consumption, and high-quality indoor environment. We use this case study to investigate how technical knowledge about building performance can be integrated into the conceptual design stage. We have selected certain points during the design process that represented design challenges...... and describe the decision process. Specific attention is given to how the engineering input was presented and how it was able to facilitate the design development. Site and context, building shape, organization of functions and HVAC-systems were all included to obtain a complete picture of the building...

  18. Scientific integrity

    DEFF Research Database (Denmark)

    Merlo, Domenico Franco; Vahakangas, Kirsi; Knudsen, Lisbeth E.

    2008-01-01

    consent was obtained.Integrity is central to environmental health research searching for causal relations. It requires open communication and trust and any violation (i.e., research misconduct, including fabrication or falsification of data, plagiarism, conflicting interests, etc.) may endanger......Environmental health research is a relatively new scientific area with much interdisciplinary collaboration. Regardless of which human population is included in field studies (e.g., general population, working population, children, elderly, vulnerable sub-groups, etc.) their conduct must guarantee...... well acknowledged ethical principles. These principles, along with codes of conduct, are aimed at protecting study participants from research-related undesired effects and guarantee research integrity. A central role is attributed to the need for informing potential participants (i.e., recruited...

  19. Integrated Photopolarimeters

    Science.gov (United States)

    Azzam, R. M.

    1988-06-01

    Measurement of the state of polarization of light, emitted from different sources or scattered by various objects, is significant to astronomers, atmospheric scientists, biologists, chemists, physicists, and engineers, and has a wide range of important applications. Conventional optical polarimetry is based on discrete polarizing optical elements (POE), such as crystal polarizers and wave retarders. Integrated polarimeters (IPs) depart from this established practice in that they rely on photodectors only, and require no POE. An IP integrates the polarization analysis and photodetection functions in the detectors. Three IPs are discussed: (1) the rotating-detector ellipsometer (RODE), (2) the two-detector ellipsometer (TDE), and (3) the four-detector photopolarimeter (FDP), in ascending order of apparent complexity. RODE can measure the state of polarization of totally polarized light, except for handedness; TDE provides a fast measurement of the degree of linear polarization of light and can also be operated as a handedness-blind ellipsometer; and FDP measures all the four Stokes parameters of light which is generally partially elliptically polarized. The FDP has several important advantages: (1) It has no moving parts or modulators; (2) it has a rugged design of four solid-state detectors; (3) it uses efficiently all of the input light flux for polarization determination; and (4) it is readily interfaceable with an on-line microcomputer. Further extension of these concepts include the in-line light-saving IP, and IPs that use anisotropic photodetectors.

  20. Surface morphology and the phase formation at Cr/Si system

    Energy Technology Data Exchange (ETDEWEB)

    Agarwal, Shivani [Centre for Non-Conventional Energy Resources, University of Rajasthan, Jaipur 302004 (India)]. E-mail: shivani95@sify.com; Jain, Ankur [Centre for Non-Conventional Energy Resources, University of Rajasthan, Jaipur 302004 (India); Lal, Chhagan [Centre for Non-Conventional Energy Resources, University of Rajasthan, Jaipur 302004 (India); Ganesan, V. [UGC-DAE Consortium for Scientific Research, Khandwa Road, Indore (India); Jain, I.P. [Centre for Non-Conventional Energy Resources, University of Rajasthan, Jaipur 302004 (India)]. E-mail: ipjain46@sify.com

    2007-03-15

    Metal silicide technology has been attracting attention worldwide and it constitutes an active, frontier area of research. Research in this area has not only stimulated the exploration of new phenomena, but is also leading to a technological revolution. Electron beam evaporation in ultra high vacuum (UHV) environment is one of the best techniques to grow thin metal film on Si substrate. Metal silicide contact is an interesting and important part of integrated circuit. Due to selective growth and high thermal stability metal silicides are used in very large scale integrated (VLSI) and ultra large scale integrated (ULSI) applications. In this paper our interest is to show GIXRD, XRR and SPM measurement on C (2 nm)/Cr (25 nm)/Si (1 0 0) system in which thin films were deposited using electron beam evaporation technique at 2 x 10{sup -8} Torr vacuum. The capping layer of 2 nm carbon is deposited to stop contamination. The C (2 nm)/Cr (25 nm)/Si (1 0 0) system were annealed in 10{sup -5} Torr vacuum at temperatures 300-600 deg. C to study the formation of chromium silicide. Structural properties at the interface has been studied by grazing incidence X-ray diffraction (GIXRD), which shows formation of Cr{sub 3}Si and CrSi{sub 2} as a result of interface mixing due to annealing. The morphology of the system was investigated by AFM in tapping mode. It was found that nano-rod type structures were formed with annealing at 600 deg. C temperature.

  1. Multidimensional singular integrals and integral equations

    CERN Document Server

    Mikhlin, Solomon Grigorievich; Stark, M; Ulam, S

    1965-01-01

    Multidimensional Singular Integrals and Integral Equations presents the results of the theory of multidimensional singular integrals and of equations containing such integrals. Emphasis is on singular integrals taken over Euclidean space or in the closed manifold of Liapounov and equations containing such integrals. This volume is comprised of eight chapters and begins with an overview of some theorems on linear equations in Banach spaces, followed by a discussion on the simplest properties of multidimensional singular integrals. Subsequent chapters deal with compounding of singular integrals

  2. Homeland Integration

    Directory of Open Access Journals (Sweden)

    Bin Ai

    2017-03-01

    Full Text Available In this study, the first author narrates his experiences of the challenges of integration into several Chinese universities as a PhD graduate after returning from Australia. His patterns of communication and psychological changes are examined in terms of identity construction and transformation. His insider position as a Chinese native and academic returnee enables him to see the realities of practice in average Chinese universities at close range, yet with the altered vision gained from his overseas experience. This study highlights the challenges for academic returnees in Chinese higher education institutions and may also have resonances for academic returnees in other countries. Wider questions about the assessment of English research writing and the attitudes to academic returnees in Chinese universities are raised, contributing to debate over the future development of Chinese higher education institutions in a globalizing world.

  3. Integrated Toys

    DEFF Research Database (Denmark)

    Petersson, Eva

    2005-01-01

    Toys play a crucial role in supporting children’s learning and creation of meaning in their everyday life. Children also play with toys out of an interest to interact with others e.g. peers and adults. Tendencies of digital technology in toys have led to greater opportunities for manipulation......). This paper suggests that a toy system integrating physical and virtual dimensions will extend the respective design specifics and will support an expansion of children’s learning opportunities. Furthermore, we suggest that such toy system should be tangible, responsive, and portable. The required technology...... changed our everyday lives. However, its contribution in development of new suitable material for play and learning has not been appropriate. We argue that play is a fruitful base for learning and training and that the design of physical and virtual artifacts advantageously should rest upon...

  4. Computing Systems Configuration for Highly Integrated Guidance and Control Systems

    Science.gov (United States)

    1988-06-01

    use of fusion splices (fusion by electric arc ) may be limited to harness fabrication in the wire shop or on the assembly line due to safety...description et caracteristiques electriques du BUS 65112 suprahybride, unite pour terminal a distance, conforme a la norme MIL-STO-1553B. Circuit VLSI...articles relatifa d’une part aux Iibertes et aux contraintes des commandes de vol electriques et d’autre part au calculateur aeroporte de l’avenir qui

  5. Introduction to gauge integrals

    CERN Document Server

    Swartz, Charles

    2001-01-01

    This book presents the Henstock/Kurzweil integral and the McShane integral. These two integrals are obtained by changing slightly the definition of the Riemann integral. These variations lead to integrals which are much more powerful than the Riemann integral. The Henstock/Kurzweil integral is an unconditional integral for which the fundamental theorem of calculus holds in full generality, while the McShane integral is equivalent to the Lebesgue integral in Euclidean spaces. A basic knowledge of introductory real analysis is required of the reader, who should be familiar with the fundamental p

  6. Elliptic integrals: Symmetry and symbolic integration

    Energy Technology Data Exchange (ETDEWEB)

    Carlson, B.C. [Ames Lab., IA (United States)]|[Iowa State Univ., Ames, IA (United States). Dept. of Mathematics

    1997-12-31

    Computation of elliptic integrals, whether numerical or symbolic, has been aided by the contributions of Italian mathematicians. Tricomi had a strong interest in iterative algorithms for computing elliptic integrals and other special functions, and his writings on elliptic functions and elliptic integrals have taught these subjects to many modern readers (including the author). The theory of elliptic integrals began with Fagnano`s duplication theorem, a generalization of which is now used iteratively for numerical computation in major software libraries. One of Lauricella`s multivariate hypergeometric functions has been found to contain all elliptic integrals as special cases and has led to the introduction of symmetric canonical forms. These forms provide major economies in new integral tables and offer a significant advantage also for symbolic integration of elliptic integrals. Although partly expository the present paper includes some new proofs and proposes a new procedure for symbolic integration.

  7. Simplification of integrity constraints for data integration

    DEFF Research Database (Denmark)

    Christiansen, Henning; Martinenghi, Davide

    2004-01-01

    When two or more databases are combined into a global one, integrity may be violated even when each database is consistent with its own local integrity constraints. Efficient methods for checking global integrity in data integration systems are called for: answers to queries can then be trusted...... together with given a priori constraints on the combination, so that only a minimal number of tuples needs to be considered. Combination from scratch, integration of a new source, and absorption of local updates are dealt with for both the local-as-view and global-as-view approaches to data integration....

  8. Backward integration, forward integration, and vertical foreclosure

    OpenAIRE

    Spiegel, Yossi

    2013-01-01

    I show that partial vertical integration may either alleviates or exacerbate the concern for vertical foreclosure relative to full vertical integration and I examine its implications for consumer welfare.

  9. Integrated project delivery : The designer as integrator

    NARCIS (Netherlands)

    Wamelink, J.W.F.; Koolwijk, J.S.J.; van Doorn, A.J.

    2012-01-01

    Process innovation related to integrated project delivery is an important topic in the building industry. Studies on process innovation through the use of integrated contracts usually focus on contractors, and particularly on the possibility of forward integration into the building process. Three

  10. Data integration technologies to support integrated modelling

    NARCIS (Netherlands)

    Knapen, M.J.R.; Roosenschoon, O.R.; Lokers, R.M.; Janssen, S.J.C.; Randen, van Y.; Verweij, P.J.F.M.

    2013-01-01

    Over the recent years the scientific activities of our organisation in large research projects show a shifting priority from model integration to the integration of data itself. Our work in several large projects on integrated modelling for impact assessment studies has clearly shown the importance

  11. Wealth Through Integration: Regional Integration and Poverty ...

    International Development Research Centre (IDRC) Digital Library (Canada)

    Wealth Through Integration: Regional Integration and Poverty-Reduction Strategies in West Africa. Book cover Wealth Through Integration. Directeur(s) : Elias T. Ayuk and Samuel T. Kaboré. Maison(s) d'édition : Springer, IDRC. 27 février 2013. ISBN : 9781461444145. 297 pages. e-ISBN : 9781552505441. Téléchargez le ...

  12. Optical and XPS studies of BCN thin films by co-sputtering of B{sub 4}C and BN targets

    Energy Technology Data Exchange (ETDEWEB)

    Prakash, Adithya, E-mail: adithya@knights.ucf.edu; Sundaram, Kalpathy B.

    2017-02-28

    Highlights: • Wide range of optical band gaps (Eg) are achieved for dual target sputtered BCN films in the range of 1.9 eV−3.7 eV. • Optical band gap (Eg) studies are performed as a function of target powers, gas ratios and deposition temperatures. • Eg is found to increase with N{sub 2}/Ar flow ratios and deposition temperatures. • XPS studies are conducted to ascertain the chemical and bonding characteristics. • XPS showed higher h-BN and B{sub 4}C property at higher N{sub 2}/Ar gas ratios for films deposited at 20 W and 40 W B{sub 4}C power respectively. - Abstract: Boron carbon nitride (BCN) thin films are investigated for their optical properties. BCN, is the unanimous choice for inter-dielectric layer (IDL) in very large scale integration (VLSI) because of its low-k dielectric constant. Optical properties can be tailored as a function of elemental composition, which makes BCN a prospective material in UV-filters and mirrors. Films are deposited by reactive co-sputtering of boroncarbide (B{sub 4}C) and boronnitride (BN) with varying N{sub 2}/Ar gas flow ratio by DC and RF sputtering respectively. XPS studies are performed to deduce the bonding and chemical properties of the BCN thinfilms. Optical band gap (Eg) studies are performed as a result of varying target powers, gas ratios and deposition temperatures. Eg is found to increase with N{sub 2}/Ar flow ratios and deposition temperatures. BCN deposited at 20 W DC exhibited higher band gap range and the highest achieved is 3.7 eV at N{sub 2}/Ar = 0.75. Lowest value achieved is 1.9 eV at N{sub 2}/Ar = 0.25 for as-deposited films.

  13. Neuromorphic meets neuromechanics, part I: the methodology and implementation

    Science.gov (United States)

    Niu, Chuanxin M.; Jalaleddini, Kian; Sohn, Won Joon; Rocamora, John; Sanger, Terence D.; Valero-Cuevas, Francisco J.

    2017-04-01

    Objective: One goal of neuromorphic engineering is to create ‘realistic’ robotic systems that interact with the physical world by adopting neuromechanical principles from biology. Critical to this is the methodology to implement the spinal circuitry responsible for the behavior of afferented muscles. At its core, muscle afferentation is the closed-loop behavior arising from the interactions among populations of muscle spindle afferents, alpha and gamma motoneurons, and muscle fibers to enable useful behaviors. Approach. We used programmable very- large-scale-circuit (VLSI) hardware to implement simple models of spiking neurons, skeletal muscles, muscle spindle proprioceptors, alpha-motoneuron recruitment, gamma motoneuron control of spindle sensitivity, and the monosynaptic circuitry connecting them. This multi-scale system of populations of spiking neurons emulated the physiological properties of a pair of antagonistic afferented mammalian muscles (each simulated by 1024 alpha- and gamma-motoneurones) acting on a joint via long tendons. Main results. This integrated system was able to maintain a joint angle, and reproduced stretch reflex responses even when driving the nonlinear biomechanics of an actual cadaveric finger. Moreover, this system allowed us to explore numerous values and combinations of gamma-static and gamma-dynamic gains when driving a robotic finger, some of which replicated some human pathological conditions. Lastly, we explored the behavioral consequences of adopting three alternative models of isometric muscle force production. We found that the dynamic responses to rate-coded spike trains produce force ramps that can be very sensitive to tendon elasticity, especially at high force output. Significance. Our methodology produced, to our knowledge, the first example of an autonomous, multi-scale, neuromorphic, neuromechanical system capable of creating realistic reflex behavior in cadaveric fingers. This research platform allows us to explore

  14. Design and implementation of efficient low complexity biomedical artifact canceller for nano devices

    Directory of Open Access Journals (Sweden)

    Md Zia Ur RAHMAN

    2016-07-01

    Full Text Available In the current day scenario, with the rapid development of communication technology remote health care monitoring becomes as an intense research area. In remote health care monitoring, the primary aim is to facilitate the doctor with high resolution biomedical data. In order to cancel various artifacts in clinical environment in this paper we propose some efficient adaptive noise cancellation techniques. To obtain low computational complexity we combine clipping the data or error with Least Mean Square (LMS algorithm. This results sign regressor LMS (SRLMS, sign LMS (SLMS and sign LMS (SSLMS algorithms. Using these algorithms, we design Very-large-scale integration (VLSI architectures of various Biomedical Noise Cancellers (BNCs. In addition, the filtering capabilities of the proposed implementations are measured using real biomedical signals. Among the various BNCs tested, SRLMS based BNC is found to be better with reference to convergence speed, filtering capability and computational complexity. The main advantage of this technique is it needs only one multiplication to compute next weight. In this manner SRLMS based BNC is independent of filter length with reference to its computations. Whereas, the average signal to noise ratio achieved in the noise cancellation experiments are recorded as 7.1059dBs, 7.1776dBs, 6.2795dBs and 5.8847dBs for various BNCs based on LMS, SRLMS, SLMS and SSSLMS algorithms respectively. Based on the filtering characteristics, convergence and computational complexity, the proposed SRLMS based BNC architecture is well suited for nanotechnology applications.

  15. Silicon Brains

    Science.gov (United States)

    Hoefflinger, Bernd

    Beyond the digital neural networks of Chap. 16, the more radical mapping of brain-like structures and processes into VLSI substrates has been pioneered by Carver Mead more than 30 years ago [1]. The basic idea was to exploit the massive parallelism of such circuits and to create low-power and fault-tolerant information-processing systems. Neuromorphic engineering has recently seen a revival with the availability of deep-submicron CMOS technology, which allows for the construction of very-large-scale mixed-signal systems combining local analog processing in neuronal cells with binary signalling via action potentials. Modern implementations are able to reach the complexity-scale of large functional units of the human brain, and they feature the ability to learn by plasticity mechanisms found in neuroscience. Combined with high-performance programmable logic and elaborate software tools, such systems are currently evolving into user-configurable non-von-Neumann computing systems, which can be used to implement and test novel computational paradigms. The chapter introduces basic properties of biological brains with up to 200 Billion neurons and their 1014 synapses, where action on a synapse takes ˜10 ms and involves an energy of ˜10 fJ. We outline 10x programs on neuromorphic electronic systems in Europe and the USA, which are intended to integrate 108 neurons and 1012 synapses, the level of a cat's brain, in a volume of 1 L and with a power dissipation intelligence, we references Hawkins' view to first perceive the task and then design an intelligent technical response.

  16. Pro Spring Integration

    CERN Document Server

    Lui, M; Chan, Andy; Long, Josh

    2011-01-01

    Pro Spring Integration is an authoritative book from the experts that guides you through the vast world of enterprise application integration (EAI) and application of the Spring Integration framework towards solving integration problems. The book is:. * An introduction to the concepts of enterprise application integration * A reference on building event-driven applications using Spring Integration * A guide to solving common integration problems using Spring Integration What makes this book unique is its coverage of contemporary technologies and real-world information, with a focus on common p

  17. Tactical Systems Integration Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Tactical Systems Integration Laboratory is used to design and integrate computer hardware and software and related electronic subsystems for tactical vehicles....

  18. Some unit square integrals

    OpenAIRE

    Sampedro, Juan Carlos

    2017-01-01

    In this article we prove some identities which allow us to evaluate some multiple unit square integrals. In our examples we will give the value of some double and triple integrals. Then, we prove several classical integral formulas with the help of these identities and we present others that seems to be new. Finally we get double integrals for classical constants and different expression for two Ramanujan's integral formulas.

  19. Cavalieri Integration - CSIR Technical report

    CSIR Research Space (South Africa)

    Grobler, TL

    2011-10-01

    Full Text Available The authors use Cavalieri's principle to develop a novel integration technique which they call Cavalieri integration. Cavalieri integrals differ from Riemann integrals in that non-rectangular integration strips are used. In this way they can use...

  20. Laplace Transforms without Integration

    Science.gov (United States)

    Robertson, Robert L.

    2017-01-01

    Calculating Laplace transforms from the definition often requires tedious integrations. This paper provides an integration-free technique for calculating Laplace transforms of many familiar functions. It also shows how the technique can be applied to probability theory.

  1. Integrated resource planning

    DEFF Research Database (Denmark)

    Østergaard, Poul Alberg

    2004-01-01

    The chapter describes two cases where the principles of Integrated Resouce Plannning (IRP) has been applied to simplified systems.......The chapter describes two cases where the principles of Integrated Resouce Plannning (IRP) has been applied to simplified systems....

  2. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  3. Integrated vs. Federated Search

    DEFF Research Database (Denmark)

    Løvschall, Kasper

    2009-01-01

    Oplæg om forskelle og ligheder mellem integrated og federated search i bibliotekskontekst. Holdt ved temadag om "Integrated Search - samsøgning i alle kilder" på Danmarks Biblioteksskole den 22. januar 2009.......Oplæg om forskelle og ligheder mellem integrated og federated search i bibliotekskontekst. Holdt ved temadag om "Integrated Search - samsøgning i alle kilder" på Danmarks Biblioteksskole den 22. januar 2009....

  4. Integrations on rings

    Directory of Open Access Journals (Sweden)

    Banič Iztok

    2017-04-01

    Full Text Available In calculus, an indefinite integral of a function f is a differentiable function F whose derivative is equal to f. The main goal of the paper is to generalize this notion of the indefinite integral from the ring of real functions to any ring. We also investigate basic properties of such generalized integrals and compare them to the well-known properties of indefinite integrals of real functions.

  5. Boolean integral calculus

    Science.gov (United States)

    Tucker, Jerry H.; Tapia, Moiez A.; Bennett, A. Wayne

    1988-01-01

    The concept of Boolean integration is developed, and different Boolean integral operators are introduced. Given the changes in a desired function in terms of the changes in its arguments, the ways of 'integrating' (i.e. realizing) such a function, if it exists, are presented. The necessary and sufficient conditions for integrating, in different senses, the expression specifying the changes are obtained. Boolean calculus has applications in the design of logic circuits and in fault analysis.

  6. Spring integration essentials

    CERN Document Server

    Pandey, Chandan

    2015-01-01

    This book is intended for developers who are either already involved with enterprise integration or planning to venture into the domain. Basic knowledge of Java and Spring is expected. For newer users, this book can be used to understand an integration scenario, what the challenges are, and how Spring Integration can be used to solve it. Prior experience of Spring Integration is not expected as this book will walk you through all the code examples.

  7. Morocco Integration Strategy Improvement

    Directory of Open Access Journals (Sweden)

    Samir Smuni

    2013-01-01

    Full Text Available The article justifies the necessity of Morocco integration strategy improvement with regard to the «Arab Spring» consequences and the global financial crisis, gives general recommendations for the development of the integration strategy in order to improve the efficiency of participation in the processes of international integration, detects cooperation lines with the European Union and the Arab Maghreb Union in coordination of these integration strategy directions

  8. Curriculum Integration: An Overview

    Science.gov (United States)

    Wall, Amanda; Leckie, Alisa

    2017-01-01

    Curriculum integration is a tenet of middle level education. "This We Believe," the position paper of the Association for Middle Level Education, advocates for curriculum that is exploratory, relevant, integrative, and meaningful for young adolescents. Teachers can integrate curriculum across content areas by anchoring units of study in…

  9. Integrating Writing and Mathematics

    Science.gov (United States)

    Wilcox, Brad; Monroe, Eula Ewing

    2011-01-01

    Teachers often find it difficult to integrate writing and mathematics while honoring the integrity of both disciplines. In this article, the authors present two levels of integration that teachers may use as a starting point. The first level, writing without revision, can be worked into mathematics instruction quickly and readily. The second…

  10. Optimizing Computer Technology Integration

    Science.gov (United States)

    Dillon-Marable, Elizabeth; Valentine, Thomas

    2006-01-01

    The purpose of this study was to better understand what optimal computer technology integration looks like in adult basic skills education (ABSE). One question guided the research: How is computer technology integration best conceptualized and measured? The study used the Delphi method to map the construct of computer technology integration and…

  11. Ramjets: Airframe integration

    NARCIS (Netherlands)

    Moerel, J.L.; Halswijk, W.

    2010-01-01

    These notes deal with the integration of a (sc)ramjet engine in either an axisymmetric or a waverider type of cruise missile configuration. The integration aspects relate to the integration of the external and internal flow paths in geometrical configurations that are being considered worldwide.

  12. Foundations for Psychotherapy Integration

    Directory of Open Access Journals (Sweden)

    António Branco Vasco

    2014-10-01

    Full Text Available The movement for integration in psychotheray is clearly one of the main trends that can be observed in the field. The author stresses three main reasons for this state of affairs and as a way of justifying the importance of integration: historical and psychosocial, empirical and philosophical. A specific way of thinking in integrative terms is also outlined - "paradigmatic complementarity."

  13. Clarifying local integration

    Directory of Open Access Journals (Sweden)

    Sarah Meyer

    2006-08-01

    Full Text Available Ana Low’s article in FMR 251 highlights the need to reexamineand re-invigorate debate on local integration as adurable solution for refugees. However, the Self-RelianceStrategy (SRS in Uganda which she describes does notprovide an adequate model of local integration as adurable solution – in fact, local integration is not its aim.

  14. Between integration and freedom

    DEFF Research Database (Denmark)

    Jørgensen, Simon Laumann

    2017-01-01

    to be insufficient considering widespread concerns with respecting parental freedom, this article discusses the more value-integrative approach found in the political philosophical work of Hegel. According to this approach, our value-commitments to both social integration and individual freedom can be integrated...

  15. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  16. Nature-based integration

    DEFF Research Database (Denmark)

    Pitkänen, Kati; Oratuomi, Joose; Hellgren, Daniela

    based integration by case study descriptions from Denmark, Sweden Norway and Finland. Across Nordic countries several practical projects and initiatives have been launched to promote the benefits of nature in integration and there is also growing academic interest in the topic. Nordic countries have......Increased attention to, and careful planning of the integration of migrants into Nordic societies is ever more important. Nature based integration is a new solution to respond to this need. This report presents the results of a Nordic survey and workshop and illustrates current practices of nature...... the potential of becoming real forerunners in nature based integration even at the global scale....

  17. Immigrant Integration: Acculturation and Social Integration

    Directory of Open Access Journals (Sweden)

    Astrid HAMBERGER

    2009-11-01

    Full Text Available This article tackles the concept of “immigrant integration” as it is analyzed by different authors in the international migration field. In this article, I will use the terms “refugee” and “immigrant” as equivalent to each other due to the interchangeable character of these concepts throughout the integration literature. First, the article brings into discussion the definitional and conceptual battle around the concept of immigrant “integration”, and second, it will describe and analyze cultural and social integration with their presupposing processes.

  18. Integrated management systems

    CERN Document Server

    Bugdol, Marek

    2015-01-01

    Examining the challenges of integrated management, this book explores the importance and potential benefits of using an integrated approach as a cross-functional concept of management. It covers not only standardized management systems (e.g. International Organization for Standardization), but also models of self-assessment, as well as different types of integration. Furthermore, it demonstrates how processes and systems can be integrated, and how management efficiency can be increased. The major part of this book focuses on management concepts which use integration as a key tool of management processes (e.g. the systematic approach, supply chain management, virtual and network organizations, processes management and total quality management). Case studies, illustrations, and tables are also provided to exemplify and illuminate the content, as well as examples of successful and failed integrations. Providing a particularly useful resource to managers and specialists involved in the improvement of organization...

  19. Integration of reusable systems

    CERN Document Server

    Rubin, Stuart

    2014-01-01

    Software reuse and integration has been described as the process of creating software systems from existing software rather than building software systems from scratch. Whereas reuse solely deals with the artifacts creation, integration focuses on how reusable artifacts interact with the already existing parts of the specified transformation. Currently, most reuse research focuses on creating and integrating adaptable components at development or at compile time. However, with the emergence of ubiquitous computing, reuse technologies that can support adaptation and reconfiguration of architectures and components at runtime are in demand. This edited book includes 15 high quality research papers written by experts in information reuse and integration to cover the most recent advances in the field. These papers are extended versions of the best papers which were presented at IEEE International Conference on Information Reuse and Integration and IEEE International Workshop on Formal Methods Integration, which wa...

  20. What constitutes information integrity?

    Directory of Open Access Journals (Sweden)

    S. Flowerday

    2007-12-01

    Full Text Available This research focused on what constitutes information integrity as this is a problem facing companies today. Moreover, information integrity is a pillar of information security and is required in order to have a sound security management programme. However, it is acknowledged that 100% information integrity is not currently achievable due to various limitations and therefore the auditing concept of reasonable assurance is adopted. This is in line with the concept that 100% information security is not achievable and the notion that adequate security is the goal, using appropriate countermeasures. The main contribution of this article is to illustrate the importance of and provide a macro view of what constitutes information integrity. The findings are in harmony with Samuel Johnson's words (1751: 'Integrity without knowledge is weak and useless, and knowledge without integrity is dangerous and dreadful.'

  1. What constitutes information integrity?

    Directory of Open Access Journals (Sweden)

    S. Flowerday

    2008-01-01

    Full Text Available This research focused on what constitutes information integrity as this is a problem facing companies today. Moreover, information integrity is a pillar of information security and is required in order to have a sound security management programme. However, it is acknowledged that 100% information integrity is not currently achievable due to various limitations and therefore the auditing concept of reasonable assurance is adopted. This is in line with the concept that 100% information security is not achievable and the notion that adequate security is the goal, using appropriate countermeasures. The main contribution of this article is to illustrate the importance of and provide a macro view of what constitutes information integrity. The findings are in harmony with Samuel Johnson's words (1751: 'Integrity without knowledge is weak and useless, and knowledge without integrity is dangerous and dreadful.'

  2. Classical Mechanics and Symplectic Integration

    DEFF Research Database (Denmark)

    Nordkvist, Nikolaj; Hjorth, Poul G.

    2005-01-01

    Content: Classical mechanics: Calculus of variations, Lagrange’s equations, Symmetries and Noether’s theorem, Hamilton’s equations, cannonical transformations, integrable systems, pertubation theory. Symplectic integration: Numerical integrators, symplectic integrators, main theorem on symplectic...

  3. Integration i Danmark

    OpenAIRE

    Mikkelsen, Caroline; Olsen, Kristine Falk; Weng, Millie Cammilla; Andersen, Stine Bjørnstrup

    2012-01-01

    We found interest in this project, when we through the media discovered that there is a lot of prejudicesregardingimmigrants in Denmark. We saw a problem in these prejudices and wanted to get an insight in howthese prejudicesaffect the integration in Denmark, which led us to following question of reach: What are the problems about the Danish integration in relation to stigma and what part do the conquests play in the debate, regarding assimilation or integration in the Danish society. Our ...

  4. Personal Integrity and Leadership

    OpenAIRE

    Gea, Antonius

    2016-01-01

    Generally, integrity is associated with leadership, especially in the organization or company. Integrity in leadership becomes a growing concern in business and organizations. The aim of this study was to find out the connection that could be shaped between personal integrity and the skill of leadership especially in the performance of work. This study used a library research, a literature study that done by using the available resources and relevant literature, related to the topic being dis...

  5. FRACTIONAL INTEGRATION TOOLBOX.

    Science.gov (United States)

    Marinov, Toma M; Ramirez, Nelson; Santamaria, Fidel

    2013-09-01

    The problems formulated in the fractional calculus framework often require numerical fractional integration/differentiation of large data sets. Several existing fractional control toolboxes are capable of performing fractional calculus operations, however, none of them can efficiently perform numerical integration on multiple large data sequences. We developed a Fractional Integration Toolbox (FIT), which efficiently performs fractional numerical integration/differentiation of the Riemann-Liouville type on large data sequences. The toolbox allows parallelization and is designed to be deployed on both CPU and GPU platforms.

  6. Wealth Through Integration: Regional Integration and Poverty ...

    International Development Research Centre (IDRC) Digital Library (Canada)

    2013-02-27

    Feb 27, 2013 ... This book explores the issues linked to regional integration in West Africa and presents empirical data about the experiences of the West African Economic and Monetary Union (WAEMU) countries in converging their economies. It also examines how these efforts influence poverty reduction in the economic ...

  7. Building integrated photovoltaic; Photovaltaique integre aux batiments

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2004-01-01

    Durable, modular and flexible in use, as demonstrated by the different case studies in this publication, photovoltaic can replace diverse building elements, from glass facades to weather proof roofs. This leaflet towards architects describes aesthetic, technical, economic and environmental interest of building integrated photovoltaic. (author)

  8. Musik, Sprog og Integration

    DEFF Research Database (Denmark)

    Holst, Finn

    2010-01-01

    Evaluering af projektet Musik, Sprog og Integration, Søndermarkskolen, Horsens. Andenårsevaluering af et treårigt projekt.......Evaluering af projektet Musik, Sprog og Integration, Søndermarkskolen, Horsens. Andenårsevaluering af et treårigt projekt....

  9. Integration Report 2007

    NARCIS (Netherlands)

    Jaco Dagevos; Mérove Gijsberts

    2007-01-01

    Original title: Jaarrapport integratie 2007. The Annual Report on Integration 2007 describes the integration of non-Western ethnic minorities in the Netherlands using a wide range of indicators. It focuses among other things on the situation of ethnic minority pupils in education, the

  10. Integrative STEM Education Defined

    OpenAIRE

    Sanders, Mark E.

    2013-01-01

    "In operationally defining integrative STEM education, we hope to avoid the gross confusion/ambiguity associated with STEM education. Those who wish to use integrative STEM education to describe instruction must be certain that instruction is grounded in the context of technological/engineering design activity.

  11. Hermeneutics of Integrative Knowledge.

    Science.gov (United States)

    Shin, Un-chol

    This paper examines and compares the formation processes and structures of three types of integrative knowledge that in general represent natural sciences, social sciences, and humanities. These three types can be observed, respectively, in the philosophies of Michael Polanyi, Jurgen Habermas, and Paul Ricoeur. These types of integrative knowledge…

  12. Religion and cultural integration

    DEFF Research Database (Denmark)

    Borup, Jørn; Ahlin, Lars

    2011-01-01

    The relations and possible causality between religion, ethnicity, and cultural integration is discussed using empirical data from survey on a group people with Vietnamese origin in Denmark......The relations and possible causality between religion, ethnicity, and cultural integration is discussed using empirical data from survey on a group people with Vietnamese origin in Denmark...

  13. On an integral transform

    Directory of Open Access Journals (Sweden)

    D. Naylor

    1986-01-01

    Full Text Available This paper establishes properties of a convolution type integral transform whose kernel is a Macdonald type Bessel function of zero order. An inversion formula is developed and the transform is applied to obtain the solution of some related integral equations.

  14. Designing for STEM Integration

    Science.gov (United States)

    Berland, Leema K.

    2013-01-01

    We are increasingly seeing an emphasis on STEM integration in high school classrooms such that students will learn and apply relevant math and science content while simultaneously developing engineering habits of mind. However, research in both science education and engineering education suggests that this goal of truly integrating STEM is rife…

  15. Integrated Marketing Communications

    Science.gov (United States)

    Black, Jim

    2004-01-01

    Integration has become a cliche in enrollment management and student services circles. The term is used to describe everything from integrated marketing to seamless services. Often, it defines organizational structures, processes, student information systems, and even communities. In Robert Sevier's article in this issue of "College and…

  16. Factorization of Behavioral Integrity

    DEFF Research Database (Denmark)

    Li, Ximeng; Nielson, Flemming; Nielson, Hanne Riis

    2015-01-01

    We develop a bisimulation-based nonintereference property that describes the allowed dependencies between communication behaviors of different integrity levels. The property is able to capture all possible combinations of integrity levels for the “presence” and “content” of actual communications...

  17. An Integrated Teaching Module.

    Science.gov (United States)

    Samuel, Marie R.; Seiferth, Berniece B.

    This integrated teaching module provides elementary and junior high school teachers with a "hands-on" approach to studying the Anasazi Indian. Emphasis is on creative exploration that focuses on integrating art, music, poetry, writing, geography, dance, history, anthropology, sociology, and archaeology. Replicas of artifacts,…

  18. Integral transformational coaching

    NARCIS (Netherlands)

    Keizer, W.A.J.; Nandram, S.S.

    2009-01-01

    In Chap. 12, Keizer and Nandram present the concept of Integral Transformational Coaching based on the concept of Flow and its effects on work performance. Integral Transformational Coaching is a method that prevents and cures unhealthy stress and burnout. They draw on some tried and tested

  19. Integrity in Transactional Leadership

    Science.gov (United States)

    Miller, Thomas

    2011-01-01

    This chapter begins with a discussion of the impact of limited resources on the integrity of transactions between students and student affairs administrators. A framework and guiding principles for maintaining integrity are offered, and then some general principles for transactions with students are presented. Next, the chapter involves integrity…

  20. ATLSS Integrated Building System

    OpenAIRE

    ECT Team, Purdue

    2007-01-01

    The AIBS (ATLSS Integrated Building Systems) program was developed to coordinate ongoing research projects in automated construction and connection systems. The objective of this technology is to design, fabricate, erect, and evaluate cost-effective building systems with a focus on providing a computer integrated approach to these activities.

  1. Integral Politics as Process

    Directory of Open Access Journals (Sweden)

    Tom Atlee

    2010-03-01

    Full Text Available Using the definition proposed here, integral politics can be a process of integrating diverse perspectives into wholesome guidance for a community or society. Characteristics that follow from this definition have ramifications for understanding what such political processes involve. Politics becomes integral as it transcends partisan battle and nurtures generative conversation toward the common good. Problems, conflicts and crises become opportunities for new (or renewed social coherence. Conversational methodologies abound that can help citizen awareness temporarily expand during policy-making, thus helping raise society’s manifested developmental stage. Convening archetypal stakeholders or randomly selected citizens in conversations designed to engage the broader public enhances democratic legitimacy. With minimal issue- and candidate-advocacy, integral political leaders would develop society’s capacity to use integral conversational tools to improve its health, resilience, and collective intelligence. This both furthers and manifests evolution becoming conscious of itself.

  2. Does energy integrate?

    Energy Technology Data Exchange (ETDEWEB)

    Hira, A.; Amaya, L. [Simon Fraser University, Burnaby, BC (Canada). Dept. of Political Science

    2003-01-01

    Amidst the international movement to privatize and deregulate electricity and gas sectors of economics, the question of the integration of those sectors has been somewhat underestimated. In fact, the integration of energy markets across boundaries is occurring. We examine this process in three regions: Europe, Central America, and South America. We analyze the forces driving integration in each area, and estimate the prospects for progress. We take a close look at Nordpool, which is now the most integrated market in the world, to see if it can serve as a model for other regions. We close with a set of conditions that we suggest are necessary for a successful international integration of energy markets. (author)

  3. Retroviral integration: Site matters

    Science.gov (United States)

    Demeulemeester, Jonas; De Rijck, Jan

    2015-01-01

    Here, we review genomic target site selection during retroviral integration as a multistep process in which specific biases are introduced at each level. The first asymmetries are introduced when the virus takes a specific route into the nucleus. Next, by co‐opting distinct host cofactors, the integration machinery is guided to particular chromatin contexts. As the viral integrase captures a local target nucleosome, specific contacts introduce fine‐grained biases in the integration site distribution. In vivo, the established population of proviruses is subject to both positive and negative selection, thereby continuously reshaping the integration site distribution. By affecting stochastic proviral expression as well as the mutagenic potential of the virus, integration site choice may be an inherent part of the evolutionary strategies used by different retroviruses to maximise reproductive success. PMID:26293289

  4. Neuroeconomics and Integrated Care

    DEFF Research Database (Denmark)

    Larsen, Torben

    2012-01-01

    of integrated home care for stroke patients. Results: (1) The classical understanding of CNS is that of a dual system of ANS and Cortex. The new neuroeconomic understanding is that of a reciprocal balance of Limbic System (LS) and Neocortex (NC). This applies directly in favour of integrated homecare compared......Background: Fragmented specialized care for the frail elderly as claimed by WHO needs horizontal integration across settings. The home of the patient seems to be a promising place to integrate hospital care, primary care and social services for high-risk discharges where the quality...... of rehabilitation makes a difference. Objective: The study aims to reveal how integrated home care may be organised to improve quality of care as compared to usual hospital care. Method: A qualitative case study of the use of a neuroeconomic model in relation to multidisciplianry collaboration on a RCT...

  5. Towards Integrating Realities

    DEFF Research Database (Denmark)

    Henriksen, Lars Bo

    2017-01-01

    reality –facts, logic, values and communication. But how? Nørreklit (2004) highlights the theoretical and methodological requirements for such integration of reality. Henriksen et al. (2004), on the other hand, describe the integration processes through a series of case stories. Buta thorough...... conceptualisation of the process of integration is itself not analysed or conceptualised to the same substantive extent as are the other elements ofthe theory of reality.The key questionaddressed here thereforebecomes: how might we betteranalyse and describe this process of integration? To address this question......, Iidentify, albeit in skeletal outline,usefulsocial theoreticalcorrespondences between Arendt’s conceptualisation of action in The Human Condition(1958) and key attributes ofthe theory of reality, which, Iclaim, couldpossibly guide an entry into the ‘how’ of this elusive integration process....

  6. Personal Integrity and Leadership

    Directory of Open Access Journals (Sweden)

    Antonius Gea

    2016-07-01

    Full Text Available Generally, integrity is associated with leadership, especially in the organization or company. Integrity in leadership becomes a growing concern in business and organizations. The aim of this study was to find out the connection that could be shaped between personal integrity and the skill of leadership especially in the performance of work. This study used a library research, a literature study that done by using the available resources and relevant literature, related to the topic being discussed by the author. Books or journal articles related to topics were used as background reading to understand well about the problems of integrity and leadership, especially in the organization or company. This study finds out that the leader integrity is related to follower work role performance and that this effect is fully mediated through follower affective organizational commitment. 

  7. European and Integration Studies

    Directory of Open Access Journals (Sweden)

    N. Yu. Kaveshnikov

    2014-01-01

    Full Text Available Soviet scientific school of pan-European integration studies began to emerge in the 1960s at the Institute of World Economy and International Relations (Russian Academy of Science. Among the leading scientists who have developed methodological approaches of Soviet integration studies were M.M. Maximova, Y.A. Borko, Y. Shishkov, L.I. Capercaillie. Later, a new center for integration studies became the Institute of Europe, created in 1987. It was led by such renowned scientists as Academicians V.V. Zhurkin and N.P. Shmelev. In the 1980s the subject of the integration process in Europe attracted attention of experts from MGIMO. An important role in the development of school of integration research in the USSR was played by a MGIMO professor, head of the chair of history of international relations and foreign policy of the USSR V.B. Knyazhinskiy. His work contributed to the deliverance of the national scientific community from skepticism about the prospects for European integration. Ideas of V.B. Knyazhinsky are developed today in MGIMO by his followers A.V. Mal'gin and T.V. Ur'eva. In the mid-1990s, having retired from diplomatic service, professor Yu. Matveevskiy started to work at MGIMO. With a considerable practical experience in the field, he produced a series of monographs on the history of European integration. In his works, he analyses the development of integration processes in Western Europe from their inception to the present day, showing the gradual maturation of the necessary spiritual and material prerequisites for the start of integration and traces the various stages of the "integration". In the late 1990s, the growing demand from the domestic business and government for professionals who are capable of interacting with the European Union, has produced the necessary supply in the form of educational programs based on accumulated scientific knowledge. Setting up a discipline "European Integration" was a major step in the development

  8. Exploring the integrated approach.

    Science.gov (United States)

    1979-01-01

    The integration of family planning with maternal and child health and nutrition has been implemented in India, but integration with developmental activities like community development involves the linking up of several different disciplines. Current trends of the integrated approach to family planning in the ESCAP countries are discussed by administrators from Bangkok, Manilla, Bangalore, Islamabad, and Trivandrum, India. IPPF experience in the nongovernmental sector found that to succeed, projects must be clearly described, realistic, and capable of evaluation. Development programs can be integrated with family planning programs as well as family planning/population education programs can be integrated with development projects. Possible areas of integration are income-generating skills/services; training programs; nutrition and health (home extension services); environmental sanitation and personal hygiene; water supply, tube wells; water management, conservation; and, utilization of agricultural by-products. The message of family planning can be effectively communciated through community organizations. In the Philippines, services which could be transferred to the field were transferred to volunteers in the barangays (neighborhoods) who worked on other projects, e.g. cooperatives, nutrition. All forum participants agreed that integration is a very good concept, but practising it is a complex reality.

  9. Integrated assessment briefs

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1995-04-01

    Integrated assessment can be used to evaluate and clarify resource management policy options and outcomes for decision makers. The defining characteristics of integrated assessment are (1) focus on providing information and analysis that can be understood and used by decision makers rather than for merely advancing understanding and (2) its multidisciplinary approach, using methods, styles of study, and considerations from a broader variety of technical areas than would typically characterize studies produced from a single disciplinary standpoint. Integrated assessment may combine scientific, social, economic, health, and environmental data and models. Integrated assessment requires bridging the gap between science and policy considerations. Because not everything can be valued using a single metric, such as a dollar value, the integrated assessment process also involves evaluating trade-offs among dissimilar attributes. Scientists at Oak Ridge National Laboratory (ORNL) recognized the importance and value of multidisciplinary approaches to solving environmental problems early on and have pioneered the development of tools and methods for integrated assessment over the past three decades. Major examples of ORNL`s experience in the development of its capabilities for integrated assessment are given.

  10. Measure and integration theory

    CERN Document Server

    Burckel, Robert B

    2001-01-01

    This book gives a straightforward introduction to the field as it is nowadays required in many branches of analysis and especially in probability theory. The first three chapters (Measure Theory, Integration Theory, Product Measures) basically follow the clear and approved exposition given in the author's earlier book on ""Probability Theory and Measure Theory"". Special emphasis is laid on a complete discussion of the transformation of measures and integration with respect to the product measure, convergence theorems, parameter depending integrals, as well as the Radon-Nikodym theorem. The fi

  11. Services for data integration

    Directory of Open Access Journals (Sweden)

    Catharina Riedemann

    2003-02-01

    Full Text Available The fact that many decisions need a combination of information sources makes easy integration of geospatial data an important data usability issue. Our vision is to achieve automated just-in-time integration. As a foundation, we present a system architecture with distributed data and services. Existing and evolving standards and technologies fitting into this architecture are presented along with their scope and shortcomings. A major point is the appropriate definition of data and operation semantics. Further research is needed here to make the automatic formation of service chains for data integration possible.

  12. Three dimensional system integration

    CERN Document Server

    Papanikolaou, Antonis; Radojcic, Riko

    2010-01-01

    Three-dimensional (3D) integrated circuit (IC) stacking is the next big step in electronic system integration. It enables packing more functionality, as well as integration of heterogeneous materials, devices, and signals, in the same space (volume). This results in consumer electronics (e.g., mobile, handheld devices) which can run more powerful applications, such as full-length movies and 3D games, with longer battery life. This technology is so promising that it is expected to be a mainstream technology a few years from now, less than 10-15 years from its original conception. To achieve thi

  13. Integrals of Bessel functions

    CERN Document Server

    Luke, Yudell L

    2014-01-01

    Integrals of Bessel Functions concerns definite and indefinite integrals, the evaluation of which is necessary to numerous applied problems. A massive compendium of useful information, this volume represents a resource for applied mathematicians in many areas of academia and industry as well as an excellent text for advanced undergraduates and graduate students of mathematics.Starting with an extensive introductory chapter on basic formulas, the treatment advances to indefinite integrals, examining them in terms of Lommel and Bessel functions. Subsequent chapters explore airy functions, incomp

  14. Principles of data integration

    CERN Document Server

    Doan, AnHai; Ives, Zachary

    2012-01-01

    How do you approach answering queries when your data is stored in multiple databases that were designed independently by different people? This is first comprehensive book on data integration and is written by three of the most respected experts in the field. This book provides an extensive introduction to the theory and concepts underlying today's data integration techniques, with detailed, instruction for their application using concrete examples throughout to explain the concepts. Data integration is the problem of answering queries that span multiple data sources (e.g., databases, web

  15. Social integration i arbejdslivet

    DEFF Research Database (Denmark)

    Nielsen, Kjeld; Christensen, Allan

    2002-01-01

    of the study that social integration depends on working environment conditions as well as cultural conditions. The social integration again is crucial for the way in which employees perceive the daily work situation and indirectly also for the well-being of the clients of the institution.......The study reported in this article is based on a combination of methods related to working environment and to organisational culture. The combination is aimed at studying the extent and meaning of the social integration of the employees in an institution for handicapped adults. It is the conclusion...

  16. SQL Server Integration Services

    CERN Document Server

    Hamilton, Bill

    2007-01-01

    SQL Server 2005 Integration Services (SSIS) lets you build high-performance data integration solutions. SSIS solutions wrap sophisticated workflows around tasks that extract, transform, and load (ETL) data from and to a wide variety of data sources. This Short Cut begins with an overview of key SSIS concepts, capabilities, standard workflow and ETL elements, the development environment, execution, deployment, and migration from Data Transformation Services (DTS). Next, you'll see how to apply the concepts you've learned through hands-on examples of common integration scenarios. Once you've

  17. Four integration patterns

    DEFF Research Database (Denmark)

    Bygstad, Bendik; Nielsen, Peter Axel; Munkvold, Bjørn Erik

    2010-01-01

    and Socio-Technical Integration. We analyze and describe the advantages and disadvantages of each pattern. The four patterns are ideal types. To explore the forces and challenges in these patterns three longitudinal case studies were conducted. In particular we investigate the management challenges for each...... pattern. We find that the patterns are context sensitive, and describe the different contexts where the patterns are applicable. For IS project management the four integration patterns is a contribution to the management of integration risks, extending the vocabulary for assessing and mitigating...

  18. Improper Riemann integrals

    CERN Document Server

    Roussos, Ioannis Markos

    2013-01-01

    Improper Riemann Integrals is the first book to collect classical and modern material on the subject for undergraduate students. The book gives students the prerequisites and tools to understand the convergence, principal value, and evaluation of the improper/generalized Riemann integral. It also illustrates applications to science and engineering problems.The book contains the necessary background, theorems, and tools, along with two lists of the most important integrals and sums computed in the text. Numerous examples at various levels of difficulty illustrate the concepts and theorems. The

  19. Ethics and academic integrity.

    Science.gov (United States)

    Milton, Constance L

    2015-01-01

    Academics from across the globe must navigate ever-increasing demands for research, practice, and educational productivity. With the increased demands, nurse faculty must choose value priorities and actions that reflect academic integrity. What does it mean to choose actions that reflect personal integrity in the academic arena? This article begins an important nursing philosophical and theoretical discussion that members and future members of the discipline of nursing must reflect upon and grapple with as they consider what it potentially means to act with straight thinking and integrity in academics. © The Author(s) 2014.

  20. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  1. Approximate calculation of integrals

    CERN Document Server

    Krylov, V I

    2006-01-01

    A systematic introduction to the principal ideas and results of the contemporary theory of approximate integration, this volume approaches its subject from the viewpoint of functional analysis. In addition, it offers a useful reference for practical computations. Its primary focus lies in the problem of approximate integration of functions of a single variable, rather than the more difficult problem of approximate integration of functions of more than one variable.The three-part treatment begins with concepts and theorems encountered in the theory of quadrature. The second part is devoted to t

  2. Integrated management systems

    DEFF Research Database (Denmark)

    Jørgensen, Tine Herreborg; Remmen, Arne; Mellado, M. Dolores

    2006-01-01

    Different approaches to integration of management systems (ISO 9001, ISO 14001, OHSAS 18001 and SA 8000) with various levels of ambition have emerged. The tendency of increased compatibility between these standards has paved the road for discussions of, how to understand the different aspects....... At present, national IMS standards are being developed, and the IMS standards in Denmark and Spain are being analysed regarding the ambition level for integration. Should the ISO organisation decide to make a standard for IMS, then it would be necessary to consider the different levels of integration...

  3. INTEGRATED RENEWAL PROCESS

    Directory of Open Access Journals (Sweden)

    Suyono .

    2012-07-01

    Full Text Available The marginal distribution of integrated renewal process is derived in this paper. Our approach is based on the theory of point processes, especially Poisson point processes. The results are presented in the form of Laplace transforms.

  4. Alternative and Integrative Medicine

    Science.gov (United States)

    ... for e-updates Please leave this field empty Alternative & Integrative Medicine SHARE Home > Treatment and Care > Treatments Listen Alternative medicine is a term used to define therapies other ...

  5. NASA UAS Integration Efforts

    Science.gov (United States)

    Hackenberg, Davis

    2017-01-01

    This is a benefit to NASA because of all the networking opportunities as well as sharing information about UAS-NAS within the UAS community. NASA has developed, and is executing, a Cohesive Strategy for UAS Integration

  6. Integrated Disposal Facility

    Data.gov (United States)

    Federal Laboratory Consortium — Located near the center of the 586-square-mile Hanford Site is the Integrated Disposal Facility, also known as the IDF.This facility is a landfill similar in concept...

  7. Integrated Health Management Definitions

    Data.gov (United States)

    National Aeronautics and Space Administration — The Joint Army Navy NASA Air Force Modeling and Simulation Subcommittee's Integrated Health Management panel was started about 6 years ago to help foster...

  8. Integration a functional approach

    CERN Document Server

    Bichteler, Klaus

    1998-01-01

    This book covers Lebesgue integration and its generalizations from Daniell's point of view, modified by the use of seminorms. Integrating functions rather than measuring sets is posited as the main purpose of measure theory. From this point of view Lebesgue's integral can be had as a rather straightforward, even simplistic, extension of Riemann's integral; and its aims, definitions, and procedures can be motivated at an elementary level. The notion of measurability, for example, is suggested by Littlewood's observations rather than being conveyed authoritatively through definitions of (sigma)-algebras and good-cut-conditions, the latter of which are hard to justify and thus appear mysterious, even nettlesome, to the beginner. The approach taken provides the additional benefit of cutting the labor in half. The use of seminorms, ubiquitous in modern analysis, speeds things up even further. The book is intended for the reader who has some experience with proofs, a beginning graduate student for example. It might...

  9. Integrated PET/MR

    National Research Council Canada - National Science Library

    Quick, Harald H

    2014-01-01

    Integrated whole‐body PET/MR hybrid imaging combines excellent soft tissue contrast and various functional imaging parameters provided by MR with high sensitivity and quantification of radiotracer metabolism provided...

  10. Integrated inventory information system

    Digital Repository Service at National Institute of Oceanography (India)

    Sarupria, J.S.; Kunte, P.D.

    The nature of oceanographic data and the management of inventory level information are described in Integrated Inventory Information System (IIIS). It is shown how a ROSCOPO (report on observations/samples collected during oceanographic programme...

  11. Complementary and Integrative Medicine

    Science.gov (United States)

    ... medical treatments that are not part of mainstream medicine. When you are using these types of care, it may be called complementary, integrative, or alternative medicine. Complementary medicine is used together with mainstream medical ...

  12. Retroviral DNA Integration

    Science.gov (United States)

    2016-01-01

    The integration of a DNA copy of the viral RNA genome into host chromatin is the defining step of retroviral replication. This enzymatic process is catalyzed by the virus-encoded integrase protein, which is conserved among retroviruses and LTR-retrotransposons. Retroviral integration proceeds via two integrase activities: 3′-processing of the viral DNA ends, followed by the strand transfer of the processed ends into host cell chromosomal DNA. Herein we review the molecular mechanism of retroviral DNA integration, with an emphasis on reaction chemistries and architectures of the nucleoprotein complexes involved. We additionally discuss the latest advances on anti-integrase drug development for the treatment of AIDS and the utility of integrating retroviral vectors in gene therapy applications. PMID:27198982

  13. Crisis and Regional Integration

    DEFF Research Database (Denmark)

    Dosenrode, Søren

    , Tunisia, Egypt …. ), where the crisis referred to could be humanitarian, environmental, economic, political … Europe, too, has also according to mass media, been a victim of a crisis, the financial one. Could ‘crisis’ be a beginning of enhanced regional integration? This paper will try to look...... at the processes of regional integration in relation to ‘crisis’ in Africa and Europe. First, this paper will look at the concept of ‘crisis’, before it moves on to discuss ‘regional integration’ and the correlation between the two, emphasizing the approaches of neo-functionalism and federal theory....... This is the basis for two short case studies of African and European regional integration. The paper tentative answers to the question: will the crisis in Africa and Europe respectively further or block regional integration? With a ‘that depends’. But the use of Federalism theory and neo-functionalism is seen...

  14. European Economic Integration

    Science.gov (United States)

    Huston, James A.

    1971-01-01

    Recounts the history and problems of European Economic Integration from the first post World War II organization, the OEEC, to the EEC (Common Market) and the EFTA. Suggestions for further reading are included. (JB)

  15. Measuring integrated care

    DEFF Research Database (Denmark)

    Strandberg-Larsen, Martin

    2011-01-01

    the multi-dimensional aspects of integrated healthcare delivery. 2) To assess the level of integration of the Danish healthcare system. 3) To assess the use of joint health plans as a tool for coordination between the regional and local level in the Danish healthcare system. 4) To compare the inputs...... different levels of the Danish healthcare system. The survey data were used to allow for analysis of the level of integration achieved. Data from the survey were additionally used to investigate the use of joint health planning as a tool for coordination of regional-local healthcare delivery. Analysis...... is a widespread challenge, and that only half or less than half of patients in need of integrated services receive such care. Options for decision makers and managers are discussed. From a theoretical perspective joint health plans as applied in Denmark do not match the degree of complexity in the healthcare...

  16. Integrated Silicon Optoelectronics

    CERN Document Server

    Zimmermann, Horst K

    2010-01-01

    Integrated Silicon Optoelectronics synthesizes topics from optoelectronics and microelectronics. The book concentrates on silicon as the major base of modern semiconductor devices and circuits. Starting from the basics of optical emission and absorption, as well as from the device physics of photodetectors, the aspects of the integration of photodetectors in modern bipolar, CMOS, and BiCMOS technologies are discussed. Detailed descriptions of fabrication technologies and applications of optoelectronic integrated circuits are included. The book, furthermore, contains a review of the newest state of research on eagerly anticipated silicon light emitters. In order to cover the topics comprehensively, also included are integrated waveguides, gratings, and optoelectronic power devices. Numerous elaborate illustrations facilitate and enhance comprehension. This extended edition will be of value to engineers, physicists, and scientists in industry and at universities. The book is also recommended to graduate student...

  17. Integration, measure and probability

    CERN Document Server

    Pitt, H R

    2012-01-01

    Introductory treatment develops the theory of integration in a general context, making it applicable to other branches of analysis. More specialized topics include convergence theorems and random sequences and functions. 1963 edition.

  18. Integrating Forensic Science.

    Science.gov (United States)

    Funkhouser, John; Deslich, Barbara J.

    2000-01-01

    Explains the implementation of forensic science in an integrated curriculum and discusses the advantages of this approach. Lists the forensic science course syllabi studied in three high schools. Discusses the unit on polymers in detail. (YDS)

  19. Integrated Biophotonics with CYTOP

    Directory of Open Access Journals (Sweden)

    Björn Agnarsson

    2012-02-01

    Full Text Available We describe how the amorphous fluoropolymer CYTOP can be advantageously used as a waveguide cladding material in integrated optical circuits suitable for applications in integrated biophotonics. The unique refractive index of CYTOP (n = 1.34 enables the cladding material to be well index-matched to an optically probed sample solution. Furthermore, ultra-high index contrast waveguides can be fabricated, using conventional optical polymers as waveguide core materials, offering a route to large-scale integration of optical functions on a single chip. We discuss applications of this platform to evanescent-wave excitation fluorescence microscopy, passive and/or thermo-electrically-controlled on-chip light manipulation, on-chip light generation, and direct integration with microfluidic circuits through low-temperature bonding.

  20. Financial Integrity Benchmarks

    Data.gov (United States)

    City of Jackson, Mississippi — This data compiles standard financial integrity benchmarks that allow the City to measure its financial standing. It measure the City's debt ratio and bond ratings....

  1. Integrated Reporting Information System -

    Data.gov (United States)

    Department of Transportation — The Integrated Reporting Information System (IRIS) is a flexible and scalable web-based system that supports post operational analysis and evaluation of the National...

  2. Integrity, Concept of

    DEFF Research Database (Denmark)

    Rendtorff, Jacob Dahl

    2015-01-01

    Integrity can be defined in the following sense: Integrity accounts for the inviolability of the human being. Although originally a virtue of uncorrupted character, expressing uprightness, honesty, and good intentions, it has, like dignity, been universalized as a quality of the person as such....... Thus, it refers to the coherence of life that should not be touched and destroyed. It is coherence of life being remembered from experiences and therefore can be told in a narrative. Therefore respect for integrity is respect for privacy and in particular for the patient's understanding of his or her...... own life and illness. Integrity is the most important principle for the creation of trust between physician and patient, because it demands that the physician listens to the patient telling the story about his or her life and illness....

  3. Entrepreneurial Integration Skills

    DEFF Research Database (Denmark)

    Bauer, Florian; Schriber, Svante; King, David R.

    2016-01-01

    on 116 acquisitions, we find that entrepreneurial integration skills can display both advantages and disadvantages. While it helps to realize expected and serendipitous synergies, it can also trigger employee uncertainty due to decreased transparency. In supplementary analysis, we show measures...

  4. State Program Integrity Reviews

    Data.gov (United States)

    U.S. Department of Health & Human Services — State program integrity reviews play a critical role in how CMS provides effective support and assistance to states in their efforts to combat provider fraud and...

  5. Integrated library systems.

    OpenAIRE

    Goldstein, C M

    1983-01-01

    The development of integrated library systems is discussed. The four major discussion points are (1) initial efforts; (2) network resources; (3) minicomputer-based systems; and (4) beyond library automation. Four existing systems are cited as examples of current systems.

  6. Wellbore Integrity Network

    Energy Technology Data Exchange (ETDEWEB)

    Carey, James W. [Los Alamos National Laboratory; Bachu, Stefan [Alberta Innovates

    2012-06-21

    In this presentation, we review the current state of knowledge on wellbore integrity as developed in the IEA Greenhouse Gas Programme's Wellbore Integrity Network. Wells are one of the primary risks to the successful implementation of CO{sub 2} storage programs. Experimental studies show that wellbore materials react with CO{sub 2} (carbonation of cement and corrosion of steel) but the impact on zonal isolation is unclear. Field studies of wells in CO{sub 2}-bearing fields show that CO{sub 2} does migrate external to casing. However, rates and amounts of CO{sub 2} have not been quantified. At the decade time scale, wellbore integrity is driven by construction quality and geomechanical processes. Over longer time-scales (> 100 years), chemical processes (cement degradation and corrosion) become more important, but competing geomechanical processes may preserve wellbore integrity.

  7. Advances in integrated optics

    CERN Document Server

    Chester, A; Bertolotti, M

    1994-01-01

    This volwne contains the Proceedings of a two-week summer conference titled "Advances in Integrated Optics" held June 1-9, 1993, in Erice, Sicily. This was the 18th annual course organized by the International School of Quantum Electronics, under the auspices of the "Ettore Majorana" Centre for Scientific Culture. The term Integrated Optics signifies guided-wave optical circuits consisting of two or more devices on a single substrate. Since its inception in the late 1960's, Integrated Optics has evolved from a specialized research topic into a broad field of work, ranging from basic research through commercial applications. Today many devices are available on market while a big effort is devolved to research on integrated nonlinear optical devices. This conference was organized to provide a comprehensive survey of the frontiers of this technology, including fundamental concepts, nonlinear optical materials, devices both in the linear and nonlinear regimes, and selected applications. These Proceedings update a...

  8. Integrated Criteria Document Chromium

    OpenAIRE

    Slooff W; Cleven RFMJ; Janus JA; van der Poel P; van Beelen P; Boumans LJM; Canton JH; Eerens HC; Krajnc EI; de Leeuw FAAM; Matthijsen AJCM; van de Meent D; van der Meulen A; Mohn GR; Wijland GC

    1990-01-01

    Betreft de engelse versie van rapport 758701001
    Bij dit rapport behoort een appendix onder hetzelfde nummer getiteld: "Integrated Criteria Document Chromium: Effects" Auteurs: Janus JA; Krajnc EI
    (appendix: see 710401002A)

  9. Pumping approximately integrable systems

    Science.gov (United States)

    Lange, Florian; Lenarčič, Zala; Rosch, Achim

    2017-06-01

    Weak perturbations can drive an interacting many-particle system far from its initial equilibrium state if one is able to pump into degrees of freedom approximately protected by conservation laws. This concept has for example been used to realize Bose-Einstein condensates of photons, magnons and excitons. Integrable quantum systems, like the one-dimensional Heisenberg model, are characterized by an infinite set of conservation laws. Here, we develop a theory of weakly driven integrable systems and show that pumping can induce large spin or heat currents even in the presence of integrability breaking perturbations, since it activates local and quasi-local approximate conserved quantities. The resulting steady state is qualitatively captured by a truncated generalized Gibbs ensemble with Lagrange parameters that depend on the structure but not on the overall amplitude of perturbations nor the initial state. We suggest to use spin-chain materials driven by terahertz radiation to realize integrability-based spin and heat pumps.

  10. (Dis) integrated valuation

    DEFF Research Database (Denmark)

    Barton, D. N.; Kelemen, E.; Dick, J.

    2017-01-01

    The operational challenges of integrated ecosystem service (ES) appraisals are determined by study purpose, system complexity and uncertainty, decision-makers' requirements for reliability and accuracy of methods, and approaches to stakeholder-science interaction in different decision contexts. T...

  11. Integrated Surface Dataset (Global)

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — The Integrated Surface (ISD) Dataset (ISD) is composed of worldwide surface weather observations from over 35,000 stations, though the best spatial coverage is...

  12. Conjugate-Gradient Algorithms For Dynamics Of Manipulators

    Science.gov (United States)

    Fijany, Amir; Scheid, Robert E.

    1993-01-01

    Algorithms for serial and parallel computation of forward dynamics of multiple-link robotic manipulators by conjugate-gradient method developed. Parallel algorithms have potential for speedup of computations on multiple linked, specialized processors implemented in very-large-scale integrated circuits. Such processors used to stimulate dynamics, possibly faster than in real time, for purposes of planning and control.

  13. Page 1 Sidhana, Vol. 9, Part 2, September 1986, pp. 139-156. (C ...

    Indian Academy of Sciences (India)

    artificial intelligence (Al) techniques, and so Al provides the essential link between pattern recognition domains and different application systems. No attempt is made to discuss other essential conceptual building blocks, such as software engineering, computer architecture and very large scale integration technology unless ...

  14. IDC Integrated Master Plan.

    Energy Technology Data Exchange (ETDEWEB)

    Clifford, David J.; Harris, James M.

    2014-12-01

    This is the IDC Re-Engineering Phase 2 project Integrated Master Plan (IMP). The IMP presents the major accomplishments planned over time to re-engineer the IDC system. The IMP and the associate Integrated Master Schedule (IMS) are used for planning, scheduling, executing, and tracking the project technical work efforts. REVISIONS Version Date Author/Team Revision Description Authorized by V1.0 12/2014 IDC Re- engineering Project Team Initial delivery M. Harris

  15. Fakta om integration

    DEFF Research Database (Denmark)

    Frederiksen, Hanne Winther; Nørredam, Marie

    Afsnit i Social- og Integrationsministeriets årlige publikation "Fakta om integration". Bygger på et litteraturreview foretaget i 2012 i samarbejde med Forskningscenter for Migration, Etnicitet og Sundhed (MESU) på opdrag af Social- og Integrationsministeriet.......Afsnit i Social- og Integrationsministeriets årlige publikation "Fakta om integration". Bygger på et litteraturreview foretaget i 2012 i samarbejde med Forskningscenter for Migration, Etnicitet og Sundhed (MESU) på opdrag af Social- og Integrationsministeriet....

  16. Integrated Electric Gas Turbine

    OpenAIRE

    Millsaps, Knox T.

    2010-01-01

    Patent An integrated electric gas turbine comprises a compressor that includes a plurality of airfoils. An electric motor is arranged to drive the compressor, and a combustor is arranged to receive compressed air from the compressor and further arranged to receive a fuel input. A turbine is arranged to receive the combustion gases from the combustor. A generator is integrated with the turbine and arranged to provide a power output. A controller is connected between the...

  17. Integrated infrared array technology

    Science.gov (United States)

    Goebel, J. H.; Mccreight, C. R.

    1987-01-01

    An overview of integrated infrared (IR) array technology is presented. Although the array pixel formats are smaller, and the readout noise of IR arrays is larger than the corresponding values achieved with optical charge-coupled-device silicon technology, substantial progress is being made in IR technology. Both existing IR arrays and those being developed are described. Examples of astronomical images are given which illustrate the potential of integrated IR arrays for scientific investigations.

  18. Discrete pseudo-integrals

    Czech Academy of Sciences Publication Activity Database

    Mesiar, Radko; Li, J.; Pap, E.

    2013-01-01

    Roč. 54, č. 3 (2013), s. 357-364 ISSN 0888-613X R&D Projects: GA ČR GAP402/11/0378 Institutional support: RVO:67985556 Keywords : concave integral * pseudo-addition * pseudo- multiplication Subject RIV: BA - General Mathematics Impact factor: 1.977, year: 2013 http://library.utia.cas.cz/separaty/2013/E/mesiar-discrete pseudo-integrals. pdf

  19. Integration gennem kroppen

    DEFF Research Database (Denmark)

    Bonde, Hans

    2013-01-01

    Den dansk-jødiske idrætsforening Hakoah er et godt eksempel på, at idrætten historisk har fungeret som en arena for integration i det danske samfund.......Den dansk-jødiske idrætsforening Hakoah er et godt eksempel på, at idrætten historisk har fungeret som en arena for integration i det danske samfund....

  20. Idrott som integration

    OpenAIRE

    Karlefors, Inger; Hertting, Krister

    2010-01-01

    Competitive sport is a global phenomenon with a common language, but at the same time locally embedded in the national culture. The global character gives competitive sport an attraction, which can create an important arena for integration when people arrive to a new country. Problems can rise when diverse expectations and images meet. To create understanding and facilitate integration for children and youth from different countries it is important to understand which images of sport that is ...

  1. Agroecology : integration with livestock

    OpenAIRE

    Tichit, Muriel; Lecompte, Philippe; Dumont, Bertrand

    2014-01-01

    Livestock systems are a large global asset contributing to food security and poverty alleviation, but livestock supply chains have major environmental impacts at global scale. The scientific literature on agroecology has not yet integrated livestock systems; only 5 percent of the indexed studies concerning agroecology deal with livestock. Following Dumont et al. (2013), we review five principles for integrating livestock systems within the agroecology debate: (i) adopting management practices...

  2. The Integrated Renovation Process

    DEFF Research Database (Denmark)

    Galiotto, Nicolas; Heiselberg, Per; Knudstrup, Mary-Ann

    2015-01-01

    . With the purpose of overcoming such barriers, a new scheme was proposed: the Integrated Renovation Process. In this paper, the scheme is applied to two single-family homes and is called the Integrated Renovation Process for Homes (IRP4homes). In both case studies, the newly developed methodology successfully led...... renovated home. Most homeowners’ needs, preferences and personal values were fulfilled. Eventually, all homeowners selected a high-performance renovation scenario....

  3. APPROACHES TO PUBLIC INTEGRITY

    Directory of Open Access Journals (Sweden)

    Simona-Roxana ULMAN

    2015-08-01

    Full Text Available Both concepts, integrity and public integrity, are always asked qualities in the social and economic environment, but they are never well defined. In this context, finding precise definitions and offering an ample explanation of the concepts are desired and useful for both economic theoretical and practical levels and become the aim of the present paper. Without a good understanding of a concept, no one is capable to attain it. In this context, it is impossible to ask for a public sector of integrity if both public actors and the citizens do not know what it really means. Therefore, the public actors first have to understand what integrity really supposes, and, then, to be capable to respect its principles. Taking into consideration the effects of public integrity or, on its opposite, of the divergence from it, especially represented by the phenomenon of corruption, on the economy at the macro, but also, on the micro level, public integrity in itself becomes a real economic problem that is aimed to be extensively analyzed through our interdisciplinary approach.

  4. The Implications of VLSI ROM Chips on Numerical Analysis.

    Science.gov (United States)

    1982-01-08

    pattern transferred onto the silicon wafer. That is, they are manufactured directly. The advatage of this approach is extremely low cost when produced...the writing of an operating system, and thuis, is impractical for the numerical j analyst. As software design aide become available, this technique may...rare for anyone to write machine code. Obviously, some type of translation j is made from another language. At the elementary level, an assembly

  5. Rapid Assemblers for Voxel-Based VLSI Robotics

    Science.gov (United States)

    2014-02-12

    and actuators based on small DC motors. We call these parts Bitblox, and intend to use them as the " ink " in a system that automatically designs and...0 ∗ ≅ −0.010 ∗ 2 − 0.1|0 ∗| + 2) [6]. The permeability (which is assumed to be isotropic) can be estimated analytically for a bed of packed...spheres by relating it to the permeability of a series of parallel straight cylinders [7]. Since permeability of spherical packed bed of spheres can

  6. Macromodeling and Optimization of Digital MOS VLSI Circuits,

    Science.gov (United States)

    1986-03-01

    the macromodeling approach. Section 3 presents models for MOS inverters. Our analysis opens with a treatment of the resistor-capacitor model. After...implications. First, the DC transfer curve is flat outside of the range VtN E (VIL, VIH ].This means that the gate will not respond until a rising input has...reached VIL, or until a failing input has dropped to ViH . These "dead zones" provide immunity to noise in the input signal. Second, the two modes of

  7. How to build VLSI-efficient neural chips

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-02-01

    This paper presents several upper and lower bounds for the number-of-bits required for solving a classification problem, as well as ways in which these bounds can be used to efficiently build neural network chips. The focus will be on complexity aspects pertaining to neural networks: (1) size complexity and depth (size) tradeoffs, and (2) precision of weights and thresholds as well as limited interconnectivity. They show difficult problems-exponential growth in either space (precision and size) and/or time (learning and depth)-when using neural networks for solving general classes of problems (particular cases may enjoy better performances). The bounds for the number-of-bits required for solving a classification problem represent the first step of a general class of constructive algorithms, by showing how the quantization of the input space could be done in O (m{sup 2}n) steps. Here m is the number of examples, while n is the number of dimensions. The second step of the algorithm finds its roots in the implementation of a class of Boolean functions using threshold gates. It is substantiated by mathematical proofs for the size O (mn/{Delta}), and the depth O [log(mn)/log{Delta}] of the resulting network (here {Delta} is the maximum fan in). Using the fan in as a parameter, a full class of solutions can be designed. The third step of the algorithm represents a reduction of the size and an increase of its generalization capabilities. Extensions by using analogue COMPARISONs, allows for real inputs, and increase the generalization capabilities at the expense of longer training times. Finally, several solutions which can lower the size of the resulting neural network are detailed. The interesting aspect is that they are obtained for limited, or even constant, fan-ins. In support of these claims many simulations have been performed and are called upon.

  8. Principles of VLSI RTL design a practical guide

    CERN Document Server

    Churiwala, Sanjay; Gianfagna, Mike

    2011-01-01

    This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

  9. VLSI Workshop and Project: February-November 1982.

    Science.gov (United States)

    1984-09-01

    proscribed or constrained, and some CIF statements have been for- bidden, to avoid possible bugs remaining in the CIF to MEBES conversion program, and to...carrying magnetic tapes were forwarded to USA on 4 June 1982. 4.4 Data format conversion The CIF-code data was converted to another format ( MEBES ) for

  10. UW/NW (University of Washington/Northwest) VLSI Consortium

    Science.gov (United States)

    1985-10-30

    fabricated did not (by simulation evidence) meet the SOns PLA None durectly. The osi gatrateaon wor dot p"f ranc goatmor requirements but by then...was no interdependence among the architectural compo- * use design generators nents on clock characteristics, which promoted more indepeu- deuce among

  11. Minimal transient modes for faults detection in analogue VLSI circuits

    OpenAIRE

    KADIM H.J.

    2003-01-01

    The method introduced here uses an investigation of the dominant natural mode to identify possible abnormalities in analogue circuits due to faults and parameter variations, and determining the reliability of circuits when operating in the presence of faults.

  12. VLSI Design Tools, Reference Manual, Release 2.0.

    Science.gov (United States)

    1984-08-01

    enhacement end depletion transistors.) Gate, source, and drain are the gate, source, and drain nodes of the transistors. Length and width ae the channel...reset; Inpad - Input pad; outpad - Output pad; -.. trlpad - Tristate pad; trpadm - Mirror image of tristate pad; frame40 - Forty pin padframe; vdd

  13. Formal Multilevel Hierarchical Verification of Synchronous MOS VLSI Circuits.

    Science.gov (United States)

    1987-06-01

    Floats, Vectors, Streams, and Procedures. Booleans There are only two boolean values Trus and Fake . They are denoted I and 0, respectively. The...Patel, Martine Schlag, and Milos Ercegovac, "vFP: An environment for the multi-level specification, analysis, and synthesis of hardward algorithms

  14. Non-linear feedback neural networks VLSI implementations and applications

    CERN Document Server

    Ansari, Mohd Samar

    2014-01-01

    This book aims to present a viable alternative to the Hopfield Neural Network (HNN) model for analog computation. It is well known that the standard HNN suffers from problems of convergence to local minima, and requirement of a large number of neurons and synaptic weights. Therefore, improved solutions are needed. The non-linear synapse neural network (NoSyNN) is one such possibility and is discussed in detail in this book. This book also discusses the applications in computationally intensive tasks like graph coloring, ranking, and linear as well as quadratic programming. The material in the book is useful to students, researchers and academician working in the area of analog computation.

  15. Sputtering materials for VLSI and thin film devices

    CERN Document Server

    Sarkar, Jaydeep

    2010-01-01

    An important resource for students, engineers and researchers working in the area of thin film deposition using physical vapor deposition (e.g. sputtering) for semiconductor, liquid crystal displays, high density recording media and photovoltaic device (e.g. thin film solar cell) manufacturing. This book also reviews microelectronics industry topics such as history of inventions and technology trends, recent developments in sputtering technologies, manufacturing steps that require sputtering of thin films, the properties of thin films and the role of sputtering target performance on overall p

  16. Seeing chips : analog VLSI circuits for computer vision

    OpenAIRE

    Koch, Christof

    1989-01-01

    Vision is simple. We open our eyes and, instantly, the world surrounding us is perceived in all its splendor. Yet Artificial Intelligence has been trying with very limited success for over 20 years to endow machines with similar abilities. A large van, filled with computers and driving unguided at a mile per hour across gently sloping hills in Colorado and using a laser-range system to “see” is the most we have accomplished so far. On the other hand, computers can play a decent game of chess ...

  17. A VLSI System-on-Chip for Particle Detectors

    CERN Document Server

    AUTHOR|(CDS)2078019

    In this thesis I present a System-on-Chip (SoC) I designed to oer a self- contained, compact data acquisition platform for micromegas detector mon- itoring. I carried on my work within the RD-51 collab oration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electro de, pro cess the data and p erform monitoring tests. The SoC is built around on a custom 8-bit micropro cessor with internal mem- ory resources and emb eds the p eripherals to b e interf...

  18. Integrative medicine for cancer treatment

    Science.gov (United States)

    ... page: //medlineplus.gov/ency/patientinstructions/000932.htm Integrative medicine for cancer treatment To use the sharing features ... This is why many people turn to integrative medicine. Integrative medicine (IM) refers to any type of ...

  19. Integration zweiter Klasse Second-Class Integration

    Directory of Open Access Journals (Sweden)

    Gesine Fuchs

    2004-07-01

    Full Text Available Regula Stämpfli analysiert den Zusammenhang zwischen der Mobilisierung von Frauen für die Landesverteidigung und den ihnen zugestandenen Staatsbürgerrechten in der Schweiz von 1914 bis 1945. In einem historischen Bogen vom Ersten Weltkrieg, der von starkem weiblichen Engagement in der Sozialarbeit gekennzeichnet war, über die Debatten zur schweizerischen Demokratie in der Zwischenkriegszeit bis zum Frauenhilfsdienst im Zweiten Weltkrieg verfolgt sie, in welchem Ausmaß die Aufrechterhaltung der alten Geschlechterordnung oberste Leitlinie für Politik und Militär war. Die Integration von Frauen und Frauenverbänden in die Landesverteidigung war instrumentell und unvollständig. Trotz gegenteiliger Hoffnungen wurden ihnen bis 1971 politische Rechte verweigert.Regula Stämpfli analyzes the connection between the mobilization of women for national defence and their acquired citizenship rights in Switzerland from 1914 to 1945. In a historical span from the First World War, characterized by women’s strong engagement in social work, to the debates of Swiss democracy in the inner-war period to women’s auxiliary work during the Second World War, she traces to what extent the maintenance of the old gender order served as the highest guideline for politics and the military. The integration of women and women’s organizations in national defence was instrumental and incomplete. Despite opposing hopes, they were denied political rights until 1971.

  20. Conceptual Integration using Wrapped Applications

    OpenAIRE

    Gassner, Christian; Österle, Hubert; Hotaka, Ryosuke

    1996-01-01

    This paper describes how object-oriented concepts can be used throughout system development for integration purposes. Based on the distinction of physical and conceptual integration the concept of object wrapping is discussed for the integration of non-object-oriented systems. By regarding applications as high-level objects, i.e. wrapped applications, integration is achieved by modelling so-called integration relationships between these wrapped applications. While in conceptual integration re...

  1. Integration i flere variable

    DEFF Research Database (Denmark)

    Markvorsen, Steen

    2010-01-01

    Denne note handler om parameterfremstillinger for kurver, flader og rumlige områder og om integration af funktioner på sådanne geometriske objekter. Formålet er primært at opstille og motivere de generelle definitioner og beregninger af henholdsvis kurve- \\, flade- \\, og rum-integraler. Udgangspu......Denne note handler om parameterfremstillinger for kurver, flader og rumlige områder og om integration af funktioner på sådanne geometriske objekter. Formålet er primært at opstille og motivere de generelle definitioner og beregninger af henholdsvis kurve- \\, flade- \\, og rum......-integralerne. Undervejs introduceres \\texttt{Integrator8}. Det er en pakke med Maple procedurer, som er udviklet specielt med henblik på eksempelbaseret visuel læring af de indledende integrationsbegreber og deres mangfoldige anvendelser. Vi giver eksempler på, hvordan integration i flere variable anvendes til beregning...... og forståelse af rumfang, vægt, massemidtpunkter, inertimomenter, kraftmomenter, etc. Flowkurverne for et givet vektorfelt i rummet kan findes og visualiseres med \\texttt{Integrator8}. De vigtige begreber divergens og rotation for et vektorfelt fremtræder derved som naturlige størrelser til...

  2. Integrated Budget Office Toolbox

    Science.gov (United States)

    Rushing, Douglas A.; Blakeley, Chris; Chapman, Gerry; Robertson, Bill; Horton, Allison; Besser, Thomas; McCarthy, Debbie

    2010-01-01

    The Integrated Budget Office Toolbox (IBOT) combines budgeting, resource allocation, organizational funding, and reporting features in an automated, integrated tool that provides data from a single source for Johnson Space Center (JSC) personnel. Using a common interface, concurrent users can utilize the data without compromising its integrity. IBOT tracks planning changes and updates throughout the year using both phasing and POP-related (program-operating-plan-related) budget information for the current year, and up to six years out. Separating lump-sum funds received from HQ (Headquarters) into separate labor, travel, procurement, Center G&A (general & administrative), and servicepool categories, IBOT creates a script that significantly reduces manual input time. IBOT also manages the movement of travel and procurement funds down to the organizational level and, using its integrated funds management feature, helps better track funding at lower levels. Third-party software is used to create integrated reports in IBOT that can be generated for plans, actuals, funds received, and other combinations of data that are currently maintained in the centralized format. Based on Microsoft SQL, IBOT incorporates generic budget processes, is transportable, and is economical to deploy and support.

  3. HIV DNA Integration

    Science.gov (United States)

    Craigie, Robert; Bushman, Frederic D.

    2012-01-01

    Retroviruses are distinguished from other viruses by two characteristic steps in the viral replication cycle. The first is reverse transcription, which results in the production of a double-stranded DNA copy of the viral RNA genome, and the second is integration, which results in covalent attachment of the DNA copy to host cell DNA. The initial catalytic steps of the integration reaction are performed by the virus-encoded integrase (IN) protein. The chemistry of the IN-mediated DNA breaking and joining steps is well worked out, and structures of IN-DNA complexes have now clarified how the overall complex assembles. Methods developed during these studies were adapted for identification of IN inhibitors, which received FDA approval for use in patients in 2007. At the chromosomal level, HIV integration is strongly favored in active transcription units, which may promote efficient viral gene expression after integration. HIV IN binds to the cellular factor LEDGF/p75, which promotes efficient infection and tethers IN to favored target sites. The HIV integration machinery must also interact with many additional host factors during infection, including nuclear trafficking and pore proteins during nuclear entry, histones during initial target capture, and DNA repair proteins during completion of the DNA joining steps. Models for some of the molecular mechanisms involved have been proposed, but important details remain to be clarified. PMID:22762018

  4. Integrated work management system.

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Edward J., Jr.; Henry, Karen Lynne

    2010-06-01

    Sandia National Laboratories develops technologies to: (1) sustain, modernize, and protect our nuclear arsenal (2) Prevent the spread of weapons of mass destruction; (3) Provide new capabilities to our armed forces; (4) Protect our national infrastructure; (5) Ensure the stability of our nation's energy and water supplies; and (6) Defend our nation against terrorist threats. We identified the need for a single overarching Integrated Workplace Management System (IWMS) that would enable us to focus on customer missions and improve FMOC processes. Our team selected highly configurable commercial-off-the-shelf (COTS) software with out-of-the-box workflow processes that integrate strategic planning, project management, facility assessments, and space management, and can interface with existing systems, such as Oracle, PeopleSoft, Maximo, Bentley, and FileNet. We selected the Integrated Workplace Management System (IWMS) from Tririga, Inc. Facility Management System (FMS) Benefits are: (1) Create a single reliable source for facility data; (2) Improve transparency with oversight organizations; (3) Streamline FMOC business processes with a single, integrated facility-management tool; (4) Give customers simple tools and real-time information; (5) Reduce indirect costs; (6) Replace approximately 30 FMOC systems and 60 homegrown tools (such as Microsoft Access databases); and (7) Integrate with FIMS.

  5. Reconfigurable Integrated Optoelectronics

    Directory of Open Access Journals (Sweden)

    Richard Soref

    2011-01-01

    Full Text Available Integrated optics today is based upon chips of Si and InP. The future of this chip industry is probably contained in the thrust towards optoelectronic integrated circuits (OEICs and photonic integrated circuits (PICs manufactured in a high-volume foundry. We believe that reconfigurable OEICs and PICs, known as ROEICs and RPICs, constitute the ultimate embodiment of integrated photonics. This paper shows that any ROEIC-on-a-chip can be decomposed into photonic modules, some of them fixed and some of them changeable in function. Reconfiguration is provided by electrical control signals to the electro-optical building blocks. We illustrate these modules in detail and discuss 3D ROEIC chips for the highest-performance signal processing. We present examples of our module theory for RPIC optical lattice filters already constructed, and we propose new ROEICs for directed optical logic, large-scale matrix switching, and 2D beamsteering of a phased-array microwave antenna. In general, large-scale-integrated ROEICs will enable significant applications in computing, quantum computing, communications, learning, imaging, telepresence, sensing, RF/microwave photonics, information storage, cryptography, and data mining.

  6. Zambia takes integrated course.

    Science.gov (United States)

    Mulimba, L

    1995-05-01

    Zambia implemented a vertical family planning program for 22 years. Assessment of the fruits of that approach, however, point to approximately 90% of Zambia's population being aware of the benefits of using family planning, but an only 15% level of contraceptive prevalence. The Planned Parenthood Association of Zambia is therefore integrating family planning services through the JOICFP Integrated Project involving communities, schools, women's programs, and the deworming of communities. In so doing, the more immediate concerns of people such as water, sanitation, and access to education and land will also be addressed. A strategic plan has been developed, expenditure priorities are being realigned, and grass-roots operations are being honed for improved service delivery and a quality integrated approach. Women's involvement in the new integrated approach will help address constraints to family planning practice. Continuing and extended integrated project service delivery mechanisms and programs are needed to maximize program coverage in Zambia. More staff will have to be trained and local volunteers identified.

  7. Integrity and the Value of an Integrated Self

    NARCIS (Netherlands)

    Archer, Alfred

    What is integrity and why is it valuable? One account of the nature of integrity, proposed by John Cottingham (2010) amongst others, is The Integrated Self View. On this account integrity is a formal relation of coherence between various aspects of a person. One problem that has been raised against

  8. Feynman’s path integral seen as a Henstock integral

    Science.gov (United States)

    Guadalupe Morales, M.; Gaitán, Ricardo

    2017-10-01

    The motivation of this paper is to give mathematical formalism to the Feynman path integral using the Henstock integral. This integral saves some of Feynman’s integral difficulties and justifies Feynman’s intuition: to interpret the state function as “a sum of complex contributions, one from each path in the region”.

  9. Policy, Sport and Integration

    DEFF Research Database (Denmark)

    Agergaard, Sine; Sørensen, Jan Kahr

    2010-01-01

    Increased public funding, more governmental involvement and an emphasis on the instrumental values of physical activities have in general become characteristic of Western nations’ policies towards sport. Denmark is, however, a little different in that there is still little political intervention...... in sport, although sports clubs do get economic support and are seen as having the potential to solve crucial social issues. The purpose of this article is to analyse and discuss the ways in which the political assumption that sport can enhance social integration is reflected in the practical governance...... of integration issues in particular in sports clubs. The article is based on a local field study in which we interviewed 10 talented football players with ethnic minority backgrounds and eight coaches and club leaders from six different football clubs. Distinguishing between integration and assimilation...

  10. INTEGRATED CORPORATE STRATEGY MODEL

    Directory of Open Access Journals (Sweden)

    CATALINA SORIANA SITNIKOV

    2014-02-01

    Full Text Available Corporations are at present operating in demanding and highly unsure periods, facing a mixture of increased macroeconomic need, competitive and capital market dangers, and in many cases, the prospect for significant technical and regulative gap. Throughout these demanding and highly unsure times, the corporations must pay particular attention to corporate strategy. In present times, corporate strategy must be perceived and used as a function of various fields, covers, and characters as well as a highly interactive system. For the corporation's strategy to become a competitive advantage is necessary to understand and also to integrate it in a holistic model to ensure sustainable progress of corporation activities under the optimum conditions of profitability. The model proposed in this paper is aimed at integrating the two strategic models, Hoshin Kanri and Integrated Strategy Model, as well as their consolidation with the principles of sound corporate governance set out by the OECD.

  11. INTEGRAL core programme

    Science.gov (United States)

    Gehrels, N.; Schoenfelder, V.; Ubertini, P.; Winkler, C.

    1997-01-01

    The International Gamma Ray Astrophysics Laboratory (INTEGRAL) mission is described with emphasis on the INTEGRAL core program. The progress made in the planning activities for the core program is reported on. The INTEGRAL mission has a nominal lifetime of two years with a five year extension option. The observing time will be divided between the core program (between 30 and 35 percent during the first two years) and general observations. The core program consists of three main elements: the deep survey of the Galactic plane in the central radian of the Galaxy; frequent scans of the Galactic plane in the search for transient sources, and pointed observations of several selected sources. The allocation of the observation time is detailed and the sensitivities of the observations are outlined.

  12. New integrable lattice hierarchies

    Energy Technology Data Exchange (ETDEWEB)

    Pickering, Andrew [Area de Matematica Aplicada, ESCET, Universidad Rey Juan Carlos, c/ Tulipan s/n, 28933 Mostoles, Madrid (Spain); Zhu Zuonong [Departamento de Matematicas, Universidad de Salamanca, Plaza de la Merced 1, 37008 Salamanca (Spain) and Department of Mathematics, Shanghai Jiao Tong University, Shanghai 200030 (China)]. E-mail: znzhu2@yahoo.com.cn

    2006-01-23

    In this Letter we give a new integrable four-field lattice hierarchy, associated to a new discrete spectral problem. We obtain our hierarchy as the compatibility condition of this spectral problem and an associated equation, constructed herein, for the time-evolution of eigenfunctions. We consider reductions of our hierarchy, which also of course admit discrete zero curvature representations, in detail. We find that our hierarchy includes many well-known integrable hierarchies as special cases, including the Toda lattice hierarchy, the modified Toda lattice hierarchy, the relativistic Toda lattice hierarchy, and the Volterra lattice hierarchy. We also obtain here a new integrable two-field lattice hierarchy, to which we give the name of Suris lattice hierarchy, since the first equation of this hierarchy has previously been given by Suris. The Hamiltonian structure of the Suris lattice hierarchy is obtained by means of a trace identity formula.

  13. Integration eller Illusion

    DEFF Research Database (Denmark)

    Rezaei, Shahamak; Goli, Marco

    2012-01-01

    Integration or illusion – a deviance perspective Denmark experienced one of its most successful periods of economic growth in 2004–2008 with a tremendous reduction of unemployment, which in June 2008 was around. 1.5 percent, far below the expected level of structural unemployment. In the wake...... of migrants’ skills. 2. Whether there were patterns of over-education as expression of institutional and societal discrimination. The focus of the present study is, however, quite different: We examine the pattern of deviance in relation to labour market participation (not integration), and instead...... of searching for explanations for the lack of integration, we attempt to identify and explain the deviance pattern as a product of institutionally inherent possibilities and barriers on the one hand and articulating immigrants as rational actors (not victims) on the other. We argue that deviance is not only...

  14. In times of Integration

    DEFF Research Database (Denmark)

    Val, Maria Rosa Rovira; Lehmann, Martin; Zinenko, Anna

    dramatically with many of the world’s economies facing downturn and a looming possible recession; and the global economic and political balance changing; (ii) most larger companies and quite a few SMEs now have a mature knowledge of these standards; and (iii) some standards are advocating for integration......-a-vis the public sectors. Internationally, organisations have implemented a collection of these standards to be in line with such development and to obtain or keep their licence to operate globally. After two decades of development and maturation, the scenario is now different: (i) the economic context has changed...... procedures, such as cases of for example ISO integrated management systems, mutual equivalences recognition of Global Compact-GRI-ISO26000, or the case of IIRC initiative to develop integrated reporting on an organization’s Financial, Environmental, Social and Governance performance. This paper focuses...

  15. An integrated magnetics component

    DEFF Research Database (Denmark)

    2013-01-01

    The present invention relates to an integrated magnetics component comprising a magnetically permeable core comprising a base member extending in a horizontal plane and first, second, third and fourth legs protruding substantially perpendicularly from the base member. First, second, third...... and fourth output inductor windings are wound around the first, second, third and fourth legs, respectively. A first input conductor of the integrated magnetics component has a first conductor axis and extends in-between the first, second, third and fourth legs to induce a first magnetic flux through a first...... flux path of the magnetically permeable core. A second input conductor of the integrated magnetics component has a second coil axis extending substantially perpendicularly to the first conductor axis to induce a second magnetic flux through a second flux path of the magnetically permeable core...

  16. Signal integrity characterization techniques

    CERN Document Server

    Bogatin, Eric

    2009-01-01

    "Signal Integrity Characterization Techniques" addresses the gap between traditional digital and microwave curricula all while focusing on a practical and intuitive understanding of signal integrity effects within the data transmission channel. High-speed interconnects such as connectors, PCBs, cables, IC packages, and backplanes are critical elements of differential channels that must be designed using today's most powerful analysis and characterization tools.Both measurements and simulation must be done on the device under test, and both activities must yield data that correlates with each other. Most of this book focuses on real-world applications of signal integrity measurements - from backplane for design challenges to error correction techniques to jitter measurement technologies. The authors' approach wisely addresses some of these new high-speed technologies, and it also provides valuable insight into its future direction and will teach the reader valuable lessons on the industry.

  17. Integrated magnetic transformer assembly

    DEFF Research Database (Denmark)

    2014-01-01

    The present invention relates to an integrated magnetics transformer assembly comprising a first magnetically permeable core forming a first substantially closed magnetic flux path and a second magnetically permeable core forming a second substantially closed magnetic flux path. A first input...... inductor winding is wound around a first predetermined segment of the first magnetically permeable core and a second input inductor winding is wound around a first predetermined segment of the second magnetically permeable core. The integrated magnetics transformer assembly further comprises a first output......-winding of the first output inductor winding and the first half-winding of the second output inductor winding are configured to produce aligned, i.e. in the same direction, magnetic fluxes through the first substantially closed magnetic flux path. The integrated magnetics transformer assembly is well- suited for use...

  18. Reflections on 'autistic integrity'.

    Science.gov (United States)

    Russell, Barbara

    2012-03-01

    Autism, particularly its moderate to severe forms, has prompted considerable scientific study and clinical involvement because the associated behaviours imply disconnections with valued features of a 'good' life, such as close relationships, enjoyment, and adaptability. Proposed causes of autism involve potent philosophical concepts including consciousness, identity, mind, and relationality. The concept of autistic integrity is used by Barnbaum in The Ethics of Autism: Among Them, But Not of Them to help provide moral justification to stop efforts to cure adults with autism, especially if the cause is presumed to be a lack of a theory of mind.(1) This article has two goals: (1) to apply four familiar definitions or characterizations of integrity to the case of moderate to severe autism, and (2) to examine whether autistic integrity does provide the moral justification Barnbaum seeks. © 2010 Blackwell Publishing Ltd.

  19. Integrality in codimension one

    DEFF Research Database (Denmark)

    Thorup, Anders

    2014-01-01

    The paper from 2001 by Simis, Ulrich, and Vasconcelos contained deep results on codimension, multiplicity and integral extensions. The results and the ideas of the paper led to substantial simplifications in the treatment of the exceptional fiber of a conormal space, considered previously...... by Kleiman and the present author. In addition, the paper contained the following theorem: Let R ⊆ S be an extension of commutative rings, where R is noetherian, universally catenary, and locally equidimensional. Then the extension R ⊆ S is integral if minimal primes of S contract to minimal primes of R and......, for every prime p of height at most 1 in R, the extension Rp ⊆ Sp is integral. Themain purpose of the present note is to give an alternative proof of the theorem, based on standard techniques of projective geometry. In addition, the results on the exceptional fiber, considered previously by Kleiman...

  20. Semantic Observation Integration

    Directory of Open Access Journals (Sweden)

    Werner Kuhn

    2012-09-01

    Full Text Available Although the integration of sensor-based information into analysis and decision making has been a research topic for many years, semantic interoperability has not yet been reached. The advent of user-generated content for the geospatial domain, Volunteered Geographic Information (VGI, makes it even more difficult to establish semantic integration. This paper proposes a novel approach to integrating conventional sensor information and VGI, which is exploited in the context of detecting forest fires. In contrast to common logic-based semantic descriptions, we present a formal system using algebraic specifications to unambiguously describe the processing steps from natural phenomena to value-added information. A generic ontology of observations is extended and profiled for forest fire detection in order to illustrate how the sensing process, and transformations between heterogeneous sensing systems, can be represented as mathematical functions and grouped into abstract data types. We discuss the required ontological commitments and a possible generalization.