WorldWideScience

Sample records for test circuit fsp-ptc

  1. Load testing circuit

    DEFF Research Database (Denmark)

    2009-01-01

    A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...

  2. Short- circuit tests of circuit breakers

    OpenAIRE

    Chorovský, P.

    2015-01-01

    This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.

  3. The test of VLSI circuits

    Science.gov (United States)

    Baviere, Ph.

    Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

  4. Digital logic circuit test

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Gil Jung; Yang, Hong Young

    2011-03-15

    This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

  5. Instrumentation and test gear circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Instrumentation and Test Gear Circuits Manual provides diagrams, graphs, tables, and discussions of several types of practical circuits. The practical circuits covered in this book include attenuators, bridges, scope trace doublers, timebases, and digital frequency meters. Chapter 1 discusses the basic instrumentation and test gear principles. Chapter 2 deals with the design of passive attenuators, and Chapter 3 with passive and active filter circuits. The subsequent chapters tackle 'bridge' circuits, analogue and digital metering techniques and circuitry, signal and waveform generation, and p

  6. The testing of generator circuit-breakers

    NARCIS (Netherlands)

    Smeets, R.P.P.; Linden, van der W.A.

    1998-01-01

    Generator circuit-breakers face much higher current and voltage stress than distribution switchgear. This has led to a special standard (ANSI C37.013). Strictly in accordance with this standard's requirements, test circuits and parameters for a 100 kA and 120 kA (25.3 kV) SF6 generator

  7. 30 CFR 56.6407 - Circuit testing.

    Science.gov (United States)

    2010-07-01

    ... series or the resistance of multiple balanced series to be connected in parallel prior to their... detonator series. (d) Total blasting circuit resistance prior to connection to the power source. Nonelectric... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit testing. 56.6407 Section 56.6407...

  8. Test-circuits for HVDC thyristor valves

    NARCIS (Netherlands)

    Thiele, G.; Alarovandi, G.; Bonfanti, I.; Cepek, M.; Dumrese, H.G.; Damstra, G.C.

    1997-01-01

    In conformity with the usual classification of the specified tests into two major categories, dielectric tests and operational tests, the report is in two parts : Part 1 - Dielectric tests which deals principally with test circuits for verifying the high voltage characteristics of the valve, and

  9. Design and Test of Advanced Thermal Simulators for an Alkali Metal-Cooled Reactor Simulator

    Science.gov (United States)

    Garber, Anne E.; Dickens, Ricky E.

    2011-01-01

    The Early Flight Fission Test Facility (EFF-TF) at NASA Marshall Space Flight Center (MSFC) has as one of its primary missions the development and testing of fission reactor simulators for space applications. A key component in these simulated reactors is the thermal simulator, designed to closely mimic the form and function of a nuclear fuel pin using electric heating. Continuing effort has been made to design simple, robust, inexpensive thermal simulators that closely match the steady-state and transient performance of a nuclear fuel pin. A series of these simulators have been designed, developed, fabricated and tested individually and in a number of simulated reactor systems at the EFF-TF. The purpose of the thermal simulators developed under the Fission Surface Power (FSP) task is to ensure that non-nuclear testing can be performed at sufficiently high fidelity to allow a cost-effective qualification and acceptance strategy to be used. Prototype thermal simulator design is founded on the baseline Fission Surface Power reactor design. Recent efforts have been focused on the design, fabrication and test of a prototype thermal simulator appropriate for use in the Technology Demonstration Unit (TDU). While designing the thermal simulators described in this paper, effort were made to improve the axial power profile matching of the thermal simulators. Simultaneously, a search was conducted for graphite materials with higher resistivities than had been employed in the past. The combination of these two efforts resulted in the creation of thermal simulators with power capacities of 2300-3300 W per unit. Six of these elements were installed in a simulated core and tested in the alkali metal-cooled Fission Surface Power Primary Test Circuit (FSP-PTC) at a variety of liquid metal flow rates and temperatures. This paper documents the design of the thermal simulators, test program, and test results.

  10. LS1 Report: short-circuit tests

    CERN Multimedia

    Katarina Anthony

    2014-01-01

    As the LS1 draws to an end, teams move from installation projects to a phase of intense testing. Among these are the so-called 'short-circuit tests'. Currently under way at Point 7, these tests verify the cables, the interlocks, the energy extraction systems, the power converters that provide current to the superconducting magnets and the cooling system.   Thermal camera images taken during tests at point 4 (IP4). Before putting beam into the LHC, all of the machine's hardware components need to be put to the test. Out of these, the most complicated are the superconducting circuits, which have a myriad of different failure modes with interlock and control systems. While these will be tested at cold - during powering tests to be done in August - work can still be done beforehand. "While the circuits in the magnets themselves cannot be tested at warm, what we can do is verify the power converter and the circuits right up to the place the cables go into the magn...

  11. Testing Superconductor Logic Integrated Circuits

    NARCIS (Netherlands)

    Arun, A.J.; Kerkhoff, Hans G.

    2005-01-01

    Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these

  12. Minimizing time for test in integrated circuit

    OpenAIRE

    Andonova, A. S.; Dimitrov, D. G.; Atanasova, N. G.

    2004-01-01

    The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimisation algorithm. A prototype of the proposed approach was tested on 1SCAS standard benchmarks and theexperimental results s...

  13. Test Structures For Bumpy Integrated Circuits

    Science.gov (United States)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  14. Test signal generation for analog circuits

    Directory of Open Access Journals (Sweden)

    B. Burdiek

    2003-01-01

    Full Text Available In this paper a new test signal generation approach for general analog circuits based on the variational calculus and modern control theory methods is presented. The computed transient test signals also called test stimuli are optimal with respect to the detection of a given fault set by means of a predefined merit functional representing a fault detection criterion. The test signal generation problem of finding optimal test stimuli detecting all faults form the fault set is formulated as an optimal control problem. The solution of the optimal control problem representing the test stimuli is computed using an optimization procedure. The optimization procedure is based on the necessary conditions for optimality like the maximum principle of Pontryagin and adjoint circuit equations.

  15. Testing Fixture For Microwave Integrated Circuits

    Science.gov (United States)

    Romanofsky, Robert; Shalkhauser, Kurt

    1989-01-01

    Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

  16. LHC Report: superconducting circuit powering tests

    CERN Multimedia

    Mirko Pojer

    2015-01-01

    After the long maintenance and consolidation campaign carried out during LS1, the machine is getting ready to start operation with beam at 6.5 TeV… the physics community can’t wait! Prior to this, all hardware and software systems have to be tested to assess their correct and safe operation.   Most of the cold circuits (those with high current/stored energy) possess a sophisticated magnet protection system that is crucial to detect a transition of the coil from the superconducting to the normal state (a quench) and safely extract the energy stored in the circuits (about 1 GJ per dipole circuit at nominal current). LHC operation relies on 1232 superconducting dipoles with a field of up to 8.33 T operating in superfluid helium at 1.9 K, along with more than 500 superconducting quadrupoles operating at 4.2 or 1.9 K. Besides, many other superconducting and normal resistive magnets are used to guarantee the possibility of correcting all beam parameters, for a total of mo...

  17. FPGA based mixed-signal circuit novel testing techniques

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

    2013-01-01

    Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

  18. Optimal planning of series resistor to control time constant of test circuit for high-voltage AC circuit-breakers

    OpenAIRE

    Yoon-Ho Kim; Jung-Hyeon Ryu; Jin-Hwan Kim; Kern-Joong Kim

    2016-01-01

    The equivalent test circuit that can deliver both short-circuit current and recovery voltage is used to verify the performance of high-voltage circuit breakers. Most of the parameters in this circuit can be obtained by using a simple calculation or a simulation program. The ratings of the circuit breaker include rated short-circuit breaking current, rated short-circuit making current, rated operating sequence of the circuit breaker and rated short-time current. Among these ratings, the short-...

  19. Design, Analysis and Test of Logic Circuits Under Uncertainty

    CERN Document Server

    Krishnaswamy, Smita; Hayes, John P

    2013-01-01

    Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...

  20. Test and Diagnosis of Integrated Circuits

    OpenAIRE

    Bosio , Alberto

    2015-01-01

    The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

  1. Calorimeter Preamplifier Hybrid Circuit Test Jig

    International Nuclear Information System (INIS)

    Abraham, B.M.

    1999-01-01

    There are two ways in which the testing may be initiated, remotely or locally. If the remote operation is desired, an external TTL level signal must be provided to the test jig with the remotellocal switch on the side of the test jig switched to remote. A logic high will initiate the test. A logic low will terminate the test. In the event that an external signal is connected to the test jig while local operation occurs, the local control takes precedence over remote control. Once a DVT has been locked in the ZIF socket and the DIP switches are selected, the Push-to-Test button may be depressed. Momentarily depressing the button will initiate a test with a minimum 400 ms duration. At the same time a PBCLOCK and PBLATCH pulses will be initiated and the power rails +12V, +8V, and -6V will be ramped to full voltage. The time at which the power rails reach the full voltage is about 13 ms and it is synchronized with bypass capacitors placed on COMP input of U20 and U22 and on the output of U23 voltage regulators. The voltage rails are supplied to a ±10% window comparator. A red LED indicates the rail is below or above 10% of the design value. A green LED indicates the rail is within acceptable limits. For DDT with a 5 pF and 10 pF feed back capacitor, the +12V and +8V rails are current-regulated to 19rnA and 22 rnA respectively and the -6V rail is short-circuit protected within the regulator. For DUT with a 22 pF feed back capacitor the current regulation is the same as above except that the +8V rail is current regulated to 43 rnA. The power rails are supplied to the DUT via a 10 (Omega) resistor. The voltage drop across this resistor is sensed by a differential amplifier AD620 and amplified by a gain of 10. An external BNC connection is provided from this point to allow for current measurements by the vendor. The current value for each rail is calculated by measuring the voltage value at this point and divided by (10*10(Omega)). The next stage inverts and amplifies the

  2. Calorimeter Preamplifier Hybrid Circuit Test Jig

    Energy Technology Data Exchange (ETDEWEB)

    Abraham, B.M.; /Fermilab

    1999-04-19

    There are two ways in which the testing may be initiated, remotely or locally. If the remote operation is desired, an external TTL level signal must be provided to the test jig with the remotellocal switch on the side of the test jig switched to remote. A logic high will initiate the test. A logic low will terminate the test. In the event that an external signal is connected to the test jig while local operation occurs, the local control takes precedence over remote control. Once a DVT has been locked in the ZIF socket and the DIP switches are selected, the Push-to-Test button may be depressed. Momentarily depressing the button will initiate a test with a minimum 400 ms duration. At the same time a PBCLOCK and PBLATCH pulses will be initiated and the power rails +12V, +8V, and -6V will be ramped to full voltage. The time at which the power rails reach the full voltage is about 13 ms and it is synchronized with bypass capacitors placed on COMP input of U20 and U22 and on the output of U23 voltage regulators. The voltage rails are supplied to a {+-}10% window comparator. A red LED indicates the rail is below or above 10% of the design value. A green LED indicates the rail is within acceptable limits. For DDT with a 5 pF and 10 pF feed back capacitor, the +12V and +8V rails are current-regulated to 19rnA and 22 rnA respectively and the -6V rail is short-circuit protected within the regulator. For DUT with a 22 pF feed back capacitor the current regulation is the same as above except that the +8V rail is current regulated to 43 rnA. The power rails are supplied to the DUT via a 10 {Omega} resistor. The voltage drop across this resistor is sensed by a differential amplifier AD620 and amplified by a gain of 10. An external BNC connection is provided from this point to allow for current measurements by the vendor. The current value for each rail is calculated by measuring the voltage value at this point and divided by (10*10{Omega}). The next stage inverts and amplifies

  3. 30 CFR 57.6407 - Circuit testing.

    Science.gov (United States)

    2010-07-01

    ...) Continuity of each electric detonator in the blasthole prior to stemming and connection to the blasting line... connection of electric detonator series; and (4) Total blasting circuit resistance prior to connection to the...) Continuity of blasting lines prior to the connection of electric detonators. Nonelectric Blasting—Surface and...

  4. Electrical short circuit and current overload tests on aircraft wiring

    Science.gov (United States)

    Cahill, Patricia

    1995-01-01

    The findings of electrical short circuit and current overload tests performed on commercial aircraft wiring are presented. A series of bench-scale tests were conducted to evaluate circuit breaker response to overcurrent and to determine if the wire showed any visible signs of thermal degradation due to overcurrent. Three types of wire used in commercial aircraft were evaluated: MIL-W-22759/34 (150 C rated), MIL-W-81381/12 (200 C rated), and BMS 1360 (260 C rated). A second series of tests evaluated circuit breaker response to short circuits and ticking faults. These tests were also meant to determine if the three test wires behaved differently under these conditions and if a short circuit or ticking fault could start a fire. It is concluded that circuit breakers provided reliable overcurrent protection. Circuit breakers may not protect wire from ticking faults but can protect wire from direct shorts. These tests indicated that the appearance of a wire subjected to a current that totally degrades the insulation looks identical to a wire subjected to a fire; however the 'fire exposed' conductor was more brittle than the conductor degraded by overcurrent. Preliminary testing indicates that direct short circuits are not likely to start a fire. Preliminary testing indicated that direct short circuits do not erode insulation and conductor to the extent that ticking faults did. Circuit breakers may not safeguard against the ignition of flammable materials by ticking faults. The flammability of materials near ticking faults is far more important than the rating of the wire insulation material.

  5. Economic testing of large integrated switching circuits - a challenge to the test engineer

    International Nuclear Information System (INIS)

    Kreinberg, W.

    1978-01-01

    With reference to large integrated switching circuits, one can use an incoming standard programme test or the customer's switching circuits. The author describes the development of suitable, extensive and economical test programmes. (orig.) [de

  6. Addressable-Matrix Integrated-Circuit Test Structure

    Science.gov (United States)

    Sayah, Hoshyar R.; Buehler, Martin G.

    1991-01-01

    Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

  7. Oscillation-based test in mixed-signal circuits

    CERN Document Server

    Sánchez, Gloria Huertas; Rueda, Adoración Rueda

    2007-01-01

    This book presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short. The results presented here assert, not only from a theoretical point of view, but also based on a wide experimental support, that OBT is an efficient defect-oriented test solution, complementing the existing functional test techniques for mixed-signal circuits.

  8. Elements configuration of the open lead test circuit

    Energy Technology Data Exchange (ETDEWEB)

    Fukuzaki, Yumi, E-mail: 14514@sr.kagawa-nct.ac.jp [Advanced course of Electronics, Information and Communication Engineering, National Institute of Technology, Kagawa College, 551 Koda, Mitoyo, Kagawa (Japan); Ono, Akira [Department of Communication Network Engineering, National Institute of Technology, Kagawa College, 551 Koda, Mitoyo, Kagawa (Japan)

    2016-07-06

    In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a test circuit in the past. This paper propose elements configuration of the test circuit.

  9. Elements configuration of the open lead test circuit

    International Nuclear Information System (INIS)

    Fukuzaki, Yumi; Ono, Akira

    2016-01-01

    In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a test circuit in the past. This paper propose elements configuration of the test circuit.

  10. Short Circuit Tests First Step of LHC Hardware Commissioning Completion

    CERN Document Server

    Barbero-Soto, E; Bordry, Frederick; Casas Lino, M P; Coelingh, G J; Cumer, G; Dahlerup-Petersen, K; Guillaume, J C; Inigo-Golfin, J; Montabonnet, V; Nisbet, D; Pojer, M; Principe, R; Rodríguez-Mateos, F; Saban, R; Schmidt, R; Thiesen, H; Vergara-Fernández, A; Zerlauth, M; Castaneda Serra, A; Romera Ramirez, I

    2008-01-01

    For the two counter rotating beams in the Large Hadron Collider (LHC) about 8000 magnets (main dipole and quadrupole magnets, corrector magnets, separation dipoles, matching section quadrupoles etc.) are powered in about 1500 superconducting electrical circuits. The magnets are powered by power converters that have been designed for the LHC with a current between 60 and 13000A. Between October 2005 and September 2007 the so-called Short Circuit Tests were carried-out in 15 underground zones where the power converters of the superconducting circuits are placed. The tests aimed to qualify the normal conducting equipments of the circuits such as power converters and normal conducting high current cables. The correct operation of interlock and energy extraction systems was validated. The infrastructure systems including AC distribution, water and air cooling and the control systems was also commissioned. In this paper the results of the two year test campaign are summarized with particular attention to problems e...

  11. Optimization of the powering tests of the LHC superconducting circuits

    CERN Document Server

    Bellesia, B; Denz, R; Fernandez-Robles, C; Pojer, M; Saban, R; Schmidt, R; Solfaroli Camillocci, M; Thiesen, H; Vergara Fernández, A

    2010-01-01

    The Large Hadron Collider has (LHC) 1572 superconducting circuits which are distributed along the eight 3.5 km LHC sectors [1]. Time and resources during the commissioning of the LHC technical systems were mostly consumed by the powering tests of each circuit. The tests consisted in carrying out several powering cycles at different current levels for each superconducting circuit. The Hardware Commissioning Coordination was in charge of planning, following up and piloting the execution of the test program. The first powering test campaign was carried out in summer 2007 for sector 7-8 with an expected duration of 12 weeks. The experience gained during these tests was used by the commissioning team for minimising the duration of the following powering campaigns to comply with the stringent LHC project deadlines. Improvements concerned several areas: strategy, procedures, control tools, automatization, and resource allocation led to an average daily test rate increase from 25 to 200 tests per day. This paper desc...

  12. RF Testing Of Microwave Integrated Circuits

    Science.gov (United States)

    Romanofsky, R. R.; Ponchak, G. E.; Shalkhauser, K. A.; Bhasin, K. B.

    1988-01-01

    Fixtures and techniques are undergoing development. Four test fixtures and two advanced techniques developed in continuing efforts to improve RF characterization of MMIC's. Finline/waveguide test fixture developed to test submodules of 30-GHz monolithic receiver. Universal commercially-manufactured coaxial test fixture modified to enable characterization of various microwave solid-state devices in frequency range of 26.5 to 40 GHz. Probe/waveguide fixture is compact, simple, and designed for non destructive testing of large number of MMIC's. Nondestructive-testing fixture includes cosine-tapered ridge, to match impedance wavequide to microstrip. Advanced technique is microwave-wafer probing. Second advanced technique is electro-optical sampling.

  13. A Low Speed BIST Framework for High Speed Circuit Testing

    NARCIS (Netherlands)

    Speek, H.; Kerkhoff, Hans G.; Shashaani, M.; Sachdev, M.

    2000-01-01

    Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high

  14. Automated Testing System for a CAN Communication Circuit

    Directory of Open Access Journals (Sweden)

    PRUTIANU, F.

    2012-05-01

    Full Text Available The paper presents a method for validation/testing a control area network (CAN communication circuit used in all electronic control units (ECUs developed in automotive industry after 2000. Using a specific hardware configuration and remotely controlled by LabVIEW. The author's presents their own vision regarding operational software algorithm implementation and integration / execution of some test cases in order to validate a CAN circuit. Using this method, it is possible to validate/test CAN hardware circuits in a short time and with the possibility of saving the test results. Human operator is interfering with the system only through the graphical user interface. The error sources for this system are reduced to minimum.

  15. Secondary coolant circuit operation tests: steam generator feedwater supply

    International Nuclear Information System (INIS)

    Beroux, M.

    1985-01-01

    No one important accident occurred during the start-up tests of the 1300MWe P4 series, concerning the feedwater system of steam generators (SG). This communication comments on some incidents, that the tests allowed to detect very soon and which had no consequences on the operation of units: 1) Water hammer in feedwater tubes, and incidents met in the emergency steam generator water supply circuit. The technological differences between SG 900 and 1300 are pointed out, and the measures taken to prevent this problem are presented. 2) Incidents met on the emergency feedwater supply circuit of steam generators; mechanical or functional modifications involved by these incidents [fr

  16. RF and microwave integrated circuit development technology, packaging and testing

    CERN Document Server

    Gamand, Patrice; Kelma, Christophe

    2018-01-01

    RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

  17. Test generation for digital circuits using parallel processing

    Science.gov (United States)

    Hartmann, Carlos R.; Ali, Akhtar-Uz-Zaman M.

    1990-12-01

    The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

  18. Digital circuit testing a guide to DFT and other techniques

    CERN Document Server

    Wong, Francis C

    1991-01-01

    Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to

  19. Laser system for testing radiation imaging detector circuits

    Science.gov (United States)

    Zubrzycka, Weronika; Kasinski, Krzysztof

    2015-09-01

    Performance and functionality of radiation imaging detector circuits in charge and position measurement systems need to meet tight requirements. It is therefore necessary to thoroughly test sensors as well as read-out electronics. The major disadvantages of using radioactive sources or particle beams for testing are high financial expenses and limited accessibility. As an alternative short pulses of well-focused laser beam are often used for preliminary tests. There are number of laser-based devices available on the market, but very often their applicability in this field is limited. This paper describes concept, design and validation of laser system for testing silicon sensor based radiation imaging detector circuits. The emphasis is put on keeping overall costs low while achieving all required goals: mobility, flexible parameters, remote control and possibility of carrying out automated tests. The main part of the developed device is an optical pick-up unit (OPU) used in optical disc drives. The hardware includes FPGA-controlled circuits for laser positioning in 2 dimensions (horizontal and vertical), precision timing (frequency and number) and amplitude (diode current) of short ns-scale (3.2 ns) light pulses. The system is controlled via USB interface by a dedicated LabVIEW-based application enabling full manual or semi-automated test procedures.

  20. Highly focused ion beams in integrated circuit testing

    International Nuclear Information System (INIS)

    Horn, K.M.; Dodd, P.E.; Doyle, B.L.

    1996-01-01

    The nuclear microprobe has proven to be a useful tool in radiation testing of integrated circuits. This paper reviews single event upset (SEU) and ion beam induced charge collection (IBICC) imaging techniques, with special attention to damage-dependent effects. Comparisons of IBICC measurements with three-dimensional charge transport simulations of charge collection are then presented for isolated p-channel field effect transistors under conducting and non-conducting bias conditions

  1. Device for testing continuity and/or short circuits in a cable

    Science.gov (United States)

    Hayhurst, Arthur R. (Inventor)

    1995-01-01

    A device for testing current paths is attachable to a conductor. The device automatically checks the current paths of the conductor for continuity of a center conductor, continuity of a shield and a short circuit between the shield and the center conductor. The device includes a pair of connectors and a circuit to provide for testing of the conductive paths of the cable. The pair of connectors electrically connects the conductive paths of a cable to be tested with the circuit paths of the circuit. The circuit paths in the circuit include indicators to simultaneously indicate the results of the testing.

  2. Apparatus and method for defect testing of integrated circuits

    Science.gov (United States)

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  3. Sodium corrosion tests in the ML 1 circuit

    International Nuclear Information System (INIS)

    Borgstedt, H.U.

    1977-01-01

    In the ML-1 circuit of the 'Juan Vigon' research centre in Madrid, sodium corrosion tests are being carried out on the austenitic steels DIN 1.4970 (X10NiCrMoTiB1515) and DIN 1.4301 (X5CrNi189) at temperatures between 500 and 700 0 C. The exposure time of the samples amounts to 6,000 h by now. Every 1,000 h, the samples were weighed in order to measure corrosion and deposition effects. After 3,000 and 6,000 h, some selected samples were destroyed for inspection. The results are given. (GSC) [de

  4. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  5. Heavy ions testing experimental results on programmable integrated circuits

    International Nuclear Information System (INIS)

    Velazco, R.; Provost-Grellier, A.

    1988-01-01

    The natural radiation environment in space has been shown to produce anomalies in satellite-borne microelectronics. It becomes then mandatory to define qualification strategies allowing to choose the less vulnerable circuits. In this paper, is presented a strategy devoted to one of the most critical effects, the soft errors (so called upset). The method addresses programmable integrated circuits i.e. circuits able to execute an instruction or command set. Experimental results on representative circuits will illustrate the approach. 11 refs [fr

  6. Design and testing of integrated circuits for reactor protection channels

    International Nuclear Information System (INIS)

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

    1995-01-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing

  7. Design and testing of integrated circuits for reactor protection channels

    International Nuclear Information System (INIS)

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

    1995-01-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built

  8. Modeling a verification test system for mixed-signal circuits

    NARCIS (Netherlands)

    San Segundo Bello, D.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.

    In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block

  9. Life testing of a low voltage air circuit breaker

    International Nuclear Information System (INIS)

    Subudhi, M.

    1991-01-01

    ADS-416 low voltage air circuit breaker manufacture by Westinghouse was mechanically cycled to identify age-related degradation in various breaker subcomponents, in particular, the power-operating mechanism. This accelerated aging test was performed on one breaker unit for over 36,000 cycles. Three separate pole shafts, one with a 60 degree weld, one with a 120 degree weld and one with a 180 degree weld in the third pole lever were used to characterize the cracking in these welds. In addition, during the testing, three different operating mechanisms and several other parts were replaced as they degraded to an inoperable condition. Of the seven welds on the pole shaft, two were found to be the critical ones whose fracture can result in misalignment problems of the pole levers. These failures, in turn can lead to many other problems with the operating mechanism including the burn-out of coils, excessive wear in certain parts and over-stressed linkages. Furthermore, the limiting service life of a number of subcomponents of the power-operated mechanism, including the operating mechanism itself, were assessed. 1 ref., 3 figs

  10. Life testing of a low voltage air circuit breaker

    International Nuclear Information System (INIS)

    Subudhi, M.; Aggarwal, S.

    1992-01-01

    A DS-416 low voltage air circuit breaker manufactured by Westinghouse was mechanically cycled to identify age-related degradation in the various breaker subcomponents, specifically the power-operated mechanism. This accelerated aging test was performed on one breaker unit for over 36,000 cycles. Three separate pole shafts, one with a 60-degree weld, one with a 120-degree weld, and one with a 180-degree weld in the third pole lever were used to characterize cracking in the welds. In addition, during the testing three different operating mechanisms and several other parts were replaced as they became inoperable. Among the seven welds on the pole shaft, number-sign 1 and number-sign 3 were found to be critical ones whose fracture can result in misalignment of the pole levers. This can lead to problems with the operating mechanism, including the burning of coils, excessive wear in certain parts, and overstressed linkages. Furthermore, the limiting service life of a number of subcomponents of the power-operated mechanism, including the operating mechanism itself, were assessed. Based on these findings, suggestions are provided to alleviate the age-related degradation that could occur as a result of normal closing and opening of the breaker contacts during its service life. Also, cause and effect analyses of various age-related degradation in various breaker parts are discussed

  11. Testing methods of gaseous admixtures in HLMC circuits

    International Nuclear Information System (INIS)

    Shelemet'ev, V.M.; Martynov, P.N.; Askhadullin, R.Sh.; Storozhenko, A.N.; Sadovnichij, R.P.; Ivanov, I.I.

    2014-01-01

    Control of gas phase is the effective method for state diagnostics of circuit of nuclear power facilities with heavy liquid metal coolants. Use of developing in IPPE solid electrolyte and conductometric oxygen and hydrogen sensors, which are set directly in gas system of the primary circuit, allows to maintain continuously control of oxygen and hydrogen content as well as operational efficiency and accuracy of these parameters determination under various situations related with oxygen and hydrogen insertion into circuit. Sensors ensure long-term safe operation under extreme conditions of high temperatures, pressures, humidity, etc., and are advanced devices for application in nuclear power facilities with heavy liquid metal coolants [ru

  12. Testing and verification of a novel single-channel IGBT driver circuit

    OpenAIRE

    Lukić, Milan; Ninković, Predrag

    2016-01-01

    This paper presents a novel single-channel IGBT driver circuit together with a procedure for testing and verification. It is based on a specialized integrated circuit with complete range of protective functions. Experiments are performed to test and verify its behaviour. Experimental results are presented in the form of oscilloscope recordings. It is concluded that the new driver circuit is compatible with modern IGBT transistors and power converter demands and that it can be applied in new d...

  13. Approaching Repetitive Short Circuit Tests on MW-Scale Power Modules by means of an Automatic Testing Setup

    DEFF Research Database (Denmark)

    Reigosa, Paula Diaz; Wang, Huai; Iannuzzo, Francesco

    2016-01-01

    An automatic testing system to perform repetitive short-circuit tests on megawatt-scale IGBT power modules is pre-sented and described in this paper, pointing out the advantages and features of such testing approach. The developed system is based on a non-destructive short-circuit tester, which has...

  14. Fourteen years of test experience with short-circuit withstand capability of large power transformers

    NARCIS (Netherlands)

    Smeets, R.P.P.; Paske, te L.H.

    2010-01-01

    Experience is reported of short-circuit testing of large power transformers during the past 14 years by KEMA in the Netherlands. In total, 119 transformers > 25 MVA participated in the survey. KEMA shows that at initial access to standard IEC short-circuit tests, 28% failed initially in a wide range

  15. Sixteen years of test experiences with short-circuit withstand capability of large power transformers

    NARCIS (Netherlands)

    Smeets, R.P.P.; Paske, te L.H.

    2012-01-01

    Experience is reported of short-circuit testing of large power transformers during the past 16 years by KEMA in the Netherlands. In total, 174 transformers > 25 MVA participated in the survey. KEMA shows that at initial access to standard IEC short-circuit tests, 24% failed initially in a wide range

  16. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    Science.gov (United States)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  17. Novel technique for reliability testing of silicon integrated circuits

    NARCIS (Netherlands)

    Le Minh, P.; Wallinga, Hans; Woerlee, P.H.; van den Berg, Albert; Holleman, J.

    2001-01-01

    We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon

  18. Testing of SF6- and vacuum generator circuit breakers

    NARCIS (Netherlands)

    Smeets, R.P.P.; Paske, te L.H.

    2011-01-01

    Generator circuit breakers differ in various aspects from standard distribution breakers. One of the main differences is in the electrical stresses during fault current interruption. This situation will be discussed in the present contribution, along with the standardization status and the

  19. Active Match Load Circuit Intended for Testing Piezoelectric Transformers

    DEFF Research Database (Denmark)

    Andersen, Thomas; Rødgaard, Martin Schøler; Andersen, Michael A. E.

    2012-01-01

    An adjustable high voltage active load circuit for voltage amplitudes above 100 volts, especially intended for resistive matching the output impedance of a piezoelectric transformer (PT) is proposed in this paper. PTs have been around for over 50 years, were C. A. Rosen is common known for his...

  20. Thirteen years test experience with short-circuit withstand capability of large power transformers

    NARCIS (Netherlands)

    Smeets, R.P.P.; Paske, te L.H.; Leufkens, P.P.; Fogelberg, T.

    2009-01-01

    The ability to withstand a short circuit is recognised more and more as an essential characteristic of power transformers. IEC and IEEE Standards, as well as other national standards specify short-circuit testing and how to check the withstand capability. Unfortunately, however, there is extensive

  1. Low Pressure Circuit Control and adjust System Test

    International Nuclear Information System (INIS)

    Rubio, R.O; Brendstrup, C.J; Ocampo, A.C

    2000-01-01

    The hydraulic mechanism (MSAC) is a system that will be employed in the movement of the control rods of the CAREM-25 reactor.In this report, the experimental work on a prototype of MSAC in a low pressure circuit is presented: also the methodology and conclusions.Basic thermalhydraulic data from the MSAC was obtained, and the most relevant control parameters were determined.The response of the mechanism to changes in the control parameters was also evaluated. In conclusion, the response of the MSAC fulfills the aspects of reliability and repetitive movement with water flow pulses control, in the low pressure circuit at the Laboratorio de Mecanica, Materiales y Mediciones of INVAP S.E

  2. Integrated circuit test-port architecture and method and apparatus of test-port generation

    Science.gov (United States)

    Teifel, John

    2016-04-12

    A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.

  3. Testing and verification of a novel single-channel IGBT driver circuit

    Directory of Open Access Journals (Sweden)

    Lukić Milan

    2016-01-01

    Full Text Available This paper presents a novel single-channel IGBT driver circuit together with a procedure for testing and verification. It is based on a specialized integrated circuit with complete range of protective functions. Experiments are performed to test and verify its behaviour. Experimental results are presented in the form of oscilloscope recordings. It is concluded that the new driver circuit is compatible with modern IGBT transistors and power converter demands and that it can be applied in new designs. It is a part of new 20kW industrial-grade boost converter.

  4. In situ testing of the Shippingport Atomic Power Station electrical circuits

    International Nuclear Information System (INIS)

    Dinsel, M.R.; Donaldson, M.R.; Soberano, F.T.

    1987-04-01

    This report discusses the results of electrical in situ testing of selected circuits and components at the Shippingport Atomic Power Station in Shippingport, Pennsylvania. Testing was performed by EG and G Idaho in support of the United States Nuclear Regulatory Commission (USNRC) Nuclear Plant Aging Research (NPAR) Program. The goal was to determine the extent of aging or degradation of various circuits from the original plant, and the two major coreplant upgrades (representing three distinct age groups), as well as to evaluate previously developed surveillance technology. The electrical testing was performed using the Electrical Circuit Characterization and Diagnostic (ECCAD) system developed by EG and G for the US Department of Energy to use at TMI-2. Testing included measurements of voltage, effective series capacitance, effective series inductance, impedance, effective series resistance, dc resistance, insulation resistance and time domain reflectometry (TDR) parameters. The circuits evaluated included pressurizer heaters, control rod position indicator cables, miscellaneous primary system Resistance Temperature Detectors (RTDs), nuclear instrumentation cables, and safety injection system motor operated valves. It is to be noted that the operability of these circuits was tested after several years had elapsed because plant operations had concluded at Shippingport. There was no need following plant shutdown to retain the circuits in working condition, so no effort was expended for that purpose. The in situ measurements and analysis of the data confirmed the effectiveness of the ECCAD system for detecting degradation of circuit connections and splices because of high resistance paths, with most of the problems caused by corrosion. Results indicate a correlation between the chronological age of circuits and circuit degradation

  5. A miniature microcontroller curve tracing circuit for space flight testing transistors.

    Science.gov (United States)

    Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

    2015-02-01

    This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

  6. A Discrete Event System Approach to Online Testing of Speed Independent Circuits

    Directory of Open Access Journals (Sweden)

    P. K. Biswal

    2015-01-01

    Full Text Available With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature.

  7. Method of boundary testing of the electric circuits and its application for calculating electric tolerances. [electric equipment tests

    Science.gov (United States)

    Redkina, N. P.

    1974-01-01

    Boundary testing of electric circuits includes preliminary and limiting tests. Preliminary tests permit determination of the critical parameters causing the greatest deviation of the output parameter of the system. The boundary tests offer the possibility of determining the limits of the fitness of the system with simultaneous variation of its critical parameters.

  8. A high frequency test bench for rapid single-flux-quantum circuits

    International Nuclear Information System (INIS)

    Engseth, H; Intiso, S; Rafique, M R; Tolkacheva, E; Kidiyarova-Shevchenko, A

    2006-01-01

    We have designed and experimentally verified a test bench for high frequency testing of rapid single-flux-quantum (RSFQ) circuits. This test bench uses an external tunable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift register. The clock pattern is consequently shifted out at high speed and split to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed read-out electronics. The test bench consists of 158 Josephson junctions and the occupied area is 3300 x 660 μm 2 . It was experimentally verified up to 33 GHz with ± 21.7% margins on the global bias supply current

  9. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  10. Test methods of total dose effects in very large scale integrated circuits

    International Nuclear Information System (INIS)

    He Chaohui; Geng Bin; He Baoping; Yao Yujuan; Li Yonghong; Peng Honglun; Lin Dongsheng; Zhou Hui; Chen Yusheng

    2004-01-01

    A kind of test method of total dose effects (TDE) is presented for very large scale integrated circuits (VLSI). The consumption current of devices is measured while function parameters of devices (or circuits) are measured. Then the relation between data errors and consumption current can be analyzed and mechanism of TDE in VLSI can be proposed. Experimental results of 60 Co γ TDEs are given for SRAMs, EEPROMs, FLASH ROMs and a kind of CPU

  11. Test and verification of a reactor protection system application-specific integrated circuit

    International Nuclear Information System (INIS)

    Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.

    1997-01-01

    Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing

  12. Defect-based testing of LTS digital circuits

    NARCIS (Netherlands)

    Arun, A.J.

    2006-01-01

    A Defect-Based Test (DBT) methodology for Superconductor Electronics (SCE) is presented in this thesis, so that commercial production and efficient testing of systems can be implemented in this technology in the future. In the first chapter, the features and prospects for SCE have been presented.

  13. Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

    International Nuclear Information System (INIS)

    Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

    1992-01-01

    Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

  14. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    Science.gov (United States)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  15. Analysis of a PCB In-Circuit Test and Its Optimized Cycle

    International Nuclear Information System (INIS)

    Chi, Moon Goo; Lee, Eun Chan; Bae, Yeon Kyoung

    2011-01-01

    KHNP performs subcomponent performance tests of the PCBs (Printed Circuit Boards) installed in safety-related systems or plant trip-related systems with every outage. The characteristics of each subcomponent are measured by test equipment. The tests are known as an ICT (In-Circuit Test). If a degraded condition is detected by this test, the affected subcomponents are replaced. This test has been conducted for 17 years, since 1994, and its results have been compiled into a test system database. As part of the reliability improvement plan of critical PCBs, KHNP developed a program that analyzes the performance of various key PCBs based on this test data. Thus, it became possible to evaluate the performance trends related to PCBs by tracing the test history of the PCB subcomponents through the ICT over many years. The present study also estimates an optimized ICT cycle that can be implemented to prevent the degradation of PCBs before they fail due to aging

  16. Development of a Three-Tier Test to Assess Misconceptions about Simple Electric Circuits

    Science.gov (United States)

    Pesman, Haki; Eryilmaz, Ali

    2010-01-01

    The authors aimed to propose a valid and reliable diagnostic instrument by developing a three-tier test on simple electric circuits. Based on findings from the interviews, open-ended questions, and the related literature, the test was developed and administered to 124 high school students. In addition to some qualitative techniques for…

  17. Hard alloys testing-machine for values of PWR primary coolant circuits

    International Nuclear Information System (INIS)

    Campan, J.L.; Sauze, A.

    1980-01-01

    Testing of valve parts or material used in valve fabrication and particularly seizing conditions in friction of plane surfaces coated with hard alloys of the type stellite. The testing equipment called Marguerite is composed of a hot pressurized water loop in conditions similar to PWR primary coolant circuits (320 0 C, 150 bars) and a testing-machine with measuring instruments. Testing conditions and samples are described [fr

  18. E-learning platform for automated testing of electronic circuits using signature analysis method

    Science.gov (United States)

    Gherghina, Cǎtǎlina; Bacivarov, Angelica; Bacivarov, Ioan C.; Petricǎ, Gabriel

    2016-12-01

    Dependability of electronic circuits can be ensured only through testing of circuit modules. This is done by generating test vectors and their application to the circuit. Testability should be viewed as a concerted effort to ensure maximum efficiency throughout the product life cycle, from conception and design stage, through production to repairs during products operating. In this paper, is presented the platform developed by authors for training for testability in electronics, in general and in using signature analysis method, in particular. The platform allows highlighting the two approaches in the field namely analog and digital signature of circuits. As a part of this e-learning platform, it has been developed a database for signatures of different electronic components meant to put into the spotlight different techniques implying fault detection, and from this there were also self-repairing techniques of the systems with this kind of components. An approach for realizing self-testing circuits based on MATLAB environment and using signature analysis method is proposed. This paper analyses the benefits of signature analysis method and simulates signature analyzer performance based on the use of pseudo-random sequences, too.

  19. Geometrical considerations in the transient ionization testing of digital logic circuits

    International Nuclear Information System (INIS)

    Johnston, A.

    1982-01-01

    Mechanisms are identified that can cause the transient response of digital logic circuits to depend on the logic state in which they are irradiated. Several of these mechanisms depend on surface topology, and for these cases the sensitive logic states can be determined by examining the topology. General approaches for transient radiation testing are also discussed for several MSI and LSI device technologies

  20. Design and test of a capacitance detection circuit based on a transimpedance amplifier

    International Nuclear Information System (INIS)

    Mu Linfeng; Zhang Wendong; He Changde; Zhang Rui; Song Jinlong; Xue Chenyang

    2015-01-01

    This paper presents a transimpedance amplifier (TIA) capacitance detection circuit aimed at detecting micro-capacitance, which is caused by ultrasonic stimulation applied to the capacitive micro-machined ultrasonic transducer (CMUT). In the capacitance interface, a TIA is adopted to amplify the received signal with a center frequency of 400 kHz, and finally detect ultrasound pressure. The circuit has a strong anti-stray property and this paper also studies the calculation of compensation capacity in detail. To ensure high resolution, noise analysis is conducted. After optimization, the detected minimum ultrasound pressure is 2.1 Pa, which is two orders of magnitude higher than the former. The test results showed that the circuit was sensitive to changes in ultrasound pressure and the distance between the CMUT and stumbling block, which also successfully demonstrates the functionality of the developed TIA of the analog-front-end receiver. (paper)

  1. The Plateau de Bure ASTEP Platform Test in natural radiation environment of electronic components and circuits

    International Nuclear Information System (INIS)

    Autran, J.L.; Munteanu, D.; Sauze, S.; Roche, Ph.; Gasiot, G.; Borel, J.

    2010-01-01

    Reducing the size of microelectronic devices and increasing the integration density of circuits lead (following the famous Moore's law) to an increased sensitivity of circuits to natural terrestrial radiation environment. - Such sensitivity to atmospheric particles (mainly neutrons) can cause non-destructive (soft-errors) or destructive (latch-up) failures in most electronic circuits, including volatile static memories (SRAM), object of the research work carried out since 2004 on the European Test Platform ASTER. - This paper presents in details the ASTEP platform, its location, the instruments (neutron monitor of the Plateau de Bure) and the experiences (memory tester) currently installed on the Plateau de Bure. In a second part, we also report a synthesis of the key results concerning the natural radiation sensitivity of SRAM fabricated in 130 nm and 65 nm bulk silicon technologies. (authors)

  2. Automatic test pattern generation for stuck-at and delay faults in combinational circuits

    International Nuclear Information System (INIS)

    Kim, Dae Sik

    1998-02-01

    The present studies are developed to propose the automatic test pattern generation (ATG) algorithms for combinational circuits. These ATG algorithms are realized in two ATG programs: One is the ATG program for stuck-at fault and the other one for delay faults. In order to accelerate the ATG process, these two ATG programs have a common feature (the search method based on the concept of the degree of freedom), whereas only ATG program for the delay fault utilizes the 19-valued logic, a type of composite valued logic. This difference between two ATG programs results from the difference of the target fault. Accelerating the ATG process is indispensable for improving the ATG algorithms. This acceleration is mainly achieved by reducing the number of the unnecessary backtrackings, making the earlier detection of the conflicts, and shortening the computation time between the implication. Because of this purpose, the developed ATG programs include the new search method based on the concept of the degree of freedom (DF). The DF concept, computed directly and easily from the system descriptions such as types of gates and their interconnections, is the criterion to decide which, among several alternate lines' logic values required along each path, promises to be the most effective in order to accelerate and improve the ATG process. This DF concept is utilized to develop and improve both of ATG programs for stuck-at and delay faults in combinational circuits. In addition to improving the ATG process, reducing number of test pattern is indispensable for testing the delay faults because the size of the delay faults grows rapidly as increasing the size of the circuit. In order to improve the compactness of the test set, 19-valued logic are derived. Unlike other TG logic systems, 19-valued logic is utilized to generate the robustly hazard-free test pattern. This is achieved by using the basic 5-valued logic, proposed in this work, where the transition with no hazard is

  3. Test results and in-orbit operation of the Infrared Astronomical Satellite circumvention circuit

    Science.gov (United States)

    Long, E. C.; Langford, D.

    1984-01-01

    The IRAS circumvention circuit (CC) eliminates the unwanted charged-particle pulses from the IR signal. The operation of the CC along with preflight and in-orbit testing is described. Ground testing of the brassboard circuit using a simulated preamplifier output showed that the CC would perform the circumvention function as designed. When all flight detectors and preamplifiers became available, the CC was tested using a gamma source to simulate charged-particle sources; with the low energy deposited in the detectors (20 keV average) the noise was reduced by up to 5 times with the CC turned on. In-orbit results show that the CC decreases the unwanted charged-particle background noise by up to two orders of magnitude. The difference in the results with the CC on and off is so great that the science team has recommended that no data be taken with the CC off.

  4. A study on the development of an automatic fault diagnosis system for testing NPP digital electronic circuits

    International Nuclear Information System (INIS)

    Kim, Dae Sik

    1993-02-01

    This paper describes a study on the development of an automatic fault diagnosis system for testing digital electronic circuits of nuclear power plants. Compared with the other conventional fault diagnosis systems, the system described in this paper uses Artificial Intelligence technique of model based reasoning and corroboration, which makes fault diagnosis much more efficient. In order to reduce the testing time, an optimal testing set which means a minimal testing set to determine whether or not the circuit is fault-free and to locate the faulty gate was derived. Compared with the testing using an exhaustive testing set, the testing using the optimal testing set makes fault diagnosis much more fast. Since the system diagnoses the circuit boards bases only on input and output signals, it can be further developed for on-line testing. The system was implemented on a microprocessor and was applied for Universal Circuit board testing of the Solid State protection System in nuclear power plants

  5. WindoWorks: A flexible program for computerized testing of accelerator control system electronic circuit boards

    International Nuclear Information System (INIS)

    Utterback, J.

    1993-09-01

    Since most accelerator control system circuit boards reside in a commercial bus architecture, such as CAMAC or VMEbus, a computerized test station is needed for exercising the boards. This test station is needed for the development of newly designed prototypes, for commissioning newly manufactured boards, for diagnosing boards which have failed in service, and for long term testing of boards with intermittent failure problems. WindoWorks was created to address these needs. It is a flexible program which runs on a PC compatible computer and uses a PC to bus crate interface. WindoWorks was designed to give the user a flexible way to test circuit boards. Each test is incapsulated into a window. By bringing up several different windows the user can run several different tests simultaneously. The windows are sizable, and moveable. They have data entry boxes so that the test can be customized to the users preference. The windows can be used in conjunction with each other in order to create supertests. There are several windows which are generic. They can be used to test basic functions on any VME (or CAMAC) board. There are other windows which have been created to test specific boards. New windows for testing specific boards can be easily created by a Pascal programmer using the WindoWorks framework

  6. Scale model test on a novel 400 kV double-circuit composite pylon

    DEFF Research Database (Denmark)

    Wang, Qian; Bak, Claus Leth; Silva, Filipe Miguel Faria da

    This paper investigates lightning shielding performance of a novel 400 kV double-circuit composite pylon, with the method of scale model test. Lightning strikes to overhead lines were simulated by long-gap discharges between a high voltage electrode with an impulse voltage and equivalent conductors...... around the pylon is discussed. Combined test results and striking distance equation in electro-geometric model, the approximate maximum lightning current that can lead to shielding failure is calculated. Test results verify that the unusual negative shielding angle of - 60° in the composite pylon meets...... requirement and the shielding wires provide acceptable protection from lightning strikes....

  7. Manufacturing experience and test results of the PS prototype flexible hybrid circuit for the CMS Tracker Upgrade

    CERN Document Server

    Kovacs, Mark Istvan; Gadek, Tomasz; Honma, Alan; Vasey, Francois

    2017-01-01

    The CMS Tracker Phase-2 Upgrade for HL-LHC requires High Density Interconnect (HDI) flexible hybrid circuits to build modules with low mass and high granularity. The hybrids are carbon fibre reinforced flexible circuits with flip-chips and passives. Three different manufacturers produced prototype hybrids for the Pixel-Strip type modules. The first part of the presentation will focus on the design challenges of this state of the art circuit. Afterwards, the difficulties and experience related to the circuit manufacturing and assembly are presented. The description of quality inspection methods with comprehensive test results will lead to the conclusion.

  8. Design and testing of a low impedance transceiver circuit for nitrogen-14 nuclear quadrupole resonance.

    Science.gov (United States)

    Sato-Akaba, Hideo

    2014-01-01

    A low impedance transceiver circuit consisting of a transmit-receive switch circuit, a class-D amplifier and a transimpedance amplifier (TIA) was newly designed and tested for a nitrogen-14 NQR. An NQR signal at 1.37MHz from imidazole was successfully observed with the dead time of ~85µs under the high Q transmission (Q~120) and reception (Q~140). The noise performance of the low impedance TIA with an NQR probe was comparable with a commercial low noise 50Ω amplifier (voltage input noise: 0.25 nV/Hz) which was also connected to the probe. The protection voltage for the pre-amplifier using the low impedance transceiver was ~10 times smaller than that for the pre-amplifier using a 50Ω conventional transceiver, which is suitable for NQR remote sensing applications. Copyright © 2014 Elsevier Inc. All rights reserved.

  9. A new circuit for at-speed scan SoC testing

    International Nuclear Information System (INIS)

    Lin Wei; Shi Wenlong

    2013-01-01

    It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. (semiconductor integrated circuits)

  10. Optimal testing input sets for reduced diagnosis time of nuclear power plant digital electronic circuits

    International Nuclear Information System (INIS)

    Kim, D.S.; Seong, P.H.

    1994-01-01

    This paper describes the optimal testing input sets required for the fault diagnosis of the nuclear power plant digital electronic circuits. With the complicated systems such as very large scale integration (VLSI), nuclear power plant (NPP), and aircraft, testing is the major factor of the maintenance of the system. Particularly, diagnosis time grows quickly with the complexity of the component. In this research, for reduce diagnosis time the authors derived the optimal testing sets that are the minimal testing sets required for detecting the failure and for locating of the failed component. For reduced diagnosis time, the technique presented by Hayes fits best for the approach to testing sets generation among many conventional methods. However, this method has the following disadvantages: (a) it considers only the simple network (b) it concerns only whether the system is in failed state or not and does not provide the way to locate the failed component. Therefore the authors have derived the optimal testing input sets that resolve these problems by Hayes while preserving its advantages. When they applied the optimal testing sets to the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, they found that the fault diagnosis using the optimal testing sets makes testing the digital electronic circuits much faster than that using exhaustive testing input sets; when they applied them to test the Universal (UV) Card which is a nuclear power plant digital input/output solid state protection system card, they reduced the testing time up to about 100 times

  11. Nuclear code case development of printed-circuit heat exchangers with thermal and mechanical performance testing

    Energy Technology Data Exchange (ETDEWEB)

    Aakre, Shaun R. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering; Jentz, Ian W. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering; Anderson, Mark H. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering

    2018-03-27

    The U.S. Department of Energy has agreed to fund a three-year integrated research project to close technical gaps involved with compact heat exchangers to be used in nuclear applications. This paper introduces the goals of the project, the research institutions, and industrial partners working in collaboration to develop a draft Boiler and Pressure Vessel Code Case for this technology. Heat exchanger testing, as well as non-destructive and destructive evaluation, will be performed by researchers across the country to understand the performance of compact heat exchangers. Testing will be performed using coolants and conditions proposed for Gen IV Reactor designs. Preliminary observations of the mechanical failure mechanisms of the heat exchangers using destructive and non-destructive methods is presented. Unit-cell finite element models assembled to help predict the mechanical behavior of these high-temperature components are discussed as well. Performance testing methodology is laid out in this paper along with preliminary modeling results, an introduction to x-ray and neutron inspection techniques, and results from a recent pressurization test of a printed-circuit heat exchanger. The operational and quality assurance knowledge gained from these models and validation tests will be useful to developers of supercritical CO2 systems, which commonly employ printed-circuit heat exchangers.

  12. Test model of the fast thyristor circuit breaker, for TORE SUPRA

    International Nuclear Information System (INIS)

    Bareyt, B.; Leloup, C.; Rijnoudt, E.

    1984-01-01

    The tokamak TORE SUPRA, permits, owing to the toroidal superconducting coils and to the poloidal field system performances, long discharges (30 s and more), for a plasma current of typically 2 MA. The poloidal field system uses the magnetic energy initially stored, for the ignition and the fast rise of the plasma current, by forcing the primary current to flow through a resistor after breaking the main rectifier current by a fast thyristor circuit breaker. In order to test the technical capabilities of such a breaker system made of fast thyristors, in series and in parallel, after a single thyristor test model T1 the series arrangement was studied on a 24 thyristor test model T2 and the parallel arrangement problems, led the manufacturer CGEE Alsthom, to build a new test model T3. (author)

  13. Test and diagnosis of analogue, mixed-signal and RF integrated circuits the system on chip approach

    CERN Document Server

    Sun, Yichuang

    2008-01-01

    This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective.

  14. New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

    Energy Technology Data Exchange (ETDEWEB)

    Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

    1983-07-01

    This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

  15. Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients

    Directory of Open Access Journals (Sweden)

    Michael Auer

    2009-02-01

    Full Text Available The aim of this work is to develop a simultaneous multi user access system – READ (Remote ASIC Design and Test that allows users to perform test and measurements remotely via clients running on mobile devices as well as on standard PCs. The system also facilitates the remote design of circuits with the PAC-Designer The system is controlled by LabVIEW and was implemented using a Data Acquisition Card from National instruments. Such systems are specially suited for manufacturing process monitoring and control. The performance of the simultaneous access was tested under load with a variable number of users. The server implements a queue that processes user’s commands upon request.

  16. Testing of interposer-based 2.5D integrated circuits

    CERN Document Server

    Wang, Ran

    2017-01-01

    This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and dela...

  17. Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods

    Directory of Open Access Journals (Sweden)

    Hai Au Huynh

    2015-01-01

    Full Text Available Direct power injection (DPI and bulk current injection (BCI methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC. The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.

  18. The Automated DC Parameter Testing of GaAs MESFETs Using the Singer Automatic Integrated Circuit Test System.

    Science.gov (United States)

    1980-09-01

    USING THE SINGER AUTOMATIC INTEGRATED CIRCUIT TEST SYSTEM, THOMAS L. HARPER AFIT/EE/GE/80- 7 Ist LT USAF -- -- - - __ AFIT/EE/GE/80-7 THE AUTOMATED DC...THOMAS L. HARPER ist Lt USAF Graduate Electrical Engineering September 1980 it’ Codes A _ _ _ J PREFACE This report is in support of the ongoing effort in...8217.-- I *t -1 ,p - tUel-, ir. ( /.s , j Yf) L) b ..... l P i:. +’ ,T i~: ",,’+l l L V i i ,’b : O Iil r, P V 47 C’+t ( ’ I ViH 47 V ’L 4 £, ,.;l 1 , h

  19. Development of data acquisition system for test circuit for the Thermo-Hydraulic Laboratory of CDTN

    International Nuclear Information System (INIS)

    Corrade, Thales Jose Rodrigues; Mesquita, Amir Zacarias; Santos, Andre Augusto Campagnole dos

    2013-01-01

    The Circuit Water-Air (CWA), present in the Laboratorio de Termo-Hidraulica of the Centro de Desenvolvimento da Tecnologia Nuclear/Comissao Nacional de Energia Nuclear (CDTN / CNEN), has been used to evaluate devices present in nuclear fuel elements of a PWR (Pressurized Water Reactor). Currently, a segment of 5x5 beam simulators grids with spacer bars is being tested, serving one of the activities under the Project FUJB / FINEP / INB - 'Development of New Generation of Nuclear Fuel Element '. For the measurements of pressure drop along this beam, a system of data acquisition based on Basic language was created. Although this system is efficient and robust, their resources are very limited. Therefore, it was decided to use the software LabVIEW® implementing a more versatile and modern system. This article describes the new data acquisition system, and presents some results. The main parameters are monitored: temperature, density, dynamic viscosity, Reynolds number. The values of standard deviation, mean and uncertainty of an arbitrary channel are calculated. The system was installed and tested in the circuit under experimental conditions and showed satisfactory results.

  20. Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

    Science.gov (United States)

    Spry, David; Neudeck, Phil; Chen, Liangyu; Chang, Carl; Lukco, Dorothy; Beheim, Glenn M

    2016-01-01

    We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

  1. Development, testing, and demonstration of an optimal fine coal cleaning circuit

    Energy Technology Data Exchange (ETDEWEB)

    Mishra, M.; Placha, M.; Bethell, P. [and others

    1995-11-01

    The overall objective of this project is to improve the efficiency of fine coal cleaning. The project will be completed in two phases: bench-scale testing and demonstration of four advanced flotation cells and; in-plant proof-of-concept (POC) pilot plant testing of two flotation cells individually and in two-stage combinations. The goal is to ascertain if a two-stage circuit can result in reduced capital and operating costs while achieving improved separation efficiency. The plant selected for this project, Cyprus Emerald Coal Preparation plant, cleans 1200 tph of raw coal. The plant produces approximately 4 million tonnes of clean coal per year at an average as received energy content of 30.2 MJ/Kg (13,000 Btu/lb).

  2. Development, testing, and demonstration of an optimal fine coal cleaning circuit

    International Nuclear Information System (INIS)

    Mishra, M.; Placha, M.; Bethell, P.

    1995-01-01

    The overall objective of this project is to improve the efficiency of fine coal cleaning. The project will be completed in two phases: bench-scale testing and demonstration of four advanced flotation cells and; in-plant proof-of-concept (POC) pilot plant testing of two flotation cells individually and in two-stage combinations. The goal is to ascertain if a two-stage circuit can result in reduced capital and operating costs while achieving improved separation efficiency. The plant selected for this project, Cyprus Emerald Coal Preparation plant, cleans 1200 tph of raw coal. The plant produces approximately 4 million tonnes of clean coal per year at an average as received energy content of 30.2 MJ/Kg (13,000 Btu/lb)

  3. A proposed hardness assurance test methodology for bipolar linear circuits and devices in a space ionizing radiation environment

    International Nuclear Information System (INIS)

    Pease, R.L.; Brown, D.B.; Cohn, L.

    1997-01-01

    A hardness assurance test approach has been developed for bipolar linear circuits and devices in space. It consists of a screen for dose rate sensitivity and a characterization test method to develop the conditions for a lot acceptance test at high dose rate

  4. Short-circuit testing of monofilar Bi-2212 coils connected in series and in parallel

    International Nuclear Information System (INIS)

    Polasek, A; Dias, R; Serra, E T; Filho, O O; Niedu, D

    2010-01-01

    Superconducting Fault Current Limiters (SCFCL's) are one of the most promising technologies for fault current limitation. In the present work, resistive SCFCL components based on Bi-2212 monofilar coils are subjected to short-circuit testing. These SCFCL components can be easily connected in series and/or in parallel by using joints and clamps. This allows a considerable flexibility to developing larger SCFCL devices, since the configuration and size of the whole device can be easily adapted to the operational conditions. The single components presented critical current (Ic) values of 240-260 A, at 77 K. Short-circuits during 40-120 ms were applied. A single component can withstand a voltage drop of 126-252 V (0.3-0.6 V/cm). Components connected in series withstand higher voltage levels, whereas parallel connection allows higher rated currents during normal operation, but the limited current is also higher. Prospective currents as high as 10-40 kA (peak value) were limited to 3-9 kA (peak value) in the first half cycle.

  5. Test gear and measurements a collection of useful and tested circuit design ideas'

    CERN Document Server

    Stewart OBE DLitthc, David

    2013-01-01

    This book provides a clear introduction to test gear in the field of electronics. As well as being a first guide to test gear and its use, the book includes much practical information and reference material for the more experienced electronics enthusiast or student.Based on a collection of feature articles originally published in Electronics - the Maplin Magazine, this work by Danny Stewart is sure to be useful to electronics constructors, students and experimenters alike. Details of all the common (and some not-so-common) items of test gear are included, alongside information regarding its us

  6. Development of the automatic test pattern generation for NPP digital electronic circuits using the degree of freedom concept

    International Nuclear Information System (INIS)

    Kim, D.S.; Seong, P.H.

    1995-01-01

    In this paper, an improved algorithm for automatic test pattern generation (ATG) for nuclear power plant digital electronic circuits--the combinational type of logic circuits is presented. For accelerating and improving the ATG process for combinational circuits the presented ATG algorithm has the new concept--the degree of freedom (DF). The DF, directly computed from the system descriptions such as types of gates and their interconnections, is the criterion to decide which among several alternate lines' logic values required along each path promises to be the most effective in order to accelerate and improve the ATG process. Based on the DF the proposed ATG algorithm is implemented in the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, it is shown that the AFDS using the ATG algorithm makes Universal Card (UV Card) testing much faster than the present testing practice or by using exhaustive testing sets

  7. Improvement and qualification of ultrasonic testing of dissimilar welds in the primary circuit of NPPs

    International Nuclear Information System (INIS)

    Mitzscherling, Steffen; Barth, Enrico; Homann, Tobias; Prager, Jens; Goetschel, Sebastian; Weiser, Martin

    2017-01-01

    The austenitic and dissimilar welds found in the primary circuit of nuclear power plants are not only extremely relevant to safety but also place very high demands on material testing. In addition to limited accessibility, the macroscopic structure of the weld seam is of paramount importance for ultrasound testing. In order to reliably determine material errors in position and size, the grain orientations and the elastic constants of the anisotropic weld bead structure must be known. The following work steps are used for the imaging representation of possible material defects: First, the weld seam is sounded in order to be able to determine important weld seam parameters, such as, for example, the grain orientation, using an inverse method. On the basis of these parameters, the sound paths are simulated in the next step by means of raytracing (RT). Finally, this RT simulation is assigned the measurement data (A-scans) from different transmitter and receiver positions and superimposed according to the Synthetic Aperature Focusing Technique (SAFT) method. The combination of inverse process, RT and SAFT also ensures a correct visualization of the faults in anisotropic materials. We explain these three methods and present the test arrangement of test specimens with artificial test errors. Measurement data as well as their evaluation are compared with the results of a CIVA simulation. [de

  8. Induced over voltage test on transformers using enhanced Z-source inverter based circuit

    Science.gov (United States)

    Peter, Geno; Sherine, Anli

    2017-09-01

    The normal life of a transformer is well above 25 years. The economical operation of the distribution system has its roots in the equipments being used. The economy being such, that it is financially advantageous to replace transformers with more than 15 years of service in the second perennial market. Testing of transformer is required, as its an indication of the extent to which a transformer can comply with the customers specified requirements and the respective standards (IEC 60076-3). In this paper, induced over voltage testing on transformers using enhanced Z source inverter is discussed. Power electronic circuits are now essential for a whole array of industrial electronic products. The bulky motor generator set, which is used to generate the required frequency to conduct the induced over voltage testing of transformers is nowadays replaced by static frequency converter. First conventional Z-source inverter, and second an enhanced Z source inverter is being used to generate the required voltage and frequency to test the transformer for induced over voltage test, and its characteristics is analysed.

  9. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    Science.gov (United States)

    Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

    2015-11-01

    We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80-120%, with respect to the designed bias currents.

  10. The life test of a DC circuit breaker of tokamak device JT-60 for a nuclear fusion research

    International Nuclear Information System (INIS)

    Shimada, Ryuichi; Tani, Keiji; Kishimoto, Hiroshi; Tamura, Sanae; Yanabu, Satoru.

    1979-01-01

    In the Tokamak devices for nuclear fusion research, the construction of the current transformer circuits having plasma as the secondary circuit and the change of the primary circuit current are necessary for generating current in the plasma. This is considered to be fairly difficult in practice if conventional methods using capacitor discharge and iron core coils are employed. Considering such circumstances, it was decided for JT-60 to use an air-core current transformer coil and to employ the method of storing energy in the form of current in the coil inductance instead of a capacitor. For this reason, a DC circuit breaker is required to interrupt coil current. The authors improved an AV vacuum breaker, which had been developed as the vacuum breaker of longitudinal magnetic field type applying a magnetic field in parallel with an arc, to get the one for DC circuit for the purpose of applying it to JT-60. In this paper, the operational characteristic of the DC breaker is described, the construction and function of the life test circuit is explained, and the test results are reported. Finally, interruptions of 10,000 times at 20 kA were carried out. It is successful that the restrike of arc occurring during tens of milli-seconds after interruptions was improved to 0.05% or less for 10,000 times operations. Further, it was found that the generation of arc restrike can be reduced practically to zero with two breakers in series. (Wakatsuki, Y.)

  11. Experimental Study of WBFC method for testing electromagnetic immunity of integrated circuits

    OpenAIRE

    香川, 直己; カガワ, ナオキ; Naoki, KAGAWA

    2004-01-01

    The author made a workbench faraday cage, WBFC, in order to estimate performance of the WBFC method for the measurement of common mode noise immunity of integrated circuits. In this report, characteristics of the constructed workbench faraday cage and results of experimental study of effects of the common mode noise on a circuit board including an electronic device are shown. Selected DUT, LM324 is popular operational amplifier for electrical circuits in vehicles.

  12. Modernized CDTN's air-water experimental test circuit: initial results

    Energy Technology Data Exchange (ETDEWEB)

    Pessoa, Mácio A.; Sobrinho, Mauricio R. da S.; Salomão, Eduardo A.; Ferreira, Arthur F.J.; Navarro, Moysés A.; Santos, André A. Campagnole dos, E-mail: marcioaraujopessoa@gmail.com, E-mail: mauricio.sobrinho223@gmail.com, E-mail: e.a.salomao@gmail.com, E-mail: arthur1303@gmail.com, E-mail: moysesnavarro@yahoo.com.br, E-mail: aacs@cdtn.br [Centro de Desenvolvimento da Tecnologia Nuclear (CDTN/CNEN-MG), Belo Horizonte, MG (Brazil)

    2017-07-01

    The Counter Current Flow Limitation (CCFL) phenomenon, specifically the control that the gas exerts in a liquid flow in the opposite direction, is of real importance in the study of design and operation of various industrial sectors, particularly the nuclear industry. In nuclear engineering, such a phenomenon can occur in a loss of coolant accident (LOCA) of a Pressurized Water Reactor (PWR) when there is the need to re-flood the reactor core during an emergency cooling process. The CCFL phenomenon is being investigated at the Nuclear Technology Development Center (CDTN) thermo-hydraulics laboratory in order to better understand the flow and its limitations and thereby contribute to the improvement of its modeling for analysis of severe accidents. For this, a series of experiments were performed in CDTN in a reduced scale acrylic test section of the 'hot leg' of a PWR. The new proposed circuit is a closed loop and no water has to be discharged during the experiment. This is only possible due to the Python program, which is associated to the data acquisition system and can interface with the automated valves through the outputs of the data acquisition board to control the experiment. The trials compare the CCFL behavior for 500mm lengths of the horizontal section, for inclined duct slope 50° for a diameter of 54mm pipe's diameter. This paper describes the new tests in comparison to tests performed in the past. (author)

  13. Modernized CDTN's air-water experimental test circuit: initial results

    International Nuclear Information System (INIS)

    Pessoa, Mácio A.; Sobrinho, Mauricio R. da S.; Salomão, Eduardo A.; Ferreira, Arthur F.J.; Navarro, Moysés A.; Santos, André A. Campagnole dos

    2017-01-01

    The Counter Current Flow Limitation (CCFL) phenomenon, specifically the control that the gas exerts in a liquid flow in the opposite direction, is of real importance in the study of design and operation of various industrial sectors, particularly the nuclear industry. In nuclear engineering, such a phenomenon can occur in a loss of coolant accident (LOCA) of a Pressurized Water Reactor (PWR) when there is the need to re-flood the reactor core during an emergency cooling process. The CCFL phenomenon is being investigated at the Nuclear Technology Development Center (CDTN) thermo-hydraulics laboratory in order to better understand the flow and its limitations and thereby contribute to the improvement of its modeling for analysis of severe accidents. For this, a series of experiments were performed in CDTN in a reduced scale acrylic test section of the 'hot leg' of a PWR. The new proposed circuit is a closed loop and no water has to be discharged during the experiment. This is only possible due to the Python program, which is associated to the data acquisition system and can interface with the automated valves through the outputs of the data acquisition board to control the experiment. The trials compare the CCFL behavior for 500mm lengths of the horizontal section, for inclined duct slope 50° for a diameter of 54mm pipe's diameter. This paper describes the new tests in comparison to tests performed in the past. (author)

  14. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

    Science.gov (United States)

    Breuer, M. A.; Carlan, A. J.

    1982-10-01

    Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

  15. Testing of 800 and 1200 kV class circuit breakers

    NARCIS (Netherlands)

    Smeets, R.P.P.; Kuivenhoven, S.; Hofstee, A.B.

    2011-01-01

    The most critical transient a circuit breaker has to endure during its operation is the transient recovery voltage (TRV), initiated by the electric power system as a natural reaction on current interruption. For circuit breakers intended to operate in ultra-high voltage systems (with rated voltage

  16. Design, construction and tests of the power crowbar and predischarge circuit of the SPICA II experiment

    International Nuclear Information System (INIS)

    Ingen, A.M. van; Manintveld, P.; Sterk, A.B.

    1983-01-01

    A 28 Farad, 1.8 MJ electrolytic capacitor power-crowbar battery and a flexible predischarge circuit for the SPICA II screw-pinch experiment is described. The battery is capable of delivering the toroidal and poloidal currents of more than 2.5 MA, during at least 1 ms after crowbarring of the high-voltage capacitor banks. To obtain a low short-circuit impedance a very compact construction was chosen, which resulted in seven modules of about 1 m 3 each, Rsub(i) = 100 μΩ, Lsub(i) = 7 nH, connected by plate systems to the main circuit. The predischarge circuit consists of a fast capacitor bank to start the predischarge and a slow circuit with a clamp switch to preheat the discharge. (author)

  17. High-Temperature Test of 800HT Printed Circuit Heat Exchanger in HELP

    International Nuclear Information System (INIS)

    Kim, Chan Soo; Hong, Sung-Deok; Kim, Min Hwan; Shim, Jaesool

    2014-01-01

    Korea Atomic Energy Research Institute has developed high-temperature Printed Circuit Heat Exchangers (PCHE) for a Very High Temperature gas-cooled Reactor and operated a very high temperature Helium Experimental LooP (HELP) to verify the performance of the high temperature heat exchanger at the component level environment. PCHE is one of the candidates for the intermediate heat exchanger in a VHTR, because its design temperature and pressure are larger than any other compact heat exchanger types. High temperature PCHEs in HELP consist of an alloy617 PCHE and an 800HT PCHE. This study presents the high temperature test of an 800HT PCHE in HELP. The experimental data include the pressure drops, the overall heat transfer coefficients, and the surface temperature distributions under various operating conditions. The experimental data are compared with the thermo-hydraulic analysis from COMSOL. In addition, the single channel tests are performed to quantify the friction factor under normal nitrogen and helium inlet conditions. (author)

  18. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    International Nuclear Information System (INIS)

    Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

    2015-01-01

    Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

  19. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    Energy Technology Data Exchange (ETDEWEB)

    Yamada, Takahiro, E-mail: yamada-takahiro@aist.go.jp [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Maezawa, Masaaki [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Urano, Chiharu [National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Central 3, Umezono 1-1-1, Tsukuba, Ibaraki 305-8563 (Japan)

    2015-11-15

    Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

  20. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    International Nuclear Information System (INIS)

    Estreich, D.B.

    1978-11-01

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

  1. Proposed minimum requirements for the operational characteristics and testing of closed circuit life support system control electronics.

    Science.gov (United States)

    Kirk, J C

    1998-01-01

    The popularization and transformation of scuba diving into a broadly practiced sport has served to ignite the interest of technically oriented divers into ever more demanding areas. This, along with the gradual release of military data, equipment, and techniques of closed circuit underwater breathing apparatus, has resulted in a virtual explosion of semiclosed and closed circuit systems for divers. Although many of these systems have been carefully thought out by capable designers, the impulse to rush to market with equipment that has not been fully developed and carefully tested is irresistible to marketers. In addition, the presence of systems developed by well-intentioned and otherwise competent designers who are, nonetheless, inexperienced in the field of life support can result in the sale of failure-prone equipment to divers who lack the knowledge and skills to identify deficiencies before disaster occurs. For this reason, a set of industry standards establishing minimum requirements and testing is needed to guide the designers of this equipment, and to protect the user community from incomplete or inadequate design. Many different technologies go into the development of closed circuit scuba. One key area is the design of electronics to monitor and maintain the critical gas mixtures of the closed circuit loop. Much of the system reliability and inherent danger is resident in the design of the circuitry and the software (if any) that runs it. This article will present a set of proposed minimum requirements, with the goal of establishing a dialog for the creation of guidelines for the classification, rating, design, and testing of embedded electronics for life support systems used in closed circuit applications. These guidelines will serve as the foundation for the later creation of a set of industry specifications.

  2. The online sealing performance test of the primary circuit pressure boundary check valve in nuclear power plants

    International Nuclear Information System (INIS)

    Yang Yunfei; Huang Huimin

    2013-01-01

    The primary circuit pressure boundary check valves of 320 MW pressurized water reactor is a nuclear grade I key equipment. The sealing demand is very high, which is directly related to the internal leakage rate of the primary circuit system. After the welding check valve is repaired, the sealing performance is judged by color printing checks. If there is water or humid vapor in the pipe, it will affect the accuracy of the color printing checks. For the particularity of the online check valve tightness test, online detecting device is designed by the hydraulic pressure drop method in other nuclear power plants, but the method has some shortcomings and restrictions. In this paper, we design a reliable and portable test equipment by the low-pressure gas seal test flow measurement, which make accurate and quantitative judgment of sealing property after the pressure boundary check valves are repaired. (authors)

  3. Short-circuit tests of 1650 and 96 MVA transformers for 1300 MW french nuclear power plants

    International Nuclear Information System (INIS)

    Mailhot, M.

    1989-01-01

    Power evacuation and feeding of the auxiliaries directly from the 400 kV grid are sensitive points governing the security of 1300 MW PWR Nuclear Power Plants of the French Program. These two different functions are provided by two specific types of transformers. - Banks of 3 single-phase 550 MVA - 400 kV/20 kV transformers. - Three-phase 96 MVA - 400 kV / 3 x 6.8 kV transformers. These passive elements must have a never failing reliability and assure a continuous service in spite of electric, thermal and mechanical stresses that may occur during the lifetime of the power plant. Dielectric and thermal tests carried out in the manufacturers test floors insure these stresses withstand capabilities of transformers. In France, high short-circuit power for the 400 kV network added to often low impedance voltages for transformers impose on them very high stresses during short-circuits. Calculation and experimentation on scale or partial models are not sufficient to insure short-circuit currents withstand capabilities of transformers. The margin of uncertainty dependent on obligatory extrapolations for this kind of complex systems [steel, magnetic sheets, copper, oil, paper and transformerboard] can be reduced in a significant way only by real scale tests on prototypes. These tests that need both high power and voltage cannot be performed in manufacturers test floors. So, in France they are carried out at the EDF Les Renardieres Laboratory. Following paper deals with SHELL TYPE TRANSFORMERS which, particularly thanks to their interleaved rectangular windings display a great resistance to short-circuit stresses

  4. A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

    Directory of Open Access Journals (Sweden)

    C. Wu

    2011-06-01

    Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.

  5. Proposal for the modernization of CDTN's Air-Water CCFL experimental test circuit

    International Nuclear Information System (INIS)

    Pessoa, Marcio Araujo; Mesquita, Amir Zacarias; Navarro, Moyses A.; Santos, Andre A. Campagnole dos

    2015-01-01

    The Counter Current Flow Limitation (CCFL) phenomenon, specifically the control that the gas exerts in a liquid flow in the opposite direction, is of real importance in the study of design and operation of various industrial sectors, particularly the nuclear industry. In nuclear engineering, such a phenomenon can occur in a loss of coolant accident (LOCA) of a Pressurized Water Reactor (PWR) when there is the need to re-flood the reactor core during an emergency cooling process. The CCFL phenomenon is being investigated at the Nuclear Technology Development Center (CDTN) thermo-hydraulics laboratory in order to better understand the flow and its limitations and thereby contribute to the improvement of its modeling for analysis of severe accidents. For this, a series of experiments were performed in CDTN in a reduced scale acrylic test section of the 'hot leg' of a PWR. In these tests, the countercurrent flow was established through the water injection by the upper end of the inclined pipe and the air addition at the end opposite to the entry of liquid flow. With the gradual increase of the air flow for predetermined water levels, the onset of the limitation of flow to the full blockage was determined. After full blockage, a gradual reduction of air flow was performed to evaluate the deflooding of the hot leg. The trials also evaluated CCFL behavior for various lengths of the horizontal section, the inclined duct slope influence and the dependence of the pipe's diameter. The infrastructure for CCFL analysis was built 14 years ago and has not been updated since. This paper describes the updates that are being performed to the existing setup. Hydraulic circuit and instrumentation upgrades and the implementation of modern control systems will allow new data to be collected and a new range of experiments to be performed with lower uncertainty. It is intended that the new data be used to validate CFD models that are also being developed by the research

  6. The laboratory testing system for radiation rsistance investigations of integrated circuits

    International Nuclear Information System (INIS)

    Wronski, W.; Wislowski, J.

    1986-01-01

    In order to evaluate the radiation tolerance of integrated circuits MCY 7102 type /MOS RAM/ two devices were built: isotope arrangement for irradiation, and portable tester registering every error of storage block which consists of 32 IC's. Principle of operation and construction of this devices is described. Exemplary results of investigations are shown. (author)

  7. Fault Modeling and Testing for Analog Circuits in Complex Space Based on Supply Current and Output Voltage

    Directory of Open Access Journals (Sweden)

    Hongzhi Hu

    2015-01-01

    Full Text Available This paper deals with the modeling of fault for analog circuits. A two-dimensional (2D fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional (3D complex space is proposed, which achieves a far better fault detection ratio (FDR against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT method. By adding redundant bypassing-components in the circuit under test (CUT, this method achieves excellent fault isolation ratio (FIR in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.

  8. The short-circuit test results of 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer

    International Nuclear Information System (INIS)

    Tomioka, A.; Otonari, T.; Ogata, T.; Iwakuma, M.; Okamoto, H.; Hayashi, H.; Iijima, Y.; Saito, T.; Gosho, Y.; Tanabe, K.; Izumi, T.; Shiohara, Y.

    2011-01-01

    The 6.9 kV/2.3 kV 400 kVA-class single-phase YBCO model transformer with the YBCO tape with copper tape was manufactured for short-circuit current test. Short-circuit test was performed and the short-circuit current of primary winding was 346 A which was about six times larger than the rated current. The I-V characteristics of the winding did not change before and after the test. The transformer withstood short-circuit current. We are planning to turn the result into a consideration of a 66 kV/6.9 kV-20 MVA-class three-phase superconducting transformer. We are developing an elemental technology for 66 kV/6.9 kV 20 MVA-class power transformer with YBCO conductors. The protection of short-circuit technology is one of the elemental technologies for HTS transformer. Since short-circuit current is much higher than critical current of YBCO tape, there is a possibility that superconducting characteristics may be damaged during short-circuit period. We made a conductor to compose the YBCO tape with copper tape. We manufactured 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer using this conductor and performed short-circuit current test. The short-circuit current of primary winding was 346 A which was about six times larger than the rated current. The I-V characteristics of the winding did not change before and after the test. We may consider this conductor withstands short-circuit current.

  9. Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

    International Nuclear Information System (INIS)

    Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

    2010-01-01

    A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

  10. Rational design of modular circuits for gene transcription: A test of the bottom-up approach

    Directory of Open Access Journals (Sweden)

    Giordano Emanuele

    2010-11-01

    Full Text Available Abstract Background Most of synthetic circuits developed so far have been designed by an ad hoc approach, using a small number of components (i.e. LacI, TetR and a trial and error strategy. We are at the point where an increasing number of modular, inter-changeable and well-characterized components is needed to expand the construction of synthetic devices and to allow a rational approach to the design. Results We used interchangeable modular biological parts to create a set of novel synthetic devices for controlling gene transcription, and we developed a mathematical model of the modular circuits. Model parameters were identified by experimental measurements from a subset of modular combinations. The model revealed an unexpected feature of the lactose repressor system, i.e. a residual binding affinity for the operator site by induced lactose repressor molecules. Once this residual affinity was taken into account, the model properly reproduced the experimental data from the training set. The parameters identified in the training set allowed the prediction of the behavior of networks not included in the identification procedure. Conclusions This study provides new quantitative evidences that the use of independent and well-characterized biological parts and mathematical modeling, what is called a bottom-up approach to the construction of gene networks, can allow the design of new and different devices re-using the same modular parts.

  11. Influence of different open circuit voltage tests on state of charge online estimation for lithium-ion batteries

    International Nuclear Information System (INIS)

    Zheng, Fangdan; Xing, Yinjiao; Jiang, Jiuchun; Sun, Bingxiang; Kim, Jonghoon; Pecht, Michael

    2016-01-01

    Highlights: • Two common tests for observing battery open circuit voltage performance are compared. • The temperature dependency of the OCV-SOC relationship is investigated. • Two estimators are evaluated in terms of accuracy and robustness for estimating battery SOC. • The incremental OCV test is better to predetermine the OCV-SOCs for SOC online estimation. - Abstract: Battery state of charge (SOC) estimation is a crucial function of battery management systems (BMSs), since accurate estimated SOC is critical to ensure the safety and reliability of electric vehicles. A widely used technique for SOC estimation is based on online inference of battery open circuit voltage (OCV). Low-current OCV and incremental OCV tests are two common methods to observe the OCV-SOC relationship, which is an important element of the SOC estimation technique. In this paper, two OCV tests are run at three different temperatures and based on which, two SOC estimators are compared and evaluated in terms of tracking accuracy, convergence time, and robustness for online estimating battery SOC. The temperature dependency of the OCV-SOC relationship is investigated and its influence on SOC estimation results is discussed. In addition, four dynamic tests are presented, one for estimator parameter identification and the other three for estimator performance evaluation. The comparison results show that estimator 2 (based on the incremental OCV test) has higher tracking accuracy and is more robust against varied loading conditions and different initial values of SOC than estimator 1 (based on the low-current OCV test) with regard to ambient temperature. Therefore, the incremental OCV test is recommended for predetermining the OCV-SOCs for battery SOC online estimation in BMSs.

  12. Oscillator circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

  13. Measuring circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

  14. EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    S. A. Chizhik

    2013-01-01

    Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

  15. Simulation of TunneLadder traveling-wave tube cold-test characteristics: Implementation of the three-dimensional, electromagnetic circuit analysis code micro-SOS

    Science.gov (United States)

    Kory, Carol L.; Wilson, Jeffrey D.

    1993-01-01

    The three-dimensional, electromagnetic circuit analysis code, Micro-SOS, can be used to reduce expensive time-consuming experimental 'cold-testing' of traveling-wave tube (TWT) circuits. The frequency-phase dispersion characteristics and beam interaction impedance of a TunneLadder traveling-wave tube slow-wave structure were simulated using the code. When reasonable dimensional adjustments are made, computer results agree closely with experimental data. Modifications to the circuit geometry that would make the TunneLadder TWT easier to fabricate for higher frequency operation are explored.

  16. Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Chang, Carl W.; Lukco, Dorothy; Beheim, Glenn M.

    2016-01-01

    We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

  17. Dimensioning of optimal probe circuits for the non-destructive testing of materials by eddy-current using Buschbeck-Meinke chart

    International Nuclear Information System (INIS)

    Ott, A.

    1982-01-01

    By application of a modified form of the Buschbeck-Meinke-diagram, known from conduction theory, easy-to use dimensioning rules can be given for the probe circuits of single-frequency eddy-current test instruments. Dimensioning is found for circuits that work with amplitude or phase measurements, that suppress optimal the disturbance parameters in certain regions. In a similar way one can determine dimensioning, with which the measurement quantity causes the highest possible signal charge. (orig.) [de

  18. Surface and 60 FSW Performance Testing of the Modified MBS 2000 Closed Circuit Oxygen Rebreather

    National Research Council Canada - National Science Library

    Fothergill, David

    2007-01-01

    ... into the system during a treatment. Since all previous testing had been performed at 1 ATA, a second major objective for the FY06 tests was to evaluate the modified MBS 2000 rebreather at 60 fsw in a hyperbaric chamber...

  19. The LFSR and BCA VHDL Models for Built-in Self-test Circuits

    Directory of Open Access Journals (Sweden)

    J. Mitrych

    2002-04-01

    Full Text Available The various test structures are proposed for BIST techniques [1],[2]. A typical structure used for generation of pseudo-random test setsis the linear feedback shift register (LFSR. The BIST techniques havewide application in testing whole devices and embedded components. Wefocus on the analysis of the state coverage, fault coverage, andoptimal structure of BIST schemes.

  20. Guidelines of the Design of Electropyrotechnic Firing Circuit for Unmanned Flight and Ground Test Projects

    Science.gov (United States)

    Gonzalez, Guillermo A.; Lucy, Melvin H.; Massie, Jeffrey J.

    2013-01-01

    The NASA Langley Research Center, Engineering Directorate, Electronic System Branch, is responsible for providing pyrotechnic support capabilities to Langley Research Center unmanned flight and ground test projects. These capabilities include device selection, procurement, testing, problem solving, firing system design, fabrication and testing; ground support equipment design, fabrication and testing; checkout procedures and procedure?s training to pyro technicians. This technical memorandum will serve as a guideline for the design, fabrication and testing of electropyrotechnic firing systems. The guidelines will discuss the entire process beginning with requirements definition and ending with development and execution.

  1. Performance Evaluation of a Printed Circuit Steam Generator for Integral Reactors: A Feasibility Test

    Energy Technology Data Exchange (ETDEWEB)

    Han, Hun Sik; Kang, Han-Ok; Yoon, Juhyeon; Kim, Young In; Kim, Keung Koo [KAERI, Daejeon (Korea, Republic of); Seo, Jang-won; Choi, Brain [Alfa Laval Korea Ltd., Daejeon (Korea, Republic of)

    2015-05-15

    SMART (System-integrated Modular Advanced ReacTor) is a small-sized integral type pressurized water reactor. It adopts advanced design features such as structural safety improvement, system simplification, and component modularization to achieve highly enhanced safety and improved economics. The design issues related to further safety enhancement and cost reduction have received significant attention to increase its competitiveness in the global small reactor market. For the cost reduction, it is important to design the reactor vessel as small as possible. Thus, it is necessary to reduce the volume of main components such as a steam generator. Its manufacturing processes of the chemical etching and diffusion bonding provide high effectiveness, high compactness, and inherent structural safety under high temperatures and high pressures. Thus, it is expected to be an alternative to the conventional shell and tube type steam generator in SMART. In this paper, simple thermal-hydraulic performance measurement of a small-scale printed circuit steam generator (PCSG) is conducted to investigate the feasibility of applying it to SMART. The simple thermal-hydraulic performance of the PCSG has been experimentally evaluated. A small-scale PCHE is employed to investigate the feasibility of operating it as a steam generator. The performance assessment reveals that the PCSG stably produces superheated steam, and the increased degree of superheat is obtained at lower water flow rate. However, the flow instability is increased with the decrease of the water flow rate. Thus, it is required to apply the orifice design into the cold side plate to suppress the density-wave oscillations. The pressure drops and heat transfer rates increase with the water flow rate.

  2. FPGAs and wavelets on circuit testing based on current signal measurements

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Manolakis, Dimitrios; Bamnios, Georgios; Papakostas, Dimitrios K.; Hatzopoulos, Alkis A.; Hristov, Valentin

    2015-01-01

    The research team designed and implemented a prototype testing system using FPGAs, where test methods for analog and digital (mixed) electronics using wavelets can be incorporated. The prototype has been evaluated and the results are promising. Moreover, the usability and verification of the system’s functionality are presented. The current sensing unit is described in detail. The new automated fault testing system incorporates reconfigurability and parallel processing capabilities.

  3. Entropy Based Test Point Evaluation and Selection Method for Analog Circuit Fault Diagnosis

    Directory of Open Access Journals (Sweden)

    Yuan Gao

    2014-01-01

    Full Text Available By simplifying tolerance problem and treating faulty voltages on different test points as independent variables, integer-coded table technique is proposed to simplify the test point selection process. Usually, simplifying tolerance problem may induce a wrong solution while the independence assumption will result in over conservative result. To address these problems, the tolerance problem is thoroughly considered in this paper, and dependency relationship between different test points is considered at the same time. A heuristic graph search method is proposed to facilitate the test point selection process. First, the information theoretic concept of entropy is used to evaluate the optimality of test point. The entropy is calculated by using the ambiguous sets and faulty voltage distribution, determined by component tolerance. Second, the selected optimal test point is used to expand current graph node by using dependence relationship between the test point and graph node. Simulated results indicate that the proposed method more accurately finds the optimal set of test points than other methods; therefore, it is a good solution to minimize the size of the test point set. To simplify and clarify the proposed method, only catastrophic and some specific parametric faults are discussed in this paper.

  4. An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

    Science.gov (United States)

    Corliss, Walter F., II

    1989-03-01

    The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

  5. Elevated voltage level I.sub.DDQ failure testing of integrated circuits

    Science.gov (United States)

    Righter, Alan W.

    1996-01-01

    Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.

  6. Elevated voltage level I{sub DDQ} failure testing of integrated circuits

    Science.gov (United States)

    Righter, A.W.

    1996-05-21

    Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.

  7. Aqueous corrosion in static capsule tests representing multi-metal assemblies in the hydraulic circuit of Tore Supra

    Energy Technology Data Exchange (ETDEWEB)

    Lipa, M. [Association Euratom-CEA, CEA/DSM/DRFC, Centre de Cadarache, 13108 Saint-Paul-Lez-Durance (France)], E-mail: manfred.lipa@cea.fr; Blanchet, J.; Feron, D. [CEA/DEN/SCCME, Centre de Saclay, 91191 Gif sur Yvette (France); Cellier, F. [AREVA ANP, Centre Technique, 71380 Saint Marcel (France)

    2008-12-15

    Tore supra (TS) in vessel components represent a unique combination of metals in the hydraulic circuit. Different materials, e.g. stainless steel, copper alloys, nickel, etc., were joined together by fusion welding, brazing and friction. Since the operation and baking temperature of all in vessel components has been defined to be set at 230 deg. C/40 bars a special water chemistry of the cooling water loop was suggested in order to prevent eventual water leaks due to corrosion at relative high temperatures and pressures in tubes, bellows, coils and coolant plant ancillary equipments. Following experiences with water chemistry in Pressurised Water Reactors, an all volatile chemical treatment (AVT) has been defined for the cooling water quality of TS. Since then, a simplified static (no fluid circulation) corrosion test program at relatively high temperature and pressure has been performed using capsule-type samples made of above mentioned multi-metal assemblies.

  8. Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

    Science.gov (United States)

    Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

    2018-04-01

    Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

  9. Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

    International Nuclear Information System (INIS)

    Casas, L.M. Jara; Ceresa, D.; Kulis, S.; Christiansen, J.; Francisco, R.; Miryala, S.; Gnani, D.

    2017-01-01

    A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, V t flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

  10. Single event upset test structures for digital CMOS application specific integrated circuits

    International Nuclear Information System (INIS)

    Baze, M.P.; Bartholet, W.G.; Braatz, J.C.; Dao, T.A.

    1993-01-01

    An approach has been developed for the design and utilization of SEU test structures for digital CMOS ASICs. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU response and designing a structure to characterize each response for each category. Critical SEU response parameters extracted from these structures are used to evaluate the SEU hardness of ASIC libraries and predict the hardness of ASIC chips

  11. IRIS (Integrity and Reliability in Integrated Circuits) Test Article Generation (ITAG)

    Science.gov (United States)

    2015-03-31

    directory of generated test configurations. A problem with the Xilinx iMPACT utility interferes with the testing process, so iMPACT is used only to read the...indicate how many tiles are impacted by the interconnect tests. This a reflection of the number of tiles that contain SLICEL and SLICEM interconnect...123 A4 spare NC 36 N3 edram_do_2 I 80 H14 edram_di_8 O 124 B5 TDO O 37 M4 edram_do_1 I 81 H13 padVDD 2.5V 125 A3 coreVDD 1.0V 38 P3 padVDD 2.5V 82

  12. A self-testing method of large analog circuits in electronic embedded systems

    Energy Technology Data Exchange (ETDEWEB)

    Czaja, Z, E-mail: zbczaja@pg.gda.p [Gdansk University of Technology, Faculty of Electronics, Telecommunications and Informatics, Department of Optoelectronics and Electronic Systems, ul. G. Narutowicza 11/12, 80-233 Gdansk (Poland)

    2010-07-01

    A new self-testing method of high-order filters consisting of a chain of first- or second-order filter units of mixed-signal electronic embedded systems controlled by microcontrollers or DSPs is presented in the paper. The main idea of the method bases on the fact that the signal response of the given filter unit is treated as the signal stimulation of the next filter unit. Thanks to this, a simple reconfigurable BIST consisting of only internal devices of the microcontroller controlling the system was obtained.

  13. A self-testing method of large analog circuits in electronic embedded systems

    International Nuclear Information System (INIS)

    Czaja, Z

    2010-01-01

    A new self-testing method of high-order filters consisting of a chain of first- or second-order filter units of mixed-signal electronic embedded systems controlled by microcontrollers or DSPs is presented in the paper. The main idea of the method bases on the fact that the signal response of the given filter unit is treated as the signal stimulation of the next filter unit. Thanks to this, a simple reconfigurable BIST consisting of only internal devices of the microcontroller controlling the system was obtained.

  14. Accelerated test techniques for micro-circuits: Evaluation of high temperature (473 k - 573 K) accelerated life test techniques as effective microcircuit screening methods

    Science.gov (United States)

    Johnson, G. M.

    1976-01-01

    The application of high temperature accelerated test techniques was shown to be an effective method of microcircuit defect screening. Comprehensive microcircuit evaluations and a series of high temperature (473 K to 573 K) life tests demonstrated that a freak or early failure population of surface contaminated devices could be completely screened in thirty two hours of test at an ambient temperature of 523 K. Equivalent screening at 398 K, as prescribed by current Military and NASA specifications, would have required in excess of 1,500 hours of test. All testing was accomplished with a Texas Instruments' 54L10, low power triple-3 input NAND gate manufactured with a titanium- tungsten (Ti-W), Gold (Au) metallization system. A number of design and/or manufacturing anomalies were also noted with the Ti-W, Au metallization system. Further study of the exact nature and cause(s) of these anomalies is recommended prior to the use of microcircuits with Ti-W, Au metallization in long life/high reliability applications. Photomicrographs of tested circuits are included.

  15. Results of water corrosion in static cell tests representing multi-metal assemblies in the hydraulic circuits of Tore Supra

    Energy Technology Data Exchange (ETDEWEB)

    Lipa, M.; Blanchet, J. [Association Euratom-CEA Cadarache, 13 - Saint-Paul-lez-Durance (France). Dept. de Recherches sur la Fusion Controlee; Cellier, F. [Framatome, Centre Technique, 71 - Saint Marcel (France)

    2007-07-01

    Full text of publication follows: Tore supra (TS) has used from the beginning of operation in 1989 actively cooled plasma facing components. Since the operation and baking temperature of all in vessel components has been defined to be up to 230 deg. C at 40 bars, a special water chemistry of the cooling water plant was suggested in order to avoid eventual water leaks due to corrosion (general corrosion, galvanic corrosion, stress corrosion, etc.) at relative high temperatures and pressures in tubes, pipes, bellows, water boxes, coils, etc. From the beginning of TS operation, in vessel components (e.g. wall protection panels, limiters, ergodic divertor coils, neutralisers and diagnostics) represented a unique combination of metals in the hydraulic circuit mainly such as stainless steel, Inconel, CuCrZr, Nickel and Copper. These different materials were joined together by welding (St to St, Inconel to Inconel, CuCrZr to CuCrZr and CuCrZr to St-St via a Ni sleeve adapter), brazing (St-St to Cu and Cu-LSTP), friction (CuCrZr and Cu to St-St), explosion (CuCrZr to St-St) and memory metal junction (Cryo-fit to Cu - only test sample). Following experiences obtained with steam generator tubes of nuclear power plants, a cooling water quality of AVT (all volatile treatment) has been defined based on demineralized water with adjustment of the pH value to about 9.0/ 7.0 (25 deg. C/ 200 deg. C) by addiction of ammoniac, and hydrazine in order to absorb oxygen dissolved in water. At that time, a simplified water corrosion test program has been performed using static (no circulation) test cell samples made of above mentioned TS metal combinations. All test cell samples, prepared and filled with AVT water, were performed at 280 deg. C and 65 bars in an autoclave during 3000 hours. The test cell water temperature has been chosen to be sufficient above the TS component working temperature, in order to accelerate an eventual corrosion process. Generally all above mentioned metal

  16. Results of water corrosion in static cell tests representing multi-metal assemblies in the hydraulic circuits of Tore Supra

    International Nuclear Information System (INIS)

    Lipa, M.; Blanchet, J.

    2007-01-01

    Full text of publication follows: Tore supra (TS) has used from the beginning of operation in 1989 actively cooled plasma facing components. Since the operation and baking temperature of all in vessel components has been defined to be up to 230 deg. C at 40 bars, a special water chemistry of the cooling water plant was suggested in order to avoid eventual water leaks due to corrosion (general corrosion, galvanic corrosion, stress corrosion, etc.) at relative high temperatures and pressures in tubes, pipes, bellows, water boxes, coils, etc. From the beginning of TS operation, in vessel components (e.g. wall protection panels, limiters, ergodic divertor coils, neutralisers and diagnostics) represented a unique combination of metals in the hydraulic circuit mainly such as stainless steel, Inconel, CuCrZr, Nickel and Copper. These different materials were joined together by welding (St to St, Inconel to Inconel, CuCrZr to CuCrZr and CuCrZr to St-St via a Ni sleeve adapter), brazing (St-St to Cu and Cu-LSTP), friction (CuCrZr and Cu to St-St), explosion (CuCrZr to St-St) and memory metal junction (Cryo-fit to Cu - only test sample). Following experiences obtained with steam generator tubes of nuclear power plants, a cooling water quality of AVT (all volatile treatment) has been defined based on demineralized water with adjustment of the pH value to about 9.0/ 7.0 (25 deg. C/ 200 deg. C) by addiction of ammoniac, and hydrazine in order to absorb oxygen dissolved in water. At that time, a simplified water corrosion test program has been performed using static (no circulation) test cell samples made of above mentioned TS metal combinations. All test cell samples, prepared and filled with AVT water, were performed at 280 deg. C and 65 bars in an autoclave during 3000 hours. The test cell water temperature has been chosen to be sufficient above the TS component working temperature, in order to accelerate an eventual corrosion process. Generally all above mentioned metal

  17. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  18. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  19. Results of water corrosion in static cell tests representing multi-metal assemblies in the hydraulic circuits of Tore supra

    Energy Technology Data Exchange (ETDEWEB)

    Lipa, M. [CEA/DSM/DRFC Centre de Cadarache, 13 - Saint-Paul lez Durance (France); Blanchet, J.; Cellier, F. [Framatome, 71 - Saint Marcel (France). Centre Technique

    2007-07-01

    Following experiences obtained with steam generator tubes of nuclear power plants, a cooling water quality of AVT (all volatile treatment) has been defined based on demineralised water with adjustment of the pH value to about 9.0/7.0 (25 C/200 C) by addiction of ammoniac, and hydrazine in order to absorb oxygen dissolved in water. At that time, a simplified water corrosion test program has been performed using static (no circulation) test cell samples made of above mentioned TS metal combinations. All test cell samples, prepared and filled with AVT water, were performed at 280 C and 65 bars in an autoclave during 3000 hours. The test cell water temperature has been chosen to be sufficient above the TS component working temperature, in order to accelerate an eventual corrosion process. Generally all above mentioned metal combinations survived the test campaign without stress corrosion cracking, with the exception of the memory metal junction (creep in Cu) and the bellows made of St-St 316L and Inconel 625 while 316 Ti bellows survived. In contrary to the vacuum brazed Cu-LSTP to St-St samples, some of flame brazed Cu to St-St samples failed either in the braze joint or in the copper structure itself. For comparison, a spot weld of an inflated 316L panel sample, filled voluntary with a caustic solution of pH 11.5 (25 C), failed after 90 h of testing (intergranular cracking at the spot weld), while an identical sample containing AVT water of pH 9.0 (25 C) survived without damage. The results of these tests, performed during 1986 and 1997, have never been published and therefore are presented more in detail in this paper since corrosion in hydraulic circuits is also an issue of ITER. Up to day, the TS cooling water plant operates with an above mentioned water treatment and no water leaks have been detected on in-vessel components originating from water corrosion at high temperature and high pressure. (orig.)

  20. Results of water corrosion in static cell tests representing multi-metal assemblies in the hydraulic circuits of Tore supra

    International Nuclear Information System (INIS)

    Lipa, M.; Blanchet, J.; Cellier, F.

    2007-01-01

    Following experiences obtained with steam generator tubes of nuclear power plants, a cooling water quality of AVT (all volatile treatment) has been defined based on demineralised water with adjustment of the pH value to about 9.0/7.0 (25 C/200 C) by addiction of ammoniac, and hydrazine in order to absorb oxygen dissolved in water. At that time, a simplified water corrosion test program has been performed using static (no circulation) test cell samples made of above mentioned TS metal combinations. All test cell samples, prepared and filled with AVT water, were performed at 280 C and 65 bars in an autoclave during 3000 hours. The test cell water temperature has been chosen to be sufficient above the TS component working temperature, in order to accelerate an eventual corrosion process. Generally all above mentioned metal combinations survived the test campaign without stress corrosion cracking, with the exception of the memory metal junction (creep in Cu) and the bellows made of St-St 316L and Inconel 625 while 316 Ti bellows survived. In contrary to the vacuum brazed Cu-LSTP to St-St samples, some of flame brazed Cu to St-St samples failed either in the braze joint or in the copper structure itself. For comparison, a spot weld of an inflated 316L panel sample, filled voluntary with a caustic solution of pH 11.5 (25 C), failed after 90 h of testing (intergranular cracking at the spot weld), while an identical sample containing AVT water of pH 9.0 (25 C) survived without damage. The results of these tests, performed during 1986 and 1997, have never been published and therefore are presented more in detail in this paper since corrosion in hydraulic circuits is also an issue of ITER. Up to day, the TS cooling water plant operates with an above mentioned water treatment and no water leaks have been detected on in-vessel components originating from water corrosion at high temperature and high pressure. (orig.)

  1. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience

    International Nuclear Information System (INIS)

    Bugnet, H.

    1995-01-01

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs

  2. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  3. Resonance circuits for adiabatic circuits

    Directory of Open Access Journals (Sweden)

    C. Schlachta

    2003-01-01

    Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

  4. Internal short circuit and accelerated rate calorimetry tests of lithium-ion cells: Considerations for methane-air intrinsic safety and explosion proof/flameproof protection methods.

    Science.gov (United States)

    Dubaniewicz, Thomas H; DuCarme, Joseph P

    2016-09-01

    Researchers with the National Institute for Occupational Safety and Health (NIOSH) studied the potential for lithium-ion cell thermal runaway from an internal short circuit in equipment for use in underground coal mines. In this third phase of the study, researchers compared plastic wedge crush-induced internal short circuit tests of selected lithium-ion cells within methane (CH 4 )-air mixtures with accelerated rate calorimetry tests of similar cells. Plastic wedge crush test results with metal oxide lithium-ion cells extracted from intrinsically safe evaluated equipment were mixed, with one cell model igniting the chamber atmosphere while another cell model did not. The two cells models exhibited different internal short circuit behaviors. A lithium iron phosphate (LiFePO 4 ) cell model was tolerant to crush-induced internal short circuits within CH 4 -air, tested under manufacturer recommended charging conditions. Accelerating rate calorimetry tests with similar cells within a nitrogen purged 353-mL chamber produced ignitions that exceeded explosion proof and flameproof enclosure minimum internal pressure design criteria. Ignition pressures within a 20-L chamber with 6.5% CH 4 -air were relatively low, with much larger head space volume and less adiabatic test conditions. The literature indicates that sizeable lithium thionyl chloride (LiSOCl 2 ) primary (non rechargeable) cell ignitions can be especially violent and toxic. Because ignition of an explosive atmosphere is expected within explosion proof or flameproof enclosures, there is a need to consider the potential for an internal explosive atmosphere ignition in combination with a lithium or lithium-ion battery thermal runaway process, and the resulting effects on the enclosure.

  5. Electronic circuit encyclopedia 2

    International Nuclear Information System (INIS)

    Park, Sun Ho

    1992-10-01

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  6. Electronic circuit encyclopedia 2

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sun Ho

    1992-10-15

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  7. The test-retest reliability and criterion validity of a high-intensity, netball-specific circuit test: The Net-Test.

    Science.gov (United States)

    Mungovan, Sean F; Peralta, Paula J; Gass, Gregory C; Scanlan, Aaron T

    2018-04-12

    To examine the test-retest reliability and criterion validity of a high-intensity, netball-specific fitness test. Repeated measures, within-subject design. Eighteen female netball players competing in an international competition completed a trial of the Net-Test, which consists of 14 timed netball-specific movements. Players also completed a series of netball-relevant criterion fitness tests. Ten players completed an additional Net-Test trial one week later to assess test-retest reliability using intraclass correlation coefficient (ICC), typical error of measurement (TEM), and coefficient of variation (CV). The typical error of estimate expressed as CV and Pearson correlations were calculated between each criterion test and Net-Test performance to assess criterion validity. Five movements during the Net-Test displayed moderate ICC (0.84-0.90) and two movements displayed high ICC (0.91-0.93). Seven movements and heart rate taken during the Net-Test held low CV (Test possessed low CV and significant (pTest possesses acceptable reliability for the assessment of netball fitness. Further, the high criterion validity for the Net-Test suggests a range of important netball-specific fitness elements are assessed in combination. Copyright © 2018 Sports Medicine Australia. Published by Elsevier Ltd. All rights reserved.

  8. The permanent NdFeB magnets in the circuits for magnetic filters and the first technological tests

    Czech Academy of Sciences Publication Activity Database

    Žežulka, Václav; Straka, Pavel; Mucha, Pavel

    2005-01-01

    Roč. 78, - (2005), s. 31-39 ISSN 0301-7516 R&D Projects: GA AV ČR IBS3046004 Institutional research plan: CEZ:AV0Z30460519 Keywords : magnetic circuit * magnetic filter * rare earth magnets ( NdFeB ) Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 0.965, year: 2005

  9. Determination of the necessary parameters for a protection insulation disk of sodium circuit weighing system for thermomechanical and small component tests

    International Nuclear Information System (INIS)

    Bloch, M.; Cesar, S.B.G.

    1985-01-01

    The parameters requisited for a plastic disk used as thermal insulation, between feeding tank and weghing system, where the tank is supported are defined. The tank and weghing system are component parts of sodium circuit for thermomechanical and small component tests. During the circuit operation the temperature at tank reaches 600 0 C, however the temperature at weghing system should not reach 50 0 C. The temperature distribution in insulation disk is obtained by finit element method in function of thickness and thermal conductivity of material. The results obtained indicate for thickness E = 32 mm should be K 0 C and for E = 48 mm the thermal conductivity should be K 0 C. In both cases the pressure is σ > 14.5 Kgf/mm 2 . (M.C.K.) [pt

  10. Cell short circuit, preshort signature

    Science.gov (United States)

    Lurie, C.

    1980-01-01

    Short-circuit events observed in ground test simulations of DSCS-3 battery in-orbit operations are analyzed. Voltage signatures appearing in the data preceding the short-circuit event are evaluated. The ground test simulation is briefly described along with performance during reconditioning discharges. Results suggest that a characteristic signature develops prior to a shorting event.

  11. Controllable circuit

    DEFF Research Database (Denmark)

    2010-01-01

    A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...

  12. Circuit Training.

    Science.gov (United States)

    Nelson, Jane B.

    1998-01-01

    Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)

  13. Testing of five methods for the control of zebra mussels in cooling circuits of power plants located on the Moselle river

    International Nuclear Information System (INIS)

    Khalanski, M.

    1993-10-01

    Bioassays have been conducted on site at the Cattenom nuclear power plant located on the Moselle River (in northeast France) to control mussels in auxiliary plant circuits. During the course of a two-year program, five methods were tested: - thermal treatment (33 deg to 40 deg C), - high dosage chlorination (> 50 ppm), - low dosage chlorine dioxide, - potassium salt (KCI > 100 ppm), - one organic compound (Mexel 432). This note presents a comparison of the treatments shown to be most effective, on the basis of technical feasibility, cost and environmental acceptability. (author). 8 figs., 10 refs., 3 tabs

  14. Silicon integrated circuit process

    International Nuclear Information System (INIS)

    Lee, Jong Duck

    1985-12-01

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  15. Silicon integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Jong Duck

    1985-12-15

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  16. A study on the short-circuit test by fault angle control and the recovery characteristics of the fault current limiter using coated conductor

    International Nuclear Information System (INIS)

    Park, D.K.; Kim, Y.J.; Ahn, M.C.; Yang, S.E.; Seok, B.-Y.; Ko, T.K.

    2007-01-01

    Superconducting fault current limiters (SFCLs) have been developed in many countries, and they are expected to be used in the recent electric power systems, because of their great efficiency for operating these power system stably. It is necessary for resistive FCLs to generate resistance immediately and to have a fast recovery characteristic after the fault clearance, because of re-closing operation. Short-circuit tests are performed to obtained current limiting operational and recovery characteristics of the FCL by a fault controller using a power switching device. The power switching device consists of anti-parallel connected thyristors. The fault occurs at the desired angle by controlling the firing angle of thyristors. Resistive SFCLs have different current limiting characteristics with respect to the fault angle in the first swing during the fault. This study deals with the short-circuit characteristic of FCL coils using two different YBCO coated conductors (CCs), 344 and 344s, by controlling the fault angle and experimental studies on the recovery characteristic by a small current flowing through the SFCL after the fault clearance. Tests are performed at various voltages applied to the SFCL in a saturated liquid nitrogen cooling system

  17. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  18. Inside anesthesia breathing circuits: time to reach a set sevoflurane concentration in toddlers and newborns: simulation using a test lung.

    Science.gov (United States)

    Kern, Delphine; Larcher, Claire; Basset, Bertrand; Alacoque, Xavier; Fesseau, Rose; Samii, Kamran; Minville, Vincent; Fourcade, Olivier

    2012-08-01

    We measured the time it takes to reach the desired inspired anesthetic concentration using the Primus (Drägerwerk, AG, Lübeck, Germany) and the Avance (GE Datex-Ohmeda, Munich, Germany) anesthesia machines with toddler and newborn ventilation settings. The time to reach 95% of inspired target sevoflurane concentration was measured during wash-in from 0 to 6 vol% sevoflurane and during wash-out from 6 to 0 vol% with fresh gas flows equal to 1 and 2 times the minute ventilation. The Avance was faster than the Primus (65 seconds [95% confidence interval (CI): 55 to 78] vs 310 seconds [95% CI: 261 to 359]) at 1.5 L/min fresh gas flow, tidal volume of 50 mL, and 30 breaths/min. Times were shorter by the same magnitude at higher fresh gas flows and higher minute ventilation rates. The effect of doubling fresh gas flow was variable and less than expected. The Primus is slower during newborn than toddler ventilation, whereas the Avance's response time was the same for newborn and toddler ventilation. Our data confirm that the time to reach the target-inspired anesthetic concentration depends on breathing circuit volume, fresh gas flow, and minute ventilation.

  19. Comminution circuits for compact itabirites

    Directory of Open Access Journals (Sweden)

    Pedro Ferreira Pinto

    Full Text Available Abstract In the beneficiation of compact Itabirites, crushing and grinding account for major operational and capital costs. As such, the study and development of comminution circuits have a fundamental importance for feasibility and optimization of compact Itabirite beneficiation. This work makes a comparison between comminution circuits for compact Itabirites from the Iron Quadrangle. The circuits developed are: a crushing and ball mill circuit (CB, a SAG mill and ball mill circuit (SAB and a single stage SAG mill circuit (SSSAG. For the SAB circuit, the use of pebble crushing is analyzed (SABC. An industrial circuit for 25 million tons of run of mine was developed for each route from tests on a pilot scale (grinding and industrial scale. The energy consumption obtained for grinding in the pilot tests was compared with that reported by Donda and Bond. The SSSAG route had the lowest energy consumption, 11.8kWh/t and the SAB route had the highest energy consumption, 15.8kWh/t. The CB and SABC routes had a similar energy consumption of 14.4 kWh/t and 14.5 kWh/t respectively.

  20. Model-based control of a fuel cell cooling circuit with automatic software testing; Modellbasierte Steuerung des Kuehlkreislaufes einer Brennstoffzelle mit automatisiertem Test der Software

    Energy Technology Data Exchange (ETDEWEB)

    Schaefer, Sascha

    2012-07-01

    For reconstruction and control of the volume flow in a cooling circuit a fuel cell system is analyzed, and physical models of the fluid temperature and pump volume flow are derived. On this basis, functional models for derivation of software algorithms are presented which enable model-based calculation of the volume flow in a fluid circuit and coolant pump control on the basis of detailed system modelling. The available functions enable complete control and diagnosis of the volume flow. The functional models in Matlab/Simulink will be implemented in a control unit; they are discussed in the context of a software development process. It is stressed that correctness of the functions must be assured, and a trial automation system for functional models of this type is presented. (orig./AKB) [German] Zur Rekonstruktion und Steuerung des Volumenstroms in einem Kuehlkreislauf, wird ein Brennstoffzellensystem analysiert und physikalische Modelle fuer die Fluidtemperatur und den Pumpenvolumenstrom werden hergeleitet. Basierend auf diesen Zusammenhaengen werden Funktionsmodelle zur Ableitung von Softwarealgorithmen vorgestellt. Diese ermoeglichen es den Volumenstrom in einem Fluidkreislauf modellbasiert zu bestimmen bzw. die Kuehlmittelpumpe basierend auf einer detaillierten Systemmodellierung zu steuern. Die zur Verfuegung stehenden Funktionen erlauben eine komplette Regelung, Steuerung und Diagnose des Volumenstroms. Die Funktionsmodelle, in Matlab/Simulink realisiert und zur Ausfuehrung auf einem Steuergeraet vorgesehen, werden im Kontext eines Softwareentwicklungsprozesses diskutiert. Es wird die Notwendigkeit der Sicherstellung der Korrektheit der Funktionen herausgearbeitet und ein Testautomatisierungssystem fuer solche Funktionsmodelle vorgestellt.

  1. LOGIC CIRCUIT

    Science.gov (United States)

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  2. Development of a pulse shape discrimination circuit

    International Nuclear Information System (INIS)

    Ye Bangjiao; Fan Wei; Fan Yangmei; Yu Xiaoqi; Mei Wen; Wang Zhongmin; Han Rongdian; Xiao Zhenxi

    1994-01-01

    A pulse shape discrimination circuit was designed and used in an experiment measuring double-differential cross sections of (n, charged particle) reaction; to identify p, α and γ. The performance of the circuit was tested. With this circuit, excellent identification of p, α and γ was obtained. ((orig.))

  3. Sensors i estratègies de test de circuits digitals CMOS per vigilància del consum

    OpenAIRE

    Rius Vázquez, Josep

    1997-01-01

    El objetivo de la tesis es realizar aportaciones en el campo de las estrategias de test basadas en la vigilancia del consumo quiescente de los circuitos integrados CMOS y de los sensores utilizados para dicho fin (test de corriente o test iddq). Para ello se analiza en primer lugar el estado del arte en el diseño de sensores para el test IDDQ y se extraen criterios para la evaluacion de la calidad de dichos sensores. En la tesis se propone un nuevo tipo de sensor integrado (proportional built...

  4. Collective of mechatronics circuit

    International Nuclear Information System (INIS)

    1987-02-01

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  5. Collective of mechatronics circuit

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1987-02-15

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  6. Circuit parties.

    Science.gov (United States)

    Guzman, R

    2000-03-01

    Circuit parties are extended celebrations, lasting from a day to a week, primarily attended by gay and bisexual men in their thirties and forties. These large-scale dance parties move from city to city and draw thousands of participants. The risks for contracting HIV during these parties include recreational drug use and unsafe sex. Limited data exists on the level of risk at these parties, and participants are skeptical of outside help because of past criticism of these events. Health care and HIV advocates can promote risk-reduction strategies with the cooperation of party planners and can counsel individuals to personally reduce their own risk. To convey the message, HIV prevention workers should emphasize positive and community-centered aspects of the parties, such as taking care of friends and avoiding overdose.

  7. Work and safety managements for on-site installation, commissioning, tests by EU of quench protection circuits for JT-60SA

    International Nuclear Information System (INIS)

    Yamauchi, Kunihito; Okano, Jun; Shimada, Katsuhiro; Ohmori, Yoshikazu; Terakado, Tsunehisa; Matsukawa, Makoto; Koide, Yoshihiko; Kobayashi, Kazuhiro; Ikeda, Yoshitaka; Fukumoto, Masahiro; Kushita, Kouhei N.

    2016-03-01

    The superconducting Satellite Tokamak machine “JT-60SA” under construction in Naka Fusion Institute is an international collaborative project between Japan Atomic Energy Agency (JAEA) as the Implementing Agency (IA) of Japan (JA) and Fusion for Energy (F4E) as the IA of Europe (EU). The contributions for this project are based on the supply of components, and thus European manufacturer shall conduct the installation, commissioning and tests on Naka site under the general supervision by F4E via the designated institute in each EU nation. This means that JAEA had an issue to manage the works by European workers and their safety although there is no direct contract. This report describes the approaches for the work and safety managements, which were agreed with EU after the negotiation, and the completed on-site works for Quench Protection Circuits (QPC) as the first experience for EU in JT-60SA project. (author)

  8. Tester Detects Steady-Short Or Intermittent-Open Circuits

    Science.gov (United States)

    Anderson, Bobby L.

    1990-01-01

    Momentary open circuits or steady short circuits trigger buzzer. Simple, portable, lightweight testing circuit sounds long-duration alarm when it detects steady short circuit or momentary open circuit in coaxial cable or other two-conductor transmission line. Tester sensitive to discontinuities lasting 10 microseconds or longer. Used extensively for detecting intermittent open shorts in accelerometer and extensometer cables. Also used as ordinary buzzer-type continuity checker to detect steady short or open circuits.

  9. Advantages of the synthetic technique for the conduction of short circuit tests to breakers; Ventajas de la tecnica sintetica para realizar pruebas de corto circuito a interruptores

    Energy Technology Data Exchange (ETDEWEB)

    Sibilski, Henry [Instituto Electrotecnico de Varsovia, Varsovia (Poland); Ochoa Vivanco, Ruben [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1987-12-31

    In this article the operational principle of the synthetic test is described; specifically of the current injection circuit in parallel. Its utilization in the research and development of new breaker models and its wide possibilities regarding its testing characteristics is outlined. Likewise the different tests that can be performed by means of the synthetic technique are described. Finally the importance of the synthetic tests is outlined for the development of own technology in the area of interruption equipment and emphasis is made that in industrialized countries this technique is of common practice. [Espanol] En este articulo se describe el principio de operacion de la prueba sintetica; especificamente del circuito de inyeccion de corriente en paralelo. Se destaca su utilizacion en la investigacion y desarrollo de nuevos modelos de interruptores y sus amplias posibilidades en cuanto a caracteristicas de prueba. Asimismo, se describen las diferentes pruebas que pueden realizarse mediante la tecnica sintetica. Por ultimo, se destaca la importancia de las pruebas sinteticas para el desarrollo de tecnologia propia en el area de equipos de interrupcion, y se hace notar que en paises desarrollados, esta tecnica es practica comun.

  10. Advantages of the synthetic technique for the conduction of short circuit tests to breakers; Ventajas de la tecnica sintetica para realizar pruebas de corto circuito a interruptores

    Energy Technology Data Exchange (ETDEWEB)

    Sibilski, Henry [Instituto Electrotecnico de Varsovia, Varsovia (Poland); Ochoa Vivanco, Ruben [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1986-12-31

    In this article the operational principle of the synthetic test is described; specifically of the current injection circuit in parallel. Its utilization in the research and development of new breaker models and its wide possibilities regarding its testing characteristics is outlined. Likewise the different tests that can be performed by means of the synthetic technique are described. Finally the importance of the synthetic tests is outlined for the development of own technology in the area of interruption equipment and emphasis is made that in industrialized countries this technique is of common practice. [Espanol] En este articulo se describe el principio de operacion de la prueba sintetica; especificamente del circuito de inyeccion de corriente en paralelo. Se destaca su utilizacion en la investigacion y desarrollo de nuevos modelos de interruptores y sus amplias posibilidades en cuanto a caracteristicas de prueba. Asimismo, se describen las diferentes pruebas que pueden realizarse mediante la tecnica sintetica. Por ultimo, se destaca la importancia de las pruebas sinteticas para el desarrollo de tecnologia propia en el area de equipos de interrupcion, y se hace notar que en paises desarrollados, esta tecnica es practica comun.

  11. Investigation on the Short-Circuit Behavior of an Aged IGBT Module Through a 6 kA/1.1 kV Non-Destructive Testing Equipment

    DEFF Research Database (Denmark)

    Wu, Rui; Smirnova, Liudmila; Iannuzzo, Francesco

    2014-01-01

    This paper describes the design and development of a 6 kA/1.1 kV non-destructive testing system, which aims for short circuit testing of high-power IGBT modules. An ultralow stray inductance of 37 nH is achieved in the implementation of the tester. An 100 MHz FPGA supervising unit enables 10 ns...

  12. Commutation circuit for an HVDC circuit breaker

    Science.gov (United States)

    Premerlani, William J.

    1981-01-01

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

  13. Development and Field Testing of a Model to Simulate a Demonstration of Le Chatelier's Principle Using the Wheatstone Bridge Circuit.

    Science.gov (United States)

    Vickner, Edward Henry, Jr.

    An electronic simulation model was designed, constructed, and then field tested to determine student opinion of its effectiveness as an instructional aid. The model was designated as the Equilibrium System Simulator (ESS). The model was built on the principle of electrical symmetry applied to the Wheatstone bridge and was constructed from readily…

  14. The Maplin electronic circuits handbook

    CERN Document Server

    Tooley, Michael

    1990-01-01

    The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

  15. An Algorithm of an X-ray Hit Allocation to a Single Pixel in a Cluster and Its Test-Circuit Implementation

    Energy Technology Data Exchange (ETDEWEB)

    Deptuch, G. W. [AGH-UST, Cracow; Fahim, F. [Fermilab; Grybos, P. [AGH-UST, Cracow; Hoff, J. [Fermilab; Maj, P. [AGH-UST, Cracow; Siddons, D. P. [Brookhaven; Kmon, P. [AGH-UST, Cracow; Trimpl, M. [Fermilab; Zimmerman, T. [Fermilab

    2017-05-06

    An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels to one virtual pixel that recovers composite signals and event driven strobes to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of 32×32 pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3 μm X-ray beam. The results of these tests are given in the paper assessing physical implementation of the algorithm.

  16. Study on Oscillations during Short Circuit of MW-Scale IGBT Power Modules by Means of a 6-kA/1.1-kV Nondestructive Testing System

    DEFF Research Database (Denmark)

    Wu, Rui; Diaz Reigosa, Paula; Iannuzzo, Francesco

    2015-01-01

    This paper uses a 6-kA/1.1-kV nondestructive testing system for the analysis of the short-circuit behavior of insulated-gate bipolar transistor (IGBT) power modules. A field-programmable gate array enables the definition of control signals to an accuracy of 10 ns. Multiple 1.7-kV/1-kA IGBT power...... modules displayed severe divergent oscillations, which were subsequently characterized. Experimental tests indicate that nonnegligible circuit stray inductance plays an important role in the divergent oscillations. In addition, the temperature dependence of the transconductance is proposed as an important...

  17. Analog circuit design designing dynamic circuit response

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

  18. Trigger circuit

    International Nuclear Information System (INIS)

    Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.

    1984-01-01

    A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)

  19. Development of data acquisition system for test circuit for the Thermo-Hydraulic Laboratory of CDTN; Desenvolvimento de sistema de aquisicao de dados para circuito de testes do Laboratorio de Termo-Hidraulica do CDTN

    Energy Technology Data Exchange (ETDEWEB)

    Corrade, Thales Jose Rodrigues; Mesquita, Amir Zacarias; Santos, Andre Augusto Campagnole dos, E-mail: thalescorrade@hotmail.com, E-mail: amir@cdtn.br, E-mail: aacs@cdtn.br [Centro de Desenvolvimento da Tecnologia Nuclear (CDTN/CNEN-MG), Belo Horizonte, MG (Brazil). Servico de Tecnologia de Reatores

    2013-07-01

    The Circuit Water-Air (CWA), present in the Laboratorio de Termo-Hidraulica of the Centro de Desenvolvimento da Tecnologia Nuclear/Comissao Nacional de Energia Nuclear (CDTN / CNEN), has been used to evaluate devices present in nuclear fuel elements of a PWR (Pressurized Water Reactor). Currently, a segment of 5x5 beam simulators grids with spacer bars is being tested, serving one of the activities under the Project FUJB / FINEP / INB - 'Development of New Generation of Nuclear Fuel Element '. For the measurements of pressure drop along this beam, a system of data acquisition based on Basic language was created. Although this system is efficient and robust, their resources are very limited. Therefore, it was decided to use the software LabVIEW® implementing a more versatile and modern system. This article describes the new data acquisition system, and presents some results. The main parameters are monitored: temperature, density, dynamic viscosity, Reynolds number. The values of standard deviation, mean and uncertainty of an arbitrary channel are calculated. The system was installed and tested in the circuit under experimental conditions and showed satisfactory results.

  20. Aging evaluation of electrical circuits using the ECCAD [Electrical Circuit Characterization and Diagnostic] system

    International Nuclear Information System (INIS)

    Edson, J.L.

    1988-01-01

    As a part of the Nuclear Regulatory Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport Atomic Power Station Decommissioning Project. The objective of this work was to evaluate the effectiveness of the Electrical Circuit Characterization and Diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

  1. Solid-state circuits

    CERN Document Server

    Pridham, G J

    2013-01-01

    Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

  2. Circuit analysis for dummies

    CERN Document Server

    Santiago, John

    2013-01-01

    Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

  3. Current limiter circuit system

    Science.gov (United States)

    Witcher, Joseph Brandon; Bredemann, Michael V.

    2017-09-05

    An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

  4. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2007-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Each chapter ends with a set

  5. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2011-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Ea

  6. Improvement and qualification of ultrasonic testing of dissimilar welds in the primary circuit of NPPs; Verbesserung und Qualifizierung der Ultraschallpruefung von Mischnaehten im Primaerkreis von KKW

    Energy Technology Data Exchange (ETDEWEB)

    Mitzscherling, Steffen; Barth, Enrico; Homann, Tobias; Prager, Jens [Bundesanstalt fuer Materialforschung und -pruefung (BAM), Berlin (Germany); Goetschel, Sebastian; Weiser, Martin [Konrad-Zuse-Zentrum fuer Informationstechnik Berlin (ZIB) (Germany)

    2017-08-01

    The austenitic and dissimilar welds found in the primary circuit of nuclear power plants are not only extremely relevant to safety but also place very high demands on material testing. In addition to limited accessibility, the macroscopic structure of the weld seam is of paramount importance for ultrasound testing. In order to reliably determine material errors in position and size, the grain orientations and the elastic constants of the anisotropic weld bead structure must be known. The following work steps are used for the imaging representation of possible material defects: First, the weld seam is sounded in order to be able to determine important weld seam parameters, such as, for example, the grain orientation, using an inverse method. On the basis of these parameters, the sound paths are simulated in the next step by means of raytracing (RT). Finally, this RT simulation is assigned the measurement data (A-scans) from different transmitter and receiver positions and superimposed according to the Synthetic Aperature Focusing Technique (SAFT) method. The combination of inverse process, RT and SAFT also ensures a correct visualization of the faults in anisotropic materials. We explain these three methods and present the test arrangement of test specimens with artificial test errors. Measurement data as well as their evaluation are compared with the results of a CIVA simulation. [German] Die im Primaerkreislauf von Kernkraftwerken anzutreffenden austenitischen Schweiss- und Mischnaehte sind nicht nur extrem sicherheitsrelevant, sondern stellen auch sehr hohe Anforderungen an die Materialpruefung. Neben der eingeschraenkten Zugaenglichkeit ist das makroskopische Gefuege der Schweissnaht fuer die Pruefung mit Ultraschall von hoechster Bedeutung. Um Materialfehler zuverlaessig in Position und Groesse bestimmen zu koennen, muessen die Kornorientierungen und die elastischen Konstanten des anisotropen Schweissnahtgefueges bekannt sein. Fuer die bildgebende Darstellung

  7. Laboratory investigations on the corrosion rate of A42 carbon steel in various secondary circuit chemistries representative of hydraulic tests conditions

    International Nuclear Information System (INIS)

    Brussieux, C.; Clinard, M.H.; Guillodo, M.; Alos-Ramos, O.

    2014-01-01

    Ammonia and hydrazine are currently used in the chemical conditioning of steam generators hydraulic test medium to minimize the corrosion rate of carbon steels. However, hydrazine is classified carcinogenic by the European Commission. Significant effort is therefore ongoing to limit its use or even replace it. The results presented in this paper were obtained in the frame of an EDF and AREVA research program on the subject. The corrosion rate of carbon steel in alkaline media with hydrazine was thoroughly studied. However, most studies concern polished coupons and very few data are available for carbon steel covered with oxides layer(s) representative of the layer(s) which can be found in a SG after operation. In this context, the corrosion rate at 25°C of carbon steel pre-oxidized by an autoclave treatment was studied. The tests coupons were submitted to a secondary circuit chemical conditioning treatment in an autoclave at 280°C during 30 days prior to the corrosion rate measurement. The corrosion rates were measured during two months by an electrochemical method (polarization resistance) in test media composed with deionized water, ammonia and hydrazine under an air blanket at 25°C. Similitudes with steam generators' volume/surface ratios were respected during these tests. The coupons submitted to an autoclave treatment were covered by a duplex magnetite layer. After exposure to hydrazine and ageing, the structure of the magnetite layer contains bigger crystallites than after ageing without exposure to hydrazine. The corrosion rate of passive A42 steel exposed to hydrazine was stable and low even after the complete consumption of hydrazine during at least 50 days. The corrosion rate of passive A42 steel not exposed to hydrazine grew steadily to reach the same corrosion rates as polished carbon steels within 50 days. The hydrazine consumption rate observed in the presence of magnetite covered A42 carbon steel was found higher than 1mg/kg/hour. To explain

  8. The short-circuit test results of 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer with fault current limiting function

    International Nuclear Information System (INIS)

    Tomioka, A.; Bohno, T.; Kakami, S.; Isozaki, M.; Watanabe, K.; Toyama, K.; Sugiyama, S.; Konno, M.; Gosho, Y.; Okamoto, H.; Hayashi, H.; Tsutsumi, T.; Iwakuma, M.; Saito, T.; Tanabe, K.; Shiohara, Y.

    2013-01-01

    Highlights: ► We manufactured the 400 kV A-class YBCO model transformer with FCL function. ► Short-circuit test was performed by applying 6.9 kV on primary side. ► The short-circuit current was limited to 174 A for a prospective current of 559 A. ► It agreed with the design and we also confirmed the I c did not degrade. ► The results suggest the possibility to design YBCO transformers with FCL function. -- Abstract: We are developing an elemental technology for 66/6.9 kV 20 MVA-class superconducting power transformer with fault current limiting function. In order to obtain the characteristics of YBCO conductor when the AC over current supplied to the conductor, the model coils were manufactured with YBCO tapes and tested. Based on these results, we manufactured the 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer with fault current limiting function and performed short-circuit test. At the 0.25 s after short-circuit, the short-circuit current of primary winding was limited to about 174 A for a prospective current of 559 A. It was consistent with the design. The I–V characteristics of the winding did not change before and after the test. We consider the model transformer to be able to withstand AC over-current with the function of current limiting. The results suggest the possibility to design YBCO superconducting transformers with fault current limiting function for practical power grid

  9. A new approach of optimization procedure for superconducting integrated circuits

    International Nuclear Information System (INIS)

    Saitoh, K.; Soutome, Y.; Tarutani, Y.; Takagi, K.

    1999-01-01

    We have developed and tested a new circuit simulation procedure for superconducting integrated circuits which can be used to optimize circuit parameters. This method reveals a stable operation region in the circuit parameter space in connection with the global bias margin by means of a contour plot of the global bias margin versus the circuit parameters. An optimal set of parameters with margins larger than these of the initial values has been found in the stable region. (author)

  10. Intuitive analog circuit design

    CERN Document Server

    Thompson, Marc

    2013-01-01

    Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

  11. The circuit designer's companion

    CERN Document Server

    Williams, Tim

    1991-01-01

    The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

  12. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1972-01-01

    Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

  13. Electrical Circuits and Water Analogies

    Science.gov (United States)

    Smith, Frederick A.; Wilson, Jerry D.

    1974-01-01

    Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

  14. Microcontroller based Integrated Circuit Tester

    OpenAIRE

    Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

    2015-01-01

    The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

  15. Electric circuits essentials

    CERN Document Server

    REA, Editors of

    2012-01-01

    REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

  16. Piezoelectric drive circuit

    Science.gov (United States)

    Treu, C.A. Jr.

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

  17. Short-circuit logic

    NARCIS (Netherlands)

    Bergstra, J.A.; Ponse, A.

    2010-01-01

    Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of

  18. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2011-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  19. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2010-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  20. F-Paris: integrated electronic circuits [Tender

    CERN Multimedia

    2003-01-01

    "Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

  1. Multiplication circuit for particle identification

    International Nuclear Information System (INIS)

    Gerlier, Jean

    1962-01-01

    After having commented some characteristics of the particles present in a cyclotron, and their interactions, this report addresses the development and the implementation of a method and a device for selecting and counting particles. The author presents the principle and existing techniques of selection. In comparison with an existing device, the proportional counter and the scintillator are replaced by junctions: a surface barrier type junction (a silicon N layer with a very thin oxygen layer playing the role of the P layer), and lithium-based junction (a silicon P type layer made intrinsic by migration of lithium). The author then describes the developed circuit and assembly (background of the choice of a multiplication circuit), and their operation. In the next part, he presents the performed tests and discuses the obtained results. He finally outlines the benefits of the herein presented circuit [fr

  2. Feedback in analog circuits

    CERN Document Server

    Ochoa, Agustin

    2016-01-01

    This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

  3. Physically based arc-circuit interaction

    International Nuclear Information System (INIS)

    Zhong-Lie, L.

    1984-01-01

    An integral arc model is extended to study the interaction of the gas blast arc with the test circuit in this paper. The deformation in the waveshapes of arc current and voltage around the current zero has been formulated to first approximation by using a simple model of arc voltage based on the arc core energy conservation. By supplementing with the time scale for the radiation, the time rates of arc processes were amended. Both the contributions of various arc processes and the influence of circuit parameters to the arc-circuit interaction have been estimated by this theory. Analysis generated a new method of calculating test circuit parameters which improves the accurate simulation of arc-circuit interaction. The new method agrees with the published experimental results

  4. Model Comparison Exercise Circuit Training Game and Circuit Ladder Drills to Improve Agility and Speed

    Directory of Open Access Journals (Sweden)

    Susilaturochman Hendrawan Koestanto

    2017-11-01

    Full Text Available The purpose of this study was to compare: (1 the effect of circuit training game and circuit ladder drill for the agility; (2 the effect of circuit training game and circuit ladder drill on speed; (3 the difference effect of circuit training game and circuit ladder drill for the speed (4 the difference effect of circuit training game and circuit ladder drill on agility. The type of this research was quantitative with quasi-experimental methods. The design of this research was Factorial Design, with analysing data using ANOVA. The process of data collection was done by using 30 meters sprint speed test and shuttle run test during the pretest and posttest. Furthermore, the data was analyzed by using SPSS 22.0 series. Result: The circuit training game exercise program and circuit ladder drill were significant to increase agility and speed (sig 0.000 < α = 0.005 Group I, II, III had significant differences (sig 0.000 < α = 0.005. The mean of increase in speed of group I = 0.20 seconds, group II = 0.31 seconds, and group III = 0.11 seconds. The average increase agility to group I = 0.34 seconds group II = 0.60 seconds, group III = 0.13 seconds. Based on the analysis above, it could be concluded that there was an increase in the speed and agility of each group after being given a training.

  5. Electric circuits and signals

    CERN Document Server

    Sabah, Nassir H

    2007-01-01

    Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...

  6. [Shunt and short circuit].

    Science.gov (United States)

    Rangel-Abundis, Alberto

    2006-01-01

    Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

  7. Analog circuits cookbook

    CERN Document Server

    Hickman, Ian

    2013-01-01

    Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.

  8. Analog circuit design

    CERN Document Server

    Dobkin, Bob

    2012-01-01

    Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

  9. Regenerative feedback resonant circuit

    Science.gov (United States)

    Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

    2014-09-02

    A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

  10. Analysis of the treatment of plastic from electrical and electronic waste in the Republic of Serbia and the testing of the recycling potential of non-metallic fractions of printed circuit boards

    Directory of Open Access Journals (Sweden)

    Vučinić Aleksandra S.

    2017-01-01

    Full Text Available This paper presents the analysis of the quantity of plastic and waste printed circuit boards obtained after the mechanical treatment of electrical and electronic waste (E-waste in the Republic of Serbia, as well as the recycling of non-metallic fractions of waste printed circuit boards. The aim is to analyze the obtained recycled material and recommendation for possible application of recyclables. The data on the quantities and treatment of plastics and printed circuit boards obtained after the mechanical treatment of WEEE, were gained through questionnaires sent to the operators who treat this type of waste. The results of the questionnaire analysis showed that in 2014 the dismantling of E-waste isolated 1,870.95 t of plastic and 499.85 t of printed circuit boards. In the Republic of Serbia, E-waste recycling is performed exclusively by using mechanical methods. Mechanical methods consist of primary crushing and separation of the materials which have a utility value as secondary raw materials, from the components and materials that have hazardous properties. Respect to that, the recycling of printed circuit boards using some of the metallurgical processes with the aim of extracting copper, precious metals and non-metallic fraction is completely absent, and the circuit boards are exported as a whole. Given the number of printed circuit boards obtained by E-waste dismantling, and the fact that from an economic point of view, hydrometallurgical methods are very suitable technological solutions in the case of a smaller capacity, there is a possibility for establishing the facilities in the Republic of Serbia for the hydrometallurgical treatment that could be used for metals extraction, and non-metallic fractions, which also have their own value. Printed circuit boards granulate obtained after the mechanical pretreatment and the selective removal of metals by hydrometallurgical processes was used for the testing of the recycling potential

  11. The design of charge measurement circuit of MWPC

    International Nuclear Information System (INIS)

    Guan Xiaolei; Xiang Haisheng; Sheng Huayi; Zhao Yubin; Zhao Pingping; Zhang Hongyu; Jiang Xiaoshan; Zhao Jingwei; Zhao Dongxu

    2010-01-01

    It introduces the design of charge measurement (MQ) circuit of MWPC, including how MQ works in the whole MWPC readout electronic system, the architecture of MQ circuit, and the logic and algorithm design of FPGA. MQ circuit can also be applied to readout systems for other detectors. The test results in different working modes are provided. (authors)

  12. 30 CFR 56.6402 - Deenergized circuits near detonators.

    Science.gov (United States)

    2010-07-01

    ... Electric Blasting § 56.6402 Deenergized circuits near detonators. Electrical distribution circuits within 50 feet of electric detonators at the blast site shall be deenergized. Such circuits need not be deenergized between 25 to 50 feet of the electric detonators if stray current tests, conducted as frequently...

  13. 30 CFR 57.6402 - Deenergized circuits near detonators.

    Science.gov (United States)

    2010-07-01

    ... Electric Blasting-Surface and Underground § 57.6402 Deenergized circuits near detonators. Electrical distribution circuits within 50 feet of electric detonators at the blast site shall be deenergized. Such circuits need not be deenergized between 25 to 50 feet of the electric detonators if stray current tests...

  14. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  15. Timergenerator circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

  16. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1968-01-01

    Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

  17. Maximum Acceleration Recording Circuit

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1995-01-01

    Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

  18. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  19. Circuits and filters handbook

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

  20. Security electronics circuits manual

    CERN Document Server

    MARSTON, R M

    1998-01-01

    Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

  1. Aging evaluation of electrical circuits using the ECCAD system

    International Nuclear Information System (INIS)

    Edson, J.L.

    1988-01-01

    As a part of the Nuclear Regulator Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport atomic power station decommissioning project. The objective of this work was to evaluate the effectiveness of the electrical circuit characterization and diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

  2. Energy-efficient neuron, synapse and STDP integrated circuits.

    Science.gov (United States)

    Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

    2012-06-01

    Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

  3. Memristor Circuits and Systems

    KAUST Repository

    Zidan, Mohammed A.

    2015-05-01

    Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort. In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results. Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for

  4. Circuits on Cylinders

    DEFF Research Database (Denmark)

    Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V

    2006-01-01

    We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching pro...

  5. Approximate circuits for increased reliability

    Science.gov (United States)

    Hamlet, Jason R.; Mayo, Jackson R.

    2015-08-18

    Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

  6. Troubleshooting analog circuits

    CERN Document Server

    Pease, Robert A

    1991-01-01

    Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other

  7. Modern TTL circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

  8. Circuit analysis with Multisim

    CERN Document Server

    Baez-Lopez, David

    2011-01-01

    This book is concerned with circuit simulation using National Instruments Multisim. It focuses on the use and comprehension of the working techniques for electrical and electronic circuit simulation. The first chapters are devoted to basic circuit analysis.It starts by describing in detail how to perform a DC analysis using only resistors and independent and controlled sources. Then, it introduces capacitors and inductors to make a transient analysis. In the case of transient analysis, it is possible to have an initial condition either in the capacitor voltage or in the inductor current, or bo

  9. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.

  10. 'Speedy' superconducting circuits

    International Nuclear Information System (INIS)

    Holst, T.

    1994-01-01

    The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

  11. Integrated circuit implementation of fuzzy controllers

    OpenAIRE

    Huertas Díaz, José Luis; Sánchez Solano, Santiago; Baturone Castillo, María Iluminada; Barriga Barros, Ángel

    1996-01-01

    This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno’s method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these...

  12. The transfer function method for the evaluation of short-circuit tests and on-site diagnostics of power transformers; Die Uebertragungsfunktion als Methode zur Beurteilung der Stosskurzschlusspruefung und Vor-Ort-Isolationsdiagnose

    Energy Technology Data Exchange (ETDEWEB)

    Christian, J.; Feser, K. [Stuttgart Univ. (Germany). Inst. fuer Energieuebertragung und Hochspannungstechnik; Leibfried, T. [Siemens AG, Nuernberg (Germany). Geschaeftsgebiet Leistungstransformatoren; Jaeggi, F. [Aare-Tessin AG fuer Elektrizitaet, Olten (Switzerland)

    1999-03-22

    A short circuit test according to IEC 76-5 was performed on a 125 MVA, 245 kV/53 kV power transformer from the Siemens factory in Nuremberg at the Kema high power laboratory (Arnhem, Netherlands) in March 1997. Thereby, the transfer function method was examined as an additional method for evaluating the short-circuit test. The visual inspection of the transformer after returning to the Nuremberg factory carried out by engineers from Atel and Siemens and representatives of Kema showed no changes of the core and coil assembly. At the Flumenthal substation a second transformer of the same type was installed. Before commissioning, the transfer functions of both transformers have been measured. These measurements provide essential information concerning the comparability of measurements from different transformers and are the basis for measurements to be carried out in the future. (orig.) [Deutsch] Im Maerz 1997 wurde ein 125-MVA-Leistungstranformator aus dem Siemens Transformatorenwerk Nuernberg im Hochleistungslabor der Kema, Arnheim einer Stosskurzschlusspruefung unterzogen. Dabei wurde die Analyse der Uebertragungsfunktion des Transformators als zusaetzliche Methode zur Beurteilung der Stosskurzschlusspruefung untersucht. Der Aktivteil wurde danach im Herstellerwerk begutachtet. Dabei ergaben sich keine Beanstandungen. Im Umspannwerk Flumenthal wurde ein zweiter baugleicher Transformator installiert. Vor der Inbetriebnahme wurden zusaetzliche Vergleichsmessungen an den zwei baugleichen Transformatoren durchgefuehrt. (orig.)

  13. Receiver Gain Modulation Circuit

    Science.gov (United States)

    Jones, Hollis; Racette, Paul; Walker, David; Gu, Dazhen

    2011-01-01

    A receiver gain modulation circuit (RGMC) was developed that modulates the power gain of the output of a radiometer receiver with a test signal. As the radiometer receiver switches between calibration noise references, the test signal is mixed with the calibrated noise and thus produces an ensemble set of measurements from which ensemble statistical analysis can be used to extract statistical information about the test signal. The RGMC is an enabling technology of the ensemble detector. As a key component for achieving ensemble detection and analysis, the RGMC has broad aeronautical and space applications. The RGMC can be used to test and develop new calibration algorithms, for example, to detect gain anomalies, and/or correct for slow drifts that affect climate-quality measurements over an accelerated time scale. A generalized approach to analyzing radiometer system designs yields a mathematical treatment of noise reference measurements in calibration algorithms. By treating the measurements from the different noise references as ensemble samples of the receiver state, i.e. receiver gain, a quantitative description of the non-stationary properties of the underlying receiver fluctuations can be derived. Excellent agreement has been obtained between model calculations and radiometric measurements. The mathematical formulation is equivalent to modulating the gain of a stable receiver with an externally generated signal and is the basis for ensemble detection and analysis (EDA). The concept of generating ensemble data sets using an ensemble detector is similar to the ensemble data sets generated as part of ensemble empirical mode decomposition (EEMD) with exception of a key distinguishing factor. EEMD adds noise to the signal under study whereas EDA mixes the signal with calibrated noise. It is mixing with calibrated noise that permits the measurement of temporal-functional variability of uncertainty in the underlying process. The RGMC permits the evaluation of EDA by

  14. Analogue circuits simulation

    Energy Technology Data Exchange (ETDEWEB)

    Mendo, C

    1988-09-01

    Most analogue simulators have evolved from SPICE. The history and description of SPICE-like simulators are given. From a mathematical formulation of the electronic circuit the following analysis are possible: DC, AC, transient, noise, distortion, Worst Case and Statistical.

  15. Printed circuit for ATLAS

    CERN Multimedia

    Laurent Guiraud

    1999-01-01

    A printed circuit board made by scientists in the ATLAS collaboration for the transition radiaton tracker (TRT). This will read data produced when a high energy particle crosses the boundary between two materials with different electrical properties.

  16. Magnonic logic circuits

    International Nuclear Information System (INIS)

    Khitun, Alexander; Bao Mingqiang; Wang, Kang L

    2010-01-01

    We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

  17. Peak reading detector circuit

    International Nuclear Information System (INIS)

    Courtin, E.; Grund, K.; Traub, S.; Zeeb, H.

    1975-01-01

    The peak reading detector circuit serves for picking up the instants during which peaks of a given polarity occur in sequences of signals in which the extreme values, their time intervals, and the curve shape of the signals vary. The signal sequences appear in measuring the foetal heart beat frequence from amplitude-modulated ultrasonic, electrocardiagram, and blood pressure signals. In order to prevent undesired emission of output signals from, e. g., disturbing intermediate extreme values, the circuit consists of the series connections of a circuit to simulate an ideal diode, a strong unit, a discriminator for the direction of charging current, a time-delay circuit, and an electronic switch lying in the decharging circuit of the storage unit. The time-delay circuit thereby causes storing of a preliminary maximum value being used only after a certain time delay for the emission of the output signal. If a larger extreme value occurs during the delay time the preliminary maximum value is cleared and the delay time starts running anew. (DG/PB) [de

  18. Effects of smoke on functional circuits

    International Nuclear Information System (INIS)

    Tanaka, T.J.

    1997-10-01

    Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs

  19. Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

    Science.gov (United States)

    Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

    2015-01-01

    Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

  20. Project Circuits in a Basic Electric Circuits Course

    Science.gov (United States)

    Becker, James P.; Plumb, Carolyn; Revia, Richard A.

    2014-01-01

    The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

  1. Coplanar strips for Josephson voltage standard circuits

    International Nuclear Information System (INIS)

    Schubert, M.; May, T.; Wende, G.; Fritzsch, L.; Meyer, H.-G.

    2001-01-01

    We present a microwave circuit for Josephson voltage standards. Here, the Josephson junctions are integrated in a microwave transmission line designed as coplanar strips (CPS). The new layout offers the possibility of achieving a higher scale of integration and to considerably simplify the fabrication technology. The characteristic impedance of the CPS is about 50 Ω, and this should be of interest for programmable Josephson voltage standard circuits with SNS or SINIS junctions. To demonstrate the function of the microwave circuit design, conventional 10 V Josephson voltage standard circuits with 17000 Nb/AlO x /Nb junctions were prepared and tested. Stable Shapiro steps at the 10 V level were generated. Furthermore, arrays of 1400 SINIS junctions in this microwave layout exhibited first-order Shapiro steps. Copyright 2001 American Institute of Physics

  2. Integrated circuit design using design automation

    International Nuclear Information System (INIS)

    Gwyn, C.W.

    1976-09-01

    Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

  3. Low latency asynchronous interface circuits

    Science.gov (United States)

    Sadowski, Greg

    2017-06-20

    In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

  4. Junction and circuit fabrication

    International Nuclear Information System (INIS)

    Jackel, L.D.

    1980-01-01

    Great strides have been made in Josephson junction fabrication in the four years since the first IC SQUID meeting. Advances in lithography have allowed the production of devices with planar dimensions as small as a few hundred angstroms. Improved technology has provided ultra-high sensitivity SQUIDS, high-efficiency low-noise mixers, and complex integrated circuits. This review highlights some of the new fabrication procedures. The review consists of three parts. Part 1 is a short summary of the requirements on junctions for various applications. Part 2 reviews intergrated circuit fabrication, including tunnel junction logic circuits made at IBM and Bell Labs, and microbridge radiation sources made at SUNY at Stony Brook. Part 3 describes new junction fabrication techniques, the major emphasis of this review. This part includes a discussion of small oxide-barrier tunnel junctions, semiconductor barrier junctions, and microbridge junctions. Part 3 concludes by considering very fine lithography and limitations to miniaturization. (orig.)

  5. Small circuits for cryptography.

    Energy Technology Data Exchange (ETDEWEB)

    Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

    2005-10-01

    This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

  6. Primer printed circuit boards

    CERN Document Server

    Argyle, Andrew

    2009-01-01

    Step-by-step instructions for making your own PCBs at home. Making your own printed circuit board (PCB) might seem a daunting task, but once you master the steps, it's easy to attain professional-looking results. Printed circuit boards, which connect chips and other components, are what make almost all modern electronic devices possible. PCBs are made from sheets of fiberglass clad with copper, usually in multiplelayers. Cut a computer motherboard in two, for instance, and you'll often see five or more differently patterned layers. Making boards at home is relatively easy

  7. Circuit design for reliability

    CERN Document Server

    Cao, Yu; Wirth, Gilson

    2015-01-01

    This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

  8. Electronic circuits fundamentals & applications

    CERN Document Server

    Tooley, Mike

    2015-01-01

    Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The

  9. Development of electron beam deflection circuit

    International Nuclear Information System (INIS)

    Leo Kwee Wah; Lojius Lombigit; Abu Bakar Ghazali; Azaman

    2007-01-01

    This paper describes a development of a power supply circuit to deflect and move the electron beam across the window of the Baby electron beam machine. It comprises a discussion of circuit design, its assembly and the test results. A variety of input and output conditions have been tested and it was found that the design is capable to supply 1.0 A with 50Hz on X-axis coil and 0.4A with 500Hz on Y-axis coil. (Author)

  10. Development of large-scale thyristor dc circuit breaker

    International Nuclear Information System (INIS)

    Kobayashi, S.; Tanoue, Y.; Ikegame, H.; Matushita, T.; Sato, Y.

    1981-01-01

    A study for developing a thyristor dc circuit breaker that is applicable to the Tokamak device for engineering feasibility is presented. The design and test of a unit circuit breaker consisting of 4kV-3kA thyristors connected 2 in series and 12 in parallel are described. And based on the results a 50kV-24kA thyristor dc circuit breaker is conceptually designed

  11. ESD analog circuits and design

    CERN Document Server

    Voldman, Steven H

    2014-01-01

    A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

  12. Unstable oscillators based hyperchaotic circuit

    DEFF Research Database (Denmark)

    Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.

    1999-01-01

    A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...

  13. Electronic Circuit Analysis Language (ECAL)

    Science.gov (United States)

    Chenghang, C.

    1983-03-01

    The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

  14. An integrated circuit switch

    Science.gov (United States)

    Bonin, E. L.

    1969-01-01

    Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

  15. Automatic sweep circuit

    International Nuclear Information System (INIS)

    Keefe, D.J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input is described. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found

  16. Automatic sweep circuit

    Science.gov (United States)

    Keefe, Donald J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

  17. "Printed-circuit" rectenna

    Science.gov (United States)

    Dickinson, R. M.

    1977-01-01

    Rectifying antenna is less bulky structure for absorbing transmitted microwave power and converting it into electrical current. Printed-circuit approach, using microstrip technology and circularly polarized antenna, makes polarization orientation unimportant and allows much smaller arrays for given performance. Innovation is particularly useful with proposed electric vehicles powered by beam microwaves.

  18. Het onzichtbare circuit

    NARCIS (Netherlands)

    Nauta, Bram

    2013-01-01

    De chip, of geïntegreerde schakeling, heeft in een razend tempo ons leven ingrijpend veranderd. Het lijkt zo vanzelfsprekend dat er weer een nieuwe generatie smartphones, tablets of computers is. Maar dat is het niet. Prof.dr.ir. Bram Nauta, hoogleraar Integrated Circuit Design, laat in zijn rede

  19. Voltage regulating circuit

    NARCIS (Netherlands)

    2005-01-01

    A voltage regulating circuit comprising a rectifier (2) for receiving an AC voltage (Vmains) and for generating a rectified AC voltage (vrec), and a capacitor (3) connected in parallel with said rectified AC voltage for providing a DC voltage (VDC) over a load (5), characterized by a unidirectional

  20. Streaming Reduction Circuit

    NARCIS (Netherlands)

    Gerards, Marco Egbertus Theodorus; Kuper, Jan; Kokkeler, Andre B.J.; Molenkamp, Egbert

    2009-01-01

    Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths

  1. A Magnetic Circuit Demonstration.

    Science.gov (United States)

    Vanderkooy, John; Lowe, June

    1995-01-01

    Presents a demonstration designed to illustrate Faraday's, Ampere's, and Lenz's laws and to reinforce the concepts through the analysis of a two-loop magnetic circuit. Can be made dramatic and challenging for sophisticated students but is suitable for an introductory course in electricity and magnetism. (JRH)

  2. Evaluation of tests for coastdown of reactor coolant flow and measure of primary circuit flow of Angra-1 nuclear power plant

    International Nuclear Information System (INIS)

    Galetti, M.R.S.; Camargo, C.T.M.; Pontedeiro, A.C.

    1987-05-01

    The Angra 1 Nuclear Power Plant first reload license was issued after several technical discussions among CNEN, FURNAS and KWU. During the license process CNEN has established that the plant could return to anormal operation if the requirements described in the letter CNEN-DExL-C 06/86 were satisfied. The requirements according to the CNEN Transient and Thermohydraulic Group Analysis were to do again the following tests: 'Primary Flow Measurement' to check if the excess flow measured in the first cycle was held; and Pump Coastdown' to check if the Westinghouse and KWU fuel elements are thermo-hydraulicaly compatibles during transients. The mixed core must keep at least the same safety margin presented on Angra 1 FSAR for the original core. The tests and the analysis of results are described. (Author) [pt

  3. The LMT circuit and SPICE

    DEFF Research Database (Denmark)

    Lindberg, Erik; Murali, K.; Tamacevicius, Arunas

    2006-01-01

    The state equations of the LMT circuit are modeled as a dedicated analogue computer circuit and solved by means of PSpice. The nonlinear part of the system is studied. Problems with the PSpice program are presented....

  4. Resistor Combinations for Parallel Circuits.

    Science.gov (United States)

    McTernan, James P.

    1978-01-01

    To help simplify both teaching and learning of parallel circuits, a high school electricity/electronics teacher presents and illustrates the use of tables of values for parallel resistive circuits in which total resistances are whole numbers. (MF)

  5. Detecting short circuits during assembly

    Science.gov (United States)

    Deboo, G. J.

    1980-01-01

    Detector circuit identifies shorts between bus bars of electronic equipment being wired. Detector sounds alarm and indicates which planes are shorted. Power and ground bus bars are scanned continuously until short circuit occurs.

  6. BR-5 primary circuit decontamination

    International Nuclear Information System (INIS)

    Efimov, I.A.; Nikulin, M.P.; Smirnov-Averin, A.P.; Tymosh, B.S.; Shereshkov, V.S.

    1976-01-01

    Results and methodology of steam-water and acid decontamination of the primary coolant circuit SBR-5 reactor in 1971 are discussed. Regeneration process in a cold trap of the primary coolant circuit is discussed

  7. Implementation of chaotic secure communication systems based on OPA circuits

    International Nuclear Information System (INIS)

    Huang, C.-K.; Tsay, S.-C.; Wu, Y.-R.

    2005-01-01

    In this paper, we proposed a novel three-order autonomous circuit to construct a chaotic circuit with double scroll characteristic. The design idea is to use RLC elements and a nonlinear resistor. The one of salient features of the chaotic circuit is that the circuit with two flexible breakpoints of nonlinear element, and the advantage of the flexible breakpoint is that it increased complexity of the dynamical performance. Here, if we take a large and suitable breakpoint value, then the chaotic state can masking a large input signal in the circuit. Furthermore, we proposed a secure communication hyperchaotic system based on the proposed chaotic circuits, where the chaotic communication system is constituted by a chaotic transmitter and a chaotic receiver. To achieve the synchronization between the transmitter and the receiver, we are using a suitable Lyapunov function and Lyapunov theorem to design the feedback control gain. Thus, the transmitting message masked by chaotic state in the transmitter can be guaranteed to perfectly recover in the receiver. To achieve the systems performance, some basic components containing OPA, resistor and capacitor elements are used to implement the proposed communication scheme. From the viewpoints of circuit implementation, this proposed chaotic circuit is superior to the Chua chaotic circuits. Finally, the test results containing simulation and the circuit measurement are shown to demonstrate that the proposed method is correct and feasible

  8. MOS voltage automatic tuning circuit

    OpenAIRE

    李, 田茂; 中田, 辰則; 松本, 寛樹

    2004-01-01

    Abstract ###Automatic tuning circuit adjusts frequency performance to compensate for the process variation. Phase locked ###loop (PLL) is a suitable oscillator for the integrated circuit. It is a feedback system that compares the input ###phase with the output phase. It can make the output frequency equal to the input frequency. In this paper, PLL ###fomed of MOSFET's is presented.The presented circuit consists of XOR circuit, Low-pass filter and Relaxation ###Oscillator. On PSPICE simulation...

  9. Behavioral synthesis of asynchronous circuits

    DEFF Research Database (Denmark)

    Nielsen, Sune Fallgaard

    2005-01-01

    This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...

  10. Selected collection of circuit drawings

    International Nuclear Information System (INIS)

    1977-01-01

    The many electronics circuits have been constracted in the Electronics Shop for use in nuclear experiments or other purposes of this Institute. The types of these circuits amount to about 500 items in total since 1968. This report describes the electronics circuit diagrams selected from this collection. The circuit details are not presented in this report, because these are already been published in the other technical reports. (auth.)

  11. Diode, transistor & fet circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

  12. Substrate Effects in Wideband SiGe HBT Mixer Circuits

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Vidkjær, Jens; Krozer, Viktor

    2005-01-01

    are also applied to predict short distance substrate coupling effects. Simulation results using extracted equivalent circuit models and substrate coupling networks are compared with experimental results obtained on a wideband mixer circuit implemented in a 0.35 μm, 60 GHz ft SiGe HBT BiCMOS process.......In this paper, the influence from substrate effects on the performance of wideband SiGe HBT mixer circuits is investigated. Equivalent circuit models including substrate networks are extracted from on-wafer test structures and compared with electromagnetic simulations. Electromagnetic simulations...

  13. Short-circuit experiments on a high Tc-superconducting cable conductor

    DEFF Research Database (Denmark)

    Tønnesen, Ole; Jensen, E.H.; Traholt, C.

    2002-01-01

    A high temperature superconductor (HTS) cable conductor (CC) with a critical current of 2.1 kA was tested over a range of short-circuit currents up to 20 kA. The duration of the short-circuit currents is 1 s. Between each short-circuit test the critical current of the HTS CC was measured in order...

  14. Electrical circuit theory and technology

    CERN Document Server

    Bird, John

    2014-01-01

    This much-loved textbook explains the principles of electrical circuit theory and technology so that students of electrical and mechanical engineering can master the subject. Real-world situations and engineering examples put the theory into context. The inclusion of worked problems with solutions help you to learn and further problems then allow you to test and confirm you have fully understood each subject. In total the book contains 800 worked problems, 1000 further problems and 14 revision tests with answers online. This an ideal text for foundation and undergraduate degree students and those on upper level vocational engineering courses, in particular electrical and mechanical. It provides a sound understanding of the knowledge required by technicians in fields such as electrical engineering, electronics and telecommunications. This edition has been updated with developments in key areas such as semiconductors, transistors, and fuel cells, along with brand new material on ABCD parameters and Fourier's An...

  15. Analysis of Bernstein's factorization circuit

    NARCIS (Netherlands)

    Lenstra, A.K.; Shamir, A.; Tomlinson, J.; Tromer, E.; Zheng, Y.

    2002-01-01

    In [1], Bernstein proposed a circuit-based implementation of the matrix step of the number field sieve factorization algorithm. These circuits offer an asymptotic cost reduction under the measure "construction cost x run time". We evaluate the cost of these circuits, in agreement with [1], but argue

  16. High voltage MOSFET switching circuit

    Science.gov (United States)

    McEwan, Thomas E.

    1994-01-01

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  17. Neuromorphic Silicon Neuron Circuits

    Science.gov (United States)

    Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

    2011-01-01

    Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

  18. Neuromorphic silicon neuron circuits

    Directory of Open Access Journals (Sweden)

    Giacomo eIndiveri

    2011-05-01

    Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

  19. An Unsolved Electric Circuit: A Common Misconception

    Science.gov (United States)

    Harsha, N. R. Sree; Sreedevi, A.; Prakash, Anupama

    2015-01-01

    Despite a number of theories in circuit analysis, little is known about the behaviour of ideal equal voltage sources in parallel, connected across a resistive load. We neither have any theory that can predict the voltage source that provides the load current, nor is there any method to test it experimentally. In a series of experiments performed…

  20. Developing 300°C Ceramic Circuit Boards

    Energy Technology Data Exchange (ETDEWEB)

    Normann, Randy A

    2015-02-15

    This paper covers the development of a geothermal ceramic circuit board technology using 3D traces in a machinable ceramic. Test results showing the circuit board to be operational to at least 550°C. Discussion on producing this type of board is outlined along with areas needing improvement.

  1. Secondary School Students' Misconceptions about Simple Electric Circuits

    Science.gov (United States)

    Küçüközer, Hüseyin; Kocakülah, Sabri

    2007-01-01

    The aim of this study is to reveal secondary school students' misconceptions about simple electric circuits and to define whether specific misconceptions peculiar to Turkish students exist within those identified. Data were obtained with a conceptual understanding test for simple electric circuits and semi-structured interviews. Conceptual…

  2. Unit: Electric Circuits, Inspection Pack, National Trial Print.

    Science.gov (United States)

    Australian Science Education Project, Toorak, Victoria.

    As a part of the unit materials in the series produced by the Australian Science Education Project, this teacher edition is primarily composed of a core relating to simple circuits, a test form, and options. Options are given under the headings: Your Invention; "How Long Does a Call Last?"; One, Two, Three Wires; Parallel Circuits; More…

  3. Integrated circuit structure

    International Nuclear Information System (INIS)

    1981-01-01

    The invention describes the fabrication of integrated circuit structures, such as read-only memory components of field-effect transistors, which may be fabricated and then maintained in inventory, and later selectively modified in accordance with a desired pattern. It is claimed that MOS depletion-mode devices in accordance with the invention can be fabricated at lower cost and at higher yields. (U.K.)

  4. Integrated coincidence circuits

    International Nuclear Information System (INIS)

    Borejko, V.F.; Grebenyuk, V.M.; Zinov, V.G.

    1976-01-01

    The description is given of two coincidence units employing integral circuits in the VISHNYA standard. The units are distinguished for the coincidence selection element which is essentially a combination of a tunnel diode and microcircuits. The output fast response of the units is at least 90 MHz in the mode of the output signal unshaped in duration and 50 MHz minimum in the mode of the output signal shaping. The resolution time of the units is dependent upon the duration of input signals

  5. Semiconductor integrated circuits

    International Nuclear Information System (INIS)

    Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

    1979-01-01

    An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

  6. A fast charge integrating and shaping circuit

    International Nuclear Information System (INIS)

    Kulka, Z.; Szoncso, F.

    1990-01-01

    The development of a low cost fast charge integrating and shaping circuit (FCISC) was motivated by the need for an interface between the photomultipliers of an existing hadronic calorimeter and recently developed new readout electronics designed to match the output of small ionization chambers for the upgraded UA1 detector at the CERN proton-antiproton collider. This paper describes the design principles of gated and ungated charge integrating and shaping circuits. An FCISC prototype using discrete components was made and its properties were determined with a computerized test setup. Finally an SMD implementation of the FCISC is presented and the performance is reported. (orig.)

  7. Electromagnetic compatibility methods, analysis, circuits, and measurement

    CERN Document Server

    Weston, David A

    2016-01-01

    Revised, updated, and expanded, Electromagnetic Compatibility: Methods, Analysis, Circuits, and Measurement, Third Edition provides comprehensive practical coverage of the design, problem solving, and testing of electromagnetic compatibility (EMC) in electrical and electronic equipment and systems. This new edition provides novel information on theory, applications, evaluations, electromagnetic computational programs, and prediction techniques available. With sixty-nine schematics providing examples for circuit level electromagnetic interference (EMI) hardening and cost effective EMI problem solving, this book also includes 1130 illustrations and tables. Including extensive data on components and their correct implementation, the myths, misapplication, misconceptions, and fallacies that are common when discussing EMC/EMI will also be addressed and corrected.

  8. Interface Circuit For Printer Port

    Science.gov (United States)

    Tucker, Jerry H.; Yadlowsky, Ann B.

    1991-01-01

    Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

  9. Changes to the shuttle circuits

    CERN Multimedia

    GS Department

    2011-01-01

    To fit with passengers expectation, there will be some changes to the shuttle circuits as from Monday 10 October. See details on http://cern.ch/ShuttleService (on line on 7 October). Circuit No. 5 is cancelled as circuit No. 1 also stops at Bldg. 33. In order to guarantee shorter travel times, circuit No. 1 will circulate on Meyrin site only and circuit No. 2, with departures from Bldg. 33 and 500, on Prévessin site only. Site Services Section

  10. Estimating the short-circuit impedance

    DEFF Research Database (Denmark)

    Nielsen, Arne Hejde; Pedersen, Knud Ole Helgesen; Poulsen, Niels Kjølstad

    1997-01-01

    A method for establishing a complex value of the short-circuit impedance from naturally occurring variations in voltage and current is discussed. It is the symmetrical three phase impedance at the fundamental grid frequency there is looked for. The positive sequence components in voltage...... and current are derived each period, and the short-circuit impedance is estimated from variations in these components created by load changes in the grid. Due to the noisy and dynamic grid with high harmonic distortion it is necessary to threat the calculated values statistical. This is done recursively...... through a RLS-algorithm. The algorithms have been tested and implemented on a PC at a 132 kV substation supplying a rolling mill. Knowing the short-circuit impedance gives the rolling mill an opportunity to adjust the arc furnace operation to keep flicker below a certain level. Therefore, the PC performs...

  11. Electromagnetic Compatibility Design of the Computer Circuits

    Science.gov (United States)

    Zitai, Hong

    2018-02-01

    Computers and the Internet have gradually penetrated into every aspect of people’s daily work. But with the improvement of electronic equipment as well as electrical system, the electromagnetic environment becomes much more complex. Electromagnetic interference has become an important factor to hinder the normal operation of electronic equipment. In order to analyse the computer circuit compatible with the electromagnetic compatibility, this paper starts from the computer electromagnetic and the conception of electromagnetic compatibility. And then, through the analysis of the main circuit and system of computer electromagnetic compatibility problems, we can design the computer circuits in term of electromagnetic compatibility. Finally, the basic contents and methods of EMC test are expounded in order to ensure the electromagnetic compatibility of equipment.

  12. Thermionic integrated circuits: electronics for hostile environments

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

    1985-01-01

    Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

  13. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  14. Integrated coherent matter wave circuits

    International Nuclear Information System (INIS)

    Ryu, C.; Boshier, M. G.

    2015-01-01

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

  15. Circuit bridging of components by smoke

    International Nuclear Information System (INIS)

    Tanaka, T.J.; Nowlen, S.P.; Anderson, D.J.

    1996-10-01

    Smoke can adversely affect digital electronics; in the short term, it can lead to circuit bridging and in the long term to corrosion of metal parts. This report is a summary of the work to date and component-level tests by Sandia National Laboratories for the Nuclear Regulatory Commission to determine the impact of smoke on digital instrumentation and control equipment. The component tests focused on short-term effects such as circuit bridging in typical components and the factors that can influence how much the smoke will affect them. These factors include the component technology and packaging, physical board protection, and environmental conditions such as the amount of smoke, temperature of burn, and humidity level. The likelihood of circuit bridging was tested by measuring leakage currents and converting those currents to resistance in ohms. Hermetically sealed ceramic packages were more resistant to smoke than plastic packages. Coating the boards with an acrylic spray provided some protection against circuit bridging. The smoke generation factors that affect the resistance the most are humidity, fuel level, and burn temperature. The use of CO 2 as a fire suppressant, the presence of galvanic metal, and the presence of PVC did not significantly affect the outcome of these results

  16. Duffing–van der Pol oscillator type dynamics in Murali–Lakshmanan–Chua (MLC) circuit

    International Nuclear Information System (INIS)

    Srinivasan, K.; Chandrasekar, V.K.; Venkatesan, A.; Raja Mohamed, I.

    2016-01-01

    Highlights: • Proposed an electronic circuit with diode based nonlinear element equivalent to a well known Murali–Lakshmanan–Chua (MLC) circuit. • For chosen circuit parameters this circuit admits familiar MLC type attractor and also Duffing–van der Pol circuit type chaotic attractor. • The performance of the circuit is investigated by means of explicit laboratory experiments, numerical simulations and analytical studies. - Abstract: We have constructed a simple second-order dissipative nonautonomous circuit exhibiting ordered and chaotic behaviour. This circuit is the well known Murali–Lakshmanan–Chua(MLC) circuit but with diode based nonlinear element. For chosen circuit parameters this circuit admits familiar MLC type attractor and also Duffing–van der Pol circuit type chaotic attractors. It is interesting to note that depending upon the circuit parameters the circuit shows both period doubling route to chaos and quasiperiodic route to chaos. In our study we have constructed two-parameter bifurcation diagrams in the forcing amplitude–frequency plane, one parameter bifurcation diagrams, Lyapunov exponents, 0–1 test and phase portrait. The performance of the circuit is investigated by means of laboratory experiments, numerical integration of appropriate mathematical model and explicit analytic studies.

  17. Switchless charge-discharge circuit for electrical capacitance tomography

    International Nuclear Information System (INIS)

    Kryszyn, J; Smolik, W T; Radzik, B; Olszewski, T; Szabatin, R

    2014-01-01

    The main factor limiting the performance of electrical capacitance tomography (ECT) is an extremely low value of inter-electrode capacitances. The charge-discharge circuit is a well suited circuit for a small capacitance measurement due to its immunity to noise and stray capacitance, although it has a problem associated with a charge injected by the analogue switches, which results in a dc offset. This paper presents a new diode-based circuit for capacitance measurement in which a charge transfer method is realized without switches. The circuit was built and tested in one channel configuration with 16 multiplexed electrodes. The performance of the elaborated circuit and a comparison with a classic charge-discharge circuit are presented. The elaborated circuit can be used for sensors with inter-electrode capacitances not lower than 10 fF. The presented approach allows us to obtain a similar performance to the classic charge-discharge circuit, but has a simplified design. A lack of the need to synchronize the analogue switches in the transmitter and the receiver part of this circuit could be a desirable feature in the design of measurement systems integrated with electrodes. (paper)

  18. Vertically integrated circuit development at Fermilab for detectors

    International Nuclear Information System (INIS)

    Yarema, R; Deptuch, G; Hoff, J; Khalid, F; Lipton, R; Shenai, A; Trimpl, M; Zimmerman, T

    2013-01-01

    Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

  19. Instrumentation for Sodium Circuits; Instrumentation des Circuits de Sodium

    Energy Technology Data Exchange (ETDEWEB)

    Cambillard, E. [CEA, Centre d' Etudes Nucleaires de Fontenay-aux-Roses (France); Lions, N. [CEA, Centre d' Etudes Nucleaires de Cadarache (France)

    1967-06-15

    Electromagnetic flow meters, level gauges and differential pressure gauges are among the main measurement instruments designed and tested at the Commissariat a l'Energie Atomique (CEA) for sodium reactors. The main characteristics of the flow meters used with RAPSODIE are indicated. The instruments used in this connection are of the permanent -magnet or electromagnet type (in the primary circuits). A description is given of the calibration methods employed - use is made of diaphragms or Venturi tubes as standard flow meters - and information is given on the results measured for maximum sodium flows of 400 m{sup 3}/h. Three types of continuous level gauge have been studied. Resistance gauge. Two varieties used for the 1 - and 10-MW test circuits of RAPSODIE are described. In one there is a compensation resistance along the whole height of the measuring element (the continuous gauges used with the RAPSODIE reactor are at present of this type). In the other type of gauge a device is incorporated to heat the measurement element and prevent the formation of conducting deposits (prototype sodium tests have been completed). Induction gauge. This type has two coupled coils and is fitted with a device to compensate for temperature effects. A description is given of a prototype which has been built and the results obtained in the course of sodium tests are described. Ultrasonic gauge. With this type, a transmitter is fitted on top of the outside of the sodium container; there is also a vertical wave guide, the bottom of which is immersed in the liquid metal and possesses a reflector system which returns the ultrasonic beam towards the surface. Fixed reference marks provide a permanent means of calibration and the whole apparatus is welded. This type of gauge is now being constructed. The differential pressure gauges that have been built, and used in particular with Venturi tube flow meters, are modified versions of the devices employed with the 1 - and 10-MW test circuits of

  20. Dynamic pulse difference circuit

    International Nuclear Information System (INIS)

    Erickson, G.L.

    1978-01-01

    A digital electronic circuit of especial use for subtracting background activity pulses in gamma spectrometry is disclosed which comprises an up-down counter connected to count up with signal-channel pulses and to count down with background-channel pulses. A detector responsive to the count position of the up-down counter provides a signal when the up-down counter has completed one scaling sequence cycle of counts in the up direction. In an alternate embodiment, a detector responsive to the count position of the up-down counter provides a signal upon overflow of the counter

  1. Electric circuits problem solver

    CERN Document Server

    REA, Editors of

    2012-01-01

    Each Problem Solver is an insightful and essential study and solution guide chock-full of clear, concise problem-solving gems. All your questions can be found in one convenient source from one of the most trusted names in reference solution guides. More useful, more practical, and more informative, these study aids are the best review books and textbook companions available. Nothing remotely as comprehensive or as helpful exists in their subject anywhere. Perfect for undergraduate and graduate studies.Here in this highly useful reference is the finest overview of electric circuits currently av

  2. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  3. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  4. Nano integrated circuit process

    International Nuclear Information System (INIS)

    Yoon, Yung Sup

    2004-02-01

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  5. Electronic logic circuits

    CERN Document Server

    Gibson, J

    2013-01-01

    Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate

  6. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  7. Nano integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Yung Sup

    2004-02-15

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  8. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    1999-01-01

    This manual is a useful single-volume guide specifically aimed at the practical design engineer, technician, and experimenter, as well as the electronics student and amateur. It deals with the subject in an easy to read, down to earth, and non-mathematical yet comprehensive manner, explaining the basic principles and characteristics of the best known devices, and presenting the reader with many practical applications and over 200 circuits. Most of the ICs and other devices used are inexpensive and readily available types, with universally recognised type numbers.The second edition

  9. Optically controllable molecular logic circuits

    International Nuclear Information System (INIS)

    Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-01-01

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

  10. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  11. Compiling quantum circuits to realistic hardware architectures using temporal planners

    Science.gov (United States)

    Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy

    2018-04-01

    To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.

  12. Simple Cell Balance Circuit

    Science.gov (United States)

    Johnson, Steven D.; Byers, Jerry W.; Martin, James A.

    2012-01-01

    A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.

  13. Quantum-Circuit Refrigerator

    Science.gov (United States)

    MöTtöNen, Mikko; Tan, Kuan Y.; Masuda, Shumpei; Partanen, Matti; Lake, Russell E.; Govenius, Joonas; Silveri, Matti; Grabert, Hermann

    Quantum technology holds great potential in providing revolutionizing practical applications. However, fast and precise cooling of the functional quantum degrees of freedom on demand remains a major challenge in many solid-state implementations, such as superconducting circuits. We demonstrate direct cooling of a superconducting resonator mode using voltage-controllable quantum tunneling of electrons in a nanoscale refrigerator. In our first experiments on this type of a quantum-circuit refrigerator, we measure the drop in the mode temperature by electron thermometry at a resistor which is coupled to the resonator mode through ohmic losses. To eliminate unwanted dissipation, we remove the probe resistor and directly observe the power spectrum of the resonator output in agreement with the so-called P(E) theory. We also demonstrate in microwave reflection experiments that the internal quality factor of the resonator can be tuned by orders of magnitude. In the future, our refrigerator can be integrated with different quantum electric devices, potentially enhancing their performance. For example, it may prove useful in the initialization of superconducting quantum bits and in dissipation-assisted quantum annealing. We acknowledge European Research Council Grant SINGLEOUT (278117) and QUESS (681311) for funding.

  14. Quasi-Linear Circuit

    Science.gov (United States)

    Bradley, William; Bird, Ross; Eldred, Dennis; Zook, Jon; Knowles, Gareth

    2013-01-01

    This work involved developing spacequalifiable switch mode DC/DC power supplies that improve performance with fewer components, and result in elimination of digital components and reduction in magnetics. This design is for missions where systems may be operating under extreme conditions, especially at elevated temperature levels from 200 to 300 degC. Prior art for radiation-tolerant DC/DC converters has been accomplished utilizing classical magnetic-based switch mode converter topologies; however, this requires specific shielding and component de-rating to meet the high-reliability specifications. It requires complex measurement and feedback components, and will not enable automatic re-optimization for larger changes in voltage supply or electrical loading condition. The innovation is a switch mode DC/DC power supply that eliminates the need for processors and most magnetics. It can provide a well-regulated voltage supply with a gain of 1:100 step-up to 8:1 step down, tolerating an up to 30% fluctuation of the voltage supply parameters. The circuit incorporates a ceramic core transformer in a manner that enables it to provide a well-regulated voltage output without use of any processor components or magnetic transformers. The circuit adjusts its internal parameters to re-optimize its performance for changes in supply voltage, environmental conditions, or electrical loading at the output

  15. Arithmetic circuits for DSP applications

    CERN Document Server

    Stouraitis, Thanos

    2017-01-01

    Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

  16. Integrated circuit cooled turbine blade

    Science.gov (United States)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  17. Control circuit for transformer relay

    International Nuclear Information System (INIS)

    Wyatt, G.A.

    1984-01-01

    A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

  18. New resonant circuits for the ISOLTRAP radiofrequency quadrupole trap

    CERN Document Server

    SENECAL, Pierre

    2015-01-01

    This report describes my work during my Summer Student Program. My main project was building and testing a resonance-circuit box for a radio-frequency power supply used with the radio-frequency cooler and buncher.

  19. Source-circuit design overview

    Science.gov (United States)

    Ross, R. G., Jr.

    1983-01-01

    The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

  20. A chopper circuit for energy transfer between superconducting magnets

    International Nuclear Information System (INIS)

    Onishi, Toshitada; Tateishi, Hiroshi; Takeda, Masatoshi; Matsuura, Toshiaki; Nakatani, Toshio.

    1986-01-01

    It has been suggested that superconducting magnets could provide a medium for storing energy and supplying the large energy pulses needed by experimental nuclear-fusion equipment and similar loads. Based on this concept, tests on energy transfer between superconducting magnets are currently being conducted at the Agency of Industrial Science and Technology's Electrotechnical Laboratory. Mitsubishi Electric has pioneered the world's first chopper circuit for this application. The circuit has the advantages of being simple and permitting high-speed, bipolar energy transfer. The article describes this circuit and its testing. (author)

  1. Azerbaijan Technical University’s Experience in Teaching Linear Electrical Circuit Theory

    Directory of Open Access Journals (Sweden)

    G. A. Mamedov

    2006-01-01

    Full Text Available An experience in teaching linear electrical circuit theory at the Azerbaijan Technical University is presented in the paper. The paper describes structure of the Linear Electrical Circuit Theory course worked out by the authors that contains a section on electrical calculation of track circuits, information on electro-magnetic compatibility and typical tests for better understanding of the studied subject.

  2. Radiation-sensitive switching circuits

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J.H.; Cockshott, C.P.

    1976-03-16

    A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

  3. Four-junction superconducting circuit

    Science.gov (United States)

    Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

    2016-01-01

    We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

  4. Measurements of the Effects of Smoke on Active Circuits

    International Nuclear Information System (INIS)

    Tanaka, T.J.

    1999-01-01

    Smoke has long been recognized as the most common source of fire damage to electrical equipment; however, most failures have been analyzed after the fire was out and the smoke vented. The effects caused while the smoke is still in the air have not been explored. Such effects have implications for new digital equipment being installed in nuclear reactors. The U.S. Nuclear Regulatory Commission is sponsoring work to determine the impact of smoke on digital instrumentation and control. As part of this program, Sandia National Laboratories has tested simple active circuits to determine how smoke affects them. These tests included the study of three possible failure modes on a functional board: (1) circuit bridging, (2) corrosion (metal loss), and (3) induction of stray capacitance. The performance of nine different circuits was measured continuously on bare and conformably coated boards during smoke exposures lasting 1 hour each and continued for 24 hours after the exposure started. The circuit that was most affected by smoke (100% change in measured values) was the one most sensitive to circuit bridging. Its high impedance (50 MOmega) was shorted during the exposure, but in some cases recovered after the smoke was vented. The other two failure modes, corrosion and induced stray capacitance, caused little change in the function of the circuits. The smoke permanently increased resistance of the circuit tested for corrosion, implying that the cent acts were corroded. However, the change was very small (< 2%). The stray-capacitance test circuit showed very little change after a smoke exposure in either the short or long term. The results of the tests suggest that conformal coatings and type of circuit are major considerations when designing digital circuitry to be used in critical control systems

  5. Measurements of the effects of smoke on active circuits

    International Nuclear Information System (INIS)

    Tanaka, T.J.

    1998-01-01

    Smoke has long been recognized as the most common source of fire damage to electrical equipment; however, most failures have been analyzed after the fire was out and the smoke vented. The effects caused while the smoke is still in the air have not been explored. Such effects have implications for new digital equipment being installed in nuclear reactors. The US Nuclear Regulatory Commission is sponsoring work to determine the impact of smoke on digital instrumentation and control. As part of this program, Sandia National Laboratories has tested simple active circuits to determine how smoke affects them. These tests included the study of three possible failure modes on a functional board: (1) circuit bridging, (2) corrosion (metal loss), and (3) induction of stray capacitance. The performance of nine different circuits was measured continuously on bare and conformally coated boards during smoke exposures lasting 1 hour each and continued for 24 hours after the exposure started. The circuit that was most affected by smoke (100% change in measured values) was the one most sensitive to circuit bridging. Its high impedance (50 Mohm) was shorted during the exposure, but in some cases recovered after the smoke was vented. The other two failure modes, corrosion and induced stray capacitance, caused little change in the function of the circuits. The smoke permanently increased resistance of the circuit tested for corrosion, implying that the contacts were corroded. However, the change was very small (< 2%). The stray capacitance test circuit showed very little change after a smoke exposure in either the short or long term. The results of the tests suggest that conformal coatings and type of circuit are major considerations when designing digital circuitry to be used in critical control systems

  6. Basic electronic circuits

    CERN Document Server

    Buckley, P M

    1980-01-01

    In the past, the teaching of electricity and electronics has more often than not been carried out from a theoretical and often highly academic standpoint. Fundamentals and basic concepts have often been presented with no indication of their practical appli­ cations, and all too frequently they have been illustrated by artificially contrived laboratory experiments bearing little relationship to the outside world. The course comes in the form of fourteen fairly open-ended constructional experiments or projects. Each experiment has associated with it a construction exercise and an explanation. The basic idea behind this dual presentation is that the student can embark on each circuit following only the briefest possible instructions and that an open-ended approach is thereby not prejudiced by an initial lengthy encounter with the theory behind the project; this being a sure way to dampen enthusiasm at the outset. As the investigation progresses, questions inevitably arise. Descriptions of the phenomena encounte...

  7. ECCS control circuit

    International Nuclear Information System (INIS)

    Sato, Takashi.

    1986-01-01

    Purpose: To afford a sufficient margin to pressure vibrations upon starting of an automatic depressurization system by dispersing pressure vibration in suppression water due to the opening action of an automatic releaf valve in the automatic depressurization system thereby reducing the dynamic load exerted to the surface of the suppression walls. Constitution: Upon occurrence of loss of coolant accidents, an automatic releaf valve for automatic depressurization is opened to deliver the steams in the pressure vessel into the suppression pool. Since a plurality of automatic releaf valves have usually been disposed, if they are opened simultaneously, excess dynamic loads are exerted due to the pressure vibrations to the wall surface of the suppression pool. In this invention, a control circuit is disposed such that the opening timing for each of the automatic releaf valves is deviated upon occurrence of a driving signal for the automatic depressurization system to thereby disperse the pressure vibrations in the suppression water. (Kamimura, M.)

  8. A dishwasher for circuits

    CERN Multimedia

    Rosaria Marraffino

    2014-01-01

    You have always been told that electronic devices fear water. However, at the Surface Mount Devices (SMD) Workshop here at CERN all the electronic assemblies are cleaned with a machine that looks like a… dishwasher.   The circuit dishwasher. Credit: Clara Nellist.  If you think the image above shows a dishwasher, you wouldn’t be completely wrong. Apart from the fact that the whole pumping system and the case itself are made entirely from stainless steel and chemical resistant materials, and the fact that it washes electrical boards instead of dishes… it works exactly like a dishwasher. It’s a professional machine (mainly used in the pharmaceutical industry) designed to clean everything that can be washed with a water-based chemical soap. This type of treatment increases the lifetime of the electronic boards and therefore the LHC's reliability by preventing corrosion problems in the severe radiation and ozone environment of the LHC tunn...

  9. Modeling cortical circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Rohrer, Brandon Robinson; Rothganger, Fredrick H.; Verzi, Stephen J.; Xavier, Patrick Gordon

    2010-09-01

    The neocortex is perhaps the highest region of the human brain, where audio and visual perception takes place along with many important cognitive functions. An important research goal is to describe the mechanisms implemented by the neocortex. There is an apparent regularity in the structure of the neocortex [Brodmann 1909, Mountcastle 1957] which may help simplify this task. The work reported here addresses the problem of how to describe the putative repeated units ('cortical circuits') in a manner that is easily understood and manipulated, with the long-term goal of developing a mathematical and algorithmic description of their function. The approach is to reduce each algorithm to an enhanced perceptron-like structure and describe its computation using difference equations. We organize this algorithmic processing into larger structures based on physiological observations, and implement key modeling concepts in software which runs on parallel computing hardware.

  10. Inductive circuit arrangements

    International Nuclear Information System (INIS)

    Mansfield, Peter; Coxon, R.J.

    1987-01-01

    A switched coil arrangement is connected in a bridge configuration of four switches S 1 , S 2 , S 3 and S 4 which are each shunted by diodes D 1 , D 2 , D 3 and D 4 so that current can flow in either direction through a coil L depending on the setting of the switches. A capacitor C is connected across the bridge through a switch S 5 to receive the inductive energy stored in coil L on breaking the current flow path through the coil. The electrostatic energy stored in capacitor C can then be used to supply current through the coil in the reverse direction either immediately or after a time delay. Coil L may be a superconductive coil. Losses in the circuit can be made up by a trickle charge of capacitor C from a separate supply V 2 . The device may be used in nuclear magnetic resonance imaging. (author)

  11. Safety of steel vessel Magnox pressure circuits

    International Nuclear Information System (INIS)

    Stokoe, T.Y.; Bolton, C.J.; Heffer, P.J.H.

    1991-01-01

    The maintenance of pressure circuit integrity is fundamental to nuclear safety at the steel vessel Magnox stations. To confirm continued pressure circuit integrity the CEGB, as part of the Long Term Safety Review, has carried out extensive assessment and inspection in recent years. The assessment methods and inspection techniques employed are based on the most modern available. Reactor pressure vessel integrity is confirmed by a combination of arguments including safety factors inferred from the successful pre-service overpressure test, leak-before-break analysis and probabilistic assessment. In the case of other parts of the pressure circuits that are more accessible, comprising the boiler shells and interconnecting gas duct work, in-service inspection is a major element of the safety substantiation. The assessment and inspection techniques and the materials property data have been underpinned for many years by extensive research and development programmes and in-reactor monitoring of representative samples has also been undertaken. The paper summarises the work carried out to demonstrate the long term integrity of the Magnox pressure circuits and provides examples of the results obtained. (author)

  12. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  13. Compact Circuit Preprocesses Accelerometer Output

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1993-01-01

    Compact electronic circuit transfers dc power to, and preprocesses ac output of, accelerometer and associated preamplifier. Incorporated into accelerometer case during initial fabrication or retrofit onto commercial accelerometer. Made of commercial integrated circuits and other conventional components; made smaller by use of micrologic and surface-mount technology.

  14. Current-mode minimax circuit

    NARCIS (Netherlands)

    Wassenaar, R.F.

    1992-01-01

    The minimum-maximum (minimax) circuit selects the minimum and maximum of two input currents. Four transistors in matched pairs are operated in the saturation region. Because the behavior of the circuit is based on matched devices and is independent of the relationship between the drain current and

  15. Short-circuit impedance measurement

    DEFF Research Database (Denmark)

    Pedersen, Knud Ole Helgesen; Nielsen, Arne Hejde; Poulsen, Niels Kjølstad

    2003-01-01

    Methods for estimating the short-circuit impedance in the power grid are investigated for various voltage levels and situations. The short-circuit impedance is measured, preferably from naturally occurring load changes in the grid, and it is shown that such a measurement system faces different...

  16. Enhancement of Linear Circuit Program

    DEFF Research Database (Denmark)

    Gaunholt, Hans; Dabu, Mihaela; Beldiman, Octavian

    1996-01-01

    In this report a preliminary user friendly interface has been added to the LCP2 program making it possible to describe an electronic circuit by actually drawing the circuit on the screen. Component values and other options and parameters can easily be set by the aid of the interface. The interface...

  17. Automatic circuit analysis based on mask information

    International Nuclear Information System (INIS)

    Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.

    1976-01-01

    The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program

  18. The RD53A Integrated Circuit

    CERN Document Server

    Garcia-Sciveres, Maurice

    2017-01-01

    Implementation details for the RD53A pixel readout integrated circuit designed by the RD53 Collaboration. This is a companion to the specifications document and will eventually become a reference for chip users. RD53A is not intended to be a final production IC for use in an experiment, and contains design variations for testing purposes, making the pixel matrix non-uniform. The chip size is 20.0 mm by 11.8 mm.

  19. Circuit of synchronous logic for the transmission of safety commands

    International Nuclear Information System (INIS)

    Uberschlag, J.

    1969-01-01

    The author reports the development of a control-command circuit for the transmission of binary commands related to the safety of nuclear reactors. He presents the main design criteria (operation safety, provided safety level, flexibility, technical adaptation), the definition of the operation principle (inputs, logical outputs), the properties of a logic system. He evokes redundancy issues, and presents the system structure, proposes a possible sketch of the logic circuit. He describes the possible options for intermediate circuits and logic outputs, and tests to be performed

  20. Circuit Design of Surface Acoustic Wave Based Micro Force Sensor

    Directory of Open Access Journals (Sweden)

    Yuanyuan Li

    2014-01-01

    Full Text Available Pressure sensors are commonly used in industrial production and mechanical system. However, resistance strain, piezoresistive sensor, and ceramic capacitive pressure sensors possess limitations, especially in micro force measurement. A surface acoustic wave (SAW based micro force sensor is designed in this paper, which is based on the theories of wavelet transform, SAW detection, and pierce oscillator circuits. Using lithium niobate as the basal material, a mathematical model is established to analyze the frequency, and a peripheral circuit is designed to measure the micro force. The SAW based micro force sensor is tested to show the reasonable design of detection circuit and the stability of frequency and amplitude.

  1. Nanofluidic Transistor Circuits

    Science.gov (United States)

    Chang, Hsueh-Chia; Cheng, Li-Jing; Yan, Yu; Slouka, Zdenek; Senapati, Satyajyoti

    2012-02-01

    Non-equilibrium ion/fluid transport physics across on-chip membranes/nanopores is used to construct rectifying, hysteretic, oscillatory, excitatory and inhibitory nanofluidic elements. Analogs to linear resistors, capacitors, inductors and constant-phase elements were reported earlier (Chang and Yossifon, BMF 2009). Nonlinear rectifier is designed by introducing intra-membrane conductivity gradient and by asymmetric external depletion with a reverse rectification (Yossifon and Chang, PRL, PRE, Europhys Lett 2009-2011). Gating phenomenon is introduced by functionalizing polyelectrolytes whose conformation is field/pH sensitive (Wang, Chang and Zhu, Macromolecules 2010). Surface ion depletion can drive Rubinstein's microvortex instability (Chang, Yossifon and Demekhin, Annual Rev of Fluid Mech, 2012) or Onsager-Wien's water dissociation phenomenon, leading to two distinct overlimiting I-V features. Bipolar membranes exhibit an S-hysteresis due to water dissociation (Cheng and Chang, BMF 2011). Coupling the hysteretic diode with some linear elements result in autonomous ion current oscillations, which undergo classical transitions to chaos. Our integrated nanofluidic circuits are used for molecular sensing, protein separation/concentration, electrospray etc.

  2. Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

    OpenAIRE

    石橋, 孝昭

    2012-01-01

    This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

  3. Variational integrators for electric circuits

    International Nuclear Information System (INIS)

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

    2013-01-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

  4. Integrated circuits, and design and manufacture thereof

    Science.gov (United States)

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  5. Radiation-sensitive switching circuits

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J.H.; Cockshott, C.P.

    1976-03-16

    A radiation-sensitive switching circuit includes a light emitting diode which from time to time illuminates a photo-transistor, the photo-transistor serving when its output reaches a predetermined value to operate a trigger circuit. In order to allow for aging of the components, the current flow through the diode is increased when the output from the transistor falls below a known level. Conveniently, this is achieved by having a transistor in parallel with the diode, and turning the transistor off when the output from the phototransistor becomes too low. The circuit is designed to control the ignition system in an automobile engine.

  6. Secure integrated circuits and systems

    CERN Document Server

    Verbauwhede, Ingrid MR

    2010-01-01

    On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

  7. INTEGRATED SENSOR EVALUATION CIRCUIT AND METHOD FOR OPERATING SAID CIRCUIT

    OpenAIRE

    Krüger, Jens; Gausa, Dominik

    2015-01-01

    WO15090426A1 Sensor evaluation device and method for operating said device Integrated sensor evaluation circuit for evaluating a sensor signal (14) received from a sensor (12), having a first connection (28a) for connection to the sensor and a second connection (28b) for connection to the sensor. The integrated sensor evaluation circuit comprises a configuration data memory (16) for storing configuration data which describe signal properties of a plurality of sensor control signals (26a-c). T...

  8. A Simple Square Rooting Circuit Based on Operational Amplifiers (OPAMPs

    Directory of Open Access Journals (Sweden)

    K. C. Selvam

    2013-02-01

    Full Text Available A simple circuit which accepts a negative voltage as input and provides an output voltage equal to the square root of the input voltage is described in this paper. The square rooting operation is dependent only on the ratio of two resistors and a DC voltage. Hence, the required accuracy can be obtained by employing precision resistors and a stable reference voltage. The feasibility of the circuit is examined by testing the results on a proto type.

  9. Capacitive short circuit detection in transformer core laminations

    International Nuclear Information System (INIS)

    Schulz, Carl A.; Duchesne, Stephane; Roger, Daniel; Vincent, Jean-Noel

    2008-01-01

    A capacitive measurement procedure is proposed that serves to detect burr-induced short circuits in transformer core laminations. The tests are conducted on stacks of transformer steel sheets as used for transformer core production and yield a short-circuit probability indicative of the additional eddy current losses to be expected. Applied during the assembly of transformer cores, the measurements can help to decide whether the burr treatment process is working efficiently or has to be readjusted

  10. Custom VLSI circuits for high energy physics

    International Nuclear Information System (INIS)

    Parker, S.

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner's guide through the maze, and that is the main purpose of this text

  11. Custom VLSI circuits for high energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  12. Quantum circuit behaviour

    International Nuclear Information System (INIS)

    Poulton, D.

    1989-09-01

    Single electron tunnelling in multiply connected weak link systems is considered. Using a second quantised approach the tunnel current, in both normal and superconducting systems, using perturbation theory, is derived. The tunnel currents are determined as a function of an Aharanov-Bohm phase (acquired by the electrons). Using these results, the multiply connected system is then discussed when coupled to a resonant LC circuit. The resulting dynamics of this composite system are then determined. In the superconducting case the results are compared and contrasted with flux mode behaviour seen in large superconducting weak link rings. Systems in which the predicted dynamics may be seen are also discussed. In analogy to the electron tunnelling analysis, the tunnelling of magnetic flux quanta through the weak link is also considered. Here, the voltage across the weak link, due to flux tunnelling, is determined as a function of an externally applied current. This is done for both singly and multiply connected flux systems. The results are compared and contrasted with charge mode behaviour seen in superconducting weak link systems. Finally, the behaviour of simple quantum fluids is considered when subject to an external rotation. Using a microscopic analysis it is found that the microscopic quantum behaviour of the particles is manifest on a macroscopic level. Results are derived for bosonic, fermionic and BCS pair-type systems. The connection between flux quantisation in electromagnetic systems is also made. Using these results, the dynamics of such a quantum fluid is considered when coupled to a rotating torsional oscillator. The results are compared with those found in SQUID devices. A model is also presented which discusses the possible excited state dynamics of such a fluid. (author)

  13. Diagnosis of soft faults in analog integrated circuits based on fractional correlation

    International Nuclear Information System (INIS)

    Deng Yong; Shi Yibing; Zhang Wei

    2012-01-01

    Aiming at the problem of diagnosing soft faults in analog integrated circuits, an approach based on fractional correlation is proposed. First, the Volterra series of the circuit under test (CUT) decomposed by the fractional wavelet packet are used to calculate the fractional correlation functions. Then, the calculated fractional correlation functions are used to form the fault signatures of the CUT. By comparing the fault signatures, the different soft faulty conditions of the CUT are identified and the faults are located. Simulations of benchmark circuits illustrate the proposed method and validate its effectiveness in diagnosing soft faults in analog integrated circuits. (semiconductor integrated circuits)

  14. Thermally-induced voltage alteration for integrated circuit analysis

    Energy Technology Data Exchange (ETDEWEB)

    Cole, E.I. Jr.

    2000-06-20

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  15. Transistor and integrated circuit manufacture

    International Nuclear Information System (INIS)

    Colman, D.

    1978-01-01

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

  16. Time domain analog circuit simulation

    NARCIS (Netherlands)

    Fijnvandraat, J.G.; Houben, S.H.M.J.; Maten, ter E.J.W.; Peters, J.M.F.

    2006-01-01

    Recent developments of new methods for simulating electric circuits are described. Emphasis is put on methods that fit existing datastructures for backward differentiation formulae methods. These methods can be modified to apply to hierarchically organized datastructures, which allows for efficient

  17. Circuit design on plastic foils

    CERN Document Server

    Raiteri, Daniele; Roermund, Arthur H M

    2015-01-01

    This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics.  The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.   • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels.

  18. Discharge quenching circuit for counters

    International Nuclear Information System (INIS)

    Karasik, A.S.

    1982-01-01

    A circuit for quenching discharges in gas-discharge detectors with working voltage of 3-5 kV based on transistors operating in the avalanche mode is described. The quenching circuit consists of a coordinating emitter follower, amplifier-shaper for avalanche key cascade control which changes potential on the counter electrodes and a shaper of discharge quenching duration. The emitter follower is assembled according to a widely used flowsheet with two transistors. The circuit permits to obtain a rectangular quenching pulse with front of 100 ns and an amplitude of up to 3.2 kV at duration of 500 μm-8 ms. Application of the quenching circuit described permits to obtain countering characteristics with the slope less than or equal to 0.02%/V and plateau extent greater than or equal to 300 V [ru

  19. Transistor and integrated circuit manufacture

    Energy Technology Data Exchange (ETDEWEB)

    Colman, D

    1978-09-27

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

  20. Ignition circuit for combustion engines

    Energy Technology Data Exchange (ETDEWEB)

    Becker, H W

    1977-05-26

    The invention refers to the ignition circuit for combustion engines, which are battery fed. The circuit contains a transistor and an oscillator to produce an output voltage on the secondary winding of an output transformer to supply an ignition current. The plant is controlled by an interrupter. The purpose of the invention is to form such a circuit that improved sparks for ignition are produced, on the one hand, and that on the other hand, the plant can continue to function after loss of the oscillator. The problem is solved by the battery and the secondary winding of the output transformers of the oscillator are connected via a rectifier circuit to produce a resultant total voltage with the ignition coil from the battery voltage and the rectified pulsating oscillator output.

  1. Reverse engineering of integrated circuits

    Science.gov (United States)

    Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  2. A Method for Automatic Inspection of Printed Circuit Boards by Using the Thermal Signature

    International Nuclear Information System (INIS)

    Amer, H.H.; Zekry, A.A.; Elaraby, S.; Ghareeb, K.E.

    2012-01-01

    This paper aims to design a system for automating inspection of the printed circuit boards (PCBs) by using the thermal signature of the different integrated circuits (I.C). The proposed inspection system consists of the inspection circuit, data acquisition system (DAS) and personal computer. Inspection is done by comparing the thermal signature of normally operated circuit with the thermal signature of circuit under test. One thermistor is assigned to each component in the circuit. The thermistor must touch tightly the surface of the I.C. to sense its temperature during the inspection process. Matlab software is used to represent the thermal signature through different colors. The Turbo C software is used to develop a program for acquiring and comparing the thermal signature of the circuit under the test with the reference circuit. If the colors of the two thermal signatures for the same I.C. are same then the circuit under test is fault free and does not contain any defect. On the other side, if the colors of the two thermal signatures for the same I.C. are different then the circuit under test is defective

  3. Instrumentation in the Rapsodie test circuits of 1 and 10 MW - flow-meters, manometers, level indicators, blockage indicators; L'instrumentation dans les cilicuits d'essais rapsodie 1 et 10 MW - debitmetres, manometres, indicateurs de niveau, indicateurs de bouchage

    Energy Technology Data Exchange (ETDEWEB)

    Lisle, J.P. de; Lions, N [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1964-07-01

    The main measuring instruments, which operate in the presence of liquid metals and which have been developed by the liquid metal section over the last few years, are electromagnetic flowmeters, differential manometers, level indicators and blockage indicators. We give here results obtained with these instruments during trial, in the 1 and 10 MW test circuits, together with the conclusions drawn about their possible use in the reactor Rapsodie, The flow rate measurements are carried out using electromagnetic flow meters with permanent magnets. We have studied more particularly the reliability of these instruments. The measurements matte show that the induction in the space between the poles is very constant with time and in the presence of the prevailing demagnetization phenomena to which the magnets are subjected. The differential manometers placed in the test circuits are very accurate. It is nevertheless necessary to carry out some technological modifications on them in order that they may operate satisfactorily over long periods. The continuous and discontinuous level-indicators tried out operate on the principle of a change in resistance. Studies carried out on the test loops of the reliability and of the accuracy of this equipment have shown the existence of phenomena convected with the condensation of sodium vapour on the upper parts of the reservoir, and have shown the importance of the condensed deposits when the oxygen content of the covering gas is appreciable. From the various blockage indicators tried out, the one chosen for equipping the reactor circuits is an automatic model with continuous recording. The development and testing of this apparatus has been going on for one year on an industrial scale circuit and has made it possible to show clearly an effect of a double blockage temperature. (authors) [French] Les principaux instruments de mesure, fonctionnant en presence de metal liquide, qui ont ete developpes et mis au point a la Section des Metaux

  4. Spectral Purity Enhancement via Polyphase Multipath Circuits

    NARCIS (Netherlands)

    Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

    2004-01-01

    The central question of this paper is: can we enhance the spectral purity of nonlinear circuits by using polyphase multipath circuits? The basic idea behind polyphase multipath circuits is to split the nonlinear circuits into two or more paths and exploit phase differences between these paths to

  5. Distortion Cancellation via Polyphase Multipath Circuits

    NARCIS (Netherlands)

    Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

    The central question of this paper is: can we enhance the spectral purity of nonlinear circuits with the help of polyphase multipath circuits. Polyphase multipath circuits are circuits with two or more paths that exploit phase differences between the paths to cancel unwanted signals. It turns out

  6. Dynamic theory for the mesoscopic electric circuit

    International Nuclear Information System (INIS)

    Chen Bin; Shen Xiaojuan; Li Youquan; Sun LiLy; Yin Zhujian

    2005-01-01

    The quantum theory for mesoscopic electric circuit with charge discreteness is briefly described. The minibands of quasienergy in LC design mesoscopic electric circuit have been found. In the mesoscopic 'pure' inductance design circuit, just like in the mesoscopic metallic rings, the quantum dynamic characteristics have been obtained explicitly. In the 'pure' capacity design circuit, the Coulomb blockade had also been addressed

  7. Multi-Layer E-Textile Circuits

    Science.gov (United States)

    Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

    2012-01-01

    Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

  8. Experimental study of natural circulation circuit

    Energy Technology Data Exchange (ETDEWEB)

    Lemos, Wanderley F.; Su, Jian, E-mail: wlemos@lasme.coppe.ufrj.br, E-mail: sujian@lasme.coppe.ufrj.br [Coordenacao dos Programas de Pos-Graduacao de Engenharia (LASME/COPPE/UFRJ), Rio de Janeiro, RJ (Brazil). Lab. de Simulacao e Metodos Numericos; Faccini, Jose L.H., E-mail: faccini@ien.gov.br [Instituto de Engenharia Nuclear (LTE/IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Lab. de Termo-Hidraulica Experimental

    2011-07-01

    This work presents an experimental study about fluid flows behavior in natural circulation, under conditions of single-phase flow. The experiment was performed through experimental thermal-hydraulic circuit built at IEN. This test equipment has performance similar to passive system of residual heat removal present in Advanced Pressurized Water Reactors (APWR). This experimental study aims to observing and analyzing the natural circulation phenomenon, using this experimental circuit that was dimensioned and built based on concepts of similarity and scale. This philosophy allows the analysis of natural circulation behavior in single-phase flow conditions proportionally to the functioning real conditions of a nuclear reactor. The experiment was performed through procedures to initialization of hydraulic feeding of primary and secondary circuits and electrical energizing of resistors installed inside heater. Power controller has availability to adjust values of electrical power to feeding resistors, in order to portray several conditions of energy decay of nuclear reactor in a steady state. Data acquisition system allows the measurement and monitoring of the evolution of the temperature in various points through thermocouples installed in strategic points along hydraulic circuit. The behavior of the natural circulation phenomenon was monitored by graphical interface on computer screen, showing the temperature evolutions of measuring points and results stored in digital spreadsheets. The results stored in digital spreadsheets allowed the getting of data to graphic construction and discussion about natural circulation phenomenon. Finally, the calculus of Reynolds number allowed the establishment for a correlation of friction in function of geometric scales of length, heights and cross section of tubing, considering a natural circulation flow throughout in the region of hot leg. (author)

  9. Experimental study of natural circulation circuit

    International Nuclear Information System (INIS)

    Lemos, Wanderley F.; Su, Jian; Faccini, Jose L.H.

    2011-01-01

    This work presents an experimental study about fluid flows behavior in natural circulation, under conditions of single-phase flow. The experiment was performed through experimental thermal-hydraulic circuit built at IEN. This test equipment has performance similar to passive system of residual heat removal present in Advanced Pressurized Water Reactors (APWR). This experimental study aims to observing and analyzing the natural circulation phenomenon, using this experimental circuit that was dimensioned and built based on concepts of similarity and scale. This philosophy allows the analysis of natural circulation behavior in single-phase flow conditions proportionally to the functioning real conditions of a nuclear reactor. The experiment was performed through procedures to initialization of hydraulic feeding of primary and secondary circuits and electrical energizing of resistors installed inside heater. Power controller has availability to adjust values of electrical power to feeding resistors, in order to portray several conditions of energy decay of nuclear reactor in a steady state. Data acquisition system allows the measurement and monitoring of the evolution of the temperature in various points through thermocouples installed in strategic points along hydraulic circuit. The behavior of the natural circulation phenomenon was monitored by graphical interface on computer screen, showing the temperature evolutions of measuring points and results stored in digital spreadsheets. The results stored in digital spreadsheets allowed the getting of data to graphic construction and discussion about natural circulation phenomenon. Finally, the calculus of Reynolds number allowed the establishment for a correlation of friction in function of geometric scales of length, heights and cross section of tubing, considering a natural circulation flow throughout in the region of hot leg. (author)

  10. A deadtime reduction circuit for thermal neutron coincidence counters with Amptek preamplifiers

    International Nuclear Information System (INIS)

    Bourret, S.C.; Krick, M.S.

    1994-01-01

    We have developed a deadtime reduction circuit for thermal neutron coincidence counters using Amptek preamplifier/amplifier/discriminator circuits. The principle is to remove the overlap between the output pulses from the Amptek circuits by adding a derandomizer between the Amptek circuits and the shift-register coincidence electronics. We implemented the derandomizer as an Actel programmable logic array; the derandomizer board is small and can be mounted in the high-voltage junction box with the Amptek circuits, if desired. Up to 32 Amptek circuits can be used with one derandomizer. The derandomizer has seven outputs: four groups of eight inputs, two groups of 16 inputs, and one group of 32 inputs. We selected these groupings to facilitate detector ring-ratio measurements. The circuit was tested with the five-ring research multiplicity counter, which has five output signals-one for each ring. The counter's deadtime was reduced from 70 to 30 ns

  11. Demodulation Radio Frequency Interference Effects in Operational Amplifier Circuits

    Science.gov (United States)

    Sutu, Yue-Hong

    A series of investigations have been carried out to determine RFI effects in analog circuits using monolithic integrated operational amplifiers (op amps) as active devices. The specific RFI effect investigated is how amplitude-modulated (AM) RF signals are demodulated in op amp circuits to produce undesired low frequency responses at AM-modulation frequency. The undesired demodulation responses were shown to be characterized by a second-order nonlinear transfer function. Four representative op amp types investigated were the 741 bipolar op amp, the LM10 bipolar op amp, the LF355 JFET-Bipolar op amp, and the CA081 MOS-Bipolar op amp. Two op amp circuits were investigated. The first circuit was a noninverting unity voltage gain buffer circuit. The second circuit was an inverting op amp configuration. In the second circuit, the investigation includes the effects of an RFI suppression capacitor in the feedback path. Approximately 30 units of each op amp type were tested to determine the statistical variations of RFI demodulation effects in the two op amp circuits. The Nonlinear Circuit Analysis Program, NCAP, was used to simulate the demodulation RFI response. In the simulation, the op amp was replaced with its incremental macromodel. Values of macromodel parameters were obtained from previous investigations and manufacturer's data sheets. Some key results of this work are: (1) The RFI demodulation effects are 10 to 20 dB lower in CA081 and LF355 FET-bipolar op amp than in 741 and LM10 bipolar op amp except above 40 MHz where the LM10 RFI response begins to approach that of CA081. (2) The experimental mean values for 30 741 op amps show that RFI demodulation responses in the inverting amplifier with a 27 pF feedback capacitor were suppressed from 10 to 35 dB over the RF frequency range 0.1 to 150 MHz except at 0.15 MHz where only 3.5 dB suppression was observed. (3) The NCAP program can predict RFI demodulation responses in 741 and LF355 unity gain buffer circuits

  12. Integrated digital superconducting logic circuits for the quantum synthesizer. Report

    International Nuclear Information System (INIS)

    Buchholz, F.I.; Kohlmann, J.; Khabipov, M.; Brandt, C.M.; Hagedorn, D.; Balashov, D.; Maibaum, F.; Tolkacheva, E.; Niemeyer, J.

    2006-11-01

    electronics/semiconductor electronics RSFQ voltage amplifiers were realized on the base of SQUID stacks. At 8-stage serial voltage drivers the voltage pulses could be amplified at the exit on the aimed amplitude values of above 400 μV at simultaneous exit-impedance increasement on about 9 Ω. Besides a manifold of test circuits was developed anf fabricated, by which the function of the developed construction elements as well as the further development of the technology process could be studied. In measurements at the IPHT performed commonly with project partners in a demonstator arrangement of the multichip module of the quantum synthesized correct digital function and signal processing by an integrated RSFQ monitor circuit with subsequent semiconductor pulse amplifier were successfully proved

  13. Simulation and experimental study on lithium ion battery short circuit

    International Nuclear Information System (INIS)

    Zhao, Rui; Liu, Jie; Gu, Junjie

    2016-01-01

    Highlights: • Both external and internal short circuit tests were performed on Li-ion batteries. • An electrochemical–thermal model with an additional nail site heat source is presented. • The model can accurately simulate the temperature variations of non-venting batteries. • The model is reliable in predicting the occurrence and start time of thermal runaway. • A hydrogel cooling system proves its strength in preventing battery thermal runaway. - Abstract: Safety is the first priority in lithium ion (Li-ion) battery applications. A large portion of electrical and thermal hazards caused by Li-ion battery is associated with short circuit. In this paper, both external and internal short circuit tests are conducted. Li-ion batteries and battery packs of different capacities are used. The results indicate that external short circuit is worse for smaller size batteries due to their higher internal resistances, and this type of short can be well managed by assembling fuses. In internal short circuit tests, higher chance of failure is found on larger capacity batteries. A modified electrochemical–thermal model is proposed, which incorporates an additional heat source from nail site and proves to be successful in depicting temperature changes in batteries. Specifically, the model is able to estimate the occurrence and approximate start time of thermal runaway. Furthermore, the effectiveness of a hydrogel based thermal management system in suppressing thermal abuse and preventing thermal runaway propagation is verified through the external and internal short tests on batteries and battery packs.

  14. Logic circuits from zero forcing.

    Science.gov (United States)

    Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

    We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

  15. Installations having pressurised fluid circuits

    International Nuclear Information System (INIS)

    Rigg, S.; Grant, J.

    1977-01-01

    Reference is made to nuclear installations having pressurised coolant flow circuits. Breaches in such circuits may quickly result in much damage to the plant. Devices such as non-return valves, orifice plates, and automatically operated shut-off valves have been provided to prevent or reduce fluid flow through a breached pipe line, but such devices have several disadvantages; they may present large restrictions to normal flow of coolant, and may depend on the operation of ancillary equipment, with consequent delay in bringing them into operation in an emergency. Other expedients that have been adopted to prevent or reduce reverse flow through an upstream breach comprise various forms of hydraulic counter flow brakes. The arrangement described has at least one variable fluid brake comprising a fluidic device connected into a duct in the pressurised circuit, the device having an inlet, an outlet, a vortex chamber between the inlet and outlet, a control jet for introducing fluid into the vortex chamber, connections communicating the inlet and the outlet into one part of the circuit and the control jet into another region at a complementary pressure so that, in the event of a breach in the circuit in one region, fluid passes from the other region to enter the vortex chamber to stimulate pressure to create a flow restricting vortex in the chamber that reduces flow through the breach. The system finds particular application to stream generating pressure tube reactors, such as the steam generating heavy water reactor at UKAEA, Winfrith. (U.K.)

  16. 30 CFR 75.601-1 - Short circuit protection; ratings and settings of circuit breakers.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit protection; ratings and settings... Trailing Cables § 75.601-1 Short circuit protection; ratings and settings of circuit breakers. Circuit breakers providing short circuit protection for trailing cables shall be set so as not to exceed the...

  17. 30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

    Science.gov (United States)

    2010-07-01

    ... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

  18. 30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

    Science.gov (United States)

    2010-07-01

    ... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

  19. Circuit reliability boosted by soldering pins of disconnect plugs to sockets

    Science.gov (United States)

    Pierce, W. B.

    1964-01-01

    Where disconnect pins must be used for wiring and testing a circuit, improved system reliability is obtained by making a permanent joint between pins and sockets of the disconnect plug. After the circuit has been tested, contact points may be fused through soldering, brazing, or welding.

  20. Experimental and theoretical analysis of vacuum circuit breaker prestrike effect on a transformer

    NARCIS (Netherlands)

    Popov, M.; Smeets, R.P.P.; Van der Sluis, L.; De Herdt, H.; Declerq, J.

    2009-01-01

    The work presented in this paper deals with the investigation of circuit breaker prestrike effect that occurs during energizing a distribution transformer. An experimental test setup that consists of a supply transformer, a vacuum circuit breaker (VCB), a cable and a test transformer is built, and

  1. Single-event effects in analog and mixed-signal integrated circuits

    International Nuclear Information System (INIS)

    Turflinger, T.L.

    1996-01-01

    Analog and mixed-signal integrated circuits are also susceptible to single-event effects, but they have rarely been tested. Analog circuit single-particle transients require modified test techniques and data analysis. Existing work is reviewed and future concerns are outlined

  2. Wiring of electronic evaluation circuits

    International Nuclear Information System (INIS)

    Bauer, R.; Svoboda, Z.

    1977-01-01

    The wiring is described of electronic evaluation circuits for the automatic viewing of photographic paper strip negatives on which line tracks with an angular scatter relative to the spectrograph longitudinal axis were recorded during the oblique flight of nuclear particles during exposure in the spectrograph. In coincidence evaluation, the size of the angular scatter eventually requires that evaluation dead time be increased. The equipment consists of minimally two fixed registers and a block of logic circuits whose output is designed such as will allow connection to equipment for recording signals corresponding to the number of tracks on the film. The connection may be implemented using integrated circuits guaranteeing high operating reliability and life. (J.B.)

  3. Counterpulse railgun energy recovery circuit

    International Nuclear Information System (INIS)

    Honig, E.M.

    1986-01-01

    This patent describes a counterpulse railgun energy recovery circuit for propelling a projectile along a railgun the counterpulse railgun energy recovery circuit consists of: a railgun having an effective inductance; a source inductor initially charged to an initial current; current means for initially charging the source inductor to the initial current; first current-zero type switching means; second current-zero type switching; third current-zero type switching; muzzle current-zero type switching means; transfer capacitor, the transfer capacitor is for cooperating with the first, second, third, and muzzle current-zero type switching means for providing a resonant circuit for transferring current from the source inductor to the effective inductance of the railgun during the propelling of a projectile along the railgun and for returning current from the effective inductance of the railgun to the source inductance after the projectile has exited the railgun

  4. Vertically Integrated Circuits at Fermilab

    International Nuclear Information System (INIS)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  5. Soft errors from particles to circuits

    CERN Document Server

    Autran, Jean-Luc

    2015-01-01

    ""Soft Errors: From Particles to Circuits covers all aspects of the design, use, application, performance, and testing of parts, devices, and systems and addresses every perspective from an engineering, scientific, or physical point of view. … Many good texts have been written on similar subjects, but none as thorough, as clear, and as complete as this volume. … [The authors] have mastered the past, absorbed the present, and captured the trends of the future in one of the most important technologies of our time. … An extremely useful text that has succeeded in presenting wit

  6. Accelerating functional verification of an integrated circuit

    Science.gov (United States)

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  7. Fermionic models with superconducting circuits

    Energy Technology Data Exchange (ETDEWEB)

    Las Heras, Urtzi; Garcia-Alvarez, Laura; Mezzacapo, Antonio; Lamata, Lucas [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); Solano, Enrique [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); IKERBASQUE, Basque Foundation for Science, Bilbao (Spain)

    2015-12-01

    We propose a method for the efficient quantum simulation of fermionic systems with superconducting circuits. It consists in the suitable use of Jordan-Wigner mapping, Trotter decomposition, and multiqubit gates, be with the use of a quantum bus or direct capacitive couplings. We apply our method to the paradigmatic cases of 1D and 2D Fermi-Hubbard models, involving couplings with nearest and next-nearest neighbours. Furthermore, we propose an optimal architecture for this model and discuss the benchmarking of the simulations in realistic circuit quantum electrodynamics setups. (orig.)

  8. Circuit modeling for electromagnetic compatibility

    CERN Document Server

    Darney, Ian B

    2013-01-01

    Very simply, electromagnetic interference (EMI) costs money, reduces profits, and generally wreaks havoc for circuit designers in all industries. This book shows how the analytic tools of circuit theory can be used to simulate the coupling of interference into, and out of, any signal link in the system being reviewed. The technique is simple, systematic and accurate. It enables the design of any equipment to be tailored to meet EMC requirements. Every electronic system consists of a number of functional modules interconnected by signal links and power supply lines. Electromagnetic interference

  9. Relative ultrasound energy measurement circuit

    OpenAIRE

    Gustafsson, E.Martin I.; Johansson, Jonny; Delsing, Jerker

    2005-01-01

    A relative ultrasound energy estimation circuit has been designed in a standard 0.35-μm CMOS process, to be a part of a thumb size internet connected wireless ultrasound measurement system. This circuit measures the relative energy between received ultrasound pulses, and presents an output signal that is linear to the received energy. Post-layout simulations indicate 7 bit linearity for 500 mV input signals, 5 μsec startup and stop times, 2.6 mW power consumption during active state. The acti...

  10. Simplified design of filter circuits

    CERN Document Server

    Lenk, John

    1999-01-01

    Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets

  11. Programming languages for circuit design.

    Science.gov (United States)

    Pedersen, Michael; Yordanov, Boyan

    2015-01-01

    This chapter provides an overview of a programming language for Genetic Engineering of Cells (GEC). A GEC program specifies a genetic circuit at a high level of abstraction through constraints on otherwise unspecified DNA parts. The GEC compiler then selects parts which satisfy the constraints from a given parts database. GEC further provides more conventional programming language constructs for abstraction, e.g., through modularity. The GEC language and compiler is available through a Web tool which also provides functionality, e.g., for simulation of designed circuits.

  12. Endogenous money, circuits and financialization

    OpenAIRE

    Malcolm Sawyer

    2013-01-01

    This paper locates the endogenous money approach in a circuitist framework. It argues for the significance of the credit creation process for the evolution of the economy and the absence of any notion of ‘neutrality of money’. Clearing banks are distinguished from other financial institutions as the providers of initial finance in a circuit whereas other financial institutions operate in a final finance circuit. Financialization is here viewed in terms of the growth of financial assets an...

  13. Design and implementation of JOM-3 Overhauser magnetometer analog circuit

    Science.gov (United States)

    Zhang, Xiao; Jiang, Xue; Zhao, Jianchang; Zhang, Shuang; Guo, Xin; Zhou, Tingting

    2017-09-01

    Overhauser magnetometer, a kind of static-magnetic measurement system based on the Overhauser effect, has been widely used in archaeological exploration, mineral resources exploration, oil and gas basin structure detection, prediction of engineering exploration environment, earthquakes and volcanic eruotions, object magnetic measurement and underground buried booty exploration. Overhauser magnetometer plays an important role in the application of magnetic field measurement for its characteristics of small size, low power consumption and high sensitivity. This paper researches the design and the application of the analog circuit of JOM-3 Overhauser magnetometer. First, the Larmor signal output by the probe is very weak. In order to obtain the signal with high signal to noise rstio(SNR), the design of pre-amplifier circuit is the key to improve the quality of the system signal. Second, in this paper, the effectual step which could improve the frequency characters of bandpass filter amplifier circuit were put forward, and theoretical analysis was made for it. Third, the shaping circuit shapes the amplified sine signal into a square wave signal which is suitable for detecting the rising edge. Fourth, this design elaborated the optimized choice of tuning circuit, so the measurement range of the magnetic field can be covered. Last, integrated analog circuit testing system was formed to detect waveform of each module. By calculating the standard deviation, the sensitivity of the improved Overhauser magnetometer is 0.047nT for Earth's magnetic field observation. Experimental results show that the new magnetometer is sensitive to earth field measurement.

  14. Implementation of Chua's circuit using simulated inductance

    Science.gov (United States)

    Gopakumar, K.; Premlet, B.; Gopchandran, K. G.

    2011-05-01

    In this study we describe how to build an inductorless version of the classic Chua's circuit. A suitable inductor for Chua's circuit is often hard to procure. The required inductor for the circuit is designed using simple circuit elements such as resistors, capacitors and operational amplifiers. The complete circuit can be implemented by using off-the-shelf components, and it can readily be integrated on a single chip. This design of Chua's circuit allows the original dynamics to be slowed down to just a few hertz, enabling implementation of sophisticated control schemes without severe time restrictions. Another novel feature of the circuit is that losses associated with capacitors due to leakages can easily be compensated by providing negative resistance using the same setup. The chaotic behaviour of the circuit is verified by PSpice and Multisim simulation and also by experimental study on a circuit breadboard. The results give excellent agreement with each other and with the results of previous investigators.

  15. Application of reliability analysis methods to the comparison of two safety circuits

    International Nuclear Information System (INIS)

    Signoret, J.-P.

    1975-01-01

    Two circuits of different design, intended for assuming the ''Low Pressure Safety Injection'' function in PWR reactors are analyzed using reliability methods. The reliability analysis of these circuits allows the failure trees to be established and the failure probability derived. The dependence of these results on test use and maintenance is emphasized as well as critical paths. The great number of results obtained may allow a well-informed choice taking account of the reliability wanted for the type of circuits [fr

  16. Advanced circuit simulation using Multisim workbench

    CERN Document Server

    Báez-López, David; Cervantes-Villagómez, Ofelia Delfina

    2012-01-01

    Multisim is now the de facto standard for circuit simulation. It is a SPICE-based circuit simulator which combines analog, discrete-time, and mixed-mode circuits. In addition, it is the only simulator which incorporates microcontroller simulation in the same environment. It also includes a tool for printed circuit board design.Advanced Circuit Simulation Using Multisim Workbench is a companion book to Circuit Analysis Using Multisim, published by Morgan & Claypool in 2011. This new book covers advanced analyses and the creation of models and subcircuits. It also includes coverage of transmissi

  17. Digital circuit boards mach 1 GHz

    CERN Document Server

    Morrison, Ralph

    2012-01-01

    A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

  18. Clocking Scheme for Switched-Capacitor Circuits

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    1998-01-01

    A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed.......A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed....

  19. Unbalanced Neuronal Circuits in Addiction

    OpenAIRE

    Volkow, Nora D.; Wang, Gen-Jack; Tomasi, Dardo; Baler, Ruben D.

    2013-01-01

    Through sequential waves of drug-induced neurochemical stimulation, addiction co-opts the brain's neuronal circuits that mediate reward, motivation, , to behavioral inflexibility and a severe disruption of self-control and compulsive drug intake. Brain imaging technologies have allowed neuroscientists to map out the neural landscape of addiction in the human brain and to understand how drugs modify it.

  20. A Low Noise Electronic Circuit

    NARCIS (Netherlands)

    Annema, Anne J.; Leenaerts, Dominicus M.W.; de Vreede, Petrus W.H.

    2002-01-01

    An electronic circuit, which can be used as a Low Noise Amplifier (LNA), comprises two complementary Field Effect Transistors (M1, M2; M5, M6), each having a gate, a source and a drain. The gates are connected together as a common input terminal, and the drains are connected together as a

  1. Circuit design for RF transceivers

    CERN Document Server

    Leenaerts, Domine; Vaucher, Cicero S

    2007-01-01

    Second edition of this successful 2001 RF Circuit Design book, has been updated, latest technology reviews have been added as well as several actual case studies. Due to the authors being active in industry as well as academia, this should prove to be an essential guide on RF Transceiver Design for students and engineers.

  2. Integrated Circuit Stellar Magnitude Simulator

    Science.gov (United States)

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  3. Simulated annealing and circuit layout

    NARCIS (Netherlands)

    Aarts, E.H.L.; Laarhoven, van P.J.M.

    1991-01-01

    We discuss the problem of approximately sotvlng circuit layout problems by simulated annealing. For this we first summarize the theoretical concepts of the simulated annealing algorithm using Ihe theory of homogeneous and inhomogeneous Markov chains. Next we briefly review general aspects of the

  4. Inductive energy storage using high voltage vacuum circuit breakers

    International Nuclear Information System (INIS)

    McCann, R.B.; Woodson, H.H.; Mukutmoni, T.

    1976-01-01

    Controlled thermonuclear fusion experiments currently being planned require large amounts of pulsed energy. Inductive energy storage systems (IES) appear to be attractive for at least two applications in the fusion research program: high beta devices and those employing turbulent heating. The well-known roadblock to successful implementation of IES is the development of a reliable and cost-effective off-switch capable of handling high currents and withstanding high recovery voltages. The University of Texas at Austin has a program to explore the application of conventional vacuum circuit breakers designed for use in AC systems, in conjunction with appropriate counter pulse circuits, as off-switches in inductive energy storage systems. The present paper describes the IES employing vacuum circuit breakers as off-switches. Since the deionization property of these circuit breakers is of great importance to the design and the cost of the counter-pulse circuit, a synthetic test installation to test these breakers has been conceived, designed and is being installed in the Fusion Research Center, University of Texas at Austin. Some design aspects of the facility will be discussed here. Finally, the results of the study on a mathematical model developed and optimized to determine the least cost system which meets both the requirements of an off-switch for IES Systems and the ratings of circuit breakers used in power systems has been discussed. This analysis indicates that the most important factor with respect to the system cost is the derating of the circuit breakers to obtain satisfactory lifetimes

  5. Simulation of worst-case operating conditions for integrated circuits operating in a total dose environment

    International Nuclear Information System (INIS)

    Bhuva, B.L.

    1987-01-01

    Degradations in the circuit performance created by the radiation exposure of integrated circuits are so unique and abnormal that thorough simulation and testing of VLSI circuits is almost impossible, and new ways to estimate the operating performance in a radiation environment must be developed. The principal goal of this work was the development of simulation techniques for radiation effects on semiconductor devices. The mixed-mode simulation approach proved to be the most promising. The switch-level approach is used to identify the failure mechanisms and critical subcircuits responsible for operational failure along with worst-case operating conditions during and after irradiation. For precise simulations of critical subcircuits, SPICE is used. The identification of failure mechanisms enables the circuit designer to improve the circuit's performance and failure-exposure level. Identification of worst-case operating conditions during and after irradiation reduces the complexity of testing VLSI circuits for radiation environments. The results of test circuits for failure simulations using a conventional simulator and the new simulator showed significant time savings using the new simulator. The savings in simulation time proved to be circuit topology-dependent. However, for large circuits, the simulation time proved to be orders of magnitude smaller than simulation time for conventional simulators

  6. Multiple Soft Fault Diagnosis of Bjt Circuits

    Directory of Open Access Journals (Sweden)

    Tadeusiewicz Michał

    2014-12-01

    Full Text Available This paper deals with multiple soft fault diagnosis of nonlinear analog circuits comprising bipolar transistors characterized by the Ebers-Moll model. Resistances of the circuit and beta forward factor of a transistor are considered as potentially faulty parameters. The proposed diagnostic method exploits a strongly nonlinear set of algebraic type equations, which may possess multiple solutions, and is capable of finding different sets of the parameters values which meet the diagnostic test. The equations are written on the basis of node analysis and include DC voltages measured at accessible nodes, as well as some measured currents. The unknown variables are node voltages and the parameters which are considered as potentially faulty. The number of these parameters is larger than the number of the accessible nodes. To solve the set of equations the block relaxation method is used with different assignments of the variables to the blocks. Next, the solutions are corrected using the Newton-Raphson algorithm. As a result, one or more sets of the parameters values which satisfy the diagnostic test are obtained. The proposed approach is illustrated with a numerical example.

  7. Crossed SMPS MOSFET-based protection circuit for high frequency ultrasound transceivers and transducers.

    Science.gov (United States)

    Choi, Hojong; Shung, K Kirk

    2014-06-12

    The ultrasonic transducer is one of the core components of ultrasound systems, and the transducer's sensitivity is significantly related the loss of electronic components such as the transmitter, receiver, and protection circuit. In an ultrasonic device, protection circuits are commonly used to isolate the electrical noise between an ultrasound transmitter and transducer and to minimize unwanted discharged pulses in order to protect the ultrasound receiver. However, the performance of the protection circuit and transceiver obviously degrade as the operating frequency or voltage increases. We therefore developed a crossed SMPS (Switching Mode Power Supply) MOSFET-based protection circuit in order to maximize the sensitivity of high frequency transducers in ultrasound systems.The high frequency pulse signals need to trigger the transducer, and high frequency pulse signals must be received by the transducer. We therefore selected the SMPS MOSFET, which is the main component of the protection circuit, to minimize the loss in high frequency operation. The crossed configuration of the protection circuit can drive balanced bipolar high voltage signals from the pulser and transfer the balanced low voltage echo signals from the transducer. The equivalent circuit models of the SMPS MOSFET-based protection circuit are shown in order to select the proper device components. The schematic diagram and operation mechanism of the protection circuit is provided to show how the protection circuit is constructed. The P-Spice circuit simulation was also performed in order to estimate the performance of the crossed MOSFET-based protection circuit. We compared the performance of our crossed SMPS MOSFET-based protection circuit with a commercial diode-based protection circuit. At 60 MHz, our expander and limiter circuits have lower insertion loss than the commercial diode-based circuits. The pulse-echo test is typical method to evaluate the sensitivity of ultrasonic transducers

  8. Utilization of process TEG for fabrication of HTS circuits

    International Nuclear Information System (INIS)

    Hato, T.; Okada, Y.; Maruyama, M.; Suzuki, H.; Wakana, H.; Adachi, S.; Kawabe, U.; Tanabe, K.

    2006-01-01

    We improved the fabrication process of high-temperature superconducting (HTS) sampler circuits with multilayer structures by utilizing a test elements group (TEG). Among a lot of difficulties in the HTS circuit fabrication process, loss of oxygen is one of the most significant problems. Since the film transition temperature (T c ) has a strong relationship with the resistance at room temperature, we fabricated a test pattern on the same wafer of the circuits and measured the resistance at room temperature by using a prober to estimate the T c of each layer. By introducing the measurement of the normal resistance after each process, we found better process conditions without a T c drop. Moreover, we constructed a low-temperature probing system, in which we can measure the junction TEG. The system enabled feedback of the fabrication condition soon after the junction process. The utilization of the process TEG contributed to reproducible fabrication of HTS circuits and that is a promising advance of the HTS circuit technology

  9. The voltage—current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

    International Nuclear Information System (INIS)

    Bao Bo-Cheng; Feng Fei; Dong Wei; Pan Sai-Hu

    2013-01-01

    A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage—current relationships (VCRs) between two parallel memristive circuits — a parallel memristor and capacitor circuit (the parallel MC circuit), and a parallel memristor and inductor circuit (the parallel ML circuit) — are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and experimental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results

  10. Test

    DEFF Research Database (Denmark)

    Bendixen, Carsten

    2014-01-01

    Bidrag med en kortfattet, introducerende, perspektiverende og begrebsafklarende fremstilling af begrebet test i det pædagogiske univers.......Bidrag med en kortfattet, introducerende, perspektiverende og begrebsafklarende fremstilling af begrebet test i det pædagogiske univers....

  11. Fabric circuits and method of manufacturing fabric circuits

    Science.gov (United States)

    Chu, Andrew W. (Inventor); Dobbins, Justin A. (Inventor); Scully, Robert C. (Inventor); Trevino, Robert C. (Inventor); Lin, Greg Y. (Inventor); Fink, Patrick W. (Inventor)

    2011-01-01

    A flexible, fabric-based circuit comprises a non-conductive flexible layer of fabric and a conductive flexible layer of fabric adjacent thereto. A non-conductive thread, an adhesive, and/or other means may be used for attaching the conductive layer to the non-conductive layer. In some embodiments, the layers are attached by a computer-driven embroidery machine at pre-determined portions or locations in accordance with a pre-determined attachment layout before automated cutting. In some other embodiments, an automated milling machine or a computer-driven laser using a pre-designed circuit trace as a template cuts the conductive layer so as to separate an undesired portion of the conductive layer from a desired portion of the conductive layer. Additional layers of conductive fabric may be attached in some embodiments to form a multi-layer construct.

  12. Investigation of Equivalent Circuit for PEMFC Assessment

    International Nuclear Information System (INIS)

    Myong, Kwang Jae

    2011-01-01

    Chemical reactions occurring in a PEMFC are dominated by the physical conditions and interface properties, and the reactions are expressed in terms of impedance. The performance of a PEMFC can be simply diagnosed by examining the impedance because impedance characteristics can be expressed by an equivalent electrical circuit. In this study, the characteristics of a PEMFC are assessed using the AC impedance and various equivalent circuits such as a simple equivalent circuit, equivalent circuit with a CPE, equivalent circuit with two RCs, and equivalent circuit with two CPEs. It was found in this study that the characteristics of a PEMFC could be assessed using impedance and an equivalent circuit, and the accuracy was highest for an equivalent circuit with two CPEs

  13. Sustainability issues in circuit board recycling

    DEFF Research Database (Denmark)

    Legarth, Jens Brøbech; Alting, Leo; Baldo, Gian Luca

    1995-01-01

    The resource recovery and environmental impact issues of printed circuit board recycling by secondary copper smelters are discussed. Guidelines concerning material selection for circuit board manufacture and concerning the recycling processes are given to enhance recovery efficiency and to lower...

  14. Developing a Domain Model for Relay Circuits

    DEFF Research Database (Denmark)

    Haxthausen, Anne Elisabeth

    2009-01-01

    In this paper we stepwise develop a domain model for relay circuits as used in railway control systems. First we provide an abstract, property-oriented model of networks consisting of components that can be glued together with connectors. This model is strongly inspired by a network model...... for railways madeby Bjørner et.al., however our model is more general: the components can be of any kind and can later be refined to e.g. railway components or circuit components. Then we show how the abstract network model can be refined into an explicit model for relay circuits. The circuit model describes...... the statics as well as the dynamics of relay circuits, i.e. how a relay circuit can be composed legally from electrical components as well as how the components may change state over time. Finally the circuit model is transformed into an executable model, and we show how a concrete circuit can be defined...

  15. Telecommunications Circuit Allocation Programs - Kansas City Area

    National Research Council Canada - National Science Library

    Thomas, William

    1994-01-01

    The overall objective of the audit was to determine whether DoD circuit allocation programs identified and used the most effective configurations for leased long-haul, special-purpose telecommunications circuits...

  16. Circuit QED lattices: Towards quantum simulation with superconducting circuits

    Energy Technology Data Exchange (ETDEWEB)

    Schmidt, Sebastian [Institute for Theoretical Physics, ETH Zurich, 8093, Zurich (Switzerland); Koch, Jens [Department of Physics and Astronomy, Northwestern University, Evanston, IL, 60208 (United States)

    2013-06-15

    The Jaynes-Cummings model describes the coupling between photons and a single two-level atom in a simplified representation of light-matter interactions. In circuit QED, this model is implemented by combining microwave resonators and superconducting qubits on a microchip with unprecedented experimental control. Arranging qubits and resonators in the form of a lattice realizes a new kind of Hubbard model, the Jaynes-Cummings-Hubbard model, in which the elementary excitations are polariton quasi-particles. Due to the genuine openness of photonic systems, circuit QED lattices offer the possibility to study the intricate interplay of collective behavior, strong correlations and non-equilibrium physics. Thus, turning circuit QED into an architecture for quantum simulation, i.e., using a well-controlled system to mimic the intricate quantum behavior of another system too daunting for a theorist to tackle head-on, is an exciting idea which has served as theorists' playground for a while and is now also starting to catch on in experiments. This review gives a summary of the most recent theoretical proposals and experimental efforts. (copyright 2013 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  17. Polarization Control for Silicon Photonic Circuits

    Science.gov (United States)

    Caspers, Jan Niklas

    In recent years, the field of silicon photonics has received much interest from researchers and companies across the world. The idea is to use photons to transmit information on a computer chip in order to increase computational speed while decreasing the power required for computation. To allow for communication between the chip and other components, such as the computer memory, these silicon photonics circuits need to be interfaced with optical fiber. Unfortunately, in order to interface an optical fiber with an integrated photonics circuit two major challenges need to be overcome: a mode-size mismatch as well as a polarization mismatch. While the problem of mode-size has been well investigated, the polarization mismatch has yet to be addressed. In order to solve the polarization mismatch one needs to gain control over the polarization of the light in a waveguide. In this thesis, I will present the components required to solve the polarization mismatch. Using a novel wave guiding structure, the hybrid plasmonic waveguide, an ultra-compact polarization rotator is designed, fabricated, and tested. The hybrid plasmonic rotator has a performance similar to purely dielectric rotators while being more than an order of magnitude smaller. Additionally, a broadband hybrid plasmonic coupler is designed and measured. This coupler has a performance similar to dielectric couplers while having a footprint an order of magnitude smaller. Finally, a system solution to the polarization mismatch is provided. The system, a polarization adapter, matches the incoming changing polarization from the fiber actively to the correct one of the silicon photonics circuit. The polarization adapter is demonstrated experimentally to prove its operation. This proof is based on dielectric components, but the aforementioned hybrid plasmonic waveguide components would make the system more compact.

  18. What's new about generator circuit breakers

    International Nuclear Information System (INIS)

    Kolarik, P.L.

    1979-01-01

    The need for updating ANSI C37 Standards for AC high-voltage circuit breakers has become necessary because of the increased interest in power circuit breakers for generator application. These circuit breakers, which have continuous current ratings and rated short-circuit currents that are much higher than those presently covered by existing C37 Standards, take on added importance because they are being installed in critical AC power supplies at nuclear power stations

  19. Trip electrical circuit of the gyrotion

    International Nuclear Information System (INIS)

    Rossi, J.O.

    1987-09-01

    The electron cyclotron resonance heating system of INPE/LAP is shown and the trip electrical circuit of the gyrotron is described, together with its fundamental aspects. The trip electrical circuit consists basically of a series regulator circuit which regulates the output voltage level and controls the pulse width time. Besides that, a protection circuit for both tubes, regulator and gyrotron, against faults in the system. (author) [pt

  20. Hybdrid integral circuit for proportional chambers

    International Nuclear Information System (INIS)

    Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

    1978-01-01

    Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

  1. A Fault Tolerant Integrated Circuit Memory

    OpenAIRE

    Barton, Anthony Francis

    1980-01-01

    Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity. A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufa...

  2. An ADC-free adaptive interface circuit of resistive sensor for electronic nose system.

    Science.gov (United States)

    Chang, Chia-Lin; Chiu, Shih-Wen; Tang, Kea-Tiong

    2013-01-01

    The initial resistance of chemiresistive gas sensors could be affected by temperature, humidity, and background odors. In a sensing system, the traditional interface circuit always requires an ADC to convert analog signal to digital signal. In this paper, we propose an ADC-free adaptive interface circuit for a resistive gas sensor to read sensor signal and cancel the baseline drift. Furthermore, methanol was used to test the proposed interface circuit, which was connected with a FIGARO® gas sensor. This circuit was fabricated by TSMC 0.18 µm CMOS process, and consumed 86.41 µW under 1 V supply voltage.

  3. A high speed, wide dynamic range digitizer circuit for photomultiplier tubes

    International Nuclear Information System (INIS)

    Yarema, R.J.; Foster, G.W.; Knickerbocker, K.; Sarraj, M.; Tschirhart, R.; Whitmore, J.; Zimmerman, T.; Lindgren, M.

    1995-01-01

    A circuit has been designed for digitizing PMT signals over a wide dynamic range (17-18 bits) with 8 bits of resolution at rates up to 53 MHz. Output from the circuit is in a floating point format with a 4 bit exponent and an 8 bit mantissa. The heart of the circuit is a full custom integrated circuit called the QIE (Charge Integrator and Encoder). The design of the QIE and associated circuitry reported here permits operation over a 17 bit dynamic range. Test results of a multirange device are presented for the first time. (orig.)

  4. High accuracy digital aging monitor based on PLL-VCO circuit

    International Nuclear Information System (INIS)

    Zhang Yuejun; Jiang Zhidi; Wang Pengjun; Zhang Xuelong

    2015-01-01

    As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm 2 . After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%. (semiconductor integrated circuits)

  5. Circuit card failures and industry mitigation strategy

    Energy Technology Data Exchange (ETDEWEB)

    Mondal, U. [Candu Owners Group, Toronto, Ontario (Canada)

    2012-07-01

    In recent years the nuclear industry has experienced an increase in circuit card failures due to ageing of components, inadequate Preventive Maintenance (PM), lack of effective circuit card health monitoring, etc. Circuit card failures have caused loss of critical equipment, e.g., electro hydraulic governors, Safety Systems, resulting in loss of function and in some cases loss of generation. INPO completed a root cause analysis of 40 Reactor Trips/Scrams in US reactors and has recommended several actions to mitigate Circuit Card failures. Obsolescence of discrete components has posed many challenges in conducting effective preventative maintenance on circuit cards. In many cases, repairs have resulted in installation of components that compromise performance of the circuit cards. Improper termination and worn edge connectors have caused intermittent contacts contributing to circuit card failures. Traditionally, little attention is paid to relay functions and preventative maintenance of relay. Relays contribute significantly to circuit card failures and have dominated loss of generation across the power industry. The INPO study recommended a number of actions to mitigate circuit card failures, such as; identification of critical components and single point vulnerabilities; strategic preventative maintenance; protection of circuit boards against electrostatic discharge; limiting power cycles; performing an effective burn-in prior to commissioning of the circuit cards; monitoring performance of DC power supplies; limiting cabinet temperatures; managing of component aging/degradation mechanism, etc. A subcommittee has been set up under INPO sponsorship to understand the causes of circuit card failure and to develop an effective mitigation strategy. (author)

  6. Improvements in or relating to transistor circuits

    International Nuclear Information System (INIS)

    Richards, R.F.; Williamson, P.W.

    1978-01-01

    This invention relates to transistor circuits and in particular to integrated transistor circuits formed on a substrate of semi-conductor material such as silicon. The invention is concerned with providing integrated circuits in which malfunctions caused by the effects of ionising, e.g. nuclear, radiations are reduced. (author)

  7. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  8. Piezo pump and pressurized circuit provided therewith

    NARCIS (Netherlands)

    Van Es, Johannes; Wits, Wessel Willems

    2015-01-01

    A piezo pump for use in a pressurized circuit includes a pump chamber with an inlet provided with a one way inlet valve, for connection to a feeding line of the pressurized circuit and an outlet provided with a one way outlet valve, for connection to a discharge line of the pressurized circuit and a

  9. 49 CFR 236.721 - Circuit, control.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Circuit, control. 236.721 Section 236.721..., MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Definitions § 236.721 Circuit, control. An electrical circuit between a source of electric energy and a device which it operates. ...

  10. 80 K - Helium circuit with innovative, gas-bearing, oil-free turbo compressor. Conception, realization, commissioning and test of the 80 K refrigeration supply for the superconducting electron source at HZB; 80 K - Helium-Kreis mit innovativem, gasgelagertem, oelfreiem Turbokompressor. Konzeption, Realisierung, Inbetriebnahme und Test der 80 K-Kaelteversorgung fuer die supraleitenden Elektronenquelle am HZB

    Energy Technology Data Exchange (ETDEWEB)

    Gloeckner, Felix [Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbH, Berlin (Germany)

    2017-07-01

    The system presented in this paper supplies the test module for the superconducting electron source (GunLab) at the Helmholtz-Zentrum Berlin (HZB) with 500 W cooling capacity at 80 K.Since direct evaporation of liquid nitrogen in the module is not desirable for safety reasons, the system operates with an intermediate helium circuit. In order to use not only the latent cold of liquid nitrogen, but also the sensitive component, a new concept consisting of a dual heat exchanger and a bath cryostat is used. The coldbox also contains an adjustable bypass with integrated electric heater for test purposes.A new type of warm compressor is used to circulate the helium. The turbo compressor is oil-free, gas-stored and in helium-tight semi-hermetic design. In order to take advantage of these unique properties, Fischer Engineering AG has adapted the turbo compressor for use with helium.The paper concludes with a test of the system and an insight into the current operating experience, as well as a preview of the next, larger version of bERLinPro. [German] Die in diesem Paper vorgestellte Anlage versorgt das Testmodul fuer die supraleitende Elektronenquelle (GunLab) am Helmholtz-Zentrum Berlin (HZB) mit 500 W Kuehlleistung bei 80 K. Da eine Direktverdampfung von Fluessigstickstoff im Modul aus Sicherheitsgruenden nicht erwuenscht ist, arbeitet die Anlage mit einem Heliumzwischenkreis. Um nicht nur die latente Kaelte des fluessigen Stickstoffs, sondern auch den sensiblen Anteil zu nutzen, wird ein neues Konzept, bestehend aus einem Dualwaermeuebertrager und einem Badkryostaten verwendet. Die Coldbox enthaelt fuer Testzwecke darueber hinaus einen regelbaren Bypass mit inte-griertem elektrischem Heizer. Fuer die Umwaelzung des Heliums kommt eine neue Art eines warmen Kompressors zum Einsatz. Der Turbokom-pressor ist oelfrei, gasgelagert und in heliumdichter halb-hermetischer Bauweise ausgefuehrt. Um dessen, in dieser Leistungsklasse einzigartigen Eigenschaften zu nutzen, wurde der

  11. NRC Information No. 87-41: Failures of certain Brown Boveri Electric circuit breakers

    International Nuclear Information System (INIS)

    Rossi, C.E.

    1992-01-01

    On April 20, 1987, Duquesne Light Company, the Beaver Valley Unit 2 licensee, notified the NRC of the failure of a BBE Type 5HK Class IE 4-KV circuit breaker. When the circuit breaker was racked onto the bus and 125-V DC control power was applied to the breaker's control circuit, the closing spring charged and the circuit breaker immediately closed and opened several times before the control power could be turned off. The licensee determined by field testing that the closing coil was not being energized. Another problem with BBE circuit breakers occurred at River Bend and was reported March 6, 1987. On February 6, 1987, with the unit at full power, the Division I diesel generator 4.16-KV output circuit breaker (Gould-Brown Boveri Type 5HK) failed to close during a weekly surveillance test. The licensee's inspection of the output circuit breaker revealed that a mounting bolt had fallen out of the closing spring charging motor, rendering the motor inoperable. Further investigation revealed several other circuit breakers that contained loose or missing charging motor mounting bolts. The licensee also stated that the River Bend circuit breaker preventive maintenance program, which the licensee believes to be in accordance with the vendor's recommendations, did not detect this problem. The licensee believes the root cause of the problem to be insufficient torquing of the charging motor mounting bolts by the vendor

  12. Superconducting flux flow digital circuits

    International Nuclear Information System (INIS)

    Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.

    1993-01-01

    The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic

  13. Advanced Microwave Circuits and Systems

    DEFF Research Database (Denmark)

    This book is based on recent research work conducted by the authors dealing with the design and development of active and passive microwave components, integrated circuits and systems. It is divided into seven parts. In the first part comprising the first two chapters, alternative concepts...... amplifier architectures. In addition, distortion analysis and power combining techniques are considered. Another key element in most microwave systems is a signal generator. It forms the heart of all kinds of communication and radar systems. The fourth part of this book is dedicated to signal generators...... push currently available technologies to the limits. Some considerations to meet the growing requirements are provided in the fifth part of this book. The following part deals with circuits based on LTCC and MEMS technologies. The book concludes with chapters considering application of microwaves...

  14. Electron commutator on integrated circuits

    International Nuclear Information System (INIS)

    Demidenko, V.V.

    1975-01-01

    The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru

  15. Smart Circuit Breaker Communication Infrastructure

    Directory of Open Access Journals (Sweden)

    Octavian Mihai MACHIDON

    2017-11-01

    Full Text Available The expansion of the Internet of Things has fostered the development of smart technologies in fields such as power transmission and distribution systems (as is the Smart Grid and also in regard to home automation (the Smart Home concept. This paper addresses the network communication infrastructure for a Smart Circuit Breaker system, a novel application at the edge of the two afore-mentioned systems (Smart Grid and Smart Home. Such a communication interface has high requirements from functionality, performance and security point of views, given the large amount of distributed connected elements and the real-time information transmission and system management. The paper describes the design and implementation of the data server, Web interface and the embedded networking capabilities of the smart circuit breakers, underlining the protocols and communication technologies used.

  16. Foundations for microstrip circuit design

    CERN Document Server

    Edwards, Terry

    2016-01-01

    Building on the success of the previous three editions, Foundations for Microstrip Circuit Design offers extensive new, updated and revised material based upon the latest research. Strongly design-oriented, this fourth edition provides the reader with a fundamental understanding of this fast expanding field making it a definitive source for professional engineers and researchers and an indispensable reference for senior students in electronic engineering. Topics new to this edition: microwave substrates, multilayer transmission line structures, modern EM tools and techniques, microstrip and planar transmision line design, transmission line theory, substrates for planar transmission lines, Vias, wirebonds, 3D integrated interposer structures, computer-aided design, microstrip and power-dependent effects, circuit models, microwave network analysis, microstrip passive elements, and slotline design fundamentals.

  17. BlockLevel Bayesian Diagnosis of Analogue Electronic Circuits

    NARCIS (Netherlands)

    Krishnan, Shaji; Krishnan, Shaji; Kerkhoff, Hans G.; Doornbosch, Klaas D.; Brand, Rudi

    2010-01-01

    Daily experience with product designers, test and diagnosis engineers it is realized that the depth of interaction among them, ought to be high for successful diagnosis of analogue circuits. With this knowledge in mind, a responsibility was undertaken to choose a popular diagnostic method and define

  18. An Inexpensive Coincidence Circuit for the Pasco Geiger Sensors

    CERN Document Server

    Fichera, F; Librizzi, F; Riggi, F

    2005-01-01

    A simple coincidence circuit was devised to carry out educational coincidence experiments involving the use of Geiger counters. The system was tested by commercially available Geiger sensors from PASCO, and is intended to be used in collaboration with high school students and teachers

  19. FUZZY NEURAL NETWORK FOR OBJECT IDENTIFICATION ON INTEGRATED CIRCUIT LAYOUTS

    Directory of Open Access Journals (Sweden)

    A. A. Doudkin

    2015-01-01

    Full Text Available Fuzzy neural network model based on neocognitron is proposed to identify layout objects on images of topological layers of integrated circuits. Testing of the model on images of real chip layouts was showed a highеr degree of identification of the proposed neural network in comparison to base neocognitron.

  20. Block-level Bayesian diagnosis of analogue electronic circuits

    NARCIS (Netherlands)

    Krishnan, S.; Doornbos, K.D.; Brand, R.; Kerkhoff, H.G.

    2010-01-01

    Daily experience with product designers, test and diagnosis engineers it is realized that the depth of interaction among them, ought be high for sucessfull diagnosis of analogue circuits. With this knowledge in mind, a responsibility was undertaken to choose a popular diagnostic method and define a

  1. 30 CFR 18.51 - Electrical protection of circuits and equipment.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Electrical protection of circuits and equipment... TESTING, EVALUATION, AND APPROVAL OF MINING PRODUCTS ELECTRIC MOTOR-DRIVEN MINE EQUIPMENT AND ACCESSORIES Construction and Design Requirements § 18.51 Electrical protection of circuits and equipment. (a) An automatic...

  2. Pre-Service and In-Service Physics Teachers' Ideas about Simple Electric Circuits

    Science.gov (United States)

    Kucukozer, Huseyin; Demirci, Neset

    2008-01-01

    The aim of the study is to determine pre-service and high school physics teachers' ideas about simple electric circuits. In this study, a test containing eight questions related to simple electric circuits was given to the pre-service physics teachers (32 subjects) that had graduated from Balikesir University, Necatibey Faculty of Education, the…

  3. Engine Tune-Up Service. Unit 4: Secondary Circuit. Posttests. Automotive Mechanics Curriculum.

    Science.gov (United States)

    Morse, David T.

    This book of posttests is designed to accompany the Engine Tune-Up Service Student Guide for Unit 4, Secondary Circuit, available separately as CE 031 214. Focus of the posttests is testing and servicing the secondary ignition circuit. One multiple choice posttest is provided that covers the seven performance objectives contained in the unit. (No…

  4. Engine Tune-Up Service. Unit 4: Secondary Circuit. Student Guide. Automotive Mechanics Curriculum.

    Science.gov (United States)

    Bacon, E. Miles

    This student guide is for Unit 4, Secondary Circuit, in the Engine Tune-Up Service portion of the Automotive Mechanics Curriculum. It deals with how to test and service the secondary ignition circuit. A companion review exercise book and posttests are available separately as CE 031 215-216. An introduction tells how this unit fits into the total…

  5. Engine Tune-Up Service. Unit 3: Primary Circuit. Review Exercise Book. Automotive Mechanics Curriculum.

    Science.gov (United States)

    Bacon, E. Miles

    This book of pretests and review exercises is designed to accompany the Engine Tune-Up Service Student Guide for Unit 3, Primary Circuit, available separately as CE 031 211. Focus of the exercises and pretests is testing the primary ignition circuit. Pretests and performance checklists are provided for each of the eight performance objectives…

  6. Engine Tune-up Service. Unit 4: Secondary Circuit. Review Exercise Book. Automotive Mechanics Curriculum.

    Science.gov (United States)

    Bacon, E. Miles

    This book of pretests and review exercises is designed to accompany the Engine Tune-Up Service Student Guide for Unit 4, Secondary Circuit, available separately as CE 031 214. Focus of the exercises and pretests is testing and servicing the secondary ignition circuit. Pretests and performance checklists are provided for each of the seven…

  7. Engine Tune-Up Service. Unit 3: Primary Circuit. Student Guide. Automotive Mechanics Curriculum.

    Science.gov (United States)

    Bacon, E. Miles

    This student guide is for Unit 3, Primary Circuit, in the Engine Tune-Up Service portion of the Automotive Mechanics Curriculum. It deals with how to test the primary ignition circuit. A companion review exercise book and posttests are available separately as CE 031 212-213. An introduction tells how this unit fits into the total tune-up service,…

  8. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  9. Unbalanced neuronal circuits in addiction.

    Science.gov (United States)

    Volkow, Nora D; Wang, Gen-Jack; Tomasi, Dardo; Baler, Ruben D

    2013-08-01

    Through sequential waves of drug-induced neurochemical stimulation, addiction co-opts the brain's neuronal circuits that mediate reward, motivation to behavioral inflexibility and a severe disruption of self-control and compulsive drug intake. Brain imaging technologies have allowed neuroscientists to map out the neural landscape of addiction in the human brain and to understand how drugs modify it. Published by Elsevier Ltd.

  10. Monolithic readout circuits for RHIC

    International Nuclear Information System (INIS)

    O'Connor, P.; Harder, J.; Sippach, W.

    1991-10-01

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology

  11. Circuit complexity of regular languages

    Czech Academy of Sciences Publication Activity Database

    Koucký, Michal

    2009-01-01

    Roč. 45, č. 4 (2009), s. 865-879 ISSN 1432-4350 R&D Projects: GA ČR GP201/07/P276; GA MŠk(CZ) 1M0545 Institutional research plan: CEZ:AV0Z10190503 Keywords : regular languages * circuit complexity * upper and lower bounds Subject RIV: BA - General Mathematics Impact factor: 0.726, year: 2009

  12. Realistic Realizations Of Threshold Circuits

    Science.gov (United States)

    Razavi, Hassan M.

    1987-08-01

    Threshold logic, in which each input is weighted, has many theoretical advantages over the standard gate realization, such as reducing the number of gates, interconnections, and power dissipation. However, because of the difficult synthesis procedure and complicated circuit implementation, their use in the design of digital systems is almost nonexistant. In this study, three methods of NMOS realizations are discussed, and their advantages and shortcomings are explored. Also, the possibility of using the methods to realize multi-valued logic is examined.

  13. Monolithic readout circuits for RHIC

    Energy Technology Data Exchange (ETDEWEB)

    O`Connor, P.; Harder, J. [Brookhaven National Laboratory, Upton, NY (United States)

    1991-12-31

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology.

  14. Root finding with threshold circuits

    Czech Academy of Sciences Publication Activity Database

    Jeřábek, Emil

    2012-01-01

    Roč. 462, Nov 30 (2012), s. 59-69 ISSN 0304-3975 R&D Projects: GA AV ČR IAA100190902; GA MŠk(CZ) 1M0545 Institutional support: RVO:67985840 Keywords : root finding * threshold circuit * power series Subject RIV: BA - General Mathematics Impact factor: 0.489, year: 2012 http://www.sciencedirect.com/science/article/pii/S0304397512008006#

  15. Refractory silicides for integrated circuits

    International Nuclear Information System (INIS)

    Murarka, S.P.

    1980-01-01

    Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

  16. Circuits and electronics hands-on learning with analog discovery

    CERN Document Server

    Okyere Attia, John

    2018-01-01

    The book provides instructions on building circuits on breadboards, connecting the Analog Discovery wires to the circuit under test, and making electrical measurements. Various measurement techniques are described and used in this book, including: impedance measurements, complex power measurements, frequency response measurements, power spectrum measurements, current versus voltage characteristic measurements of diodes, bipolar junction transistors, and Mosfets. The book includes end-of-chapter problems for additional exercises geared towards hands-on learning, experimentation, comparisons between measured results and those obtained from theoretical calculations.

  17. The primary circuit of the dragon high temperature reactor experiment

    International Nuclear Information System (INIS)

    Simon, R.

    2005-01-01

    The 20 MWth Dragon Reactor Experiment was the first HTGR (High Temperature Gas-cooled Reactor) with coated particle fuel. Its purpose was to test fuel and materials for the High Temperature Reactor programmes pursued in Europe 40 years ago. This paper describes the design and construction of the primary (helium) circuit. It summarizes the main design objectives, lists the performance data and explains the flow paths of the heat removal and helium purification systems. The principal circuit accidents postulated are discussed and the choice of the main construction materials is given. (author)

  18. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  19. A memristor-based nonvolatile latch circuit

    International Nuclear Information System (INIS)

    Robinett, Warren; Pickett, Matthew; Borghetti, Julien; Xia Qiangfei; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

    2010-01-01

    Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

  20. Insulated transcriptional elements enable precise design of genetic circuits.

    Science.gov (United States)

    Zong, Yeqing; Zhang, Haoqian M; Lyu, Cheng; Ji, Xiangyu; Hou, Junran; Guo, Xian; Ouyang, Qi; Lou, Chunbo

    2017-07-03

    Rational engineering of biological systems is often complicated by the complex but unwanted interactions between cellular components at multiple levels. Here we address this issue at the level of prokaryotic transcription by insulating minimal promoters and operators to prevent their interaction and enable the biophysical modeling of synthetic transcription without free parameters. This approach allows genetic circuit design with extraordinary precision and diversity, and consequently simplifies the design-build-test-learn cycle of circuit engineering to a mix-and-match workflow. As a demonstration, combinatorial promoters encoding NOT-gate functions were designed from scratch with mean errors of 96% using our insulated transcription elements. Furthermore, four-node transcriptional networks with incoherent feed-forward loops that execute stripe-forming functions were obtained without any trial-and-error work. This insulation-based engineering strategy improves the resolution of genetic circuit technology and provides a simple approach for designing genetic circuits for systems and synthetic biology.Unwanted interactions between cellular components can complicate rational engineering of biological systems. Here the authors design insulated minimal promoters and operators that enable biophysical modeling of bacterial transcription without free parameters for precise circuit design.

  1. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  2. Design of analog integrated circuits and systems

    CERN Document Server

    Laker, Kenneth R

    1994-01-01

    This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

  3. Simplified slow anti-coincidence circuit for Compton suppression systems

    International Nuclear Information System (INIS)

    Al-Azmi, Darwish

    2008-01-01

    Slow coincidence circuits for the anti-coincidence measurements have been considered for use in Compton suppression technique. The simplified version of the slow circuit has been found to be fast enough, satisfactory and allows an easy system setup, particularly with the advantage of the automatic threshold setting of the low-level discrimination. A well-type NaI detector as the main detector surrounded by plastic guard detector has been arranged to investigate the performance of the Compton suppression spectrometer using the simplified slow circuit. The system has been tested to observe the improvement in the energy spectra for medium to high-energy gamma-ray photons from terrestrial and environmental samples

  4. Single Day Construction of Multigene Circuits with 3G Assembly.

    Science.gov (United States)

    Halleran, Andrew D; Swaminathan, Anandh; Murray, Richard M

    2018-05-18

    The ability to rapidly design, build, and test prototypes is of key importance to every engineering discipline. DNA assembly often serves as a rate limiting step of the prototyping cycle for synthetic biology. Recently developed DNA assembly methods such as isothermal assembly and type IIS restriction enzyme systems take different approaches to accelerate DNA construction. We introduce a hybrid method, Golden Gate-Gibson (3G), that takes advantage of modular part libraries introduced by type IIS restriction enzyme systems and isothermal assembly's ability to build large DNA constructs in single pot reactions. Our method is highly efficient and rapid, facilitating construction of entire multigene circuits in a single day. Additionally, 3G allows generation of variant libraries enabling efficient screening of different possible circuit constructions. We characterize the efficiency and accuracy of 3G assembly for various construct sizes, and demonstrate 3G by characterizing variants of an inducible cell-lysis circuit.

  5. High resolution capacitance detection circuit for rotor micro-gyroscope

    Directory of Open Access Journals (Sweden)

    Ming-Yuan Ren

    2014-03-01

    Full Text Available Conventional methods for rotor position detection of micro-gyroscopes include common exciting electrodes (single frequency and common sensing electrodes (frequency multiplex, but they have encountered some problems. So we present a high resolution and low noise pick-off circuit for micro-gyroscopes which utilizes the time multiplex method. The detecting circuit adopts a continuous-time current sensing circuit for capacitance measurement, and its noise analysis of the charge amplifier is introduced. The equivalent output noise power spectral density of phase-sensitive demodulation is 120 nV/Hz1/2. Tests revealed that the whole circuitry has a relative capacitance resolution of 1 × 10−8.

  6. Study of recursive model for pole-zero cancellation circuit

    International Nuclear Information System (INIS)

    Zhou Jianbin; Zhou Wei; Hong Xu; Hu Yunchuan; Wan Xinfeng; Du Xin; Wang Renbo

    2014-01-01

    The output of charge sensitive amplifier (CSA) is a negative exponential signal with long decay time which will result in undershoot after C-R differentiator. Pole-zero cancellation (PZC) circuit is often applied to eliminate undershoot in many radiation detectors. However, it is difficult to use a zero created by PZC circuit to cancel a pole in CSA output signal accurately because of the influences of electronic components inherent error and environmental factors. A novel recursive model for PZC circuit is presented based on Kirchhoff's Current Law (KCL) in this paper. The model is established by numerical differentiation algorithm between the input and the output signal. Some simulation experiments for a negative exponential signal are carried out using Visual Basic for Application (VBA) program and a real x-ray signal is also tested. Simulated results show that the recursive model can reduce the time constant of input signal and eliminate undershoot. (authors)

  7. Graphene radio frequency receiver integrated circuit.

    Science.gov (United States)

    Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

    2014-01-01

    Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

  8. The single-event effect evaluation technology for nano integrated circuits

    International Nuclear Information System (INIS)

    Zheng Hongchao; Zhao Yuanfu; Yue Suge; Fan Long; Du Shougang; Chen Maoxin; Yu Chunqing

    2015-01-01

    Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally. (paper)

  9. Circuit bridging of digital equipment caused by smoke from a cable fire

    International Nuclear Information System (INIS)

    Tanaka, T.J.; Anderson, D.J.

    1997-01-01

    Advanced reactor systems are likely to use protection systems with digital electronics that ideally should be resistant to environmental hazards, including smoke from possible cable fires. Previous smoke tests have shown that digital safety systems can fail even at relatively low levels of smoke density and that short-term failures are likely to be caused by circuit bridging. Experiments were performed to examine these failures, with a focus on component packaging and protection schemes. Circuit bridging, which causes increased leakage currents and arcs, was gauged by measuring leakage currents among the leads of component packages. The resistance among circuit leads typically varies over a wide range, depending on the nature of the circuitry between the pins, bias conditions, circuit board material, etc. Resistance between leads can be as low as 20 kΩ and still be good, depending on the component. For these tests, the authors chose a printed circuit board and components that normally have an interlead resistance above 10 12 Ω, but if the circuit is exposed to smoke, circuit bridging causes the resistance to fall below 10 3 Ω. Plated-through-hole (PTH) and surface-mounted (SMT) packages were exposed to a series of different smoke environments using a mixture of environmentally qualified cables for fuel. Conformal coatings and enclosures were tested as circuit protection methods. High fuel levels, high humidity, and high flaming burns were the conditions most likely to cause circuit bridging. The inexpensive conformal coating that was tested - an acrylic spray - reduced leakage currents, but enclosure in a chassis with a fan did not. PTH packages were more resistant to smoke-induced circuit bridging than SMT packages. Active components failed most often in tests where the leakage currents were high, but failure did not always accompany high leakage currents

  10. Design and experimental results of coaxial circuits for gyroklystron amplifiers

    International Nuclear Information System (INIS)

    Flaherty, M.K.E.; Lawson, W.; Cheng, J.; Calame, J.P.; Hogan, B.; Latham, P.E.; Granatstein, V.L.

    1994-01-01

    At the University of Maryland high power microwave source development for use in linear accelerator applications continues with the design and testing of coaxial circuits for gyroklystron amplifiers. This presentation will include experimental results from a coaxial gyroklystron that was tested on the current microwave test bed, and designs for second harmonic coaxial circuits for use in the next generation of the gyroklystron program. The authors present test results for a second harmonic coaxial circuit. Similar to previous second harmonic experiments the input cavity resonated at 9.886 GHz and the output frequency was 19.772 GHz. The coaxial insert was positioned in the input cavity and drift region. The inner conductor consisted of a tungsten rod with copper and ceramic cylinders covering its length. Two tungsten rods that bridged the space between the inner and outer conductors supported the whole assembly. The tube produced over 20 MW of output power with 17% efficiency. Beam interception by the tungsten rods resulted in minor damage. Comparisons with previous non-coaxial circuits showed that the coaxial configuration increased the parameter space over which stable operation was possible. Future experiments will feature an upgraded modulator and beam formation system capable of producing 300 MW of beam power. The fundamental frequency of operation is 8.568 GHz. A second harmonic coaxial gyroklystron circuit was designed for use in the new system. A scattering matrix code predicts a resonant frequency of 17.136 GHz and Q of 260 for the cavity with 95% of the outgoing microwaves in the desired TE032 mode. Efficiency studies of this second harmonic output cavity show 20% expected efficiency. Shorter second harmonic output cavity designs are also being investigated with expected efficiencies near 34%

  11. Developing equivalent circuits for radial distribution networks

    Energy Technology Data Exchange (ETDEWEB)

    Prada, Ricardo; Coelho, Agnelo; Rodrigues, Anselmo [Catholic University of Rio de Janeiro (PUC-Rio), RJ (Brazil). Dept. of Electrical Engineering], Emails: prada@ele.puc-rio.br, agnelo@ele.puc-rio.br, nebulok_99@yahoo.com; Silva, Maria da Guia da [Federal University of Maranhao, Sao Luiz, MA (Brazil). Dept. of Electrical Engineering

    2009-07-01

    This paper presents a method for evaluating External Equivalent in Electric Distribution Networks (EDN).The proposed method has as its main objectives the reduction of the computational costs in distribution network reconfiguration, investigation of the optimal allocation of banks of capacitors, investigation of the allocation of distributed generation, etc. In these sorts of problems a large number of alternative projects must be assessed in order to identify the optimal solution. The optimal solution comes up with the voltage level in the load points within specified limits. Consequently, the EDN must retain the external network load points but without major increasing in the dimension of the equivalent circuit. The proposed method has been tested and validated in a substation of the Electricity Utility of Maranhao - CEMAR, in Brazil. (author)

  12. RD53A Integrated Circuit Specifications

    CERN Document Server

    Garcia-Sciveres, Mauricio

    2015-01-01

    Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with realistic sensors in this new technology and to measure the performance of hybrid assemblies. RD53A is not intended to be a final production IC for use in an experiment, and will contain design variations for testing purposes, making the pixel matrix non-uniform.

  13. Circuit for Driving Piezoelectric Transducers

    Science.gov (United States)

    Randall, David P.; Chapsky, Jacob

    2009-01-01

    The figure schematically depicts an oscillator circuit for driving a piezoelectric transducer to excite vibrations in a mechanical structure. The circuit was designed and built to satisfy application-specific requirements to drive a selected one of 16 such transducers at a regulated amplitude and frequency chosen to optimize the amount of work performed by the transducer and to compensate for both (1) temporal variations of the resonance frequency and damping time of each transducer and (2) initially unknown differences among the resonance frequencies and damping times of different transducers. In other words, the circuit is designed to adjust itself to optimize the performance of whichever transducer is selected at any given time. The basic design concept may be adaptable to other applications that involve the use of piezoelectric transducers in ultrasonic cleaners and other apparatuses in which high-frequency mechanical drives are utilized. This circuit includes three resistor-capacitor networks that, together with the selected piezoelectric transducer, constitute a band-pass filter having a peak response at a frequency of about 2 kHz, which is approximately the resonance frequency of the piezoelectric transducers. Gain for generating oscillations is provided by a power hybrid operational amplifier (U1). A junction field-effect transistor (Q1) in combination with a resistor (R4) is used as a voltage-variable resistor to control the magnitude of the oscillation. The voltage-variable resistor is part of a feedback control loop: Part of the output of the oscillator is rectified and filtered for use as a slow negative feedback to the gate of Q1 to keep the output amplitude constant. The response of this control loop is much slower than 2 kHz and, therefore, does not introduce significant distortion of the oscillator output, which is a fairly clean sine wave. The positive AC feedback needed to sustain oscillations is derived from sampling the current through the

  14. Coherent defects in superconducting circuits

    International Nuclear Information System (INIS)

    Mueller, Clemens

    2011-01-01

    The interaction of superconducting circuits with additional quantum systems is a topic that has found extensive study in the recent past. In the limit where the added system are incoherent, this is the standard field of decoherence and the system dynamics can be described by a simple master equation. In the other limit however, when the additional parts are coherent, the resulting time-evolution can become more complicated. In this thesis we have investigated the interaction of superconducting circuits with coherent and incoherent two-level defects. We have shown theoretical calculations characterizing this interaction for all relevant parameter regimes. In the weak coupling limit, the interaction can be described in an effective bath picture, where the TLS act as parts of a large, decohering environment. For strong coupling, however, the coherent dynamics of the full coupled system has to be considered. We show the calculations of the coupled time-evolution and again characterize the interaction by an effective decoherence rate. We also used experimental data to characterize the microscopic origin of the defects and the details of their interaction with the circuits. The results obtained by analyzing spectroscopic data allow us to place strong constraint on several microscopic models for the observed TLS. However, these calculations are not yet fully conclusive as to the physical nature of the TLS. We propose additional experiments to fully characterize the interaction part of the Hamiltonian, thus providing the answer to the question of the physical origin of the coupling. Additionally we have developed a method to directly drive individual defect states via virtual excitation of the qubit. This method allows one to directly probe the properties of single TLS and possibly make use of their superior coherence times for quantum information purposes. The last part of this thesis provided a way for a possible implementation of geometric quantum computation in

  15. Miniaturization of Josephson logic circuits

    International Nuclear Information System (INIS)

    Ko, H.; Van Duzer, T.

    1985-01-01

    The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements

  16. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    , and it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt...... the impact of substrate-induced currents. Basic models are derived in the design phase, and the technological limits of the device are considered. Measurement results show that a very compact coil can provide ~1nH inductance up to 20GHz (physical limit for the measurement equipment), with a peak quality...

  17. Model reduction for circuit simulation

    CERN Document Server

    Hinze, Michael; Maten, E Jan W Ter

    2011-01-01

    Simulation based on mathematical models plays a major role in computer aided design of integrated circuits (ICs). Decreasing structure sizes, increasing packing densities and driving frequencies require the use of refined mathematical models, and to take into account secondary, parasitic effects. This leads to very high dimensional problems which nowadays require simulation times too large for the short time-to-market demands in industry. Modern Model Order Reduction (MOR) techniques present a way out of this dilemma in providing surrogate models which keep the main characteristics of the devi

  18. HF radio systems and circuits

    CERN Document Server

    Sabin, William

    1998-01-01

    A comprehensive reference for the design of high frequency communications systems and equipment. This revised edition is loaded with practical data, much of which cannot be found in other reference books. Its approach to the subject follows the needs of an engineer from system definition and performance requirements down to the individual circuit elements that make up radio transmitters and receivers. The accompanying disk contains updated software on filters, matching networks and receiver analysis. SciTech Publishing also provides many other products related to Communication Systems Design.

  19. Polysilicon photoconductor for integrated circuits

    Science.gov (United States)

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  20. Wideband 4-diode sampling circuit

    Science.gov (United States)

    Wojtulewicz, Andrzej; Radtke, Maciej

    2016-09-01

    The objective of this work was to develop a wide-band sampling circuit. The device should have the ability to collect samples of a very fast signal applied to its input, strengthen it and prepare for further processing. The study emphasizes the method of sampling pulse shaping. The use of ultrafast pulse generator allows sampling signals with a wide frequency spectrum, reaching several gigahertzes. The device uses a pulse transformer to prepare symmetrical pulses. Their final shape is formed with the help of the step recovery diode, two coplanar strips and Schottky diode. Made device can be used in the sampling oscilloscope, as well as other measurement system.