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Sample records for sub-half micron cmos

  1. Sub-half-micron contact window design with 3D photolithography simulator

    Science.gov (United States)

    Brainerd, Steve K.; Bernard, Douglas A.; Rey, Juan C.; Li, Jiangwei; Granik, Yuri; Boksha, Victor V.

    1997-07-01

    In state of the art IC design and manufacturing certain lithography layers have unique requirements. Latitudes and tolerances that apply to contacts and polysilicon gates are tight for such critical layers. Industry experts are discussing the most cost effective ways to use feature- oriented equipment and materials already developed for these layers. Such requirements introduce new dimensions into the traditionally challenging task for the photolithography engineer when considering various combinations of multiple factors to optimize and control the process. In addition, he/she faces a rapidly increasing cost of experiments, limited time and scarce access to equipment to conduct them. All the reasons presented above support simulation as an ideal method to satisfy these demands. However lithography engineers may be easily dissatisfied with a simulation tool when discovering disagreement between the simulation and experimental data. The problem is that several parameters used in photolithography simulation are very process specific. Calibration, i.e. matching experimental and simulation data using a specific set of procedures allows one to effectively use the simulation tool. We present results of a simulation based approach to optimize photolithography processes for sub-0.5 micron contact windows. Our approach consists of: (1) 3D simulation to explore different lithographic options, (2) calibration to a range of process conditions with extensive use of specifically developed optimization techniques. The choice of a 3D simulator is essential because of 3D nature of the problem of contact window design. We use DEPICT 4.1. This program performs fast aerial image simulation as presented before. For 3D exposure the program uses an extension to three-dimensions of the high numerical aperture model combined with Fast Fourier Transforms for maximum performance and accuracy. We use Kim (U.C. Berkeley) model and the fast marching Level Set method respectively for the

  2. Analysis and Design of Monolithic Inductors in Sub-micron CMOS

    DEFF Research Database (Denmark)

    Fallesen, Carsten; Jørgensen, Allan

    1997-01-01

    In the last few years the CMOS processes have gone into deep sub-micron channel lengths. This means that it is now possible to make GHz applications in CMOS. In analog GHz applications it is often necessary to have access to inductors. This report describes the development of a physical model of ...

  3. Radiation Tolerant Design with 0.18-micron CMOS Technology

    CERN Document Server

    Chen, Li; Durdle , Nelson G.

    This thesis discusse s th e issues r elated to the us e of enclosed-gate layou t trans isto rs and guard rings in a 0.18 μ m CMOS technology in order to im prove the radiation tolerance of ASICs. The thin gate oxides of subm icron technologies ar e inherently m ore radiation tole rant tha n the thick er oxides present in less advanced technologies. Using a commercial deep subm icron technology to bu ild up radiation-ha rdened circuits introduces several advantages com pared to a dedicated radiation-ha rd technology, such as speed, power, area, stability, and expense. Som e novel aspects related to the use of encl osed-gate layout transist ors are presented in this th esis. A m odel to calculate the aspect ratio is introduced and verified. Some im portant electrica l par ameters of the tran sistors such as threshold voltage, leakage current, subthreshold slope, and transconducta nce are studied before and afte...

  4. Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

    Science.gov (United States)

    Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

    2014-03-01

    We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

  5. A large dynamic range radiation-tolerant analog memory in a quarter- micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2001-01-01

    An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 1...

  6. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    This paper is a survey paper presenting the Nordic CONFRONT project and reporting some results from the group at CIE/DTU, Denmark. The objective of the project is to demonstrate the feasibility of sub-micron CMOS for the realisation of RF front-end circuits operating at frequencies in the 1...

  7. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    This paper is a survey paper presenting the Nordic CONFRONT project and reporting some results from the group at CIE/DTU, Denmark. The objective of the project is to demonstrate the feasibility of sub-micron CMOS for the realisation of RF front-end circuits operating at frequencies in the 1.......8-2.0 GHz range. The ultimate goal is a single-chip transceiver, requiring only an external band-pass filter between the chip and the antenna. DECT has been chosen as a comparative standard to compare the new approaches developed in the work as well as to facilitate good knowledge transfer to industry. All...

  8. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    This paper is a survey paper presenting the Nordic CONFRONT project and reporting some results from the group at CIE/DTU, Denmark. The objective of the project is to demonstrate the feasibility of sub-micron CMOS for the realisation of RF front-end circuits operating at frequencies in the 1.......8-2.0 GHz range. The ultimate goal is a single-chip transceiver, requiring only an external band-pass filter between the chip and the antenna. DECT has been chosen as a comparative standard to compare the new approaches developed in the work as well as to facilitate good knowledge transfer to industry. All...... of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses...

  9. A large dynamic range radiation tolerant analog memory in a quarter micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2000-01-01

    A 8*128 cell analog memory prototype has been designed in a commercial 0.25 jam CMOS process. The aim of this work was to investigate the possibility of designing large dynamic range mixed- mode switched capacitor circuits for High-Energy Physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant left bracket 1 right bracket . The memory cells employ gate-oxide capacitors for storage, allowing for a very high density. A voltage write - voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (V//D//D = 2.5 V), with a linearity of at least 7.5 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is plus or minus 0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after lOMrd (...

  10. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  11. Proposal to negotiate an amendment to an existing blanket contract for the supply of foundry services in quarter-micron CMOS technology for the LHC experiments

    CERN Document Server

    2003-01-01

    This document concerns the proposal to negotiate an amendment to an existing blanket contract for the supply of foundry services in quarter-micron CMOS technology for the LHC experiments. For the reasons explained in this document, the Finance Committee is invited to agree to the negotiation of an amendment to the blanket contract for the supply of foundry services in quarter-micron CMOS technology with the company IBM TECHNOLOGY GROUP (CH), formerly IBM ITALIA (IT), for an extension of the period of validity from five to eight years and for an amount exceeding the previously authorised amount of 8 500 000 US dollars by up to 6 500 000 US dollars, not subject to revision, bringing the total contract amount to a maximum amount of 15 000 000 US dollars, not subject to revision. At the present rate of exchange, the total amended amount of the blanket contract is equivalent to approximately 19 800 000 Swiss francs. This requirement will be financed by the collaborating institutes of the LHC experiments and by CER...

  12. Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50 micron pitch

    CERN Document Server

    Bellazzini, R; Minuti, M; Baldini, L; Brez, A; Cavalca, F; Latronico, L; Omodei, N; Massai, M M; Sgro, C; Costa, E; Krummenacher, P S F; De Oliveira, R

    2006-01-01

    We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50 micron pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and two poly-silicon layers of a 0.18 micron VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The ve...

  13. Chemically amplified negative-tone photoresist for sub-half-micron device and mask fabrication

    Science.gov (United States)

    Conley, Will; Dundatscheck, Robert; Gelorme, Jeffrey D.; Horvat, John; Martino, Ronald M.; Murphy, Elizabeth; Petrosky, Anne; Spinillo, Gary T.; Stewart, Kevin J.; Wilbarg, Robert; Wood, Robert L.

    1991-06-01

    In this paper we discuss a new alkaline soluble negative acting photoresist which incorporates a phenolic based resin, urea/formaldehyde prepolymer as a crosslinking agent and an organic acid-generating sensitizer. This system, dubbed 'EBX' (Electron Beam/X-ray) resist has demonstrated excellent lithographic properties in various exposure modes. Discussion will center on imaging characteristics in the deep and mid ultraviolet using Micrascan I and I-line (365 nm) steppers; electron-beam imaging with MEBES 10 kV mask maker and IBM's EL-4 50 kV electron beam exposure system; and XRAY imaging with point source soft x-ray and synchotron hard x-ray lithography.

  14. Generation of a sub-half-wavelength focal spot with purely transverse spin angular momentum

    Science.gov (United States)

    Hang, Li; Fu, Jian; Yu, Xiaochang; Wang, Ying; Chen, Peifeng

    2017-11-01

    We theoretically demonstrate that optical focus fields with purely transverse spin angular momentum (SAM) can be obtained when a kind of special incident fields is focused by a high numerical aperture (NA) aplanatic lens (AL). When the incident pupil fields are refracted by an AL, two transverse Cartesian components of the electric fields at the exit pupil plane do not have the same order of sinusoidal or cosinoidal components, resulting in zero longitudinal SAMs of the focal fields. An incident field satisfying above conditions is then proposed. Using the Richard-Wolf vectorial diffraction theory, the energy density and SAM density distributions of the tightly focused beam are calculated and the results clearly validate the proposed theory. In addition, a sub-half-wavelength focal spot with purely transverse SAM can be achieved and a flattop energy density distribution parallel to z-axis can be observed around the maximum energy density point.

  15. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  16. Small Pixel Hybrid CMOS X-ray Detectors

    Science.gov (United States)

    Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

    2018-01-01

    Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

  17. Selenium coated CMOS passive pixel array for medical imaging

    Science.gov (United States)

    Majid, Shaikh Hasibul; Goldan, Amir H.; Hadji, Bahman; Belev, George; Kasap, Safa; Karim, Karim S.

    2011-03-01

    Digital imaging systems for medical applications use amorphous silicon thin-film transistor (TFT) technology due to its ability to be manufactured over large areas. However, TFT technology is far inferior to crystalline silicon CMOS technology in terms of the speed, stability, noise susceptibility, and feature size. This work investigates the feasibility of integrating an imaging array fabricated in CMOS technology with an a-Se detector. The design of a CMOS passive pixel sensor (PPS) array is presented, in addition to how an 8×8 PPS array is integrated with the 75 micron thick stabilized amorphous selenium detector. A non-linear increase in the dark current of 200 pA, 500 pA and 2 nA is observed with 0.27, 0.67 and 1.33 V/micron electric field respectively, which shows a successful integration of selenium layer with the CMOS array. Results also show that the integrated Selenium-CMOS PPS array has good responsivity to optical light and X-rays, leaving the door open for further research on implementing CMOS imaging architectures going forward. Demonstrating that the PPS chips using CMOS technology can use a-Se as a detector is thus the first step in a promising path of research, which should yield substantial and exciting results for the field. Though area may still prove challenging, larger CMOS wafers can be manufactured and tiled to allow for a large enough size for certain diagnostic imaging applications and potentially even large area applications like digital mammography.

  18. Reliability engineering in RF CMOS

    NARCIS (Netherlands)

    Sasse, G.T.

    2008-01-01

    In this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is

  19. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  20. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  1. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  2. Integrated tunable CMOS laser.

    Science.gov (United States)

    Creazzo, Timothy; Marchena, Elton; Krasulick, Stephen B; Yu, Paul K L; Van Orden, Derek; Spann, John Y; Blivin, Christopher C; He, Lina; Cai, Hong; Dallesasse, John M; Stone, Robert J; Mizrahi, Amit

    2013-11-18

    An integrated tunable CMOS laser for silicon photonics, operating at the C-band, and fabricated in a commercial CMOS foundry is presented. The III-V gain medium section is embedded in the silicon chip, and is hermetically sealed. The gain section is metal bonded to the silicon substrate creating low thermal resistance into the substrate and avoiding lattice mismatch problems. Optical characterization shows high performance in terms of side mode suppression ratio, relative intensity noise, and linewidth that is narrow enough for coherent communications.

  3. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  4. Implantable CMOS Biomedical Devices

    Directory of Open Access Journals (Sweden)

    Toshihiko Noda

    2009-11-01

    Full Text Available The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented.

  5. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  6. TID Simulation of Advanced CMOS Devices for Space Applications

    Science.gov (United States)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  7. Measuring past a micron...

    CERN Multimedia

    Anaïs Schaeffer

    2011-01-01

    Infinity: That is the name of the new ultra-precision machine used by CERN's Metrology Service to measure the copper components for the CLIC accelerating structures. This project is the result of a collaboration between CLIC and the EN Department. Curious to find out more? Read on because there’ll be an opportunity for you to get a very close look at Infinity!    Infinity, the new, ultra-precise, measuring machine, is currently in operation at the CERN Metrology Service. The CLIC (Compact LInear Collider) radiofrequency structures will operate under very high electric fields (100 MV/m). They should be manufactured within minimal mechanical tolerances. To validate the quality of these components, they have to be measured with a precision that far exceeds the machining tolerances, i.e. 0.3 microns. No “ordinary” measuring machine can achieve this precision, but Infinity, the newly developed high-precision three-dimensional measuring machine i...

  8. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  9. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...... that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used....

  10. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  11. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A.

    2017-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  12. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    CERN Document Server

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  13. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    Science.gov (United States)

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

  14. Development of CMOS integrated circuits

    Science.gov (United States)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  15. Designing analog circuits in CMOS

    NARCIS (Netherlands)

    Annema, Anne J.; Nauta, Bram; van Langevelde, Ronald; Tuinhout, Hans

    2004-01-01

    The evolution in CMOS technology dictated by Moore's Law is clearly beneficial for designers of digital circuits, but it presents difficult challenges, such as lowered nominal supply voltages, for their peers in the analog world who want to keep pace with this rapid progression. This article

  16. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  17. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  18. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  19. A Surface Micromachined CMOS MEMS Humidity Sensor

    OpenAIRE

    Jian-Qiu Huang; Fei Li; Min Zhao; Kai Wang

    2015-01-01

    This paper reports a CMOS MEMS (complementary metal oxide semiconductor micro electromechanical system) piezoresistive humidity sensor fabricated by a surface micromachining process. Both pre-CMOS and post-CMOS technologies were used to fabricate the piezoresistive humidity sensor. Compared with a bulk micromachined humidity sensor, the machining precision and the sizes of the surface micromachined humidity sensor were both improved. The package and test systems of the sensor were designed. A...

  20. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  1. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  2. CMOS Image Sensors for High Speed Applications

    OpenAIRE

    Jamal Deen, M.; Qiyin Fang; Louis Liu; Frances Tse; David Armstrong; Munir El-Desouki

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm) due to ...

  3. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  4. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  5. Real-time detection of fast and thermal neutrons in radiotherapy with CMOS sensors.

    Science.gov (United States)

    Arbor, Nicolas; Higueret, Stephane; Elazhar, Halima; Combe, Rodolphe; Meyer, Philippe; Dehaynin, Nicolas; Taupin, Florence; Husson, Daniel

    2017-03-07

    The peripheral dose distribution is a growing concern for the improvement of new external radiation modalities. Secondary particles, especially photo-neutrons produced by the accelerator, irradiate the patient more than tens of centimeters away from the tumor volume. However the out-of-field dose is still not estimated accurately by the treatment planning softwares. This study demonstrates the possibility of using a specially designed CMOS sensor for fast and thermal neutron monitoring in radiotherapy. The 14 microns-thick sensitive layer and the integrated electronic chain of the CMOS are particularly suitable for real-time measurements in γ/n mixed fields. An experimental field size dependency of the fast neutron production rate, supported by Monte Carlo simulations and CR-39 data, has been observed. This dependency points out the potential benefits of a real-time monitoring of fast and thermal neutron during beam intensity modulated radiation therapies.

  6. Total-ionizing-dose effects on isolation oxides in modern CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Barnaby, Hugh J. [Arizona State University, Electrical Engineering Department, Goldwater Room 350, Mail Code 5706, Tempe, AZ 85287-5706 (United States)]. E-mail: hbarnaby@asu.edu; Mclain, Michael [Arizona State University, Electrical Engineering Department, Goldwater Room 350, Mail Code 5706, Tempe, AZ 85287-5706 (United States); Esqueda, Ivan Sanchez [Arizona State University, Electrical Engineering Department, Goldwater Room 350, Mail Code 5706, Tempe, AZ 85287-5706 (United States)

    2007-08-15

    This paper presents experimental data on the total dose response of deep sub-micron bulk CMOS devices and integrated circuits. Ionizing radiation experiments on shallow trench isolation (STI) field oxide MOS capacitors (FOXCAP) indicate a characteristic build-up of radiation-induced defects in the dielectric. In this paper, capacitors fabricated with STI, thermal, SIMOX and bipolar base oxides of similar thickness are compared and show the STI oxide to be most susceptible to radiation effects. Experimental data on irradiated shift registers and n-channel MOSFETs are also presented. These data indicate that radiation damage to the STI can increase the off-state current of n-channel devices and the standby current of CMOS integrated circuits.

  7. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  8. MATHEMATICAL MODEL OF GRAIN MICRONIZATION

    Directory of Open Access Journals (Sweden)

    V. A. Afanas’ev

    2014-01-01

    Full Text Available Summary. During micronisation grain moisture evaporates mainly in decreasing drying rate period. Grain layer located on the surface of the conveyor micronisers will be regarded as horizontal plate. Due to the fact that the micronisation process the surface of the grain evaporates little moisture (within 2-7 % is assumed constant plate thickness. Because in the process of micronization grain structure is changing, in order to achieve an exact solution of the equations necessary to take into account changes thermophysical, optical and others. Equation of heat transfer is necessary to add a term that is responsible for the infrared heating. Because of the small thickness of the grain, neglecting the processes occurring at the edge of the grain, that is actually consider the problem of an infinite plate. To check the adequacy of the mathematical model of the process of micronisation of wheat grain moisture content must be comparable to the function of time, obtained by solving the system of equations with the measured experimental data of experience. Numerical solution of a system of equations for the period of decreasing drying rate is feasible with the help of the Maple 14, substituting the values of the constants in the system. Calculation of the average relative error does not exceed 7- 10 %, and shows a good agreement between the calculated data and the experimental values.

  9. One Micron Laser Technology Advancements at GSFC

    Science.gov (United States)

    Heaps, William S.

    2010-01-01

    This slide presentation reviews the advancements made in one micron laser technology at Goddard Space Flight Center. It includes information about risk factors that are being addressed by GSFC, and overviews of the various programs that GSFC is currently managing that are using 1 micron laser technology.

  10. MICRON-SIZED POLYMER PARTICLES FROM TANZANIAN ...

    African Journals Online (AJOL)

    Micron sized polymeric particles were prepared from cashew nut shell liquid and subsequently functionalized to produce micron-sized carboxylated cation exchange resin (MCCER). By titrimetry and analytical procedures employing atomic absorption spectrometry, an assessment of the cation exchange capability of the ...

  11. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  12. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  13. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...... the technology facilitates integration of discrete components directly on the surface of the chip, the need for an additional substrate is eliminated. For a single chip solution employing the presented via technology and on-chip integration of components, the total height of the package constituting a complete...

  14. Design, Characterization and Analysis of a 0.35 μm CMOS SPAD

    Directory of Open Access Journals (Sweden)

    Khalil Jradi

    2014-12-01

    Full Text Available Most of the works about single-photon detectors rely on Single Photon Avalanche Diodes (SPADs designed with dedicated technological processes in order to achieve single-photon sensitivity and excellent timing resolution. Instead, this paper focuses on the implementation of high-performance SPADs detectors manufactured in a standard 0.35-micron opto-CMOS technology provided by AMS. We propose a series of low-noise SPADs designed with a variable pitch from 20 µm down to 5 µm. This opens the further way to the integration of large arrays of optimized SPAD pixels with pitch of a few micrometers in order to provide high-resolution single-photon imagers. We experimentally demonstrate that a 20-micron SPAD appears as the most relevant detector in terms of Signal-to-Noise ratio, enabling emergence of large arrays of SPAD.

  15. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  16. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  17. Delay estimation for CMOS functional cells

    DEFF Research Database (Denmark)

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr...... on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment....

  18. Compact 2 Micron Seed Laser Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal is for the development of innovative compact, high power and extremely reliable 2 micron seed laser using newly developed Tm3+ doped germanate glass...

  19. Compact 2 Micron Seed Laser Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal is for the development of new compact, high power and extremely reliable 2 micron seed laser using newly developed Tm3+ doped germanate glass fibers,...

  20. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  1. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  2. Smart CMOS sensor for wideband laser threat detection

    Science.gov (United States)

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  3. Design and Experimental Evaluation of a 3rd Generation Addressable CMOS Piezoresistive Stress Sensing Test Chip

    Energy Technology Data Exchange (ETDEWEB)

    Sweet, J.N.; Peterson, D.W.; Hsia, A.H.

    1999-04-13

    Piezoresistive stress sensing chips have been used extensively for measurement of assembly related die surface stresses. Although many experiments can be performed with resistive structures which are directly bonded, for extensive stress mapping it is necessary to have a large number of sensor cells which can be addressed using CMOS logic circuitry. Our previous test chip, the ATC04, has 100 cells, each approximately 0.012 in. on a side, on a chip with a side dimension of 0.45 in. When a cell resistor is addressed, it is connected to a four terminal measurement bus through CMOS transmission gates. In theory, the gate resistances do not affect the measurement. In practice, there may be subtle effects which appear when very high accuracy is required. At high temperatures, gate leakage can increase to a point at which the resistor measurement becomes inaccurate. For ATC04 this occurred at or above 50 C. Here, we report on the first measurements obtained with a new prototype test chip, the ATC06. This prototype was fabricated in a 0.5 micron feature size silicided CMOS process using the MOSIS prototyping facility. The cell size was approximately 0.004 in. on a side. In order to achieve piezoresistive behavior for the implanted resistors it was necessary to employ a non-standard silicide ''blocking'' process. The stress sensitivity of both implanted and polysilicon blocked resistors is discussed. Using a new design strategy for the CMOS logic, it was possible to achieve a design in which only 5 signals had to be routed to a cell for addressing vs. 9 for ATC04. With our new design, the resistor under test is more effectively electrically isolated from other resistors on the chip, thereby improving high temperature performance. We present data showing operation up to 140 C.

  4. Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

    Science.gov (United States)

    Mohammed Napiah, Zul Atfyi Fauzan; Hishiki, Takuya; Iiyama, Koichi

    2017-07-01

    Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure.

  5. Experiments with synchronized sCMOS cameras

    Science.gov (United States)

    Steele, Iain A.; Jermak, Helen; Copperwheat, Chris M.; Smith, Robert J.; Poshyachinda, Saran; Soonthorntham, Boonrucksar

    2016-07-01

    Scientific-CMOS (sCMOS) cameras can combine low noise with high readout speeds and do not suffer the charge multiplication noise that effectively reduces the quantum efficiency of electron multiplying CCDs by a factor 2. As such they have strong potential in fast photometry and polarimetry instrumentation. In this paper we describe the results of laboratory experiments using a pair of commercial off the shelf sCMOS cameras based around a 4 transistor per pixel architecture. In particular using a both stable and a pulsed light sources we evaluate the timing precision that may be obtained when the cameras readouts are synchronized either in software or electronically. We find that software synchronization can introduce an error of 200-msec. With electronic synchronization any error is below the limit ( 50-msec) of our simple measurement technique.

  6. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  7. A Standard CMOS Humidity Sensor without Post-Processing

    OpenAIRE

    Oleg Nizhnik; Kazusuke Maenaka; Kohei Higuchi

    2011-01-01

    A 2 µW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  8. Challenges & Roadmap for Beyond CMOS Computing Simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-12-01

    Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

  9. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...

  10. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  11. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  12. Efavirenz Dissolution Enhancement I: Co-Micronization

    Directory of Open Access Journals (Sweden)

    Helvécio Vinícius Antunes Rocha

    2012-12-01

    Full Text Available AIDS constitutes one of the most serious infectious diseases, representing a major public health priority. Efavirenz (EFV, one of the most widely used drugs for this pathology, belongs to the Class II of the Biopharmaceutics Classification System for drugs with very poor water solubility. To improve EFV’s dissolution profile, changes can be made to the physical properties of the drug that do not lead to any accompanying molecular modifications. Therefore, the study objective was to develop and characterize systems with efavirenz able to improve its dissolution, which were co-processed with sodium lauryl sulfate (SLS and polyvinylpyrrolidone (PVP. The technique used was co-micronization. Three different drug:excipient ratios were tested for each of the two carriers. The drug dispersion dissolution results showed significant improvement for all the co-processed samples in comparison to non-processed material and corresponding physical mixtures. The dissolution profiles obtained for dispersion with co-micronized SLS samples proved superior to those of co-micronized PVP, with the proportion (1:0.25 proving the optimal mixture. The improvements may be explained by the hypothesis that formation of a hydrophilic layer on the surface of the micronized drug increases the wettability of the system formed, corroborated by characterization results indicating no loss of crystallinity and an absence of interaction at the molecular level.

  13. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  14. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  15. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation...

  16. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  17. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  18. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, H.; Klumperink, Eric A.M.; Venkatesh, Srinivasan; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel

  19. Smart temperature sensors in standard CMOS

    NARCIS (Netherlands)

    Makinwa, K.A.A.

    2010-01-01

    A smart temperature sensor is an integrated system consisting of a temperature sensor, its bias circuitry and an analog-to-digital converter (ADC). When manufactured in CMOS technology, such sensors have found widespread use due to their low cost, small size and ease of use. In this paper the basic

  20. A fail-safe CMOS logic gate

    Science.gov (United States)

    Bobin, V.; Whitaker, S.

    1990-01-01

    This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

  1. Transmission Lines in CMOS: An Explorative Study

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Kreienkamp, R.; Ellermeyer, T.; Langmann, U.

    On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important

  2. On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

    Directory of Open Access Journals (Sweden)

    Hongyi Mi

    2017-03-01

    Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

  3. Low-Power SOI CMOS Transceiver

    Science.gov (United States)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  4. Current-Mode CMOS A/D Converter for pA to nA Input Currents

    DEFF Research Database (Denmark)

    Breten, Madalina; Lehmann, Torsten; Bruun, Erik

    1999-01-01

    This paper describes a current mode A/D converter designed for a maximum input current range of 5nA and a resolution of the order of 1pA. The converter is designed for a potentiostat for amperometric chemical sensors and provides a constant polarization voltage for the measuring electrode....... A prototype chip using the dual slope conversion method has been fabricated in a 0.7micron CMOS process. Experimental results from this converter are reported. Design problems and limitations of the converter are discussed and a new conversion technique providing a larger dynamic range and easy calibration...

  5. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  6. A CMOS-based high-resolution fluoroscope (HRF) detector prototype with 49.5μm pixels for use in endovascular image guided interventions (EIGI)

    Science.gov (United States)

    Russ, M.; Shankar, A.; Setlur Nagesh, S. V.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2017-03-01

    X-ray detectors to meet the high-resolution requirements for endovascular image-guided interventions (EIGIs) are being developed and evaluated. A new 49.5-micron pixel prototype detector is being investigated and compared to the current suite of high-resolution fluoroscopic (HRF) detectors. This detector featuring a 300-micron thick CsI(Tl) scintillator, and low electronic noise CMOS readout is designated the HRF- CMOS50. To compare the abilities of this detector with other existing high resolution detectors, a standard performance metric analysis was applied, including the determination of the modulation transfer function (MTF), noise power spectra (NPS), noise equivalent quanta (NEQ), and detective quantum efficiency (DQE) for a range of energies and exposure levels. The advantage of the smaller pixel size and reduced blurring due to the thin phosphor was exemplified when the MTF of the HRF-CMOS50 was compared to the other high resolution detectors, which utilize larger pixels, other optical designs or thicker scintillators. However, the thinner scintillator has the disadvantage of a lower quantum detective efficiency (QDE) for higher diagnostic x-ray energies. The performance of the detector as part of an imaging chain was examined by employing the generalized metrics GMTF, GNEQ, and GDQE, taking standard focal spot size and clinical imaging parameters into consideration. As expected, the disparaging effects of focal spot unsharpness, exacerbated by increasing magnification, degraded the higher-frequency performance of the HRF-CMOS50, while increasing scatter fraction diminished low-frequency performance. Nevertheless, the HRF-CMOS50 brings improved resolution capabilities for EIGIs, but would require increased sensitivity and dynamic range for future clinical application.

  7. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    Science.gov (United States)

    Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

    2011-10-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  8. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Science.gov (United States)

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

  9. Spectrum acquisition of detonation based on CMOS

    Science.gov (United States)

    Li, Yan; Bai, Yonglin; Wang, Bo; Liu, Baiyu; Xue, Yingdong; Zhang, Wei; Gou, Yongsheng; Bai, Xiaohong; Qin, Junjun; Xian, Ouyang

    2010-10-01

    The detection of high-speed dynamic spectrum is the main method to acquire transient information. In order to obtain the large amount spectral data in real-time during the process of detonation, a CMOS-based system with high-speed spectrum data acquisition is designed. The hardware platform of the system is based on FPGA, and the unique characteristic of CMOS image sensors in the rolling shutter model is used simultaneously. Using FPGA as the master control chip of the system, not only provides the time sequence for CIS, but also controls the storage and transmission of the spectral data. In the experiment of spectral data acquisition, the acquired information is transmitted to the host computer through the CameraLink bus. The dynamic spectral curve is obtained after the subsequent processing. The experimental results demonstrate that this system is feasible in the acquisition and storage of high-speed dynamic spectrum information during the process of detonation.

  10. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  11. Recent X-ray hybrid CMOS detector developments and measurements

    Science.gov (United States)

    Hull, Samuel V.; Falcone, Abraham D.; Burrows, David N.; Wages, Mitchell; Chattopadhyay, Tanmoy; McQuaide, Maria; Bray, Evan; Kern, Matthew

    2017-08-01

    The Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors (TIS), have progressed their efforts to improve soft X-ray Hybrid CMOS detector (HCD) technology on multiple fronts. Having newly acquired a Teledyne cryogenic SIDECARTM ASIC for use with HxRG devices, measurements were performed with an H2RG HCD and the cooled SIDECARTM. We report new energy resolution and read noise measurements, which show a significant improvement over room temperature SIDECARTM operation. Further, in order to meet the demands of future high-throughput and high spatial resolution X-ray observatories, detectors with fast readout and small pixel sizes are being developed. We report on characteristics of new X-ray HCDs with 12.5 micron pitch that include in-pixel CDS circuitry and crosstalk-eliminating CTIA amplifiers. In addition, PSU and TIS are developing a new large-scale array Speedster-EXD device. The original 64 × 64 pixel Speedster-EXD prototype used comparators in each pixel to enable event driven readout with order of magnitude higher effective readout rates, which will now be implemented in a 550 × 550 pixel device. Finally, the detector lab is involved in a sounding rocket mission that is slated to fly in 2018 with an off-plane reflection grating array and an H2RG X-ray HCD. We report on the planned detector configuration for this mission, which will increase the NASA technology readiness level of X-ray HCDs to TRL 9.

  12. Supply Voltage Glitches Effects on CMOS Circuits

    OpenAIRE

    Djellid-Ouar, Anissa; Cathébras, Guy; Bancel, Frédéric

    2006-01-01

    International audience; Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers. . . ) ...

  13. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique......, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique....

  14. 10 Gb/s CMOS photonics technology

    Science.gov (United States)

    Gunn, Cary

    2006-02-01

    Freescale's production 0.13μm SOI process is used to fabricate all required electrical and optical components for 10Gb interconnect up to 2000m using only 1.7W. The optical transceiver cores are monolithically fabricated with CMOS circuitry required for bias and control as well as the electrical PHY interface. Optical multiplexing of 4 to 10 channels allows scaling to 40/100Gb.

  15. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  16. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  17. A 205GHz Amplifier in 90nm CMOS Technology

    Science.gov (United States)

    2017-03-01

    A 205GHz Amplifier in 90nm CMOS Technology Shahab Ardalan, Senior Member, IEEE Electrical Department, Charles W. Davidson College of Engineering...greater CMOS technologies . Keywords: Amplifier, neutralization, parasitic, Psat, P1dB.   Introduction Millimeter-wave and sub-mm-wave (THz band...amplifier has been implemented and fabricated in 90nm CMOS technology . The proposed amplifier attained a gain of 10.5 dB whilst consuming a dc power

  18. Behavior of faulty double BJT BiCMOS logic gates

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  19. A standard CMOS humidity sensor without post-processing.

    Science.gov (United States)

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 μW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  20. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  1. Interferometric comparison of the performance of a CMOS and sCMOS detector

    Science.gov (United States)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  2. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-09-21

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  3. Fundamental performance differences of CMOS and CCD imagers: part V

    Science.gov (United States)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  4. Integrated X-ray and charged particle active pixel CMOS sensor arrays using an epitaxial silicon sensitive region

    Energy Technology Data Exchange (ETDEWEB)

    Kleinfelder, Stuart; Bichsel, Hans; Bieser, Fred; Matis, Howard S.; Rai, Gulshan; Retiere, Fabrice; Weiman, Howard; Yamamoto, Eugene

    2002-07-01

    Integrated CMOS Active Pixel Sensor (APS) arrays have been fabricated and tested using X-ray and electron sources. The 128 by 128 pixel arrays, designed in a standard 0.25 micron process, use a {approx}10 micron epitaxial silicon layer as a deep detection region. The epitaxial layer has a much greater thickness than the surface features used by standard CMOS APS, leading to stronger signals and potentially better signal-to-noise ratio (SNR). On the other hand, minority carriers confined within the epitaxial region may diffuse to neighboring pixels, blur images and reduce peak signal intensity. But for low-rate, sparse-event images, centroid analysis of this diffusion may be used to increase position resolution. Careful trade-offs involving pixel size and sense-node area verses capacitance must be made to optimize overall performance. The prototype sensor arrays, therefore, include a range of different pixel designs, including different APS circuits and a range of different epitaxial layer contact structures. The fabricated arrays were tested with 1.5 GeV electrons and Fe-55 X-ray sources, yielding a measured noise of 13 electrons RMS and an SNR for single Fe-55 X-rays of greater than 38.

  5. Current-mode CMOS hybrid image sensor

    Science.gov (United States)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  6. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  7. Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

    Science.gov (United States)

    Yoshida, Eiji; Sakai, Yasufumi; Oishi, Kazuaki; Yamazaki, Hiroshi; Mori, Toshihiko; Yamaura, Shinji; Suto, Kazuo; Tanaka, Tetsu

    2014-01-01

    A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

  8. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  9. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  10. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  11. Monolithic CMOS imaging x-ray spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  12. CMOS current controlled fully balanced current conveyor

    Energy Technology Data Exchange (ETDEWEB)

    Wang Chunhua; Zhang Qiujing; Liu Haiguang, E-mail: wch1227164@sina.co [School of Computer and Communication, Hunan University, Changsha 410082 (China)

    2009-07-15

    This paper presents a current controlled fully balanced second-generation current conveyor circuit (CF-BCCII). The proposed circuit has the traits of fully balanced architecture, and its X-Y terminals are current controllable. Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications. The CFBCCII circuits and the two filters were fabricated with chartered 0.35-{mu}m CMOS technology; with {+-}1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW. Comparisons between measured and HSpice simulation results are also given.

  13. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  14. Method and circuitry for CMOS transconductor linearization

    OpenAIRE

    Kundur Subramaniyan, H.; Klumperink, Eric A.M.; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a sec...

  15. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  16. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  17. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  18. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  19. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  20. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  1. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.......5 mum CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/rootHz. The amplifier power consumption is 275 muW, drawn...

  2. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  3. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  4. Deformation Behavior of Sub-micron and Micron Sized Alumina Particles in Compression.

    Energy Technology Data Exchange (ETDEWEB)

    Sarobol, Pylin; Chandross, Michael E.; Carroll, Jay; Mook, William; Boyce, Brad; Kotula, Paul Gabriel; McKenzie, Bonnie Beth; Bufford, Daniel Charles; Hall, Aaron Christopher.

    2014-09-01

    The ability to integrate ceramics with other materials has been limited due to high temperature (>800degC) ceramic processing. Recently, researchers demonstrated a novel process , aerosol deposition (AD), to fabricate ceramic films at room temperature (RT). In this process, sub - micro n sized ceramic particles are accelerated by pressurized gas, impacted on the substrate, plastically deformed, and form a dense film under vacuum. This AD process eliminates high temperature processing thereby enabling new coatings and device integration, in which ceramics can be deposited on metals, plastics, and glass. However, k nowledge in fundamental mechanisms for ceramic particle s to deform and form a dense ceramic film is still needed and is essential in advancing this novel RT technology. In this wo rk, a combination of experimentation and atomistic simulation was used to determine the deformation behavior of sub - micron sized ceramic particle s ; this is the first fundamental step needed to explain coating formation in the AD process . High purity, singl e crystal, alpha alumina particles with nominal size s of 0.3 um and 3.0 um were examined. Particle characterization, using transmission electron microscopy (TEM ), showed that the 0.3 u m particles were relatively defect - free single crystals whereas 3.0 u m p articles were highly defective single crystals or particles contained low angle grain boundaries. Sub - micron sized Al 2 O 3 particles exhibited ductile failure in compression. In situ compression experiments showed 0.3um particles deformed plastically, fractured, and became polycrystalline. Moreover, dislocation activit y was observed within the se particles during compression . These sub - micron sized Al 2 O 3 particles exhibited large accum ulated strain (2 - 3 times those of micron - sized particles) before first fracture. I n agreement with the findings from experimentation , a tomistic simulation s of nano - Al 2 O 3 particles showed dislocation slip and

  5. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  6. Noise Properties of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1996-01-01

    The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise...... model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model...... is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current...

  7. The CMOS integration of a power inverter

    Science.gov (United States)

    Mannarino, Eric Francis

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this process using two topologies. The first is a cell-based switched-capacitor topology first presented by Ke Zou. The second is a novel topology that explores the advantage of using a bused input-output system, as in digital electronics. Simulations run on both topologies confirm the high-efficiency demonstrated in Zou’s process as well as the advantage the bus-based system has in output voltage levels.

  8. High-speed analog CMOS pipeline system

    Science.gov (United States)

    Möschen, J.; Caldwell, A.; Hervas, L.; Hosticka, B.; Kötz, U.; Sippach, B.

    1990-03-01

    We present a switched-capacitor readout system for high speed analog signals. It consists of a 10 MHz four-channel delay-line chip with 58 samples per channel and a 12 channel buffer chip with a sampling rate of 1 MHz and a depth of nine samples. In addition the buffer chip includes an analog multiplexer with 25 inputs for the buffer channels and for 13 additional unbuffered signals. Both chips have been fabricated in CMOS-technology and will be used for the readout of the ZEUS high resolution calorimeter. The circuit and chip concept will be presented and some design optimizations will be discussed. Measurements from integrated prototypes will be given including some experimental data from irradiated chips.

  9. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with mic......Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible...... with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...... platform and its integration in future electronic chips....

  10. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  11. Modulated CMOS camera for fluorescence lifetime microscopy.

    Science.gov (United States)

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. © 2015 Wiley Periodicals, Inc.

  12. Monolithic integration of a plasmonic sensor with CMOS technology

    Science.gov (United States)

    Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

    2017-02-01

    Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

  13. System and Circuit Design Aspects for CMOS Wireless Handset Receivers

    DEFF Research Database (Denmark)

    Mikkelsen, Jan H.

    The presented work deals with system and circuit design aspects for Complementary Metal Oxide Semiconductor (CMOS) implementations of wireless handset receivers. First, an overview, from a historic perspective, on the use of CMOS in cellular applications is provided. Based on this the tremendous...... developments in CMOS technology are considered and the short-comings from an analog design perspective are evaluated. The lack of high quality passive devices, inductors in particular, is found to be one of the major obstacles in achieving a fully integrated RF design based on CMOS. Following this, an overview...... practice to employ a full separation of different distortion mechanisms. While this approach is very useful when an implementation performance surplus is available it is not an option when a low-cost silicon technology is the target. To manage this, a simple approach that allows all interfering components...

  14. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  15. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

    2016-12-31

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  16. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  17. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  18. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  19. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    OpenAIRE

    Fangming Deng; Yigang He; Chaolong Zhang; Wei Feng

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate ...

  20. Model for EOS caused EF screening in CMOS VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Lisenker, B. [Tower Semiconductor Ltd., Migdal Haemek (Israel); Nevo, Y. [National Semiconductor Ltd., Herzlia B` (Israel)

    1995-12-31

    This paper introduced a Fault Model, capable to elucidate the sensitivity to Electrical Overstress (EOS) and Early Fault (EF) rising nature in CMOS VLSI circuit. The Model based on the general Percolation Theory applied to the CMOS technology. Early Failures screening technique employing this Model, shows strong correlation between rejected devices, EOS faults and EF rate. This technique is recommenced both as an EF screening test and a process reliability monitor.

  1. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  2. Modeling and simulation of TDI CMOS image sensors

    Science.gov (United States)

    Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

    2013-09-01

    In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

  3. A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

    DEFF Research Database (Denmark)

    Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid

    As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...... transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results...... obtained using the 70nm Berkeley predictive models, our proposed circuit increases the noise immunity by least 2times compared to previous circuits...

  4. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  5. Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

    CERN Document Server

    Bonacini, Sandro; Kloukinas, Kostas

    2007-01-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

  6. SU-E-I-25: Performance Evaluation of a Proposed CMOS-Based X-Ray Detector Using Linear Cascade Model Analysis.

    Science.gov (United States)

    Jain, A; Bednarek, D; Rudin, S

    2012-06-01

    The need for high-resolution, dynamic x-ray imaging capability for neurovascular applications has put an ever increasing demand on x-ray detector technology. Present state-of-the-art detectors such as flat panels have limited resolution and noise performance. A linear cascade model analysis was used to estimate the theoretical performance for a proposed CMOS-based detector. The proposed CMOS-based detector was assumed to have a 300-micron thick HL type CsI phosphor, 35-micron pixels, a variable gain light image intensifier (LU), and 400 electron readout noise. The proposed detector has a CMOS sensor coupled to an LII which views the output of the CsI phosphor. For the analysis the whole imaging chain was divided into individual stages characterized by one of the basic processes (stochastic/deterministic blurring, binomial selection, quantum gain, additive noise). Standard linear cascade modeling was used for the propagation of signal and noise through the stages and an RQA5 spectrum was assumed. The gain, blurring or transmission of different stages was either measured or taken from manufacturer's specifications. The theoretically calculated MTF and DQE for the proposed detector were compared with a high-resolution, high-sensitive Micro-Angio Fluoroscope (MAF), predecessor of the proposed detector. Signal and noise for each of the 19 stages in the complete imaging chain were calculated and showed improved performance. For example, at 5 cycles/mm the MTF and DQE were 0.08 and 0.28, respectively, for the CMOS detector compared to 0.05 and 0.07 for the MAF detector. The proposed detector will have improved MTF and DQE and slimmer physical dimension due to the elimination of the large fiber-optic taper used in the MAF. Once operational, the proposed CMOS detector will serve as a further improvement over standard flat panel detectors compared to the MAF which is already receiving a very positive reception by neuro-vascular interventionalists. (Support:NIH-Grant R01EB

  7. Electrothermal frequency references in standard CMOS

    CERN Document Server

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  8. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  9. Single Frequency Narrow Linewidth 2 Micron Laser Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA needs narrow linewidth lasers in the 1.5 or 2 micron wavelength regime for coherent Lidar applications. The laser should be tunable by several nm and frequency...

  10. RIVKIN THREE MICRON ASTEROID DATA V3.0

    Data.gov (United States)

    National Aeronautics and Space Administration — This data set is a collection of 3-micron spectra of 33 asteroids and Phobos and Deimos obtained by Andy Rivkin and collaborators. Nearly all these data have been...

  11. Apparatus for handling micron size range particulate material

    Science.gov (United States)

    Friichtenicht, J. F.; Roy, N. L. (Inventor)

    1968-01-01

    An apparatus for handling, transporting, or size classifying comminuted material was described in detail. Electrostatic acceleration techniques for classifying particles as to size in the particle range from 0.1 to about 100 microns diameter were employed.

  12. 1.55 Micron High Peak Power Fiber Amplifier Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, we propose to demonstrate and build a 1.55 micron single frequency high energy and high peak power fiber amplifier by developing an innovative...

  13. Two- and multi-terminal CMOS/BiCMOS Si LED’s

    Science.gov (United States)

    du Plessis, Monuko; Aharoni, Herzl; Snyman, Lukas W.

    2005-02-01

    Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented. The differences observed between avalanche and low-voltage field emission LED performance are presented. It is shown that the low-voltage devices exhibit a square-law light intensity vs. reverse current non-linearity at low-current levels, but a linear dependency at higher currents, compared to the linear behaviour of avalanche devices at all current levels. The detail spectral characteristics of the field emission devices are investigated, showing that in the non-linear region of operation, the shape of the emitted spectrum changes, with reduced short wavelength generation at lower current levels. Bipolar junction transistor (BJT) multi-terminal devices are also discussed, and the square-law behaviour of these devices is presented.

  14. Micronized Organic Magnesium Salts Enhance Opioid Analgesia in Rats.

    Directory of Open Access Journals (Sweden)

    Magdalena Bujalska-Zadrożny

    Full Text Available As previously reported, magnesium sulphate administered parenterally significantly increased an opioid antinociception in different kinds of pain. Since the typical form of magnesium salts are poorly and slowly absorbed from the gastrointestinal tract we examined whether their micronized form could increase opioids induced antinociception.In behavioural studies on rats morphine, tramadol and oxycodone together with magnesium (lactate dihydrate, hydroaspartate, chloride in micronized (particles of size D90 < 50 μm and conventional forms were used. Changes in pain thresholds were determined using mechanical stimuli. The intestinal absorption of two forms of magnesium lactate dihydrate (at the doses of 7.5 or 15 mg ions in the porcine gut sac model were also compared.Micronized form of magnesium lactate dihydrate or hydroaspartate but not chloride (15 mg of magnesium ions kg-1 enhanced the analgesic activity of orally administered opioids, significantly faster and more effective in comparison to the conventional form of magnesium salts (about 40% for oxycodone administered together with a micronized form of magnesium hydroaspartate. Moreover, in vitro studies of transport across porcine intestines of magnesium ions showed that magnesium salts administered in micronized form were absorbed from the intestines to a greater extent than the normal form of magnesium salts.The co-administration of micronized magnesium organic salts with opioids increased their synergetic analgesic effect. This may suggest an innovative approach to the treatment of pain in clinical practice.

  15. Characterization of active CMOS pixel sensors on high resistive substrate

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

    2016-07-01

    Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  16. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  17. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  18. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Science.gov (United States)

    2012-12-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors and...

  19. Prescribed 3-D Direct Writing of Suspended Micron/Sub-micron Scale Fiber Structures via a Robotic Dispensing System.

    Science.gov (United States)

    Yuan, Hanwen; Cambron, Scott D; Keynton, Robert S

    2015-06-12

    A 3-axis dispensing system is utilized to control the initiating and terminating fiber positions and trajectory via the dispensing software. The polymer fiber length and orientation is defined by the spatial positioning of the dispensing system 3-axis stages. The fiber diameter is defined by the prescribed dispense time of the dispensing system valve, the feed rate (the speed at which the stage traverses from an initiating to a terminating position), the gauge diameter of the dispensing tip, the viscosity and surface tension of the polymer solution, and the programmed drawing length. The stage feed rate affects the polymer solution's evaporation rate and capillary breakup of the filaments. The dispensing system consists of a pneumatic valve controller, a droplet-dispensing valve and a dispensing tip. Characterization of the direct write process to determine the optimum combination of factors leads to repeatedly acquiring the desired range of fiber diameters. The advantage of this robotic dispensing system is the ease of obtaining a precise range of micron/sub-micron fibers onto a desired, programmed location via automated process control. Here, the discussed self-assembled micron/sub-micron scale 3D structures have been employed to fabricate suspended structures to create micron/sub-micron fluidic devices and bioengineered scaffolds.

  20. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    Science.gov (United States)

    Woo, D. S.

    1982-01-01

    The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

  1. A demonstrator analog signal processing circuit in a radiation hard SOI-CMOS technology

    CERN Document Server

    Anghinolfi, Francis; Campbell, M; Heijne, Erik H M; Jarron, Pierre; Meddeler, G; CERN. Geneva. Detector Research and Development Committee

    1990-01-01

    It is proposed to develop a demonstrator integrated circuit for particle detector analog signal processing using the advanced 1.2 micron HSOI3-HD Silicon-on-Insulator (SOI) CMOS radiation hard technology of Thomson-TMS, which has recently become accessible for selected civilian applications. The characteristics announced for this process promise survivability after a total dose in excess of 10 Mrad (SiO2) and 10**14 to 10**15 n/cm2, which is probably satisfactory for applications in LHC detector systems. The properties of such a SOI process look promising, in particular regarding speed. In view of the special analog requirements in the particle physics environment,one should verify the analog characteristics before and after irradiation by producing a demonstrator signal processing circuit which incorporates the most vital functional blocks. This demonstrator would consist of a low noise front-end amplifier, a comparator and an analog pipeline element with associated logic, following the scheme of the Hierarc...

  2. Dense Heterogeneous Integration for InP Bi-CMOS Technology

    Science.gov (United States)

    2009-05-01

    many mixed signal applications, having circuits composed of both Si CMOS, which possesses low power dissipation and high transistor count, and...compound semiconductor transistors with high-speed high-voltage swing performance would be advantageous. In general, heterogeneous integration (HI) of...Fastest CMOS and HBTs  / >109LowHighCoSMOS Lags latest CMOS᝺ 6ModModSiGe HBT No precision fast device, low drive >109LowModCMOS BJT only

  3. A CMOS humidity sensor for passive RFID sensing applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-05-16

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  4. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2014-05-01

    Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  5. Analytic models of CMOS logic in various regimes

    Directory of Open Access Journals (Sweden)

    Dokić Branko

    2014-01-01

    Full Text Available In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.

  6. Design of CMOS logic gates for TID radiation

    Science.gov (United States)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  7. Equalizing Si photodetectors fabricated in standard CMOS processes

    Science.gov (United States)

    Guerrero, E.; Aguirre, J.; Sánchez-Azqueta, C.; Royo, G.; Gimeno, C.; Celma, S.

    2017-05-01

    This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

  8. Piezoresistive Sensors Development Using Monolithic CMOS MEMS Technology

    Directory of Open Access Journals (Sweden)

    A. Chaehoi

    2011-04-01

    Full Text Available This paper presents the development of a monolithic CMOS-MEMS platform under the iDesign and SemeMEMS projects with the aim of jointly providing an open access “one-stop-shop” design and prototyping facility for integrated CMOS-MEMS. This work addresses the implementation of a 3-axis accelerometer and a pressure sensor using Semefab’s in-house 2-poly 1-metal CMOS process on a 380/4/15 μm SOI wafer; the membrane and the proof mass being micromachined using double-sided Deep Reactive Ion Etching (DRIE. This monolithic approach promises, in high volume production and using low complexity processes, a dramatic cost reduction over hybrid sensors. Furthermore, the embedded signal conditioning and the low-noise level in polysilicon gauges enables high performance to be achieved by implementing dedicated on-chip amplification and filtering circuitry.

  9. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications.

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-31

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  10. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  11. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri...... of the electrical parameters of n-channel and p-channel transistors. The magnetron sputtering technique is shown to be compatible with standard CMOS electronics without any restriction of the metal types and annealing requirements.......This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation...

  12. X-ray Hybrid CMOS Detectors : Recent progress in development and characterization

    Science.gov (United States)

    Chattopadhyay, Tanmoy; Falcone, Abraham; Burrows, David N.

    2017-08-01

    PennState high energy astronomy laboratory has been working on the development and characterization of Hybrid CMOS Detectors (HCDs) for last few years in collaboration with Teledyne Imaging Sensors (TIS). HCDs are preferred over X-ray CCDs due to their higher and flexible read out rate, radiation hardness and low power which make them more suitable for next generation large area X-ray telescopic missions. An H2RG detector with 36 micron pixel pitch and 18 micron ROIC, has been selected for a sounding rocket flight in 2018. The H2RG detector provides ~2.5 % energy resolution at 5.9 keV and ~7 e- read noise when coupled to a cryo-SIDECAR. We could also detect a clear Oxygen line (~0.5 keV) from the detector implying a lower energy threshold of ~0.3 keV. Further improvement in the energy resolution and read noise is currently under progress. We have been working on the characterization of small pixel HCDs (12.5 micron pixel; smallest pixel HCDs developed so far) which is important for the development of next generation high resolution X-ray spectroscopic instrument based on HCDs. Event recognition in HCDs is another exciting prospect which have been successfully shown to work with a 64 X 64 pixel prototype SPEEDSTAR-EXD which use comparators at each pixel to read out only those pixels having detectable signal, thereby providing an order of magnitude improvement in the read out rate. Currently, we are working on the development of a large area SPEEDSTAR-EXD array for the development of a full fledged instrument. HCDs due to their fast read out, can also be explored as a large FOV instrument to study GRB afterglows and variability and spectroscopic study of other astrophysical transients. In this context, we are characterizing a Lobster-HCD system at multiple energies and multiple off-axis angles for future rocket or CubeSate experiments. In this presentation, I will briefly present these new developments and experiments with HCDs and the analysis techniques.

  13. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  14. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Science.gov (United States)

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as respondents...

  15. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  16. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  17. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  18. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  19. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  20. A 0.5-GHz CMOS digital RF memory chip

    Science.gov (United States)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  1. An introduction to deep submicron CMOS for vertex applications

    CERN Document Server

    Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

    2001-01-01

    Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

  2. Improved properties of micronized genetically modified flax fibers.

    Science.gov (United States)

    Dymińska, Lucyna; Szatkowski, Michał; Wróbel-Kwiatkowska, Magdalena; Zuk, Magdalena; Kurzawa, Adam; Syska, Wojciech; Gągor, Anna; Zawadzki, Mirosław; Ptak, Maciej; Mączka, Mirosław; Hanuza, Jerzy; Szopa, Jan

    2012-12-15

    The aim of this study was to investigate the effect of micronization on the compound content, crystalline structure and physicochemical properties of fiber from genetically modified (GM) flax. The GM flax was transformed with three bacterial (Ralstonia eutropha) genes coding for enzymes of polyhydroxybutyrate (PHB) synthesis and under the control of the vascular bundle promoter. The modification resulted in fibers containing the 3-hydroxybutyrate polymer bound to cellulose via hydrogen and ester bonds and antioxidant compounds (phenolic acids, vanillin, vitexin, etc.). The fibers appeared to have a significantly decreased particle size after 20h of ball-milling treatment. Micronized fibers showed reduced phenolic contents and antioxidant capacity compared to the results for untreated fibers. An increased level of PHB was also detected. Micronization introduces structural changes in fiber constituents (cellulose, hemicellulose, pectin, lignin, PHB) and micronized fibers exhibit more functional groups (hydroxyl, carboxyl) derived from those constituents. It is thus concluded that micronization treatments improve the functional properties of the fiber components. Copyright © 2013 Elsevier B.V. All rights reserved.

  3. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  4. A Wide-Band CMOS Injection Locked Frequency Divider

    NARCIS (Netherlands)

    Acar, M.; Leenaerts, Domine; Nauta, Bram

    In this paper we propose a novel inductorless injection-locked frequency divider (ILFD) that can make divisions with ratios 2,4,6 and 8 with wide locking ranges. Fabricated in a digital 0.18 μm CMOS process the divider can operate up to 15 GHz. The measured locking ranges of the divider for division

  5. Design for manufacturability and yield for nano-scale CMOS

    CERN Document Server

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  6. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  7. Temperature Sensors Integrated into a CMOS Image Sensor

    NARCIS (Netherlands)

    Abarca Prouza, A.N.; Xie, S.; Markenhof, Jules; Theuwissen, A.J.P.

    2017-01-01

    In this work, a novel approach is presented for measuring relative temperature variations inside the pixel array of a CMOS image sensor itself. This approach can give important information when compensation for dark (current) fixed pattern noise (FPN) is needed. The test image sensor consists of

  8. A CMOS four-quadrant analog current multiplier

    NARCIS (Netherlands)

    Wiegerink, Remco J.

    1991-01-01

    A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual

  9. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...

  10. High-speed photodiodes in standard CMOS technology

    NARCIS (Netherlands)

    Radovanovic, S.

    2004-01-01

    This thesis describes high-speed photodiodes in standard CMOS technology which allow monolithic integration of optical receivers for short-haul communication. The electronics for (multiple users) long-haul communication is very expensive (InP, GaAs), but the usage is justified by the large number of

  11. Monolithic optical link in silicon-on-insulator CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal; Agarwal, Vishal Vishal; Hueting, Raymond Josephus Engelbart; Schmitz, Jurriaan; Annema, Anne J.

    2017-01-01

    This work presents a monolithic laterally-coupled wide-spectrum (350 nm < λ < 1270 nm) optical link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical

  12. High-speed lateral polysilicon photodiode in standard CMOS

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    2003-01-01

    A high-performance lateral polysilicon photodiode was designed in standard 0.18 /spl mu/m CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which figure was limited by the measurement equipment. The high intrinsic

  13. CMOS monolithic pixel sensors research and development at LBNL

    Indian Academy of Sciences (India)

    Abstract. This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS ...

  14. A toroidal inductor integrated in a standard CMOS process

    DEFF Research Database (Denmark)

    Vandi, Luca; Andreani, Pietro; Temporiti, Enrico

    2007-01-01

    This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches...

  15. Fundamental Characteristics of a Pinned Photodiode CMOS Pixels

    NARCIS (Netherlands)

    Xu, Y.

    2015-01-01

    This thesis gives an insightful analysis of the pinned photodiode 4T CMOS pixel from three different aspects. Firstly, from the charge accumulated aspect, the PPD full well capacity and related parameters of influence are investigated such as the pinning voltage, and transfer gate potential barrier.

  16. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Directory of Open Access Journals (Sweden)

    Rescigno R.

    2014-03-01

    Full Text Available Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  17. High-speed lateral polysilicon photodiode in standard CMOS

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    A high-performance lateral polysilicon photodiode was designed in standard 0.18 μm CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which figure was limited by the measurement equipment. The high intrinsic (physical)

  18. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    Directory of Open Access Journals (Sweden)

    Mao-Chen Liu

    2010-02-01

    Full Text Available This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

  19. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2017-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  20. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  1. CMOS in-pixel optical pulse frequency modulator

    Science.gov (United States)

    Nel, Nicolaas E.; du Plessis, M.; Joubert, T.-H.

    2016-02-01

    This paper covers the design of a complementary metal oxide semiconductor (CMOS) pixel readout circuit with a built-in frequency conversion feature. The pixel contains a CMOS photo sensor along with all signal-to-frequency conversion circuitry. An 8×8 array of these pixels is also designed. Current imaging arrays often use analog-to-digital conversion (ADC) and digital signal processing (DSP) techniques that are off-chip1. The frequency modulation technique investigated in this paper is preferred over other ADC techniques due to its smaller size, and the possibility of a higher dynamic range. Careful considerations are made regarding the size of the components of the pixel, as various characteristics of CMOS devices are limited by decreasing the scale of the components2. The methodology used was the CMOS design cycle for integrated circuit design. All components of the pixel were designed from first principles to meet necessary requirements of a small pixel size (30×30 μm2) and an output resolution greater than that of an 8-bit ADC. For the photodetector, an n+-p+/p-substrate diode was designed with a parasitic capacitance of 3 fF. The analog front-end stage was designed around a Schmitt trigger circuit. The photo current is integrated on an integration capacitor of 200 fF, which is reset when the Schmitt trigger output voltage exceeds a preset threshold. The circuit schematic and layout were designed using Cadence Virtuoso and the process used was the AMS CMOS 350 nm process using a power supply of 5V. The simulation results were confirmed to comply with specifications, and the layout passed all verification checks. The dynamic range achieved is 58.828 dB per pixel, with the output frequencies ranging from 12.341kHz to 10.783 MHz. It is also confirmed that the output frequency has a linear relationship to the photocurrent generated by the photodiode.

  2. Micron-sized polymer particles from tanzanian cashew nut shell ...

    African Journals Online (AJOL)

    Micron-sized polymer particles (MSPP) were prepared by formaldehyde condensation polymerization of cashew nut shell liquid (CNSL) previously emulsified with sodium lauryl sulphate. The sizes of the MSPP were found to range from 0.1 to 4.4 mm. Increasing the emulsifier concentration had the effect of increasing the ...

  3. Micron-sized polymer particles from Tanzanian cashew nut shell

    African Journals Online (AJOL)

    a

    ABSTRACT. Micron-sized polymer particles (MSPP) were prepared by formaldehyde condensation polymerization of cashew nut shell liquid (CNSL) previously emulsified with sodium lauryl sulphate. The sizes of the MSPP were found to range from 0.1 to 4.4 μm. Increasing the emulsifier concentration had the effect of ...

  4. INFLUENCE OF GRAIN DEBRIS ON THE MICRONIZATION PROCESS

    Directory of Open Access Journals (Sweden)

    D. S. Kochanov

    2014-01-01

    Full Text Available Summary. Effect of weed, mineral and metallomagnetic impurities in the grain feedstock to micronization process was investigated. In laboratory and production conditions conducted a study on the influence of the impurity content in the treated grain, different size, density and metallomagnetic properties on the process of micronization. Trash content in feed grains of barley, wheat and corn according to current standards for grain must match the basic approach, and do not exceed 5 % , including mineral impurities - 1.0%. No restrictions on metallomagnetic and organic impurities. Dependence of the clearing of mineral impurities in various capacities device for separating stones was installed. Most effectively, 95-98 % grain (especially barley where these studies were carried out allocated pebbles, i.e. mineral impurity density which is almost twice the density of barley. Lumps of earth, the density of which is virtually identical to the density of barley allocated a maximum of 70%. Setting in the shop micronization grain separator and magnetic separator device for separating stones led to increase the reliability of the process equipment and process stability micronization. Year and a half after the reconstruction of the workshop there were no failure nodes of device for flattening. A particularly important consideration is to increase the duration of exploitation of the working surfaces of the rolls crusher to guaranteed by period (not less than 1 year.

  5. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    Science.gov (United States)

    Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

    2013-07-01

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

  6. Variability of Jupiter's Five-Micron Hot Spot Inventory

    Science.gov (United States)

    Yanamandra-Fisher, Padma A.; Orton, G. S.; Wakefield, L.; Rogers, J. H.; Simon-Miller, A. A.; Boydstun, K.

    2012-01-01

    Global upheavals on Jupiter involve changes in the albedo of entire axisymmetric regions, lasting several years, with the last two occurring in 1989 and 2006. Against this backdrop of planetary-scale changes, discrete features such as the Great Red Spot (GRS), and other vortices exhibit changes on shorter spatial- and time-scales. We track the variability of the discrete equatorial 5-micron hot spots, semi-evenly spaced in longitude and confined to a narrow latitude band centered at 6.5degN (southern edge of the North Equatorial Belt, NEB), abundant in Voyager images. Tantalizingly similar patterns were observed in the visible (bright plumes and blue-gray regions), where reflectivity in the red is anti-correlated with 5-microns thermal radiance. Ortiz et al. (1998, GRL, 103) characterized the latitude and drift rates of the hot spots, including the descent of the Galileo probe at the southern edge of a 5-micron hot spot, as the superposition of equatorial Rossby waves, with phase speeds between 99 - 103m/s, relative to System III. We note that the high 5-micron radiances correlate well but not perfectly with high 8.57-micron radiances. Because the latter are modulated primarily by changes in the upper ammonia (NH3) ice cloud opacity, this correlation implies that changes in the ammonia ice cloud field may be responsible for the variability seen in the 5-m maps. During the NEB fade (2011 - early 2012), however, these otherwise ubiquitous features were absent, an atmospheric state not seen in decades. The ongoing NEB revival indicates nascent 5-m hot spots as early as April 2012, with corresponding visible dark spots. Their continuing growth through July 2012 indicates the possit.le re-establishment of Rossby waves. The South Equatorial Belt (SEB) and NEB revivals began similarly with an instability that developed into a major outbreak, and many similarities in the observed propagation of clear regions.

  7. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  8. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  9. Nanophotonic integration in state-of-the-art CMOS foundries.

    Science.gov (United States)

    Orcutt, Jason S; Khilo, Anatol; Holzwarth, Charles W; Popović, Milos A; Li, Hanqing; Sun, Jie; Bonifield, Thomas; Hollingsworth, Randy; Kärtner, Franz X; Smith, Henry I; Stojanović, Vladimir; Ram, Rajeev J

    2011-01-31

    We demonstrate a monolithic photonic integration platform that leverages the existing state-of-the-art CMOS foundry infrastructure. In our approach, proven XeF2 post-processing technology and compliance with electronic foundry process flows eliminate the need for specialized substrates or wafer bonding. This approach enables intimate integration of large numbers of nanophotonic devices alongside high-density, high-performance transistors at low initial and incremental cost. We demonstrate this platform by presenting grating-coupled, microring-resonator filter banks fabricated in an unmodified 28 nm bulk-CMOS process by sharing a mask set with standard electronic projects. The lithographic fidelity of this process enables the high-throughput fabrication of second-order, wavelength-division-multiplexing (WDM) filter banks that achieve low insertion loss without post-fabrication trimming.

  10. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  11. Smart CMOS image sensor for lightning detection and imaging.

    Science.gov (United States)

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

  12. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  13. CMOS nanoelectrode array for all-electrical intracellular electrophysiological imaging

    Science.gov (United States)

    Abbott, Jeffrey; Ye, Tianyang; Qin, Ling; Jorgolli, Marsela; Gertner, Rona S.; Ham, Donhee; Park, Hongkun

    2017-05-01

    Developing a new tool capable of high-precision electrophysiological recording of a large network of electrogenic cells has long been an outstanding challenge in neurobiology and cardiology. Here, we combine nanoscale intracellular electrodes with complementary metal-oxide-semiconductor (CMOS) integrated circuits to realize a high-fidelity all-electrical electrophysiological imager for parallel intracellular recording at the network level. Our CMOS nanoelectrode array has 1,024 recording/stimulation 'pixels' equipped with vertical nanoelectrodes, and can simultaneously record intracellular membrane potentials from hundreds of connected in vitro neonatal rat ventricular cardiomyocytes. We demonstrate that this network-level intracellular recording capability can be used to examine the effect of pharmaceuticals on the delicate dynamics of a cardiomyocyte network, thus opening up new opportunities in tissue-based pharmacological screening for cardiac and neuronal diseases as well as fundamental studies of electrogenic cells and their networks.

  14. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    CERN Document Server

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  15. Micromachined high-performance RF passives in CMOS substrate

    Science.gov (United States)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  16. A passive CMOS pixel sensor for the high luminosity LHC

    Energy Technology Data Exchange (ETDEWEB)

    Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

    2016-07-01

    The high luminosity upgrade for the Large Hadron Collider at CERN requires a new inner tracking detector for the ATLAS experiment. About 200 m{sup 2} of silicon detectors are needed demanding new, low cost hybridization- and sensor technologies. One promising approach is to use commercial CMOS technologies to produce the passive sensor for a hybrid pixel detector design. In this talk a fully functional prototype of a 300 μm thick, backside biased CMOS pixel sensor in 150 nm LFoundry technology is presented. The sensor is bump bonded to the ATLAS FE-I4 with AC and DC coupled pixels. Results like leakage current, noise performance, and charge collection efficiency are presented and compared to the actual ATLAS pixel sensor design.

  17. LED pumped micron-scale all-silicon Raman amplifier

    Science.gov (United States)

    Datta, Tanmoy; Sen, Mrinal

    2017-10-01

    A micron-scale all-silicon Raman amplifier has been proposed in this paper, exploiting the giant Raman gain of silicon nanocrystal material along with the extreme optical confinement of slotted photonic crystal waveguide. Light Emitting Diode (LED) has been considered here for low-cost optical pumping and the possibility of on-chip integration. At the same time, LED pumping eradicates the temporal impairment of output pulses which is otherwise unavoidable in case of continuous wave laser pumping. An overall gain of 3.22 dB has been achieved for a 400 Gbps input pulse train with a waveguide length of the amplifier which is as small as 4 μm. Moreover, the strong electroluminescence of silicon nanocrystal opens up the possibility of integrating the pump source on the same platform and, hence, expedites the future scope of realizing micron-scale silicon Raman laser without external pump source.

  18. Non-uniform plastic deformation of micron scale objects

    DEFF Research Database (Denmark)

    Niordson, Christian Frithiof; Hutchinson, J. W.

    2003-01-01

    Significant increases in apparent flow strength are observed when non-uniform plastic deformation of metals occurs at the scale ranging from roughly one to ten microns. Several basic plane strain problems are analyzed numerically in this paper based on a new formulation of strain gradient...... plasticity. The problems are the tangential and normal loading of a finite rectangular block of material bonded to rigid platens and having traction-free ends, and the normal loading of a half-space by a flat, rigid punch. The solutions illustrate fundamental features of plasticity at the micron scale...... that are not captured by conventional plasticity theory. These include the role of material length parameters in establishing the size dependence of strength and the elevation of resistance to plastic flow resulting from constraint on plastic flow at boundaries. Details of the finite element method employed...

  19. Prospects for use of micronized coal in power industry

    Energy Technology Data Exchange (ETDEWEB)

    Burdukov, A.P.; Konovalov, V.V.; Yusupov, T.S. [Inst. of Thermophysics SB RAS, Novosibirsk (Russian Federation)

    2002-07-01

    Heat-and-power engineering is the basis for industrial development of developed countries and the main energy fuel for plants is coal. The main directions in improvement of coal energy technologies are related to better ignition of fuel and to gas and mazut substitution with pulverized coal. This paper considerers the prospects of energy coal enrichment and the method for production of ultrafine coal with the average size of particles about 10-20 microns, and the existing machines for ultrafine coal production. This method increases substantially the velocity of ignition and combustion of pulverized coal flame. The changes of physical and chemical properties of coal after grinding were considered, and the processes of ignition, combustion of micronized coal, spaying and stabilization of flame combustion were analyzed in this paper. The problem of ultrafine coal ignition were considered also. 20 refs., 3 figs., 1 tab.

  20. Prospects for use of micronized coal in power industry

    Directory of Open Access Journals (Sweden)

    Burdukov Anatolii P.

    2002-01-01

    Full Text Available Heat-and-power engineering is the basis for industrial development of developed countries and the main energy fuel for plants is coal. The main directions in improvement of coal energy technologies are related with better ignition of powered fuel and with gas and mazut substitution with coal powder. This paper considered the prospects of energy coal enrichment and the method for production of ultrafine coal with the average size of particles about 10-20 microns, and the existing machines for ultrafine coal production. This method increases substantially the velocity of ignition and combustion of pulverized coal flame. The changes of physical and chemical properties of coal after grinding were considered, the processes of ignition, combustion of micronized coal, spaying and stabilization of flame combustion were analyzed in this paper. The problem of ultrafine coal ignition were considered also.

  1. 60 micron luminosity evolution of rich clusters of galaxies

    Energy Technology Data Exchange (ETDEWEB)

    Kelly, D.M.; Rieke, G.H. (Steward Observatory, Tucson, AZ (USA))

    1990-10-01

    The average 60-micron flux has been determined for a collection of optically selected galaxy clusters at redshifts ranging from 0.30 to 0.92. The result, 26 mJy per cluster, represents the faintest flux determination known of using the IRAS data base. The flux from this set of clusters has been compared to the 60-micron flux from a sample of nearby galaxy clusters. It is found that the far-infrared luminosity evolution in cluster galaxies can be no more than a factor of 1.7 from z = 0.4 to the present epoch. This upper limit is close to the evolution predicted for simple aging of the stellar populations. Additional processes such as mergers, cannibalism, or enhanced rates of starbursts appear to occur at a low enough level that they have little influence on the far-infrared emission from clusters over this redshift range. 38 refs.

  2. Smart CMOS image sensor for lightning detection and imaging

    OpenAIRE

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-01-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel fra...

  3. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6...

  4. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  5. Radiation-induced edge effects in deep submicron CMOS transistors

    CERN Document Server

    Faccio, F

    2005-01-01

    The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).

  6. Hardening of commercial CMOS PROMs with polysilicon fusible links

    Science.gov (United States)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  7. A CMOS biosensor array for measuring cellular exocytosis.

    OpenAIRE

    Ayers, S.

    2009-01-01

    Release of neurotransmitters and hormones from secretory vesicles plays a fundamental role in the function of the nervous system including neuronal communication. High-throughput testing of drugs modulating transmitter release is becoming an increasingly important area in the fields of cell biology, neurobiology, and neurology. In this thesis, I will describe the design and operation of a novel CMOS potentiostat circuit that is capable of measuring transient amperometric oxidation currents at...

  8. Performance Analysis of Visible Light Communication Using CMOS Sensors.

    Science.gov (United States)

    Do, Trong-Hop; Yoo, Myungsik

    2016-02-29

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis.

  9. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  10. Development program for 1.93-micron lasers

    Science.gov (United States)

    Longeway, P.; Zamerowski, T.; Martinelli, R.; Stolzenberger, R.; Digiuseppe, N.

    1988-01-01

    For the first time lasers operating at 1.93 microns were demonstrated. The lasers were fabricated by Vapor Phase Epitaxial (VPE) growth techniques currently used for the fabrication of high power lasers at 1.3 microns. The structure of these laser diodes consisted of compositionally graded, sulfur-doped InAsP, grown on an InP substrate; a constant-composition n+InAs(0.27)P(0.73) layer, which is the first cladding layer; an In(0.66)Ga(0.34)As layer, which is the active region, and a second InAs(0.27)P(0.73) layer. The devices were oxide-stripe DH lasers (gain-guided only). The best devices had 80 K lasing thresholds in the range of from 80 to 150 mA, and T sub o (below 220 K) in the range of 60 to 90 K. The highest observed temperature of oscillation was 15.5 C. The highest observed power output at 80 K was in the range of 3 to 5 mW. The calculated delta I/delta T was 4.4 A/K. As a part of the materials development, PIN homojunction detectors having the band edge near 1.93 were also fabricated. The best devices (100 micron diameter, mesa structure) exhibited room temperature dark currents in the range of from 20 to 50 nA and had QE at 1.93 microns in the range of 35 to 40 percent. In addition to the device results, the InGaAs-InAsP materials system was extensively investigated and low defect density layers can now be grown allowing for significant device performance improvement.

  11. micron-sized polymeric particles from cashew nut shell liquid

    African Journals Online (AJOL)

    Micron-sized polymeric particles from cashew nut shell liquid … 38 to 0.21 µm. When the concentration of. NaOH was increased further to 1.2 g/dm3 while keeping constant the values of the other variables, the extent of coagulation in the latex was found to have intensified; this gave rise to the increase in particle size to.

  12. Characterization of Micron-Scale Nanotublar Super Dielectric Materials

    Science.gov (United States)

    2015-09-01

    unit of electrical resistance) r  relative permittivity of a dielectric material   permittivity of free space (or vacuum) m micron (or...reliance on fossil fuels and overall energy consumption [14]. The Navy set an energy goal to improve energy efficiency and reduce afloat fuel ...transient demands, a so-called “rolling reserve” that continuously burns fuel at a minimum load waiting for planned or unexpected needs [15]. In an

  13. Polycrystalline Mercuric Iodide Films on CMOS Readout Arrays

    Science.gov (United States)

    Hartsough, Neal E.; Iwanczyk, Jan S.; Nygard, Einar; Malakhov, Nail; Barber, William C.; Gandhi, Thulasidharan

    2009-08-01

    We have created high-resolution x-ray imaging devices using polycrystalline mercuric iodide (HgI2) films grown directly onto CMOS readout chips using a thermal vapor transport process. Images from prototype 400 times 400 pixel HgI2-coated CMOS readout chips are presented, where the pixel grid is 30 mum times 30 mum. The devices exhibited sensitivity of 6.2 muC/Rcm2 with corresponding dark current of 2.7 nA/cm2, and a 80 mum FWHM planar image response to a 50 mum slit aperture. X-ray CT images demonstrate a point spread function sufficient to obtain a 50 mum spatial resolution in reconstructed CT images at a substantially reduced dose compared to phosphor-coated readouts. The use of CMOS technology allows for small pixels (30 mum), fast readout speeds (8 fps for a 3200 times 3200 pixel array), and future design flexibility due to the use of well-developed fabrication processes.

  14. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  15. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers.

    Science.gov (United States)

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d(33f), d(31) and d(33) of up to 2.9, -1.9 and 6.5 pm V(-1), respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

  16. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Chen Qu

    2017-09-01

    Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  17. CMOS IC design for wireless medical and health care

    CERN Document Server

    Wang, Zhihua; Chen, Hong

    2014-01-01

    This book provides readers with detailed explanation of the design principles of CMOS integrated circuits for wireless medical and health care, from the perspective of two successfully-commercialized applications. Design techniques for both the circuit block level and the system level are discussed, based on real design examples. CMOS IC design techniques for the entire signal chain of wireless medical and health care systems are covered, including biomedical signal acquisition, wireless transceivers, power management and SoC integration, with emphasis on ultra-low-power IC design techniques. • Discusses CMOS integrated circuit design for wireless medical and health care, based on two successfully-commercialized medical and health care applications; • Describes design techniques for the entire signal chain of wireless medical and health care systems; • Focuses on techniques for short-range wireless communication systems; • Emphasizes ultra-low-power IC design techniques; • Enables readers to tu...

  18. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors.

    Science.gov (United States)

    Qu, Chen; Bi, Du-Yan; Sui, Ping; Chao, Ai-Nong; Wang, Yun-Fei

    2017-09-22

    The CMOS (Complementary Metal-Oxide-Semiconductor) is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze), causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF) framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  19. CMOS integration of inkjet-printed graphene for humidity sensing

    Science.gov (United States)

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  20. Scanning SQUID susceptometers with sub-micron spatial resolution

    Energy Technology Data Exchange (ETDEWEB)

    Kirtley, John R., E-mail: jkirtley@stanford.edu; Rosenberg, Aaron J.; Palmstrom, Johanna C.; Holland, Connor M.; Moler, Kathryn A. [Department of Applied Physics, Stanford University, Stanford, California 94305-4045 (United States); Paulius, Lisa [Department of Physics, Western Michigan University, Kalamazoo, Michigan 49008-5252 (United States); Spanton, Eric M. [Department of Physics, Stanford University, Stanford, California 94305-4045 (United States); Schiessl, Daniel [Attocube Systems AG, Königinstraße 11A, 80539 Munich (Germany); Jermain, Colin L.; Gibbons, Jonathan [Department of Physics, Cornell University, Cornell, Ithaca, New York 14853 (United States); Fung, Y.-K.K.; Gibson, Gerald W. [IBM Research Division, T. J. Watson Research Center, Yorktown Heights, New York 10598 (United States); Huber, Martin E. [Department of Physics, University of Colorado Denver, Denver, Colorado 80217-3364 (United States); Ralph, Daniel C. [Department of Physics, Cornell University, Cornell, Ithaca, New York 14853 (United States); Kavli Institute at Cornell, Ithaca, New York 14853 (United States); Ketchen, Mark B. [OcteVue, Hadley, Massachusetts 01035 (United States)

    2016-09-15

    Superconducting QUantum Interference Device (SQUID) microscopy has excellent magnetic field sensitivity, but suffers from modest spatial resolution when compared with other scanning probes. This spatial resolution is determined by both the size of the field sensitive area and the spacing between this area and the sample surface. In this paper we describe scanning SQUID susceptometers that achieve sub-micron spatial resolution while retaining a white noise floor flux sensitivity of ≈2μΦ{sub 0}/Hz{sup 1/2}. This high spatial resolution is accomplished by deep sub-micron feature sizes, well shielded pickup loops fabricated using a planarized process, and a deep etch step that minimizes the spacing between the sample surface and the SQUID pickup loop. We describe the design, modeling, fabrication, and testing of these sensors. Although sub-micron spatial resolution has been achieved previously in scanning SQUID sensors, our sensors not only achieve high spatial resolution but also have integrated modulation coils for flux feedback, integrated field coils for susceptibility measurements, and batch processing. They are therefore a generally applicable tool for imaging sample magnetization, currents, and susceptibilities with higher spatial resolution than previous susceptometers.

  1. Soft tissue engineering with micronized-gingival connective tissues.

    Science.gov (United States)

    Noda, Sawako; Sumita, Yoshinori; Ohba, Seigo; Yamamoto, Hideyuki; Asahina, Izumi

    2018-01-01

    The free gingival graft (FGG) and connective tissue graft (CTG) are currently considered to be the gold standards for keratinized gingival tissue reconstruction and augmentation. However, these procedures have some disadvantages in harvesting large grafts, such as donor-site morbidity as well as insufficient gingival width and thickness at the recipient site post-treatment. To solve these problems, we focused on an alternative strategy using micronized tissue transplantation (micro-graft). In this study, we first investigated whether transplantation of micronized gingival connective tissues (MGCTs) promotes skin wound healing. MGCTs (≤100 µm) were obtained by mincing a small piece (8 mm 3 ) of porcine keratinized gingiva using the RIGENERA system. The MGCTs were then transplanted to a full skin defect (5 mm in diameter) on the dorsal surface of immunodeficient mice after seeding to an atelocollagen matrix. Transplantations of atelocollagen matrixes with and without micronized dermis were employed as experimental controls. The results indicated that MGCTs markedly promote the vascularization and epithelialization of the defect area 14 days after transplantation compared to the experimental controls. After 21 days, complete wound closure with low contraction was obtained only in the MGCT grafts. Tracking analysis of transplanted MGCTs revealed that some mesenchymal cells derived from MGCTs can survive during healing and may function to assist in wound healing. We propose here that micro-grafting with MGCTs represents an alternative strategy for keratinized tissue reconstruction that is characterized by low morbidity and ready availability. © 2017 Wiley Periodicals, Inc.

  2. Demonstration of an optical enhancement cavity with 10 micron wavelength

    Science.gov (United States)

    Sakaue, K.; Washio, M.; Endo, A.

    2015-05-01

    We have been developing a pulsed-laser optical enhancement cavity for laser-Compton scattering (LCS). LCS can produce high brightness X-ray through the collision between relativistic electrons generated from the accelerator and high power laser photons with a compact facility. In order to increase the number of collisions/sec, high repetition rate accelerator and laser are required. For the laser system, an optical enhancement cavity is the most powerful tool for LCS, thus we have been developing the cavity for storing 1 micron laser pulse. On the other hand, the resulting X-ray energy can be changed by the collision laser wavelength. If we have another optical cavity with different wavelength, the multicolor, quasi-monochromatic, high brightness and compact X-ray source can be realized. Therefore, we started to develop an optical cavity at 10 micron wavelength with CO2 laser. At this wavelength region, the absorption loss is dominant compared with scattering loss. Thus we carefully chose the optical mirrors for enhancement cavity. We demonstrated a more than 200 enhancement factor with 795 finesse optical cavity at 10 micron CO2 laser. Moreover, 2.3 kW storage in the optical cavity was successfully demonstrated. The design of optical cavity, first experimental results and future prospects will be presented at the conference.

  3. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  4. Self-calibrated humidity sensor in CMOS without post-processing.

    Science.gov (United States)

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  5. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    OpenAIRE

    Kazusuke Maenaka; Kohei Higuchi; Oleg Nizhnik

    2011-01-01

    A 1.1 µW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  6. Radiation hardness of CMOS monolithic active pixel sensors manufactured in a 0.18 μm CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Linnik, Benjamin [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    CMOS Monolithic Active Pixels Sensors (MAPS) are considered as the technology of choice for various vertex detectors in particle and heavy-ion physics including the STAR HFT, the upgrade of the ALICE ITS, the future ILC detectors and the CBM experiment at FAIR. To match the requirements of those detectors, their hardness to radiation is being improved, among others in a joined research activity of the Goethe University Frankfurt and the IPHC Strasbourg. It was assumed that combining an improved high resistivity (1-8 kΩcm) sensitive medium with the features of a 0.18 μm CMOS process, is suited to reach substantial improvements in terms of radiation hardness as compared to earlier sensor designs. This strategy was tested with a novel generation of sensor prototypes named MIMOSA-32 and MIMOSA-34. We show results on the radiation hardness of those sensors and discuss its impact on the design of future vertex detectors.

  7. Solar-Powered, Micron-Gap Thermophotovoltaics for MEO Applications Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposed innovation is an InGaAs-based, radiation-tolerant, micron-gap thermophotovoltaic (MTPV) technology. The use of a micron wide gap between the radiation...

  8. The design, simulation, and fabrication of a BiCMOS VLSI digitally programmable GIC filter

    OpenAIRE

    Milne, Paul R.

    2001-01-01

    This thesis used a previously-designed programmable GIC filter as a basis in which to incorporate a BiCMOS operational amplifier. An NPN bipolar transistor layout was designed and incorporated into an opamp layout, which was a modified version of a CMOS-only design. The BiCMOS opamp was simulated using Silvaco SmartSpice and showed considerable improvement over its CMOS equivalent. Additional improvements were made to the GIC filter to include a passgate with reduced resistance, and a correct...

  9. Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS Inverters on plastic.

    Science.gov (United States)

    Lee, Myeongwon; Jeon, Youngin; Moon, Taeho; Kim, Sangsig

    2011-04-26

    A route to the top-down fabrication of highly ordered and aligned silicon nanowire (SiNW) arrays with degenerately doped source/drain regions from a bulk Si wafer is presented. In this approach, freestanding n- and p-SiNWs with an inverted triangular cross section are obtained using conventional photolithography, crystal orientation dependent wet etching, size reduction oxidation, and ion implantation doping. Based on these n- and p-SiNWs transferred onto a plastic substrate, simple SiNW-based complementary metal-oxide-semiconductor (CMOS) inverters are constructed for the possible applications of these SiNW arrays in integrated circuits on plastic. The static voltage transfer characteristic of the SiNW-based CMOS inverter exhibits a voltage gain of ∼9 V/V and a transition of 0.32 V at an operating voltage of 1.5 V with a full output voltage swing between 0 V and V(DD), and its mechnical bendability indicates good fatigue properties for potential applications of flexible electronics. This novel top-down approach is fully compatible with the current state-of-the-art Si-based CMOS technologies and, therefore, offers greater flexibility in device design for both high-performance and low-power functionality.

  10. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    Science.gov (United States)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  11. Micron-scale lens array having diffracting structures

    Science.gov (United States)

    Goldberg, Kenneth A

    2013-10-29

    A novel micron-scale lens, a microlens, is engineered to concentrate light efficiently onto an area of interest, such as a small, light-sensitive detector element in an integrated electronic device. Existing microlens designs imitate the form of large-scale lenses and are less effective at small sizes. The microlenses described herein have been designed to accommodate diffraction effects, which dominate the behavior of light at small length scales. Thus a new class of light-concentrating optical elements with much higher relative performance has been created. Furthermore, the new designs are much easier to fabricate than previous designs.

  12. 8-9 and 14-15 Micron Two-Color 640x486 GaAs/AlGaAs Quantum Well Infrared Photodetector (QWIP) Focal Plane Array Camera

    Science.gov (United States)

    Gunapala, S. D.; Bandara, S. V.; Singh, A.; Liu, J. K.; Rafol, S. B.; Luong, E. M.; Mumolo, J. M.; Tran, N. Q.; Vincent, J. D.; Shott, C. A.

    2000-01-01

    An optimized long-wavelength two-color Quantum Well Infrared Photodetector (QWIP) device structure has been designed. This device structure was grown on a three inch semi-insulating GaAs substrate by molecular beam epitaxy (MBE). This wafer was processed into several 640x486 format monolithically integrated 8-9 and 14-15 micron two color (or dual wavelength) QWIP focal plane arrays (FPAs). These FPAs were then hybridized to 640x486 silicon CMOS readout multiplexers. A thinned (i.e., substrate removed) FPA hybrid was integrated into a liquid helium cooled dewar to perform electrical and optical characterization and to demonstrate simultaneous two-color imagery. The 8-9 micron detectors in the FPA have shown background limited performance (BLIP) at 70 K operating temperature, at 300 K background with f/2 cold stop. The 14-15 micron detectors of the FPA have reached BLIP at 40 K operating temperature at the same background conditions. In this presentation we discuss the performance of this long-wavelength dualband QWIP FPA in quantum efficiency, detectivity, noise equivalent temperature difference (NEAT), uniformity, and operability.

  13. Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

    Science.gov (United States)

    Balestri, G.; Batignani, G.; Beck, G.; Bernardelli, A.; Berra, A.; Bettarini, S.; Bevan, |A.; Bombelli, L.; Bosi, F.; Bosisio, L.; Casarosa, G.; Ceccanti, M.; Cenci, R.; Citterio, M.; Coelli, S.; Comotti, D.; Dalla Betta, G.-F.; Fabbri, L.; Fiorini, C.; Fontana, G.; Forti, F.; Gabrielli, A.; Gaioni, L.; Gannaway, F.; Giorgi, F.; Giorgi, M. A.; Lanceri, L.; Liberali, V.; Lietti, D.; Lusiani, A.; Mammini, P.; Manazza, A.; Manghisoni, M.; Monti, M.; Morris, J.; Morsani, F.; Nasri, B.; Neri, N.; Oberhof, B.; Palombo, F.; Pancheri, L.; Paoloni, E.; Pellegrini, G.; Perez, A.; Petragnani, G.; Prest, M.; Povoli, M.; Profeti, A.; Quartieri, E.; Rashevskaya, I.; Ratti, L.; Re, V.; Rizzo, G.; Sbarra, C.; Semprini-Cesari, N.; Soldani, A.; Stabile, A.; Stella, C.; Traversi, G.; Valentinetti, S.; Verzellesi, G.; Villa, M.; Vitale, L.; Walsh, J.; Wilson, F.; Zoccoli, A.; Zucca, S.

    2013-12-01

    Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

  14. Latest results of the R and D on CMOS MAPS for the Layer0 of the SuperB SVT

    Energy Technology Data Exchange (ETDEWEB)

    Balestri, G. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Batignani, G. [Università degli Studi di Pisa (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Beck, G. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Bernardelli, A. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Berra, A. [Università dell' Insubria, Como (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano Bicocca (Italy); Bettarini, S. [Università degli Studi di Pisa (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Bevan, A. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Bombelli, L. [Politecnico di Milano (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano (Italy); Bosi, F. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Bosisio, L. [Università degli Studi di Trieste (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Trieste (Italy); Casarosa, G., E-mail: giulia.casarosa@pi.infn.it [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Ceccanti, M. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Cenci, R. [University of Maryland (United States); Citterio, M.; Coelli, S. [Istituto Nazionale di Fisica Nucleare, Sezione di Milano (Italy); Comotti, D. [Università degli Studi di Bergamo (Italy); Dalla Betta, G.-F. [Università degli Studi di Trento (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Padova (Italy); Fabbri, L. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); and others

    2013-12-21

    Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R and D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

  15. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  16. Comparison of Total Dose Effects on Micropower Op-Amps: Bipolar and CMOS

    Science.gov (United States)

    Lee, C.; Johnston, A.

    1998-01-01

    This paper compares low-paper op-amps, OPA241 (bipolar) and OPA336 (CMOS), from Burr-Brown, MAX473 (bipolar) and MAX409 (CMOS), characterizing their total dose response with a single 2.7V power supply voltage.

  17. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  18. An Analytical Model for Spectral Peak Frequency Prediction of Substrate Noise in CMOS Substrates

    DEFF Research Database (Denmark)

    Shen, Ming; Mikkelsen, Jan H.

    2013-01-01

    This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform us...

  19. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Science.gov (United States)

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the `126...

  20. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... to solve the problem, namely freeze-drying and resist-assisted release. The fabrication results of cantilevers defined by laser and E-beam lithography are shown. Finally, an AFM based characterization setup is presented and the electrical characterization of a laser-defined cantilever fully integrated...

  1. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  2. A CMOS readout system for very large detector capacitances

    Science.gov (United States)

    Schoeneberg, U.; Hosticka, B. J.; Fent, J.; Oberlack, H.; Zimmer, G.

    1990-03-01

    In this contribution we present readout electronics for a liquid-argon calorimeter. It has been designed and optimized for operation at cryogenic temperatures and it is integrated in an n-well 2 μm CMOS technology. The chip contains 16 analog channels with switched-capacitor circuits for charge collection, storage, and amplification, and averaging and correlated double sampling circuits for noise reduction. Further components include a trigger generator, an analog multiplexer, digital control circuits for analog switching, and 50 ω cable drivers.

  3. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  4. Performance Analysis of Visible Light Communication Using CMOS Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hop Do

    2016-02-01

    Full Text Available This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR, is formulated. Finally, a simulation is conducted to verify the analysis.

  5. Solar Battery Charger in CMOS 0.25 um Technology

    OpenAIRE

    Tao Wang; Chang-Ching Huang; Tian-Jen Wang

    2014-01-01

    A solar cell powered Li-ion battery charger in CMOS 0.25um is proposed. The solar battery charger consists of a DC/DC boost converter and a battery charger. The voltage generated by a solar cell is up converted from 0.65V to 1.8V, which is used as the VDD of the battery charger.  In this way, the solar battery charger automatically converts solar energy to electricity and stores it directly to a Li-ion rechargeable battery. In this system, a super capacitor is needed as a charge buffer betwee...

  6. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Directory of Open Access Journals (Sweden)

    John-Ojur Dennis

    2015-07-01

    Full Text Available This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2 nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that

  7. Displacement Damage Effects in Pinned Photodiode CMOS Image Sensors

    OpenAIRE

    Virmontois, Cédric; Goiffon, Vincent; Corbière, Franck; Magnan, Pierre; Girard, Sylvain; Bardoux, Alain

    2012-01-01

    This paper investigates the effects of displacement damage in Pinned Photodiode (PPD) CMOS Image Sensors (CIS) using proton and neutron irradiations. The DDD ranges from 12 TeV/g to ${1.2 times 10^{6}}$ TeV/g. Particle fluence up to $5 times 10^{14}$ n.cm $^{-2}$ is investigated to observe electro-optic degradation in harsh environments. The dark current is also investigated and it would appear that it is possible to use the dark current spectroscopy in PPD CIS. The dark current random telegr...

  8. CMOS RF circuit design for reliability and variability

    CERN Document Server

    Yuan, Jiann-Shiun

    2016-01-01

    The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

  9. On drift fields in CMOS monolithic active pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Deveaux, Michael [Goethe-Universitaet, Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2016-07-01

    CMOS Monolithic Active Pixel Sensors (MAPS) combine an excellent spatial resolution of few μm with a very low material budget of 0.05% X{sub 0}. To extend their radiation tolerance to the level needed for future experiments like e.g. CBM, it is regularly considered to deplete their active volume. We discuss the limits of this strategy accounting for the specific features of the sensing elements of MAPS. Moreover, we introduce an alternative approach to generate the drift fields needed to provoke a faster charge collection by means of doping gradients.

  10. An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

    Science.gov (United States)

    Torres, Erick Omar

    Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz

  11. Micron: an Actively Stabilized Handheld Tool for Microsurgery.

    Science.gov (United States)

    Maclachlan, Robert A; Becker, Brian C; Tabarés, Jaime Cuevas; Podnar, Gregg W; Lobes, Louis A; Riviere, Cameron N

    2012-02-01

    We describe the design and performance of a hand-held actively stabilized tool to increase accuracy in micro-surgery or other precision manipulation. It removes involuntary motion such as tremor by actuating the tip to counteract the effect of the undesired handle motion. The key components are a three-degree-of-freedom piezoelectric manipulator that has 400 μm range of motion, 1 N force capability, and bandwidth over 100 Hz, and an optical position measurement subsystem that acquires the tool pose with 4 μm resolution at 2000 samples/s. A control system using these components attenuates hand motion by at least 15 dB (a fivefold reduction). By considering the effect of the frequency response of Micron on the human visual feedback loop, we have developed a filter that reduces unintentional motion, yet preserves intuitive eye-hand coordination. We evaluated the effectiveness of Micron by measuring the accuracy of the human/machine system in three simple manipulation tasks. Handheld testing by three eye surgeons and three non-surgeons showed a reduction in position error of between 32% and 52%, depending on the error metric.

  12. Griseofulvin micronization and dissolution rate improvement by supercritical assisted atomization.

    Science.gov (United States)

    Reverchon, E; Della Porta, G; Spada, A; Antonacci, A

    2004-11-01

    Supercritical assisted atomization (SAA) was used to micronize griseofulvin (GF), selected as a model compound, to verify the performance of this innovative process. SAA is based on the solubilization of supercritical carbon dioxide in a liquid solution containing the drug. The ternary mixture is then sprayed through a nozzle and microparticles are formed as a consequence of the enhanced atomization. Precipitation temperature and drug concentration in the liquid solution were studied to evaluate their influence on morphology and size of precipitated particles. A good particle size control was obtained and GF spherical particles with mean diameters ranging from 0.5 to 2.5 microm were produced with a narrow particle size distribution. Processed GF was characterized by high-performance liquid chromatography-UV/vis, headspace-gas chromatography-flame ionization detection, differential scanning calorimetry, BET and X-ray analyses. No drug degradation was observed and a solvent residue (acetone) less than 800 ppm was measured. GF microparticles showed good stability and surface areas ranging from about 4 to 6 m(2) g(-1); moreover, the micronized drug retained the crystalline habit. GF capsules were formulated with starch and used to compare the dissolution rate of SAA-processed and conventional jet-milled drug. A faster dissolution and a better reproducibility of the dissolution profile were observed for SAA-processed GF.

  13. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  14. CMOS digital intra-oral sensor for x-ray radiography

    Science.gov (United States)

    Liu, Xinqiao; Byczko, Andrew; Choi, Marcus; Chung, Lap; Do, Hung; Fowler, Boyd; Ispasoiu, Radu; Joshi, Kumar; Miller, Todd; Nagy, Alex; Reaves, David; Rodricks, Brian; Teeter, Doug; Wang, George; Xiao, Feng

    2011-03-01

    In this paper, we present a CMOS digital intra-oral sensor for x-ray radiography. The sensor system consists of a custom CMOS imager, custom scintillator/fiber optics plate, camera timing and digital control electronics, and direct USB communication. The CMOS imager contains 1700 x 1346 pixels. The pixel size is 19.5um x 19.5um. The imager was fabricated with a 0.18um CMOS imaging process. The sensor and CMOS imager design features chamfered corners for patient comfort. All camera functions were integrated within the sensor housing and a standard USB cable was used to directly connect the intra-oral sensor to the host computer. The sensor demonstrated wide dynamic range from 5uGy to 1300uGy and high image quality with a SNR of greater than 160 at 400uGy dose. The sensor has a spatial resolution more than 20 lp/mm.

  15. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  16. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  17. The 2-micron plasmid as a nonselectable, stable, high copy number yeast vector

    Science.gov (United States)

    Ludwig, D. L.; Bruschi, C. V.

    1991-01-01

    The endogenous 2-microns plasmid of Saccharomyces cerevisiae has been used extensively for the construction of yeast cloning and expression plasmids because it is a native yeast plasmid that is able to be maintained stably in cells at high copy number. Almost invariably, these plasmid constructs, containing some or all 2-microns sequences, exhibit copy number levels lower than 2-microns and are maintained stably only under selective conditions. We were interested in determining if there was a means by which 2-microns could be utilized for vector construction, without forfeiting either copy number or nonselective stability. We identified sites in the 2-microns plasmid that could be used for the insertion of genetic sequences without disrupting 2-microns coding elements and then assessed subsequent plasmid constructs for stability and copy number in vivo. We demonstrate the utility of a previously described 2-microns recombination chimera, pBH-2L, for the manipulation and transformation of 2-microns as a pure yeast plasmid vector. We show that the HpaI site near the STB element in the 2-microns plasmid can be utilized to clone yeast DNA of at least 3.9 kb with no loss of plasmid stability. Additionally, the copy number of these constructs is as high as levels reported for the endogenous 2-microns.

  18. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  19. Development of a multi-sensor CMOS ASIC

    Science.gov (United States)

    van der Merwe, D. G.

    2016-02-01

    A multi-sensor application specific integrated circuit has been developed with a number of sensors: capacitive, inductive, magnetic, ambient light, infrared and acceleration. The capacitive sensing is implemented using a unique, patented, charge transfer technique allowing the measurement of very small capacitances while at the same time eliminating the effects of unwanted parasitic capacitances in the measurement circuit. For cost effective implementation the charge transfer measurement circuit has been has been modified, augmented and expanded to not only measure capacitance but also to act as the measurement circuit for all the sensors. Enabling the multi-sensor chip to measure acceleration on a range of MEMs accelerometer chips including a single axis accelerometer, a dual axis xy accelerometer and a z-axis accelerometer, innovative and patent pending techniques have been developed and implemented on standard CMOS. The CMOS ASIC and a MEMs chip will be double bonded in a plastic package offering multi-sensor capability in a small low cost package.

  20. Single donor electronics and quantum functionalities with advanced CMOS technology.

    Science.gov (United States)

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-16

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  1. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

    Science.gov (United States)

    Ghodsevali, Elnaz; Morneau-Gamache, Samuel; Mathault, Jessy; Landari, Hamza; Boisselier, Élodie; Boukadoum, Mounir; Gosselin, Benoit; Miled, Amine

    2017-01-01

    A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µVrms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter. PMID:28394289

  2. Macromolecular crystallography with a large format CMOS detector

    Energy Technology Data Exchange (ETDEWEB)

    Nix, Jay C., E-mail: jcnix@lbl.gov [Molecular Biology Consortium 12003 S. Pulaski Rd. #166 Alsip, IL 60803 U.S.A (United States)

    2016-07-27

    Recent advances in CMOS technology have allowed the production of large surface area detectors suitable for macromolecular crystallography experiments [1]. The Molecular Biology Consortium (MBC) Beamline 4.2.2 at the Advanced Light Source in Berkeley, CA, has installed a 2952 x 2820 mm RDI CMOS-8M detector with funds from NIH grant S10OD012073. The detector has a 20nsec dead pixel time and performs well with shutterless data collection strategies. The sensor obtains sharp point response and minimal optical distortion by use of a thin fiber-optic plate between the phosphor and sensor module. Shutterless data collections produce high-quality redundant datasets that can be obtained in minutes. The fine-sliced data are suitable for processing in standard crystallographic software packages (XDS, HKL2000, D*TREK, MOSFLM). Faster collection times relative to the previous CCD detector have resulted in a record number of datasets collected in a calendar year and de novo phasing experiments have resulted in publications in both Science and Nature [2,3]. The faster collections are due to a combination of the decreased overhead requirements of shutterless collections combined with exposure times that have decreased by over a factor of 2 for images with comparable signal to noise of the NOIR-1 detector. The overall increased productivity has allowed the development of new beamline capabilities and data collection strategies.

  3. A Review on Energy Efficient CMOS Digital Logic

    Directory of Open Access Journals (Sweden)

    B. L. Dokic

    2013-12-01

    Full Text Available Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt and power supply voltage (Vdd on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL, complementary pass logic (CPL, push-pull pass logic (PPL and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

  4. Backside illuminated CMOS-TDI line scanner for space applications

    Science.gov (United States)

    Cohen, O.; Ben-Ari, N.; Nevo, I.; Shiloah, N.; Zohar, G.; Kahanov, E.; Brumer, M.; Gershon, G.; Ofer, O.

    2017-09-01

    A new multi-spectral line scanner CMOS image sensor is reported. The backside illuminated (BSI) image sensor was designed for continuous scanning Low Earth Orbit (LEO) space applications including A custom high quality CMOS Active Pixels, Time Delayed Integration (TDI) mechanism that increases the SNR, 2-phase exposure mechanism that increases the dynamic Modulation Transfer Function (MTF), very low power internal Analog to Digital Converters (ADC) with resolution of 12 bit per pixel and on chip controller. The sensor has 4 independent arrays of pixels where each array is arranged in 2600 TDI columns with controllable TDI depth from 8 up to 64 TDI levels. A multispectral optical filter with specific spectral response per array is assembled at the package level. In this paper we briefly describe the sensor design and present some electrical and electro-optical recent measurements of the first prototypes including high Quantum Efficiency (QE), high MTF, wide range selectable Full Well Capacity (FWC), excellent linearity of approximately 1.3% in a signal range of 5-85% and approximately 1.75% in a signal range of 2-95% out of the signal span, readout noise of approximately 95 electrons with 64 TDI levels, negligible dark current and power consumption of less than 1.5W total for 4 bands sensor at all operation conditions .

  5. A CMOS smart temperature and humidity sensor with combined readout.

    Science.gov (United States)

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  6. A CMOS variable gain LNA for UWB receivers

    Science.gov (United States)

    Feihua, Chen; Lingyun, Li; Xinzhong, Duo; Tong, Tian; Xiaowei, Sun

    2011-02-01

    A CMOS variable gain low noise amplifier (LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13-μm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S(1,1) less than -9 dB and S(2,2) less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point (IIP3) is -2 dBm.

  7. Performance of Very Small Robotic Fish Equipped with CMOS Camera

    Directory of Open Access Journals (Sweden)

    Yang Zhao

    2015-10-01

    Full Text Available Underwater robots are often used to investigate marine animals. Ideally, such robots should be in the shape of fish so that they can easily go unnoticed by aquatic animals. In addition, lacking a screw propeller, a robotic fish would be less likely to become entangled in algae and other plants. However, although such robots have been developed, their swimming speed is significantly lower than that of real fish. Since to carry out a survey of actual fish a robotic fish would be required to follow them, it is necessary to improve the performance of the propulsion system. In the present study, a small robotic fish (SAPPA was manufactured and its propulsive performance was evaluated. SAPPA was developed to swim in bodies of freshwater such as rivers, and was equipped with a small CMOS camera with a wide-angle lens in order to photograph live fish. The maximum swimming speed of the robot was determined to be 111 mm/s, and its turning radius was 125 mm. Its power consumption was as low as 1.82 W. During trials, SAPPA succeeded in recognizing a goldfish and capturing an image of it using its CMOS camera.

  8. CMOS tunable-wavelength multi-color photogate sensor.

    Science.gov (United States)

    Ho, Derek; Noor, M Omair; Krull, Ulrich J; Gulak, Glenn; Genov, Roman

    2013-12-01

    A CMOS tunable-wavelength multi-color photogate (CPG) sensor is presented. Sensing of a small set of well-separated wavelengths (e.g., > 50 nm apart) is achieved by tuning the spectral response of the device with a bias voltage. The CPG employs the polysilicon gate as an optical filter, which eliminates the need for an external color filter. A prototype has been fabricated in a standard 0.35 μm digital CMOS technology and demonstrates intensity measurements of blue (450 nm), green (520 nm), and red (620 nm) illumination with peak signal-to-noise ratios (SNRs) of 34.7 dB , 29.2 dB, and 34.8 dB, respectively. The prototype is applied to fluorescence detection of green-emitting quantum dots (gQDs) and red-emitting quantum dots (rQDs). It spectrally differentiates among multiple emission bands, effectively implementing on-chip emission filtering. The prototype demonstrates single-color measurements of gQD and rQD concentrations to a detection limit of 24 nM, and multi-color measurements of solutions containing both colors of QDs to a detection limit of 90 nM and 120 nM of gQD and rQD, respectively.

  9. A Low-Cost CMOS Programmable Temperature Switch

    Directory of Open Access Journals (Sweden)

    Nanjian Wu

    2008-05-01

    Full Text Available A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45-120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  10. Si light-emitting device in integrated photonic CMOS ICs

    Science.gov (United States)

    Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

    2017-07-01

    The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

  11. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

    Directory of Open Access Journals (Sweden)

    Elnaz Ghodsevali

    2017-04-01

    Full Text Available A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µV rms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter.

  12. Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

    Science.gov (United States)

    Yang, Jong-Ryul; Han, Seong-Tae; Baek, Donghyun

    2017-09-09

    We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

  13. Deciphering sub-micron ice particles on Enceladus surface

    Science.gov (United States)

    Scipioni, F.; Schenk, P.; Tosi, F.; D'Aversa, E.; Clark, R.; Combe, J.-Ph.; Ore, C. M. Dalle

    2017-07-01

    The surface of Saturn's moon Enceladus is composed primarily by pure water ice. The Cassini spacecraft has observed present-day geologic activity at the moon's South Polar Region, related with the formation and feeding of Saturn's E-ring. Plumes of micron-sized particles, composed of water ice and other non-ice contaminants (e.g., CO2, NH3, CH4), erupt from four terrain's fractures named Tiger Stripes. Some of this material falls back on Enceladus' surface to form deposits that extend to the North at ∼40°W and ∼220°W, with the highest concentration found at the South Pole. In this work we analyzed VIMS-IR data to identify plumes deposits across Enceladus' surface through the variation in band depth of the main water ice spectral features. To characterize the global variation of water ice band depths across Enceladus, the entire surface was sampled with an angular resolution of 1° in both latitude and longitude, and for each angular bin we averaged the value of all spectral indices as retrieved by VIMS. The position of the plumes' deposits predicted by theoretical models display a good match with water ice band depths' maps on the trailing hemisphere, whereas they diverge significantly on the leading side. Space weathering processes acting on Enceladus' surface ionize and break up water ice molecules, resulting in the formation of particles smaller than one micron. We also mapped the spectral indices for sub-micron particles and we compared the results with the plumes deposits models. Again, a satisfactory match is observed on the trailing hemisphere only. Finally, we investigated the variation of the depth of the water ice absorption bands as a function of the phase angle. In the visible range, some terrains surrounding the Tiger Stripes show a decrease in albedo when the phase angle is smaller than 10°. This unusual effect cannot be confirmed by near infrared data, since observations with a phase angle lower than 10° are not available. For phase angle

  14. Discovering sub-micron ice particles across Dione' surface

    Science.gov (United States)

    Scipioni, Francesca; Schenk, Pual; Tosi, Federico; Clark, Roger; Dalle Ore, Cristina; Combe, Jean-Philippe

    2015-11-01

    Water ice is the most abundant component of Saturn’s mid-sized moons. However, these moons show an albedo asymmetry - their leading sides are bright while their trailing side exhibits dark terrains. Such differences arise from two surface alteration processes: (i) the bombardment of charged particles from the interplanetary medium and driven by Saturn’s magnetosphere on the trailing side, and (ii) the impact of E-ring water ice particles on the satellites’ leading side. As a result, the trailing hemisphere appears to be darker than the leading side. This effect is particularly evident on Dione's surface. A consequence of these surface alteration processes is the formation or the implantation of sub-micron sized ice particles.The presence of such particles influences and modifies the surfaces' spectrum because of Rayleigh scattering by the particles. In the near infrared range of the spectrum, the main sub-micron ice grains spectral indicators are: (i) asymmetry and (ii) long ward minimum shift of the absorption band at 2.02 μm (iii) a decrease in the ratio between the band depths at 1.50 and 2.02 μm (iv) a decrease in the height of the spectral peak at 2.6 μm (v) the suppression of the Fresnel reflection peak at 3.1 μm and (vi) the decrease of the reflection peak at 5 μm relative to those at 3.6 μm.We present results from our ongoing work mapping the variation of sub-micron ice grains spectral indicators across Dione' surface using Cassini-VIMS cubes acquired in the IR range (0.8-5.1 μm). To characterize the global variations of spectral indicators across Dione' surface, we divided it into a 1°x1° grid and then averaged the band depths and peak values inside each square cell.We will investigate if there exist a correspondence with water ice abundance variations by producing water ice' absorption band depths at 1.25, 1.52 and 2.02 μm, and with surface morphology by comparing the results with ISS color maps in the ultraviolet, visible and infrared

  15. Micron size superconducting quantum interference devices of lead (Pb)

    Science.gov (United States)

    Paul, Sagar; Biswas, Sourav; Gupta, Anjan K.

    2017-02-01

    Micron size superconducting quantum interference devices (μ-SQUID) of lead (Pb), for probing nano-magnetism, were fabricated and characterized. In order to get continuous Pb films with small grain size, Pb was thermally evaporated on a liquid nitrogen cooled Si substrate. Pb was sandwiched between two thin Cr layers for improved adhesion and protection. The SQUID pattern was made by e-beam lithography with Pb lift-off after deposition. The current-voltage characteristics of these devices show a critical current, which exhibits the expected SQUID oscillations with magnetic field, and two re-trapping currents. As a result these devices have hysteresis at low temperatures, which disappears just below the critical temperature.

  16. Shock-wave micron-size diamond synthesis from fullerenes

    Energy Technology Data Exchange (ETDEWEB)

    Epanchintsev, O.G.; Zubchenko, A.S.; Kobelev, N.N. [Federal Scientific Center, Moscow (Russian Federation)] [and others

    1995-12-31

    Shock-wave synthesis of micron-size diamond is performed from fullerenes C{sub 60} -- C {sub 150} powders using the explosive compaction technique with plane shock-wave loading at different pressures in the range of 24-40 GPa. The compacts of different initial compositions consisted of diamond, fcc fullerite C{sub 60}, graphite and amorphous carbon. The most coarse diamond grains sized up to 6 {mu}n were formed at the shock pressure of 24 and 40 GPa in the compacts of initial powder mixture copper-5 mass.% fullerite and at shock pressure of 40 GPa in the compact of initial powder mixture copper - 10 mass.% fullerite. Shock-wave synthesis of diamond is performed without forming intermediate diamond-like phases, such as n-diamond and lonsdaleite (hexagonal diamond) in the final products.

  17. Mars Atmospheric Characterization Using Advanced 2-Micron Orbiting Lidar

    Science.gov (United States)

    Singh, U.; Engelund, W.; Refaat, T.; Kavaya, M.; Yu, J.; Petros, M.

    2015-01-01

    Mars atmospheric characterization is critical for exploring the planet. Future Mars missions require landing massive payloads to the surface with high accuracy. The accuracy of entry, descent and landing (EDL) of a payload is a major technical challenge for future Mars missions. Mars EDL depends on atmospheric conditions such as density, wind and dust as well as surface topography. A Mars orbiting 2-micron lidar system is presented in this paper. This advanced lidar is capable of measuring atmospheric pressure and temperature profiles using the most abundant atmospheric carbon dioxide (CO2) on Mars. In addition Martian winds and surface altimetry can be mapped, independent of background radiation or geographical location. This orbiting lidar is a valuable tool for developing EDL models for future Mars missions.

  18. Two Micron Laser Technology Advancements at NASA Langley Research Center

    Science.gov (United States)

    Singh, Upendra N.

    2010-01-01

    An Independent Laser Review Panel set up to examine NASA s space-based lidar missions and the technology readiness of lasers appropriate for space-based lidars indicated a critical need for an integrated research and development strategy to move laser transmitter technology from low technical readiness levels to the higher levels required for space missions. Based on the review, a multiyear Laser Risk Reduction Program (LRRP) was initiated by NASA in 2002 to develop technologies that ensure the successful development of the broad range of lidar missions envisioned by NASA. This presentation will provide an overview of the development of pulsed 2-micron solid-state laser technologies at NASA Langley Research Center for enabling space-based measurement of wind and carbon dioxide.

  19. Short range investigation of sub-micron zirconia particles

    Energy Technology Data Exchange (ETDEWEB)

    Caracoche, M C; Martinez, J A [Departamento de Fisica, IFLP, Facultad de Ciencias Exactas, CICPBA, Universidad Nacional de La Plata (Argentina); Rivas, P C [IFLP-CONICET, Facultad de Ciencias Agrarias y Forestales, Universidad Nacional de La Plata (Argentina); Bondioli, F; Cannillo, V [Dipartimento di Ingegniria dei Materiali e dell' Ambiente, Facolta di Ingegneria, Universita di Modena e Reggio Emilia (Italy); Ferrari, A M, E-mail: cristina@fisica.unlp.edu.a [Dipartimento di Scienza a Metodi dell' Ingegneria, Universita di Modena e Reggio Emilia (Italy)

    2009-05-01

    The Perturbed Angular Correlations technique was used to determine the configurations around Zirconium ions and their thermal behavior in non-aggregated sub-micron zirconia spherical particles. Three residues containing- Zr surroundings were determined for the non-crystalline starting particles, which were identified under the assumption of a certain chemical reactions sequence during synthesis. While the one made up mainly by hydroxyl groups was common to both samples, the two involving mainly organic residues were particle size dependent. Upon crystallization, both samples stabilized in the t'- and t- tetragonal forms and the Xc-cubic form but their amounts and temperatures of appearance were different. On heating, the structure of the smaller particles became gradually monoclinic achieving total degradation upon the subsequent cooling to RT.

  20. Predicting fracture in micron-scale polycrystalline silicon MEMS structures.

    Energy Technology Data Exchange (ETDEWEB)

    Hazra, Siddharth S. (Carnegie Mellon University, Pittsburgh, PA); de Boer, Maarten Pieter (Carnegie Mellon University, Pittsburgh, PA); Boyce, Brad Lee; Ohlhausen, James Anthony; Foulk, James W., III; Reedy, Earl David, Jr.

    2010-09-01

    Designing reliable MEMS structures presents numerous challenges. Polycrystalline silicon fractures in a brittle manner with considerable variability in measured strength. Furthermore, it is not clear how to use a measured tensile strength distribution to predict the strength of a complex MEMS structure. To address such issues, two recently developed high throughput MEMS tensile test techniques have been used to measure strength distribution tails. The measured tensile strength distributions enable the definition of a threshold strength as well as an inferred maximum flaw size. The nature of strength-controlling flaws has been identified and sources of the observed variation in strength investigated. A double edge-notched specimen geometry was also tested to study the effect of a severe, micron-scale stress concentration on the measured strength distribution. Strength-based, Weibull-based, and fracture mechanics-based failure analyses were performed and compared with the experimental results.

  1. Tunneling of micron-sized droplets through soap films.

    Science.gov (United States)

    Kim, Ildoo; Wu, X L

    2010-08-01

    When a micron-sized water droplet impacts on a freely suspended soap film with speed v(i), there exists a critical impact velocity of penetration v(C). Droplets with v(i)film after impacts, whereas droplets with v(i)>v(C) tunnel through it. In all cases, the film remains intact despite the fact that the droplet radius (R_{0}=26 μm) is much greater than the film thickness (0film is required for penetration. Quantitatively, we found that this deformation energy corresponds to the creation of ∼14 times of the cross-sectional area of the droplet (14πR(0)(2)) or a critical Weber number We(C)}(≡2ρ(w) v(C0)(2) R(0)/σ)≃44 , where ρ(w) and σ are, respectively, the density and the surface tension of water.

  2. Dynamical Nuclear Magnetic Resonance Imaging of Micron-scale Liquids

    Science.gov (United States)

    Sixta, Aimee; Choate, Alexandra; Maeker, Jake; Bogat, Sophia; Tennant, Daniel; Mozaffari, Shirin; Markert, John

    We report our efforts in the development of Nuclear Magnetic Resonance Force Microscopy (NMRFM) for dynamical imaging of liquid media at the micron scale. Our probe contains microfluidic samples sealed in thin-walled (µm) quartz tubes, with a micro-oscillator sensor nearby in vacuum to maintain its high mechanical resonance quality factor. Using 10 µm spherical permalloy magnets at the oscillator tips, a 3D T1-resolved image of spin density can be obtained by reconstruction from our magnetostatics-modelled resonance slices; as part of this effort, we are exploring single-shot T1 measurements for faster dynamical imaging. We aim to further enhance imaging by using a 2 ω technique to eliminate artifact signals during the cyclic inversion of nuclear spins. The ultimate intent of these efforts is to perform magnetic resonance imaging of individual biological cells.

  3. EUV mask reflectivity measurements with micron-scale spatial resolution

    Energy Technology Data Exchange (ETDEWEB)

    Goldberg, Kenneth A.; Rekawa, S.B.; Kemp, C.D.; Barty, A.; Anderson, E.H.; Kearney, Patrick; Han, Hakseung

    2008-05-26

    The effort to produce defect-free mask blanks for EUV lithography relies on increasing the detection sensitivity of advanced mask inspection tools, operating at several wavelengths. We describe the unique measurement capabilities of a prototype actinic (EUV wavelength) microscope that is capable of detecting small defects and reflectivity changes that occur on the scale of microns to nanometers. Types of defects: (a) Buried Substrate Defects: particles & pits (causes amplitude and/or phase variations); (b) Surface Contamination (reduces reflectivity and (possibly) contrast); (c) Damage from Inspection and Use (reduces the reflectivity of the multilayer coating). This paper presents an overview of several topics where scanning actinic inspection makes a unique contribution to EUVL research. We describe the role of actinic scanning inspection in four cases: defect repair studies; observations of laser damage; after scanning electron microscopy; and native and programmed defects.

  4. Acoustically enhanced combustion of micronized coal water slurry fuel

    Energy Technology Data Exchange (ETDEWEB)

    Koopmann, G. M.; Scaroni, A. W.; Yavuzkurt, S.; Reethof, G.; Ramachandran, P.; Ha, M. Y.

    1989-05-01

    A multi-faceted investigation has been carried out to demonstrate analytically and experimentally, that a high intensity acoustic field can be substantially enhance the convective transfer processes occurring during MCWSF (micronized coal water slurry fuel) combustion. The initial stage of the investigation dealt with elucidating the transient as well as time-averaged efforts of high intensity acoustic fields on the heat and mass transfer between a single spherical particle and its environment. A two-dimensional unsteady computer code was developed, which employs the unsteady conservation of mass, momentum, and energy equations for laminar flow in spherical coordinates. One objective of the present project was the modeling of MCWSF combustion in a laboratory scale combustor with and without the application of a sonic field. The influence of various operating parameters (sound frequency and level, etc.) on sonic enhancement could thus be studied. The combustion of pulverized coal (PC) was also modeled for the sake of comparison. The first of the two coal combustion experiments was performed using a flat flame methane-air burner. Micronized coal was injected in the same direction as, and burned together with the methane. The final investigation was carried out in a 300,000 Btu/h sonic combustor. For the runs conducted, SPLs of 156 dB and 145 dB, respectively, were measured below the fuel injection point and before the exit to the combustor. Frequency was held at 1400 Hz. Finally, an attempt was made to model the runs performed in the down-fired unit, using the PCGC-2 code. 61 refs., 60 figs., 8 tabs.

  5. Venus - The 17- to 38-micron spectrum. [atmospheric thermal emission spectrum

    Science.gov (United States)

    Reed, R. A.; Forrest, W. J.; Houck, J. R.; Pollack, J. B.

    1978-01-01

    A far-IR emission spectrum of Venus covering the wavelength range from 17 to 38 microns is examined which was obtained on five nights at an altitude of 14 km with the 30-cm telescope of the NASA Lear Jet. The spectrum is found to be characterized by an overall continuum level with noticeable absorption shortward of 20 microns and longward of 30 microns as compared with a 245-K blackbody. The continuum level is taken as implying a continuous source of opacity in the Venusian atmosphere over the entire range from 17 to 38 microns with increased opacity shortward of 20 microns and longward of 30 microns. It is shown that a haze of sulfuric acid droplets can provide the necessary opacity and explain the observed depressions. A pressure level of roughly 200 mb is deduced for this spectrum.

  6. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Science.gov (United States)

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

  7. The dual-channel ultraviolet/low light CMOS camera using image fusion technique

    Science.gov (United States)

    Qian, Yunsheng; Zhou, Xiaoyu; Kong, Xiangyu; Wu, Yujing; Tang, Xiaodong; Zhang, Yijun

    2017-09-01

    Ultraviolet detection technology, as immediate area of research focus, has been adopted in the fields of fingerprint identification, corona detection and exhaust plume detection. Low-light CMOS, which can work in even 10-3lux, is used in visible light channel. The prominent advantage of the dual-channel Ultraviolet/Low-light CMOS camera is the fusion of UV and wide dynamic range visible light information, which can enrich image details and help observers locate the UV targets in the complicated background around the clock rapidly. The paper studied on the component structure of UV ICMOS, imaging driving, the Ultraviolet/Low-light images fusion algorithm and the photon counting algorithm. The one-inch and wide dynamic range CMOS chip with the coupling optical fiber panel are coupled to the UV image intensifier. In consideration of the ultraviolet detection demand, the driving circuit of the CMOS chips is designed and the corresponding program based on Verilog language is written. After analysis and comparison of the characteristics of UV image and Low-light CMOS image, the improved Laplace pyramid fusion algorithm is applied. UV image and Low-light CMOS image are multiscale decompose, and the features in different frequency layer are chosen from either UV image or Low-light CMOS image. The connected components labeling way is utilized for the UV detection and imaging. At last, the detection experiments of the ultraviolet signal are carried out, and the results are given and analyzed.

  8. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

    2016-09-21

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  9. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Directory of Open Access Journals (Sweden)

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  10. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

    Directory of Open Access Journals (Sweden)

    Eloi Marigó

    2015-07-01

    Full Text Available A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology.

  11. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction.

    Science.gov (United States)

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-07-14

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology.

  12. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

    Science.gov (United States)

    Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

    2012-01-11

    Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

  13. Evaluation of circuit performance of ultra-thin-body SOI CMOS

    Science.gov (United States)

    Pacha, Christian; Schmal, Artur; Schulz, Thomas; Göttsche, Ralf; Steinhögl, Werner

    2003-07-01

    Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm [1]. In this paper we analyze the impact of this emerging CMOS device concept on the performance of a representative selection of various digital CMOS circuits under different load conditions for typical ASIC/SOC applications. For compact modeling a physics-based fully depleted SOI model is used [2] and combined with a technology scenario assuming an undoped Si-body, elevated source-drain regions, and midgap gate workfunction.

  14. CMOS capacitive biosensors for highly sensitive biosensing applications.

    Science.gov (United States)

    Chang, An-Yu; Lu, Michael S-C

    2013-01-01

    Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

  15. A photonics design tool for advanced CMOS nodes

    CERN Document Server

    Alloatti, Luca; Stojanovic, Vladimir; Popovic, Milos; Ram, Rajeev Jagga

    2015-01-01

    Recently, we have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigor that is embodied in the 10000 to 50000 design rules that these designs must comply within advanced CMOS manufacturing. Here, we present a photonic design automation (PDA) tool which allows automatic generation of layouts without design-rule violations. Our tool is written in SKILL, the native language of the mainstream electric design automation (EDA) software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. Removal of design-rule violations - based on Manhattan discretization, Boolean and sizing operations - occurs during data preparation from the initial photonic layers to the final mask...

  16. A single ended low Noise Rail to Rail CMOS Preamplifier

    CERN Document Server

    Trampitsch, G

    2007-01-01

    The CMOS scaling process that is mainly driven by the need to improve digital performance poses critical problems in terms of dynamic range to analog design. Conventional preamplifier-architectures that are considered as optimum design practice have proven useful for many decades. To overcome some of the new constraints a variety of components is available. This increases the number of necessary masks and therefore the cost of circuit fabrication. In order to cope with the constraints of today's low supply voltages a rail to rail charge sensitive preamplifier designed in a 0.13 mum process is presented. A comparison is made of the proposed design with conventional architectures. Design parameters like output swing ability, gain, bandwidth, power consumption and noise performance are investigated. Finally, experimental results from a prototype submission are presented.

  17. Analysis of the Noise Characteristics of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1997-01-01

    The definition of the current conveyor is reviewed and a multiple-output second generation current conveyor (CCII) is shown to combine the different generations of current conveyors presently existing. Next, noise sources are introduced, and a general noise model for the current conveyor...... is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches...... to an optimization of the noise performance are discussed. It is concluded that a class AB implementation can yield a lower noise output for the same dynamic range than a class A implementation. For both the class A implementation and the class AB implementation it is essential to design low noise current mirrors...

  18. A CMOS low-noise instrumentation amplifier using chopper modulation

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Bruun, Erik

    2005-01-01

    This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal...... band hereby ensuring overall low noise performance. The resulting equivalent input referred noise is approximately 7 nV/rootHz for a chopping frequency of 20 kHz. The amplifier operates from a modest supply voltage of 1.8 V, drawing 136 muA of current thus consuming 245 muW of power. The gain is 72.5 d...

  19. Voltage-to-frequency converters CMOS design and implementation

    CERN Document Server

    Azcona Murillo, Cristina; Pueyo, Santiago Celma

    2013-01-01

    This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

  20. Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor

    Directory of Open Access Journals (Sweden)

    Wei-Song Wang

    2010-03-01

    Full Text Available Presented is a single-ended potentiostat topology with a new interface connection between sensor electrodes and potentiostat circuit to avoid deviation of cell voltage and linearly convert the cell current into voltage signal. Additionally, due to the increased harmonic distortion quantity when detecting low-level sensor current, the performance of potentiostat linearity which causes the detectable current and dynamic range to be limited is relatively decreased. Thus, to alleviate these irregularities, a fully-differential potentiostat is designed with a wide output voltage swing compared to single-ended potentiostat. Two proposed potentiostats were implemented using TSMC 0.18-μm CMOS process for biomedical application. Measurement results show that the fully differential potentiostat performs relatively better in terms of linearity when measuring current from 500 ºpA to 10 uA. Besides, the dynamic range value can reach a value of 86 dB.

  1. Characterizing Subpixel Spatial Resolution of a Hybrid CMOS Detector

    Science.gov (United States)

    Bray, Evan; Burrows, Dave; Chattopadhyay, Tanmoy; Falcone, Abraham; Hull, Samuel; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

    2018-01-01

    The detection of X-rays is a unique process relative to other wavelengths, and allows for some novel features that increase the scientific yield of a single observation. Unlike lower photon energies, X-rays liberate a large number of electrons from the silicon absorber array of the detector. This number is usually on the order of several hundred to a thousand for moderate-energy X-rays. These electrons tend to diffuse outward into what is referred to as the charge cloud. This cloud can then be picked up by several pixels, forming a specific pattern based on the exact incident location. By conducting the first ever “mesh experiment" on a hybrid CMOS detector (HCD), we have experimentally determined the charge cloud shape and used it to characterize responsivity of the detector with subpixel spatial resolution.

  2. CMOS Silicon-on-Sapphire RF Tunable Matching Networks

    Directory of Open Access Journals (Sweden)

    Chamseddine Ahmad

    2006-01-01

    Full Text Available This paper describes the design and optimization of an RF tunable network capable of matching highly mismatched loads to 50 at 1.9 GHz. Tuning was achieved using switched capacitors with low-loss, single-transistor switches. Simulations show that the performance of the matching network depends strongly on the switch performances and on the inductor losses. A 0.5 m silicon-on-sapphire (SOS CMOS technology was chosen for network implementation because of the relatively high-quality monolithic inductors achievable in the process. The matching network provides very good matching for inductive loads, and acceptable matching for highly capacitive loads. A 1 dB compression point greater than dBm was obtained for a wide range of load impedances.

  3. On Dynamic Range Limitations of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1999-01-01

    This paper is concerned with the dynamic range of continuous time CMOS current mode circuits. As a representative current mode device a class AB current conveyor is examined. First, the voltage input range of the high impedance Y input is investigated. Next, the current input range of the low...... impedance X input is investigated. It is compared to the thermal noise in the X to Z signal path in order to evaluate the dynamic range, and the dependencies of the dynamic range on the supply voltage and the transistor lay-out is derived, both for the situation where the conveyor is used over a narrow...... frequency band and for the situation where the conveyor is used over the full bandwidth achievable. Finally, the optimisation of the current input range is related to the distortion characteristics and it is pointed out that to a first order approximation the distortion is independent of the current range....

  4. CMOS Ultra-Wideband Low Noise Amplifier Design

    Directory of Open Access Journals (Sweden)

    K. Yousef

    2013-01-01

    Full Text Available This paper presents the design of ultra-wideband low noise amplifier (UWB LNA. The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

  5. Selection of quasi-monodisperse super-micron aerosol particles

    Science.gov (United States)

    Rösch, Michael; Pfeifer, Sascha; Wiedensohler, Alfred; Stratmann, Frank

    2014-05-01

    Size-segregated quasi monodisperse particles are essential for e.g. fundamental research concerning cloud microphysical processes. Commonly a DMA (Differential Mobility Analyzer) is used to produce quasi-monodisperse submicron particles. Thereto first, polydisperse aerosol particles are bipolarly charged by a neutralizer, and then selected according to their electrical mobility with the DMA [Knutson et al. 1975]. Selecting a certain electrical mobility with a DMA results in a particle size distribution, which contains singly charged particles as well as undesired multiply charged larger particles. Often these larger particles need to either be removed from the generated aerosol or their signals have to be corrected for in the data inversion and interpretation process. This problem becomes even more serious when considering super-micron particles. Here we will present two different techniques for generating quasi-monodisperse super-micron aerosol particles with no or only an insignificant number of larger sized particles being present. First, we use a combination of a cyclone with adjustable aerodynamic cut-off diameter and our custom-built Maxi-DMA [Raddatz et al. 2013]. The cyclone removes particles larger than the desired ones prior to mobility selection with the DMA. This results in a reduction of the number of multiply charged particles of up to 99.8%. Second, we utilize a new combination of cyclone and PCVI (Pumped Counterflow Virtual Impactor), which is based on purely inertial separation and avoids particle charging. The PCVI instrument was previously described by Boulter et al. (2006) and Kulkarni et al. (2011). With our two setups we are able to produce quasi-monodisperse aerosol particles in the diameter range from 0.5 to 4.4 µm without a significant number of larger undesired particles being present. Acknowledgements: This work was done within the framework of the DFG funded Ice Nucleation research UnIT (INUIT, FOR 1525) under WE 4722/1-1. References

  6. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  7. Single closed contact for 0.18-micron photolithography process

    Science.gov (United States)

    Cheung, Cristina; Phan, Khoi A.; Chiu, Robert J.

    2000-06-01

    With the rapid advances of deep submicron semiconductor technology, identifying defects is converted into a challenge for different modules in the fabrication of chips. Yield engineers often do bitmap on a memory circuit array (SRAM) to identify the failure bits. This is followed by a wafer stripback to look for visual defects at each deprocessed layer for feedback to the Fab. However, to identify the root cause of a problem, Fab engineers must be able to detect similar defects either on the product wafers in process or some short loop test wafers. In the photolithography process, we recognize that the detection of defects is becoming as important as satisfying the critical dimension (CD) of the device. For a multi-level metallization chemically mechanical polish backend process, it is very difficult to detect missing contacts or via at the masking steps due to metal grain roughness, film color variation and/or previous layer defects. Often, photolithography engineer must depend on Photo Cell Monitor (PCM) and short loop experiments for controlling baseline defects and improvement. In this paper, we discuss the findings on the Poly mask PCM and the Contact mask PCM. We present the comparison between the Poly mask and the Contact mask of the I-line Phase Shifted Via mask and DUV mask process for a 0.18 micron process technology. The correlation and the different type of defects between the Contact PCM and the Poly Mask are discussed. The Contact PCM was found to be more sensitive and correlated to contact failure at sort yield better. We also dedicate to study the root cause of a single closed contact hole in the Contact mask short loop experiment for a 0.18 micron process technology. A single closed contact defect was often caused by the developer process, such as bubbles in the line, resist residue left behind, and the rinse mechanism. We also found surfactant solution helps to improve the surface tension of the wafer for the developer process and this prevents

  8. Viewing Seasonality in 8 Megacities at 4 Microns

    Science.gov (United States)

    Tomaszewska, M. A.; Kovalskyy, V.; Small, C.; Henebry, G. M.

    2013-12-01

    The middle infrared (MIR) spectral region, between 3 and 5 microns, offers a different perspective on cities. The MIR is the mixing zone of both emitted terrestrial radiation and reflected solar radiation. The relatively long wavelengths enable views of surfaces often obscured by anthropogenic haze. Green vegetation appears very dark in the MIR due to high absorption by leaf water. In contrast, building, roofing, and paving materials reflect much MIR and exposed soils and dried vegetation reflect even more. Thus, physics dictates a strong expression of seasonality in the MIR. But is there sufficient signal in the MIR to merit it as a complementary approach for characterizing urbanized areas and monitoring their dynamics? We have explored this question in a research effort that links two NASA Interdisciplinary Science projects on the effect of cities on the environment. We focused on 8 global megacities: Beijing, Cairo, Istanbul, Mexico, Moscow, Nairobi, New Delhi, and São Paulo. We used Level 1B calibrated radiance data from band 23 (~4 microns) of the Aqua MODIS during ascending passes in 2010. These 1 km data were processed to reduce cloud cover using monthly maximum value compositing into four sensor view zenith angle (VZA) classes: 0urban, agriculture, and 'natural' which included forest, savanna, or desert depending on the city. The seasonal patterns of MIR radiance varied, as expected, by latitude, with very strong seasonality effects at higher latitudes (Beijing, Cairo, Istanbul, Moscow), and lesser to minimal seasonal signals evident in the tropics (Mexico City, Nairobi, São Paulo). The monsoon imposed strong MIR seasonality in New Delhi. The strength of the seasonality was modulated by the VZA with smaller VZAs (30°). SNR was higher in the summer months and quite low in the winter months at high latitudes, as was expected due to the seasonal cycle of irradiance. The urban land cover showed higher seasonal dynamic range than most other cover types, with

  9. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Risti{c}, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  10. Merits of CMOS/SIMOX technology for low-voltage SRAM macros

    CERN Document Server

    Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

    1999-01-01

    A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

  11. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II SBIR project a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at sub 1 micro-g levels...

  12. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This Phase I SBIR effort initiates development of a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at...

  13. Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Q [Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA94720 (United States); Van Duzer, T [Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA94720 (United States); Fujiwara, K [Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA94720 (United States); Yoshikawa, N [Department of Electrical and Computer Engineering, Yokohama National University, Hodogaya, Yokohama (Japan)

    2006-06-01

    Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 {mu}m CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm{sup 2} technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory.

  14. Design and coupled-effect simulations of CMOS micro gas sensors built on SOI thin membranes

    Science.gov (United States)

    Lu, Chih-Cheng; Udrea, Florin; Gardner, Julian W.; Setiadi, D.; Dogaru, T.; Tsai, T. H.; Covington, James A.

    2001-04-01

    This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro- thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

  15. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    Science.gov (United States)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  16. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  17. A CMOS-Compatible Hybrid Plasmonic Slot Waveguide With Enhanced Field Confinement

    NARCIS (Netherlands)

    Xiao, Jing; Wei, Qi-Qin; Yang, Daoguo; Zhang, Ping; He, Ning; Zhang, G.Q.; Ren, Tian-Ling; Chen, XP

    2016-01-01

    The emerging field of nanophotonics requires plasmonic devices to be fully compatible with semiconductor fabrication techniques. However, very few feasible practical structures exist at present. Here, we propose a CMOS-compatible hybrid plasmonic slot waveguide (HPSW) with enhanced field

  18. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Gaudiello, Andrea; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  19. The power conversion efficiency of visible light emitting devices in standard BiCMOS processes

    NARCIS (Netherlands)

    Kuindersma, P.; Hoang, T.; Schmitz, Jurriaan; Vijayaraghavan, M.N.; Dijkstra, Mindert; Dijkstra, M.; van Noort, W.A.; Vanhoucke, T.; Peters, W.C.M.; Kramer, M.C.J.C.M.

    2008-01-01

    We present experimental and theoretical proof for a single and unique relationship between the breakdown voltage and power efficiency of visible light emitting devices fabricated in standard BiCMOS processes.

  20. Micronized Coal Reburning Demonstration for NOx Control: A DOE Assessment

    Energy Technology Data Exchange (ETDEWEB)

    National Energy Technology Laboratory

    2001-08-15

    The goal of the U.S. Department of Energy's (DOE) Clean Coal Technology (CCT) program is to furnish the energy marketplace with a number of advanced, more efficient, and environmentally responsible coal utilization technologies through demonstration projects. These projects seek to establish the commercial feasibility of the most promising advanced coal technologies that have developed beyond the proof-of-concept stage. This document serves as a DOE post-project assessment of a project selected in CCT Round IV, the Micronized Coal Reburning (MCR) Demonstration for NO{sub x} Control, as described in a report to Congress (U.S. Department of Energy 1999). The need to meet strict emissions requirements at a minimum cost prompted the Tennessee Valley Authority (TVA), in conjunction with Fuller Company, Energy and Environmental Research Corporation (EER), and Fluor Daniel, to submit the proposal for this project to be sited at TVA's Shawnee Fossil Plant. In July 1992, TVA entered into a cooperative agreement with DOE to conduct the study. However, because of operational and environmental compliance strategy changes, the Shawnee site became unavailable.

  1. Carotenoids microencapsulation by spray drying method and supercritical micronization.

    Science.gov (United States)

    Janiszewska-Turak, Emilia

    2017-09-01

    Carotenoids are used as natural food colourants in the food industry. As unstable natural pigments they need protection. This protection can involve the microencapsulation process. There are numerous techniques that can be used for carotenoid protection, but two of them -spray drying and supercritical micronization - are currently the most commonly used. The objective of this paper is to describe these two techniques for carotenoid microencapsulation. In this review information from articles from the last five years was taken into consideration. Pigments described in the review are all carotenoids. Short summary of carotenoids sources was presented. For the spray drying technique, a review of carrier material and process conditions was made. Moreover, a short description of some of the most suitable processes involving supercritical fluids for carotenoids (astaxanthin, β-carotene, lutein and lycopene) encapsulation was given. These include the Supercritical Antisolvent process (SAS), Particles from Gas-Saturated Solutions (PGSS), Supercritical Fluid Extraction From an Emulsion (SFEE) and Solution Enhanced Dispersion by Supercritical fluids (SEDS). In most cases the studies, independently of the described method, were conducted on the laboratory scale. In some a scale-up was also tested. In the review a critical assessment of the used methods was made. Copyright © 2017 Elsevier Ltd. All rights reserved.

  2. Marketing activities in the area of micronization services

    Directory of Open Access Journals (Sweden)

    Sołtysik Barbara

    2016-12-01

    Full Text Available Under conditions of constantly growing competition, what is becoming a key problem is keeping the previously acquired clients. Their trust in the provider and regularly repeated purchases are an expression of the efficiency of marketing activities conducted by companies. What is becoming a measure of success is the satisfaction and loyalty of buyers. Companies spend a lot of money to attract clients and the competition keeps trying to take away their clients. A lost client means not just the loss of a future order – this is the loss of revenues equal to the value of all products which a particular buyer could purchase in his entire life. On top of that comes the cost of acquiring new client to replace the old one. TARP research shows that the cost of acquiring a new client is five times higher than the cost of pleasing an existing client (Kotler, 2006. In the publication the significance of the relations with the client are discussed with regard to efficient marketing strategy. Moreover, the results of client satisfaction surveys and market analysis taking into consideration the revenues from sale of services in the area of micronization are presented.

  3. Timing Challenges for Very Deep Sub-Micron (VDSM IC

    Directory of Open Access Journals (Sweden)

    Ichiang Lin

    2002-01-01

    Full Text Available Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half-micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan-outs, buses, which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to lost market share. Full-chip, sign-off verification with silicon-accuracy will allow these problems to be discovered and fixed before tape-out.

  4. Mapping coalescence of micron-sized drops and bubbles.

    Science.gov (United States)

    Berry, Joseph D; Dagastine, Raymond R

    2017-02-01

    Emulsion formulation, solvent extraction and multiphase microfluidics are all examples of processes that require precise control of drop or bubble collision stability. We use a previously validated numerical model to map the exact conditions under which micron-sized drops or bubbles undergo coalescence in the presence of colloidal forces and hydrodynamic effects relevant to Brownian motion and low Reynolds number flows. We demonstrate that detailed understanding of how the equilibrium surface forces vary with film thickness can be applied to make accurate predictions of the outcome of a drop or bubble collision when hydrodynamic effects are negligible. In addition, we illuminate the parameter space (i.e. interaction velocity, drop deformation, interfacial tension, etc.) at which hydrodynamic effects can stabilise collisions that are unstable at equilibrium. Further, we determine conditions for which drop or bubble collisions become unstable upon separation, caused by negative hydrodynamic pressure in the film. Lastly, we show that scaling analyses are not applicable for constant force collisions where the approach timescale is comparable to the coalescence timescale, and demonstrate that initial conditions under these circumstances cannot be ignored. Copyright © 2016 Elsevier Inc. All rights reserved.

  5. Micron size GMR magnetic sensor with needle structure

    Science.gov (United States)

    Yamada, S.; Haraszczuk, R.; Kakikawa, M.; Hoang, H.

    2012-05-01

    The work presents inimitable shaped needle type probe with spin valve giant magnetoresistance (SV-GMR) elements. Sensitive elements with 75 μm width are connected in the Wheatstone bridge structure. The length of the needle is 20-30 mm and its cross section is square. The magnetic sensor probe has the advantage of micron order spatial resolution. The needle type probe works as a gradient meter which concurrently suppresses the influence of externally applied field and detects magnetic fields emanating from nano or micro order size sources. Sensing elements present high sensitivity 260 μV/μT and are capable of detecting the magnetic fields in order of few nT. SV-GMR elements present flat amplitude and phase characteristics in wide frequency range. The novel characteristicsof the probe allow it to be utilized in detection of the in-phase and out of phase signal components. An additional merit of this design is extremely small liftoff height between sensing element and the source of magnetic field. The SV-GMR elements are isolated only by very thin protection layer (a few μm), that gives opportunity to apply the probe in biological (in vivo) experiments, and in non destructive evaluation of current detection. The needle shape allows the sensing element toapproach the examined materials in a distance of few ten μm.

  6. Discovering Motifs in Biological Sequences Using the Micron Automata Processor.

    Science.gov (United States)

    Roy, Indranil; Aluru, Srinivas

    2016-01-01

    Finding approximately conserved sequences, called motifs, across multiple DNA or protein sequences is an important problem in computational biology. In this paper, we consider the (l, d) motif search problem of identifying one or more motifs of length l present in at least q of the n given sequences, with each occurrence differing from the motif in at most d substitutions. The problem is known to be NP-complete, and the largest solved instance reported to date is (26,11). We propose a novel algorithm for the (l,d) motif search problem using streaming execution over a large set of non-deterministic finite automata (NFA). This solution is designed to take advantage of the micron automata processor, a new technology close to deployment that can simultaneously execute multiple NFA in parallel. We demonstrate the capability for solving much larger instances of the (l, d) motif search problem using the resources available within a single automata processor board, by estimating run-times for problem instances (39,18) and (40,17). The paper serves as a useful guide to solving problems using this new accelerator technology.

  7. Penetration and Effectiveness of Micronized Copper in Refractory Wood Species.

    Directory of Open Access Journals (Sweden)

    Chiara Civardi

    Full Text Available The North American wood decking market mostly relies on easily treatable Southern yellow pine (SYP, which is being impregnated with micronized copper (MC wood preservatives since 2006. These formulations are composed of copper (Cu carbonate particles (CuCO3·Cu(OH2, with sizes ranging from 1 nm to 250 μm, according to manufacturers. MC-treated SYP wood is protected against decay by solubilized Cu2+ ions and unreacted CuCO3·Cu(OH2 particles that successively release Cu2+ ions (reservoir effect. The wood species used for the European wood decking market differ from the North American SYP. One of the most common species is Norway spruce wood, which is poorly treatable i.e. refractory due to the anatomical properties, like pore size and structure, and chemical composition, like pit membrane components or presence of wood extractives. Therefore, MC formulations may not suitable for refractory wood species common in the European market, despite their good performance in SYP. We evaluated the penetration effectiveness of MC azole (MCA in easily treatable Scots pine and in refractory Norway spruce wood. We assessed the effectiveness against the Cu-tolerant wood-destroying fungus Rhodonia placenta. Our findings show that MCA cannot easily penetrate refractory wood species and could not confirm the presence of a reservoir effect.

  8. Micron-gap ThermoPhotoVoltaics (MTPV)

    Science.gov (United States)

    DiMatteo, R.; Greiff, P.; Seltzer, D.; Meulenberg, D.; Brown, E.; Carlen, E.; Kaiser, K.; Finberg, S.; Nguyen, H.; Azarkevich, J.; Baldasaro, P.; Beausang, J.; Danielson, L.; Dashiell, M.; DePoy, D.; Ehsani, H.; Topper, W.; Rahner, K.; Siergiej, R.

    2004-11-01

    This paper discusses advances made in the field of Micron-gap ThermoPhotoVoltaics (MTPV). Initial modeling has shown that MTPV may enable significant performance improvements relative to conventional far field TPV. These performance improvements include up to a 10× increase in power density, 30% to 35% fractional increase in conversion efficiency, or alternatively, reduced radiator temperature requirements to as low as 550°C. Recent experimental efforts aimed at supporting these predictions have successfully demonstrated that early current and voltage enhancements could be done repeatedly and at higher temperatures. More importantly, these efforts indicated that no unknown energy transfer process occurs reducing the potential utility of MTPV. Progress has been made by running tests with at least one of the following characteristics relative to the MTPV results reported in 2001: • Tests at over twice the temperature (900°C). • Tests at 50% smaller gaps (0.12 μm) • Tests with emitter areas from 4 to 100 times larger (16 mm2 to 4 cm2). • Tests with over 20× reduction in parasitic spacer heat flow. Remaining fundamental challenges to realizing these improvements relative to the recent breakthroughs in conventional far field TPV include reengineering the photovoltaic (PV) diode, filter, and emitter system for MTPV and engineering devices and systems that can achieve submicron vacuum gaps between surfaces with large temperature differences.

  9. Micron-gap ThermoPhotoVoltaics (MTPV)

    Energy Technology Data Exchange (ETDEWEB)

    R DiMatteo; P Greiff; D Seltzer; D Meaulenberg; E Brown; E Carlen; K Kaiser; S Finberg; H Ngyyen; J Azarkevich; P Baldasaro; J Beausang; L Danielson; M Dashiell; D DePoy; H Ehsani; W Topper; K Rahner; R Siergiej

    2004-08-24

    This paper discusses advances made in the field of Micron-gap ThermoPhotoVoltaics (MTPV). Initial modeling has shown that MTPV may enable significant performance improvements relative to conventional far field TPV. These performance improvements include up to a 10x increase in power density, 30% to 35% fractional increase in conversion efficiency, or alternatively, reduced radiator temperature requirements to as low as 550 C. Recent experimental efforts aimed at supporting these predictions have successfully demonstrated that early current and voltage enhancements could be done repeatedly and at higher temperatures. More importantly, these efforts indicated that no unknown energy transfer process occurs reducing the potential utility of MTPV. Progress has been made by running tests with at least one of the following characteristics relative to the MTPV results reported in 2001: Tests at over twice the temperature (900 C); Tests at 50% smaller gaps (0.12 {micro}m); Tests with emitter areas from 4 to 100 times larger (16 mm{sup 2} to 4 cm{sup 2}); and Tests with over 20x reduction in parasitic spacer heat flow. Remaining fundamental challenges to realizing these improvements relative to the recent breakthroughs in conventional far field TPV include reengineering the photovoltaic (PV) diode, filter, and emitter system for MTPV and engineering devices and systems that can achieve submicron vacuum gaps between surfaces with large temperature differences.

  10. Method of producing carbon coated nano- and micron-scale particles

    Science.gov (United States)

    Perry, W. Lee; Weigle, John C; Phillips, Jonathan

    2013-12-17

    A method of making carbon-coated nano- or micron-scale particles comprising entraining particles in an aerosol gas, providing a carbon-containing gas, providing a plasma gas, mixing the aerosol gas, the carbon-containing gas, and the plasma gas proximate a torch, bombarding the mixed gases with microwaves, and collecting resulting carbon-coated nano- or micron-scale particles.

  11. Separating the signal from the noise: Expanding flow cytometry into the sub-micron range.

    Science.gov (United States)

    Cytometry Part A Special Section: Separating the signal from the noise: Expanding flow cytometry into the sub-micron range. The current Cytometry Part A Special Section presents three studies that utilize cytometers to study sub-micron particles. The three studies involve the 1...

  12. β-Tricalcium Phosphate Micron Particles Enhance Calcification of Human Mesenchymal Stem Cells In Vitro

    Directory of Open Access Journals (Sweden)

    Yusuke Nakagawa

    2013-01-01

    Full Text Available β-Tricalcium phosphate (β-TCP micron particles whose diameters range from 1 μm to 10 μm have been recently developed, however, their biological effects remain unknown. We investigated the biological effects of β-TCP micron particles on proliferation, cytotoxicity, and calcification of human synovial mesenchymal stem cells (MSCs. MSCs were cultured without dexamethasone, β-glycerophosphate, or ascorbic acid. 1.0 mg/mL β-TCP micron particles inhibited proliferation of MSCs significantly and increased dead cells. In the contact condition, 0.1 mg/mL β-TCP micron particles promoted calcification of MSCs evaluated by alizarin red staining and enhanced mRNA expressions of runx2, osteopontin, and type I collagen. In the noncontact condition, these effects were not observed. 0.1 mg/mL β-TCP micron particles increased calcium concentration in the medium in the contact condition, while 1.0 mg/mL β-TCP micron particles decreased calcium and phosphorus concentrations in the medium in the noncontact condition. By transmission electron microscopy, β-TCP micron particles were localized in the phagosome of MSCs and were dissolved. In conclusion, β-TCP micron particles promoted calcification of MSCs and enhanced osteogenesis-related gene expressions in vitro.

  13. Synchronous and asynchronous detection of ultra-law light levels using CMOS-compatible semiconductor technologies

    OpenAIRE

    Lotto, Christian; Seitz, Peter; Charbon, Edoardo; Enz, Christian; Farine, Pierre-André

    2011-01-01

    This work presents significant improvements of noise performance in synchronous CMOS image sensors and in asynchronous energy-sensitive singlephoton X-ray imaging systems. A detailed analysis of synchronous CMOS low-noise image sensors using conventional architectures reveals room for potential noise performance improvements, namely noise in switched-capacitor column-parallel amplifiers as well as imperfections in the low-pass filtering properties provided by such switched-capacitor amplifier...

  14. A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance

    DEFF Research Database (Denmark)

    Andreani, Pietro; Fard, Ali

    2006-01-01

    The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3mum CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V...

  15. Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

    CERN Document Server

    Duzer, T V; Meng Xiao Fan; Whiteley, S R; Yoshikawa, N

    2002-01-01

    The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented.

  16. Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

    Energy Technology Data Exchange (ETDEWEB)

    Duzer, Theodore van [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Feng Yijun [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Meng Xiaofan [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Whiteley, Stephen R [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Yoshikawa, Nobuyuki [Department of Electrical and Computer Engineering, Yokohama National University (Japan)

    2002-12-01

    The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented.

  17. CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

    OpenAIRE

    De Groof, Anik; Berghmans, David; Nicula, Bogdan; Halain, Jean-Philippe; Defise, J. -M.; Thibert, Tanguy; Schühle, Udo

    2008-01-01

    CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is...

  18. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    CERN Document Server

    Benoit, M.

    2016-07-21

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  19. Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

    Science.gov (United States)

    Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

    2017-02-01

    The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

  20. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    Science.gov (United States)

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  1. A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

    Science.gov (United States)

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

  2. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    Directory of Open Access Journals (Sweden)

    Mohd Haris Md Khir

    2011-08-01

    Full Text Available This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

  3. Counting neutrons with a commercial S-CMOS camera

    Science.gov (United States)

    Patrick, Van Esch; Paolo, Mutti; Emilio, Ruiz-Martinez; Estefania, Abad Garcia; Marita, Mosconi; Jon, Ortega

    2018-01-01

    It is possible to detect individual flashes from thermal neutron impacts in a ZnS scintillator using a CMOS camera looking at the scintillator screen, and off line image processing. Some preliminary results indicated that the efficiency of recognition could be improved by optimizing the light collection and the image processing. We will report on this ongoing work which is a result from the collaboration between ESS Bilbao and the ILL. The main progress to be reported is situated on the level of the on-line treatment of the imaging data. If this technology is to work on a genuine scientific instrument, it is necessary that all the processing happens on line, to avoid the accumulation of large amounts of image data to be analyzed off line. An FPGA-based real-time full-deca mode VME-compatible CameraLink board has been developed at the SCI of the ILL, which is able to manage the data flow from the camera and convert it in a reasonable "neutron impact" data flow like from a usual neutron counting detector. The main challenge of the endeavor is the optical light collection from the scintillator. While the light yield of a ZnS scintillator is a priori rather important, the amount of light collected with a photographic objective is small. Different scintillators and different light collection techniques have been experimented with and results will be shown for different setups improving upon the light recuperation on the camera sensor. Improvements on the algorithm side will also be presented. The algorithms have to be at the same time efficient in their recognition of neutron signals, in their rejection of noise signals (internal and external to the camera) but also have to be simple enough to be easily implemented in the FPGA. The path from the idea of detecting individual neutron impacts with a CMOS camera to a practical working instrument detector is challenging, and in this paper we will give an overview of the part of the road that has already been walked.

  4. Advanced source/drain and contact design for nanoscale CMOS

    Science.gov (United States)

    Vega, Reinaldo

    The development of nanoscale MOSFETs has given rise to increased attention paid to the role of parasitic source/drain and contact resistance as a performance-limiting factor. Dopant-segregated Schottky (DSS) source/drain MOSFETs have become popular in recent years to address this series resistance issue, since DSS source/drain regions comprise primarily of metal or metal silicide. The small source/drain extension (SDE) regions extending from the metallic contact regions are an important design parameter in DSS MOSFETs, since their size and concentration affect contact resistance, series resistance, band-to-band tunneling (BTBT), SDE tunneling, and direct source-to-drain tunneling (DSDT) leakage. This work investigates key design issues surrounding DSS MOSFETs from both a modeling and experimental perspective, including the effect of SDE design on ambipolar leakage, the effect of random dopant fluctuation (RDF) on specific contact resistivity, 3D FinFET source/drain and contact design optimization, and experimental methods to achieve tuning of the SDE region. It is found that DSS MOSFETs are appropriate for thin body high performance (HP) and low operating power (LOP) MOSFETs, but not low standby power (LSTP) MOSFETs, due to a trade-off between ambipolar leakage and contact resistance. It is also found that DSDT will not limit DSS MOSFET scalability, nor will RDF limit contact resistance scaling, at the end of the CMOS roadmap. Furthermore, it is found that SDE tunability in DSS MOSFETs is achievable in the real-world, for an implant-to-silicide (ITS) process, by employing fluorine implant prior to metal deposition and silicidation. This is found to open up the DSS process design space for the trade-off between SDE junction depth and contact resistance. Si1-xGex process technology is also explored, and Ge melt processing is found to be a promising low-cost alternative to epitaxial Si1-xGex growth for forming crystalline Si1-xGe x films. Finally, a new device

  5. On the degradation of OTA-C--based CMOS low-power filter circuits for biomedical instrumentation

    OpenAIRE

    ÖZCELEP, Yasin; KUNTMAN, Ayten; Kuntman, Hulusi Hakan

    2011-01-01

    In this work, we propose a degraded transistor-based circuit degradation simulation method to investigate the degradation effect in complementary metal-oxide semiconductor (CMOS) biomedical devices. The method is demonstrated on an operational transconductance amplifier and capacitor (OTA-C)-based CMOS filter structure. First, we simulate the degradation of the symmetrical CMOS OTA by determining the degraded transistors in the structure. The simulation results are compared with the exper...

  6. The formation of photoresist film with thicknesses from 0.7 microns to 100 microns on surfaces with considerable relief by spray coating on the heated substrate

    Science.gov (United States)

    Romashkin, Alexey V.; Levin, Denis D.; Rozanov, Roman Yu.; Nevolin, Vladimir K.

    2016-12-01

    The principle of the formation of thin and thick photoresist films on surfaces with considerable relief by the aerosol deposition using ultra low flow was investigated. It was shown that the change in the photoresist blend composition of solution is required with decreasing film thickness less than 1 micron to achieve a roughness of less than 150 nm. And the film at least 0.7 microns thickness can be formed and have the uniform film thickness as on the walls and on horizontal surfaces on the substrate with grooves obtained by etching liquid. It is shown that even with a film thickness of 10 microns vertical walls may be partially cover the of the photoresist and unfilled plasma-chemical etching grooves with vertical walls, whose width not exceeding 10 microns. To determine the uniformity of film thickness atomic force microscopy was used. And it was shown that up to 2 microns of film thickness spectroscopic methods with the analysis of the fluorescent signal intensity for positive photoresists is possible to use too.

  7. Analysis and Test Development for Parasitic Fails in Deep Sub-Micron Memory Devices

    NARCIS (Netherlands)

    Irobi, I.S.

    2011-01-01

    Emerging technology trends are gravitating towards extremely high levels of integration at the package and chip levels, and use of deeply scaled technology in nanometer, approaching 10nm CMOS. Challenges will arise due to the ability to design complex systems such as robots that encompass sensors,

  8. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

    Directory of Open Access Journals (Sweden)

    Michele Grassi

    2009-06-01

    Full Text Available This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively.

  9. Variation-aware adaptive voltage scaling for digital CMOS circuits

    CERN Document Server

    Wirnshofer, Martin

    2013-01-01

    Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engine...

  10. CMOS indoor light energy harvesting system for wireless sensing applications

    CERN Document Server

    Ferreira Carvalho, Carlos Manuel

    2016-01-01

    This book discusses in detail the CMOS implementation of energy harvesting.  The authors describe an integrated, indoor light energy harvesting system, based on a controller circuit that dynamically and automatically adjusts its operation to meet the actual light circumstances of the environment where the system is placed.  The system is intended to power a sensor node, enabling an autonomous wireless sensor network (WSN). Although designed to cope with indoor light levels, the system is also able to work with higher levels, making it an all-round light energy harvesting system.  The discussion includes experimental data obtained from an integrated manufactured prototype, which in conjunction with a photovoltaic (PV) cell, serves as a proof of concept of the desired energy harvesting system.  ·         Discusses several energy sources which can be used to power energy harvesting systems and includes an overview of PV cell technologies  ·         Includes an introduction to voltage step-...

  11. Edge-TCT measurements on irradiated HV CMOS sensors

    CERN Document Server

    Weisser, Constantin

    2014-01-01

    Passive $100 \\times 100 \\,\\mu$m test diodes in an unirradiated and an irradiated HV2FEI4v3 HV-CMOS silicon sensor were analysed using the edge TCT technique. To integrate the sensor into the setup a PCB was designed to extract the signals, a cooling mechanism was constructed and the system housed in a shielding box. The observed signal had fast and slow contributions, that were interpreted as drift and diffusion. The former peaked in a region, that was interpreted as the depletion region, while the latter peaked further in the bulk material. Raising the bias voltage increased the depth of the former region, while pushing the latter region further into the bulk. The irradiated sample lost signal strength mainly in its slow part compared to the unirradiated sample, while its quick signal remained largely unaffected. As only the signal interpreted as drift is fast enough to be useful in LHC operation the investigated sensors could be considered radiation hard for this purpose. This gives further promise to ...

  12. High resolution, high bandwidth global shutter CMOS area scan sensors

    Science.gov (United States)

    Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

    2013-10-01

    Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

  13. Silicon CMOS architecture for a spin-based quantum computer.

    Science.gov (United States)

    Veldhorst, M; Eenink, H G J; Yang, C H; Dzurak, A S

    2017-12-15

    Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

  14. Monolithic optical link in silicon-on-insulator CMOS technology.

    Science.gov (United States)

    Dutta, Satadal; Agarwal, Vishal; Hueting, Raymond J E; Schmitz, Jurriaan; Annema, Anne-Johan

    2017-03-06

    This work presents a monolithic laterally-coupled wide-spectrum (350 nm link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical abrupt n+p junctions, separated by a shallow trench isolation composed of silicon dioxide. Medium trench isolation around the devices along with the buried oxide layer provides galvanic isolation. Optical coupling in both avalanche-mode and forward-mode operation of the LED are analyzed for various designs and bias conditions. From both DC and pulsed transient measurements, it is further shown that heating in the avalanche-mode LED leads to a slow thermal coupling to the PD with time constants in the ms range. An integrated heat sink in the same technology leads to a ∼ 6 times reduction in the change in PD junction temperature per unit electrical power dissipated in the avalanche-mode LED. The analysis paves way for wide-spectrum optical links integrated in smart power technologies.

  15. Novel integrated CMOS pixel structures for vertex detectors

    Energy Technology Data Exchange (ETDEWEB)

    Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

    2003-10-29

    Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

  16. CMOS Image Sensor with a Built-in Lane Detector

    Directory of Open Access Journals (Sweden)

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  17. CMOS Image Sensor with a Built-in Lane Detector.

    Science.gov (United States)

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  18. Compact modeling of CMOS transistors under variable uniaxial stress

    Science.gov (United States)

    Wacker, Nicoleta; Richter, Harald; Hassan, Mahadi-Ul; Rempp, Horst; Burghartz, Joachim N.

    2011-03-01

    This paper presents a novel implementation of variable uniaxial mechanical stress model to be used with DC circuit simulation, e.g. using BSIM3v3 transistor model. Based on transistor measurements under various uniaxial stress conditions two stress-dependent parameters are identified, namely the carriers mobility and to a lesser extend the carrier saturation velocity. The effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail. Using the fundamental piezoresistive coefficients, the model has implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0 0 1) silicon (Si) plane. The extended transistor model allows for simulating the effect of uniaxial stress on any MOSFET geometry, under different operation conditions and for any combination of the drain current and stress orientations in the (0 0 1) silicon (Si) plane. The method proposed in this paper is validated by static and dynamic stress-dependent simulations and comparison with experimental data. The method is simulator-independent and can be adapted to other bulk CMOS technologies including SOI processes.

  19. Room-temperature InGaAs detector arrays for 2.5 microns

    Science.gov (United States)

    Olsen, G. H.; Joshi, A. M.; Mason, S. M.; Woodruff, K. M.; Mykietyn, E.

    1989-01-01

    This paper describes new alloy heterojunction detectors of In(.8)Ga(.2)As/InAs(.6)P(.4) which can detect light between 1.7 and 2.6 microns with 50 percent quantum efficiency and 5 mA/sq cm dark current (-1 V) density at room temperature. Wafer probe data showed that over 50 good contiguous 100 micron diameter devices (spaced 400 microns) could be made on a 25 x 30 mm wafer with overall yield above 93 percent. The ability to operate under -1 V reverse bias makes these devices ideally compatible with existing commercial multiplexer readouts.

  20. Effect of micronization on the solubility, viscosity and structural properties of tapioca starch

    Science.gov (United States)

    Xia, Wen; Li, Ji-Hua; Wei, Xiao-Yi; Wang, Fei; Lin, Yan-Yun

    2017-09-01

    Tapioca starch (TS) was treated by vibrating superfine mill with different micronization time (15, 30, 45, and 60 mins) and the solubility, viscosity and structural were also studied. The solubilities of treated samples were dramatically increased after micronization treatment. The Fourier Transform Infrared Spectroscopy (FTIR) spectrum of samples did not display any new peaks compared to native TS but had different intensity in some peaks. Rapid visco analyzer (RVA) determination suggested that micronization process altered pasting features, resulting in a decrease in viscosity and pasting temperature.

  1. Emission and extinction of ground and vapor-condensed silicates from 4 to 14 microns and the 10 micron silicate feature

    Science.gov (United States)

    Stephens, J. R.; Rusell, R. W.

    1979-01-01

    Emission and absorption spectra from 4 to 14 microns of ground and laser-vaporized olivine and enstatite silicates are compared with the 10-micron emission feature of the Orion Trapezium. The agreement in band center and shape between the amorphous laser-vaporized olivine sample and the Trapezium feature suggests that amorphous silicate grains of approximately olivine composition may be a major constituent of interstellar dust. Differences between the emission and absorption spectral profiles (absorption plus scattering) show characteristics that could be used as a sensitive probe of the morphology of interstellar grain systems when high signal-to-noise ratio (30-100) observational spectra become available.

  2. George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

    Science.gov (United States)

    Chen, Tze-Chiang (T. C.)

    The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

  3. Ultraviolet detector with CMOS-coupled microchannel plates for future space missions

    Science.gov (United States)

    Murakami, Go; Kuwabara, Masaki; Yoshioka, Kazuo; Hikida, Reina; Suzuki, Fumiharu; Yoshikawa, Ichiro

    2016-07-01

    The extreme ultraviolet (EUV) telescopes and spectrometers have been used as powerful tools in a variety of space applications, especially in planetary science. Many EUV instruments adopted microchannel plate (MCP) detection systems with resistive anode encoders (RAEs). An RAE is one of the position sensitive anodes suitable for space-based applications because of its low power, mass, and volume coupled with very high reliability. However, this detection system with RAE has limitations of resolution (up to 512 x 512 pixels) and incident count rate (up to 104 count/sec). Concerning the future space and planetary missions, a new detector with different position sensitive system is required in order to a higher resolution and dynamic range of incident photons. One of the solutions of this issue is using a CMOS imaging sensor. The CMOS imaging sensor with high resolution and high radiation tolerance has been widely used. Here we developed a new CMOS-coupled MCP detector for future UV space and planetary missions. It consists of MCPs followed by a phosphor screen, fiber optic plate, and a windowless CMOS. We manufactured a test model of this detector and performed vibration, thermal cycle, and performance tests. The test sample of FOP-coupled CMOS image sensor achieved the resolving limit of 32 lp/mm and the PSF of 28 um, corresponds to the spatial resolution of 1024 x 1024 pixels. Our results indicate that this new type of UV detector can be widely used for future space applications.

  4. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    Science.gov (United States)

    Jain, A.; Takemoto, H.; Silver, M. D.; Nagesh, S. V. S.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm x 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  5. A new process for CMOS MEMS capacitive sensors with high sensitivity and thermal stability

    Science.gov (United States)

    Tan, S. S.; Liu, C. Y.; Yeh, L. K.; Chiu, Y. H.; Hsu, Klaus Y. J.

    2011-03-01

    Structure curling induces thermal instability into CMOS MEMS capacitive sensors. The charging effect during reactive ion etching damages the existing on-chip MOS transistors and drastically reduces the yield rate of chips. This paper presents a novel post-CMOS process that solves the problems and leads to CMOS MEMS capacitive sensors with high sensitivity and thermal stability. The novel process was demonstrated with a capacitive accelerometer in 0.35 µm CMOS technology. The accelerometer contains a thermally stable MEMS sensor and an on-chip CMOS sensing circuit with a chopper stabilization scheme. The temperature stabilization was achieved by forming a thick single-crystal silicon (SCS) layer at the bottom of the multi-layer MEMS structure. No leakage current due to charge damage was ever observed in the sample chips. The proposed process also led to minimal undercut of the SCS layer after MEMS structure release. The sensitivity of the accelerometer is 595 mV g-1, and the overall noise floor is 50 µg Hz-1/2 which corresponds to an effective capacitance noise floor of 0.024 aF Hz-1/2. The zero-g temperature coefficient of the accelerometer output voltage is only 1 mV °C-1 in the temperature range from 0 to 70 °C, which corresponds to an effective acceleration variation rate of 1.68 mg °C-1.

  6. CMOS photodetectors/receivers for smart-pixel based photonic systems

    Science.gov (United States)

    Tang, Jianjing; Konanki, Sunil; Seshadri, Bharath; Lee, Boon K.; Chi, Robert C. J.; Steckl, Andrew J.; Beyette, Fred R., Jr.

    2000-11-01

    The design, characterization and evaluation of CMOS based silicon photodetectors/photoreceivers suitable for smart-pixel based applications are presented. Implemented with a conventional CMOS fabrication process, these photodetectors/receiver circuits can be reliably fabricated for smart-pixel based photonic information processing systems that combine the parallelism associated with optics and the data processing capabilities associated with CMOS logic. Several different CMOS based photodetector structures including p-n junction detectors and bipolar phototransistors are presented. Simulation results indicate that the p-n junction detectors will provide photocurrents in the range of nanoamps with rise/fall times on the order of picoseconds. Although slower response is expected with the phototransistor structure, the optoelectronic gain increases the photocurrent to the microamps range. In addition to fabrication and evaluation of individual photodetectors, we present the design and evaluation of high gain photoreceiver array. Based on a standard 1.2 micrometer CMOS fabrication process the monolithic photodetector/receiver circuit includes a bipolar phototransistor, a three-stage current amplifier and a differential amplifier that produces output at digital logic levels. The photoreceiver with high gain and adjustable threshold has a wide dynamic range. For a reference voltage of 3.2 V, the optical power threshold has been measured at less than 1 nW. A page-oriented optical data detection is demonstrated using a 5 X 5 smart-pixel photoreceiver array.

  7. Characterisation of novel prototypes of monolithic HV-CMOS pixel detectors for high energy physics experiments

    Science.gov (United States)

    Terzo, S.; Cavallaro, E.; Casanova, R.; Di Bello, F.; Förster, F.; Grinstein, S.; Períc, I.; Puigdengoles, C.; Ristić, B.; Barrero Pinto, M. Vicente; Vilella, E.

    2017-06-01

    An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active pixel sensors built with the High Voltage CMOS (HV-CMOS) technology are investigated as an option to cover large areas in the outermost layers of the pixel detector and are especially interesting for the development of monolithic devices which will reduce the production costs and the material budget with respect to the present hybrid assemblies. For this purpose the H35DEMO, a large area HV-CMOS demonstrator chip, was designed by KIT, IFAE and University of Liverpool, and produced in AMS 350 nm CMOS technology. It consists of four pixel matrices and additional test structures. Two of the matrices include amplifiers and discriminator stages and are thus designed to be operated as monolithic detectors. In these devices the signal is mainly produced by charge drift in a small depleted volume obtained by applying a bias voltage of the order of 100V. Moreover, to enhance the radiation hardness of the chip, this technology allows to enclose the electronics in the same deep N-WELLs which are also used as collecting electrodes. In this contribution the characterisation of H35DEMO chips and results of the very first beam test measurements of the monolithic CMOS matrices with high energetic pions at CERN SPS will be presented.

  8. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  9. Silicon Germanium Alloy Photovoltaics for 1.06 Micron Wireless Power Transmission Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase I SBIR effort, Structured Materials Industries, Inc. (SMI)will design, fabricate, and test more efficient photovoltaics for 1.06 micron wavelength...

  10. Mid-IR fiber optic light source around 6 micron through parametric wavelength translation

    CERN Document Server

    Barh, A; Varshney, R K; Pal, B P; Sanghera, J; Shaw, L B; Aggarwal, I D

    2014-01-01

    We report numerically designed highly nonlinear all glass chalcogenide microstructured optical fiber for efficient generation of light around 6 micron through degenerate four wave mixing by considering continuous wave CO laser of 5 to 10 Watts power emitting at 5.6 micron as the pump. By tuning the pump wavelength, pump power, fiber dispersion and nonlinear properties, narrow and broad band mid-IR all-fiber light source could be realized. Parametric amplification of more than 20 decibel is achievable for the narrow band source at 6.46 micron with a maximum power conversion efficiency of 33 percent while amplification of 22 decibel is achievable for a B-band source over the wavelength range of 5 to 6.3 micron with a conversion efficiency of 40 percent.

  11. Nimbus-5/THIR Level 1 Brightness Temperature at 6.7 microns V001

    Data.gov (United States)

    National Aeronautics and Space Administration — The Nimbus-5 Temperature-Humidity Infrared Radiometer (THIR) Level 1 Brightness Temperature at 6.7 microns data product contains radiances expressed in units of...

  12. Nimbus-5/THIR Level 1 Brightness Temperature at 11.5 microns V001

    Data.gov (United States)

    National Aeronautics and Space Administration — The Nimbus-5 Temperature-Humidity Infrared Radiometer (THIR) Level 1 Brightness Temperature at 11.5 microns data product contains radiances expressed in units of...

  13. Single-Frequency Semiconductor Lasers Operating at 1.5 and 2.0 microns Project

    Data.gov (United States)

    National Aeronautics and Space Administration — While conventional injection seeding sources (such as DFB diode lasers and rare-earth doped solid-state microchip lasers) are available at 1.5 microns, these sources...

  14. High Power Narrow Linewidth 1.26 Micron Ho-Doped Fiber Amplifier Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal is for the development of an innovative, high power, and extremely reliable 1.26-micron Ho-doped fluoride fiber amplifier. The proposed fiber amplifier...

  15. Tunable Narrow Linewidth, Low Noise 2.05 Micron Single Frequency Seeder Laser Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose an all-fiber based 2.05-micron single frequency, narrow linewidth seeder laser with 10 nm tuning range and 5GHz frequency modulation for next generation...

  16. Bench-scale testing of a micronized magnetite, fine-coal cleaning process

    Energy Technology Data Exchange (ETDEWEB)

    Suardini, P.J. [Custom Coals, International, Pittsburgh, PA (United States)

    1995-11-01

    Custom Coals, International has installed and is presently testing a 500 lb/hr. micronized-magnetite, fine-coal cleaning circuit at PETC`s Process Research Facility (PRF). The cost-shared project was awarded as part of the Coal Preparation Program`s, High Efficiency Preparation Subprogram. The project includes design, construction, testing, and decommissioning of a fully-integrated, bench-scale circuit, complete with feed coal classification to remove the minus 30 micron slimes, dense medium cycloning of the 300 by 30 micron feed coal using a nominal minus 10 micron size magnetite medium, and medium recovery using drain and rinse screens and various stages and types of magnetic separators. This paper describes the project circuit and goals, including a description of the current project status and the sources of coal and magnetite which are being tested.

  17. Nimbus-6/THIR Level 1 Brightness Temperature at 11.5 microns V001

    Data.gov (United States)

    National Aeronautics and Space Administration — The Nimbus-6 Temperature-Humidity Infrared Radiometer (THIR) Level 1 Brightness Temperature at 11.5 microns data product contains radiances expressed in units of...

  18. HIRDLS/Aura Level 3 Extinction at 12.1 Microns Zonal Fourier Coefficients V007

    Data.gov (United States)

    National Aeronautics and Space Administration — The "HIRDLS/Aura Level 3 Extinction at 12.1 Microns Zonal Fourier Coefficients" version 7 data product (H3ZFC12MEXT) contains the entire mission (~3 years) of HIRDLS...

  19. HIRDLS/Aura Level 3 Extinction at 8.3 Microns Zonal Fourier Coefficients V007

    Data.gov (United States)

    National Aeronautics and Space Administration — The "HIRDLS/Aura Level 3 Extinction at 8.3 Microns Zonal Fourier Coefficients" version 7 data product (H3ZFC8MEXT) contains the entire mission (~3 years) of HIRDLS...

  20. Tunable Single Frequency 2.05 Micron Fiber Laser Using New Ho-Doped Fiber Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, we propose to demonstrate and build a widely tunable, narrow linewidth, single frequency fiber laser near 2.05 micron by developing an innovative...

  1. Tunable Single Frequency 2.054 Micron Fiber Laser Using New Ho-Doped Fiber Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, we propose to demonstrate and build a near 2 micron widely tunable, narrow linewidth, single frequency fiber laser by developing an innovative...

  2. Frequency-Locked Single-Frequency Fiber Laser at 2 Micron Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Frequency-locked single-frequency 2 micron fiber laser is proposed to be used for airborne/spaceborne coherent lidar measurements, i.e., Active Sensing of CO2...

  3. Efficient High Power 2 micron Tm3+-Doped Fiber Laser Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal is for the development of new Tm3+ doped germanate glass fibers for efficient high power 2-micron fiber lasers capable of generating an output power of...

  4. Efficient high power 2 micron Tm3+-Doped Fiber Laser Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal is for the development of new Tm3+ doped germanate glass fibers for efficient high power 2 micron fiber lasers capable of generating an output power of...

  5. 2-Micron Pulsed Direct Detection IPDA Lidar for Atmospheric CO2 Measurement

    Science.gov (United States)

    Yu, Jirong; Petros, Mulugeta; Refaat, Tamer; Reithmaier, Karl; Remus, Ruben; Singh, Upendra; Johnson, Will; Boyer, Charlie; Fay, James; Johnston, Susan; hide

    2014-01-01

    A 2-micron high energy, pulsed Integrated Path Differential Absorption (IPDA) lidar has been developed for atmospheric CO2 measurements. Development of this lidar heavily leverages the 2-micron laser technologies developed in LaRC over the last decade. The high pulse energy, direct detection lidar operating at CO2 2-micron absorption band provides an alternate approach to measure CO2 concentrations. This new 2-micron pulsed IPDA lidar has been flown in spring of this year for total ten flights with 27 flight hours. It is able to make measurements of the total amount of atmospheric CO2 from the aircraft to the ground or cloud. It is expected to provide high-precision measurement capability by unambiguously eliminating contamination from aerosols and clouds that can bias the IPDA measurement.

  6. Nimbus-6/THIR Level 1 Brightness Temperature at 6.7 microns V001

    Data.gov (United States)

    National Aeronautics and Space Administration — The Nimbus-6 Temperature-Humidity Infrared Radiometer (THIR) Level 1 Brightness Temperature at 6.7 microns data product contains radiances expressed in units of...

  7. Silicon Germanium Alloy Photovoltaics for 1.06 Micron Wireless Power Transmission Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Structured Materials Industries, Inc. proposes to develop SiGe photovoltaic technology that matches the Nd:YAG wavelength of 1.06 micron for insertion in future...

  8. Development of Double-Pulsed Two-Micron Laser for Atmospheric Carbon Dioxide Measurements

    Science.gov (United States)

    Petros, Mulugeta; Singh, Upendra N.; Yu, Jirong; Refaat, Tamer F.

    2017-01-01

    A CO2 lidar double-pulse two-micron high-energy transmitter, tuned to on- and off-line absorption wavelengths, has been developed. Transmitter operation and performance has been verified on ground and airborne platform.

  9. In Vitro Permeation of Micronized and Nanonized Alaptide from Semisolid Formulations

    Directory of Open Access Journals (Sweden)

    Radka Opatrilova

    2013-01-01

    Full Text Available This study is focused on in vitro permeation of the original Czech compound, a skin/mucosa tissue regeneration promoter, known under the international nonproprietary name “alaptide,” in micronized and nanonized forms. Alaptide showed a great potential for local applications for treatment and/or regeneration of the injured skin. The above mentioned technological modifications influence the permeation of alaptide through artificial or biological membranes, such as PAMPA or skin. The permeation of micronized and nanonized form of alaptide formulated to various semisolid pharmaceutical compositions through full-thickness pig ear skin using a Franz cell has been investigated in detail. In general, it can be concluded that the nanonized alaptide permeated through the skin less than the micronized form; different observations were made for permeation through the PAMPA system, where the micronized form showed lower permeation than the nanonized alaptide.

  10. Preparation and Characterization of Micronized Artemisinin via a Rapid Expansion of Supercritical Solutions (RESS Method

    Directory of Open Access Journals (Sweden)

    Xiaonan Zhang

    2012-04-01

    Full Text Available The particle sizes of pharmaceutical substances are important for their bioavailability. Bioavailability can be improved by reducing the particle size of the drug. In this study, artemisinin was micronized by the rapid expansion of supercritical solutions (RESS. The particle size of the unprocessed white needle-like artemisinin particles was 30 to 1200 µm. The optimum micronization conditions are determined as follows: extraction temperature of 62 °C, extraction pressure of 25 MPa, precipitation temperature 45 °C and nozzle diameter of 1000 μm. Under the optimum conditions, micronized artemisinin with a (mean particle size MPS of 550 nm is obtained. By analysis of variance (ANOVA, extraction temperature and pressure have significant effects on the MPS of the micronized artemisinin. The particle size of micronized artemisinin decreased with increasing extraction temperature and pressure. Moreover, the SEM, LC-MS, FTIR, DSC and XRD allowed the comparison between the crystalline initial state and the micronization particles obtained after the RESS process. The results showed that RESS process has not induced degradation of artemisinin and that processed artemisinin particles have lower crystallinity and melting point. The bulk density of artemisinin was determined before and after RESS process and the obtained results showed that it passes from an initial density of 0.554 to 0.128 g·cm−3 after the processing. The decrease in bulk density of the micronized powder can increase the liquidity of drug particles when they are applied for medicinal preparations. These results suggest micronized powder of artemisinin can be of great potential in drug delivery systems.

  11. Solid methane on Triton and Pluto - 3- to 4-micron spectrophotometry

    Science.gov (United States)

    Spencer, John R.; Buie, Marc W.; Bjoraker, Gordon L.

    1990-01-01

    Methane has been identified in the Pluto/Charon system on the basis of absorption features in the reflectance spectrum at 1.5 and 2.3 microns; attention is presently given to observations of a 3.25 micron-centered deep absorption feature in Triton and Pluto/Charon system reflectance spectra. This absorption may indicate the presence of solid methane, constituting either the dominant surface species or a mixture with a highly transparent substance, such as N2 frost.

  12. 2-Micron Laser Transmitter for Coherent CO2 DIAL Measurement

    Science.gov (United States)

    Singh, Upendra N.; Bai, Yingxin; Yu, Jirong

    2009-01-01

    Carbon dioxide (CO2) has been recognized as one of the most important greenhouse gases. It is essential for the study of global warming to accurately measure the CO2 concentration in the atmosphere and continuously record its variation. A high repetition rate, highly efficient, Q-switched 2-micron laser system as the transmitter of a coherent differential absorption lidar for CO2 measurement has been developed in NASA Langley Research Center. This laser system is capable of making a vertical profiling of CO2 from ground and column measurement of CO2 from air and space-borne platform. The transmitter is a master-slave laser system. The master laser operates in a single frequency, either on-line or off-line of a selected CO2 absorption line. The slave laser is a Q-switched ring-cavity Ho:YLF laser which is pumped by a Tm:fiber laser. The repetition rate can be adjusted from a few hundred Hz to 10 kHz. The injection seeding success rate is from 99.4% to 99.95%. For 1 kHz operation, the output pulse energy is 5.5mJ with the pulse length of 50 ns. The optical-to-optical efficiency is 39% when the pump power is 14.5W. A Ho:YLF laser operating in the range of 2.05 micrometers can be tuned over several characteristic lines of CO2 absorption. Experimentally, a diode pumped Ho:Tm:YLF laser has been successfully used as the transmitter of coherent differential absorption lidar for the measurement of CO2 with a repetition rate of 5 Hz and pulse energy of 75 mJ. For coherent detection, high repetition rate is required for speckle averaging to obtain highly precise measurements. However, a diode pumped Ho:Tm:YLF laser can not operate in high repetition rate due to the large heat loading and up-conversion. A Tm:fiber laser pumped Ho:YLF laser with low heat loading can operate in high repetition rate. A theoretical model has been established to simulate the performance of Tm:fiber laser pumped Ho:YLF lasers. For continuous wave (CW) operation, high pump intensity with small beam

  13. sCMOS detector for imaging VNIR spectrometry

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  14. Integration of complex optical functionality in a production CMOS process

    Science.gov (United States)

    Gunn, Lawrence C., III

    Optical functionality has been developed within the confines of an existing CMOS process. As of this writing, 10Gigabit modulators, electrically tunable optical filters, waveguides, and grating coupler technology have been successfully implemented alongside the existing transistors in the Freescale Hip7SOI process. This technology will be used to manufacture high bandwidth optical interconnections directly on silicon chips, allowing a new type of network and computing infrastructure to be developed. This work is covered in two distinct phases. First, the exploratory work done to gain experience with high index contrast silicon waveguides primarily served to uncover challenges related with simulation of these devices, and with the practical limitations of efficiently coupling the resulting waveguide devices with the outside world. The second phase began as the grating coupler emerged to address the coupling challenge. It became feasible to conceive of a commercially viable technology based on silicon photonics. The coupler has been evolved to a high level, currently achieving coupling loss of less than 1dB. Once the light is on chip, filtering and modulation technology are implemented. The reverse-biased plasma dispersion modulator has a 3dB roll-off of 10GHz, and an insertion loss less than 5dB. Optical filters based on ring resonators, arrayed waveguide gratings, and interleavers have all been implemented, often with world record performance, and many of the devices have been made electronically tunable to compensate for manufacturing variations and environmental excursions. Finally, circuitry has been designed and constructed on the same die with the optical functionality, fully demonstrating the ability to achieve monolithic integration of these devices.

  15. Integrating silicon photonic interconnects with CMOS: Fabrication to architecture

    Science.gov (United States)

    Sherwood, Nicholas Ramsey

    While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

  16. Advanced 2-micron Solid-state Laser for Wind and CO2 Lidar Applications

    Science.gov (United States)

    Yu, Jirong; Trieu, Bo C.; Petros, Mulugeta; Bai, Yingxin; Petzar, Paul J.; Koch, Grady J.; Singh, Upendra N.; Kavaya, Michael J.

    2006-01-01

    Significant advancements in the 2-micron laser development have been made recently. Solid-state 2-micron laser is a key subsystem for a coherent Doppler lidar that measures the horizontal and vertical wind velocities with high precision and resolution. The same laser, after a few modifications, can also be used in a Differential Absorption Lidar (DIAL) system for measuring atmospheric CO2 concentration profiles. The world record 2-micron laser energy is demonstrated with an oscillator and two amplifiers system. It generates more than one joule per pulse energy with excellent beam quality. Based on the successful demonstration of a fully conductive cooled oscillator by using heat pipe technology, an improved fully conductively cooled 2-micron amplifier was designed, manufactured and integrated. It virtually eliminates the running coolant to increase the overall system efficiency and reliability. In addition to technology development and demonstration, a compact and engineering hardened 2-micron laser is under development. It is capable of producing 250 mJ at 10 Hz by an oscillator and one amplifier. This compact laser is expected to be integrated to a lidar system and take field measurements. The recent achievements push forward the readiness of such a laser system for space lidar applications. This paper will review the developments of the state-of-the-art solid-state 2-micron laser.

  17. The Carnegie Hubble Program: The Leavitt Law at 3.6 microns and 4.5 microns in the Large Magellanic Cloud

    Science.gov (United States)

    Scowcroft, Victoria; Freedman, Wendy L.; Madore, Barry F.; Monson, Andrew J.; Persson, S. E.; Seibert, Mark; Rigby, Jane R.; Sturch, Laura

    2011-01-01

    The Carnegie Hubble Program (CHP) is designed to improve the extragalactic distance scale using data from the post-cryogenic era of Spitzer. The ultimate goal is a determination of the Hubble constant to an accuracy of 2%. This paper is the first in a series on the Cepheid population of the Large Magellanic Cloud, and focuses on the period-luminosity relations (Leavitt laws) that will be used, in conjunction with observations of Milky Way Cepheids, to set the slope and zero-point of the Cepheid distance scale in the mid-infrared. To this end, we have obtained uniformly-sampled light curves for 85 LMC Cepheids, having periods between 6 and 140 days. Period- luminosity and period-color relations are presented in the 3.6 micron and 4.5 micron bands. We demonstrate that the 3.6 micron band is a superb distance indicator. The cyclical variation of the [3.6]-[4.5] color has been measured for the first time. We attribute the amplitude and phase of the color curves to the dissociation and recombination of CO molecules in the Cepheid s atmosphere. The CO affects only the 4.5 micron flux making it a potential metallicity indicator.

  18. A CMOS 128-APS linear array integrated with a LVOF for highsensitivity and high-resolution micro-spectrophotometry

    NARCIS (Netherlands)

    Liu, C.; Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

    A linear array of 128 Active Pixel Sensors has been developed in standard CMOS technology and a Linear Variable Optical Filter (LVOF) is added using CMOS-compatible post-process, resulting in a single chip highly-integrated highresolution microspectrometer. The optical requirements imposed by the

  19. A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

    NARCIS (Netherlands)

    Nauta, Bram; Venes, Ardie G.W.

    1995-01-01

    A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance

  20. Optimization Design Method for the CMOS-type Capacitive Micro-Machined Ultrasonic Transducer

    Directory of Open Access Journals (Sweden)

    D. Y. Chiou

    2011-12-01

    Full Text Available In this study, an integrated modeling technique for characterization and optimization design of the complementary metal-oxide-semiconductor (CMOS capacitive micro-arrayed ultrasonic transducer (pCMOS-CMUT is presented. Electromechanical finite element simulations are performed to investigate its operational characteristics, such as the collapse voltage and the resonant frequency. Both the numerical and experimental results are in good agreement. In order to simultaneously customize the resonant frequency and minimize the collapse voltage, the genetic algorithm (GA is applied to optimize dimensional parameters of the transducer. From the present results, it is concluded that the FE/GA coupling approach provides another efficient numerical tool for multi-objective design of the pCMOS-CMUT.

  1. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Ristic, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

  2. TCAD simulations of High-Voltage-CMOS Pixel structures for the CLIC vertex detector

    CERN Document Server

    Buckland, Matthew Daniel

    2016-01-01

    The requirements for precision physics and the experimental conditions at CLIC result in stringent constraints for the vertex detector. Capacitively coupled active pixel sensors with 25 μm pitch implemented in a commercial 180 nm High-Voltage CMOS (HV-CMOS) process are currently under study as a candidate technology for the CLIC vertex detector. Laboratory calibration measurements and beam tests with prototypes are complemented by detailed TCAD and electronic circuit simulations, aiming for a comprehensive understanding of the signal formation in the HV-CMOS sensors and subsequent readout stages. In this note 2D and 3D TCAD simulation results of the prototype sensor, the Capacitively Coupled Pixel Detector version three (CCPDv3), will be presented. These include the electric field distribution, leakage current, well capacitance, transient response to minimum ionising particles and charge-collection.

  3. Recent progress in the development of 3D deep n-well CMOS MAPS

    CERN Document Server

    Traversi, Gianluca; Manazza, Alessia; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Zucca, Stefano; 10.1088/1748-0221/7/02/C02007

    2012-01-01

    In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

  4. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

  5. Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

    Science.gov (United States)

    Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

    2017-06-01

    Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

  6. CMOS Pixel Spectroscopic Circuits for Cd(ZnTe Gamma Ray Imagers

    Directory of Open Access Journals (Sweden)

    Hatzistratis D.

    2016-01-01

    Full Text Available A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

  7. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    CERN Document Server

    Rivetti, A; Wyss, J; Bisello, D; Costa, M; Kloukinas, K; Demaria, N; Pantano, D; Rousset, J; Battaglia, M; Mansuy, C; Potenza, A; Ikemoto, Y; Giubilato, P; Chalmet, P; Mugnier, H; Silvestrin, L; Marchioro, A

    2013-01-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Omega cm, which is at least one order of magnitude greater than the typical value (1-10 Omega cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported. (C) 2013 Elsevier B.V. All rights reserved

  8. Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

    Directory of Open Access Journals (Sweden)

    Worapong Tangsrirat

    2014-01-01

    Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

  9. Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

    Directory of Open Access Journals (Sweden)

    S. M. Rezaul Hasan

    2002-01-01

    Full Text Available This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

  10. Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor

    Science.gov (United States)

    Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

    2014-09-01

    A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35 μm CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35 dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 Ω-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10 kΩ, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

  11. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  12. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Science.gov (United States)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  13. Design and Simulation of 1-bit Sigma Delta ADC in 0.18um CMOS Technology

    OpenAIRE

    Jaydip H. Chaudhari

    2013-01-01

    This paper presents the design of a first order single bit Sigma-Delta ADC which is realized using CMOS technology. In this paper, a first Order Sigma-Delta ADC is implemented in a standard 0.18um CMOS technology. The Design and Simulation of the Modulator is done using Mentor Graphics Tool. First order single bit Sigma Delta ADC Modulator is implemented using ±1.8 power supply and simulation results are plotted using Mentor Graphics Tool. This paper firstly elaborate about ADC types and Clas...

  14. Fabrication and Measurement of a Suspended Nanochannel Microbridge Resonator Monolithically Integrated with CMOS Readout Circuitry

    Directory of Open Access Journals (Sweden)

    Gabriel Vidal-Álvarez

    2016-03-01

    Full Text Available We present the fabrication and characterization of a suspended microbridge resonator with an embedded nanochannel. The suspended microbridge resonator is electrostatically actuated, capacitively sensed, and monolithically integrated with complementary metal-oxide-semiconductor (CMOS readout circuitry. The device is fabricated using the back end of line (BEOL layers of the AMS 0.35 μm commercial CMOS technology, interconnecting two metal layers with a contact layer. The fabricated device has a 6 fL capacity and has one of the smallest embedded channels so far. It is able to attain a mass sensitivity of 25 ag/Hz using a fully integrable electrical transduction.

  15. Wireless power transmission for biomedical implants: The role of near-zero threshold CMOS rectifiers.

    Science.gov (United States)

    Mohammadi, Ali; Redoute, Jean-Michel; Yuce, Mehmet R

    2015-01-01

    Biomedical implants require an electronic power conditioning circuitry to provide a stable electrical power supply. The efficiency of wireless power transmission is strongly dependent on the power conditioning circuitry specifically the rectifier. A cross-connected CMOS bridge rectifier is implemented to demonstrate the impact of thresholds of rectifiers on wireless power transfer. The performance of the proposed rectifier is experimentally compared with a conventional Schottky diode full wave rectifier over 9 cm distance of air and tissue medium between the transmitter and receiver. The output voltage generated by the CMOS rectifier across a 1 KΩ resistive load is around twice as much as the Schottky rectifier.

  16. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  17. A Wafer scale active pixel CMOS image sensor for generic x-ray radiology

    Science.gov (United States)

    Scheffer, Danny

    2007-03-01

    This paper describes a CMOS Active Pixel Image Sensor developed for generic X-ray imaging systems using standard CMOS technology and an active pixel architecture featuring low noise and a high sensitivity. The image sensor has been manufactured in a standard 0.35 μm technology using 8" wafers. The resolution of the sensor is 3360x3348 pixels of 40x40 μm2 each. The diagonal of the sensor measures little over 190 mm. The paper discusses the floor planning, stitching diagram, and the electro-optical performance of the sensor that has been developed.

  18. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  19. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    CERN Document Server

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  20. Novel Si-Ge-C Superlattices for More than Moore CMOS

    Science.gov (United States)

    2016-03-31

    superlattices strained to SiGe relaxed buffer layers [4]; and compound semiconductors such as InP [5] and InGaAs [6] grown in silicon nano-trenches. The...future Si-Ge-C SLs are high- quantum efficiency photo-diodes in CMOS pixels, for the visible range, as well as for the Short-Wavelength Infra-Red (SWIR...Novel Si-Ge-C Superlattices for “More than Moore” CMOS Lynn Forester, Carlos J. Augusto, Pedro C. Diniz Quantum Semiconductor LLC 4340 Stevens

  1. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  2. Imaging performance comparison between CMOS and sCMOS detectors in a vibration test on large areas using digital holographic interferometry

    Science.gov (United States)

    Flores-Morenoa, J. M.; Torre I., Manuel H. De la; Aguayo, Daniel D.; Fernando Mendoza, S.

    2014-05-01

    A comparison of the interferometric imaging performance of two different cameras during a vibration study is presented. One of the cameras has a high speed CMOS sensor and the second one uses a high resolution (scientific) sCMOS sensor. This comparison is based on the interferometric response as a merit parameter of these sensors which is not a conventional procedure. Even when the current standard for image quality is on the signal to noise ratio calculations, an interferometric test to evaluate the fringe pattern visibility is equivalent to the contrast to noise ratio value. An out of plane digital holographic interferometer is used to test each camera once at the time with the same experimental conditions. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The sample is deformed by means of a controlled vibration induced by a tip ended linear step motor. Results from each camera are presented as the retrieved optical phase during the vibration. Finally, some conclusions based on the post processed images are presented suggesting a smoother optical phase obtained with the sCMOS camera.

  3. Development of megapixel HgCdTe detector arrays with 15 micron cutoff

    Science.gov (United States)

    Forrest, William J.; McMurtry, Craig W.; Dorn, Meghan; Pipher, Judith; Cabrera, Mario S.

    2016-10-01

    I. HistoryHgCdTe is a versatile II-VI semiconductor with a direct-bandgap tunable via the Hg:Cd ratio. Hg:Cd ratio = 53:47 (2.5 micron cutoff) was used on the NICMOS instrument on HST and the 2MASS. Increasing Hg:Cd ratio to 70:30 leads to a 5.4 micron cutoff, utilized in NEOWISE and many JWST instruments. Bailey, Wu et al. (1998) motivated extending this technology to 10 microns and beyond. Bacon, McMurtry et al. (2003, 2004) indicated significant progress toward this longwave (LW) goal.Warm-Spitzer has pioneered passive cooling to below 30 K in space, enabling the JWST mission.II. CurrentNASA's proposed NEOcam mission selected HgCdTe with a 10.6 micron cutoff because it promises natural Zodiacal background limited sensitivity with modest cooling (40 K). Teledyne Imaging Systems (TIS) is producing megapixel arrays with excellent performance (McMurtry, Lee, Dorn et al. (2013)) for this mission.III. FutureModest cooling requirements (circa 30 K) coupled with megapixel arrays and LW sensitivity in the thermal IR make HgCdTe attractive for many infrared instruments. For instance, the spectral signature of a terrestrial planet orbiting in the habitable zone of a nearby star will be the deep and wide absorption by CO_2 centered at 15 microns (Seager and Deming, 2010). LW instruments can enhance Solar System missions, such as exploration of the Enceladus geysers (Spencer, Buratti et al. 2006). Passive cooling will be adequate for these missions. Modern ground-based observatories will benefit from infrared capability out to the N band (7.5-13.6 microns). The required detector temperatures (30-40 K) are easily achievable using commercially available mechanical cryo-coolers (refrigerators).IV. Progress to dateTIS is developing megapixel HgCdTe arrays sensitive out to 15 microns under the direction of the University of Rochester. As a first step, we have produced arrays with a 13 micron cutoff. The initial measurements indicate very promising performance. We will present the

  4. Penetration of sub-micron particles into dentinal tubules using ultrasonic cavitation.

    Science.gov (United States)

    Vyas, N; Sammons, R L; Pikramenou, Z; Palin, W M; Dehghani, H; Walmsley, A D

    2017-01-01

    Functionalised silica sub-micron particles are being investigated as a method of delivering antimicrobials and remineralisation agents into dentinal tubules. However, their methods of application are not optimised, resulting in shallow penetration and aggregation. The aim of this study is to investigate the impact of cavitation occurring around ultrasonic scalers for enhancing particle penetration into dentinal tubules. Dentine slices were prepared from premolar teeth. Silica sub-micron particles were prepared in water or acetone. Cavitation from an ultrasonic scaler (Satelec P5 Newtron, Acteon, France) was applied to dentine slices immersed inside the sub-micron particle solutions. Samples were imaged with scanning electron microscopy (SEM) to assess tubule occlusion and particle penetration. Qualitative observations of SEM images showed some tubule occlusion. The particles could penetrate inside the tubules up to 60μm when there was no cavitation and up to ∼180μm when there was cavitation. The cavitation bubbles produced from an ultrasonic scaler may be used to deliver sub-micron particles into dentine. This method has the potential to deliver such particles deeper into the dentinal tubules. Cavitation from a clinical ultrasonic scaler may enhance penetration of sub-micron particles into dentinal tubules. This can aid in the development of novel methods for delivering therapeutic clinical materials for hypersensitivity relief and treatment of dentinal caries. Copyright © 2016 Elsevier Ltd. All rights reserved.

  5. 2-Micron Coherent Doppler Lidar Instrument Advancements for Tropospheric Wind Measurement

    Science.gov (United States)

    Petros, Mulugeta; Singh, U. N.; Yu, J.; Kavaya, M. J.; Koch, G.

    2014-01-01

    Knowledge derived from global tropospheric wind measurement is an important constituent of our overall understanding of climate behavior [1]. Accurate weather prediction saves lives and protects properties from destructions. High-energy 2-micron laser is the transmitter of choice for coherent Doppler wind detection. In addition to the eye-safety, the wavelength of the transmitter suitably matches the aerosol size in the lower troposphere. Although the technology of the 2-micron laser has been maturing steadily, lidar derived wind data is still a void in the global weather database. In the last decade, researchers at NASA Langley Research Center (LaRC) have been engaged in this endeavor, contributing to the scientific database of 2-micron lidar transmitters. As part of this effort, an in depth analysis of the physics involved in the workings of the Ho: Tm laser systems have been published. In the last few years, we have demonstrated lidar transmitter with over1Joule output energy. In addition, a large body of work has been done in characterizing new laser materials and unique crystal configurations to enhance the efficiency and output energy of the 2-micron laser systems. At present 2-micron lidar systems are measuring wind from both ground and airborne platforms. This paper will provide an overview of the advancements made in recent years and the technology maturity levels attained.

  6. 2-micron coherent Doppler lidar instrument advancements for tropospheric wind measurement

    Science.gov (United States)

    Petros, Mulugeta; Singh, U. N.; Yu, J.; Kavaya, M. J.; Koch, G.

    2014-10-01

    Knowledge derived from global tropospheric wind measurement is an important constituent of our overall understanding of climate behavior [1]. Accurate weather prediction saves lives and protects properties from destructions. High-energy 2-micron laser is the transmitter of choice for coherent Doppler wind detection. In addition to the eye-safety, the wavelength of the transmitter suitably matches the aerosol size in the lower troposphere. Although the technology of the 2-micron laser has been maturing steadily, lidar derived wind data is still a void in the global weather database. In the last decade, researchers at NASA Langley Research Center (LaRC) have been engaged in this endeavor, contributing to the scientific database of 2-micron lidar transmitters. As part of this effort, an in depth analysis of the physics involved in the workings of the Ho: Tm laser systems have been published. In the last few years, we have demonstrated lidar transmitter with over1Joule output energy. In addition, a large body of work has been done in characterizing new laser materials and unique crystal configurations to enhance the efficiency and output energy of the 2-micron laser systems. At present 2-micron lidar systems are measuring wind from both ground and airborne platforms. This paper will provide an overview of the advancements made in recent years and the technology maturity levels attained.

  7. Easy simulation and design of on-chip inductors in standard CMOS processes

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jørgensen, Allan

    1998-01-01

    This paper presents an approach to CMOS inductor modelling, that allow easy simulation in SPICE-like simulators. A number of test results are presented concerning optimal center hole, inductor area, wire spacing and self-inductance. Finally a comprehensive design guide is provided on how to desig...

  8. Implementation of material decomposition using an EMCCD and CMOS-based micro-CT system

    Science.gov (United States)

    Podgorsak, Alexander R.; Nagesh, S. V. Setlur; Bednarek, Daniel R.; Rudin, Stephen; Ionita, Ciprian N.

    2017-03-01

    This project assessed the effectiveness of using two different detectors to obtain dual-energy (DE) micro-CT data for the carrying out of material decomposition. A micro-CT coupled to either a complementary metal-oxide semiconductor (CMOS) or an electron multiplying CCD (EMCCD) detector was used to acquire image data of a 3D-printed phantom with channels filled with different materials. At any instance, materials such as iohexol contrast agent, water, and platinum were selected to make up the scanned object. DE micro-CT data was acquired, and slices of the scanned object were differentiated by material makeup. The success of the decomposition was assessed quantitatively through the computation of percentage normalized root-mean-square error (%NRMSE). Our results indicate a successful decomposition of iohexol for both detectors (%NRMSE values of 1.8 for EMCCD, 2.4 for CMOS), as well as platinum (%NRMSE value of 4.7). The CMOS detector performed material decomposition on air and water on average with 7 times more %NRMSE, possibly due to the decreased sensitivity of the CMOS system. Material decomposition showed the potential to differentiate between materials such as the iohexol and platinum, perhaps opening the door for its use in the neurovascular anatomical region. Work supported by Toshiba America Medical Systems, and partially supported by NIH grant 2R01EB002873.

  9. A wideband supply modulator for 20MHz RF bandwidth polar PAs in 65nm CMOS

    NARCIS (Netherlands)

    Shrestha, R.; van der Zee, Ronan A.R.; de Graauw, A.J.M.; Nauta, Bram

    2008-01-01

    Abstract A wideband modulator for a 20MHz bandwidth polar modulated PA is presented which achieves a maximum efficiency of 87.5% and a small signal -3dB bandwidth of 285MHz. Realized in 65nm CMOS, it consists of a cascoded nested Miller compensated linear amplifier and a class D switching amplifier.

  10. 1/f Noise Characterization in CMOS Transistors in 0.13μm Technology

    DEFF Research Database (Denmark)

    Citakovic, J.; Stenberg, L J; Andreani, Pietro

    2006-01-01

    Low-frequency noise has been studied on a set of n- and p-channel CMOS transistors fabricated in a 0.13μm technology. Noise measurements have been performed on transistors with different gate lengths operating under wide bias conditions, ranging from weak to strong inversion. Noise origin has been...

  11. A CMOS class-AB transconductance amplifier for switched-capacitor applications

    NARCIS (Netherlands)

    Rijns, J.J.F.; Rijns, J.J.F.; Wallinga, Hans

    1990-01-01

    A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high

  12. CMOS-Compatible PureGaB Ge-on-Si APD pixel arrays

    NARCIS (Netherlands)

    Sammak, A.; Aminian, Mahdi; Nanver, L.K.; Charbon, E.E.E.

    2016-01-01

    Pure gallium and pure boron (PureGaB) Ge-on-Si photodiodes were fabricated in a CMOS compatible process and operated in linear and avalanche mode. Three different pixel geometries with very different area-to-perimeter ratios were investigated in linear arrays of 300 pixels with each a size of 26 ×

  13. High-Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

    CERN Document Server

    Mak, Pui-In

    2012-01-01

    This book presents high-/mixed-voltage analog and radio frequency (RF) circuit techniques for developing low-cost multistandard wireless receivers in nm-length CMOS processes.  Key benefits of high-/mixed-voltage RF and analog CMOS circuits are explained, state-of-the-art examples are studied, and circuit solutions before and after voltage-conscious design are compared. Three real design examples are included, which demonstrate the feasibility of high-/mixed-voltage circuit techniques.    Provides a valuable summary and real case studies of the state-of-the-art in high-/mixed-voltage circuits and systems; Includes novel high-/mixed-voltage analog and RF circuit techniques – from concept to practice; Describes the first high-voltage-enabled mobile-TVRF front-end in 90nm CMOS and the first mixed-voltage full-band mobile-TV Receiver in 65nm CMOS; Demonstrates the feasibility of high-/mixed-voltage circuit techniques with real design examples.  

  14. Sol–gel deposited ceria thin films as gate dielectric for CMOS ...

    Indian Academy of Sciences (India)

    Sol–gel deposited ceria thin films as gate dielectric for CMOS technology. ANIL G KHAIRNAR and ASHOK M MAHAJAN ... tum mechanical effects as the thickness of conventional SiO2 gate insulators is reduced just to a few .... depleting the semiconductor of the mobile carriers and leaving a negative charge in the space. 0.

  15. CMOS-compatible fabrication of metamaterial-based absorbers for the mid-IR spectral range

    NARCIS (Netherlands)

    Karimishahmarvandi, E.; Ghaderi, M.; Wolffenbuttel, R.F.

    2016-01-01

    A CMOS-compatible approach is presented for the fabrication of a wideband mid-IR metamaterial-based absorber on top of a Si3N4 membrane, which contains poly-Si thermopiles. The application is in IR microspectrometers that are intended for implementation in portable microsystem for use in absorption

  16. Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology

    NARCIS (Netherlands)

    Agarwal, Vishal Vishal; Dutta, Satadal; Annema, Anne J.; Hueting, Raymond Josephus Engelbart; Steeneken, P.G.; Nauta, Bram

    2017-01-01

    This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant overlap

  17. TID and SEU performance of a commercial 013 $\\mu$ m CMOS technology

    CERN Document Server

    Hänsler, Kurt; Baldi, S; Faccio, F; Hajdas, W; Marchioro, A

    2004-01-01

    The radiation tolerance of a commercial 0.13 mu m CMOS technology is investigated. Total ionizing dose (TID) effects, on individual transistors, are evaluated up to 30 Mrd. Single event upset (SEU) sensitivity has been measured on a SRAM with a proton beam.

  18. Digitally-assisted analog and RF CMOS circuit design for software-defined radio

    CERN Document Server

    Okada, Kenichi

    2011-01-01

    This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millions of transistors, as well as several real examples from the most recent research results.

  19. Reliability aspects of a radiation detector fabricated by post-processing a standard CMOS chip

    NARCIS (Netherlands)

    Salm, Cora; Blanco Carballo, V.M.; Melai, J.; Schmitz, Jurriaan

    2008-01-01

    This paper describes various reliability concerns of the newly developed INGRID detector. This radiation detector is fabricated by waferscale CMOS post-processing; fresh detectors show excellent performance. Since the microsystems will be used unpackaged they are susceptible to all kinds of

  20. Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

    CERN Document Server

    Nguyen, Cam

    2017-01-01

    This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

  1. Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

    NARCIS (Netherlands)

    Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

    2001-01-01

    Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

  2. Design and fabrication of a CMOS-compatible MHP gas sensor

    Directory of Open Access Journals (Sweden)

    Ying Li

    2014-03-01

    Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  3. A new single-photon avalanche diode in 90nm standard CMOS technology

    NARCIS (Netherlands)

    Karami, M.A.; Gersbach, M.; Yoon, H.J.; Charbon, E.

    2010-01-01

    We report on the first implementation of a single-photon avalanche diode (SPAD) in 90nm complementary metal oxide semiconductor (CMOS) technology. The detector features an octagonal multiplication region and a guard ring to prevent premature edge breakdown using a standard mask set exclusively. The

  4. CMOS upconversion mixer with filterless carrier feedthrough cancelation and output power tuning

    NARCIS (Netherlands)

    Sanchez Gaspariano, Luis Abraham; Annema, Anne J.; Muniz Montero, Carlos; Diaz Sanchez, Alejandro

    2014-01-01

    The synthesis, design and implementation of a CMOS upconversion mixer that both can adjust, by means of a DC voltage control, its output power and that cancels the carrier feedthrough is presented. Aiming at very low cost medical implant applications, a prototype of the architecture was implemented

  5. CMOS VCSEL driver circuit for 25+Gbps/channel short-reach parallel optical links

    Science.gov (United States)

    Shibata, Masumi

    This thesis proposes a new CMOS driver for Vertical Cavity Surface Emitting LASER (VCSEL) diode arrays. A VCSEL is a promising light source for optical communication. However, its threshold voltage (1.5V for a 850-nm VCSEL) exceeds the rated supply voltage of nanoscale CMOS technologies. This makes difficult designing a driver sourcing a modulated current to a VCSELs anode directly, an arrangement suitable for low-cost parallel optical links. To overcome this problem, a combination of analog circuit techniques is proposed including a novel pad shield driving technique. A prototype fabricated in a 65-nm CMOS technology achieved 26-Gb/s bit-rate and 1.80-pJ/b power efficiency with an optical modulation amplitude (OMA) of +1.8dBm and 3.1ps-rms jitter when driving a 850-nm 14Gb/s commercial VCSEL. This is the highest-speed anode-driving CMOS VCSEL driver reported to date. Also it has the best power efficiency and the smallest area (0:024 mm2) amongst anode-driving drivers in any process technology.

  6. A CMOS-compatible high aspect ratio silicon-on-glass in-plane micro-accelerometer

    Science.gov (United States)

    Chae, Junseok; Kulah, Haluk; Najafi, Khalil

    2005-02-01

    This paper presents a post-CMOS-compatible micro-machined silicon-on-glass (SOG) in-plane capacitive accelerometer. The accelerometer is a high aspect ratio structure with a 120 µm thick single-crystal silicon proof-mass and 3.4 µm sense gap, bonded to a glass substrate. It is fabricated using a simple 3-mask, 5-step process, and is fully CMOS compatible. A CMOS switched-capacitor readout circuit and an oversampled Σ-Δ modulator are used to read out capacitance changes from the accelerometer. The CMOS chip is 2.6 × 2.4 mm2 in size, utilizes chopper stabilization and correlated double sampling techniques, has a 106 dB open-loop dynamic range, a low input offset of 370 µV, and can resolve better than 20 aF. The accelerometer system has a measured sensitivity of 40 mV g-1 and input referred noise density of 79 µg Hz-1/2. Using the SOG configuration, a post-CMOS monolithic integration technique is developed. The integration technique utilizes dielectric bridges, silicon islands and the SOG configuration to obtain a simple, robust and post-CMOS-compatible process. Utilizing this technique, an integrated SOG accelerometer has been fabricated using the University of Michigan 3 µm CMOS process.

  7. The use of mechanically activated micronized coal in thermal power engineering

    Directory of Open Access Journals (Sweden)

    Burdukov Anatoliy P.

    2016-01-01

    Full Text Available Coal is one of the main energy resources and development of new promising technologies on its basis is certainly topical. This article discusses the use of new technology of gas and fuel oil replacement by mechanically activated micronized coal in power engineering: ignition and stabilization of pulverized coal flame combustion, as well as gasification of micronized coal in the flow. The new technology coal combustion with two stages of grinding is suggested. Optimization of the scheme of two-stage combustion is calculated. The first experimental data on the combustion process are obtained. The first demonstration tests on gas and heavy oil replacement by micronized coal during boiler ignition were carried out in the real power boiler with the capacity of 320 tons of steam per hour.

  8. Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

    Science.gov (United States)

    Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

    2016-02-01

    Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

  9. Technology for an Experimental Test of Micron Length Scale Interactions on Ultracold Neutrons in Gravitational Eigenstates

    Science.gov (United States)

    Dees, Eric; Young, Albert; Riehn, Robert; Abele, Hartmut; Jenke, Tobias

    2014-09-01

    We have manufactured a new technology for studies of short range interactions on ultracold neutrons in eigenstates of earth's gravitational potential. By using a separated oscillatory fields apparatus in combination with our device (in collaboration with the QBOUNCE experiment at ILL), we hope to probe new sensitivity levels of micron length scale forces by looking for a shift in the resonant frequency of the gravitational states induced by attractor materials with different densities. This technology should permit a direct exploration of ranges near micron scales and produce improved limits on certain Beyond Standard Model interactions, such as from chameleon fields or dimensional compactification.

  10. Hidden Broad Line Seyfert 2 Galaxies in the CfA and 12micron Samples

    OpenAIRE

    Tran, Hien D.

    2001-01-01

    We report the results of a spectropolarimetric survey of the CfA and 12micron samples of Seyfert 2 galaxies (S2s). Polarized (hidden) broad line regions (HBLRs) are confirmed in a number of galaxies, and several new cases (F02581-1136, MCG -3-58-7, NGC 5995, NGC 6552, NGC 7682) are reported. The 12micron S2 sample shows a significantly higher incidence of HBLR (50%) than its CfA counterpart (30%), suggesting that the latter may be incomplete in hidden AGNs. Compared to the non-HBLR S2s, the H...

  11. Measuring charge carrier mobility in photovoltaic devices with micron-scale resolution

    Energy Technology Data Exchange (ETDEWEB)

    Ashraf, A. [Sustainable Energy Technologies Department, Brookhaven National Laboratory, Upton, New York 11973 (United States); Department of Physics and Astronomy, Stony Brook University, Stony Brook, New York 11794 (United States); Dissanayake, D. M. N. M. [Sustainable Energy Technologies Department, Brookhaven National Laboratory, Upton, New York 11973 (United States); Eisaman, M. D., E-mail: meisaman@bnl.gov [Sustainable Energy Technologies Department, Brookhaven National Laboratory, Upton, New York 11973 (United States); Department of Physics and Astronomy, Stony Brook University, Stony Brook, New York 11794 (United States); Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, New York 11794 (United States)

    2015-03-16

    We present a charge-extraction technique, micron-scale charge extraction by linearly increasing voltage, which enables simultaneous spatially resolved measurements of charge carrier mobility and photocurrent in thin-film photovoltaic devices with micron-scale resolution. An intensity-modulated laser with beam diameter near the optical diffraction limit is scanned over the device, while a linear voltage ramp in reverse bias is applied at each position of illumination. We calculate the majority carrier mobility, photocurrent, and number of photogenerated charge carriers from the resulting current transient. We demonstrate this technique on an organic photovoltaic device, but it is applicable to a wide range of photovoltaic materials.

  12. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  13. InGaAs/InGaAsP/InP strained-layer quantum well lasers at about 2 microns

    Science.gov (United States)

    Forouhar, S.; Ksendzov, A.; Larsson, A.; Temkin, H.

    1992-01-01

    The first successful operation of InGaAs strained layer quantum well (Sl-QW) injection lasers at about 2 microns is reported. The threshold current density and the external differential quantum efficiency of 5 microns wide and 800 microns long ridge waveguide lasers were 2.5 kA/sq cm and 6 percent, respectively. The devices had a reverse leakage current of less than 20 micro-A at -1 V indicating epitaxial layers with low defect density.

  14. Efficient ultrasonic grinding: a new technology for micron-sized coal. Final report, September 15, 1979-December 14, 1980

    Energy Technology Data Exchange (ETDEWEB)

    Tarpley, W.B. Jr.; Howard, P.L.; Moulder, G.R.

    1981-01-01

    To burn coal most efficiently and cleanly, much smaller particle sizes are needed than can now be ground economically. This project was performed to demonstrate the technical feasibility of using ultrasonics to enhance grinding below the standard plant grind of 75 microns, and to extrapolate from this laboratory work the ultrasonic energy requirements for production use. Successively improved laboratory arrays demonstrated a repeatable production of particulates from 2000-micron coal to the desired size ranges (approximately 35% below 7 microns, 95% below 44 microns) with selective liberation of ash and pyrite inclusions to facilitate removal, with equipment translatable to production use, and the possibility of only 37 kwh/ton energy input requirement.

  15. Reduction of NO[sub x] emissions for a 175-MWe boiler by micronized coal reburning

    Energy Technology Data Exchange (ETDEWEB)

    Daugherty, E.D.; Bradshaw, D.T.; Butler, T.F.; Kazemersky, P.M. (Tennessee Valley Authority, Chattanooga, TN (United States))

    1993-01-01

    The Tennessee Valley Authority (TVA) has been selected for the Department of Energy's (DOE's) Clean Coal Technology IV program to demonstrate Micronized Coal Reburn technology for control of nitrogen oxide (NO[sub x]) emissions on a 175 MWe wall-fired steam generator at its Shawnee Fossil Plant. TVA has selected MicroFuel Division of Fuller Power Corporation as the prime contractor for the project and partner in the commercialization of this technology. The project will demonstrate the technology with which Microfuel can produce micro fine coal. This retrofit demonstration is expected to decrease NO[sub x] emissions by 50 to 60 percent. Up to 30 percent of the total fuel fired in the furnace will be micronized coal injected in the upper furnace creating a fuel-rich reburn zone. Overfire will be injected above the reburn zone at high velocity for good furnace gas mixing above the reburn zone to ensure complete combustion. TVA Shawnee Steam Plant, comprised of 10 units of 175-MW[sub e] each, is indicative of a large portion of boilers in TVA's and the nation's utility operating base. Micronized coal Reburn technology compares favourably with other NO[sub x] control technologies and yet offers additional performance benefits. This paper focuses on Micronized Coal Reburn technology and the schedule and activities for implementing a full-scale demonstration at Shawnee. 6 figs.

  16. Chemigation with micronized sulfur rapidly reduces soil pH in northern highbush blueberry

    Science.gov (United States)

    Northern highbush blueberry is adapted to low soil pH in the range of 4.5–5.5. When pH is higher, soil is usually acidified by incorporating elemental sulfur (S) prior to planting. A study was conducted to determine the potential of applying micronized S by chemigation through the drip system to red...

  17. Bragg diffraction from sub-micron particles isolated by optical tweezers

    Energy Technology Data Exchange (ETDEWEB)

    Gao, Yuan, E-mail: ygao0709@anl.gov; Harder, Ross; Southworth, Stephen; Guest, Jeffrey; Ocola, Leonidas; Young, Linda [Argonne National Laboratory, 9700 South Cass Avenue, Argonne, IL 60439 (United States); Scherer, Norbert; Yan, Zijie [Department of Chemistry, University of Chicago, Chicago, IL 60637 (United States); Pelton, Matthew [Department of Physics, University of Maryland, Baltimore County, MD 21250 (United States)

    2016-07-27

    We describe an apparatus using dynamic holographic optical tweezers which is capable of trapping and aligning a single micron scale anisotropic ZnO particle for x-ray Bragg diffraction experiments. The optical tweezers demonstrate enough stability to perform coherent x-ray diffraction imaging.

  18. Observation of Shapiro-steps in AFM-plought micron-size YBCO planar construction

    CSIR Research Space (South Africa)

    Elkaseh, AAO

    2009-01-01

    Full Text Available Using an Atomic Force Microscope (AFM), micron size planar constriction type junctions was successfully ploughed on YBa2Cu3O7-x thin films. The 100 nanometer (nm) thin films are deposited on MgO substrates by an Inverted Cylindrical Magnetron (ICM...

  19. High spatial resolution observations of NGC 7027 with a 10 micron array camera

    Science.gov (United States)

    Arens, J. F.; Lamb, G. M.; Peck, M. C.; Moseley, H.; Hoffmann, W. F.; Tresch-Fienberg, R.; Fazio, G. G.

    1984-01-01

    First observations of a planetary nebula with an infrared charge injection device (CID) array camera are reported. The 10 micron images of NGC 7027 have spatial resolution comparable to that of the highest resolution (less than 2 arcsec) radio aperture-synthesis maps of this source. A much closer correspondence between the mid-infrared and radio appearance of NGC 7027 was found than was known previously, confirming that warm dust is coextensive and well mixed with the gas in the ionized zone. Using maps at three wavelengths, the spatial dependence of the shape of the 8-13 micron spectrum within the nebula is examined. The dip at 9.60 microns is shallowest in regions of enhanced optical extinction (as determined from new images near 4000 and 9000 A obtained with an optical charge coupled device). The 9.60 micron emission is strongest in these same positions. It is shown that the results may be explained not by silicate absorption, but by a combination of emission from two distinct grain populations, one of which is also partly responsible for the variation in extinction across the nebula.

  20. PROXIMATE COMPOSITION AND TECHNOLOGICAL CHARACTERISTICS OF DRY PASTA INCORPORATED WITH MICRONIZED CORN PERICARP

    Directory of Open Access Journals (Sweden)

    JOÃO RENATO DE JESUS JUNQUEIRA

    2017-01-01

    Full Text Available Pastas are generally accepted all over the world, mainly because they are versatile, cheap and easy - to - prepare. They are not nutritionally balanced, since they provide mainly carbohydrates. As a result of this, it is important to use ingredients which could improve the nutritional deficiencies, without affecting the technological and sensorial characteristics. This study evaluated the effect of using wheat semolina and micronized corn pericarp (MCP, on the proximate composition, cooking quality and color of spaghetti type pasta. Spaghetti pasta was produced using wheat semolina with the incorporation of micronized corn pericarp, at levels of 0, 10, 20 and 30%. There were no significant differences (p > 0.05 between the formulated samples with regards to the contents of moisture and lipid, cooking time, weight gain and volume increase. As observed, supplementation with micronized corn pericarp presented significant difference on the contents of proteins, minerals, dietary fiber and solid soluble loss of the spaghetti pasta (p < 0.05. With increase in micronized corn pericarp concentration, the color difference became accentuated. The use of MCP appears to be viable, providing a nutritionally enriched product without further impairment on pasta quality.

  1. New silicon photonics integration platform enabled by novel micron-scale bends

    CERN Document Server

    Cherchi, Matteo; Harjanne, Mikko; Kapulainen, Markku; Aalto, Timo

    2013-01-01

    Even though submicron silicon waveguides have been proposed for dense integration of photonic devices, to date the lightwave circuits on the market mainly rely on waveguides with micron-scale core dimensions. These larger waveguides feature easier fabrication, higher reliability and better interfacing to optical fibres. Single-mode operation with large core dimensions is obtained with low lateral refractive index contrast. Hence, the main limitation in increasing the level of integration and in reducing the cost of micron-scale waveguide circuits is their mm- to cm-scale minimum bending radius. Fortunately, single-mode rib waveguides with a micron-scale silicon core can be locally transformed into multi-mode strip waveguides that have very high lateral index contrast. Here we show how Euler spiral bends realized with these waveguides can have bending radii below 10 {\\mu}m and losses below 0.02 dB/90{\\deg} for the fundamental mode, paving way for a novel densely integrated platform based on micron-scale wavegu...

  2. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  3. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    Science.gov (United States)

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

  4. Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

    Science.gov (United States)

    Deleonibus, S.

    2006-12-01

    Since the end of the last millenium, the microelectronics industry has been facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power consumption are reviewed. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (Ge, diamond/graphite carbon, HiK, ...), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For example, the association of C-diamond with HiK, as a combination for new functionalized Buried Insulators, will bring new ways of improving short channel effects and suppress self-heating. Because of the low parasitics required to obtain high performance circuits, alternative devices will hardly compete against logic CMOS.

  5. A comparison of film and 3 digital imaging systems for natural dental caries detection: CCD, CMOS, PSP and film

    Energy Technology Data Exchange (ETDEWEB)

    Han, Won Jeong [Dankook University College of Medicine, Seoul (Korea, Republic of)

    2004-03-15

    To evaluate the diagnostic accuracy of occlusal and proximal caries detection using CCD, CMOS, PSP and film system. 32 occlusal and 30 proximal tooth surfaces were radiographed under standardized conditions using 3 digital systems; CCD (CDX-2000HQ, Biomedysis Co., Seoul, Korea), CMOS (Schick, Schick Inc., Long Island, USA), PSP (Digora FMX, Orion Co./Soredex, Helsinki, Finland) and 1 film system (Kodak Insight, Eastman Kodak, Rochester, USA). 5 observers examined the radiographs for occlusal and proximal caries using a 5-point confidence scale. The presence of caries was validated histologically and radiographically. Diagnostic accuracy was evaluated using ROC curve areas (AZ). Analysis using ROC curves revealed the area under each curve which indicated a diagnostic accuracy. For occlusal caries, Kodak Insight film had an Az of 0.765, CCD one of 0.730, CMOS one of 0.742 and PSP one of 0.735. For proximal caries, Kodak Insight film had an Az of 0.833, CCD one of 0.832, CMOS one of 0.828 and PSP one of 0.868. No statistically significant difference was noted between any of the imaging modalities. CCD, CMOS, PSP and film performed equally well in the detection of occlusal and proximal dental caries. CCD, CMOS and PSP-based digital images provided a level of diagnostic performance comparable to Kodak Insight film.

  6. A low power 3.125 Gbps CMOS analog equalizer for serial links

    Science.gov (United States)

    Hao, Ju; Yumei, Zhou; Yishu, Jiao

    2010-11-01

    A CMOS analog equalizer is designed to meet the different high speed communication specifications, such as USB 2.0, PCI-E and rapid IO. The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero, so that the circuit can change its response accordingly as the channel characteristic alters. In order to balance the parasitic capacitors in the internal point, symmetric switches are addressed to generate the equal load for differential signals. A prototype chip was fabricated in 0.13-μm 1P8M mix-signal CMOS technology. The actual area is 0.49 × 0.5 mm2, and the analog equalizer operates up to 3.125 Gbps over 3 m RG-58 coaxial cable and 50 cm FR4-PCB trace. The overall power dissipation is approximately 14.4 mW.

  7. A low power 3.125 Gbps CMOS analog equalizer for serial links

    Energy Technology Data Exchange (ETDEWEB)

    Ju Hao; Zhou Yumei; Jiao Yishu, E-mail: juhao0122@163.com [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2010-11-15

    A CMOS analog equalizer is designed to meet the different high speed communication specifications, such as USB 2.0, PCI-E and rapid IO. The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero, so that the circuit can change its response accordingly as the channel characteristic alters. In order to balance the parasitic capacitors in the internal point, symmetric switches are addressed to generate the equal load for differential signals. A prototype chip was fabricated in 0.13-{mu}m 1P8M mix-signal CMOS technology. The actual area is 0.49 x 0.5 mm{sup 2}, and the analog equalizer operates up to 3.125 Gbps over 3 m RG-58 coaxial cable and 50 cm FR4-PCB trace. The overall power dissipation is approximately 14.4 mW.

  8. High-gain monolithic 3D CMOS inverter using layered semiconductors

    Science.gov (United States)

    Sachid, Angada B.; Desai, Sujay B.; Javey, Ali; Hu, Chenming

    2017-11-01

    We experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide semiconductor N-channel (NMOS) and P-channel (PMOS) MOSFETs, which are sequentially integrated on two levels. The two devices share a common gate. Molybdenum disulphide and tungsten diselenide are used as channel materials for NMOS and PMOS, respectively, with an ON-to-OFF current ratio (ION/IOFF) greater than 106 and electron and hole mobilities of 37 and 236 cm2/Vs, respectively. The voltage gain of the monolithic 3D inverter is about 45 V/V at a supply voltage of 1.5 V and a gate length of 1 μm. This is the highest reported gain at the smallest gate length and the lowest supply voltage for any 3D integrated CMOS inverter using any layered semiconductor.

  9. A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

    Science.gov (United States)

    Kim, Jungsuk

    2016-12-01

    This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

  10. Radiation hardness of two CMOS prototypes for the ATLAS HL-LHC upgrade project

    CERN Document Server

    Huffman, B T; Arndt, K; Bates, R; Benoit, M; Di Bello, F; Blue, A; Bortoletto, D; Buckland, M; Buttar, C; Caragiulo, P; Das, D; Dopke, J; Dragone, A; Ehrler, F; Fadeyev, V; Galloway, Z; Grabas, H; Gregor, I M; Grenier, P; Grillo, A; Hoeferkamp, M; Hommels, L B A; John, J; Kanisauskas, K; Kenney, C; Kramberger, J; Liang, Z; Mandic, I; Maneuski, D; Martinez-McKinney, F; McMahon, S; Meng, L; Mikuž, M; Muenstermann, D; Nickerson, R; Peric, I; Phillips, P; Plackett, R; Rubbo, F; Segal, J; Seidel, S; Seiden, A; Shipsey, I; Song, W; Stanitzki, M; Su, D; Tamma, C; Turchetta, R; Vigani, L; olk, J; Wang, R; Warren, M; Wilson, F; Worm, S; Xiu, Q; Zhang, J; Zhu, H

    2016-01-01

    The LHC luminosity upgrade, known as the High Luminosity LHC (HL-LHC), will require the replacement of the existing silicon strip tracker and the transistion radiation tracker. Although a baseline design for this tracker exists the ATLAS collaboration and other non-ATLAS groups are exploring the feasibility of using CMOS Monolithic Active Pixel Sensors (MAPS) which would be arranged in a strip-like fashion and would take advantage of the service and support structure already being developed for the upgrade. Two test devices made with theAMSH35 process (a High voltage or HV CMOS process) have been subjected to various radiation environments and have performed well. The results of these tests are presented in this paper.

  11. Flip-flop design in nanometer CMOS from high speed to low energy

    CERN Document Server

    Alioto, Massimo; Palumbo, Gaetano

    2015-01-01

    This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gai...

  12. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Milin Zhang

    2010-01-01

    Full Text Available Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

  13. A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

    Energy Technology Data Exchange (ETDEWEB)

    Xiao Shimao; Yu Yunfeng; Ma Chengyan; Ye Tianchun [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China); Yin Ming, E-mail: xiaoshimao@casic.ac.c [Hangzhou Zhongke Microelectronics Co Ltd, Hangzhou 310053 (China)

    2010-03-15

    The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 {mu}m 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm{sup 2}. (semiconductor integrated circuits)

  14. Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

    Science.gov (United States)

    Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

    2015-02-01

    An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

  15. A Zero Suppression Micro-Circuit for Binary Readout CMOS Monolithic Sensors

    CERN Document Server

    Himmi, A; Torheim, O; Hu-Guo, C; Winter, A

    2009-01-01

    The EUDET-JRA1 beam telescope and the STAR vertex detector upgrade will be equipped with CMOS pixel sensors allowing to provide high density tracking adapted to intense particle beams. The EUDET sensor Mimosa26, is designed and fabricated in a CMOS-0.35μm Opto process. Its architecture is based on a matrix of 1152x576 pixels, 1152 column-level Analogue-to-Digital Conversion (ADC) by discriminators and a zero suppression circuitry. This paper focused on the data sparsification architecture, allowing a data compression factor between from 10 and 1000, depending on the hit density per frame. It can be extended to the final sensor for the STAR upgrade.

  16. Stochastic process variation in deep-submicron CMOS circuits and algorithms

    CERN Document Server

    Zjajo, Amir

    2014-01-01

    One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and ne...

  17. Reliability of high mobility SiGe channel MOSFETs for future CMOS applications

    CERN Document Server

    Franco, Jacopo; Groeseneken, Guido

    2014-01-01

    Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and pr...

  18. Analog CMOS design for optical coherence tomography signal detection and processing.

    Science.gov (United States)

    Xu, Wei; Mathine, David L; Barton, Jennifer K

    2008-02-01

    A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

  19. Opportunities of CMOS-MEMS integration through LSI foundry and open facility

    Science.gov (United States)

    Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

    2017-06-01

    Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

  20. Modellierung und Simulation des Substrat-Rauschens in integrierten RF CMOS-Schaltungen

    Science.gov (United States)

    Lin, L.; Xiong, J.; Mathis, W.

    2009-05-01

    Im integrierten CMOS-Schaltungsentwurf kann das Substrat-Rauschen, das vom digitalen Teil entsteht, die Funktionalität des analogen Teils stark beeinflussen. Es wird daher immer wichtiger, das Substrat als ein Medium der Rauschen-Propagation genau zu modellieren. Im vorliegenden Artikel wird ein auf der Finite Elemente Methode (FEM) und Modellordnungsreduktion (MOR) basiertes Modellierungsverfahren zur Admittanzen-Extraktion im Halbleitersubstrat vorgestellt. Nach der Diskretisierung mit FEM wird das Substrat im Allgemeinen als ein resistives/kapazitives Netz angesehen. Durch Bestimmung der Admittanz-Matrix und MOR ist es möglich ein äquivalentes Dreipol-Modell zwischen digitalem und analogem Teil über das Substrat zu bilden. Das Ergebnis der Modellierung wird dargestellt und mit numerischer Simulation des Substrat-Rauschens verglichen. Die Modellierung ermöglicht es, die Einflüsse des Substrat-Rauschens im Schaltungsentwurf zu berücksichtigen und so bestehende CMOS-Schaltungsarchitekturen zu optimieren.