WorldWideScience

Sample records for single silicon wafer

  1. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    Science.gov (United States)

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

  2. Fabrication of silicon condenser microphones using single wafer technology

    NARCIS (Netherlands)

    Scheeper, P.R.; van der Donk, A.G.H.; Olthuis, Wouter; Bergveld, Piet

    1992-01-01

    A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-¿m plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm2), covered with a thin

  3. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  4. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  5. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Directory of Open Access Journals (Sweden)

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  6. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  7. The evolution of silicon wafer cleaning technology

    International Nuclear Information System (INIS)

    Kern, W.

    1990-01-01

    The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What has changed is its implementation with optimized equipment:from simple immersion to centrifugal spraying, megasonic techniques, and enclosed system processing that allow simultaneous removal of both contaminant films and particles. Improvements in wafer drying by use of isopropanol vapor or by slow-pull out of hot deionized water are being investigated. Several alternative cleaning methods are also being tested, including choline solutions, chemical vapor etching, and UV/ozone treatments. The evolution of silicon wafer cleaning processes and technology is traced and reviewed

  8. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  9. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  10. Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

    Energy Technology Data Exchange (ETDEWEB)

    Tiriolo, Raffaele [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Rangnekar, Neel [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Zhang, Han [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Shete, Meera [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Bai, Peng [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Nelson, John [Characterization Facility, University of Minnesota, 12 Shepherd Labs, 100 Union St. S.E. Minneapolis MN 55455 USA; Karapetrova, Evguenia [Surface Scattering and Microdiffraction, X-ray Science Division, Argonne National Laboratory, 9700 S. Cass Ave, Building 438-D002 Argonne IL 60439 USA; Macosko, Christopher W. [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Siepmann, Joern Ilja [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Lamanna, Ernesto [Department of Health Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Lavano, Angelo [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Tsapatsis, Michael [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA

    2017-05-08

    A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.

  11. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  12. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  13. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  14. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding......Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...

  15. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  16. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  17. Metallization of large silicon wafers. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Pryor, R A

    1979-01-01

    A metallization scheme has been developed which allows selective plating of silicon solar cell surfaces. The system is comprised of three layers. Palladium, through the formation of palladium silicide at 300/sup 0/C in nitrogen, makes ohmic contact to the silicon surface. Nickel, plated on top of the palladium silicide layer, forms a solderable interface. Lead-tin solder on the nickel provides conductivity and allows a convenient means for interconnection of cells. To apply this metallization, three chemical plating baths are employed. Palladium is deposited with an immersion palladium solution and an electroless palladium solution, and nickel is deposited with an electroless nickel solution. Solder is applied with a molten solder dip. Extensive development work has been performed to achieve an effective immersion palladium solution formulation, leading to reproducible formation of the palladium silicide contact layer. This metallization system has been repeatedly demonstrated to be extremely effective. Current-voltage characteristic curve fill factors of 78% are easily achieved. This has been done while maintaining metal contact adhesion at such a strength as to fail by fracturing silicon upon perpendicular pull testing rather than be delaminating the metal system. Process specifications and procedures have been prepared.

  18. Chemical method for producing smooth surfaces on silicon wafers

    Science.gov (United States)

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  19. Thin-film resistance thermometers on silicon wafers

    International Nuclear Information System (INIS)

    Kreider, Kenneth G; Ripple, Dean C; Kimes, William A

    2009-01-01

    We have fabricated Pt thin-film resistors directly sputtered on silicon substrates to evaluate their use as resistance thermal detectors (RTDs). This technique was chosen to achieve more accurate temperature measurements of large silicon wafers during semiconductor processing. High-purity (0.999 968 mass fraction) platinum was sputter deposited on silicon test coupons using titanium and zirconium bond coats. These test coupons were annealed, and four-point resistance specimens were prepared for thermal evaluation. Their response was compared with calibrated platinum–palladium thermocouples in a tube furnace. We evaluated the effects of furnace atmosphere, thin-film thickness, bond coats, annealing temperature and peak thermal excursion of the Pt thin films. Secondary ion mass spectrometry (SIMS) was performed to evaluate the effect of impurities on the thermal resistance coefficient, α. We present typical resistance versus temperature curves, hysteresis plots versus temperature and an analysis of the causes of uncertainties in the measurement of seven test coupons. We conclude that sputtered thin-film platinum resistors on silicon wafers can yield temperature measurements with uncertainties of less than 1 °C, k = 1 up to 600 °C. This is comparable to or better than commercially available techniques

  20. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  1. Characterization of perovskite layer on various nanostructured silicon wafer

    Science.gov (United States)

    Rostan, Nur Fairuz Mohd; Sepeai, Suhaila; Ramli, Noor Fadhilah; Azhari, Ayu Wazira; Ludin, Norasikin Ahmad; Teridi, Mohd Asri Mat; Ibrahim, Mohd Adib; Zaidi, Saleem H.

    2017-05-01

    Crystalline silicon (c-Si) solar cell dominates 90% of photovoltaic (PV) market. The c-Si is the most mature of all PV technologies and expected to remain leading the PV technology by 2050. The attractive characters of Si solar cell are stability, long lasting and higher lifetime. Presently, the efficiency of c-Si solar cell is still stuck at 25% for one and half decades. Tandem approach is one of the attempts to improve the Si solar cell efficiency with higher bandgap layer is stacked on top of Si bottom cell. Perovskite offers a big potential to be inserted into a tandem solar cell. Perovskite with bandgap of 1.6 to 1.9 eV will be able to absorb high energy photons, meanwhile c-Si with bandgap of 1.124 eV will absorb low energy photons. The high carrier mobility, high carrier lifetime, highly compatible with both solution and evaporation techniques makes perovskite an eligible candidate for perovskite-Si tandem configuration. The solution of methyl ammonium lead iodide (MAPbI3) was prepared by single step precursor process. The perovskite layer was deposited on different c-Si surface structure, namely planar, textured and Si nanowires (SiNWs) by using spin-coating technique at different rotation speeds. The nanostructure of Si surface was textured using alkaline based wet chemical etching process and SiNW was grown using metal assisted etching technique. The detailed surface morphology and absorbance of perovskite were studied in this paper. The results show that the thicknesses of MAPbI3 were reduced with the increasing of rotation speed. In addition, the perovskite layer deposited on the nanostructured Si wafer became rougher as the etching time and rotation speed increased. The average surface roughness increased from ˜24 nm to ˜38 nm for etching time range between 5-60 min at constant low rotation speed (2000 rpm) for SiNWs Si wafer.

  2. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  3. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  4. An electron-multiplying 'Micromegas' grid made in silicon wafer post-processing technology

    NARCIS (Netherlands)

    Chefdeville, M.; Chefdeville, M.A.; Colas, P.; Giomataris, Y.; van der Graaf, H.; Heijne, E.H.M.; van der Putten, S.; Salm, Cora; Schmitz, Jurriaan; Smits, Sander M.; Timmermans, J.; Visschers, J.L.

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 μm by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication

  5. An electron-multiplying 'Micromegas' grid made in silicon wafer post-processing technology

    NARCIS (Netherlands)

    Chefdeville, M.; Chefdeville, M.A.; Colas, P.; Giomataris, Y.; van der Graaf, H.; Heijne, E.H.M.; van der Putten, S.; Salm, Cora; Schmitz, Jurriaan; Smits, Sander M.; Timmermans, J.; Visschers, J.L.

    2005-01-01

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 μm by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication

  6. An electron-multiplying ''Micromegas'' grid made in silicon wafer post-processing technology

    NARCIS (Netherlands)

    Chefdeville, M.A.; Colas, P.; Giomataris, Y.; van der Graaf, H.; Heijne, E.H.M.; van der Putten, S.; Salm, Cora; Schmitz, Jurriaan; Smits, Sander M.; Timmermans, J.; Timmermans, J.; Visschers, J.L.

    2005-01-01

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 mm by means of insulating pillars. When some 400V are applied between the grid and (anode) wafer, gas multiplication

  7. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  8. Simulation Research on Micro Contact Based on Force in Silicon Wafer Rotation Grinding

    Science.gov (United States)

    Ren, Qinglei; Wei, Xin; Xie, Xiaozhu; Hu, Wei

    2017-10-01

    Silicon wafer rotation grinding with cup type diamond wheel is a typical ultra precision grinding process. In this paper, a simulation model based on force for micro contact between wheel micro unit and silicon wafer is established from the stable ductile grinding process. Micro contact process in grinding is simulated using the nonlinear explicit finite element analysis software LS-DYNA. The stress-strain results on silicon wafer and wheel micro unit are analyzed by finite element method. The results show that the critical displacement and load corresponding elastic to plastic - plastic to brittle exist on silicon wafer. In silicon plastic zone tangential sliding can produce plastic groove and uplift. Wear of wheel micro unit can be based on the simulation data to judge. The research provides support for wafer grinding and wheel wear mechanism.

  9. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  10. Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer

    Science.gov (United States)

    Massoubre, David; Wang, Li; Hold, Leonie; Fernandes, Alanna; Chai, Jessica; Dimitrijev, Sima; Iacopi, Alan

    2015-11-01

    Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100 mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100 nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70 A/cm2 above 1.5 V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers.

  11. Sheet resistivity of silicon wafers implanted with a high current machine

    International Nuclear Information System (INIS)

    Steeples, K.

    1985-01-01

    Silicon wafers, as used in the integrated circuits and semiconductor device industry, have been implanted with all the common dopants using Eaton Corporation's commercially available 'NV' series of high current implanters. Most detailed studies of the implanted wafers have focused on using arsenic and boron as dopants since the transport of these dopants in silicon has been found to be more compatible with the trend towards shrinking device dimensions. Four point probe measurements have been taken on implanted wafers with subsequent annealing to indicate the quality and effect of the implant. The variation of sheet resistance with dose and energy have been studied using a machine in standard condition over the range of 10 14 -10 16 ions/cm 2 and over an energy range of 5-180 keV for arsenic and boron implants into bare wafers and wafers with screen oxides. Dose control at low doses in the Eaton High Current Implanter has been studied over a range of 10 10 -10 13 ions/cm 2 using MOS devices and other measurements. Repeatability of the machines has been obtained by tracking the manufacture of over one hundred machines for nearly three years. With the use of an Eaton Standard Test Implant Procedure for each machine before shipment, it has been shown that the dose repeatability can be as good as 2% (including furnace and four point probe variations) for machine to machine. The repeatability within a single machine was found to be better than 0.5%. Arsenic ion beams have shown excellent independence of end station pressure, as may occur during photoresist outgassing or controlled gas leaks. Boron beams have a higher electron capture cross-section than other commonly used beams and require a dose control compensation for high end station pressure implants to give agreement with the low pressure regime. (orig./TW)

  12. Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding

    Science.gov (United States)

    Beggans, Michael H.; Ivanov, Dentcho I.; Fu, Steven G.; Digges, Thomas G., III; Farmer, Kenneth R.

    1999-03-01

    A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been fabricated on 10 cm diameter, 500-micron thick, Pyrex glass wafers. The glass wafers have been micro-machined using ultrasonic drilling in order to form cavities, optical fiber feedthrough holes and vent holes. One of the main challenges of the manufacturing process is the handling of the ultra-thin silicon wafers. Being extremely flexible, the thin silicon wafers cannot be cleaned, oxidized, or dried in the same way as normal since wafers with a thickness of the order of 400 microns. Specific handling techniques have been developed in order to achieve reproducible cleaning and oxidation processes. The anodic bonding was performed using an Electronic Visions EV501S bonder. The wafers were heated at 420 degrees C and a voltage of 1200 volts was applied in vacuum of 10-5 Torr. The bonded wafer stack was then fixed in a wax and diced. The resulting chips have been used to fabricate operating pressure sensors.

  13. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Directory of Open Access Journals (Sweden)

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  14. Delineation of Crystalline Extended Defects on Multicrystalline Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Mohamed Fathi

    2007-01-01

    Full Text Available We have selected Secco and Yang etch solutions for the crystalline defect delineation on multicrystalline silicon (mc-Si wafers. Following experimentations and optimization of Yang and Secco etching process parameters, we have successfully revealed crystalline extended defects on mc-Si surfaces. A specific delineation process with successive application of Yang and Secco agent on the same sample has proved the increased sensitivity of Secco etch to crystalline extended defects in mc-Si materials. The exploration of delineated mc-Si surfaces indicated that strong dislocation densities are localized mainly close to the grain boundaries and on the level of small grains in size (below 1 mm. Locally, we have observed the formation of several parallel dislocation lines, perpendicular to the grain boundaries. The overlapping of several dislocations lines has revealed particular forms for etched pits of dislocations.

  15. Fabrication of PIN diode detectors on thinned silicon wafers

    CERN Document Server

    Ronchin, Sabina; Dalla Betta, Gian Franco; Gregori, Paolo; Guarnieri, Vittorio; Piemonte, Claudio; Zorzi, Nicola

    2004-01-01

    Thin substrates are one of the possible choices to provide radiation hard detectors for future high-energy physics experiments. Among the advantages of thin detectors are the low full depletion voltage, even after high particle fluences, the improvement of the tracking precision and momentum resolution and the reduced material budget. In the framework of the CERN RD50 Collaboration, we have developed p-n diode detectors on membranes obtained by locally thinning the silicon substrate by means of tetra-methyl ammonium hydroxide etching from the wafer backside. Diodes of different shapes and sizes have been fabricated on 57 and 99mum thick membranes. They have been tested, showing a very low leakage current ( less than 0.4nA/cm**2) and, as expected, a very low depletion voltage ( less than 1V for the 57mum membrane). The paper describes the technological approach used for devices fabrication and reports selected results from the electrical characterization.

  16. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    CERN Document Server

    Casse, G L; Lemeilleur, F; Ruzin, A; Wegrzecki, M

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10/sup 17/ atoms cm/sup -3 /) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO/sub 2/ layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 mu m thick silicon wafer. (7 refs).

  17. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  18. Laser cleaning of silicon wafers: mechanisms and efficiencies

    Science.gov (United States)

    Mosbacher, Mario; Bertsch, M.; Muenzer, H.-J.; Dobler, V.; Runge, B.-U.; Baeuerle, Dieter; Boneberg, Johannes; Leiderer, Paul

    2002-02-01

    We report on experiments on the underlying physical mechanisms in the Dry-(DLC) and Steam Laser Cleaning (SLC) process. Using a frequency doubled, Q-switched Nd:YAG laser (FWHMequals8 ns), we removed polystyrene (PS) particles with diameters from 110-2000 nm from industrial silicon wafers by the DLC process. The experiments have been carried out both in ambient conditions as well as in high vacuum (10-6mbar) and the cleaned areas have been characterized by atomic force microscopy for damage inspection. Besides the determining the cleaning thresholds in laser fluence for a large interval of particle sizes we could show that particle removal in DLC is due to a combination of at least three effects: thermal substrate expansion, local substrate ablation due to field enhancement at the particle and explosive evaporation of absorbed humidity from the air. Which effect dominates the process is subject to the boundary conditions. For our laser parameters no damage free DLC was possible, i.e. whenever a particle was removed by DLC we damaged the substrate by local field enhancement. In our SLC experiments we determined the amount of superheating of a liquid layer adjacent to surfaces with controlled roughness that is necessary, in good agreement with theoretical predictions. Rough surfaces exhibited only a much smaller superheating.

  19. Evaluation of water based intelligent fluids for resist stripping in single wafer cleaning tools

    Science.gov (United States)

    Rudolph, Matthias; Esche, Silvio; Hohle, Christoph; Schumann, Dirk; Steinke, Philipp; Thrun, Xaver; von Sonntag, Justus

    2016-03-01

    The application of phasefluid based intelligent fluids® in the field of photoresist stripping was studied. Due to their highly dynamic inner structure, phasefluids penetrate into the polymer network of photoresists and small gaps between resist layer and substrate and lift off the material from the surface. These non-aggressive stripping fluids were investigated regarding their efficiency in various resist stripping applications including initial results on copper metallization. Furthermore intelligent fluids® have been evaluated on an industry standard high volume single wafer cleaner. A baseline process on 300 mm wafers has been developed and characterized in terms of metallic and ionic impurities and defect level. Finally a general proof of concept for removal of positive tone resist from 300 mm silicon wafers is demonstrated.

  20. Analysis of Processing Mechanism in Stealth Dicing of Ultra Thin Silicon Wafer

    Science.gov (United States)

    Ohmura, Etsuji; Kumagai, Masayoshi; Nakano, Makoto; Kuno, Koji; Fukumitsu, Kenshi; Morita, Hideki

    In this study, “stealth dicing” (SD) was applied to ultra thin wafers 50 μm in thickness. A coupling problem composed of focused laser propagation in single crystal silicon, along with laser absorption, temperature rise and heat conduction was analyzed by considering the temperature dependence of the absorption coefficient. When the depth of the focal plane is too shallow, the laser is also absorbed at the surface as the thermal shock wave reaches the surface. As a result, not only is an internal modified layer generated but ablation occurs at the surface as well. When the laser is focused at the surface, strong ablation occurs. Ablation at the surface is unfavorable because of the debris pollution and thermal effect on the device domain. It was concluded that there is a suitable depth for the focal plane so that the thermal shock wave propagates inside the wafer only. The optimum irradiating conditions such as pulse energy, pulse width, spot radius, and depth of focal plane can be estimated theoretically also for ultra thin wafer.

  1. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  2. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    International Nuclear Information System (INIS)

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  3. Improvement of surface roughness in silicon-on-insulator wafer fabrication using a neutral beam etching

    Science.gov (United States)

    Min, T. H.; Park, B. J.; Kang, S. K.; Gweon, G. H.; Kim, Y. Y.; Yeom, G. Y.

    2009-08-01

    Silicon-on-insulator (SOI) wafers were etched by an energetic chlorine neutral beam obtained by the low-angle forward reflection of an ion beam, and the surface roughness of the etched wafers was compared with that of the SOI wafers etched by an energetic chlorine ion beam. When the ion beam was used to etch the silicon layer of the SOI wafers, the surface roughness was not significantly changed even though the use of higher ion bombardment energy slightly decreased the surface roughness of the SOI wafer. However, when the chlorine neutral beam was used instead of the chlorine ion beam having a similar beam energy, the surface roughness of the SOI wafer was significantly improved compared with that etched by the chlorine ion beam. By etching about 150 nm silicon from the SOI wafer having a 300 nm-thick top silicon layer with the chlorine neutral beam at the energy of 500 eV, the rms surface roughness of 1.5 Å could be obtained with the etch rate of about 750 Å min-1.

  4. AFM study of hippocampal cells cultured on silicon wafers with nano-scale surface topograph.

    Science.gov (United States)

    Ma, J; Liu, B F; Xu, Q Y; Cui, F Z

    2005-08-01

    The rat hippocampal cells were selected as model to study the interaction between the neural cells and silicon substrates using atomic force microscopy (AFM). The hippocampal cells show tight adherence on silicon wafers with nano-scale surface topograph. The lateral friction force investigated by AFM shows significant increase on the boundary around the cellular body. It is considered to relate to the cytoskeleton and cellular secretions. After ultrasonic wash in ethanol and acetone step by step, the surface of silicon wafers was observed by AFM sequentially. We have found that the culture leftovers form tight porous networks and a monolayer on the silicon wafers. It is concluded that the leftovers overspreading on the silicon substrates are the base of cell adherence on such smooth inert surfaces.

  5. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage

    Directory of Open Access Journals (Sweden)

    Alexander Rack

    2016-03-01

    Full Text Available Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1–2 ms followed by jumps faster than 2–6 m s−1, leading to a macroscopically observed average velocity of 0.028–0.055 m s−1. The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound.

  6. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    NARCIS (Netherlands)

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  7. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    International Nuclear Information System (INIS)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  8. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  9. Development of Megasonic cleaning for silicon wafers. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  10. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  11. Adhesion of neural cells on silicon wafer with nano-topographic surface

    Science.gov (United States)

    Fan, Y. W.; Cui, F. Z.; Chen, L. N.; Zhai, Y.; Xu, Q. Y.; Lee, I.-S.

    2002-02-01

    The adherence and subsequent viability of central neural cells (substantia nigra) on silicon wafers with different surface roughness conditions were investigated. Various roughness conditions of the silicon wafer were achieved by etching at different times. The topography was evaluated by AFM. Primary neurons were obtained from Wistar rats. The adherence and subsequent viability of the cells on the wafer were examined by scanning electronic microscopy and fluorescence immunostaining of tyrosine hydroxylase. It is found that the surface roughness affects significantly cell adhesion and viability. Cells can survive for over 5 days on the surface with average roughness in the range 20-70 nm. Such a treatment may provide a new method to make a mild interface of silicon-based electronic devices and neurons as well as other living tissues.

  12. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  13. Nano silver-catalyzed chemical etching of polycrystalline silicon wafer for solar cell application

    Directory of Open Access Journals (Sweden)

    S. R. Chen

    2016-03-01

    Full Text Available Silver nanoparticles were deposited on the surface of polycrystalline silicon wafer via vacuum thermal evaporation and metal-catalyzed chemical etching (MCCE was conducted in a HF-H2O2 etching system. Treatment of the etched silicon wafer with HF transformed the textured structure on the surface from nanorods into nanocones. An etching time of 30 s and treatment with HF resulted in nanocones with uniform size distribution and a reflectivity as low as 1.98% across a spectral range from 300 to 1000 nm.

  14. Bismuth onion thin film in situ grown on silicon wafer synthesized through a hydrothermal approach

    International Nuclear Information System (INIS)

    Zhao Yue; Liu Hong; Liu Jin; Hu Chenguo; Wang Jiyang

    2010-01-01

    Bismuth onion structured nanospheres with the same structure as carbon onions have been synthesized and observed. The nanospheres were synthesized through a hydrothermal method using bismuth hydroxide and silicon wafer as reactants. By controlling the heating temperature, heating time, and the pressure, nanoscale bismuth spheres can be in situ synthesized on silicon wafer, and forms a bismuth onion film on the substrate. The electronic property of the films was investigated. A formation mechanism of the formation of bismuth onions and the onion film has been proposed on the basis of experimental observations.

  15. Sheet resistance uniformity in drive-in step for different multi-crystalline silicon wafer dispositions

    Energy Technology Data Exchange (ETDEWEB)

    Moussi, A.; Bouhafs, D.; Mahiou, L. [Laboratoire des Cellules Photovoltaiques, Unite de Developpement de la Technologie du Silicium, 2 Bd, Frantz Fanon, B.P. 140, 7 Merveilles Alger (Algeria); Belkaid, M.S. [Dep. Electronique, Faculte de Genie Electrique et Informatique, UMMTO (Algeria)

    2009-09-15

    In this work, we present a study of emitters realized using different configurations of the silicon wafers in the quartz boat. The phosphorous liquid source is sprayed onto p-type multi-crystalline silicon substrates and the drive-in is made at high temperature in a muffle furnace. Three different configurations of the wafers in the boat are tested: separated, back to back and compact block of wafers. A fourth configuration is also used in source-receptor mode. The emitter phosphorous concentration profile is obtained by SIMS analysis. The resulting emitters are characterized by sheet resistance measurements and a comparison is made between the wafers within the same batch and from one batch to another. The uniformity and the standard deviation of the sheet resistance are calculated in each case. The emitter sheet resistance mapping of the wafer set in the middle of the boat for a given process gives a mean R{sub sq} 14.66 {omega}/sq with a standard deviation of 1.76% and uniformity of 18.7%. Standard deviations of 2.116% and 1.559% are obtained for wafers in the batch when using the spaced and compact configurations, respectively. The standard deviation is reduced to 0.68% when the wafers are used in source/receptor mode. A comparison is also made between wafers with different dilution of phosphorous source in ethanol. From these results we can conclude that the compact configuration offers better uniformity and lower standard deviation. Furthermore, when combined with the source-receptor configuration these parameters are significantly improved. This study allows the experimenter to identify the technological parameters of the solar cell emitter manufacturing and target precisely the desired values of the sheet resistance while limiting the number of rejected wafers. (author)

  16. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  17. Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

    Science.gov (United States)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-30

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  18. Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

    Science.gov (United States)

    Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

    2018-02-01

    Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

  19. Light coupling and light trapping in alkaline etched multicrystalline silicon wafers for solar cells

    NARCIS (Netherlands)

    Hylton, J.D.

    2006-01-01

    The reflection reducing and light trapping properties of alkaline etched multicrystalline silicon wafers are investigated experimentally. Following an overview of various chemical texturisation methods and their effect upon the surface morphology, a high concentration saw-damage etch and a low

  20. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    Science.gov (United States)

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  1. Sample pretreatment for the determination of metal impurities in silicon wafer

    International Nuclear Information System (INIS)

    Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

    1999-01-01

    The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

  2. Silicon Wafer Fabrication and Microchannel for Cooling System in ALICE ITS

    CERN Document Server

    Pasuwan, Patrawan

    2013-01-01

    My summer student project covered details of the upgrade of Inner Tracking System (ITS) of the ALICE detector. The tasks are divided in two parts. First was on silicon wafer dicing technology and its resistivity under the supervision of Petra Riedler. Next was on silicon wafer microfabrication and cooling system in microchannel under the supervision of Andrea Francescon. ITS upgrade was proposed for better detection performance and reduction of budget. Detectors in the ITS are composed of monolithic silicon pixel chips. The thickness of the chips was proposed to be 50 μm so that particles that pass through them do not lose too much momentum. Working with very thin chips requires suitable dicing technology. Sum- mary of dicing technology is proposed for the most suitable dicing technique. Properties of the chip can be denoted by observing its resistivity. Literature reviews on surface resistivity profile measurement is represented for consideration. Cooling system is very important for the detector. Fluid t...

  3. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    Administrator

    1Silicon Technology Unit (UDTS), 02 Bd Frantz Fanon, BP. 140, Alger-7 Merveilles, Algiers, Algeria. 2Houari Boumediene University of Science and Technology (USTHB), Bab Ezzouar, Algiers, Algeria. 3SSN-Research Centre, Rajiv ... ally, for solar cells metallization a standard screen print- ing process is applied. Initially ...

  4. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    ... Messaoud1 B Palahouane1 N Benrekaa2. Silicon Technology Unit (UDTS), 02 Bd Frantz Fanon, BP. 140, Alger-7 Merveilles, Algiers, Algeria; Houari Boumediene University of Science and Technology (USTHB), Bab Ezzouar, Algiers, Algeria; SSN-Research Centre, Rajiv Gandhi Salai (OMR), Kalavakkam 603 110, India ...

  5. Silicon Alignment Pins: An Easy Way to Realize a Wafer-To-Wafer Alignment

    Science.gov (United States)

    Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Thomas, Bertrand (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor); Gill, John J. (Inventor); Lee, Choonsup (Inventor); Siles, Jose V. (Inventor); Toda, Risaku (Inventor); Chattopadhyay, Goutam (Inventor)

    2016-01-01

    A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

  6. The deposition of silicon nitride films under low pressure on wafers up to 200 mm

    Directory of Open Access Journals (Sweden)

    Nalivaiko O. Yu.

    2012-12-01

    Full Text Available The influence of silicon nitride deposition condition on parameters of the obtained films has been investigated. It has been found that the deposition rate of silicon nitride films decreases with deposition temperature decreasing, and at the same time the within wafer thickness uniformity improves. It allows performing the reproducible deposition of silicon nitride films with thickness of less than 10 nm. It has been found that in order to decrease the oxidation depth of silicon nitride, it is appropriate to carry out the oxidation under 850—900°C. The developed process of silicon nitride deposition made it possible to obtain reservoir capacitors with specific capacitance of 3,8—3,9 fF/μm2 at film thickness of 7,0 nm.

  7. An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology

    CERN Document Server

    Chefdeville, M; Giomataris, Ioanis; van der Graaf, H; Heijne, Erik H M; Van der Putten, S; Salm, C; Schmitz, J; Smits, S; Timmermans, J; Visschers, J L

    2006-01-01

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 \\mum by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication occurs : primary electrons from the drift space above the grid enter the holes and cause electron avalanches in the high-field region between the grid and the anode. Production and operational characteristics of the device are described. With this newly developed technology, CMOS (pixel) readout chips can be covered with a gas multiplication grid. Such a chip forms, together with the grid, an integrated device which can be applied as readout in a wide field of gaseous detectors.

  8. Micro-spectroscopy on silicon wafers and solar cells

    Directory of Open Access Journals (Sweden)

    Gundel Paul

    2011-01-01

    Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

  9. Grain-boundary type and distribution in silicon carbide coatings and wafers

    Science.gov (United States)

    Cancino-Trejo, Felix; López-Honorato, Eddie; Walker, Ross C.; Ferrer, Romelia Salomon

    2018-03-01

    Silicon carbide is the main diffusion barrier against metallic fission products in TRISO (tristructural isotropic) coated fuel particles. The explanation of the accelerated diffusion of silver through SiC has remained a challenge for more than four decades. Although, it is now well accepted that silver diffuse through SiC by grain boundary diffusion, little is known about the characteristics of the grain boundaries in SiC and how these change depending on the type of sample. In this work five different types (coatings and wafers) of SiC produced by chemical vapor deposition were characterized by electron backscatter diffraction (EBSD). The SiC in TRISO particles had a higher concentration of high angle grain boundaries (aprox. 70%) compared to SiC wafers, which ranged between 30 and 60%. Similarly, SiC wafers had a higher concentration of low angle grain boundaries ranging between 15 and 30%, whereas TRISO particles only reached values of around 7%. The same trend remained when comparing the content of coincidence site lattice (CSL) boundaries, since SiC wafers showed a concentration of more than 30%, whilst TRISO particles had contents of around 20%. In all samples the largest fractions of CSL boundaries (3 ≤ Σ ≤ 17) were the Σ3 boundaries. We show that there are important differences between the SiC in TRISO particles and SiC wafers which could explain some of the differences observed in diffusion experiments in the literature.

  10. Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

    Science.gov (United States)

    Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

    2018-01-01

    Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

  11. Atomic force and confocal microscopy for the study of cortical cells cultured on silicon wafers.

    Science.gov (United States)

    Ma, J; Cui, F Z; Liu, B F; Xu, Q Y

    2007-05-01

    The primary cortical cells were selected as a model to study the adherence and neural network development on chemically roughened silicon substrates without any coatings using confocal laser scanning microscopy (CLSM) and atomic force microscopy (AFM). The silicon substrates have a nano-range roughness (RMS) achieved by chemical etching using hydrofluoric (HF) acid. After 7 days of culturing, the neurons were observed to connect together and form dense neural networks. Furthermore, AFM results revealed that some porous structures at a few micrometer range existed between the neuron cells and the silicon substrates. It is suggested that the porous structures are made of extracellular matrix (ECM) components and play an important role in the neuronal adhesion and neurite outgrowth on the inert silicon wafers.

  12. High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

    Energy Technology Data Exchange (ETDEWEB)

    Antoniadis, H.

    2011-03-01

    Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink high efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.

  13. A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

    International Nuclear Information System (INIS)

    Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

    1990-01-01

    The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

  14. Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

    International Nuclear Information System (INIS)

    Moslehi, M.M.; Davis, C.

    1989-01-01

    Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

  15. Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection

    International Nuclear Information System (INIS)

    Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

    2015-01-01

    This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50  ×  55 µm (width × height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75 °C) bonding adhesive and as etch mask during 300 µm deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10 µm size could be detected with a mean signal amplitude of 0.39  ±  0.13 V (n=439) at particle velocities of up to 9.6 mm s −1 inside the chip. (paper)

  16. Fabrication of through-wafer 3D microfluidics in silicon carbide using femtosecond laser

    Science.gov (United States)

    Huang, Yinggang; Wu, Xiudong; Liu, Hewei; Jiang, Hongrui

    2017-06-01

    We demonstrate a prototype through-wafer microfluidic structure in bulk silicon carbide (SiC) fabricated by femtosecond laser micromachining. The effects of laser fluence and scanning speed on the laser-affected zone are also investigated. Furthermore, the wettability of the laser-affected surface for the target liquid, mineral oil, is examined. Microchannels of various cross-sectional shapes are fabricated by the femtosecond laser and their effects on the liquid flow are simulated and compared. This fabrication approach offers a fast and efficient route to implement SiC-based through-wafer micro-structures, which are not able to be realized using other methods such as chemical etching. The flexibility of manufacturing 3D structures based on this fabrication method enables more complex structures as well. Smooth liquid flow in the microchannels of the bulk SiC substrate is presented. The work shown here paves a new way for various applications such as reliable microfluidic systems in a high-temperature, high radioactivity, and corrosive environment, and could be combined with SiC wafer-to-wafer bonding to realize a plethora of novel microelectromechanical (MEMS) structures.

  17. Geometrical Deviation and Residual Strain in Novel Silicon-on-Aluminium-Nitride Bonded Wafers

    Science.gov (United States)

    Men, Chuan-Ling; Xu, Zheng; Wu, Yan-Jun; An, Zheng-Hua; Xie, Xin-Yun; Lin, Cheng-Lu

    2002-11-01

    Aluminium nitride (AlN), with much higher thermal conductivity, is considered to be an excellent alternative to the SiO2 layer in traditional silicon-on-insulator (SOI) materials. The silicon-on-aluminium-nitride (SOAN) structure was fabricated by the smart-cut process to alleviate the self-heating effects for traditional SOI. The convergent beam Kikuchi line diffraction pattern results show that some rotational misalignment exists when two wafers are bonded, which is about 3°. The high-resolution x-ray diffraction result indicates that, before annealing at high temperature, the residual lattice strain in the top silicon layer is tensile. After annealing at 1100°C for an hour, the strain in the top Si decreases greatly and reverses from tensile to slightly compressive as a result of viscous flow of AlN.

  18. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale.

    Science.gov (United States)

    Berman, Diana; Deshmukh, Sanket A; Narayanan, Badri; Sankaranarayanan, Subramanian K R S; Yan, Zhong; Balandin, Alexander A; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V

    2016-07-04

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.

  19. The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

    Directory of Open Access Journals (Sweden)

    Gnilenko A. B.

    2012-02-01

    Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

  20. Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

    Science.gov (United States)

    Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

    2011-01-01

    Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

  1. Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

    International Nuclear Information System (INIS)

    Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

    2005-01-01

    This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

  2. Dislocation sources and slip band nucleation from indents on silicon wafers

    International Nuclear Information System (INIS)

    Wittge, J.; Danilewsky, A.N.; Allen, D.

    2010-01-01

    The nucleation of dislocations at controlled indents in silicon during rapid thermal annealing has been studied by in situ X-ray diffraction imaging (topography). Concentric loops extending over pairs of inclined {111} planes were formed, the velocities of the inclined and parallel segments being almost equal. Following loss of the screw segment from the wafer, the velocity of the inclined segments almost doubled, owing to removal of the line tension of the screw segments. The loops acted as obstacles to slip band propagation. (orig.)

  3. Culture of neural cells on silicon wafers with nano-scale surface topograph.

    Science.gov (United States)

    Fan, Y W; Cui, F Z; Hou, S P; Xu, Q Y; Chen, L N; Lee, I-S

    2002-10-15

    The adherence and viability of central neural cells (substantia nigra) on a thin layer of SiO(2) on Si wafers with different surface roughness were investigated. Variable roughness of the Si wafer surface was achieved by etching. The nano-scale surface topography was evaluated by atomic force microscopy. The adherence and subsequent viability of the cells on the wafer were examined by scanning electron microscopy (SEM) and fluorescence immunostaining of tyrosine hydroxylase (TH). It is found that the surface roughness significantly affected cell adhesion and viability. Cells survived for over 5 days with normal morphology and expressed neuronal TH when grown on surfaces with an average roughness (Ra) ranging from 20 to 50 nm. However, cell adherence was adversely affected when surfaces with Ra less than 10 nm and rough surfaces with Ra above 70 nm were used as the substrate. Such a simple preparation procedure may provide a suitable interface surface for silicon-based devices and neurones or other living tissues.

  4. Boron implant profile variation across a single wafer due to electrostatic scanning

    International Nuclear Information System (INIS)

    Park, Changhae; Klein, K.M.; Tasch, A.F.; Simonton, R.B.; Kamenitsa, D.E.; Novak, S.

    1991-01-01

    The implanted impurity profile variation across a wafer due to an electrostatic scanning system has been studied for boron implants into (100) silicon wafers. The variation of the actual tilt and rotation angles across a wafer has been precisely determined for the implanter used in this study. The sensitivity of the impurity profiles to this angular variation has been studied through both a theoretical prediction based on an improved calculation of critical angles for channeling, and a qualitative analysis using the thermal wave measurement technique. A quantitative study of the profile variation across a wafer has also been performed using extensive secondary ion mass spectrometry (SIMS) profile measurements. For the energy range (15-80 keV) and angle range (0-10deg tilt angle, 0-360deg rotation angle) used in this study, we have identified the ranges of tilt and rotation angles that should be used for minimum channeling and minimum profile variation. (orig.)

  5. Detection of trace contamination of copper on a silicon wafer with TXRF

    International Nuclear Information System (INIS)

    Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

    2000-01-01

    The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

  6. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    Science.gov (United States)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  7. Formation of cross-cutting structures with different porosity on thick silicon wafers

    Directory of Open Access Journals (Sweden)

    Vera A. Yuzova

    2017-06-01

    The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

  8. N-type high-performance multicrystalline and mono-like silicon wafers with lifetimes above 2 ms

    Science.gov (United States)

    Pheng Phang, Sieu; Cheong Sio, Hang; Yang, Chia-Fu; Lan, Chung-Wen; Yang, Yu-Min; Wen-Huai Yu, Andy; Sung-Lin Hsu, Bruce; Wen-Ching Hsu, Chuck; Macdonald, Daniel

    2017-08-01

    Combined with advanced crystal growth technology and reduced dislocation densities, the higher tolerance to metal contamination of n-type silicon makes n-type cast-grown silicon a potential option for low cost high quality substrates for solar cells. Using a combination of photoconductance based lifetime testing and photoluminescence imaging, we have investigated the carrier lifetime in wafers from the bottom, middle, and top parts of a n-type high-performance multicrystalline (HPM) silicon ingot, and wafers from n-type mono-like silicon ingots after each high temperature solar cell processes, including after boron diffusion, phosphorus diffusion, and hydrogenation. Although boron diffusion leads to a degradation of the sample lifetime, phosphorus diffusion and hydrogenation is effective at recovering the lifetime in the intra-grain region and at the grain boundaries respectively. Quasi-steady-state photoconductance (QSSPC) measurements show that the arithmetic average lifetime of HPM silicon wafers and mono-like silicon wafers can reach up to 1.8 and 3.3 ms respectively for a process sequence including a boron diffusion, with corresponding implied open circuit voltage of about 720 mV. If the boron diffusion can be avoided, average lifetimes up to 3.0 and 6.6 ms can be achieved respectively, highlighting the excellent potential of n-type cast-grown materials.

  9. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Science.gov (United States)

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  10. Silicon crystals: Process for manufacturing wafer-like silicon crystals with a columnar structure

    Science.gov (United States)

    Authier, B.

    1978-01-01

    Wafer-like crystals suitable for making solar cells are formed by pouring molten Si containing suitable dopants into a mold of the desired shape and allowing it to solidify in a temperature gradient, whereby the large surface of the melt in contact with the mold is kept at less than 200 D and the free surface is kept at a temperature of 200-1000 D higher, but below the melting point of Si. The mold can also be made in the form of a slit, whereby the 2 sides of the mold are kept at different temperatures. A mold was milled in the surface of a cylindrical graphite block 200 mm in diameter. The granite block was induction heated and the bottom of the mold was cooled by means of a water-cooled Cu plate, so that the surface of the mold in contact with one of the largest surfaces of the melt was held at approximately 800 D. The free surface of the melt was subjected to thermal radiation from a graphite plate located 2 mm from the surface and heated to 1500 D. The Si crystal formed after slow cooling to room temperature had a columnar structure and was cut with a diamond saw into wafers approximately 500 mm thick. Solar cells prepared from these wafers had efficiencies of 10 to 11%.

  11. Theoretical analysis of improved efficiency of silicon-wafer solar cells with textured nanotriangular grating structure

    Science.gov (United States)

    Zhang, Yaoju; Zheng, Jun; Zhao, Xuesong; Ruan, Xiukai; Cui, Guihua; Zhu, Haiyong; Dai, Yuxing

    2018-03-01

    A practical model of crystalline silicon-wafer solar cells is proposed in order to enhance the light absorption and improve the conversion efficiency of silicon solar cells. In the model, the front surface of the silicon photovoltaic film is designed to be a textured-triangular-grating (TTG) structure, and the ITO contact film and the antireflection coating (ARC) of glass are coated on the TTG surface of silicon solar cells. The optical absorption spectrum of solar cells are simulated by applying the finite difference time domain method. Electrical parameters of the solar cells are calculated using two models with and without carrier loss. The effect of structure parameters on the performance of the TTG cell is discussed in detail. It is found that the thickness (tg) of the ARC, period (p) of grating, and base angle (θ) of triangle have a crucial influence on the conversion efficiency. The optimal structure of the TTG cell is designed. The TTG solar cell can produce higher efficiency in a wide range of solar incident angle and the average efficiency of the optimal TTG cell over 7:30-16:30 time of day is 8% higher than that of the optimal plane solar cell. In addition, the study shows that the bulk recombination of carriers has an influence on the conversion efficiency of the cell, the conversion efficiency of the actual solar cell with carrier recombination is reduced by 20.0% of the ideal cell without carrier recombination.

  12. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.

    2018-01-02

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  13. Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

    Science.gov (United States)

    Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

    2017-12-01

    Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

  14. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Science.gov (United States)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  15. High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

    CERN Document Server

    Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

    2003-01-01

    Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

  16. Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

    Science.gov (United States)

    Westerik, P. J.; Vijselaar, W. J. C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G. E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

  17. Effect of PECVD SiNx/SiOy Nx –Si interface property on surface passivation of silicon wafer

    International Nuclear Information System (INIS)

    Jia Xiao-Jie; Zhou Chun-Lan; Zhou Su; Wang Wen-Jing; Zhu Jun-Jie

    2016-01-01

    It is studied in this paper that the electrical characteristics of the interface between SiO y N x /SiN x stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiO y N x layer on interface parameters, such as interface state density Di t and fixed charge Q f , and the surface passivation quality of silicon are observed. Capacitance–voltage measurements reveal that inserting a thin SiO y N x layer between the SiN x and the silicon wafer can suppress Q f in the film and D it at the interface. The positive Q f and D it and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiO y N x film increasing. Prepared by deposition at a low temperature and a low ratio of N 2 O/SiH 4 flow rate, the SiO y N x /SiN x stacks result in a low effective surface recombination velocity (S eff ) of 6 cm/s on a p-type 1 Ω·cm–5 Ω·cm FZ silicon wafer. The positive relationship between S eff and D it suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. (paper)

  18. Dehydration and dehydroxylation of C-S-H phases synthesized on silicon wafers

    Science.gov (United States)

    Giraudo, Nicolas; Bergdolt, Samuel; Laye, Fabrice; Krolla, Peter; Lahann, Joerg; Thissen, Peter

    2018-03-01

    In this work, the synthesis of specific ultrathin Calcium-Silicate-Hydrate (C-S-H) phases on silicon wafers and their transformation into C-S phases is achieved. Specific mineral phases are identified, and the synthesis is successful controlled. Samples are investigated by means of Fourier Transform Infrared (FTIR) spectroscopy and X-ray Diffraction (XRD) and the results are analyzed based on first-principles calculations. When C-S-H phases are transformed into C-S phases, only a few reflexes are detected on XRD, and the coherent scattering domains decrease with the increment of the temperature and time of exposure. This behavior is explained by the Ca/Si changes, which are identified by changes in the FTIR spectra. A thermodynamic analysis is performed with the help of first-principles calculations to underline the influence of the calcium-to-silicon (Ca/Si) ratio in the process of dehydroxylation. To increase the Ca/Si ratio water is partially substituted by methanol at the synthesis. This is observed in the FTIR spectra and is confirmed by lower temperatures of dehydroxylation. The catalytic nature of calcium towards the dehydroxylation is confirmed. The core of this work lies in the preparation of a model, which perfection makes possible to model reactivity, stability and mechanical properties using first-principles calculations, and is the starting point for the synthesis of many others.

  19. Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

    International Nuclear Information System (INIS)

    Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

    2012-01-01

    Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

  20. Single electron transistor in pure silicon

    Science.gov (United States)

    Hu, Binhui

    As promising candidates for spin qubits, semiconductor quantum dots (QDs) have attracted tremendous research efforts. Currently most advanced progress is from GaAs QDs. Compared to GaAs, lateral QDs in 28silicon are expected to have a spin coherence time orders of magnitude longer, because 28Si has zero nuclear spin, and there is no hyperfine interaction between electron spins and nuclear spins. We have developed enhancement mode metal-oxide-semiconductor (MOS) single electron transistors (SETs) using pure silicon wafers with a bi-layer gated configuration. In an MOS-SET, the top gate is used to induce a two-dimensional electron gas (2DEG), just as in an MOS field effect transistor. The side gates deplete the 2DEG into a QD and two point contact channels; one connects the QD to the source reservoir, and the other connects the QD to the drain reservoir. We have systematically investigated the MOS-SETs at 4.2 K, and separately in a dilution refrigerator with a base temperature of 10 mK. The data show that there is an intrinsic QD in each point contact channel due to the local potential fluctuations in these SETs. However, after scaling down the SETs, we have found that the intrinsic QDs can be removed and the electrostatically defined dots dominate the device behavior, but these devices currently only work in the many-electron regime. In order to realize single electron confinement, it is necessary to continue scaling down the device and improving the interface quality. To explore the spin dynamics in silicon, we have investigated a single intrinsic QD by applying a magnetic field perpendicular to the sample surface. The magnetic field dependence of the ground-state and excited-state energy levels of the QD mostly can be explained by the Zeeman effect, with no obvious orbital effect up to 9 T. The two-electron singlet-triplet (ST) transition is first time directly observed in a silicon QD by excitation spectroscopy. In this ST transition, electron-electron Coulomb

  1. Fabrication of a mechanically aligned single-wafer MEMS turbine with turbocharger

    Science.gov (United States)

    Pelekies, S. O.; Schuhmann, T.; Gardner, W. G.; Camacho, A.; Protz, J. M.

    2010-10-01

    We describe the fabrication of a turbocharged, microelectromechanical system (MEMS) turbine. The turbine will be part of a standalone power unit and includes extra layers to connect the turbine to a generator. The project goal is to demonstrate the successful combination of several features, namely: silicon fusion bonding (SFB), a micro turbocharger [2], two rotors, mechanical alignment between two wafers [1], and the use of only one 5" silicon wafer. The dimension of the actual turbine casing will be 14mm. The turbine rotor will have a diameter of 8mm. Given these dimensions, MEMS processes are an adequate way to fabricate the device, but it will be necessary to stack up seven different layers to build the turbine, as it is not possible to construct it out of one thick wafer. SFB will be used for bonding because it permits the great precision necessary for high quality alignment. Yet a more precise alignment will be necessary between the layers that contain the turbine rotor, to decrease imbalance and guarantee operation at a very high rpm. To achieve these tight tolerances, a mechanical alignment feature announced by Liudi Jiang [1] is used. The alignment accuracy is expected to be around 200nm. Despite the fact that the turbine consists of multiple layers, it will be fabricated on only one silicon-on-insulator (SOI) wafer. As a result, all layers are exposed to the same process flow. The fabrication process includes MEMS technology as photolithography, nine deep reactive ion etching (DRIE) steps, and six SFB operations. A total of 14 masks are necessary for the fabrication.

  2. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Science.gov (United States)

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  3. Fabrication and Characterization of Ultra-Thin Silicon Crystalline Wafers for Photovoltaic Applications using a Stress-Induced Lift-off Method (Maken en karakterizeren van ultra-dunne kristallijne silicium substraten met een spanningsgeïnduceerde kliefmethode voor fotovoltaïsche toepassingen)

    OpenAIRE

    Masolin, Alex

    2012-01-01

    In order to reduce material-related costs, there is a need to develop new wafering techniques to produce thin (< 100 µm) crystalline silicon wafers for photovoltaic applications.This work presents a new kerf-free wafering process for single crystal silicon which relies only on thermo-mechanical treatments. The process is named SLIM-Cut (Stress-Induced LIft-off Method).The process flow is as follows: a layer of a material with a coefficient of thermal expansion (metal or polymer) significantly...

  4. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Science.gov (United States)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  5. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  6. Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

    Directory of Open Access Journals (Sweden)

    Di Di

    2014-01-01

    Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

  7. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    Science.gov (United States)

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  8. Design and fabrication of a planar patch-clamp substrate using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Zhang Zhenlong; Liu Xiangyang; Mao Yanli

    2009-01-01

    The planar patch-clamp technique has been applied to high throughput screening in drug discovery. The key feature of this technique is the fabrication of a planar patch-clamp substrate using appropriate materials. In this study, a planar patch-clamp substrate was designed and fabricated using a silicon-on-insulator (SOI) wafer. The access resistance and capacitance of SOI-based planar patch-clamp substrates are smaller than those of bulk silicon-based planar substrates, which will reduce the distributed RC noise.

  9. Linear self-assembly and grafting of gold nanorods into arrayed micrometer-long nanowires on a silicon wafer via a combined top-down/bottom-up approach.

    Science.gov (United States)

    Lestini, Elena; Andrei, Codrin; Zerulla, Dominic

    2018-01-01

    Macroscopically long wire-like arrangements of gold nanoparticles were obtained by controlled evaporation and partial coalescence of an aqueous colloidal solution of capped CTAB-Au nanorods onto a functionalised 3-mercaptopropyl trimethoxysilane (MPTMS) silicon substrate, using a removable, silicon wafer with a hydrophobic surface that serves as a "handrail" for the initial nanorods' linear self-assembly. The wire-like structures display a quasi-continuous pattern by thermal annealing of the gold nanorods when the solvent (i.e. water) is evaporated at temperatures rising from 20°C to 140°C. Formation of both single and self-replicating parallel 1D-superstructures consisting of two or even three wires is observed and explained under such conditions.

  10. Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

    Science.gov (United States)

    Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

    2013-08-20

    To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles rms is consistent with atomic force microscope measurements of the sidewalls.

  11. Self-diffusion in single crystalline silicon nanowires

    Science.gov (United States)

    Südkamp, T.; Hamdana, G.; Descoins, M.; Mangelinck, D.; Wasisto, H. S.; Peiner, E.; Bracht, H.

    2018-04-01

    Self-diffusion experiments in single crystalline isotopically controlled silicon nanowires with diameters of 70 and 400 nm at 850 and 1000 °C are reported. The isotope structures were first epitaxially grown on top of silicon substrate wafers. Nanowires were subsequently fabricated using a nanosphere lithography process in combination with inductively coupled plasma dry reactive ion etching. Three-dimensional profiling of the nanosized structure before and after diffusion annealing was performed by means of atom probe tomography (APT). Self-diffusion profiles obtained from APT analyses are accurately described by Fick's law for self-diffusion. Data obtained for silicon self-diffusion in nanowires are equal to the results reported for bulk silicon crystals, i.e., finite size effects and high surface-to-volume ratios do not significantly affect silicon self-diffusion. This shows that the properties of native point defects determined from self-diffusion in bulk crystals also hold for nanosized silicon structures with diameters down to 70 nm.

  12. Structure and resistivity of bismuth nanobelts in situ synthesized on silicon wafer through an ethanol-thermal method

    International Nuclear Information System (INIS)

    Gao Zheng; Qin Haiming; Yan Tao; Liu Hong; Wang Jiyang

    2011-01-01

    Bismuth nanobelts in situ grown on a silicon wafer were synthesized through an ethanol-thermal method without any capping agent. The structure of the bismuth belt–silicon composite nanostructure was characterized by scanning electron microscope, energy-dispersive X-ray spectroscopy, and high resolution transmission electron microscope. The nanobelt is a multilayered structure 100–800 nm in width and over 50 μm in length. One layer has a thickness of about 50 nm. A unique sword-like nanostructure is observed as the initial structure of the nanobelts. From these observations, a possible growth mechanism of the nanobelt is proposed. Current–voltage property measurements indicate that the resistivity of the nanobelts is slightly larger than that of the bulk bismuth material. - Graphical Abstract: TEM images, EDS, and electron diffraction pattern of bismuth nanobelts. Highlights: ► Bismuth nanobelts in situ grown on silicon wafer were achieved. ► Special bismuth–silicon nanostructure. ► Potential application in sensitive magnetic sensor and other electronic devices.

  13. Single crystalline silicon solar cells with rib structure

    Directory of Open Access Journals (Sweden)

    Shuhei Yoshiba

    2017-02-01

    Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  14. High efficiency heterojunction solar cells on n-type kerfless mono crystalline silicon wafers by epitaxial growth

    Science.gov (United States)

    Kobayashi, Eiji; Watabe, Yoshimi; Hao, Ruiying; Ravi, T. S.

    2015-06-01

    We present a heterojunction (HJ) solar cell on n-type epitaxially grown kerfless crystalline-silicon (c-Si) with a conversion efficiency of 22.5%. The total cell area is 243.4 cm2. The cell has a short-circuit current density of 38.6 mA/cm2, an open-circuit voltage of 735 mV, and a fill factor of 0.791. The key advantages and technological tasks of epitaxial wafers for HJ solar cells are discussed, in comparison with conventional n-type Czockralski c-Si wafers. The combination of HJ and kerfless technology can lead to high conversion efficiency with a potential at low cost.

  15. Thin Single Crystal Silicon Solar Cells on Ceramic Substrates: November 2009 - November 2010

    Energy Technology Data Exchange (ETDEWEB)

    Kumar, A.; Ravi, K. V.

    2011-06-01

    In this program we have been developing a technology for fabricating thin (< 50 micrometres) single crystal silicon wafers on foreign substrates. We reverse the conventional approach of depositing or forming silicon on foreign substrates by depositing or forming thick (200 to 400 micrometres) ceramic materials on high quality single crystal silicon films ~ 50 micrometres thick. Our key innovation is the fabrication of thin, refractory, and self-adhering 'handling layers or substrates' on thin epitaxial silicon films in-situ, from powder precursors obtained from low cost raw materials. This 'handling layer' has sufficient strength for device and module processing and fabrication. Successful production of full sized (125 mm X 125 mm) silicon on ceramic wafers with 50 micrometre thick single crystal silicon has been achieved and device process flow developed for solar cell fabrication. Impurity transfer from the ceramic to the silicon during the elevated temperature consolidation process has resulted in very low minority carrier lifetimes and resulting low cell efficiencies. Detailed analysis of minority carrier lifetime, metals analysis and device characterization have been done. A full sized solar cell efficiency of 8% has been demonstrated.

  16. Fabrication of a microstrip patch antenna integrated in low-resistance silicon wafer using a BCB dielectric

    Science.gov (United States)

    Tianxi, Wang; Mei, Han; Gaowei, Xu; Le, Luo

    2013-10-01

    This paper demonstrates a technique for microstrip patch antenna fabrication using a benzocyclobutene (BCB) dielectric. The most distinctive feature of this method is that the antenna is integrated on a low-resistance silicon wafer, and is fully compatible with the microwave multi-chip module packaging process. Low-permittivity dielectric BCB with excellent thermal and mechanical stability is employed to enhance the performance of the antenna. The as-fabricated antenna is characterized, and the experimental results show that the antenna resonates at 14.9 GHz with a 1.67% impedance bandwidth.

  17. Towards wafer-size graphene layers by atmospheric pressure graphitization of silicon carbide.

    Science.gov (United States)

    Emtsev, Konstantin V; Bostwick, Aaron; Horn, Karsten; Jobst, Johannes; Kellogg, Gary L; Ley, Lothar; McChesney, Jessica L; Ohta, Taisuke; Reshanov, Sergey A; Röhrl, Jonas; Rotenberg, Eli; Schmid, Andreas K; Waldmann, Daniel; Weber, Heiko B; Seyller, Thomas

    2009-03-01

    Graphene, a single monolayer of graphite, has recently attracted considerable interest owing to its novel magneto-transport properties, high carrier mobility and ballistic transport up to room temperature. It has the potential for technological applications as a successor of silicon in the post Moore's law era, as a single-molecule gas sensor, in spintronics, in quantum computing or as a terahertz oscillator. For such applications, uniform ordered growth of graphene on an insulating substrate is necessary. The growth of graphene on insulating silicon carbide (SiC) surfaces by high-temperature annealing in vacuum was previously proposed to open a route for large-scale production of graphene-based devices. However, vacuum decomposition of SiC yields graphene layers with small grains (30-200 nm; refs 14-16). Here, we show that the ex situ graphitization of Si-terminated SiC(0001) in an argon atmosphere of about 1 bar produces monolayer graphene films with much larger domain sizes than previously attainable. Raman spectroscopy and Hall measurements confirm the improved quality of the films thus obtained. High electronic mobilities were found, which reach mu=2,000 cm (2) V(-1) s(-1) at T=27 K. The new growth process introduced here establishes a method for the synthesis of graphene films on a technologically viable basis.

  18. Trap profiling at nanocavity bands in silicon wafers by means of capacitance-voltage measurements

    CERN Document Server

    Auriac, N

    2002-01-01

    Nanocavities are formed by He sup + -and H sup + -ion implantation in silicon single crystals, at the projected range R sub p , after post-implantation annealing. The present paper deals with the characterization of deep trap levels associated with such defects. P-type silicon single crystals were implanted using He sup + -and H sup + -ion beams, at an energy of 250 keV and to a dose of 3 x 10 sup 1 sup 6 cm sup - sup 2. Capacitance-voltage (C-V) profiling and deep-level transient spectroscopy (DLTS) techniques were used to determine the density profile and the energy levels of deep traps in the gap. In implanted and post-annealed samples a quasi-triangular profile of the space charge is revealed around R sub p by C-V profiling, and the space charge density reaches 10 sup 1 sup 6 cm sup - sup 3. DLTS suggests that trap levels are located at 0.4 eV above the valence band, with a maximum density around 10 sup 1 sup 5 cm sup - sup 3 at R sub p. The sign and distribution of the space charge for depletion in He su...

  19. Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

    Science.gov (United States)

    Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

    2013-04-01

    In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

  20. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    International Nuclear Information System (INIS)

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  1. Exploration of surface hydrophilic properties on AISI 304 stainless steel and silicon wafer against aging after atmospheric pressure plasma treatment

    Science.gov (United States)

    Chuang, Shang-I.; Duh, Jenq-Gong

    2014-11-01

    The aim of this work is to seek the enhanced surface hydrophilic properties on AISI 304 stainless steel and silicon wafer after atmospheric pressure plasma treatment using a specifically designed atmospheric pressure plasma jet. The aging tendency of surface hydrophilic property under air is highlighted. It is concluded that both of the silicon wafer and stainless steel treated with plasma generated from supply gas of argon 15 slm mixed with oxygen 40 sccm shows a better tendency on remaining high water contact angle as compared to that with pure argon and nitrogen addition. Additional peaks of O I (777, 844 nm), O II (408 nm) are detected by optical emission spectroscope indicating the presence of the oxygen radicals and ionic species, which interact with surfaces and thus contribute to low water contact angle (WCA) surfaces. Moreover, the result acquired from X-ray photoelectron spectroscopy (XPS) indicates that the increase in the oxygen-related bonding exhibits a better contribution on remaining high surface energy over a period of time.

  2. Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

    Energy Technology Data Exchange (ETDEWEB)

    Takahara, Hikari, E-mail: hikari@rigaku.co.jp [Rigaku Corp., 14-8 Akaoji-cho, Takatsuki, Osaka 569-1146 (Japan); Mori, Yoshihiro [Horiba Ltd., 2 Miyanohigashi, Kisshoin, Minami-ku, Kyoto 601-8510 (Japan); Shibata, Harumi [SUMCO Corporation, Seavance North, 1-2-1 Shibaura, Minato-ku, Tokyo 105-8634 (Japan); Shimazaki, Ayako [Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522 (Japan); Shabani, Mohammad B. [Mitsubishi Material Corporation, 1-297, Kitabukuro-cho, Omiya-ku, Saitama 330-8508 (Japan); Yamagami, Motoyuki [Rigaku Corp., 14-8 Akaoji-cho, Takatsuki, Osaka 569-1146 (Japan); Yabumoto, Norikuni [Analysis Atelier Co., 4-36-4, Yoyogi, Shibuya-ku, Tokyo 151-0053 (Japan); Nishihagi, Kazuo [Horiba Ltd., 2 Miyanohigashi, Kisshoin, Minami-ku, Kyoto 601-8510 (Japan); Gohshi, Yohichi [Tsukuba University, 1-1-1, Tennodai, Tsukuba, Ibaraki 305-8571 (Japan)

    2013-12-01

    Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10{sup 9} and 5 × 10{sup 10} atoms/cm{sup 2} Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO{sub 2}, silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10{sup 10} atoms/cm{sup 2}. • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies.

  3. Investigation of transparent conductive electrodes for application in heterojunction silicon wafer solar cells

    Science.gov (United States)

    Huang, Mei

    This thesis focuses on the fabrication, characterisation and analysis of high-quality transparent conductive electrodes for application in heterojunction silicon wafer solar cells. Indium tin oxide (ITO) is the material of interest, which is investigated by both the pulsed direct current (PDC) and the unbalanced radio frequency (URF) magnetron sputtering methods. The influences of deposition parameters and annealing conditions on the performance of the ITO films are studied and the optimal deposition conditions are established for both systems. The results show that ITO films with low crystallinity have degraded electrical properties after annealing at 200°C. The degradation of ITO film properties is associated with the excess scattering centres formed along with the newly crystallised regions, which significantly deteriorate the electron mobility. The relationships between the deposition conditions and the material properties are investigated by X-ray photoelectron spectroscopy (XPS). It is shown that the major electron donors in amorphous ITO films are oxygen vacancies. With the increase of the film crystallinity, the doping efficiency of Sn atoms improves. The substitutional Sn atoms contribute additional free electrons in ITO films, which improve the film's conductivity. It is also shown that the darkening of ITO films observed in PDC sputtering is due to the existence of second phase Sn3O4, which severely darken the ITO sample when it is excessively present in the surface layer and in the bulk of the film. The hydrogen gas used in the URF sputtering method is shown to effectively lower the concentration of free electrons. Benefiting from the reduced electron scattering by ionized dopant atoms, the ITO films deposited with hydrogen gas maintain a high electron mobility. Besides the ITO material properties, the sputter induced damages are also studied. It is shown that in PDC sputtering the ion bombardment damage is the primary damage contributor, while plasma

  4. Charge collection measurements with p-type Magnetic Czochralski silicon single pad detectors

    International Nuclear Information System (INIS)

    Tosi, C.; Bruzzi, M.; Macchiolo, A.; Scaringella, M.; Petterson, M.K.; Sadrozinski, H.F.-W.; Betancourt, C.; Manna, N.; Creanza, D.; Boscardin, M.; Piemonte, C.; Zorzi, N.; Borrello, L.; Messineo, A.

    2007-01-01

    The charge collected from beta source particles in single pad detectors produced on p-type Magnetic Czochralski (MCz) silicon wafers has been measured before and after irradiation with 26 MeV protons. After a 1 MeV neutron equivalent fluence of 1x10 15 cm -2 the collected charge is reduced to 77% at bias voltages below 900 V. This result is compared with previous results from charge collection measurements

  5. Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

    Energy Technology Data Exchange (ETDEWEB)

    Rouault de Coligny, P.

    2002-09-15

    This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

  6. Room-temperature direct bonding of silicon and quartz glass wafers

    Science.gov (United States)

    Wang, Chenxi; Wang, Yuan; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2017-05-01

    We demonstrate a facile bonding method for combining Si/Si, Si/quartz, and quartz/quartz wafers at room temperature (˜25 °C) using a one-step O2/CF4/H2O plasma treatment. The bonding strengths were significantly improved by adding a small amount of CF4 into the oxygen plasma, such that reliable and tight bonding was obtained after storage in ambient air for 24 h, even without employing heat. Moreover, by introducing water vapor during O2/CF4 plasma treatment, uniform wafer bonding was spontaneously achieved without applying an external force. The fluorinated surface asperities appear to be softened more easily by the interfacial water stress corrosion, enabling reliable bonding at room temperature. Additionally, adding an optimized amount of water vapor to the O2/CF4 plasma increases sufficiently the amount of hydroxyl groups without eliminating the CF4 effect. The additional water adsorbed on the surface may help to close the gap between the bonded wafers, resulting in better bonding efficiency.

  7. Development of an on-line isotope dilution laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS) method for determination of boron in silicon wafers.

    Science.gov (United States)

    Yang, Chao-Kai; Chi, Po-Hsiang; Lin, Yong-Chine; Sun, Yuh-Chang; Yang, Mo-Hsiung

    2010-01-15

    A method has been developed based on an on-line isotope dilution technique couple with laser ablation/inductively coupled plasma mass spectrometry (LA-ICP-MS), for the determination of boron in p-type silicon wafers. The laser-ablated sample aerosol was mixed on-line with an enriched boron aerosol supplied continuously using a conventional nebulization system. Upon mixing the two aerosol streams, the isotope ratio of boron changed rapidly and was then recorded by the ICP-MS system for subsequent quantification based on the isotope dilution principle. As an on-line solid analysis method, this system accurately quantifies boron concentrations in silicon wafers without the need for an internal or external solid reference standard material. Using this on-line isotope dilution technique, the limit of detection for boron in silicon wafers is 2.8x10(15)atomscm(-3). The analytical results obtained using this on-line methodology agree well with those obtained using wet chemical digestion methods for the analysis of p-type silicon wafers containing boron concentrations ranging from 1.0x10(16) to 9.6x10(18)atomscm(-3).

  8. Characterization of deliberately nickel-doped silicon wafers and solar cells. [microstructure, electrical properties, and energy conversion efficiency

    Science.gov (United States)

    Salama, A. M.

    1980-01-01

    Microstructural and electrical evaluation tests were performed on nickel-doped p-type silicon wafers before and after solar cell fabrication. The concentration levels of nickel in silicon were 5 x 10 to the 14th power, 4 x 10 to the 15th power, and 8 x 10 to the 15th power atoms/cu cm. It was found that nickel precipitated out during the growth process in all three ingots. Clumps of precipitates, some of which exhibited star shape, were present at different depths. If the clumps are distributed at depths approximately 20 micron apart and if they are larger than 10 micron in diameter, degradation occurs in solar cell electrical properties and cell conversion efficiency. The larger the size of the precipitate clump, the greater the degradation in solar cell efficiency. A large grain boundary around the cell effective area acted as a gettering center for the precipitates and impurities and caused improvement in solar cell efficiency. Details of the evaluation test results are given.

  9. Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

    Directory of Open Access Journals (Sweden)

    Ali Attaran

    2014-01-01

    Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

  10. Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Takaura, Norikatsu

    1997-10-01

    As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular

  11. Large Out-of-Plane Displacement Bistable Electromagnetic Microswitch on a Single Wafer.

    Science.gov (United States)

    Miao, Xiaodan; Dai, Xuhan; Huang, Yi; Ding, Guifu; Zhao, Xiaolin

    2016-05-05

    This paper presents a bistable microswitch fully batch-fabricated on a single glass wafer, comprising of a microactuator, a signal transformer, a microspring and a permanent magnet. The bistable mechanism of the microswitch with large displacement of 160 μm depends on the balance of the magnetic force and elastic force. Both the magnetic force and elastic force were optimized by finite-element simulation to predict the reliable of the device. The prototype was fabricated and characterized. By utilizing thick laminated photoresist sacrificial layer, the large displacement was obtained to ensure the insulation of the microswitch. The testing results show that the microswitch realized the bistable mechanism at a 3-5 V input voltage and closed in 0.96 ms, which verified the simulation.

  12. Damage-free polishing of monocrystalline silicon wafers without chemical additives

    International Nuclear Information System (INIS)

    Biddut, A.Q.; Zhang, L.C.; Ali, Y.M.; Liu, Z.

    2008-01-01

    This investigation explores the possibility and identifies the mechanism of damage-free polishing of monocrystalline silicon without chemical additives. Using high resolution electron microscopy and contact mechanics, the study concludes that a damage-free polishing process without chemicals is feasible. All forms of damages, such as amorphous Si, dislocations and plane shifting, can be eliminated by avoiding the initiation of the β-tin phase of silicon during polishing. When using 50 nm abrasives, the nominal pressure to achieve damage-free polishing is 20 kPa

  13. Three-dimensional numerical analysis of hybrid heterojunction silicon wafer solar cells with heterojunction rear point contacts

    Directory of Open Access Journals (Sweden)

    Zhi Peng Ling

    2015-07-01

    Full Text Available This paper presents a three-dimensional numerical analysis of homojunction/heterojunction hybrid silicon wafer solar cells, featuring front-side full-area diffused homojunction contacts and rear-side heterojunction point contacts. Their device performance is compared with conventional full-area heterojunction solar cells as well as conventional diffused solar cells featuring locally diffused rear point contacts, for both front-emitter and rear-emitter configurations. A consistent set of simulation input parameters is obtained by calibrating the simulation program with intensity dependent lifetime measurements of the passivated regions and the contact regions of the various types of solar cells. We show that the best efficiency is obtained when a-Si:H is used for rear-side heterojunction point-contact formation. An optimization of the rear contact area fraction is required to balance between the gains in current and voltage and the loss in fill factor with shrinking rear contact area fraction. However, the corresponding optimal range for the rear-contact area fraction is found to be quite large (e.g. 20-60 % for hybrid front-emitter cells. Hybrid rear-emitter cells show a faster drop in the fill factor with decreasing rear contact area fraction compared to front-emitter cells, stemming from a higher series resistance contribution of the rear-side a-Si:H(p+ emitter compared to the rear-side a-Si:H(n+ back surface field layer. Overall, we show that hybrid silicon solar cells in a front-emitter configuration can outperform conventional heterojunction silicon solar cells as well as diffused solar cells with rear-side locally diffused point contacts.

  14. Precipitation in silicon wafers after high temperature preanneal studied by X-ray diffraction methods

    Czech Academy of Sciences Publication Activity Database

    Meduňa, M.; Růžička, J.; Caha, O.; Buršík, Jiří; Svoboda, Milan

    2012-01-01

    Roč. 407, č. 15 (2012), s. 3002-3005 ISSN 0921-4526 R&D Projects: GA ČR(CZ) GA202/09/1013 Institutional research plan: CEZ:AV0Z20410507 Keywords : silicon * interstitial oxygen * precipitation Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 1.327, year: 2012

  15. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  16. Control of grown-in defects and oxygen precipitates in silicon wafers with DZ-IG structure by ultrahigh-temperature rapid thermal oxidation

    Science.gov (United States)

    Maeda, Susumu; Sudo, Haruo; Okamura, Hideyuki; Nakamura, Kozo; Sueoka, Koji; Izunome, Koji

    2018-04-01

    A new control technique for achieving compatibility between crystal quality and gettering ability for heavy metal impurities was demonstrated for a nitrogen-doped Czochralski silicon wafer with a diameter of 300 mm via ultra-high temperature rapid thermal oxidation (UHT-RTO) processing. We have found that the DZ-IG structure with surface denuded zone and the wafer bulk with dense oxygen precipitates were formed by the control of vacancies in UHT-RTO process at temperature exceeding 1300 °C. It was also confirmed that most of the void defects were annihilated from the sub-surface of the wafer due to the interstitial Si atoms that were generated at the SiO2/Si interface. These results indicated that vacancies corresponded to dominant species, despite numerous interstitial silicon injections. We have explained these prominent features by the degree of super-saturation for the interstitial silicon due to oxidation and the precise thermal properties of the vacancy and interstitial silicon.

  17. Relaxation of vacancy depth profiles in silicon wafers: A low apparent diffusivity of vacancy species

    OpenAIRE

    Voronkov, Vladimir V.; Falster, Robert; Pichler, Peter

    2014-01-01

    Vacancy depth profiles in silicon wafersinstalled by Rapid Thermal Annealing and monitored by Pt diffusionshow, upon subsequent annealing at 975 or 950 °C, a peculiar evolution: the concentration profile goes down without any trace of vacancy out-diffusion. The estimated apparent diffusivity is less than 1E7 cm2/s at 975 °C. The monitored vacancy species is tentatively identified as a "slow vacancy" that was recently concluded to exist along with other (highly mobile) vacancy species.

  18. Mechanism of single atom switch on silicon

    DEFF Research Database (Denmark)

    Quaade, Ulrich; Stokbro, Kurt; Thirstrup, C.

    1998-01-01

    We demonstrate single atom switch on silicon which operates by displacement of a hydrogen atom on the silicon (100) surface at room temperature. We find two principal effects by which the switch is controlled: a pronounced maximum of the switching probability as function of sample bias...... and a preferred direction of switching as function of STM tip position. Based on first principles calculations, are show that this behaviour is due to a novel mechanism involving an electronic excitation of a localized surface resonance. (C) 1998 Elsevier Science B.V. All rights reserved....

  19. Toward the synthesis of wafer-scale single-crystal graphene on copper foils.

    Science.gov (United States)

    Yan, Zheng; Lin, Jian; Peng, Zhiwei; Sun, Zhengzong; Zhu, Yu; Li, Lei; Xiang, Changsheng; Samuel, E Loïc; Kittrell, Carter; Tour, James M

    2012-10-23

    In this research, we constructed a controlled chamber pressure CVD (CP-CVD) system to manipulate graphene's domain sizes and shapes. Using this system, we synthesized large (~4.5 mm(2)) single-crystal hexagonal monolayer graphene domains on commercial polycrystalline Cu foils (99.8% purity), indicating its potential feasibility on a large scale at low cost. The as-synthesized graphene had a mobility of positive charge carriers of ~11,000 cm(2) V(-1) s(-1) on a SiO(2)/Si substrate at room temperature, suggesting its comparable quality to that of exfoliated graphene. The growth mechanism of Cu-based graphene was explored by studying the influence of varied growth parameters on graphene domain sizes. Cu pretreatments, electrochemical polishing, and high-pressure annealing are shown to be critical for suppressing graphene nucleation site density. A pressure of 108 Torr was the optimal chamber pressure for the synthesis of large single-crystal monolayer graphene. The synthesis of one graphene seed was achieved on centimeter-sized Cu foils by optimizing the flow rate ratio of H(2)/CH(4). This work should provide clear guidelines for the large-scale synthesis of wafer-scale single-crystal graphene, which is essential for the optimized graphene device fabrication.

  20. Process design and simulation for optimizing the oxygen concentration in Czochralski-grown single-crystal silicon

    International Nuclear Information System (INIS)

    Jung, Y. J.; Kim, W. K.; Jung, J. H.

    2014-01-01

    The highest-concentration impurity in a single-crystal silicon ingot is oxygen, which infiltrates the ingot during growth stage. This oxygen adversely affects the wafer is quality. This study was aimed at finding an optimal design for the Czochralski (Cz) process to enable high-quality and low cost (by reducing power consumption) wafer production by controlling the oxygen concentration in the silicon ingots. In the Cz process, the characteristics of silicon ingots during crystallization are greatly influenced by the design and the configuration of the hot zone, and by crystallization rate. In order to identify process conditions for obtaining an optimal oxygen concentration of 11 - 13 ppma (required for industrial-grade ingots), designed two shield shapes for the hot zone. Furthermore, oxygen concentrations corresponding to these two shapes were compared by evaluating each shape at five different production speeds. In addition, simulations were performed to identify the optimal shield design for industrial applications.

  1. Process design and simulation for optimizing the oxygen concentration in Czochralski-grown single-crystal silicon

    Energy Technology Data Exchange (ETDEWEB)

    Jung, Y. J.; Kim, W. K.; Jung, J. H. [Yeungnam University, Gyeongsan (Korea, Republic of)

    2014-08-15

    The highest-concentration impurity in a single-crystal silicon ingot is oxygen, which infiltrates the ingot during growth stage. This oxygen adversely affects the wafer is quality. This study was aimed at finding an optimal design for the Czochralski (Cz) process to enable high-quality and low cost (by reducing power consumption) wafer production by controlling the oxygen concentration in the silicon ingots. In the Cz process, the characteristics of silicon ingots during crystallization are greatly influenced by the design and the configuration of the hot zone, and by crystallization rate. In order to identify process conditions for obtaining an optimal oxygen concentration of 11 - 13 ppma (required for industrial-grade ingots), designed two shield shapes for the hot zone. Furthermore, oxygen concentrations corresponding to these two shapes were compared by evaluating each shape at five different production speeds. In addition, simulations were performed to identify the optimal shield design for industrial applications.

  2. Neutron activation analysis of low-level element contents in silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Goerner, W. [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Berger, A. [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Niese, S. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Koehler, M. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Matthes, M. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Gawlik, D. [Hahn-Meitner-Institut, Berlin (Germany)

    1997-03-01

    Semiconductor silicon is among the purest materials having ever been produced by modern technology. Thus, it is quite suitable as a primary reference material validating the correctness and the detection capabilities of developed analytical methods. Among them neutron activation analysis plays a competitive role. The U.S. National Institute of Science and Technology (NIST) has initiated and carried out an interlaboratory comparison in order to study the spread of analytical results worldwide evolved by several laboratories dealing with specimens of extreme purity. The outcome of the experiment was intended to review the capabilities of NAA as well as to differentiate between bulk and surface contamination. (orig./DG)

  3. Understanding the Fundamental Properties of Transfer-Free, Wafer-Level Graphene on Silicon and its Potential for Micro- and Nanodevices

    Science.gov (United States)

    2015-06-18

    quality, uniform bilayer graphene directly was realized on silicon wafers, at temperatures compatible with conventional semiconductor processing. The...conventional semiconductor processing. We demonstrated the highest doping ever reported for graphene (~ 1015 at cm-2, in the same order of magnitude as the...compatible with conventional semiconductor processing. The sheet resistance of the graphene is about 25 ohms/square, unprecedented for Distribution A

  4. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    International Nuclear Information System (INIS)

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  5. Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

    Directory of Open Access Journals (Sweden)

    Nigel T. Maidment

    2008-08-01

    Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

  6. Nanowire decorated, ultra-thin, single crystalline silicon for photovoltaic devices

    Science.gov (United States)

    Aurang, Pantea; Turan, Rasit; Emrah Unalan, Husnu

    2017-10-01

    Reducing silicon (Si) wafer thickness in the photovoltaic industry has always been demanded for lowering the overall cost. Further benefits such as short collection lengths and improved open circuit voltages can also be achieved by Si thickness reduction. However, the problem with thin films is poor light absorption. One way to decrease optical losses in photovoltaic devices is to minimize the front side reflection. This approach can be applied to front contacted ultra-thin crystalline Si solar cells to increase the light absorption. In this work, homojunction solar cells were fabricated using ultra-thin and flexible single crystal Si wafers. A metal assisted chemical etching method was used for the nanowire (NW) texturization of ultra-thin Si wafers to compensate weak light absorption. A relative improvement of 56% in the reflectivity was observed for ultra-thin Si wafers with the thickness of 20 ± 0.2 μm upon NW texturization. NW length and top contact optimization resulted in a relative enhancement of 23% ± 5% in photovoltaic conversion efficiency.

  7. Nanowire decorated, ultra-thin, single crystalline silicon for photovoltaic devices.

    Science.gov (United States)

    Aurang, Pantea; Turan, Rasit; Unalan, Husnu Emrah

    2017-10-06

    Reducing silicon (Si) wafer thickness in the photovoltaic industry has always been demanded for lowering the overall cost. Further benefits such as short collection lengths and improved open circuit voltages can also be achieved by Si thickness reduction. However, the problem with thin films is poor light absorption. One way to decrease optical losses in photovoltaic devices is to minimize the front side reflection. This approach can be applied to front contacted ultra-thin crystalline Si solar cells to increase the light absorption. In this work, homojunction solar cells were fabricated using ultra-thin and flexible single crystal Si wafers. A metal assisted chemical etching method was used for the nanowire (NW) texturization of ultra-thin Si wafers to compensate weak light absorption. A relative improvement of 56% in the reflectivity was observed for ultra-thin Si wafers with the thickness of 20 ± 0.2 μm upon NW texturization. NW length and top contact optimization resulted in a relative enhancement of 23% ± 5% in photovoltaic conversion efficiency.

  8. Corporate array of micromachined dipoles on silicon wafer for 60 GHz communication systems

    KAUST Repository

    Sallam, M. O.

    2013-03-01

    In this paper, an antenna array operating at 60 GHz and realized on 0.675 mm thick silicon substrate is presented. The array is constructed using four micromachined half-wavelength dipoles fed by a corporate feeding network. Isolation between the antenna array and its feeding network is achieved via a ground plane. This arrangement leads to maximizing the broadside radiation with relatively high front-to-back ratio. Simulations have been carried out using both HFSS and CST, which showed very good agreement. Results reveal that the proposed antenna array has good radiation characteristics, where the directivity, gain, and radiation efficiency are around 10.5 dBi, 9.5 dBi, and 79%, respectively. © 2013 IEEE.

  9. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    International Nuclear Information System (INIS)

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  10. Solar cell structure incorporating a novel single crystal silicon material

    Science.gov (United States)

    Pankove, Jacques I.; Wu, Chung P.

    1983-01-01

    A novel hydrogen rich single crystal silicon material having a band gap energy greater than 1.1 eV can be fabricated by forming an amorphous region of graded crystallinity in a body of single crystalline silicon and thereafter contacting the region with atomic hydrogen followed by pulsed laser annealing at a sufficient power and for a sufficient duration to recrystallize the region into single crystal silicon without out-gassing the hydrogen. The new material can be used to fabricate semiconductor devices such as single crystal silicon solar cells with surface window regions having a greater band gap energy than that of single crystal silicon without hydrogen.

  11. Optothermal response of a single silicon nanotip

    Science.gov (United States)

    Vella, A.; Shinde, D.; Houard, J.; Silaeva, E.; Arnoldi, L.; Blum, I.; Rigutti, L.; Pertreux, E.; Maioli, P.; Crut, A.; Del Fatti, N.

    2018-02-01

    The optical properties and thermal dynamics of conical single silicon nanotips are experimentally and theoretically investigated. The spectral and spatial dependencies of their optical extinction are quantitatively measured by spatial modulation spectroscopy (SMS). A nonuniform optical extinction along the tip axis and an enhanced near-infrared absorption, as compared to bulk crystalline silicon, are evidenced. This information is a key input for computing the thermal response of single silicon nanotips under ultrafast laser illumination, which is investigated by laser assisted atom probe tomography (La-APT) used as a highly sensitive temperature probe. A combination of these two experimental techniques and comparison with modeling also permits us to elucidate the impact of thermal effects on the laser assisted field evaporation process. Extension of this coupled approach opens up future perspectives for the quantitative study of the optical and thermal properties of a wide class of individual nano-objects, in particular elongated ones such as nanotubes, nanowires, and nanocones, which constitute promising nanosources for electron and/or ion emission.

  12. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  13. Single-Event Effects in Silicon and Silicon Carbide Power Devices

    Science.gov (United States)

    Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

    2014-01-01

    NASA Electronics Parts and Packaging program-funded activities over the past year on single-event effects in silicon and silicon carbide power devices are presented, with focus on SiC device failure signatures.

  14. Simulation of V/G During Φ450 mm Czochralski Grown Silicon Single Crystal Growth Under the Different Crystal and Crucible Rotation Rates

    Directory of Open Access Journals (Sweden)

    Guan X J

    2016-01-01

    Full Text Available For discovering the principle of processing parameter combination for the stable growth and better wafer quality of Φ450 mm Czochralski grown silicon single crystal (shortly called Cz silicon crystal, the effects of crystal rotation rate and crucible one on the V/G ratio were simulated by using CGSim software. The results show that their effect laws on the V/G ratio for Φ450 mm Cz silicon crystal growth are some different from that for Φ200 mm Cz silicon one, and the effects of crucible rotation rate are relatively smaller than that of crystal one and its increasing only makes the demarcation point between two regions with different V/G ratio variations outward move along radial direction, and it promotes the wafer quality to weaken crystal rotation rate and strengthen crucible one.

  15. A facility for plastic deformation of germanium single-crystal wafers

    DEFF Research Database (Denmark)

    Lebech, B.; Theodor, K.; Breiting, B.

    1998-01-01

    . All movements and temperature changes are done by a robot via a PLC-control system. Two nine-crystal focusing monochromators (54 x 116 and 70 x 116 mm(2)) made from 100 wafers with average mosaicity similar to 13' have been constructed. Summaries of the test results are presented. (C) 1998 Elsevier...

  16. Composite single crystal silicon scan mirror substrates, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Single crystal silicon is a desirable mirror substrate for scan mirrors in space telescopes. As diameters of mirrors become larger, existing manufacturing...

  17. Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

    International Nuclear Information System (INIS)

    Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

    1993-01-01

    The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

  18. The formation of an amorphous interface layer precedes the onset of the nucleation of an orderly carbon structure on a silicon wafer

    Science.gov (United States)

    Belay, Kalayu; Jackson, Jeremy; Johnson, Kevin

    2002-03-01

    A thin film was grown by plasma assisted chemical vapor deposition (PACVD) process on a heated silicon wafer substrate. The reactants in the process were 298pressure and substrate temperature were 40 Torr and 9000 C respectively. The silicon wafer was scratched with diamond dust to increase the rate of nucleation. Upon absorbing energy from microwave generated plasma the methane breaks down freeing the carbon atoms, which are deposited on the substrate. The system was run for ten hours. A seemingly uniform milky thin layer of film was formed on the substrate. Initial characterization using an X-ray diffractometer was unable to detect the presence of any orderly structure of carbon atoms forming diamond or graphite. This leads us to believe that an amorphous interlayer is formed before diamond or other diamond like structure is formed on the substrate. Results of additional investigations and interpretations will be reported. *This research was supported in part by a grant from NASA MURED to Florida A&M University.

  19. Through-Wafer Optical Interconnects For Multi-Wafer Wafer-Scale Integrated Architectures

    Science.gov (United States)

    Hornak, L. A.; Tewksbury, S. K.; Hatamian, M.; Ligtenberg, A.; Sugla, B.; Franzon, P.

    1986-12-01

    Hybrid mounting of optical components, combined perhaps with integrated optical waveguides and lenses on a large area silicon, wafer-scale integrated (WSI) electronic circuit provides one potential approach to combine advanced electronic and photonic functions. The desire to achieve a high degree of parallelism in multi-wafer WSI-based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and. providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While presently it is difficult for optical interconnects to compete with electrical interconnects in the wafer plane, it is appropriate to look at vertical optical interconnections between wafer planes since the corresponding conductive structures would be large in area and may impede system repairability. The ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages for multi-wafer WSI or other dense three-dimensional architectures. However, while optical waveguides are readily fabricated in the plane of the wafer, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one straightforward method of meeting this criterion. Using optical device technology operating at wavelengths beyond the ≍1.1μm Si absorption cutoff, low loss, through-wafer propagation between WSI circuit boards can be achieved over the distances of interest (≍1mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that the transmittance can be raised to ≍77% for n-type and to ≍97% for p-type silicon. Optical interconnect source

  20. Silicon etching using only Oxygen at high temperature: An alternative approach to Si micro-machining on 150 mm Si wafers

    Science.gov (United States)

    Chai, Jessica; Walker, Glenn; Wang, Li; Massoubre, David; Tan, Say Hwa; Chaik, Kien; Hold, Leonie; Iacopi, Alan

    2015-12-01

    Using a combination of low-pressure oxygen and high temperatures, isotropic and anisotropic silicon (Si) etch rates can be controlled up to ten micron per minute. By varying the process conditions, we show that the vertical-to-lateral etch rate ratio can be controlled from 1:1 isotropic etch to 1.8:1 anisotropic. This simple Si etching technique combines the main respective advantages of both wet and dry Si etching techniques such as fast Si etch rate, stiction-free, and high etch rate uniformity across a wafer. In addition, this alternative O2-based Si etching technique has additional advantages not commonly associated with dry etchants such as avoiding the use of halogens and has no toxic by-products, which improves safety and simplifies waste disposal. Furthermore, this process also exhibits very high selectivity (>1000:1) with conventional hard masks such as silicon carbide, silicon dioxide and silicon nitride, enabling deep Si etching. In these initial studies, etch rates as high as 9.2 μm/min could be achieved at 1150 °C. Empirical estimation for the calculation of the etch rate as a function of the feature size and oxygen flow rate are presented and used as proof of concepts.

  1. Silicon etching using only Oxygen at high temperature: An alternative approach to Si micro-machining on 150 mm Si wafers.

    Science.gov (United States)

    Chai, Jessica; Walker, Glenn; Wang, Li; Massoubre, David; Tan, Say Hwa; Chaik, Kien; Hold, Leonie; Iacopi, Alan

    2015-12-04

    Using a combination of low-pressure oxygen and high temperatures, isotropic and anisotropic silicon (Si) etch rates can be controlled up to ten micron per minute. By varying the process conditions, we show that the vertical-to-lateral etch rate ratio can be controlled from 1:1 isotropic etch to 1.8:1 anisotropic. This simple Si etching technique combines the main respective advantages of both wet and dry Si etching techniques such as fast Si etch rate, stiction-free, and high etch rate uniformity across a wafer. In addition, this alternative O2-based Si etching technique has additional advantages not commonly associated with dry etchants such as avoiding the use of halogens and has no toxic by-products, which improves safety and simplifies waste disposal. Furthermore, this process also exhibits very high selectivity (>1000:1) with conventional hard masks such as silicon carbide, silicon dioxide and silicon nitride, enabling deep Si etching. In these initial studies, etch rates as high as 9.2 μm/min could be achieved at 1150 °C. Empirical estimation for the calculation of the etch rate as a function of the feature size and oxygen flow rate are presented and used as proof of concepts.

  2. Productivity Improvement for the SHX--SEN's Single-Wafer High-Current Ion Implanter

    International Nuclear Information System (INIS)

    Ninomiya, Shiro; Ochi, Akihiro; Kimura, Yasuhiko; Yumiyama, Toshio; Kudo, Tetsuya; Kurose, Takeshi; Kariya, Hiroyuki; Tsukihara, Mitsukuni; Ishikawa, Koji; Ueno, Kazuyoshi

    2011-01-01

    Equipment productivity is a critical issue for device fabrication. For ion implantation, productivity is determined both by ion current at the wafer and by utilization efficiency of the ion beam. Such improvements not only result in higher fabrication efficiency but also reduce consumption of both electrical power and process gases. For high-current ion implanters, reduction of implant area is a key factor to increase efficiency. SEN has developed the SAVING system (Scanning Area Variation Implantation with Narrower Geometrical pattern) to address this opportunity. In this paper, three variations of the SAVING system are introduced along with discussion of their effects on fab productivity.

  3. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    NARCIS (Netherlands)

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  4. Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

    International Nuclear Information System (INIS)

    Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

    2009-01-01

    Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

  5. Generation of vacancy cluster-related defects during single MeV silicon ion implantation of silicon

    Energy Technology Data Exchange (ETDEWEB)

    Pastuović, Ž., E-mail: zkp@ansto.gov.au [Australian Nuclear Science and Technology Organization, Locked Bag 2001, Kirrawee DC NSW 2232 (Australia); Capan, I. [Ruđer Bošković Institute, Bijenička cesta 54, P.O. Box 180, 10002 Zagreb (Croatia); Siegele, R. [Australian Nuclear Science and Technology Organization, Locked Bag 2001, Kirrawee DC NSW 2232 (Australia); Jačimović, R. [Jozef Stefan Institute, 1000 Ljubljana (Slovenia); Forneris, J. [Physics Department and NIS Excellence Centre, University of Torino, INFN – sez. Torino, CNISM – sez. Torino, via P. Giuria 1, 10125 Torino (Italy); Cohen, D.D. [Australian Nuclear Science and Technology Organization, Locked Bag 2001, Kirrawee DC NSW 2232 (Australia); Vittone, E. [Physics Department and NIS Excellence Centre, University of Torino, INFN – sez. Torino, CNISM – sez. Torino, via P. Giuria 1, 10125 Torino (Italy)

    2014-08-01

    Deep Level Transient Spectroscopy (DLTS) has been used to study defects formed in bulk silicon after implantation of 8.3 MeV {sup 28}Si{sup 3+} ions at room temperature. For this study, Schottky diodes prepared from n-type Czohralski-grown silicon wafers have been implanted in the single ion regime up to fluence value of 1 × 10{sup 10} cm{sup −2} utilizing the scanning focused ion microbeam as implantation tool and the Ion Beam Induced Current (IBIC) technique for ion counting. Differential DLTS analysis of the vacancy-rich region in self-implanted silicon reveals a formation of the broad vacancy-related defect state(s) at E{sub c} −0.4 eV. Direct measurements of the electron capture kinetics associated with this trap at E{sub c} −0.4 eV, prior to any annealing do not show an exponential behaviour typical for the simple point-like defects. The logarithmic capture kinetics is in accordance with the theory of majority carrier capture at extended or cluster-related defects. We have detected formation of two deep electron traps at E{sub c} −0.56 eV and E{sub c} −0.61 eV in the interstitial-rich region of the self-implanted silicon, before any annealing. No DLTS signal originating from vacancy-oxygen trap at E{sub c} −0.17 eV, present in the sample irradiated with 0.8 MeV neutrons, has been recorded in the self-implanted sample.

  6. Influence of ITO-Silver Wire Electrode Structure on the Performance of Single-Crystal Silicon Solar Cells

    Directory of Open Access Journals (Sweden)

    Wern-Dare Jheng

    2012-01-01

    Full Text Available This study aimed to explore the effect of various electrode forms on single-crystal silicon solar cells by changing their front and back electrode structures. The high light penetration depth of the Indium Tin Oxide (ITO and the high conductivity of the silver wire that were coated on the single crystal silicon solar cells increased photoelectron export, thus increasing the efficiency of the solar cell. The experiment utilized a sol-gel solution containing phosphorus that was spin coated on single-crystal silicon wafers; this phosphorus also served as a phosphorus diffusion source. A p-n junction was formed after annealing at high temperature, and the substrate was coated with silver wires and ITO films of various structures to produce the electrodes. This study proposed that applying a heat treatment to the aluminum of back electrodes would result in a higher efficiency for single-crystal silicon solar cells, whereas single-crystal silicon solar cells containing front electrodes with ITO film coated with silver wires would result in efficiencies that are higher than those achieved using pure ITO thin-film electrodes.

  7. An experimental and theoretical study of pendellösung fringes in synchrotron section topographs of silicon wafers.

    Science.gov (United States)

    Partanen, J; Tuomi, T

    1990-01-01

    X-ray section topographs of nearly perfect Czochralski-grown wafers were made with synchrotron radiation having a continuous spectrum. An intensity curve measured from the x-ray film is compared to the calculated curve obtained using the dynamical theory of x-ray diffraction. A computer simulation of the topograph is also presented. A good agreement between theory and experiment is found except in the middle part of the topograph.

  8. Antifuse with a single silicon-rich silicon nitride insulating layer

    Science.gov (United States)

    Habermehl, Scott D.; Apodaca, Roger T.

    2013-01-22

    An antifuse is disclosed which has an electrically-insulating region sandwiched between two electrodes. The electrically-insulating region has a single layer of a non-hydrogenated silicon-rich (i.e. non-stoichiometric) silicon nitride SiN.sub.X with a nitrogen content X which is generally in the range of 0silicon. Arrays of antifuses can also be formed.

  9. Far infrared spectroscopy of Ge film deposited on a piece of Si wafer and single crystal Ge

    International Nuclear Information System (INIS)

    Roslan, M.; Ibrahim, K.; Wan Abdullah, A.K.

    1991-01-01

    The far infrared spectrum of thin polycrystalline film of Ge of approximately 10 μm deposited on a piece of Si wafer (99.99% purity) has been obtained using the far infrared Fourier transform spectroscopy system developed recently in our laboratory. The spectrum of Ge film from 180 to 480 cm -1 obtained after rationing against Si wafer spectrum at a resolution of about 1 cm -1 has been obtained. It is interesting to note that this thin film of Ge is extremely transparent to radiation in this region and phonon absorption processes as reported previously could not be observed due to thinness of the film. The spectrum of a single crystal of Ge (99.9% purity) and Ge-doped Li have revealed several absorption bands which we have assigned as due to 2-phonon and 3-phonon processes in Ge. The bands at 195, 273 and 287 cm -1 could not be assigned as phonon processes and at present we do not know the causes of these absorption bands

  10. Elastocapillary folding of three dimensional micro-structures using water pumped through the wafer via a silicon nitride tube

    NARCIS (Netherlands)

    Legrain, A.B.H.; Berenschot, Johan W.; Sanders, Remco G.P.; Ma, Kechun; Tas, Niels Roelof; Abelmann, Leon

    2011-01-01

    In this paper we present the first investigation of a batch method for folding of threedimensional micrometer-sized silicon nitride structures by capillary forces. Silicon nitride tubes have been designed and fabricated using DRIE at the center of the planar origami patterns of the structures. Water

  11. Performance of silicon solar cells fabricated from multiple Czochralski ingots grown by using a single crucible

    Science.gov (United States)

    Kachare, A. H.; Uno, F. M.; Miyahira, T.; Lane, R. L.

    1980-01-01

    Results on the performance of solar cells fabricated on wafers from multiple silicon ingots of large diameter, grown by using a single crucible and a sequential melt replenishment Czochralski (CZO) technique are presented. Samples were analyzed for resistivity, dislocation density and impurity content. Solar cells were fabricated from the seed, center and tang end of each ingot to evaluate the growth reproducibility and material quality. The cell efficiency within a given wafer varies by no more than plus or minus 5% of the average value. A small but consistent decrease in the cell efficiency is observed from the first to the fourth ingot grown from a single crucible. This decrease may be related to an increase in impurity content or dislocation density or a combination of both. The efficiency of the cells fabricated from the tang end of the fourth ingot is about 10% lower than that of the control cell. An impurity effects model is employed to correlate this decrease in efficiency with the impurity build-up in the residual melt.

  12. Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Directory of Open Access Journals (Sweden)

    Heinz Horstmann

    Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  13. A simple chemical method for the separation of phosphorus interfering the trace element determinations by neutron activation analysis in high doped silicon wafers

    International Nuclear Information System (INIS)

    Wagler, H.; Flachowsky, J.

    1986-01-01

    Neutron activation analysis is one of the most available method for the determination of trace elements, but in the case of P-doped silicon wafers the 32 P-activity interferes the gamma spectrometry. It is not possible to determine the trace elements without chemical manipulations. On the other hand, time consuming chemical separations should be avoided. Therefore, a simple and rapid P-separation method has to be developed, in which the following twelve trace elements should be taken into consideration: Ag, As, Au, Co, Cr, Cu, Fe, Mo, Na, Sb, W, and Zn. After acid oxidative dissolution of the activated sample, P is present as phosphate ion. The phosphate ion is removed by precipitation as BiPO 4 . (author)

  14. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    Science.gov (United States)

    Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

    2009-10-01

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W-1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than -20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than -10 dB from 8 GHz to 14 GHz.

  15. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    International Nuclear Information System (INIS)

    Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

    2009-01-01

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W −1 . The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S 21 ) is below 0.4 dB from 0 to 40 GHz and the return loss (S 11 ) is less than −20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S 21 shifting caused by the packaging structure is below 0.5 dB, and S 11 is less than −10 dB from 8 GHz to 14 GHz

  16. Magnetic resonance spectroscopy of single centers in silicon quantum wells

    Energy Technology Data Exchange (ETDEWEB)

    Bagraev, Nikolay T., E-mail: impurity.dipole@mail.ioffe.r [Ioffe Physical-Technical Institute, 194021 St. Petersburg (Russian Federation); Klyachkin, Leonid E.; Kudryavtsev, Andrey A.; Malyarenko, Anna M. [Ioffe Physical-Technical Institute, 194021 St. Petersburg (Russian Federation)

    2009-12-15

    We present the new optically detected magnetic resonance (ODMR) technique which reveals single point defects in silicon quantum wells embedded in microcavities within frameworks of the excitonic normal-mode coupling (NMC) without the external cavity and the hf source.

  17. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    Science.gov (United States)

    Zhuang, Xuefeng

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with a front-end integrated circuit (IC) to achieve compact packaging and to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for CMUT arrays, and many other types of micro-electro-mechanical system (MEMS) devices. However, to date, no successful through-wafer via fabrication technique compatible with the wafer-bonding method of making CMUT arrays has been demonstrated. The through-wafer via fabrication steps degrade the surface conditions of the wafer, reduce the radius of curvature, thus making it difficult to bond. This work focuses on new through-wafer interconnect techniques that are compatible with common MEMS fabrication techniques, including both surface-micromachining and direct wafer-to-wafer fusion bonding. In this dissertation, first, a through-wafer via interconnect technique with improved characteristics is presented. Then, two implementations of through-wafer trench isolation are demonstrated. The through-wafer trench methods differ from the through-wafer vias in that the electrical conduction is through the bulk silicon instead of the conductor in the vias. In the first implementation, a carrier wafer is used to provide mechanical support; in the second, mechanical support is provided by a silicon frame structure embedded inside the isolation trenches. Both implementations reduce fabrication complexity compared to the through-wafer

  18. An air-breathing micro direct methanol fuel cell stack employing a single shared anode using silicon microfabrication technologies

    Science.gov (United States)

    Wang, Xiaohong; Zhou, Yan'an; Zhang, Qian; Zhu, Yiming; Liu, Litian

    2009-09-01

    This paper presents a silicon-based air-breathing micro direct methanol fuel cell (μDMFC) stack with a shared anode plate and two air-breathing cathode plates. Three kinds of anode plates featured by different methanol transport methods are designed and simulated. Microfabrication technologies, including double-side lithography and bulk-micromachining, are used to fabricate both anode and cathode silicon plates on the same wafer simultaneously. Three μDMFC stacks with different kinds of anodes are assembled, and characterized with a single cell together. Simulation and experimental results show that the μDMFC stack with fuel transport in a shared model has the best performance, and this stack achieves a power of 2.52 mW which is almost double that of a single cell of 1.28 mW.

  19. Ion beam studies of hydrogen implanted Si wafers

    International Nuclear Information System (INIS)

    Nurmela, A.; Henttinen, K.; Suni, T.; Tolkki, A.; Suni, I.

    2004-01-01

    We have studied silicon-on-insulator (SOI) materials with two different ion beam analysis methods. The SOI samples were implanted with boron and hydrogen ions. After implantation the wafers were annealed, and some of them were bonded to thermally oxidized silicon wafers. The damage in silicon single crystal due to ion implantations has been studied by Rutherford Backscattering in the channeling mode (RBS/C). The content of the ion-implanted hydrogen has been studied by elastic recoil detection analysis (ERDA) method. The strength of the implanted region after thermal annealings were measured with the crack opening method. The boron implantation before hydrogen implantation resulted to shallower implantation depth and lower splitting temperature than in samples implanted with hydrogen only. The boron implantation after hydrogen implantation did not influence the splitting temperature and RBS spectra showed that B implantation drove the H deeper to the sample

  20. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  1. Characterization of the first double-sided 3D radiation sensors fabricated at FBK on 6-inch silicon wafers

    International Nuclear Information System (INIS)

    Sultan, D.M.S.; Mendicino, R.; Betta, G.-F. Dalla; Boscardin, M.; Ronchin, S.; Zorzi, N.

    2015-01-01

    Following 3D pixel sensor production for the ATLAS Insertable B-Layer, Fondazione Bruno Kessler (FBK) fabrication facility has recently been upgraded to process 6-inch wafers. In 2014, a test batch was fabricated to check for possible issues relevant to this upgrade. While maintaining a double-sided fabrication technology, some process modifications have been investigated. We report here on the technology and the design of this batch, and present selected results from the electrical characterization of sensors and test structures. Notably, the breakdown voltage is shown to exceed 200 V before irradiation, much higher than in earlier productions, demonstrating robustness in terms of radiation hardness for forthcoming productions aimed at High Luminosity LHC upgrades

  2. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y.; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K{alpha}0.28 keV and Al K{alpha}1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K{alpha} ({approx}6 nm rms) is significantly larger than {approx}1 nm at Al K{alpha}. This can be explained by different coherent lengths at two energies.

  3. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers.

    Science.gov (United States)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K(alpha)0.28 keV and Al K(alpha)1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K(alpha) (approximately 6 nm rms) is significantly larger than approximately 1 nm at Al K(alpha). This can be explained by different coherent lengths at two energies.

  4. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    Science.gov (United States)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress

  5. Resistivity distribution of silicon single crystals using codoping

    Science.gov (United States)

    Wang, Jong Hoe

    2005-07-01

    Numerous studies including continuous Czochralski method and double crucible technique have been reported on the control of macroscopic axial resistivity distribution in bulk crystal growth. The simple codoping method for improving the productivity of silicon single-crystal growth by controlling axial specific resistivity distribution was proposed by Wang [Jpn. J. Appl. Phys. 43 (2004) 4079]. Wang [J. Crystal Growth 275 (2005) e73] demonstrated using numerical analysis and by experimental results that the axial specific resistivity distribution can be modified in melt growth of silicon crystals and relatively uniform profile is possible by B-P codoping method. In this work, the basic characteristic of 8 in silicon single crystal grown using codoping method is studied and whether proposed method has advantage for the silicon crystal growth is discussed.

  6. Temperature dependent evolution of wrinkled single-crystal silicon ribbons on shape memory polymers.

    Science.gov (United States)

    Wang, Yu; Yu, Kai; Qi, H Jerry; Xiao, Jianliang

    2017-10-25

    Shape memory polymers (SMPs) can remember two or more distinct shapes, and thus can have a lot of potential applications. This paper presents combined experimental and theoretical studies on the wrinkling of single-crystal Si ribbons on SMPs and the temperature dependent evolution. Using the shape memory effect of heat responsive SMPs, this study provides a method to build wavy forms of single-crystal silicon thin films on top of SMP substrates. Silicon ribbons obtained from a Si-on-insulator (SOI) wafer are released and transferred onto the surface of programmed SMPs. Then such bilayer systems are recovered at different temperatures, yielding well-defined, wavy profiles of Si ribbons. The wavy profiles are shown to evolve with time, and the evolution behavior strongly depends on the recovery temperature. At relatively low recovery temperatures, both wrinkle wavelength and amplitude increase with time as evolution progresses. Finite element analysis (FEA) accounting for the thermomechanical behavior of SMPs is conducted to study the wrinkling of Si ribbons on SMPs, which shows good agreement with experiment. Merging of wrinkles is observed in FEA, which could explain the increase of wrinkle wavelength observed in the experiment. This study can have important implications for smart stretchable electronics, wrinkling mechanics, stimuli-responsive surface engineering, and advanced manufacturing.

  7. Single-Event Effects in Silicon Carbide Power Devices

    Science.gov (United States)

    Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

    2015-01-01

    This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

  8. Organized metamaterials comprised of gold nanoneedles in a lattice generated on silicon (100) wafer substrates by interfering femtosecond laser processing

    Science.gov (United States)

    Nakata, Yoshiki; Momoo, Kazuma; Miyanaga, Noriaki; Hiromoto, Takuya; Tsuchida, Kunio

    2013-07-01

    Interfering femtosecond (fs) laser processing has been applied to fabricate organized metamaterials on substrates. We have named the unit structures as nanowhiskers, nanoneedles, nanodrops, and nanocrowns. The processes used for formation of these structures are analogous to the motion of a liquid as captured by a high-speed CCD camera; these structures are fabricated via liquid motion of a metallic thin film on solid substrates. From the perspective of a practical, the adaptability of this technique to silicon technology, including lithography, is very important. In this paper, Au nanoneedles on nanobumps in a lattice structure were fabricated on silicon (100) substrates. In addition, the use of a zeroth-order beam, which has been excluded in past experiments, was shown to result in a low photon cost.

  9. Silicon Dioxide Thin Film Mediated Single Cell Nucleic Acid Isolation

    Science.gov (United States)

    Bogdanov, Evgeny; Dominova, Irina; Shusharina, Natalia; Botman, Stepan; Kasymov, Vitaliy; Patrushev, Maksim

    2013-01-01

    A limited amount of DNA extracted from single cells, and the development of single cell diagnostics make it necessary to create a new highly effective method for the single cells nucleic acids isolation. In this paper, we propose the DNA isolation method from biomaterials with limited DNA quantity in sample, and from samples with degradable DNA based on the use of solid-phase adsorbent silicon dioxide nanofilm deposited on the inner surface of PCR tube. PMID:23874571

  10. Special Issue: The Silicon Age

    Science.gov (United States)

    Kittler, Martin; Yang, Deren

    2006-03-01

    The present issue of physica status solidi (a) contains a collection of articles about different aspects of current silicon research and applications, ranging from basic investigations of mono- and polycrystalline silicon materials and nanostructures to technologies for device fabrication in silicon photovoltaics, micro- and optoelectronics. Guest Editors are Martin Kittler and Deren Yang, the organizers of a recent Sino-German symposium held in Cottbus, Germany, 19-24 September 2005.The cover picture shows four examples of The Silicon Age: the structure of a thin film solar cell on low-cost SSP (silicon sheet from powder) substrate (upper left image) [1], a high-resolution transmission electron microscopy image and diffraction pattern of a single-crystalline Si nanowire (upper right) [2], a carrier lifetime map from an n-type multicrystalline silicon wafer after gettering by a grain boundary (lower left) [3], and a scanning acoustic microscopy image of a bonded 150 mm diameter wafer pair (upper right) [4].

  11. Atomic mechanism for the growth of wafer-scale single-crystal graphene: theoretical perspective and scanning tunneling microscopy investigations

    Science.gov (United States)

    Niu, Tianchao; Zhang, Jialin; Chen, Wei

    2017-12-01

    Chemical vapor deposition (CVD) is the most promising approach for producing low-cost, high-quality, and large area graphene. Revealing the graphene growth mechanism at the atomic-scale is of great importance for realizing single crystal graphene (SCG) over wafer scale. Density functional theoretical (DFT) calculations are playing an increasingly important role in revealing the structure of the most stable carbon species, understanding the evolution processes, and disclosing the active sites. Scanning tunneling microscopy (STM) is a powerful surface characterization tool to illustrate the real space distribution and atomic structures of growth intermediates during the CVD process. Combining them together can provide valuable information to improve the atomically controlled growth of SCG. Starting from a basic concept of the substrate effect on realizing SCG, this review covers the progress made in theoretical investigations on various carbon species during graphene growth on different transition metal substrates, in the STM study of the structural intermediates on transition metal surfaces, and in synthesizing graphene nanoribbons with atomic-precise width and edge structure, ending with a perspective on the future development of 2D materials beyond graphene.

  12. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  13. Influence of the organic solvents on the properties of the phosphoric acid dopant emulsion deposited on multicrystalline silicon wafers

    International Nuclear Information System (INIS)

    Bouhafs, D; Moussi, A; Boumaour, M; Abaidia, S E K; Mahiou, L; Messaoud, A

    2007-01-01

    This study is devoted to the formation of an n + p emitter for multicrystalline silicon (mc-Si) solar cells for photovoltaic (PV) application. The atomization technique has been used to make the emitter from H 3 PO 4 phosphoric acid as a doping source. The doping emulsion has been optimized using several organic solvents. H 3 PO 4 was mixed with one of these solutions: ethanol, 2-butanol, isopropanol alcohol and deionized water. The volume concentration of H 3 PO 4 does not exceed 20% of the total volume emulsion. The deposit characteristics of the emulsion change with the organic solvent. H 3 PO 4 : 2-butanol gives the best deposited layer with acceptable adherence and uniformity on silicon surface. Fourier transform infrared characterizations show the presence of organic and mineral phosphorous bonds in the formed layer. The obtained emitters are characterized by a junction depth in the range 0.2-0.75 μm and a sheet resistance of about 10-90 Ω/□. Such a low cost dopant source combined with a continuous spray process can effectively reduce the cost per Wp of the PV generator

  14. Porous Silicon Nanowires

    Science.gov (United States)

    Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

    2011-01-01

    In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

  15. Silver nanocrystals of various morphologies deposited on silicon wafer and their applications in ultrasensitive surface-enhanced Raman scattering

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Limiao, E-mail: chenlimiao@csu.edu.cn; Jing, Qifeng; Chen, Jun; Wang, Bodong; Huang, Jianhan; Liu, Younian

    2013-11-15

    Silver nanostructures with dendritic, flower-like and irregular morphologies were controllably deposited on a silicon substrate in an aqueous hydrogen fluoride solution at room temperature. The morphology of the Ag nanostructures changed from dendritic to urchin-like, flowerlike and pinecone-like with increasing the concentration of polyvinyl pyrrolidone (MW = 55,000) from 2 to 10 mM. The Ag nanostructures were characterized by transmission electron microscopy, high-resolution transmission electron microscopy, scanning electron microscopy, energy-dispersive X-ray, and X-ray diffraction. Through a series of time-dependent morphological evolution studies, the growth processes of Ag nanostructures have been systematically investigated and the corresponding growth mechanisms have been discussed. In addition, the morphology-dependent surface-enhanced Raman scattering of as-synthesized Ag nanostructures were investigated. The results indicated that flower-like Ag nanostructure had the highest activity than the other Ag nanostructures for Rhodamine 6G probe molecules. Highlights: • A simple method was developed to prepare dendritic and flower-like Ag nanostructures. • The flower-like Ag nanoparticles exhibit highest SERS activity. • The SERS substrate based on flower-like Ag particles can be used to detect melamine.

  16. A single dopant atom in silicon sees the light

    Science.gov (United States)

    Rogge, Sven

    2014-03-01

    Optical access to a single qubit is very attractive since it allows for readout with unprecedented high spectral resolution and long distance coupling. Substantial progress has been demonstrated for nitrogen-vacancy centers in diamond (Bernien, Nature, 2013). Optical access to qubits in silicon been an important goal but has to date only been achieved in the ensemble limit (Steger, Science, 2012). Here, we present the photoionization of an individual erbium dopant in silicon (Yin, Nature, 2013). A single-electron transistor is used as a single-shot charge detector to observe the resonant ionization of a single atom as a function of photon energy. This allows for optical addressing and electrical detection of individual erbium dopants with exceptionally narrow line width. The hyperfine coupling is clearly resolved which paves the way to single shot readout of the nuclear spin. This hybrid approach is a first step towards an optical interface to dopants in silicon. in collaboration with Chunming Yin, Milos Rancic, Gabriele G. de Boo, Nikolas Stavrias, Jeffrey C. McCallum, Matthew J. Sellars.

  17. Wafer-Scale Integration of Inverted Nanopyramid Arrays for Advanced Light Trapping in Crystalline Silicon Thin Film Solar Cells.

    Science.gov (United States)

    Zhou, Suqiong; Yang, Zhenhai; Gao, Pingqi; Li, Xiaofeng; Yang, Xi; Wang, Dan; He, Jian; Ying, Zhiqin; Ye, Jichun

    2016-12-01

    Crystalline silicon thin film (c-Si TF) solar cells with an active layer thickness of a few micrometers may provide a viable pathway for further sustainable development of photovoltaic technology, because of its potentials in cost reduction and high efficiency. However, the performance of such cells is largely constrained by the deteriorated light absorption of the ultrathin photoactive material. Here, we report an efficient light-trapping strategy in c-Si TFs (~20 μm in thickness) that utilizes two-dimensional (2D) arrays of inverted nanopyramid (INP) as surface texturing. Three types of INP arrays with typical periodicities of 300, 670, and 1400 nm, either on front, rear, or both surfaces of the c-Si TFs, are fabricated by scalable colloidal lithography and anisotropic wet etch technique. With the extra aid of antireflection coating, the sufficient optical absorption of 20-μm-thick c-Si with a double-sided 1400-nm INP arrays yields a photocurrent density of 39.86 mA/cm(2), which is about 76 % higher than the flat counterpart (22.63 mA/cm(2)) and is only 3 % lower than the value of Lambertian limit (41.10 mA/cm(2)). The novel surface texturing scheme with 2D INP arrays has the advantages of excellent antireflection and light-trapping capabilities, an inherent low parasitic surface area, a negligible surface damage, and a good compatibility for subsequent process steps, making it a good alternative for high-performance c-Si TF solar cells.

  18. Controlling growth density and patterning of single crystalline silicon nanowires

    International Nuclear Information System (INIS)

    Chang, Tung-Hao; Chang, Yu-Cheng; Liu, Fu-Ken; Chu, Tieh-Chi

    2010-01-01

    This study examines the usage of well-patterned Au nanoparticles (NPs) as a catalyst for one-dimensional growth of single crystalline Si nanowires (NWs) through the vapor-liquid-solid (VLS) mechanism. The study reports the fabrication of monolayer Au NPs through the self-assembly of Au NPs on a 3-aminopropyltrimethoxysilane (APTMS)-modified silicon substrate. Results indicate that the spin coating time of Au NPs plays a crucial role in determining the density of Au NPs on the surface of the silicon substrate and the later catalysis growth of Si NWs. The experiments in this study employed optical lithography to pattern Au NPs, treating them as a catalyst for Si NW growth. The patterned Si NW structures easily produced and controlled Si NW density. This approach may be useful for further studies on single crystalline Si NW-based nanodevices and their properties.

  19. 90 nm device validation of the use of a single-wafer, high-current implanter for high tilt halo implants

    International Nuclear Information System (INIS)

    Felch, S.B.; Foad, M.A.; Olsen, C.; Nouri, F.; Matsunaga, Y.; Natsuaki, N.

    2005-01-01

    As CMOS device dimensions shrink, the depths of the halo regions are shrinking and the implant doses used to form these regions are increasing to minimize short-channel effects. Shallow implant depths require lower implant energies, so the beam currents and wafer throughputs on the traditionally used medium-current implanters are starting to drop and become a concern for device manufacturers. In addition, halo implants are typically performed with a high tilt angle of 20-30 deg. and require tight angle control. All of these requirements are leading to increased interest in use of single-wafer, high-current implanters for halo implants. This paper reports the results of a study where 90 nm CMOS transistors had halo implants performed on the Applied Materials' Quantum[reg] X implanter. A comparison with device wafers whose halos were implanted on a medium-current implanter was also conducted. In addition, the sensitivity of the device parameters to the implant dose and angle was evaluated

  20. Adhesive wafer bonding

    Science.gov (United States)

    Niklaus, F.; Stemme, G.; Lu, J.-Q.; Gutmann, R. J.

    2006-02-01

    Wafer bonding with intermediate polymer adhesives is an important fabrication technique for advanced microelectronic and microelectromechanical systems, such as three-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive bears the forces involved to hold the surfaces together. The main advantages of adhesive wafer bonding include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers. Compared to alternative wafer bonding techniques, adhesive wafer bonding is simple, robust, and low cost. This article reviews the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications.

  1. Organization of silicon nanocrystals by localized electrochemical etching

    International Nuclear Information System (INIS)

    Ayari-Kanoun, Asma; Drouin, Dominique; Beauvais, Jacques; Lysenko, Vladimir; Nychyporuk, Tetyana; Souifi, Abdelkader

    2009-01-01

    An approach to form a monolayer of organized silicon nanocrystals on a monocrystalline Si wafer is reported. Ordered arrays of nanoholes in a silicon nitride layer were obtained by combining electron beam lithography and plasma etching. Then, a short electrochemical etching current pulse led to formation of a single Si nanocrystal per each nanohole. As a result, high quality silicon nanocrystal arrays were formed with well controlled and reproducible morphologies. In future, this approach can be used to fabricate single electron devices.

  2. Isolating and moving single atoms using silicon nanocrystals

    Science.gov (United States)

    Carroll, Malcolm S.

    2010-09-07

    A method is disclosed for isolating single atoms of an atomic species of interest by locating the atoms within silicon nanocrystals. This can be done by implanting, on the average, a single atom of the atomic species of interest into each nanocrystal, and then measuring an electrical charge distribution on the nanocrystals with scanning capacitance microscopy (SCM) or electrostatic force microscopy (EFM) to identify and select those nanocrystals having exactly one atom of the atomic species of interest therein. The nanocrystals with the single atom of the atomic species of interest therein can be sorted and moved using an atomic force microscope (AFM) tip. The method is useful for forming nanoscale electronic and optical devices including quantum computers and single-photon light sources.

  3. Silicon trench photodiodes on a wafer for efficient X-ray-to-current signal conversion using side-X-ray-irradiation mode

    Science.gov (United States)

    Ariyoshi, Tetsuya; Takane, Yuta; Iwasa, Jumpei; Sakamoto, Kenji; Baba, Akiyoshi; Arima, Yutaka

    2018-04-01

    In this paper, we report a direct-conversion-type X-ray sensor composed of trench-structured silicon photodiodes, which achieves a high X-ray-to-current conversion efficiency under side X-ray irradiation. The silicon X-ray sensor with a length of 22.6 mm and a trench depth of 300 µm was fabricated using a single-poly single-metal 0.35 µm process. X-rays with a tube voltage of 80 kV were irradiated along the trench photodiode from the side of the test chip. The theoretical limit of X-ray-to-current conversion efficiency of 83.8% was achieved at a low reverse bias voltage of 25 V. The X-ray-to-electrical signal conversion efficiency of conventional indirect-conversion-type X-ray sensors is about 10%. Therefore, the developed sensor has a conversion efficiency that is about eight times higher than that of conventional sensors. It is expected that the developed X-ray sensor will be able to markedly lower the radiation dose required for X-ray diagnoses.

  4. Single crystal ternary oxide ferroelectric integration with Silicon

    Science.gov (United States)

    Bakaul, Saidur; Serrao, Claudy; Youun, Long; Khan, Asif; Salahuddin, Sayeef

    2015-03-01

    Integrating single crystal, ternary oxide ferroelectric thin film with Silicon or other arbitrary substrates has been a holy grail for the researchers since the inception of microelectronics industry. The key motivation is that adding ferroelectric materials to existing electronic devices could bring into new functionality, physics and performance improvement such as non-volatility of information, negative capacitance effect and lowering sub-threshold swing of field effect transistor (FET) below 60 mV/decade in FET [Salahuddin, S, Datta, S. Nano Lett. 8, 405(2008)]. However, fabrication of single crystal ferroelectric thin film demands stringent conditions such as lattice matched single crystal substrate and high processing temperature which are incompatible with Silicon. Here we report on successful integration of PbZr0.2Ti0.8O3 in single crystal form with by using a layer transfer method. The lattice structure, surface morphology, piezoelectric coefficient d33, dielectric constant, ferroelectric domain switching and spontaneous and remnant polarization of the transferred PZT are as good as these characteristics of the best PZT films grown by pulsed laser deposition on lattice matched oxide substrates. We also demonstrate Si based, FE gate controlled FET devices.

  5. Efficient Generation of an Array of Single Silicon-Vacancy Defects in Silicon Carbide

    Science.gov (United States)

    Wang, Junfeng; Zhou, Yu; Zhang, Xiaoming; Liu, Fucai; Li, Yan; Li, Ke; Liu, Zheng; Wang, Guanzhong; Gao, Weibo

    2017-06-01

    Color centers in silicon carbide have increasingly attracted attention in recent years owing to their excellent properties such as single-photon emission, good photostability, and long spin-coherence time even at room temperature. As compared to diamond, which is widely used for hosting nitrogen-vacancy centers, silicon carbide has an advantage in terms of large-scale, high-quality, and low-cost growth, as well as an advanced fabrication technique in optoelectronics, leading to prospects for large-scale quantum engineering. In this paper, we report an experimental demonstration of the generation of a single-photon-emitter array through ion implantation. VSi defects are generated in predetermined locations with high generation efficiency (approximately 19 % ±4 % ). The single emitter probability reaches approximately 34 % ±4 % when the ion-implantation dose is properly set. This method serves as a critical step in integrating single VSi defect emitters with photonic structures, which, in turn, can improve the emission and collection efficiency of VSi defects when they are used in a spin photonic quantum network. On the other hand, the defects are shallow, and they are generated about 40 nm below the surface which can serve as a critical resource in quantum-sensing applications.

  6. The tensile effect on crack formation in single crystal silicon irradiated by intense pulsed ion beam

    Science.gov (United States)

    Liang, Guoying; Shen, Jie; Zhang, Jie; Zhong, Haowen; Cui, Xiaojun; Yan, Sha; Zhang, Xiaofu; Yu, Xiao; Le, Xiaoyun

    2017-10-01

    Improving antifatigue performance of silicon substrate is very important for the development of semiconductor industry. The cracking behavior of silicon under intense pulsed ion beam irradiation was studied by numerical simulation in order to understand the mechanism of induced surface peeling observed by experimental means. Using molecular dynamics simulation based on Stillinger Weber potential, tensile effect on crack growth and propagation in single crystal silicon was investigated. Simulation results reveal that stress-strain curves of single crystal silicon at a constant strain rate can be divided into three stages, which are not similar to metal stress-strain curves; different tensile load velocities induce difference of single silicon crack formation speed; the layered stress results in crack formation in single crystal silicon. It is concluded that the crack growth and propagation is more sensitive to strain rate, tensile load velocity, stress distribution in single crystal silicon.

  7. Poly-silicon quantum-dot single-electron transistors

    International Nuclear Information System (INIS)

    Kang, Kwon-Chil; Lee, Joung-Eob; Lee, Jung-Han; Lee, Jong-Ho; Shin, Hyung-Cheol; Park, Byung-Gook

    2012-01-01

    For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also, to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.

  8. ODMR of single point defects in silicon nanostructures

    Energy Technology Data Exchange (ETDEWEB)

    Bagraev, Nikolay; Danilovsky, Eduard; Gets, Dmitry; Klyachkin, Leonid; Kudryavtsev, Andrey; Kuzmin, Roman; Malyarenko, Anna [Ioffe Physical-Technical Institute, Polytekhnicheskaya st. 26, 194021 St. Petersburg (Russian Federation)

    2012-05-15

    We present the findings of the optically detected magnetic resonance technique (ODMR), which reveal single point defects in the ultra-narrow silicon quantum wells (Si-QW) confined by the superconductor {delta}-barriers. This technique allows the ODMR identification without application of an external cavity, as well as a high frequency source and recorder, and with measuring the transmission spectra within the frameworks of the excitonic normal-mode coupling caused by the microcavities embedded in the Si-QW plane. (copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  9. Silicon bulk growth for solar cells: Science and technology

    Science.gov (United States)

    Kakimoto, Koichi; Gao, Bing; Nakano, Satoshi; Harada, Hirofumi; Miyamura, Yoshiji

    2017-02-01

    The photovoltaic industry is in a phase of rapid expansion, growing by more than 30% per annum over the last few decades. Almost all commercial solar cells presently use single-crystalline or multicrystalline silicon wafers similar to those used in microelectronics; meanwhile, thin-film compounds and alloy solar cells are currently under development. The laboratory performance of these cells, at 26% solar energy conversion efficiency, is now approaching thermodynamic limits, with the challenge being to incorporate these improvements into low-cost commercial products. Improvements in the optical design of cells, particularly in their ability to trap weakly absorbed light, have also led to increasing interest in thin-film cells based on polycrystalline silicon; these cells have advantages over other thin-film photovoltaic candidates. This paper provides an overview of silicon-based solar cell research, especially the development of silicon wafers for solar cells, from the viewpoint of growing both single-crystalline and multicrystalline wafers.

  10. Comparison of aggregation behaviors between ionic liquid-type imidazolium gemini surfactant [C12-4-C12im]Br2 and its monomer [C12mim]Br on silicon wafer.

    Science.gov (United States)

    Ao, Mingqi; Xu, Guiying; Pang, Jinyu; Zhao, Taotao

    2009-09-01

    The aggregation of ionic liquid-type imidazolium gemini surfactant [C(12)-4-C(12)im]Br(2) on silicon wafer, which is compared with its monomer [C(12)mim]Br, have been studied. AFM morphology images and contact angle measurements suggest that the aggregations of [C(12)-4-C(12)im]Br(2) and [C(12)mim]Br on silicon wafer follow different mechanisms. Below the critical surface aggregation concentrations (CSAC), both surfactant molecules are adsorbed with their hydrophobic tails facing the air. But above the CSAC, [C(12)-4-C(12)im]Br(2) molecules finally form a bilayer structure with hydrophilic head groups facing the air, whereas [C(12)mim]Br molecules form a multilayer structure, and with increasing its concentration, the layer numbers increase with the hydrophobic chains and hydrophilic head groups facing the air by turns. Besides, the watery wettability of [C(12)-4-C(12)im]Br(2)-treated silica surface is lower than that of [C(12)mim]Br at the concentration of 5.0 cmc, and the infrared spectroscopy suggests that the poorer watery wettability of [C(12)-4-C(12)im]Br(2) may be relative to the less-ordered packing of methylene chains inside the aggregate. These different aggregation behaviors for the two surfactants ascribe to the different molecular structures and electrostatic interactions. This work would have certain theoretical guidance meaning on the modification of solid surface.

  11. Anisotropy of Single-Crystal Silicon in Nanometric Cutting.

    Science.gov (United States)

    Wang, Zhiguo; Chen, Jiaxuan; Wang, Guilian; Bai, Qingshun; Liang, Yingchun

    2017-12-01

    The anisotropy exhibited by single-crystal silicon in nanometric cutting is very significant. In order to profoundly understand the effect of crystal anisotropy on cutting behaviors, a large-scale molecular dynamics model was conducted to simulate the nanometric cutting of single-crystal silicon in the (100)[0-10], (100)[0-1-1], (110)[-110], (110)[00-1], (111)[-101], and (111)[-12-1] crystal directions in this study. The simulation results show the variations of different degrees in chip, subsurface damage, cutting force, and friction coefficient with changes in crystal plane and crystal direction. Shear deformation is the formation mechanism of subsurface damage, and the direction and complexity it forms are the primary causes that result in the anisotropy of subsurface damage. Structurally, chips could be classified into completely amorphous ones and incompletely amorphous ones containing a few crystallites. The formation mechanism of the former is high-pressure phase transformation, while the latter is obtained under the combined action of high-pressure phase transformation and cleavage. Based on an analysis of the material removal mode, it can be found that compared with the other crystal direction on the same crystal plane, the (100)[0-10], (110)[-110], and (111)[-101] directions are more suitable for ductile cutting.

  12. Mutiple Czochralski growth of silicon crystals from a single crucible

    Science.gov (United States)

    Lane, R. L.; Kachare, A. H.

    1980-01-01

    An apparatus for the Czochralski growth of silicon crystals is presented which is capable of producing multiple ingots from a single crucible. The growth chamber features a refillable crucible with a water-cooled, vacuum-tight isolation valve located between the pull chamber and the growth furnace tank which allows the melt crucible to always be at vacuum or low argon pressure when retrieving crystal or introducing recharge polysilicon feed stock. The grower can thus be recharged to obtain 100 kg of silicon crystal ingots from one crucible, and may accommodate crucibles up to 35 cm in diameter. Evaluation of the impurity contents and I-V characteristics of solar cells fabricated from seven ingots grown from two crucibles reveals a small but consistent decrease in cell efficiency from 10.4% to 9.6% from the first to the fourth ingot made in a single run, which is explained by impurity build-up in the residual melt. The crystal grower thus may offer economic benefits through the extension of crucible lifetime and the reduction of furnace downtime.

  13. Influence of high temperature processing of sol-gel derived barium titanate thin films deposited on platinum and strontium ruthenate coated silicon wafers

    NARCIS (Netherlands)

    Stawski, Tomasz; Vijselaar, Wouter Jan, Cornelis; Göbel, Ole; Veldhuis, Sjoerd; Smith, B.F.; Blank, David H.A.; ten Elshof, Johan E.

    2012-01-01

    Thin films of barium titanate (BTO) of 200 nm thickness, derived from an alkoxide¿carboxylate sol¿gel process, were deposited on Pt/Ti and SrRuO3/ZrO2¿8%Y2O3 coated Si wafers. Films with a dense columnar microstructure were obtained by repeated deposition of thin amorphous layers from

  14. Single-phase {beta}-FeSi{sub 2} thin films prepared on Si wafer by femtosecond laser ablation and its photoluminescence at room temperature

    Energy Technology Data Exchange (ETDEWEB)

    Lu Peixiang [State Key Laboratory of Laser Technology and Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China)]. E-mail: lupeixiang@mail.hust.edu.cn; Zhou Youhua [State Key Laboratory of Laser Technology and Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China) and Physics and Information School, Jianghan University, Wuhan 430056 (China)]. E-mail: yhzhou@jhun.edu.cn; Zheng Qiguang [State Key Laboratory of Laser Technology and Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China); Yang Guang [State Key Laboratory of Laser Technology and Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China)

    2006-02-06

    Single-phase {beta}-FeSi{sub 2} thin films were prepared on Si(100) and Si(111) wafers by using femtosecond laser deposition with a FeSi{sub 2} alloy target for the first time. X-ray diffraction (XRD), field scanning electron microscopy (FSEM), scanning probe microscopy (SPM), electron backscattered diffraction pattern (EBSD), and Fourier-transform Raman infrared spectroscopy (FTRIS) were used to characterize the structure, composition, and properties of the {beta}-FeSi{sub 2}/Si films. The orientation of {beta}-FeSi{sub 2} grains was found to depend on the orientation of the Si substrates, and photoluminescence at wavelength of 1.53 {mu}m was observed from the single-phase {beta}-FeSi{sub 2}/Si thin film at room temperature (20 {sup o}C)

  15. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  16. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  17. Single-layer graphene on silicon nitride micromembrane resonators

    Energy Technology Data Exchange (ETDEWEB)

    Schmid, Silvan; Guillermo Villanueva, Luis; Amato, Bartolo; Boisen, Anja [Department of Micro- and Nanotechnology, Technical University of Denmark, DTU Nanotech, Building 345 East, 2800 Kongens Lyngby (Denmark); Bagci, Tolga; Zeuthen, Emil; Sørensen, Anders S.; Usami, Koji; Polzik, Eugene S. [QUANTOP, Niels Bohr Institute, University of Copenhagen, 2100 Copenhagen (Denmark); Taylor, Jacob M. [Joint Quantum Institute/NIST, College Park, Maryland 20899 (United States); Herring, Patrick K.; Cassidy, Maja C. [School of Engineering and Applied Science, Harvard University, Cambridge, Massachusetts 02138 (United States); Marcus, Charles M. [Center for Quantum Devices, Niels Bohr Institute, University of Copenhagen, 2100 Copenhagen (Denmark); Cheol Shin, Yong; Kong, Jing [Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States)

    2014-02-07

    Due to their low mass, high quality factor, and good optical properties, silicon nitride (SiN) micromembrane resonators are widely used in force and mass sensing applications, particularly in optomechanics. The metallization of such membranes would enable an electronic integration with the prospect for exciting new devices, such as optoelectromechanical transducers. Here, we add a single-layer graphene on SiN micromembranes and compare electromechanical coupling and mechanical properties to bare dielectric membranes and to membranes metallized with an aluminium layer. The electrostatic coupling of graphene covered membranes is found to be equal to a perfectly conductive membrane, without significantly adding mass, decreasing the superior mechanical quality factor or affecting the optical properties of pure SiN micromembranes. The concept of graphene-SiN resonators allows a broad range of new experiments both in applied physics and fundamental basic research, e.g., for the mechanical, electrical, or optical characterization of graphene.

  18. Creating and Controlling Single Spins in Silicon Carbide

    Science.gov (United States)

    Christle, David

    Silicon carbide (SiC) is a well-established commercial semiconductor used in high-power electronics, optoelectronics, and nanomechanical devices, and has recently shown promise for semiconductor-based implementations of quantum information technologies. In particular, a set of divacancy-related point defects have improved coherence properties relative to the prominent nitrogen-vacancy center in diamond, are addressable at near-telecom wavelengths, and reside in a material for which there already exist advanced growth, doping, and microfabrication capabilities. These properties suggest divacancies in SiC have compelling advantages for photonics and micromechanical applications, yet their relatively recent discovery means crucial aspects of their fundamental physics for these applications are not well understood. I will review our progress on manipulating spin defects in SiC, and discuss efforts towards isolating and controlling them at the single defect limit. In particular, our most recent experimental results demonstrate isolation and control of long-lived (T2 = 0 . 9 ms) divacancies in a form of SiC that can be grown epitaxially on silicon. By studying the time-resolved photoluminescence of a single divacancy, we reveal its fundamental orbital structure and characterize in detail the dynamics of its special optical cycle. Finally, we probe individual divacancies using resonant laser techniques and reveal an efficient spin-photon interface with figures of merit comparable to those reported for NV centers in diamond. These results suggest a pathway towards photon-mediated entanglement of SiC defect spins over long distances. This work was supported by NSF, AFOSR, the Argonne CNM, the Knut & Alice Wallenberg Foundation, the Linköping Linnaeus Initiative, the Swedish Government Strategic Research Area, and the Ministry of Education, Science, Sports and Culture of Japan.

  19. RBS/channeling analysis of hydrogen-implanted single crystals of FZ silicon and 6H silicon

    International Nuclear Information System (INIS)

    Irwin, R.B.

    1984-01-01

    Single crystals of FZ silicon and 6H silicon carbide were implanted with hydrogen ions (50 and 80 keV, respectively) to fluences from 2 x 10 16 H + /cm 2 to 2 x 10 18 H+/cm 2 . The implantations were carried out at three temperatures: approx.95K, 300 K, and approx.800 K. Swelling of the samples was measured by surface profilometry. RBS/channeling was used to obtain the damage profiles and to determine the amount of hydrogen retained in the lattice. The damage profiles are centered around X/sub m/ for the implants into silicon and around R/sub p/ for silicon carbide. For silicon carbide implanted at 95 K and 300 K and for silicon implanted at 95 K, the peak damage region is amorphous for fluences above 8 x 10 16 H + /cm 2 , 4 x 10 17 H + /cm 2 , and 2 x 10 17 H + /cm 2 , respectively. Silicon implanted at 300 and 800 K and silicon carbide implanted at 800 K remain crystalline up to fluences of 1 x 10 18 H + /cm 2 . The channeling damage results agree with previously reported TEM and electron diffraction data. The predictions of a simple disorder-accumulation model with a linear annealing term explains qualitatively the observed damage profiles in silicon carbide. Quantitatively, however, the model predicts faster development of the damage profiles than is observed at low fluences in both silicon and silicon carbide. For samples implanted at 300 and 800 K, the model also predicts substantially less peak disorder than is observed. The effect of the surface, the retained hydrogen, the shape of S/sub D/(X), and the need for a nonlinear annealing term may be responsible for the discrepancy

  20. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  1. A simple and controlled single electron transistor based on doping modulation in silicon nanowires

    OpenAIRE

    Hofheinz, M.; Jehl, X.; Sanquer, M.; Molas, G.; Vinet, M.; Deleonibus, S.

    2006-01-01

    A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic...

  2. Buckling of Single-Crystal Silicon Nanolines under Indentation

    Directory of Open Access Journals (Sweden)

    Min K. Kang

    2008-01-01

    Full Text Available Atomic force microscope-(AFM- based indentation tests were performed to examine mechanical properties of parallel single-crystal silicon nanolines (SiNLs of sub-100-nm line width, fabricated by a process combining electron-beam lithography and anisotropic wet etching. The SiNLs have straight and nearly atomically flat sidewalls, and the cross section is almost perfectly rectangular with uniform width and height along the longitudinal direction. The measured load-displacement curves from the indentation tests show an instability with large displacement bursts at a critical load ranging from 480 μN to 700 μN. This phenomenon is attributed to a transition of the buckling mode of the SiNLs under indentation. Using a set of finite element models with postbuckling analyses, we analyze the indentation-induced buckling modes and investigate the effects of tip location, contact friction, and substrate deformation on the critical load of mode transition. The results demonstrate a unique approach for the study of nanomaterials and patterned nanostructures via a combination of experiments and modeling.

  3. Experimental Evaluation of Incorporating Digital and Analog Integrated Circuit Die on a Common Substrate Utilizing Silicon-Hybrid Wafer-Scale Integration Technology

    Science.gov (United States)

    1992-03-01

    an uncoated optical alignment flat surface ... ............. . 5-4 5.2. Profilometer measurement of a polished Teflon coating on the optical...as interlevel dielectrics. The most common examples are: silicon dioxide, silicon nitride, spin- on glass (SOG), benzocyclobutene ( BCB ), and the...Glass 3.0 0.2-0.5 - 0.9 BCB 2.75 2.5 30-60 0.2-0.3 Polyimide 3.4 3 5-60 0.5-1.5 the area of vias tend to absorb moisture which adversely affects metal

  4. Coupling of an electrodialyzer with inductively coupled plasma mass spectrometry for the on-line determination of trace impurities in silicon wafers after surface metal extraction.

    Science.gov (United States)

    Chang, I-long; Hsu, I-hsiang; Yang, Mo-hsiung; Sun, Yun-chang

    2010-02-19

    Understanding the properties that determine the distribution and behavior of trace impurities in Si wafers is critical to defining and controlling the performance, reliability, and yields of integrated microelectronic devices. It remains, however, an intrinsically difficult task to determine trace impurities in Si because of the minute concentrations and extremely high levels of matrix involved. In this study, we used an electrodialyzer for the simultaneous on-line removal of the silicate and acid matrices through the neutralization of the excessive hydrogen ion and selectively separation of acid and silicate ions by the combination of electrode reaction as a source of hydroxide ions with the anion exchange membrane separation. To retain the analyte ions in the sample stream, we found that the presence of moderate amounts of nitric acid and hydrazine were necessary to improve the retention efficiency, not only for Zn(2+), Ni(2+), Cu(2+), and Co(2+) ions but also for CrO(4)(2-) ion. Under the optimized conditions, the interference that resulted from the sample matrix was suppressed significantly to provide satisfactory analytical signals. The precision of this method was ca. 5% when we used an electrodialyzer equipped with an anion exchange membrane to remove the sample matrix prior to performing inductively coupled plasma mass spectrometry (ICP-MS); the good agreement between the data obtained using our proposed method and those obtained using a batchwise wet chemical technique confirmed its accuracy. Our method permits the determination of Zn, Ni, Cu, Co, and Cr in Si wafers at detection limits within the range from 2.2 x 10(15) to 9.0 x 10(15) atoms cm(-3). Copyright 2009 Elsevier B.V. All rights reserved.

  5. H+ ion-implantation energy dependence of electronic transport properties in the MeV range in n-type silicon wafers using frequency-domain photocarrier radiometry

    International Nuclear Information System (INIS)

    Wang Chinhua; Mandelis, Andreas; Tolev, Jordan; Burchard, Bernd; Meijer, Jan

    2007-01-01

    Industrial n-type Si wafers (resistivity of 5-10 Ω cm) were H + ion implanted with energies between 0.75 and 2.00 MeV, and the electronic transport properties of the implanted layer (recombination lifetime, carrier diffusion coefficient, and front-surface and implanted-interface recombination velocities s 1 and s 2 ) were studied using photocarrier radiometry (PCR). A quantitative fitting procedure to the diffusing photoexcited free-carrier density wave was introduced using a relatively simple two-layer PCR model in lieu of the more realistic but substantially more complicated three-layer model. The experimental trends in the transport properties of H + -implanted Si layers extracted from the PCR amplitude and phase data as functions of implantation energy corroborate a physical model of the implanted layer in which (a) overlayer damage due to the light H + ions decreases with increased depth of implantation at higher energies (b) the implanted region damage close to the interface is largely decoupled from the overlayer crystallinity, and (c) the concentration of implanted H + ions decreases at higher implantation energies at the interface, thus decreasing the degree of implantation damage at the interface proper

  6. Silicon Nanowire Field-effect Chemical Sensor

    OpenAIRE

    Chen, S.

    2011-01-01

    This thesis describes the work that has been done on the project “Design and optimization of silicon nanowire for chemical sensing‿, including Si-NW fabrication, electrical/electrochemical modeling, the application as ISFET, and the build-up of Si- NW/LOC system for automatic sample delivery. A novel top-down fabrication technique was presented for single-crystal Si-NW fabrication realized with conventional microfabrication technique. High quality triangular Si-NWs were made with high wafer-s...

  7. Single-molecule microscopy using silicone oil immersion objective lenses

    NARCIS (Netherlands)

    Hink, M.

    2012-01-01

    Microscopy techniques capable of detecting individual molecules and providing quantitative data have the potential to offer great biological insight; however, such approaches require the efficient capture of light. Here, Mark Hink explains how the use of new silicone oil immersion objective lenses

  8. Effect of oxygen and nitrogen interactions on friction of single-crystal silicon carbide

    Science.gov (United States)

    Miyoshi, K.; Buckley, D. H.

    1978-01-01

    Friction studies were conducted with single-crystal silicon carbide contacting silicon carbide and titanium after having been exposed to oxygen and nitrogen in various forms. After they had been sputter cleaned, the surfaces were (1) exposed to gaseous oxygen and nitrogen (adsorption), (2) ion bombarded with oxygen and nitrogen, or (3) reacted with oxygen (SiC only). Auger emission spectroscopy was used to determine the presence of oxygen and nitrogen. The results indicate that the surfaces of silicon carbide with reacted and ion-bombarded oxygen ions give higher coefficients of friction than do argon sputter-cleaned surfaces. The effects of oxygen on friction may be related to the relative chemical, thermodynamic properties of silicon, carbon, and titanium for oxygen. The adsorbed films of oxygen, nitrogen, and mixed gases of oxygen and nitrogen on sputter-cleaned, oxygen-ion bombarded, and oxygen-reacted surfaces generally reduce friction. Adsorption to silicon carbide is relatively weak.

  9. Wafer-bonded 2-D CMUT arrays incorporating through-wafer trench-isolated interconnects with a supporting frame.

    Science.gov (United States)

    Zhuang, Xuefeng; Wygant, Ira O; Lin, Der-Song; Kupnik, Mario; Oralkan, Omer; Khuri-Yakub, Butrus T

    2009-01-01

    This paper reports on wafer-bonded, fully populated 2-D capacitive micromachined ultrasonic transducer (CMUT) arrays. To date, no successful through-wafer via fabrication technique has been demonstrated that is compatible with the wafer-bonding method of making CMUT arrays. As an alternative to through-wafer vias, trench isolation with a supporting frame is incorporated into the 2-D arrays to provide through-wafer electrical connections. The CMUT arrays are built on a silicon-on-insulator (SOI) wafer, and all electrical connections to the array elements are brought to the back side of the wafer through the highly conductive silicon substrate. Neighboring array elements are separated by trenches on both the device layer and the bulk silicon. A mesh frame structure, providing mechanical support, is embedded between silicon pillars, which electrically connect to individual elements. We successfully fabricated a 16 x 16-element 2-D CMUT array using wafer bonding with a yield of 100%. Across the array, the pulse-echo amplitude distribution is uniform (rho = 6.6% of the mean amplitude). In one design, we measured a center frequency of 7.6 MHz, a peak-to-peak output pressure of 2.9 MPa at the transducer surface, and a 3-dB fractional bandwidth of 95%. Volumetric ultrasound imaging was demonstrated by chip-to-chip bonding one of the fabricated 2-D arrays to a custom-designed integrated circuit (IC). This study shows that through-wafer trench-isolation with a supporting frame is a viable solution for providing electrical interconnects to CMUT elements and that 2-D arrays fabricated using waferbonding deliver good performance.

  10. Production of silicon disks for PV systems; Herstellung von Siliciumscheiben fuer die Photovoltaik

    Energy Technology Data Exchange (ETDEWEB)

    Woditsch, P. [Bayer Solar GmbH, Freiberg (Germany)

    1999-07-01

    The contribution describes the production of silicon wafers in all stages: Melting and crystallisation, production of wafers and columns, careful cleaning and quality control of every single silicon wafer. The initial material is pure silicon as used in the production of electronic chips. Bayer Solar GmbH are producers of monocrystalline and multicrystalline silicon wafers. By the end of 1999, their two works at Uerdingen and Freiberg had a total capacity of about 36 MWp, i.e. about 25% of the world demand. [German] Im Beitrag wird der Werdegang vom Silicium bis zum photovoltaischen System kurz dargestellt, wobei, bedingt durch eine teilweise Arbeitsteilung, die Si-Wafer und Zellen als Zwischenstufen auftreten. Die Bayer Solar GmbH hat sich dabei bis heute auf die Herstellung von mono- und multikristallinen Siliciumscheiben konzentriert, wobei Werke in Uerdingen und Freiberg Ende 1999 eine Gesamtkapazitaet von etwa 36 MWp bereit halten, was ca. 25% des weltweiten Bedarfs entspricht. Der Weg vom Silicium zum Wafer umfasst das Schmelzen und Kristallisieren, die Saeulen- und Scheibenherstellung, eine sorgfaeltige Scheibenreinigung und anschliessende Qualitaetskontrolle jeder einzelnen Siliciumscheibe. Ausgangsmaterial ist ein hochreines Silicium, wie es aehnlich auch fuer die Chipherstellung in der Elektronik verwendet wird. (orig.)

  11. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    of wafer through-holes the main challenge is to protect the CMOS wafer during etching. In the case of DRIE etching of the wafer through-holes the main challenges are proper insulation of the wafer through-holes, conformal deposition of via metal and structuring of the deposited metal. This thesis discusses...

  12. Stable wafer-carrier system

    Energy Technology Data Exchange (ETDEWEB)

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  13. Annealing effect of H+ -implanted single crystal silicon on strain and crystal structure

    International Nuclear Information System (INIS)

    Duo Xinzhong; Liu Weili; Zhang Miao; Gao Jianxia; Fu Xiaorong; Lin Chenglu

    2000-01-01

    The work focuses on the rocking curves of H + -implanted single silicon crystal detected by Four-Crystal X-ray diffractometer. The samples were annealed under different temperatures. Lattice defect in H + -implanted silicon crystals was detected by Rutherford Backscattering Spectrometry. It appeared that H-related complex did not crush until annealing temperature reached about 400 degree C. At that temperature H 2 was formed, deflated in silicon lattice and strained the lattice. But defects did not come into being in large quantity. The lattice was undamaged. When annealing temperature reached 500 degree C, strain induced by H 2 deflation crashed the silicon lattice. A large number of defects were formed. At the same time bubbles in the crystal and blister/flaking on the surface could be observed

  14. Anisotropy effect of crater formation on single crystal silicon surface under intense pulsed ion beam irradiation

    Science.gov (United States)

    Shen, Jie; Yu, Xiao; Zhang, Jie; Zhong, Haowen; Cui, Xiaojun; Liang, Guoying; Yu, Xiang; Huang, Wanying; Shahid, Ijaz; Zhang, Xiaofu; Yan, Sha; Le, Xiaoyun

    2018-04-01

    Due to the induced extremely fast thermal and dynamic process, Intense Pulsed Ion Beam (IPIB) is widely applied in material processing, which can bring enhanced material performance and surface craters as well. To investigate the craters' formation mechanism, a specific model was built with Finite Element Methods (FEM) to simulate the thermal field on irradiated single crystal silicon. The direct evidence for the existence of the simulated 6-fold rotational symmetric thermal distribution was provided by electron microscope images obtained on single crystal silicon. The correlation of the experiment and simulation is of great importance to understand the interaction between IPIB and materials.

  15. Preparation and single molecule structure of electroactive polysilane end-grafted on a crystalline silicon surface

    Science.gov (United States)

    Furukawa, Kazuaki; Ebata, Keisuke

    2000-12-01

    Electrically active polysilanes of poly(methylphenylsilane) (PMPS) and poly[bis(p-n-butylphenyl)silane] (PBPS), which are, respectively, known as a good hole transporting material and a near-ultraviolet electroluminescent material, are end-grafted directly on a crystalline silicon surface. The single polysilane molecules are clearly distinguished one from the other on the surface by means of atomic force microscopy observations. End-grafted single molecules of PMPS are observed as dots while end-grafted PBPS appear as worms extending for more than 100 nm on the crystalline silicon surface.

  16. Silicon microphotonic waveguides

    International Nuclear Information System (INIS)

    Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

    2004-01-01

    Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

  17. The charge collection in single side silicon microstrip detectors

    CERN Document Server

    Eremin, V V; Roe, S; Ruggiero, G; Weilhammer, Peter

    2003-01-01

    The transient current technique has been used to investigate signal formation in unirradiated silicon microstrip detectors, which are similar in geometry to those developed for the ATLAS experiment at LHC. Nanosecond pulsed infrared and red lasers were used to induce the signals under study. Two peculiarities in the detector performance were observed: an unexpectedly slow rise to the signal induced in a given strip when signals are injected opposite to the strip, and a long duration of the induced signal in comparison with the calculated drift time of charge carriers through the detector thickness - with a significant fraction of the charge being induced after charge carrier arrival. These major effects and details of the detector response for different positions of charge injection are discussed in the context of Ramo's theorem and compared with predictions arising from the more commonly studied phenomenon of signal formation in planar pad detectors.

  18. Acoustically driven degradation in single crystalline silicon solar cell

    Science.gov (United States)

    Olikh, O. Ya.

    2018-05-01

    The influence of ultrasound on current-voltage characteristics of crystalline silicon solar sell was investigated experimentally. The transverse and longitudinal acoustic waves were used over a temperature range of 290-340 K. It was found that the ultrasound loading leads to the reversible decrease in the photogenerated current, open-circuit voltage, fill factor, carrier lifetime, and shunt resistance as well as the increase in the ideality factor. The experimental results were described by using the models of coupled defect level recombination, Shockley-Read-Hall recombination, and dislocation-induced impedance. The contribution of the boron-oxygen related defects, iron-boron pairs, and oxide precipitates to both the carrier recombination and acousto-defect interaction was discussed. The experimentally observed phenomena are associated with the increase in the distance between coupled defects as well as the extension of the carrier capture coefficient of complex point defects and dislocations.

  19. Genesis of nanostructured, magnetically tunable ceramics from the pyrolysis of cross-linked polyferrocenylsilane networks and formation of shaped macroscopic objects and micron scale patterns by micromolding inside silicon wafers.

    Science.gov (United States)

    Ginzburg, Madlen; MacLachlan, Mark J; Yang, San Ming; Coombs, Neil; Coyle, Thomas W; Raju, Nandyala P; Greedan, John E; Herber, Rolfe H; Ozin, Geoffrey A; Manners, Ian

    2002-03-20

    The ability to form molded or patterned metal-containing ceramics with tunable properties is desirable for many applications. In this paper we describe the evolution of a ceramic from a metal-containing polymer in which the variation of pyrolysis conditions facilitates control of ceramic structure and composition, influencing magnetic and mechanical properties. We have found that pyrolysis under nitrogen of a well-characterized cross-linked polyferrocenylsilane network derived from the ring-opening polymerization (ROP) of a spirocyclic [1]ferrocenophane precursor gives shaped macroscopic magnetic ceramics consisting of alpha-Fe nanoparticles embedded in a SiC/C/Si(3)N(4) matrix in greater than 90% yield up to 1000 degrees C. Variation of the pyrolysis temperature and time permitted control over the nucleation and growth of alpha-Fe particles, which ranged in size from around 15 to 700 A, and the crystallization of the surrounding matrix. The ceramics contained smaller alpha-Fe particles when prepared at temperatures lower than 900 degrees C and displayed superparamagnetic behavior, whereas the materials prepared at 1000 degrees C contained larger alpha-Fe particles and were ferromagnetic. This flexibility may be useful for particular materials applications. In addition, the composition of the ceramic was altered by changing the pyrolysis atmosphere to argon, which yielded ceramics that contain Fe(3)Si(5). The ceramics have been characterized by a combination of physical techniques, including powder X-ray diffraction, TEM, reflectance UV-vis/near-IR spectroscopy, elemental analysis, XPS, SQUID magnetometry, Mössbauer spectroscopy, nanoindentation, and SEM. Micromolding of the spirocyclic [1]ferrocenophane precursor within soft lithographically patterned channels housed inside silicon wafers followed by thermal ROP and pyrolysis enabled the formation of predetermined micron scale designs of the magnetic ceramic.

  20. One step automated unpatterned wafer defect detection and classification

    International Nuclear Information System (INIS)

    Dou Lie; Kesler, Daniel; Bruno, William; Monjak, Charles; Hunt, Jim

    1998-01-01

    Automated detection and classification of crystalline defects on micro-grade silicon wafers is extremely important for integrated circuit (IC) device yield. High training cost, limited capability of classifying defects, increasing possibility of contamination, and unexpected human mistakes necessitate the need to replace the human visual inspection with automated defect inspection. The Laser Scanning Surface Inspection Systems (SSISs) equipped with the Reconvergent Specular Detection (RSD) apparatus are widely used for final wafer inspection. RSD, more commonly known as light channel detection (LC), is capable of detecting and classifying material defects by analyzing information from two independent phenomena, light scattering and reflecting. This paper presents a new technique including a new type of light channel detector to detect and classify wafer surface defects such as slipline dislocation, Epi spikes, Pits, and dimples. The optical system to study this technique consists of a particle scanner to detect and quantify light scattering events from contaminants on the wafer surface and a RSD apparatus (silicon photo detector). Compared with the light channel detector presently used in the wafer fabs, this new light channel technique provides higher sensitivity for small defect detection and more defect scattering signatures for defect classification. Epi protrusions (mounds and spikes), slip dislocations, voids, dimples, and some other common defect features and contamination on silicon wafers are studied using this equipment. The results are compared quantitatively with that of human visual inspection and confirmed by microscope or AFM. This new light channel technology could provide the real future solution to the wafer manufacturing industry for fully automated wafer inspection and defect characterization

  1. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  2. Bright trions in direct-bandgap silicon nanocrystals revealed bylow-temperature single-nanocrystal spectroscopy

    Czech Academy of Sciences Publication Activity Database

    Kůsová, Kateřina; Pelant, Ivan; Valenta, J.

    2015-01-01

    Roč. 4, Oct (2015), e336 ISSN 2047-7538 R&D Projects: GA ČR(CZ) GBP108/12/G108; GA ČR GPP204/12/P235 Institutional support: RVO:68378271 Keywords : silicon nanocrystals * single-nanocrystal spectroscopy * luminescing trions Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 13.600, year: 2015

  3. An all-silicon single-photon source by unconventional photon blockade.

    Science.gov (United States)

    Flayac, Hugo; Gerace, Dario; Savona, Vincenzo

    2015-06-10

    The lack of suitable quantum emitters in silicon and silicon-based materials has prevented the realization of room temperature, compact, stable, and integrated sources of single photons in a scalable on-chip architecture, so far. Current approaches rely on exploiting the enhanced optical nonlinearity of silicon through light confinement or slow-light propagation, and are based on parametric processes that typically require substantial input energy and spatial footprint to reach a reasonable output yield. Here we propose an alternative all-silicon device that employs a different paradigm, namely the interplay between quantum interference and the third-order intrinsic nonlinearity in a system of two coupled optical cavities. This unconventional photon blockade allows to produce antibunched radiation at extremely low input powers. We demonstrate a reliable protocol to operate this mechanism under pulsed optical excitation, as required for device applications, thus implementing a true single-photon source. We finally propose a state-of-art implementation in a standard silicon-based photonic crystal integrated circuit that outperforms existing parametric devices either in input power or footprint area.

  4. Evolution of single-particle structure of silicon isotopes

    Science.gov (United States)

    Bespalova, O. V.; Fedorov, N. A.; Klimochkina, A. A.; Markova, M. L.; Spasskaya, T. I.; Tretyakova, T. Yu.

    2018-01-01

    New data on proton and neutron single-particle energies E_{nlj} of Si isotopes with neutron number N from 12 to 28 as well as occupation probabilities N_{nlj} of single-particle states of stable isotopes 28, 30Si near the Fermi energy were obtained by the joint evaluation of the stripping and pick-up reaction data and excited state decay schemes of neighboring nuclei. The evaluated data indicate the following features of single-particle structure evolution: persistence of Z = 14 subshell closure with N increase, the new magicity of the number N = 16, and the conservation of the magic properties of the number N = 20 in Si isotopic chain. The features were described by the dispersive optical model. The calculation also predicts the weakening of N = 28 shell closure and demonstrates evolution of a bubble-like structure of the proton density distributions in neutron-rich Si isotopes.

  5. Single-charge tunneling in ambipolar silicon quantum dots

    NARCIS (Netherlands)

    Müller, Filipp

    2015-01-01

    Spin qubits in coupled quantum dots (QDs) are promising for future quantum information processing (QIP). A quantum bit (qubit) is the quantum mechanical analogon of a classical bit. In general, each quantum mechanical two-level system can represent a qubit. For the spin of a single charge carrier

  6. Single-layer graphene on silicon nitride micromembrane resonators

    DEFF Research Database (Denmark)

    Schmid, Silvan; Bagci, Tolga; Zeuthen, Emil

    2014-01-01

    for exciting new devices, such as optoelectromechanical transducers. Here, we add a single-layer graphene on SiN micromembranes and compare electromechanical coupling and mechanical properties to bare dielectric membranes and to membranes metallized with an aluminium layer. The electrostatic coupling...

  7. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  8. Microelectronic temperature sensor; silicon temperature sensor

    International Nuclear Information System (INIS)

    Beitner, M.; Kanert, W.; Reichert, H.

    1982-01-01

    The goal of this work was to develop a silicon temperature sensor with a sensitivity and a reliability as high and a tolerance as small as possible, for use in measurement and control. By employing the principle of spreading-resistance, using silicon doped by neutron transmutation, and trimming of the single wafer tolerances of resistance less than +- 5% can be obtained; overstress tests yielded a long-term stability better than 0.2%. Some applications show the advantageous use of this sensor. (orig.) [de

  9. Simple and controlled single electron transistor based on doping modulation in silicon nanowires

    Science.gov (United States)

    Hofheinz, M.; Jehl, X.; Sanquer, M.; Molas, G.; Vinet, M.; Deleonibus, S.

    2006-10-01

    A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and therefore controlled by lithography. The source and drain capacitances have also been characterized. This design could be used to build more complex SET devices.

  10. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  11. Charge carrier Density Imaging / IR lifetime mapping of Si wafers by Lock-In Thermography

    NARCIS (Netherlands)

    Van der Tempel, L.

    2012-01-01

    ABSTRACT Minority carrier lifetime imaging by lock-in thermography of passivated silicon wafers for photovoltaic cells has been developed for the public Pieken in de Delta project geZONd. CONCLUSIONS Minority carrier lifetime imaging by lock-in thermography of passivatedsilicon wafers is released

  12. Analysis of single-photon time resolution of FBK silicon photomultipliers

    International Nuclear Information System (INIS)

    Acerbi, Fabio; Ferri, Alessandro; Gola, Alberto; Zorzi, Nicola; Piemonte, Claudio

    2015-01-01

    We characterized and analyzed an important feature of silicon photomultipliers: the single-photon time resolution (SPTR). We characterized the SPTR of new RGB (Red–Green–Blue) type Silicon Photomultipliers and SPADs produced at FBK (Trento, Italy), studying its main limiting factors. We compared time resolution of 1×1 mm 2 and 3×3 mm 2 SiPMs and a single SiPM cell (i.e. a SPAD with integrated passive-quenching), employing a mode-locked pulsed laser with 2-ps wide pulses. We estimated the contribution of front-end electronic-noise, of cell-to-cell uniformity, and intrinsic cell time-resolution. At a single-cell level, we compared the results obtained with different layouts. With a circular cell with a top metallization covering part of the edge and enhancing the signal extraction, we reached ~20 ps FWHM of time resolution

  13. Analysis of single-photon time resolution of FBK silicon photomultipliers

    Energy Technology Data Exchange (ETDEWEB)

    Acerbi, Fabio, E-mail: acerbi@fbk.eu; Ferri, Alessandro; Gola, Alberto; Zorzi, Nicola; Piemonte, Claudio

    2015-07-01

    We characterized and analyzed an important feature of silicon photomultipliers: the single-photon time resolution (SPTR). We characterized the SPTR of new RGB (Red–Green–Blue) type Silicon Photomultipliers and SPADs produced at FBK (Trento, Italy), studying its main limiting factors. We compared time resolution of 1×1 mm{sup 2} and 3×3 mm{sup 2} SiPMs and a single SiPM cell (i.e. a SPAD with integrated passive-quenching), employing a mode-locked pulsed laser with 2-ps wide pulses. We estimated the contribution of front-end electronic-noise, of cell-to-cell uniformity, and intrinsic cell time-resolution. At a single-cell level, we compared the results obtained with different layouts. With a circular cell with a top metallization covering part of the edge and enhancing the signal extraction, we reached ~20 ps FWHM of time resolution.

  14. Fabrication of single-crystal silicon nanotubes with sub-10 nm walls using cryogenic inductively coupled plasma reactive ion etching

    Science.gov (United States)

    Li, Zhiqin; Chen, Yiqin; Zhu, Xupeng; Zheng, Mengjie; Dong, Fengliang; Chen, Peipei; Xu, Lihua; Chu, Weiguo; Duan, Huigao

    2016-09-01

    Single-crystal silicon nanostructures have attracted much attention in recent years due in part to their unique optical properties. In this work, we demonstrate direct fabrication of single-crystal silicon nanotubes with sub-10 nm walls which show low reflectivity. The fabrication was based on a cryogenic inductively coupled plasma reactive ion etching process using high-resolution hydrogen silsesquioxane nanostructures as the hard mask. Two main etching parameters including substrate low-frequency power and SF6/O2 flow rate ratio were investigated to determine the etching mechanism in the process. With optimized etching parameters, high-aspect-ratio silicon nanotubes with smooth and vertical sub-10 nm walls were fabricated. Compared to commonly-used antireflection silicon nanopillars with the same feature size, the densely packed silicon nanotubes possessed a lower reflectivity, implying possible potential applications of silicon nanotubes in photovoltaics.

  15. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  16. Enhancement mode single electron transistor in pure silicon

    Science.gov (United States)

    Hu, Binhui; Yang, C. H.; Jones, G. M.; Yang, M. J.

    2007-03-01

    Solid state implementations of lateral qubits offer the advantage of being scalable and can be easily integrated by existing main stream IC technologies. In addition, the two Zeeman states of an electron spin in a quantum dot (QD) provide a promising candidate for a qubit. Spins in lateral QDs in the GaAs/AlGaAs single electron transistors (SETs) have been intensively investigated. In contrast, Si provides a number of advantages, including long spin coherence time, large g-factor, and small spin-orbit coupling effect. We have demonstrated Si SET in the few electron regime.* In this talk, we will report the isolation of a single electron in a Si QD using a fabrication technique that incorporates the standard Al/SiO2/Si system with an enhancement mode SET structure. Our SET is built in highly resistive Si substrates with bilayer gates. The high purity Si minimizes the potential disorder from impurities. The top gate induces 2D electrons, and several side gates help define the tunneling barriers, fine tune the shape of the QD, and control the number of electrons in it. We will discuss the operating principle, computer simulation, and low temperature transport data. *APPLIED PHYSICS LETTERS 89, 073106 (2006)

  17. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    International Nuclear Information System (INIS)

    Heib, F.; Hempelmann, R.; Munief, W.M.; Ingebrandt, S.; Fug, F.; Possart, W.; Groß, K.; Schmitt, M.

    2015-01-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ a and the receding θ r contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple line dis

  18. Wafer-Scale Aluminum Nanoplasmonic Resonators with Optimized Metal Deposition

    Science.gov (United States)

    2016-01-04

    plasmonics. Unlike plasmonic devices based on coinage metals , such as gold and silver , which are effectively banned from silicon semiconductor fabrication...necessarily represent the view of the United States Government. Wafer-scale Aluminum Nanoplasmonic Resonators with Optimized Metal Deposition...method of aluminum deposition. Three-layer metal -dielectric- metal nanopillar arrays were fabricated in a complementary metal -oxide semiconductor (CMOS

  19. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  20. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  1. Surface texture of single-crystal silicon oxidized under a thin V{sub 2}O{sub 5} layer

    Energy Technology Data Exchange (ETDEWEB)

    Nikitin, S. E., E-mail: nikitin@mail.ioffe.ru; Verbitskiy, V. N.; Nashchekin, A. V.; Trapeznikova, I. N.; Bobyl, A. V.; Terukova, E. E. [Russian Academy of Sciences, Ioffe Physical–Technical Institute (Russian Federation)

    2017-01-15

    The process of surface texturing of single-crystal silicon oxidized under a V{sub 2}O{sub 5} layer is studied. Intense silicon oxidation at the Si–V{sub 2}O{sub 5} interface begins at a temperature of 903 K which is 200 K below than upon silicon thermal oxidation in an oxygen atmosphere. A silicon dioxide layer 30–50 nm thick with SiO{sub 2} inclusions in silicon depth up to 400 nm is formed at the V{sub 2}O{sub 5}–Si interface. The diffusion coefficient of atomic oxygen through the silicon-dioxide layer at 903 K is determined (D ≥ 2 × 10{sup –15} cm{sup 2} s{sup –1}). A model of low-temperature silicon oxidation, based on atomic oxygen diffusion from V{sub 2}O{sub 5} through the SiO{sub 2} layer to silicon, and SiO{sub x} precipitate formation in silicon is proposed. After removing the V{sub 2}O{sub 5} and silicon-dioxide layers, texture is formed on the silicon surface, which intensely scatters light in the wavelength range of 300–550 nm and is important in the texturing of the front and rear surfaces of solar cells.

  2. Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

    Science.gov (United States)

    1989-12-01

    for both tiIhe test anid referer c lar rr ’I) was accessedl throuigh a BNC connector on lie friit panel of thle HP 4~ 19 1A. F’or all gaini- phase...rrforturnatelv. nonie 4fthle alpriolnriate stakl~ ardl calibrations suppId with other mi- cro)wave p~rob~es ( sh as thle Cascade lprAlws described! in (78...made through cables from the probes to the BNC connectors on the front, panel of the lip 4191A. 3. Volt-ohm meter, for continuity verification. 4. Z-248

  3. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  4. Silicon Wafer X-ray Mirror

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  5. Control of single-electron charging of metallic nanoparticles onto amorphous silicon surface.

    Science.gov (United States)

    Weis, Martin; Gmucová, Katarína; Nádazdy, Vojtech; Capek, Ignác; Satka, Alexander; Kopáni, Martin; Cirák, Július; Majková, Eva

    2008-11-01

    Sequential single-electron charging of iron oxide nanoparticles encapsulated in oleic acid/oleyl amine envelope and deposited by the Langmuir-Blodgett technique onto Pt electrode covered with undoped hydrogenated amorphous silicon film is reported. Single-electron charging (so-called quantized double-layer charging) of nanoparticles is detected by cyclic voltammetry as current peaks and the charging effect can be switched on/off by the electric field in the surface region induced by the excess of negative/positive charged defect states in the amorphous silicon layer. The particular charge states in amorphous silicon are created by the simultaneous application of a suitable bias voltage and illumination before the measurement. The influence of charged states on the electric field in the surface region is evaluated by the finite element method. The single-electron charging is analyzed by the standard quantized double layer model as well as two weak-link junctions model. Both approaches are in accordance with experiment and confirm single-electron charging by tunnelling process at room temperature. This experiment illustrates the possibility of the creation of a voltage-controlled capacitor for nanotechnology.

  6. Temperature effect on phase states of quartz nano-crystals in silicon single crystal

    International Nuclear Information System (INIS)

    Kalanov, M.U.; Ibragimova, E.M.; Khamraeva, R.N.; Rustamova, V.M.; Ummatov, Kh.D.

    2006-01-01

    Full text: Oxygen penetrates into the silicon lattice up to the concentration of 2·10 18 cm -3 in the course of growing [1]. By the author's opinion at a low oxygen content the formation of solid solution is possible in the local defect places of the silicon single crystal lattice due to the difference in effective ion radius of oxygen and silicon (r O 0.176 and r Si = 0.065 nm). Upon reaching some critical content (∼ 10 17 cm -3 ), it becomes favorable energetically for oxygen ions to form precipitates (SiO x ) and finally a dielectric layer (stoichiometric inclusions of SiO 2 ). It was shown later that depending on the growth conditions, indeed the quartz crystal inclusions are formed in the silicon single crystals at an amount of 0.3 /0.5 wt. % [2]. However the authors did not study a phase state of the quartz inclusions. Therefore the aim of this work was to study a phase state of the quartz inclusions in silicon crystal at various temperatures. We examined the silicon single crystals grown by Czochralski technique, which were cut in (111) plane in the form of disk of 20 mm diameter and 1.5 thickness and had hole conductivity with the specific resistance ρ o ≅ 1/10 Ohm cm. The dislocation density was N D ≅ 10 1 /10 3 cm -2 , the concentrations of oxygen and boron were N 0 ≅ 2/ 4·10 17 cm -3 and N B ≅ 3*10 15 cm -3 . Structure was analyzed at the set-up DRON-UM1 with high temperature supply UVD-2000 ( CuK = 0.1542 nm) at the temperatures of 300, 1173 and 1573 K measured with platinum-platinum-rhodium thermocouple. The high temperature diffraction spectrum measured at 1573 K in the angle range (2Θ≅10/70 d egree ) there is only one main structure reflection (111) with a high intensity and d/n ≅ 0.3136 nm (2 Θ≅ 28.5 d egree ) from the matrix lattice of silicon single crystal. The weak line at 2 Θ≅ 25.5 d egree ( d/n≅0.3136 nm) is β component of the main reflection (111), and the weak structure peak at 2Θ≅59 d egree ( d/n≅ 0.1568 nm

  7. Wafer fab mask qualification techniques and limitations

    Science.gov (United States)

    Poock, Andre; Maelzer, Stephanie; Spence, Chris; Tabery, Cyrus; Lang, Michael; Schnasse, Guido; Peikert, Milko; Bhattacharyya, Kaustuve

    2006-10-01

    Mask inspection and qualification is a must for wafer fabs to ensure and guarantee high and stable yields. Single defect events can easily cause a million dollar loss through a defect duplicating onto the wafer. Several techniques and methods for mask qualification within a wafer fab are known but not all of them are neither used nor understood regarding their limitations. Increasing effort on existing tool platforms is necessary to detect the defects of interest which are at the limit of the tools specification - On the other hand next generation tools are very sensitive and therefore consume only a negligible amount of time for recipe optimization. Knowing the limits of each inspection tool helps to balance between effort and benefit. Masks with programmed defects of 90nm and 65nm design rule were used in order to compare the different available inspection techniques. During the course of this technical work, the authors concentrate mainly on two inspection techniques. The first one inspects the reticle itself using KLA-Tencor's SLF27 (TeraStar) and SL536 (TeraScan) tools. As the reticle gets inspected itself this is the so called "direct" mask defect inspection. The second inspection technique discussed is the "indirect" mask defect inspection which consists of printing the pattern on a blank wafer and use KLA-Tencor's bright-field wafer inspection tool (2xxx series) to inspect the wafer. Data of this work will include description of the techniques, inspection results, defect maps, sensitivity analysis, effort estimation as well as limitations for both techniques for the used design rule.

  8. Spin Measurements of an Electron Bound to a Single Phosphorous Donor in Silicon

    Science.gov (United States)

    Luhman, D. R.; Nguyen, K.; Tracy, L. A.; Carr, S. M.; Borchardt, J.; Bishop, N. C.; Ten Eyck, G. A.; Pluym, T.; Wendt, J.; Carroll, M. S.; Lilly, M. P.

    2014-03-01

    The spin of an electron bound to a single donor implanted in silicon is potentially useful for quantum information processing. We report on our efforts to measure and manipulate the spin of an electron bound to a single P donor in silicon. A low number of P donors are implanted using a self-aligned process into a silicon substrate in close proximity to a single-electron-transistor (SET) defined by lithographically patterned polysilicon gates. The SET is used to sense the occupancy of the electron on the donor and for spin read-out. An adjacent transmission line allows the application of microwave pulses to rotate the spin of the electron. We will present data from various experiments designed to exploit these capabilities. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. The work was supported by Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  9. Enhancing the brightness of electrically driven single-photon sources using color centers in silicon carbide

    Science.gov (United States)

    Khramtsov, Igor A.; Vyshnevyy, Andrey A.; Fedyanin, Dmitry Yu.

    2018-03-01

    Practical applications of quantum information technologies exploiting the quantum nature of light require efficient and bright true single-photon sources which operate under ambient conditions. Currently, point defects in the crystal lattice of diamond known as color centers have taken the lead in the race for the most promising quantum system for practical non-classical light sources. This work is focused on a different quantum optoelectronic material, namely a color center in silicon carbide, and reveals the physics behind the process of single-photon emission from color centers in SiC under electrical pumping. We show that color centers in silicon carbide can be far superior to any other quantum light emitter under electrical control at room temperature. Using a comprehensive theoretical approach and rigorous numerical simulations, we demonstrate that at room temperature, the photon emission rate from a p-i-n silicon carbide single-photon emitting diode can exceed 5 Gcounts/s, which is higher than what can be achieved with electrically driven color centers in diamond or epitaxial quantum dots. These findings lay the foundation for the development of practical photonic quantum devices which can be produced in a well-developed CMOS compatible process flow.

  10. Single-mask thermal displacement sensor in MEMS

    NARCIS (Netherlands)

    Krijnen, B.; Hogervorst, R.P.; Engelen, Johannes Bernardus Charles; van Dijk, J.W.; Brouwer, Dannis Michel; Abelmann, Leon

    In this work we describe a one degree- of-freedom microelectromechanical thermal displacement sensor integrated with an actuated stage. The system was fabricated in the device layer of a silicon-on-insulator wafer using a single-mask process. The sensor is based on the temperature dependent

  11. Wafer thinning for high-density, through-wafer interconnects

    Science.gov (United States)

    Wang, Lianwei; Visser, Cassan C. G.; de Boer, Charles R.; Laros, M.; van der Vlist, W.; Groeneweg, J.; Craciun, G.; Sarro, Pasqualina M.

    2003-01-01

    Thinning of micromachined wafers containing trenches and cavities to realize through-chip interconnects is presented. Successful thinning of wafers by lapping and polishing until the cavities previously etched by deep reactive ion etching are reached is demonstrated. The possible causes of damage to the etched structures are investigated. The trapping of particles in the cavities and suitable cleaning procedures to address this issue are studied. The results achieved so far allow further processing of the thinned wafers to form through wafer interconnections by copper electroplating. Further improvement of the quality of thinned surfaces can be achieved by alternative cleaning procedures.

  12. Preservation of Seed Crystals in Feedstock Melting for Cast Quasi-Single Crystalline Silicon Ingots

    Directory of Open Access Journals (Sweden)

    Zaoyang Li

    2013-01-01

    Full Text Available The preservation of seed crystals is important for the casting of quasi-single crystalline (QSC silicon ingots. We carried out transient global simulations of the feedstock melting process in an industrial-sized directional solidification (DS furnace to investigate key factors influencing seed preservation. The power distribution between the top and side heaters is adjusted in the conventional furnace for multicrystalline silicon ingots and in the evolved furnace with a partition block for QSC silicon ingots. The evolution of the solid-liquid interface for melting and the temperature distribution in the furnace core area are analyzed. The power distribution can influence the temperature gradient in the silicon domain significantly. However, its effect on seed preservation is limited in both furnaces. Seed crystals can be preserved in the evolved furnace, as the partition block reduces the radiant heat flux from the insulation walls to the heat exchange block and prevents the heat flowing upwards under the crucible. Therefore, the key to seed preservation is to control radiant heat transfer in the DS furnace and guarantee downward heat flux under the crucible.

  13. Surface finish in ultra-precision diamond turning of single-crystal silicon

    Science.gov (United States)

    Ayomoh, M.; Abou-El-Hossein, K.

    2015-10-01

    Silicon is an optical material widely used in the production of infrared optics. However, silicon as a brittle material exhibits some difficulties when ultra-precision machined by mono-crystalline single point diamond. Finish turning of silicon with mono- crystalline diamond inserts results in accelerated tool wear rates if the right combination of the machining parameters is not properly selected. In this study, we conducted a series of machining tests on an ultra-high precision machine tool using finish turning conditions when using mono-crystalline diamond inserts with negative rake angle and relatively big nose radius. The study yields some recommendations on the best combination of machining parameters that will result in maximum material removal rates with smallest possible surface finish. In this work, standard non-controlled waviness diamond inserts having nose radius of about 1.5 mm, rake angle of negative 25°, and clearance angle of 5° were used to produce flat surfaces on silicon disk. From the results, it has been established that feed rate has the most influential effect followed by the depth of cut and cutting speed.

  14. Porous silicon: Synthesis and optical properties

    International Nuclear Information System (INIS)

    Naddaf, M.; Awad, F.

    2006-06-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  15. Electronic spectrum of a deterministic single-donor device in silicon

    International Nuclear Information System (INIS)

    Fuechsle, Martin; Miwa, Jill A.; Mahapatra, Suddhasatta; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.

    2013-01-01

    We report the fabrication of a single-electron transistor (SET) based on an individual phosphorus dopant that is deterministically positioned between the dopant-based electrodes of a transport device in silicon. Electronic characterization at mK-temperatures reveals a charging energy that is very similar to the value expected for isolated P donors in a bulk Si environment. Furthermore, we find indications for bulk-like one-electron excited states in the co-tunneling spectrum of the device, in sharp contrast to previous reports on transport through single dopants

  16. A novel hybrid III–V/silicon deformed micro-disk single-mode laser

    International Nuclear Information System (INIS)

    Feng Peng; Zhang Yejin; Liu Lei; Zhang Siriguleng; Wang Hailing; Zheng Wanhua; Wang Yufei

    2015-01-01

    A novel hybrid III–V/silicon deformed micro-disk single-mode laser connecting to a Si output waveguide is designed, and fabricated through BCB bonding technology and standard i-line photolithography. Compared to a traditional circular micro-disk in multi-longitudinal-mode operation, unidirectional emission and single longitudinal-mode output from a Si waveguide are realized. In the experiments, an output power of 0.31 mW and a side-mode suppression ratio of 27 dB in the continuous-wave regime are obtained. (semiconductor devices)

  17. Low Temperature Characterization of PMOS-type Gate-all-around Silicon nanowire FETs as single-hole-transistors

    Science.gov (United States)

    Hong, B. H.; Hwang, S. W.; Lee, Y. Y.; Son, M. H.; Ahn, D.; Cho, K. H.; Yeo, K. H.; Kim, D.-W.; Jin, G. Y.; Park, D.

    2011-12-01

    We report the single hole tunneling characteristics observed from a PMOS-type gate-all-around silicon nanowire field-effect-transistor with the radius 5 nm and the length 44 nm. The total capacitance of the quantum dot obtained from the measured Coulomb oscillations and Coulomb diamonds matches with the ideal capacitance of the silicon cylinder. It suggests that the observed single hole tunneling is originated from the fabricated structure.

  18. IR and UV laser-induced morphological changes in silicon surface under oxygen atmosphere

    Energy Technology Data Exchange (ETDEWEB)

    Jimenez-Jarquin, J.; Fernandez-Guasti, M.; Haro-Poniatowski, E.; Hernandez-Pozos, J.L. [Laboratorio de Optica Cuantica, Departamento de Fisica, Universidad Autonoma Metropolitana-Iztapalapa, Av. San Rafael Atlixco No. 186, Col. Vicentina, C.P. 09340, Mexico D.F. (Mexico)

    2005-08-01

    We irradiated silicon (100) wafers with IR (1064 nm) and UV (355 nm) nanosecond laser pulses with energy densities within the ablation regime and used scanning electron microscopy to analyze the morphological changes induced on the Si surface. The changes in the wafer morphology depend both on the incident radiation wavelength and the environmental atmosphere. We have patterned Si surfaces with a single focused laser spot and, in doing the experiments with IR or UV this reveals significant differences in the initial surface cracking and pattern formation, however if the experiment is carried out in O{sub 2} the final result is an array of microcones. We also employed a random scanning technique to irradiate the silicon wafer over large areas, in this case the microstructure patterns consist of a ''semi-ordered'' array of micron-sized cones. (copyright 2005 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  19. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon

    Science.gov (United States)

    Tracy, Lisa; Luhman, Dwight; Carr, Stephen; Borchardt, John; Bishop, Nathaniel; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Witzel, Wayne; Blume-Kohout, Robin; Nielsen, Erik; Lilly, Michael; Carroll, Malcolm

    In this talk we will discuss electron spin resonance experiments in single donor silicon qubit devices fabricated at Sandia National Labs. A self-aligned device structure consisting of a polysilicon gate SET located adjacent to the donor is used for donor electron spin readout. Using a cryogenic HEMT amplifier next to the silicon device, we demonstrate spin readout at 100 kHz bandwidth and Rabi oscillations with 0.96 visibility. Electron spin resonance measurements on these devices show a linewidth of 30 kHz and coherence times T2* = 10 us and T2 = 0.3 ms. We also discuss estimates of the fidelity of our donor electron spin qubit measurements using gate set tomography. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon.

  20. Mapping the "forbidden" transverse-optical phonon in single strained silicon (100) nanowire.

    Science.gov (United States)

    Tarun, Alvarado; Hayazawa, Norihiko; Ishitobi, Hidekazu; Kawata, Satoshi; Reiche, Manfred; Moutanabbir, Oussama

    2011-11-09

    The accurate manipulation of strain in silicon nanowires can unveil new fundamental properties and enable novel or enhanced functionalities. To exploit these potentialities, it is essential to overcome major challenges at the fabrication and characterization levels. With this perspective, we have investigated the strain behavior in nanowires fabricated by patterning and etching of 15 nm thick tensile strained silicon (100) membranes. To this end, we have developed a method to excite the "forbidden" transverse-optical (TO) phonons in single tensile strained silicon nanowires using high-resolution polarized Raman spectroscopy. Detecting this phonon is critical for precise analysis of strain in nanoscale systems. The intensity of the measured Raman spectra is analyzed based on three-dimensional field distribution of radial, azimuthal, and linear polarizations focused by a high numerical aperture lens. The effects of sample geometry on the sensitivity of TO measurement are addressed. A significantly higher sensitivity is demonstrated for nanowires as compared to thin layers. In-plane and out-of-plane strain profiles in single nanowires are obtained through the simultaneous probe of local TO and longitudinal-optical (LO) phonons. New insights into strained nanowires mechanical properties are inferred from the measured strain profiles.

  1. Nonequilibrium Growth of GaN/Si(1-x-y)Ge(x)C(y)/Silicon-on-Insulator

    National Research Council Canada - National Science Library

    Ho, Wilson

    2000-01-01

    ... of this growth technique. Research highlights include the successful growth of silicon carbide, gallium nitride, and aluminum nitride thin films on silicon and miscut silicon substrates, on four-inches silicon wafers...

  2. Wafer-shape based in-plane distortion predictions using superfast 4G metrology

    Science.gov (United States)

    van Dijk, Leon; Mileham, Jeffrey; Malakhovsky, Ilja; Laidler, David; Dekkers, Harold; Van Elshocht, Sven; Anberg, Doug; Owen, David M.; van Haren, Richard

    2017-03-01

    With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent ( 1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.

  3. Direct monolithic integration of vertical single crystalline octahedral molecular sieve nanowires on silicon

    Energy Technology Data Exchange (ETDEWEB)

    Carretero-Genevrier, Adrian [Institut des Nanotechnologies de Lyon (INL), UMR-CNRS 5270, Ecole Central de Lyon, Ecully (France); Institut de Ciencia de Materials de Barcelona ICMAB, Catalonia (Spain); Sorbonne Univ., UPMC Univ. Paris 06, CNRS, College de France, Paris (France); Oro-Sole, Judith [Institut de Ciencia de Materials de Barcelona ICMAB, Catalonia (Spain); Gazquez, Jaume [Institut de Ciencia de Materials de Barcelona ICMAB, Catalonia (Spain); Magen, Cesar [Univ. de Zaragoza, Zaragoza (Spain); Miranda, Laura [Sorbonne Univ., UPMC Univ. Paris 06, CNRS, College de France, Paris (France); Puig, Teresa [Institut de Ciencia de Materials de Barcelona ICMAB, Catalonia (Spain); Obradors, Xavier [Institut de Ciencia de Materials de Barcelona ICMAB, Catalonia (Spain); Ferain, Etienne [Univ. Catholique de Louvain, Louvain-la-Neuve (Belgium); Sanchez, Clement [Sorbonne Univ., UPMC Univ. Paris 06, CNRS, College de France, Paris (France); Rodriguez-Carvajal, Juan [Institut Laue-Langevin, Grenoble Cedex (France); Mestres, Narcis [Institut de Ciencia de Materials de Barcelona ICMAB, Catalonia (Spain)

    2013-12-13

    We developed an original strategy to produce vertical epitaxial single crystalline manganese oxide octahedral molecular sieve (OMS) nanowires with tunable pore sizes and compositions on silicon substrates by using a chemical solution deposition approach. The nanowire growth mechanism involves the use of track-etched nanoporous polymer templates combined with the controlled growth of quartz thin films at the silicon surface, which allowed OMS nanowires to stabilize and crystallize. α-quartz thin films were obtained after thermal activated crystallization of the native amorphous silica surface layer assisted by Sr2+- or Ba2+-mediated heterogeneous catalysis in the air at 800 °C. These α-quartz thin films work as a selective template for the epitaxial growth of randomly oriented vertical OMS nanowires. Furthermore, the combination of soft chemistry and epitaxial growth opens new opportunities for the effective integration of novel technological functional tunneled complex oxides nanomaterials on Si substrates.

  4. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  5. Friction and metal transfer for single-crystal silicon carbide in contact with various metals in vacuum

    International Nuclear Information System (INIS)

    Miyoshi, K.; Buckley, D.H.

    1978-04-01

    Sliding friction experiments were conducted with single-crystal silicon carbide in contact with transition metals (tungsten, iron, rhodium, nickel, titanium, and cobalt), copper, and aluminum. Results indicate the coefficient of friction for a silicon carbide-metal system is related to the d bond character and relative chemical activity of the metal. The more active the metal, the higher the coefficient of friction. All the metals examined transferred to the surface of silicon carbide in sliding. The chemical activity of metal to silicon and carbon and shear modulus of the metal may play important roles in metal transfer and the form of the wear debris. The less active metal is, and the greater resistance to shear it has, with the exception of rhodium and tungsten, the less transfer to silicon carbide

  6. Development of Single-Sided Silicon Detectors in the Emulsion-Hybrid System at J-PARC

    Science.gov (United States)

    Lee, J. Y.; Ahn, J. K.; Ekawa, H.; Han, Y. C.; Hasegawa, S.; Hayakawa, S.; Hayakawa, T.; Hosomi, K.; Hwang, S. H.; Imai, K.; Ito, K.; Kim, M. H.; Kim, S. H.; Kiuchi, R.; Moon, T. J.; Nakazawa, K.; Oue, K.; Sako, H.; Sato, S.; Sugimura, H.; Tanida, K.; Watabe, T.

    A new single-sided silicon micro-strip detector (SSD) is being developed at the J-PARC K1.8 beam line for an emulsion-counter hybrid experiment (J-PARC E07). The SSD will be mainly used for vetex measurements in emulsion plates. Two prototypes of SSD have been fabricated to check the performance of the circuit board and silicon sensors. The first prototype consists of only one layer of a silicon sensor whereas the second prototype consists of two layers of silicon sensors. The final product will be a stack of 4 layers of silicon sensors in the order of X-Y-X-Y. The first and second prototypes of SSD have been tested and the final product will be fabricated based on the test result.

  7. Transformational silicon electronics

    KAUST Repository

    Rojas, Jhonathan Prieto

    2014-02-25

    In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

  8. SEM-induced shrinkage and site-selective modification of single-crystal silicon nanopores

    Science.gov (United States)

    Chen, Qi; Wang, Yifan; Deng, Tao; Liu, Zewen

    2017-07-01

    Solid-state nanopores with feature sizes around 5 nm play a critical role in bio-sensing fields, especially in single molecule detection and sequencing of DNA, RNA and proteins. In this paper we present a systematic study on shrinkage and site-selective modification of single-crystal silicon nanopores with a conventional scanning electron microscope (SEM). Square nanopores with measurable sizes as small as 8 nm × 8 nm and rectangle nanopores with feature sizes (the smaller one between length and width) down to 5 nm have been obtained, using the SEM-induced shrinkage technique. The analysis of energy dispersive x-ray spectroscopy and the recovery of the pore size and morphology reveal that the grown material along with the edge of the nanopore is the result of deposition of hydrocarbon compounds, without structural damage during the shrinking process. A simplified model for pore shrinkage has been developed based on observation of the cross-sectional morphology of the shrunk nanopore. The main factors impacting on the task of controllably shrinking the nanopores, such as the accelerating voltage, spot size, scanned area of e-beam, and the initial pore size have been discussed. It is found that single-crystal silicon nanopores shrink linearly with time under localized irradiation by SEM e-beam in all cases, and the pore shrinkage rate is inversely proportional to the initial equivalent diameter of the pore under the same e-beam conditions.

  9. Nanopore arrays in a silicon membrane for parallel single-molecule detection: DNA translocation.

    Science.gov (United States)

    Zhang, Miao; Schmidt, Torsten; Jemt, Anders; Sahlén, Pelin; Sychugov, Ilya; Lundeberg, Joakim; Linnros, Jan

    2015-08-07

    Optical nanopore sensing offers great potential in single-molecule detection, genotyping, or DNA sequencing for high-throughput applications. However, one of the bottle-necks for fluorophore-based biomolecule sensing is the lack of an optically optimized membrane with a large array of nanopores, which has large pore-to-pore distance, small variation in pore size and low background photoluminescence (PL). Here, we demonstrate parallel detection of single-fluorophore-labeled DNA strands (450 bps) translocating through an array of silicon nanopores that fulfills the above-mentioned requirements for optical sensing. The nanopore array was fabricated using electron beam lithography and anisotropic etching followed by electrochemical etching resulting in pore diameters down to ∼7 nm. The DNA translocation measurements were performed in a conventional wide-field microscope tailored for effective background PL control. The individual nanopore diameter was found to have a substantial effect on the translocation velocity, where smaller openings slow the translocation enough for the event to be clearly detectable in the fluorescence. Our results demonstrate that a uniform silicon nanopore array combined with wide-field optical detection is a promising alternative with which to realize massively-parallel single-molecule detection.

  10. Compact single-chip VMUX/DEMUX on the silicon-on-insulator platform.

    Science.gov (United States)

    Feng, Dazeng; Feng, Ning-Ning; Kung, Cheng-Chih; Liang, Hong; Qian, Wei; Fong, Joan; Luff, B Jonathan; Asghari, Mehdi

    2011-03-28

    We demonstrate a compact, single-chip 40-channel, dense wavelength division multiplexing (DWDM) variable attenuator multi/demultiplexer (VMUX/DEMUX) by monolithic integration of an echelle grating and high-speed p-i-n VOA on the silicon-on-insulator (SOI) platform. The demonstrated device has a flat-top filter shape, on chip loss of 5.0 dB, low PDL of 0.3 dB after compensation of the polarization dependent frequency (PDF) shift, a fast attenuation response speed of 3 MHz, and an area of only 25 mm by 10 mm.

  11. Fabrication of double-dot single-electron transistor in silicon nanowire

    Energy Technology Data Exchange (ETDEWEB)

    Jo, Mingyu; Kaizawa, Takuya; Arita, Masashi [Graduate School of Information Science and Technology, Hokkaido Univ., Sapporo, 060-0814 (Japan); Fujiwara, Akira; Ono, Yukinori [NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato Wakamiya, Atsugi, 243-0198 (Japan); Inokawa, Hiroshi [Research Institute of Electronics, Shizuoka Univ., 3-5-1, Johoku, Hamamatsu, 432-8011 (Japan); Choi, Jung-Bum [Physics and Research Institute of NanoScience and Technology, Chungbuk National Univ., Cheongju, Chungbuk 361-763 (Korea, Republic of); Takahashi, Yasuo, E-mail: y-taka@nano.ist.hokudai.ac.j [Graduate School of Information Science and Technology, Hokkaido Univ., Sapporo, 060-0814 (Japan)

    2010-01-01

    We propose a simple method for fabricating Si single-electron transistors (SET) with coupled dots by means of a pattern-dependent-oxidation (PADOX) method. The PADOX method is known to convert a small one-dimensional Si wire formed on a silicon-on-insulator (SOI) substrate into a SET automatically. We fabricated a double-dot Si SET when we oxidized specially designed Si nanowires formed on SOI substrates. We analyzed the measured electrical characteristics by fitting the measurement and simulation results and confirmed the double-dot formation and the position of the two dots in the Si wire.

  12. Dissolution chemistry and biocompatibility of single-crystalline silicon nanomembranes and associated materials for transient electronics.

    Science.gov (United States)

    Hwang, Suk-Won; Park, Gayoung; Edwards, Chris; Corbin, Elise A; Kang, Seung-Kyun; Cheng, Huanyu; Song, Jun-Kyul; Kim, Jae-Hwan; Yu, Sooyoun; Ng, Joanne; Lee, Jung Eun; Kim, Jiyoung; Yee, Cassian; Bhaduri, Basanta; Su, Yewang; Omennetto, Fiorenzo G; Huang, Yonggang; Bashir, Rashid; Goddard, Lynford; Popescu, Gabriel; Lee, Kyung-Mi; Rogers, John A

    2014-06-24

    Single-crystalline silicon nanomembranes (Si NMs) represent a critically important class of material for high-performance forms of electronics that are capable of complete, controlled dissolution when immersed in water and/or biofluids, sometimes referred to as a type of "transient" electronics. The results reported here include the kinetics of hydrolysis of Si NMs in biofluids and various aqueous solutions through a range of relevant pH values, ionic concentrations and temperatures, and dependence on dopant types and concentrations. In vitro and in vivo investigations of Si NMs and other transient electronic materials demonstrate biocompatibility and bioresorption, thereby suggesting potential for envisioned applications in active, biodegradable electronic implants.

  13. Space-qualified silicon avalanche-photodiode single-photon-counting modules

    Science.gov (United States)

    Sun, Xiaoli; Krainak, Michael A.; Abshire, James B.; Spinhirne, James D.; Trottier, Claude; Davies, Murray; Dautet, Henri; Allan, Graham R.; Lukemire, Alan T.; Vandiver, James C.

    2004-09-01

    A space-qualified silicon avalanche-photodiode (APD) based single-photon-counting-module (SPCM) was developed for the Geoscience Laser Altimeter System (GLAS) on board NASA's Ice, Cloud, and Land Elevation Satellite (ICESat). Numerous improvements were made over the commercially available SPCMs in both performance and reliability. The measured optoelectronic parameters include, 65% photon detection efficiency at the 532 nm wavelength, 15-17 mega-counts per second (Mcps) maximum count rate and less than 200 s-1 dark counts before exposure to space radiation.

  14. Subattoampere current induced by single ions in silicon oxide layers of nonvolatile memory cells

    International Nuclear Information System (INIS)

    Cellere, G.; Paccagnella, A.; Larcher, L.; Visconti, A.; Bonanomi, M.

    2006-01-01

    A single ion impinging on a thin silicon dioxide layer generates a number of electron/hole pairs proportional to its linear energy transfer coefficient. Defects generated by recombination can act as a conductive path for electrons that cross the oxide barrier, thanks to a multitrap-assisted mechanism. We present data on the dependence of this phenomenon on the oxide thickness by using floating gate memory arrays. The tiny number of excess electrons stored in these devices allows for extremely high sensitivity, impossible with any direct measurement of oxide leakage current. Results are of particular interest for next generation devices

  15. Fracture analysis of surface exfoliation on single crystal silicon irradiated by intense pulsed ion beam

    Science.gov (United States)

    Shen, Jie; Shahid, Ijaz; Yu, Xiao; Zhang, Jie; Zhong, Haowen; Cui, Xiaojun; Liang, Guoying; Yu, Xiang; Huang, Wanying; Yan, Sha; Zhang, Gaolong; Zhang, Xiaofu; Le, Xiaoyun

    2017-12-01

    Surface exfoliation was observed on single crystal silicon surface irradiated by Intense Pulsed Ion Beam (IPIB). As the strong transient thermal stress impact induced by IPIB was mainly attributed to the exfoliation, a micro scale model combined with thermal conduction and linear elastic fracture mechanics was built to analyze the thermal stress distribution along the energy deposition process. After computation with finite element method, J integral parameter was applied as the criterion for crack development. It was demonstrated that the exfoliation initiation calls for specific material, crack depth and IPIB parameter. The results are potentially valuable for beam/target selection and IPIB parameter optimization.

  16. High-aspect-ratio grooves fabricated in silicon by a single pass of femtosecond laser pulses

    International Nuclear Information System (INIS)

    Ma Yuncan; Shi Haitao; Si Jinhai; Ren Hai; Chen Tao; Chen Feng; Hou Xun

    2012-01-01

    High-aspect-ratio grooves have been fabricated in silicon by a single pass of femtosecond laser pulses in water and ambient air. Scanning electron microscopy and energy dispersive x-ray spectroscopy were employed to image for the morphology of the photoinduced grooves and analyze the chemical composition in the surrounding of the grooves. It was observed that the sidewall of the grooves fabricated in water was much smoother than that in ambient air, and there were homogeneous nano-scale protrusions on the sidewall of the grooves fabricated in water. Meanwhile, oxygen species, which was incorporated into the grooves fabricated in air, was not observed in those in water.

  17. Single photon timing resolution and detection efficiency of the IRST silicon photo-multipliers

    International Nuclear Information System (INIS)

    Collazuol, G.; Ambrosi, G.; Boscardin, M.; Corsi, F.; Dalla Betta, G.F.; Del Guerra, A.; Dinu, N.; Galimberti, M.; Giulietti, D.; Gizzi, L.A.; Labate, L.; Llosa, G.; Marcatili, S.; Morsani, F.; Piemonte, C.; Pozza, A.; Zaccarelli, L.; Zorzi, N.

    2007-01-01

    Silicon photo-multipliers (SiPM) consist in matrices of tiny, passive quenched avalanche photo-diode cells connected in parallel via integrated resistors and operated in Geiger mode. Novel types of SiPM are being developed at FBK-IRST (Trento, Italy). Despite their classical shallow junction n-on-p structure the devices are unique in their enhanced photo-detection efficiency (PDE) for short-wavelengths and in their low level of dark rate and excess noise factor. After a summary of the extensive SiPM characterization we will focus on the study of PDE and the single photon timing resolution

  18. Deflection of high energy channeled charged particles by elastically bent silicon single crystals

    International Nuclear Information System (INIS)

    Gibson, W.M.; Kim, I.J.; Pisharodoy, M.; Salman, S.M.; Sun, C.R.; Wang, G.H.; Wijayawardana, R.; Forster, J.S.; Mitchell, I.V.; Baker, S.I.; Carrigan, R.A. Jr.; Toohig, T.E.; Avdeichikov, V.V.; Ellison, J.A.; Siffert, P.

    1984-01-01

    An experiment has been carried out to observe the deflection of charged particles by planar channeling in bent single crystals of silicon for protons with energy up to 180 GeV. Anomolous loss of particles from the center point of a three point bending apparatus was observed at high incident particle energy. This effect has been exploited to fashion a 'dechanneling spectrometer' to study dechanneling effects due to centripital displacement of channeled particle trajectories in a bent crystal. The bending losses generally conform to the predictions of calculations based on a classical model. (orig.)

  19. Structured Antireflective Coating for Silicon at Submillimeter Frequencies

    Science.gov (United States)

    Padilla, Estefania

    2018-01-01

    Observations at millimeter and submillimeter wavelengths are useful for many astronomical studies, such as the polarization of the cosmic microwave background or the formation and evolution of galaxy clusters. In order to allow observations over a broad spectral bandwidth (approximatively from 70 to 420 GHz), innovative broadband anti-reflective (AR) optics must be utilized in submillimeter telescopes. Due to its low loss and high refractive index, silicon is a fine optical material at these frequencies, but an AR coating with multiple layers is required to maximize its transmission over a wide bandwidth. Structured multilayer AR coatings for silicon are currently being developed at Caltech and JPL. The development process includes the design of the structured layers with commercial electromagnetic simulation software, the fabrication by using deep reactive ion etching, and the test of the transmission and reflection of the patterned wafers. Geometrical 3D patterns have successfully been etched at the surface of the silicon wafers creating up to 2 layers with different effective refractive indices. The transmission and reflection of single AR layer wafers, measured between 75 and 330 GHz, are close to the simulation predictions. These results allow the development of new designs with 5 or 6 AR layers in order to improve the bandwidth and transmission of the silicon AR coatings.

  20. Proposed method of assembly for the BCD silicon strip vertex detector modules

    International Nuclear Information System (INIS)

    Lindenmeyer, C.

    1989-01-01

    The BCD Silicon strip Vertex Detector is constructed of 10 identical central region modules and 18 similar forward region modules. This memo describes a method of assembling these modules from individual silicon wafers. Each wafer is fitted with associated front end electronics and cables and has been tested to insure that only good wafers reach the final assembly stage. 5 figs

  1. Optical properties of a single free standing nanodiamond

    Energy Technology Data Exchange (ETDEWEB)

    Sun, K W; Wang, C Y [Department of Applied Chemistry and Institute of Molecular Science, National Chiao Tung University, Hsinchu, 300, Taiwan (China)

    2007-12-15

    We report the techniques for measuring optical properties of a single nanometer-sized diamond. The electron beam (e-beam) lithography defined coordination markers on a silicon wafer provide us a convenient tool for allocating a single nanodiamond immobilized on the surface. By combining a confocal microscope with the e-beam lithography patterned smart substrate, we are able to measure the Raman and photoluminescence spectra from a single nanodiamond with a size less than 100 nm.

  2. Optical properties of a single free standing nanodiamond

    International Nuclear Information System (INIS)

    Sun, K W; Wang, C Y

    2007-01-01

    We report the techniques for measuring optical properties of a single nanometer-sized diamond. The electron beam (e-beam) lithography defined coordination markers on a silicon wafer provide us a convenient tool for allocating a single nanodiamond immobilized on the surface. By combining a confocal microscope with the e-beam lithography patterned smart substrate, we are able to measure the Raman and photoluminescence spectra from a single nanodiamond with a size less than 100 nm

  3. Influence of temperature on the anisotropic cutting behaviour of single crystal silicon: A molecular dynamics simulation investigation

    OpenAIRE

    Chavoshi, Saeed Zare; Goel, Saurav; Luo, Xichun

    2016-01-01

    Using molecular dynamics (MD) simulation, this paper investigates anisotropic cutting behaviour of single crystal silicon in vacuum under a wide range of substrate temperatures (300 K, 500 K, 750 K, 850 K, 1173 K and 1500 K). Specific cutting energy, force ratio, stress in the cutting zone and cutting temperature were the indicators used to quantify the differences in the cutting behaviour of silicon. A key observation was that the specific cutting energy required to cut the (1 1 1) surface o...

  4. Effects of laser fluence on silicon modification by four-beam laser interference

    International Nuclear Information System (INIS)

    Zhao, Le; Li, Dayou; Wang, Zuobin; Yue, Yong; Zhang, Jinjin; Yu, Miao; Li, Siwei

    2015-01-01

    This paper discusses the effects of laser fluence on silicon modification by four-beam laser interference. In this work, four-beam laser interference was used to pattern single crystal silicon wafers for the fabrication of surface structures, and the number of laser pulses was applied to the process in air. By controlling the parameters of laser irradiation, different shapes of silicon structures were fabricated. The results were obtained with the single laser fluence of 354 mJ/cm 2 , 495 mJ/cm 2 , and 637 mJ/cm 2 , the pulse repetition rate of 10 Hz, the laser exposure pulses of 30, 100, and 300, the laser wavelength of 1064 nm, and the pulse duration of 7–9 ns. The effects of the heat transfer and the radiation of laser interference plasma on silicon wafer surfaces were investigated. The equations of heat flow and radiation effects of laser plasma of interfering patterns in a four-beam laser interference distribution were proposed to describe their impacts on silicon wafer surfaces. The experimental results have shown that the laser fluence has to be properly selected for the fabrication of well-defined surface structures in a four-beam laser interference process. Laser interference patterns can directly fabricate different shape structures for their corresponding applications

  5. Multi-Channel 40 Gbit/s NRZ-DPSK Demodulation Using a Single Silicon Microring Resonator

    DEFF Research Database (Denmark)

    Ding, Yunhong; Xu, Jing; Peucheret, Christophe

    2011-01-01

    We comprehensively analyze the demodulation of wavelength division multiplexed (WDM) non return-to-zero differential phase-shift keying (NRZ-DPSK) signals by a single microring resonator. Simultaneous demodulation of multiple 40 Gbit/s WDM NRZ-DPSK channels is demonstrated using a single silicon...

  6. Investigation of a new low cost and low consumption single poly-silicon memory

    Directory of Open Access Journals (Sweden)

    Patrick Calenzo

    2010-10-01

    Full Text Available In this paper is presented an investigation on a new low cost and voltage consumption single poly-silicon memory cell for passive RFID (Radio Frequency IDentificationapplications. This structure is low cost due to its single poly-silicon design. This memory cell has two particularities : the first one is that no deported capacitor is necessary to program this cell which allows to reduce the structure size to 1.1μm². The second one is the way the cell is erased. A Zener diode is used to generate carriers in order to be injected into the floating gate. This Zener diode is one of the key points for the functionality that has to be validated with some electrical trials. These trials permit to integrate and use the Zener diodes measured in simulations of the complete memory cell. This is done to validate the best candidate between the Zener diodes used for the cell and highlight the efficiency in consumption and rapidity to erase the cell. Besides, the writing and the reading cases are simulated in order to show the low consumption required by the cell during these phases.

  7. Single molecule localization imaging of exosomes using blinking silicon quantum dots

    Science.gov (United States)

    Zong, Shenfei; Zong, Junzhu; Chen, Chen; Jiang, Xiaoyue; Zhang, Yizhi; Wang, Zhuyuan; Cui, Yiping

    2018-02-01

    Discovering new fluorophores, which are suitable for single molecule localization microscopy (SMLM) is important for promoting the applications of SMLM in biological or material sciences. Here, we found that silicon quantum dots (Si QDs) possess a fluorescence blinking behavior, making them an excellent candidate for SMLM. The Si QDs are fabricated using a facile microwave-assisted method. Blinking of Si QDs is confirmed by single particle fluorescence measurement and the spatial resolution achieved is about 30 nm. To explore the potential application of Si QDs as the nanoprobes for SMLM imaging, cell derived exosomes are chosen as the object owing to their small size (50-100 nm in diameter). Since CD63 is commonly presented on the membrane of exosomes, CD63 aptamers are attached to the surface of Si QDs to form nanoprobes which can specifically recognize exosomes. SMLM imaging shows that Si QDs based nanoprobes can indeed realize super resolved optical imaging of exosomes. More importantly, blinking of Si QDs is observed in water or PBS buffer with no need for special imaging buffers. Besides, considering that silicon is highly biocompatible, Si QDs should have minimal cytotoxicity. These features make Si QDs quite suitable for SMLM applications especially for live cell imaging.

  8. Resonant tunnelling features in a suspended silicon nanowire single-hole transistor

    Energy Technology Data Exchange (ETDEWEB)

    Llobet, Jordi; Pérez-Murano, Francesc, E-mail: francesc.perez@csic.es, E-mail: z.durrani@imperial.ac.uk [Institut de Microelectrònica de Barcelona (IMB-CNM CSIC), Campus UAB, E-08193 Bellaterra, Catalonia (Spain); Krali, Emiljana; Wang, Chen; Jones, Mervyn E.; Durrani, Zahid A. K., E-mail: francesc.perez@csic.es, E-mail: z.durrani@imperial.ac.uk [Department of Electrical and Electronic Engineering, Imperial College London, South Kensington, London SW7 2AZ (United Kingdom); Arbiol, Jordi [Institució Catalana de Recerca i Estudis Avançats (ICREA) and Institut Català de Nanociència i Nanotecnologia (ICN2), Campus UAB, 08193 Bellaterra, Catalonia (Spain); CELLS-ALBA Synchrotron Light Facility, 08290 Cerdanyola, Catalonia (Spain)

    2015-11-30

    Suspended silicon nanowires have significant potential for a broad spectrum of device applications. A suspended p-type Si nanowire incorporating Si nanocrystal quantum dots has been used to form a single-hole transistor. Transistor fabrication uses a novel and rapid process, based on focused gallium ion beam exposure and anisotropic wet etching, generating <10 nm nanocrystals inside suspended Si nanowires. Electrical characteristics at 10 K show Coulomb diamonds with charging energy ∼27 meV, associated with a single dominant nanocrystal. Resonant tunnelling features with energy spacing ∼10 meV are observed, parallel to both diamond edges. These may be associated either with excited states or hole–acoustic phonon interactions, in the nanocrystal. In the latter case, the energy spacing corresponds well with reported Raman spectroscopy results and phonon spectra calculations.

  9. Memory effect in silicon time-gated single-photon avalanche diodes

    Energy Technology Data Exchange (ETDEWEB)

    Dalla Mora, A.; Contini, D., E-mail: davide.contini@polimi.it; Di Sieno, L. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Tosi, A.; Boso, G.; Villa, F. [Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Pifferi, A. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); CNR, Istituto di Fotonica e Nanotecnologie, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

    2015-03-21

    We present a comprehensive characterization of the memory effect arising in thin-junction silicon Single-Photon Avalanche Diodes (SPADs) when exposed to strong illumination. This partially unknown afterpulsing-like noise represents the main limiting factor when time-gated acquisitions are exploited to increase the measurement dynamic range of very fast (picosecond scale) and faint (single-photon) optical signals following a strong stray one. We report the dependences of this unwelcome signal-related noise on photon wavelength, detector temperature, and biasing conditions. Our results suggest that this so-called “memory effect” is generated in the deep regions of the detector, well below the depleted region, and its contribution on detector response is visible only when time-gated SPADs are exploited to reject a strong burst of photons.

  10. Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

    Energy Technology Data Exchange (ETDEWEB)

    Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

    2017-07-01

    We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

  11. Fabrication of capacitive absolute pressure sensor using Si-Au eutectic bonding in SOI wafer

    International Nuclear Information System (INIS)

    Lee, Kang Ryeol; Kim, Kunnyun; Park, Hyo-Derk; Kim, Yong Kook; Choi, Seung-Woo; Choi, Woo-Beom

    2006-01-01

    A capacitive absolute pressure sensor was fabricated using a large deflected diaphragm with a sealed vacuum cavity formed by removing handling silicon wafer and oxide layers from a SOI wafer after eutectic bonding of a silicon wafer to the SOI wafer. The deflected displacements of the diaphragm formed by the vacuum cavity in the fabricated sensor were similar to simulation results. Initial capacitance values were about 2.18pF and 3.65pF under normal atmosphere, where the thicknesses of the diaphragm used to fabricate the vacuum cavity were 20 μm and 30 μm, respectively. Also, it was confirmed that the differences of capacitance value from 1000hPa to 5hPa were about 2.57pF and 5.35pF, respectively

  12. GaInP/GaP quantum dots: a material for OEIC on silicon substrates

    Science.gov (United States)

    Lee, Jong Won; Schremer, Alfred T.; Shealy, James R.; Ballantyne, Joseph M.

    1997-12-01

    Realization of optoelectronic integrated circuits on silicon substrates has many difficulties, one of which is depositing high quality light-emitting material on the silicon surface. A desirable depositing method from a manufacturing point of view is chemical vapor deposition. Because there are currently no light emitting semiconductor alloys lattice-matched to silicon, epitaxial growth of III-V compound devices on Si has required a lattice constant engineering step such as wafer bonding or thick buffer layer growth. Growth of GaInP/GaP strain-induced quantum dots offers an opportunity to grow single crystal light-emitting devices monolithically on silicon substrates without lattice constant engineering steps, since single crystal GaP can be grown on silicon. In this presentation, progress on MOCVD growth of GaInP/GaP quantum dots and its device applications are reviewed.

  13. arXiv Single-electron and single-photon sensitivity with a silicon Skipper CCD

    CERN Document Server

    Tiffenberg, Javier; Drlica-Wagner, Alex; Essig, Rouven; Guardincerri, Yann; Holland, Steve; Volansky, Tomer; Yu, Tien-Tien

    2017-09-26

    We have developed ultralow-noise electronics in combination with repetitive, nondestructive readout of a thick, fully depleted charge-coupled device (CCD) to achieve an unprecedented noise level of 0.068  e- rms/pixel. This is the first time that discrete subelectron readout noise has been achieved reproducible over millions of pixels on a stable, large-area detector. This enables the contemporaneous, discrete, and quantized measurement of charge in pixels, irrespective of whether they contain zero electrons or thousands of electrons. Thus, the resulting CCD detector is an ultra-sensitive calorimeter. It is also capable of counting single photons in the optical and near-infrared regime. Implementing this innovative non-destructive readout system has a negligible impact on CCD design and fabrication, and there are nearly immediate scientific applications. As a particle detector, this CCD will have unprecedented sensitivity to low-mass dark matter particles and coherent neutrino-nucleus scattering, while ...

  14. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  15. Single-Seed Casting Large-Size Monocrystalline Silicon for High-Efficiency and Low-Cost Solar Cells

    Directory of Open Access Journals (Sweden)

    Bing Gao

    2015-09-01

    Full Text Available To grow high-quality and large-size monocrystal-line silicon at low cost, we proposed a single-seed casting technique. To realize this technique, two challenges—polycrystalline nucleation on the crucible wall and dislocation multiplication inside the crystal—needed to be addressed. Numerical analysis was used to develop solutions for these challenges. Based on an optimized furnace structure and operating conditions from numerical analysis, experiments were performed to grow monocrystalline silicon using the single-seed casting technique. The results revealed that this technique is highly superior to the popular high-performance multicrystalline and multiseed casting mono-like techniques.

  16. Metal-Catalyst-Free Synthesis and Characterization of Single-Crystalline Silicon Oxynitride Nanowires

    Directory of Open Access Journals (Sweden)

    Shuang Xi

    2012-01-01

    Full Text Available Large quantities of single-crystal silicon oxynitride nanowires with high N concentration have been synthesized directly on silicon substrate at 1200°C without using any metal catalyst. The diameter of these ternary nanowires is ranging from 10 to 180 nm with log-normal distribution, and the length of these nanowires varies from a few hundreds of micrometers to several millimeters. A vapor-solid mechanism was proposed to explain the growth of the nanowires. These nanowires are grown to form a disordered mat with an ultrabright white nonspecular appearance. The mat demonstrates highly diffusive reflectivity with the optical reflectivity of around 80% over the whole visible wavelength, which is comparable to the most brilliant white beetle scales found in nature. The whiteness might be resulted from the strong multiscattering of a large fraction of incident light on the disordered nanowire mat. These ultra-bright white nanowires could form as reflecting surface to meet the stringent requirements of bright-white light-emitting-diode lighting for higher optical efficiency. They can also find applications in diverse fields such as sensors, cosmetics, paints, and tooth whitening.

  17. Silicon Solar Cell Process Development, Fabrication and Analysis, Phase 1

    Science.gov (United States)

    Yoo, H. I.; Iles, P. A.; Tanner, D. P.

    1979-01-01

    Solar cells from RTR ribbons, EFG (RF and RH) ribbons, dendritic webs, Silso wafers, cast silicon by HEM, silicon on ceramic, and continuous Czochralski ingots were fabricated using a standard process typical of those used currently in the silicon solar cell industry. Back surface field (BSF) processing and other process modifications were included to give preliminary indications of possible improved performance. The parameters measured included open circuit voltage, short circuit current, curve fill factor, and conversion efficiency (all taken under AM0 illumination). Also measured for typical cells were spectral response, dark I-V characteristics, minority carrier diffusion length, and photoresponse by fine light spot scanning. the results were compared to the properties of cells made from conventional single crystalline Czochralski silicon with an emphasis on statistical evaluation. Limited efforts were made to identify growth defects which will influence solar cell performance.

  18. Lightweight and High-Resolution Single Crystal Silicon Optics for X-ray Astronomy

    Science.gov (United States)

    Zhang, William W.; Biskach, Michael P.; Chan, Kai-Wing; Mazzarella, James R.; McClelland, Ryan S.; Riveros, Raul E.; Saha, Timo T.; Solly, Peter M.

    2016-01-01

    We describe an approach to building mirror assemblies for next generation X-ray telescopes. It incorporates knowledge and lessons learned from building existing telescopes, including Chandra, XMM-Newton, Suzaku, and NuSTAR, as well as from our direct experience of the last 15 years developing mirror technology for the Constellation-X and International X-ray Observatory mission concepts. This approach combines single crystal silicon and precision polishing, thus has the potential of achieving the highest possible angular resolution with the least possible mass. Moreover, it is simple, consisting of several technical elements that can be developed independently in parallel. Lastly, it is highly amenable to mass production, therefore enabling the making of telescopes of very large photon collecting areas.

  19. Study of the signal formation in single-type column 3D silicon detectors

    International Nuclear Information System (INIS)

    Piemonte, Claudio; Boscardin, Maurizio; Bosisio, Luciano; Dalla Betta, Gian-Franco; Pozza, Alberto; Ronchin, Sabina; Zorzi, Nicola

    2007-01-01

    Because of their superior radiation resistance, three-dimensional (3D) silicon sensors are receiving more and more interest for application in the innermost layers of tracker systems for experiments running in very high luminosity colliders. Their short electrode distance allows for both a low depletion voltage and a high charge collection efficiency even at extremely high radiation fluences. In order to fully understand the properties of a 3D detector, a thorough characterization of the signal formation mechanism is of paramount importance. In this work the shape of the current induced by localized and uniform charge depositions in a single-type column 3D detector is studied. A first row estimation is given applying the Ramo theorem, then a more complete TCAD simulation is used to provide a more realistic pulse shape

  20. Hall mobility reduction in single-crystalline silicon gradually compensated by thermal donors activation

    Science.gov (United States)

    Veirman, J.; Dubois, S.; Enjalbert, N.; Garandet, J. P.; Heslinga, D. R.; Lemiti, M.

    2010-06-01

    This letter focuses on the variation of the Hall majority carrier mobility with the dopant compensation level in purely Boron-doped Czochralski grown silicon single crystals. Compensation was varied continuously at the sample scale via a step by step activation of the oxygen-based thermal donors. At room temperature, we show a strong drop in mobility for high compensation levels in both p- and n-type Si. Mobility models taking into account carrier scattering on ionized impurities and phonons could not reproduce this drop. We conclude that a specific effect of compensation must be taken into account to explain the observed behaviour. We qualitatively discuss physical mechanisms susceptible to reduce mobility in highly compensated Si.

  1. Electronic properties of dislocations introduced mechanically at room temperature on a single crystal silicon surface

    International Nuclear Information System (INIS)

    Ogawa, Masatoshi; Kamiya, Shoji; Izumi, Hayato; Tokuda, Yutaka

    2012-01-01

    This paper focuses on the effects of temperature and environment on the electronic properties of dislocations in n-type single crystal silicon near the surface. Deep level transient spectroscopy (DLTS) analyses were carried out with Schottky electrodes and p + -n junctions. The trap level, originally found at E C -0.50 eV (as commonly reported), shifted to a shallower level at E C -0.23 eV after a heat treatment at 350 K in an inert environment. The same heat treatment in lab air, however, did not cause any shift. The trap level shifted by the heat treatment in an inert environment was found to revert back to the original level when the specimens were exposed to lab air again. Therefore, the intrinsic trap level is expected to occur at E C -0.23 eV and shift sensitively with gas adsorption in air.

  2. Hybrid Integrated Platforms for Silicon Photonics

    Science.gov (United States)

    Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

    2010-01-01

    A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  3. Single-Event Effect Testing of the Cree C4D40120D Commercial 1200V Silicon Carbide Schottky Diode

    Science.gov (United States)

    Lauenstein, J.-M.; Casey, M. C.; Wilcox, E. P.; Kim, Hak; Topper, A. D.

    2014-01-01

    This study was undertaken to determine the single event effect (SEE) susceptibility of the commercial silicon carbide 1200V Schottky diode manufactured by Cree, Inc. Heavy-ion testing was conducted at the Texas A&M University Cyclotron Single Event Effects Test Facility (TAMU). Its purpose was to evaluate this device as a candidate for use in the Solar-Electric Propulsion flight project.

  4. Surface Passivation for Silicon Heterojunction Solar Cells

    NARCIS (Netherlands)

    Deligiannis, D.

    2017-01-01

    Silicon heterojunction solar cells (SHJ) are currently one of the most promising solar cell technologies in the world. The SHJ solar cell is based on a crystalline silicon (c-Si) wafer, passivated on both sides with a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer. Subsequently, p-type

  5. Quality evaluation of resistivity-controlled silicon crystals

    Science.gov (United States)

    Wang, Jong Hoe

    2006-01-01

    The segregation phenomenon of dopants causes a low production yield of silicon crystal that meets the resistivity tolerance required by device manufacturers. In order to control the macroscopic axial resistivity distribution in bulk crystal growth, numerous studies including continuous Czochralski method and double crucible technique have been studied. The simple B-P codoping method for improving the productivity of p-type silicon single-crystal growth by controlling axial specific resistivity distribution was proposed by Wang [Jpn. J. Appl. Phys. 43 (2004) 4079]. In this work, the quality of Czochralski-grown silicon single crystals with a diameter 200 mm using B-P codoping method was studied from the chemical and structural points of view. It was found that the characteristics of B-P codoped wafers including the oxygen precipitation behavior and the grown-in defects are same as that of conventional B-doped Czochralski crystals.

  6. Hybrid III-V/silicon lasers

    Science.gov (United States)

    Kaspar, P.; Jany, C.; Le Liepvre, A.; Accard, A.; Lamponi, M.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Shen, A.; Charbonnier, P.; Mallecot, F.; Duan, G.-H.; Gentner, J.-.; Fedeli, J.-M.; Olivier, S.; Descos, A.; Ben Bakir, B.; Messaoudene, S.; Bordel, D.; Malhouitre, S.; Kopp, C.; Menezo, S.

    2014-05-01

    The lack of potent integrated light emitters is one of the bottlenecks that have so far hindered the silicon photonics platform from revolutionizing the communication market. Photonic circuits with integrated light sources have the potential to address a wide range of applications from short-distance data communication to long-haul optical transmission. Notably, the integration of lasers would allow saving large assembly costs and reduce the footprint of optoelectronic products by combining photonic and microelectronic functionalities on a single chip. Since silicon and germanium-based sources are still in their infancy, hybrid approaches using III-V semiconductor materials are currently pursued by several research laboratories in academia as well as in industry. In this paper we review recent developments of hybrid III-V/silicon lasers and discuss the advantages and drawbacks of several integration schemes. The integration approach followed in our laboratory makes use of wafer-bonded III-V material on structured silicon-on-insulator substrates and is based on adiabatic mode transfers between silicon and III-V waveguides. We will highlight some of the most interesting results from devices such as wavelength-tunable lasers and AWG lasers. The good performance demonstrates that an efficient mode transfer can be achieved between III-V and silicon waveguides and encourages further research efforts in this direction.

  7. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  8. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  9. Electron Spin Resonance Experiments on a Single Electron in Silicon Implanted with Phosphorous

    Science.gov (United States)

    Luhman, Dwight R.; Nguyen, K.; Tracy, L. A.; Carr, S.; Borchardt, J.; Bishop, N.; Ten Eyck, G.; Pluym, T.; Wendt, J.; Lilly, M. P.; Carroll, M. S.

    2015-03-01

    In this talk we will discuss the results of our ongoing experiments involving electron spin resonance (ESR) on a single electron in a natural silicon sample. The sample consists of an SET, defined by lithographic polysilicon gates, coupled to nearby phosphorous donors. The SET is used to detect charge transitions and readout the spin of the electron being investigated with ESR. The measurements were done with the sample at dilution refrigerator temperatures in the presence of a 1.3 T magnetic field. We will present data demonstrating Rabi oscillations of a single electron in this system as well as measurements of the coherence time, T2. We will also discuss our results using these and various other pulsing schemes in the context of a donor-SET system. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  10. Quantifying the Traction Force of a Single Cell by Aligned Silicon Nanowire Array

    KAUST Repository

    Li, Zhou

    2009-10-14

    The physical behaviors of stationary cells, such as the morphology, motility, adhesion, anchorage, invasion and metastasis, are likely to be important for governing their biological characteristics. A change in the physical properties of mammalian cells could be an indication of disease. In this paper, we present a silicon-nanowire-array based technique for quantifying the mechanical behavior of single cells representing three distinct groups: normal mammalian cells, benign cells (L929), and malignant cells (HeLa). By culturing the cells on top of NW arrays, the maximum traction forces of two different tumor cells (HeLa, L929) have been measured by quantitatively analyzing the bending of the nanowires. The cancer cell exhibits a larger traction force than the normal cell by ∼20% for a HeLa cell and ∼50% for a L929 cell. The traction forces have been measured for the L929 cells and mechanocytes as a function of culture time. The relationship between cells extending area and their traction force has been investigated. Our study is likely important for studying the mechanical properties of single cells and their migration characteristics, possibly providing a new cellular level diagnostic technique. © 2009 American Chemical Society.

  11. Nanoampere charge pump by single-electron ratchet using silicon nanowire metal-oxide-semiconductor field-effect transistor

    Science.gov (United States)

    Fujiwara, Akira; Nishiguchi, Katsuhiko; Ono, Yukinori

    2008-01-01

    Nanoampere single-electron pumping is presented at 20K using a single-electron ratchet comprising silicon nanowire metal-oxide-semiconductor field-effect transistors. The ratchet features an asymmetric potential with a pocket that captures single electrons from the source and ejects them to the drain. Directional single-electron transfer is achieved by applying one ac signal with the frequency up to 2.3GHz. We find anomalous shapes of current steps which can be ascribed to nonadiabatic electron capture.

  12. A Theoretical Study of a Novel Single-Electron Refrigerator Fabricated from Semiconductor Materials

    OpenAIRE

    Ikeda, Hiroya; Salleh, Faiz

    2011-01-01

    We propose a novel single-electron refrigerator (SER) that can be fabricated from semiconductor materials such as a silicon-on-insulator wafer. The SER consists of a single-electron box and a single-electron pump (SEP). An equivalent circuit of the SEP refrigerator was derived. Its stability diagram (Coulomb diamond) was theoretically calculated and found to have a distorted honeycomb structure. In addition, a Monte Carlo simulation based on the orthodox theory for the Coulomb blockade phenom...

  13. Silicon-Film(TM) Solar Cells by a Flexible Manufacturing System: Final Report, 16 April 1998 -- 31 March 2001

    Energy Technology Data Exchange (ETDEWEB)

    Rand, J.

    2002-02-01

    This report describes the overall goal to engineer and develop flexible manufacturing methods and equipment to process Silicon-Film solar cells and modules. Three major thrusts of this three-year effort were to: develop a new larger-area (208 mm x 208 mm) Silicon-Film solar cell, the APx-8; construct and operate a new high-throughput wafer-making system; and develop a 15-MW single-thread manufacturing process. Specific technical accomplishments from this period are: Increase solar cell area by 80%, increase the generation capacity of a Silicon-Film wafer-making system by 350%, use a new in-line HF etch system in solar cell production, design and develop an in-line NaOH etch system, eliminate cassettes in solar cell processing, and design a new family of module products.

  14. Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

    International Nuclear Information System (INIS)

    Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki; Park, Jae-Hyoung

    2013-01-01

    We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test. (paper)

  15. Single nanowire electrode electrochemistry of silicon anode by in situ atomic force microscopy: solid electrolyte interphase growth and mechanical properties.

    Science.gov (United States)

    Liu, Xing-Rui; Deng, Xin; Liu, Ran-Ran; Yan, Hui-Juan; Guo, Yu-Guo; Wang, Dong; Wan, Li-Jun

    2014-11-26

    Silicon nanowires (SiNWs) have attracted great attention as promising anode materials for lithium ion batteries (LIBs) on account of their high capacity and improved cyclability compared with bulk silicon. The interface behavior, especially the solid electrolyte interphase (SEI), plays a significant role in the performance and stability of the electrodes. We report herein an in situ single nanowire atomic force microscopy (AFM) method to investigate the interface electrochemistry of silicon nanowire (SiNW) electrode. The morphology and Young's modulus of the individual SiNW anode surface during the SEI growth were quantitatively tracked. Three distinct stages of the SEI formation on the SiNW anode were observed. On the basis of the potential-dependent morphology and Young's modulus evolution of SEI, a mixture-packing structural model was proposed for the SEI film on SiNW anode.

  16. Application of ITO/Al reflectors for increasing the efficiency of single-crystal silicon solar cells

    International Nuclear Information System (INIS)

    Kopach, V. R.; Kirichenko, M. V.; Khrypunov, G. S.; Zaitsev, R. V.

    2010-01-01

    It is shown that an increase in the efficiency and manufacturability of single-junction single-crystal silicon photoelectric converters of solar energy requires the use of a back-surface reflector based on conductive transparent indium-tin oxide (ITO) 0.25-2 μm thick. To increase the efficiency and reduce the sensitivity to the angle of light incidence on the photoreceiving surface of multijunction photoelectric converters with vertical diode cells based on single-crystal silicon, ITO/Al reflectors with an ITO layer >1 μm thick along vertical boundaries of diode cells should be fabricated. The experimental study of multijunction photoelectric converters with ITO/Al reflectors at diode cell boundaries shows the necessity of modernizing the used technology of ITO layers to achieve their theoretically calculated thickness.

  17. First principles investigations of single dopants in diamond and silicon carbide

    Science.gov (United States)

    Hu, Wenhao

    In the most recent two decades, the development of impurity controls with ultra-high precision in semiconductors motivates people to put more and more attentions on the solotronic devices, whose properties depend on one or a few dopants. One of the most promising applications of solotronic device is the qubit in quantum computing. In the procedure of exploring qubit candidates, the most straightforward challenges we need face include that the qubit must be highly isolated and can be initialized/manipulated efficiently with high fidelities. It has been proved that qubits based on single defects have excellent performances as quits. For instance, the NV center in diamond forms a ground spin triplet which can be manipulated at room temperature with electromagnetic fields. This work focuses on searching for new single defects as qubit candidates with density functional theory. Lanthanides element possesses excellent optical characteristics and extremely long nuclear coherence time. Therefore, combining it into the diamond platform can be possible design for integrated quantum information processing devices in the future. To investigate the stability of lanthanides dopants in the diamond matrix, the formation energies of charge states of complexes are calculated. The broadening of Eu(III) peak in the photoluminescence spectrum can be verified according to the existence of more than stable configuration and steady 4f electron occupation. In the case of transition-metal dopant in the silicon carbide, it is found that both silicon and carbon substituted nickels in 3C-SiC shows a magnetic-antimagnetic transition under applied strains. The virtual hopping rate of electrons strongly depends on the distance between the spin pair residing in the nickel and dangling bonds. Therefore, the Heisenberg exchange coupling between them can be adjusted subtly by controlling the external strain. According to the spin Hamiltonian of the defect, the spin state can be manipulated

  18. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  19. Porous silicon technology for integrated microsystems

    Science.gov (United States)

    Wallner, Jin Zheng

    With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially

  20. Fabrication of thick silicon nitride blocks embedded in low-resistivity silicon substrates for radio frequency applications

    NARCIS (Netherlands)

    Fernandez, L.J.; Berenschot, Johan W.; Wiegerink, Remco J.; Flokstra, Jakob; Flokstra, Jan; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2006-01-01

    Thick silicon nitride blocks embedded in silicon wafers were recently proposed as a substrate for RF devices. In this paper we show that deep trenches filled with silicon nitride—having thin slices of monocrystalline silicon in between—already result in a significantly improved RF behavior.

  1. Single-crystal-silicon-based microinstrument to study friction and wear at MEMS sidewall interfaces

    International Nuclear Information System (INIS)

    Ansari, N; Ashurst, W R

    2012-01-01

    Since the advent of microelectromechanical systems (MEMS) technology, friction and wear are considered as key factors that determine the lifetime and reliability of MEMS devices that contain contacting interfaces. However, to date, our knowledge of the mechanisms that govern friction and wear in MEMS is insufficient. Therefore, systematically investigating friction and wear at MEMS scale is critical for the commercial success of many potential MEMS devices. Specifically, since many emerging MEMS devices contain more sidewall interfaces, which are topographically and chemically different from in-plane interfaces, studying the friction and wear characteristics of MEMS sidewall surfaces is important. The microinstruments that have been used to date to investigate the friction and wear characteristics of MEMS sidewall surfaces possess several limitations induced either by their design or the structural film used to fabricate them. Therefore, in this paper, we report on a single-crystal-silicon-based microinstrument to study the frictional and wear behavior of MEMS sidewalls, which not only addresses some of the limitations of other microinstruments but is also easy to fabricate. The design, modeling and fabrication of the microinstrument are described in this paper. Additionally, the coefficients of static and dynamic friction of octadecyltrichlorosilane-coated sidewall surfaces as well as sidewall surfaces with only native oxide on them are also reported in this paper. (paper)

  2. A silicon-based single-electron interferometer coupled to a fermionic sea

    Science.gov (United States)

    Chatterjee, Anasua; Shevchenko, Sergey N.; Barraud, Sylvain; Otxoa, Rubén M.; Nori, Franco; Morton, John J. L.; Gonzalez-Zalba, M. Fernando

    2018-01-01

    We study Landau-Zener-Stückelberg-Majorana (LZSM) interferometry under the influence of projective readout using a charge qubit tunnel-coupled to a fermionic sea. This allows us to characterize the coherent charge-qubit dynamics in the strong-driving regime. The device is realized within a silicon complementary metal-oxide-semiconductor (CMOS) transistor. We first read out the charge state of the system in a continuous nondemolition manner by measuring the dispersive response of a high-frequency electrical resonator coupled to the quantum system via the gate. By performing multiple fast passages around the qubit avoided crossing, we observe a multipassage LZSM interferometry pattern. At larger driving amplitudes, a projective measurement to an even-parity charge state is realized, showing a strong enhancement of the dispersive readout signal. At even larger driving amplitudes, two projective measurements are realized within the coherent evolution resulting in the disappearance of the interference pattern. Our results demonstrate a way to increase the state readout signal of coherent quantum systems and replicate single-electron analogs of optical interferometry within a CMOS transistor.

  3. Direct exchange between silicon nanocrystals and tunnel oxide traps under illumination on single electron photodetector

    Energy Technology Data Exchange (ETDEWEB)

    Chatbouri, S., E-mail: Samir.chatbouri@yahoo.com; Troudi, M.; Sghaier, N.; Kalboussi, A. [Avenue de I’environnement, Université de Monastir, Laboratoire de Micro électronique et Instrumentation (LR13ES12), Faculté des Sciences de Monastir (Tunisia); Aimez, V. [Université de Sherbrooke, Laboratoire Nanotechnologies et Nanosystémes (UMI-LN2 3463), Université de Sherbrooke—CNRS—INSA de Lyon-ECL-UJF-CPE Lyon, Institut Interdisciplinaire d’Innovation Technologique (Canada); Drouin, D. [Avenue de I’environnement, Université de Monastir, Laboratoire de Micro électronique et Instrumentation (LR13ES12), Faculté des Sciences de Monastir (Tunisia); Souifi, A. [Institut des Nanotechnologies de Lyon—site INSA de Lyon, UMR CNRS 5270 (France)

    2016-09-15

    In this paper we present the trapping of photogenerated charge carriers for 300 s resulted by their direct exchange under illumination between a few silicon nanocrystals (ncs-Si) embedded in an oxide tunnel layer (SiO{sub x} = 1.5) and the tunnel oxide traps levels for a single electron photodetector (photo-SET or nanopixel). At first place, the presence of a photocurrent limited in the inversion zone under illumination in the I–V curves confirms the creation of a pair electron/hole (e–h) at high energy. This photogenerated charge carriers can be trapped in the oxide. Using the capacitance-voltage under illumination (the photo-CV measurements) we show a hysteresis chargement limited in the inversion area, indicating that the photo-generated charge carriers are stored at traps levels at the interface and within ncs-Si. The direct exchange of the photogenerated charge carriers between the interface traps levels and the ncs-Si contributed on the photomemory effect for 300 s for our nanopixel at room temperature.

  4. Silicon spectral response extension through single wall carbon nanotubes in hybrid solar cells

    KAUST Repository

    Del Gobbo, Silvano

    2013-01-01

    Photovoltaic devices based on single wall carbon nanotubes (SWCNTs) and n-silicon multiple heterojunctions have been fabricated by a SWCNT film transferring process. We report on the ability of the carbon nanotubes to extend the Si spectral range towards the near ultraviolet (UV) and the near infrared regions. Semiconducting and about metallic SWCNT networks have been studied as a function of the film sheet resistance, Rsh. Optical absorbance and Raman spectroscopy have been used to assign nanotube chirality and electronic character. This gave us hints of evidence of the participation of the metal nanotubes in the photocurrent generation. Moreover, we provide evidence that the external quantum efficiency spectral range can be modulated as a function of the SWCNT network sheet resistance in a hybrid SWCNT/Si solar cell. This result will be very useful to further design/optimize devices with improved performance in spectral regions generally not covered by conventional Si p-n devices. © 2013 The Royal Society of Chemistry.

  5. Silicon/Porous Silicon Composite Membrane for High Sensitivity Pressure Sensor

    Science.gov (United States)

    2009-07-21

    for integrating with other processes on silicon wafer. The fabrication of silicone rubber membranes for making microvalves has been reported [5...alcohol (IPA) is used along with HF to increase the wettability of the silicon surface and to remove the bubbles formed during the reaction. Aluminium ...Report for AOARD funded Project No. AOARD-074061 Title: Silicon /Porous Silicon composite membrane for high sensitivity pressure sensor PI

  6. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  7. Muon decay channeling in silicon

    International Nuclear Information System (INIS)

    Bosshard, A.; Patterson, B.D.; Straumann, U.; Truoel, P.; Wichert, Th.

    1984-01-01

    This experiment employs the channeling effect of the host lattice on the trajectories of decay positrons in order to determine the position of positive muons implanted into silicon crystals. Low-momentum ( 0 ). In order to achieve sufficient angular resolution, the Si wafer is bent to a spherical shape, thereby focussing a particular crystal axis to a point at the center of the MWPC (located 3.4 m from the wafer). (Auth.)

  8. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    Science.gov (United States)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  9. Numerical and experimental study of a solid pellet feed continuous Czochralski growth process for silicon single crystals

    Science.gov (United States)

    Anselmo, A.; Prasad, V.; Koziol, J.; Gupta, K. P.

    1993-07-01

    A polysilicon pellets (≅1 mm diameter) feed continuous Czochralski (CCZ) growth process for silicon single crystals is proposed and investigated. Experiments in an industrial puller (14-18 inch diameter crucible) successfully demonstrate the feasibility of this process. The advantages of the proposed scheme are: a steady state growth process, a low aspect ratio melt, uniformity of heat addition and a growth apparatus with single crucible and no baffle(s). The addition of dopant with the solid charge will allow a better control of oxygen concentration leading to crystals of uniform properties and better quality. This paper presents theoretical results on melting of fully and partially immersed silicon spheres and numerical solutions on temperature and flow fields in low aspect ration melts with and without the addition of solid pellets. The theoretical and experimental results obtained thus far show a great promise for the proposed scheme.

  10. Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

    International Nuclear Information System (INIS)

    Dixit, Pradeep; Vehmas, Tapani; Vähänen, Sami; Monnoyer, Philippe; Henttinen, Kimmo

    2012-01-01

    This paper presents the fabrication and the electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 µm thin silicon device wafer, bonded to a handle wafer by plasma activated oxide-to-silicon bonding. Heavily doped poly-Si was used as interconnection material, which was deposited by low-pressure chemical vapor deposition. Two different via geometries, i.e. stadium shaped, and circular shaped, were tried. Sputtered aluminum metallization layers as double-side redistribution lines and contact pads, were used. Both Kelvin structures and daisy chains were fabricated and their electrical resistances were measured. The electrical resistance of a single stadium-shaped via was measured to be about 24 Ω. The electrical resistance was varying from 60 Ω to 90 Ω for two-vias daisy chains. Measured results indicate that this via-first technology can be used for varying range of sensor applications like microphone, oscillator, resonator, etc where CMOS compatibility and high temperature processing are the prime requirements. (paper)

  11. Characteristics of thermally induced acoustic emission from nanoporous silicon device under full digital operation

    Science.gov (United States)

    Koshida, Nobuyoshi; Hippo, Daihei; Mori, Masamitsu; Yanazawa, Hiroshi; Shinoda, Hiroyuki; Shimada, Toshikazu

    2013-03-01

    The resonance-free frequency response of the thermo-acoustic emission is demonstrated under a full digital drive. The device is composed of a thin-film heater electrode, a nano-porous silicon layer, and a single-crystalline silicon wafer. When sequential electrical pulse trains converted by the density modulation of an analog signal are introduced into the heater electrode, a significant sound pressure is reproduced with a sufficiently low distortion. The characteristic output behaviour in the audible ultrasonic band is clarified in either open- or closed-space. The advantageous features of thermally induced sound emission and its underlying physics have been made clear.

  12. Optical and passivating properties of hydrogenated amorphous silicon nitride deposited by plasma enhanced chemical vapour deposition for application on silicon solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Wight, Daniel Nilsen

    2008-07-01

    Within this thesis, several important subjects related to the use of amorphous silicon nitride made by plasma enhanced chemical vapour deposition as an anti-reflective coating on silicon solar cells are presented. The first part of the thesis covers optical simulations to optimise single and double layer anti-reflective coatings with respect to optical performance when situated on a silicon solar cell. The second part investigates the relationship between important physical properties of silicon nitride films when deposited under different conditions. The optical simulations were either based on minimising the reflectance off a silicon nitride/silicon wafer stack or maximising the transmittance through the silicon nitride into the silicon wafer. The former method allowed consideration of the reflectance off the back surface of the wafer, which occurs typically at wavelengths above 1000 nm due to the transparency of silicon at these wavelengths. However, this method does not take into consideration the absorption occurring in the silicon nitride, which is negligible at low refractive indexes but quite significant when the refractive index increases above 2.1. For high-index silicon nitride films, the latter method is more accurate as it considers both reflectance and absorbance in the film to calculate the transmittance into the Si wafer. Both methods reach similar values for film thickness and refractive index for optimised single layer anti-reflective coatings, due to the negligible absorption occurring in these films. For double layer coatings, though, the reflectance based simulations overestimated the optimum refractive index for the bottom layer, which would have lead to excessive absorption if applied to real anti-reflective coatings. The experimental study on physical properties for silicon nitride films deposited under varying conditions concentrated on the estimation of properties important for its applications, such as optical properties, passivation

  13. Wafer-Scale Leaning Silver Nanopillars for Molecular Detection at Ultra-Low Concentrations

    DEFF Research Database (Denmark)

    Wu, Kaiyu; Rindzevicius, Tomas; Schmidt, Michael Stenbæk

    2015-01-01

    Wafer-scale surface-enhanced Raman scattering (SERS) substrates fabricated using maskless lithography are important for scalable production targets. Large-area, leaning silver-capped silicon nanopillar (Ag NP) structures suitable for SERS molecular detection at extremely low analyte concentrations...

  14. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  15. Single-silicon CCD-CMOS platform for multi-spectral detection from terahertz to x-rays.

    Science.gov (United States)

    Shalaby, Mostafa; Vicario, Carlo; Hauri, Christoph P

    2017-11-15

    Charge-coupled devices (CCDs) are a well-established imaging technology in the visible and x-ray frequency ranges. However, the small quantum photon energies of terahertz radiation have hindered the use of this mature semiconductor technological platform in this frequency range, leaving terahertz imaging totally dependent on low-resolution bolometer technologies. Recently, it has been shown that silicon CCDs can detect terahertz photons at a high field, but the detection sensitivity is limited. Here we show that silicon, complementary metal-oxide-semiconductor (CMOS) technology offers enhanced detection sensitivity of almost two orders of magnitude, compared to CCDs. Our findings allow us to extend the low-frequency terahertz cutoff to less than 2 THz, nearly closing the technological gap with electronic imagers operating up to 1 THz. Furthermore, with the silicon CCD/CMOS technology being sensitive to mid-infrared (mid-IR) and the x-ray ranges, we introduce silicon as a single detector platform from 1 EHz to 2 THz. This overcomes the present challenge in spatially overlapping a terahertz/mid-IR pump and x-ray probe radiation at facilities such as free electron lasers, synchrotron, and laser-based x-ray sources.

  16. Adhesion of single- and multi-walled carbon nanotubes to silicon substrate: atomistic simulations and continuum analysis

    Science.gov (United States)

    Yuan, Xuebo; Wang, Youshan

    2017-10-01

    The radial deformation of carbon nanotubes (CNTs) adhering to a substrate may prominently affect their mechanical and physical properties. In this study, both classical atomistic simulations and continuum analysis are carried out, to investigate the lateral adhesion of single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) to a silicon substrate. A linear elastic model for analyzing the adhesion of 2D shells to a rigid semi-infinite substrate is constructed in the framework of continuum mechanics. Good agreement is achieved between the cross-section profiles of adhesive CNTs obtained by the continuum model and by the atomistic simulation approach. It is found that the adhesion of a CNT to the silicon substrate is significantly influenced by its initial diameter and the number of walls. CNTs with radius larger than a certain critical radius are deformed radially on the silicon substrate with flat contact regions. With increasing number of walls, the extent of radial deformation of a MWCNT on the substrate decreases dramatically, and the flat contact area reduces—and eventually vanishes—due to increasing equivalent bending stiffness. It is analytically predicted that large-diameter MWCNTs with a large number of walls are likely to ‘stand’ on the silicon substrate. The present work can be useful for understanding the radial deformation of CNTs adhering to a solid planar substrate.

  17. A silicon-based electrochemical sensor for highly sensitive, specific, label-free and real-time DNA detection

    International Nuclear Information System (INIS)

    Guo, Yuanyuan; Su, Shao; Wei, Xinpan; Zhong, Yiling; Su, Yuanyuan; He, Yao; Huang, Qing; Fan, Chunhai

    2013-01-01

    We herein present a new kind of silicon-based electrochemical sensor using a gold nanoparticles-decorated silicon wafer (AuNPs@Si) as a high-performance electrode, which is facilely prepared via in situ AuNPs growth on a silicon wafer. Particularly significantly, the resultant electrochemical sensor is efficacious for label-free DNA detection with high sensitivity due to the unique merits of the prepared silicon-based electrode. Typically, DNA at remarkably low concentrations (1–10 fM) could be readily detected without requiring additional signal-amplification procedures, which is better than or comparable to the lowest DNA concentration ever detected via well-studied signal-amplification-assisted electrochemical sensors. Moreover, the silicon-based sensor features high specificity, allowing unambiguous discrimination of single-based mismatches. We further show that real-time DNA assembly is readily monitored via recording the intensity changes of current signals due to the robust thermal stability of the silicon-based electrode. The unprecedented advantages of the silicon-based electrochemical sensor would offer new opportunities for myriad sensing applications. (paper)

  18. Time-correlated single-photon counting study of multiple photoluminescence lifetime components of silicon nanoclusters

    Energy Technology Data Exchange (ETDEWEB)

    Diamare, D., E-mail: d.diamare@ee.ucl.ac.uk [Department of Electronic and Electrical Engineering, University College London, Torrington Place, London, WC1E 7JE (United Kingdom); Wojdak, M. [Department of Electronic and Electrical Engineering, University College London, Torrington Place, London, WC1E 7JE (United Kingdom); Lettieri, S. [Institute for Superconductors and Innovative Materials, National Council of Research (CNR-SPIN), Via Cintia 80126, Naples (Italy); Department of Physical Sciences, University of Naples “Federico II”, Via Cintia 80126, Naples (Italy); Kenyon, A.J. [Department of Electronic and Electrical Engineering, University College London, Torrington Place, London, WC1E 7JE (United Kingdom)

    2013-04-15

    We report time-resolved photoluminescence measurements of thin films of silica containing silicon nanoclusters (Si NCs), produced by PECVD and annealed at temperatures between 700 °C and 1150 °C. While the near infrared emission of Si NCs has long been studied, visible light emission has only recently attracted interest due to its very short decay times and its recently-reported redshift with decreasing NCs size. We analyse the PL decay dynamics in the range 450–700 nm with picosecond time resolution using Time Correlated Single Photon Counting. In the resultant multi-exponential decays two dominant components can clearly be distinguished: a very short component, in the range of hundreds of picoseconds, and a nanosecond component. In this wavelength range we do not detect the microsecond component generally associated with excitonic recombination. We associate the nanosecond component to defect relaxation: it decreases in intensity in the sample annealed at higher temperature, suggesting that the contribution from defects decreases with increasing temperature. The origin of the very fast PL component (ps time region) is also discussed. We show that it is consistent with the Auger recombination times of multiple excitons. Further work needs to be done in order to assess the contribution of the Auger-controlled recombinations to the defect-assisted mechanism of photoluminescence. -- Highlights: ► We report time-resolved PL measurements of Si-Ncs embedded in SiO{sub 2} matrix. ► Net decrease of PL with increasing the annealing temperature has been observed. ► Lifetime distribution analysis revealed a multiexponential decay with ns and ps components. ► Ps components are consistent with the lifetime range of the Auger recombination times. ► No evidence for a fast direct transition at the Brillouin zone centre.

  19. New plant designs for aqueous etching and electroforming of wafers; Neues modulares Anlagenkonzept fuer nasschemische Aetzprozesse und die Wafergalvanoformung

    Energy Technology Data Exchange (ETDEWEB)

    Guttmann, Markus; Kaiser, Konradin; Muth, Stephanie [Karlsruher Institut fuer Technologie, Karlsruhe (Germany). Inst. fuer Mikrostrukturtechnik; Moritz, Hans [silicet AG, Lohfelden (Germany); Schmidt, Ralf; Zwanzig, Michael [Fraunhofer-Institut fuer Zuverlaessigkeit und Mikrointegration (IZM), Berlin (Germany); Hofmann, Lutz [TU Chemnitz (Germany). Zentrum fuer Mikrotechnologien; Schubert, Ina [Fraunhofer-Einrichtung fuer Elektronische Nanosysteme (ENAS), Chemnitz (Germany)

    2009-07-01

    In order to carry out a study of wafer patterning, equipment was developed for safe handling of silicon wafers from 2 to 8 inch diameters. The unit can be safely and relatively straightforwardly operated by personnel, using a wide range of etchants and electrochemical deposition processes. The design also allows the effects of electrolyte flowrate in the process chamber confronting the silicon wafer, to be assessed. These features were utilised to study copper and nickel electrodeposition to pattern the wafer surface. (orig.) [German] Zur Untersuchung der Strukturierung von Wafern wurde eine Prozesseinheit zur bruchsicheren Aufnahme von Siliziumwafern mit Durchmessern zwischen zwei und acht Zoll entwickelt. Die Einheit kann relativ einfach und mit hoher Sicherheit fuer die handhabenden Personen mit den unterschiedlichsten Medien zum Aetzen oder galvanotechnischen Aufbau betrieben werden. Die Anordnung ermoeglicht zudem die gezielte Beeinflussung der Stroemung im Prozessraum vor der Waferoberflaeche. Die Moeglichkeiten zur Untersuchung werden an der Nickel- und Kupferabscheidung zur Herstellung von Strukturen aufgezeigt. (orig.)

  20. Friction and Wear of Metals With a Single-Crystal Abrasive Grit of Silicon Carbide - Effect of Shear Strength of Metal

    National Research Council Canada - National Science Library

    Miyoshi, Kazuhisa

    1978-01-01

    An investigation was conducted to examine the removal and plastic deformation of metal as a function of the metal properties when the metal is in sliding contact with a single-crystal abrasive grit of silicon carbide...

  1. Investigation of optical properties of benzocyclobutene wafer bonding layer used for 3D interconnects via infrared spectroscopic ellipsometry

    International Nuclear Information System (INIS)

    Kamineni, Vimal K.; Singh, Pratibha; Kong, LayWai; Hudnall, John; Qureshi, Jamal; Taylor, Chris; Rudack, Andy; Arkalgud, Sitaram; Diebold, Alain C.

    2011-01-01

    Benzocyclobutene (BCB) used for bonding silicon wafers to enable 3D interconnect technology is characterized using spectroscopic ellipsometry (SE). SE is a non-destructive technique that has been used to characterize the thickness and dielectric properties of BCB. The infrared (IR) absorption spectrum was used to calculate the percentage of curing of BCB on 300 mm bare and bonded wafers. The percentage of curing in BCB is a key parameter that impacts the bond strength and bond quality. This study presents the potential application of IRSE for measurements on bonded wafers to characterize the chemical information, curing percentage, bond quality and thickness of the BCB bonding layer. One of the key issues in the process development and characterization of BCB bonding for 3D interconnects of 300 mm wafers is the presence of dendrites and voids between the bonded wafers. The presence of dendrites and voids was identified by using scanning acoustic microscopy (SAM) and imaged by scanning electron microscope (SEM).

  2. Investigation of optical properties of benzocyclobutene wafer bonding layer used for 3D interconnects via infrared spectroscopic ellipsometry

    Energy Technology Data Exchange (ETDEWEB)

    Kamineni, Vimal K., E-mail: vkamineni@uamail.albany.ed [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States); Singh, Pratibha [GLOBALFOUNDRIES Inc., Albany, NY 12203 (United States); SEMATECH, Albany, NY 12203 (United States); Kong, LayWai [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States); Hudnall, John [SEMATECH, Albany, NY 12203 (United States); Qureshi, Jamal [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States); SEMATECH, Albany, NY 12203 (United States); Taylor, Chris [SEMATECH, Albany, NY 12203 (United States); Hewlett-Packard Company, Corvallis, OR (United States); Rudack, Andy; Arkalgud, Sitaram [SEMATECH, Albany, NY 12203 (United States); Diebold, Alain C. [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States)

    2011-02-28

    Benzocyclobutene (BCB) used for bonding silicon wafers to enable 3D interconnect technology is characterized using spectroscopic ellipsometry (SE). SE is a non-destructive technique that has been used to characterize the thickness and dielectric properties of BCB. The infrared (IR) absorption spectrum was used to calculate the percentage of curing of BCB on 300 mm bare and bonded wafers. The percentage of curing in BCB is a key parameter that impacts the bond strength and bond quality. This study presents the potential application of IRSE for measurements on bonded wafers to characterize the chemical information, curing percentage, bond quality and thickness of the BCB bonding layer. One of the key issues in the process development and characterization of BCB bonding for 3D interconnects of 300 mm wafers is the presence of dendrites and voids between the bonded wafers. The presence of dendrites and voids was identified by using scanning acoustic microscopy (SAM) and imaged by scanning electron microscope (SEM).

  3. Silicon materials task of the low cost solar array project (Phase III). Effect of impurities and processing on silicon solar cells. Fifteenth quarterly report, April-June 1979

    Energy Technology Data Exchange (ETDEWEB)

    Hopkins, R.H.; Davis, J.R.; Blais, P.D.; Rohatgi, A.; Campbell, R.B.; Rai-Choudhury, P.; Stapleton, R.E.; Mollenkopf, H.C.; McCormick, J.R.

    1979-07-01

    The overall objective of this program is to define the effects of impurities, various thermochemical processes, and any impurity-process interactions on the performance of terrestrial silicon solar cells. The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly Solar Grade silicon. The first reported determinations of the segregation coefficients of tungsten, tantalum, and cobalt for the Czochralski pulling of silicon single crystals were performed. Sensitive neutron activation analysis was used to determine the metal impurity content of the silicon (C/sub S/) while atomic absorption was used to measure the metal content of the residual liquid (C/sub L/) from which the doped crystals were grown. Gettering of Ti-doped silicon wafers improves cell performance by 1 to 2% (absolute) for the highest temperatures and longest times. The measured profile for Ti centers formed after an 850/sup 0/C gettering operation was fitted by a mathematical expression for the out-diffusion of an impurity species. By means of cell performance data and the newly-measured segregation coefficients curves were computed to predict the variation in cell efficiency with impurity concentration for Mo, Ta, W, Nb, and Co, materials commonly employed in the construction of high temperature silicon processing equipment. Using data for second and third generation n-base ingots the cell performance curves were updated for single impurities in n-type silicon. Most impurities degrade n-base cells less than p-base devices. The effect is larges for Mo, Al, Mn, Ti, and V while Fe and Cr behave much the same in both types of solar cells. In contrast Ni and Cu both degrade n-base devices (apparently by a junction mechanism) more severely than p-base cells. (WHK)

  4. Synchrotron Topographic and Diffractometer Studies of Buried Layered Structures Obtained by Implantation with Swift Heavy Ions in Silicon Single Crystals

    International Nuclear Information System (INIS)

    Wierzchowski, W.; Wieteska, K.; Zymierska, D.; Graeff, W.; Czosnyka, T.; Choinski, J.

    2006-01-01

    A distribution of crystallographic defects and deformation in silicon crystals subjected to deep implantation (20-50 μm) with ions of the energy of a few MeV/amu is studied. Three different buried layered structures (single layer, binary buried structure and triple buried structure) were obtained by implantation of silicon single crystals with 184 MeV argon ions, 29.7 MeV boron ions, and 140 MeV argon ions, each implantation at a fluency of 1x10 14 ions cm -2 . The implanted samples were examined by means of white beam X-ray section and projection topography, monochromatic beam topography and by recording local rocking curves with the beam restricted to 50 x 50 μm 2 . The experiment pointed to a very low level of implantation-induced strain (below 10 -5 ). The white beam Bragg case section experiment revealed a layer producing district black contrast located at a depth of the expected mean ion range. The presence of these buried layered structures in studied silicon crystals strongly affected the fringe pattern caused by curvature of the samples. In case of white beam projection and monochromatic beam topographs the implanted areas were revealed as darker regions with a very tiny grain like structure. One may interpret these results as the effect of considerable heating causing annihilation of point defects and formation of dislocation loops connected with point defect clusters. (author)

  5. Porous silicon photonic devices using pulsed anodic etching of lightly doped silicon

    International Nuclear Information System (INIS)

    Escorcia-Garcia, J; Sarracino MartInez, O; Agarwal, V; Gracia-Jimenez, J M

    2009-01-01

    The fabrication of porous silicon photonic structures using lightly doped, p-type, silicon wafers (resistivity: 14-22 Ω cm) by pulsed anodic etching is reported. The optical properties have been found to be strongly dependent on the duty cycle and frequency of the applied current. All the interfaces of the single layered samples were digitally analysed by calculating the mean interface roughness (R m ). The interface roughness was found to be maximum for the sample with direct current. The use of a duty cycle above 50%, in a certain range of frequencies, is found to reduce the interface roughness. The optical properties of some microcavities and rugate filters are investigated from the optimized parameters of the duty cycle and frequency, using the current densities of 10, 90 and 150 mA cm -2 .

  6. Porous silicon photonic devices using pulsed anodic etching of lightly doped silicon

    Energy Technology Data Exchange (ETDEWEB)

    Escorcia-Garcia, J; Sarracino MartInez, O; Agarwal, V [CIICAP-Universidad Autonoma del Estado de Morelos, Av. Universidad 1001, Col Chamilpa, CP 62210, Cuernavaca, Morelos (Mexico); Gracia-Jimenez, J M, E-mail: vagarwal@uaem.m [Instituto de Fisica, BUAP, Apdo. Postal J-48, San Manuel, 72570 Puebla, Puebla (Mexico)

    2009-07-21

    The fabrication of porous silicon photonic structures using lightly doped, p-type, silicon wafers (resistivity: 14-22 OMEGA cm) by pulsed anodic etching is reported. The optical properties have been found to be strongly dependent on the duty cycle and frequency of the applied current. All the interfaces of the single layered samples were digitally analysed by calculating the mean interface roughness (R{sub m}). The interface roughness was found to be maximum for the sample with direct current. The use of a duty cycle above 50%, in a certain range of frequencies, is found to reduce the interface roughness. The optical properties of some microcavities and rugate filters are investigated from the optimized parameters of the duty cycle and frequency, using the current densities of 10, 90 and 150 mA cm{sup -2}.

  7. Internal mechanical stresses and the thermodynamic and adhesion parameters of the metal condensate-single-crystal silicon system

    Science.gov (United States)

    Coman, B. P.; Juzevych, V. N.

    2012-07-01

    The kinetics of generation of internal mechanical stresses σ( d) in chromium, copper, gold, and aluminum thin films on single-crystal silicon substrates at different deposition rates has been experimentally investigated using the cantilever method. A two-step character of the variations in internal tensile stresses has been revealed. The regularities of the formation of the maximum level of mechanical stresses in the condensates under investigation have been established. The energy and adhesion parameters of chromium, copper, gold, and aluminum nanolayers on silicon, germanium, and nickel substrates have been studied using the macroscopic methods of surface physics. The interfacial energy, interfacial tension, work of adhesion, interfacial charge, and a new energy characteristic of the interfacial layer, namely, the energy of adhesive bonds, which exceeds the interfacial energy, have been determined.

  8. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  9. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  10. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  11. Growth and characterization of indium doped silicon single crystals at industrial scale

    Science.gov (United States)

    Haringer, Stephan; Giannattasio, Armando; Alt, Hans Christian; Scala, Roberto

    2016-03-01

    Indium is becoming one of the most important dopant species for silicon crystals used in photovoltaics. In this work we have investigated the behavior of indium in silicon crystals grown by the Czochralski pulling process. The experiments were performed by growing 200 mm crystals, which is a standard diameter for large volume production, thus the data reported here are of technological interest for the large scale production of indium doped p-type silicon. The indium segregation coefficient and the evaporation rate from the silicon melt have been calculated to be 5 × 10-4 ± 3% and 1.6 × 10-4 cm·s-1, respectively. In contrast to previous works the indium was introduced in liquid phase and the efficiency was compared with that deduced by other authors, using different methods. In addition, the percentage of electrically active indium at different dopant concentrations is calculated and compared with the carrier concentration at room temperature, measured by four-point bulk method.

  12. The Fabrication of Arrays of Single Ions in Silicon via Ion Implantation

    Science.gov (United States)

    2014-02-01

    coherence and electron nuclear double resonance of Bi donors in natural Si. Physical Review Letters, 105:067601, 2010. [225] T. Sekiguchi, M. Steger ...Exchange in silicon-based quantum computer architechture. Physical Review Letters, 88(2):027903, 2002. [246] A. Yang, M. Steger , T. Sekiguchi, M. L. W

  13. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  14. Single-particle properties of N = 12 to N = 20 silicon isotopes within the dispersive optical model

    Science.gov (United States)

    Bespalova, O. V.; Ermakova, T. A.; Klimochkina, A. A.; Spasskaya, T. I.

    2017-09-01

    Experimental neutron and proton single-particle energies in N = 12 to N = 20 silicon isotopes and data on neutron and proton scattering by nuclei of the isotope 28Si are analyzed on the basis of the dispersive optical model. Good agreement with available experimental data was attained. The occupation probabilities calculated for the single-particle states in question suggest a parallel-type filling of the 1 d and 2 s 1/2 neutron states in the isotopes 26,28,30,32,34Si. The single-particle spectra being considered are indicative of the closure of the Z = 14 proton subshell in the isotopes 30,32,34Si and the N = 20 neutron shell.

  15. Initial steps toward the realization of large area arrays of single photon counting pixels based on polycrystalline silicon TFTs

    Science.gov (United States)

    Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Jiang, Hao; Street, Robert A.; Lu, Jeng Ping

    2014-03-01

    The thin-film semiconductor processing methods that enabled creation of inexpensive liquid crystal displays based on amorphous silicon transistors for cell phones and televisions, as well as desktop, laptop and mobile computers, also facilitated the development of devices that have become ubiquitous in medical x-ray imaging environments. These devices, called active matrix flat-panel imagers (AMFPIs), measure the integrated signal generated by incident X rays and offer detection areas as large as ~43×43 cm2. In recent years, there has been growing interest in medical x-ray imagers that record information from X ray photons on an individual basis. However, such photon counting devices have generally been based on crystalline silicon, a material not inherently suited to the cost-effective manufacture of monolithic devices of a size comparable to that of AMFPIs. Motivated by these considerations, we have developed an initial set of small area prototype arrays using thin-film processing methods and polycrystalline silicon transistors. These prototypes were developed in the spirit of exploring the possibility of creating large area arrays offering single photon counting capabilities and, to our knowledge, are the first photon counting arrays fabricated using thin film techniques. In this paper, the architecture of the prototype pixels is presented and considerations that influenced the design of the pixel circuits, including amplifier noise, TFT performance variations, and minimum feature size, are discussed.

  16. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  17. Sliver{sup (R)} solar cells: A new thin-crystalline silicon photovoltaic technology

    Energy Technology Data Exchange (ETDEWEB)

    Verlinden, P.J.; Kerr, M.J.; Stuckings, M.F.; Gordeev, D.; Stocks, M.J. [Origin Energy Solar, G.P.O Box 1097, Adelaide, SA 5001 (Australia); Blakers, A.W.; Weber, K.J.; Babaei, J.; Everett, V. [Centre for Sustainable Energy Systems, ANU, Canberra, ACT 0200 (Australia)

    2006-11-23

    A new technique for producing thin single-crystal silicon solar cells has been developed. The new technology allows for large decreases in silicon usage by a factor of 12 (including kerf losses) compared to conventional crystalline silicon wafer technologies. The new Sliver{sup (R)} cell process uses a micromachining technique to form 60{mu}m-thick solar cells, fully processed while they are still supported by the silicon substrate at the edge of the wafer. The Sliver{sup (R)} solar cells are capable of excellent performance due to their thickness and unique cell design with demonstrated efficiencies over 19.3% and open-circuit voltages of 683mV. In addition, the cells are bifacial (accepts light from either sides) and very flexible. Several prototype modules have been fabricated using a new design approach that introduces a diffuse reflector to the rear of a bi-glass module. To save expensive silicon material, a significant gap is kept between cells. The light striking between cells is scattered from the rear reflector and is directed onto the rear surface of the bifacial Sliver{sup (R)} cells. Module efficiency of 13% (AM1.5, 25C) has been demonstrated with a module presenting a 50% solar-cell coverage fraction, and 18.3% with a 100% Sliver{sup (R)} cell coverage fraction. (author)

  18. Channeling and Radiation of Electrons in Silicon Single Crystals and Si1−xGex Crystalline Undulators

    DEFF Research Database (Denmark)

    Backe, H.; Krambrich, D.; Lauth, W.

    2013-01-01

    The phenomenon of channeling and the basic features of channeling radiation emission are introduced in a pedestrian way. Both, radiation spectra as well as dechanneling length measurements at electron beam energies between 195 and 855 MeV feature quantum state phenomena for the (110) planar...... potential of the silicon single crystals. Radiation from a crystalline undulator, produced at the Aarhus University (UAAR), has been investigated at the Mainz Microtron electron accelerator facility MAMI. The 4-period epitaxially grown strained layer Si1−xGex undulator had a period length λu = 9.9 μm...

  19. Comparative analysis on surface property in anodic oxidation polishing of reaction-sintered silicon carbide and single-crystal 4H silicon carbide

    Science.gov (United States)

    Shen, Xinmin; Tu, Qunzhang; Deng, Hui; Jiang, Guoliang; He, Xiaohui; Liu, Bin; Yamamura, Kazuya

    2016-04-01

    For effective machining of difficult-to-machine materials, such as reaction-sintered silicon carbide (RS-SiC) and single-crystal 4H silicon carbide (4H-SiC), a novel polishing technique named anodic oxidation polishing was proposed, which combined with the anodic oxidation of substrate and slurry polishing of oxide. By scanning electron microscopy/energy-dispersive X-ray spectroscopy (SEM-EDX) observation and atomic force microscopy analysis, both the anodic oxidation behaviors of RS-SiC and 4H-SiC were investigated. Through comparison of the surfaces before and after hydrofluoric acid etching of the oxidized samples by the scanning white light interferometry (SWLI) measurement, the relationships between oxidation depth and oxidation time were obtained, and the calculated oxidation rate for RS-SiC was 5.3 nm/s and that for 4H-SiC was 5.8 nm/s based on the linear Deal-Grove model. Through anodic oxidation polishing of RS-SiC substrate and 4H-SiC substrate, respectively, the surface roughness rms obtained by SWLI was improved to 2.103 nm for RS-SiC and to 0.892 nm for 4H-SiC. Experimental results indicate that anodic oxidation polishing is an effective method for the machining of RS-SiC and 4H-SiC samples, which would improve the process level of SiC substrates and promote the application of SiC products in the fields of optics, ceramics, semiconductors, electronics, and so on.

  20. Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

    Science.gov (United States)

    Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

    2017-09-01

    The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

  1. Transport properties of boron-doped single-walled silicon carbide nanotubes

    International Nuclear Information System (INIS)

    Yang, Y.T.; Ding, R.X.; Song, J.X.

    2011-01-01

    The doped boron (B) atom in silicon carbide nanotube (SiCNT) can substitute carbon or silicon atom, forming two different structures. The transport properties of both B-doped SiCNT structures are investigated by the method combined non-equilibrium Green's function with density functional theory (DFT). As the bias ranging from 0.8 to 1.0 V, the negative differential resistance (NDR) effect occurs, which is derived from the great difficulty for electrons tunneling from one electrode to another with the increasing of localization of molecular orbital. The high similar transport properties of both B-doped SiCNT indicate that boron is a suitable impurity for fabricating nano-scale SiCNT electronic devices.

  2. A silicon-based single-electron interferometer coupled to a fermionic sea

    OpenAIRE

    Chatterjee, Anasua; Shevchenko, Sergey N.; Barraud, Sylvain; Otxoa, Ruben M.; Nori, Franco; Morton, John J. L.; Gonzalez-Zalba, M. Fernando

    2017-01-01

    We study Landau-Zener-Stueckelberg-Majorana (LZSM) interferometry under the influence of projective readout using a charge qubit tunnel-coupled to a fermionic sea. This allows us to characterise the coherent charge qubit dynamics in the strong-driving regime. The device is realised within a silicon complementary metal-oxide-semiconductor (CMOS) transistor. We first read out the charge state of the system in a continuous non-demolition manner by measuring the dispersive response of a high-freq...

  3. Wafer based mask characterization for double patterning lithography

    Science.gov (United States)

    de Kruif, Robert; Bubke, Karsten; Janssen, Gert-Jan; van der Heijden, Eddy; Fochler, Jörg; Dusa, Mircea; Peters, Jan Hendrik; de Haas, Paul; Connolly, Brid

    2008-04-01

    Double Patterning Technology (DPT) is considered the most acceptable solution for 32nm node lithography. Apart from the obvious drawbacks of additional exposure and processing steps and therefore reduced throughput, DPT possesses a number of additional technical challenges. This relates to exposure tool capability, the actual applied process in the wafer fab but also to mask performance. This paper will focus on the latter. We will report on the performance of a two-reticle set based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. For 32 nm node lithography using DPT a reticle to reticle overlay contribution target of data resulting from the earlier mentioned reticle set. The reticles contain a 13x19 array of modules comprising various standard overlay features such as ASML overlay gratings and bar-in-bar overlay targets. Furthermore the modules contain split 40nm half pitch DPT features. The reticles have been exposed on an ASML XT:1700i on several wafers in multiple fields. Reticle to reticle overlay contribution has been studied in resist (double exposure) and using the IMEC dual line process (DPT). We will show that the reticle to reticle overlay contribution on the wafer is smaller than 1.5nm (1x). We will compare the wafer data with the reticle data, study the correlation and show that reticle to reticle overlay contribution based single mask registration measurements can be used to qualify the reticle to reticle overlay contribution on wafer.

  4. Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

    NARCIS (Netherlands)

    Popovich, V.A.

    2013-01-01

    Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

  5. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  6. 1366 Project Silicon: Reclaiming US Silicon PV Leadership

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2016-02-16

    1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

  7. Internal alignement of the BABAR silicon vertex tracking detector

    CERN Document Server

    Brown, D; Roberts, D

    2007-01-01

    The BABAR Silicon Vertex Tracker (SVT ) is a five-layer double-sided silicon detector designed to provide precise measurements of the position and direction of primary tracks, and to fully reconstruct low-momentum tracks produced in e+e¡ collisions at the PEP-II asymmetric collider at Stanford Linear Accelerator Center. This paper describes the design, implementation, performance and validation of the local alignment procedure used to determine the relative positions and orientations of the 340 Silicon Vertex Trackerwafers. This procedure uses a tuned mix of lab-bench measurements and complementary in-situ experimental data to control systematic distortions. Wafer positions and orientations are determined by minimizing a Â2 computed using these data for each wafer individually, iterating to account for between-wafer correlations. A correction for aplanar distortions of the silicon wafers is measured and applied. The net effect of residual mis-alignments on relevant physical variables evaluated in special co...

  8. Development of ultra-low impedance Through-wafer Micro-vias

    Energy Technology Data Exchange (ETDEWEB)

    Finkbeiner, F.M. E-mail: fmf@lheapop.gsfc.nasa.gov; Adams, C.; Apodaca, E.; Chervenak, J.A.; Fischer, J.; Doan, N.; Li, M.J.; Stahle, C.K.; Brekosky, R.P.; Bandler, S.R.; Figueroa-Feliciano, E.; Lindeman, M.A.; Kelley, R.L.; Saab, T.; Talley, D.J

    2004-03-11

    Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end Superconducting Quantum Interference Device readout. We are concentrating our developmental efforts on ultra-low impedance copper and superconducting aluminum TWMV in 300-400 micron thick silicon wafers. For both schemes, a periodic pulse-reverse electroplating process is used to fill or coat micron-scale through-wafer holes of aspect ratios up to 20. Here we discuss the design, fabrication process, and recent electro-mechanical test results of Al and Cu TWMV at room and cryogenic temperatures.

  9. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    Science.gov (United States)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  10. Design, fabrication and characterization of the first AC-coupled silicon microstrip sensors in India

    CERN Document Server

    Aziz, T; Mohanty, G.B.; Patil, M.R.; Rao, K.K.; Rani, Y.R.; Rao, Y.P.P.; Behnamian, H.; Mersi, S.; Naseri, M.

    2014-01-01

    This paper reports the design, fabrication and characterization of single-sided silicon microstrip sensors with integrated biasing resistors and coupling capacitors, produced for the first time in India. We have first developed a prototype sensor with different width and pitch combinations on a single 4-inch wafer. After finding test procedures for characterizing these AC coupled sensors, we have chosen an optimal width-pitch combination and also fine-tuned various process parameters in order to produce sensors with the desired specifications.

  11. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  12. Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

    KAUST Repository

    Zhai, Yujia

    2012-11-26

    We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf

  13. 25-Gb/s transmission over 2.5-km SSMF by silicon MRR enhanced 1.55-μm III-V/SOI DML

    DEFF Research Database (Denmark)

    Cristofori, Valentina; Da Ros, Francesco; Ozolins, Oskars

    2017-01-01

    a 11-GHz 1.55-μm directly modulated hybrid III-V/SOI DFB laser realized by bonding III-V materials (InGaAlAs) on a silicon-on-insulator (SOI) wafer and a silicon MRR also fabricated on SOI. Such a transmitter enables error-free transmission (BER... dispersion compensation nor forward error correction (FEC). As both laser and MRR are fabricated on the SOI platform, they could be combined into a single device with enhanced performance, thus providing a cost-effective transmitter for short reach applications....

  14. Study of irradiation induced defects in silicon

    International Nuclear Information System (INIS)

    Pal, Gayatri; Sebastian, K.C.; Somayajulu, D.R.S.; Chintalapudi, S.N.

    2000-01-01

    Pure high resistivity (6000 ohm-cm) silicon wafers were recoil implanted with 1.8 MeV 111 In ions. As-irradiated wafers showed a 13 MHz quadrupole interaction frequency, which was not observed earlier. The annealing behaviour of these defects in the implanted wafers was studied between room temperature and 1073 K. At different annealing temperatures two more interaction frequencies corresponding to defect complexes D2 and D3 are observed. Even though the experimental conditions were different, these are identical to the earlier reported ones. Based on an empirical point charge model calculation, an attempt is made to identify the configuration of these defect complexes. (author)

  15. Summary of theoretical and experimental investigation of grating type, silicon photovoltaic cells. [using p-n junctions on light receiving surface of base crystal

    Science.gov (United States)

    Chen, L. Y.; Loferski, J. J.

    1975-01-01

    Theoretical and experimental aspects are summarized for single crystal, silicon photovoltaic devices made by forming a grating pattern of p/n junctions on the light receiving surface of the base crystal. Based on the general semiconductor equations, a mathematical description is presented for the photovoltaic properties of such grating-like structures in a two dimensional form. The resulting second order elliptical equation is solved by computer modeling to give solutions for various, reasonable, initial values of bulk resistivity, excess carrier concentration, and surface recombination velocity. The validity of the computer model is established by comparison with p/n devices produced by alloying an aluminum grating pattern into the surface of n-type silicon wafers. Current voltage characteristics and spectral response curves are presented for cells of this type constructed on wafers of different resistivities and orientations.

  16. Single Photon Counting UV Solar-Blind Detectors Using Silicon and III-Nitride Materials

    Science.gov (United States)

    Nikzad, Shouleh; Hoenk, Michael; Jewell, April D.; Hennessy, John J.; Carver, Alexander G.; Jones, Todd J.; Goodsall, Timothy M.; Hamden, Erika T.; Suvarna, Puneet; Bulmer, J.; Shahedipour-Sandvik, F.; Charbon, Edoardo; Padmanabhan, Preethi; Hancock, Bruce; Bell, L. Douglas

    2016-01-01

    Ultraviolet (UV) studies in astronomy, cosmology, planetary studies, biological and medical applications often require precision detection of faint objects and in many cases require photon-counting detection. We present an overview of two approaches for achieving photon counting in the UV. The first approach involves UV enhancement of photon-counting silicon detectors, including electron multiplying charge-coupled devices and avalanche photodiodes. The approach used here employs molecular beam epitaxy for delta doping and superlattice doping for surface passivation and high UV quantum efficiency. Additional UV enhancements include antireflection (AR) and solar-blind UV bandpass coatings prepared by atomic layer deposition. Quantum efficiency (QE) measurements show QE > 50% in the 100–300 nm range for detectors with simple AR coatings, and QE ≅ 80% at ~206 nm has been shown when more complex AR coatings are used. The second approach is based on avalanche photodiodes in III-nitride materials with high QE and intrinsic solar blindness. PMID:27338399

  17. Ultrafast terahertz control of extreme tunnel currents through single atoms on a silicon surface

    DEFF Research Database (Denmark)

    Jelic, Vedran; Iwaszczuk, Krzysztof; Nguyen, Peter H.

    2017-01-01

    Ultrafast control of current on the atomic scale is essential for future innovations in nanoelectronics. Extremely localized transient electric fields on the nanoscale can be achieved by coupling picosecond duration terahertz pulses to metallic nanostructures. Here, we demonstrate terahertz...... scanning tunnelling microscopy (THz-STM) in ultrahigh vacuum as a new platform for exploring ultrafast non-equilibrium tunnelling dynamics with atomic precision. Extreme terahertz-pulse-driven tunnel currents up to 10(7) times larger than steady-state currents in conventional STM are used to image...... individual atoms on a silicon surface with 0.3nm spatial resolution. At terahertz frequencies, the metallic-like Si(111)-(7 x 7) surface is unable to screen the electric field from the bulk, resulting in a terahertz tunnel conductance that is fundamentally different than that of the steady state. Ultrafast...

  18. 77 GHz MEMS antennas on high-resistivity silicon for linear and circular polarization

    KAUST Repository

    Sallam, M. O.

    2011-07-01

    Two new MEMS antennas operating at 77 GHz are presented in this paper. The first antenna is linearly polarized. It possesses a vertical silicon wall that carries a dipole on top of it. The wall is located on top of silicon substrate covered with a ground plane. The other side of the substrate carries a microstrip feeding network in the form of U-turn that causes 180 phase shift. This phase-shifter feeds the arms of the dipole antenna via two vertical Through-Silicon Vias (TSVs) that go through the entire wafer. The second antenna is circularly polarized and formed using two linearly polarized antennas spatially rotated with respect to each other by 90 and excited with 90 phase shift. Both antennas are fabricated using novel process flow on a single high-resistivity silicon wafer via bulk micromachining. Only three processing steps are required to fabricate these antennas. The proposed antennas have appealing characteristics, such as high polarization purity, high gain, and high radiation efficiency. © 2011 IEEE.

  19. Optimization of the Surface Structure on Black Silicon for Surface Passivation

    Science.gov (United States)

    Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

    2017-03-01

    Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al2O3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH4OH/H2O2/H2O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

  20. Optimization of the Surface Structure on Black Silicon for Surface Passivation.

    Science.gov (United States)

    Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

    2017-12-01

    Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al 2 O 3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH 4 OH/H 2 O 2 /H 2 O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

  1. Atomic hydrogen and oxygen adsorptions in single-walled zigzag silicon nanotubes

    International Nuclear Information System (INIS)

    Chen, Haoliang; Ray, Asok K.

    2013-01-01

    Ab initio calculations have been performed to study the electronic and geometric structure properties of zigzag silicon nanotubes. Full geometry and spin optimizations have been performed without any symmetry constraints with an all electron 3-21G* basis set and the B3LYP hybrid functional. The largest zigzag SiNT studied here, (12, 0), has a binding energy per atom of 3.584 eV. Atomic hydrogen and oxygen adsorptions on (9, 0) and (10, 0) nanotubes have also been studied by optimizing the distances of the adatoms from both inside and outside the tube. The adatom is initially placed in four adsorption sites-parallel bridge (PB), zigzag bridge (ZB), hollow, and on-top site. The on-top site is the most preferred site for hydrogen atom adsorbed on (9, 0), with an adsorption energy of 3.0 eV and an optimized distance of 1.49 Å from the adatom to the nearest silicon atom. For oxygen adsorption on (9, 0), the most preferred site is the ZB site, with an adsorption energy of 5.987 eV and an optimized distance of 1.72 Å. For atomic hydrogen adsorption on (10, 0), the most preferred site is also the on-top site with an adsorption energy of 3.174 eV and an optimized distance of 1.49 Å. For adsorption of atomic oxygen on (10, 0), the most preferred site is PB site, with an adsorption energy of 6.306 eV and an optimized distance of 1.71 Å. The HOMO–LUMO gaps of (9, 0) after adsorptions of hydrogen and oxygen atoms decrease while the HOMO–LUMO gaps of (10, 0) increase after adsorption of hydrogen and oxygen

  2. Development of low-cost silicon crystal growth techniques for terrestrial photovoltaic solar energy conversion

    Science.gov (United States)

    Zoutendyk, J. A.

    1976-01-01

    Because of the growing need for new sources of electrical energy, photovoltaic solar energy conversion is being developed. Photovoltaic devices are now being produced mainly from silicon wafers obtained from the slicing and polishing of cylindrically shaped single crystal ingots. Inherently high-cost processes now being used must either be eliminated or modified to provide low-cost crystalline silicon. Basic to this pursuit is the development of new or modified methods of crystal growth and, if necessary, crystal cutting. If silicon could be grown in a form requiring no cutting, a significant cost saving would potentially be realized. Therefore, several techniques for growth in the form of ribbons or sheets are being explored. In addition, novel techniques for low-cost ingot growth and cutting are under investigation.

  3. Enhanced efficiency of hybrid amorphous silicon solar cells based on single-walled carbon nanotubes and polymer composite thin film

    Science.gov (United States)

    Rajanna, Pramod M.; Gilshteyn, Evgenia P.; Yagafarov, Timur; Aleekseeva, Alena K.; Anisimov, Anton S.; Neumüller, Alex; Sergeev, Oleg; Bereznev, Sergei; Maricheva, Jelena; Nasibulin, Albert G.

    2018-03-01

    We report a simple approach to fabricate hybrid solar cells (HSCs) based on a single-walled carbon nanotube (SWCNT) film and thin film hydrogenated amorphous silicon (a-Si:H). Randomly oriented high-quality SWCNTs with conductivity enhanced by means of poly(3,4-ethylenedioxythiophene) polystyrene sulfonate are used as a window layer and a front electrode. A series of HSCs are fabricated in ambient conditions with varying SWCNT film thicknesses. The polymethylmethacrylate layer drop-casted on fabricated HSCs reduces the reflection fourfold and enhances the short-circuit J sc , open-circuit V oc , and efficiency by nearly 10%. A state-of-the-art J-V performance is shown for SWCNT/a-Si HSC with an open-circuit voltage of 900 mV and an efficiency of 3.4% under simulated one-sun AM 1.5 G direct illumination.

  4. Novel Gas Sensor Arrays Based on High-Q SAM-Modified Piezotransduced Single-Crystal Silicon Bulk Acoustic Resonators

    Directory of Open Access Journals (Sweden)

    Yuan Zhao

    2017-06-01

    Full Text Available This paper demonstrates a novel micro-size (120 μm × 200 μm piezoelectric gas sensor based on a piezotransduced single-crystal silicon bulk acoustic resonator (PSBAR. The PSBARs operate at 102 MHz and possess high Q values (about 2000, ensuring the stability of the measurement. A corresponding gas sensor array is fabricated by integrating three different self-assembled monolayers (SAMs modified PSBARs. The limit of detection (LOD for ethanol vapor is demonstrated to be as low as 25 ppm with a sensitivity of about 1.5 Hz/ppm. Two sets of identification code bars based on the sensitivities and the adsorption energy constants are utilized to successfully discriminate isopropanol (IPA, ethanol, hexane and heptane vapors at low and high gas partial pressures, respectively. The proposed sensor array shows the potential to form a portable electronic nose system for volatile organic compound (VOC differentiation.

  5. Modelling deformation and fracture in confectionery wafers

    Science.gov (United States)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  6. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  7. Multi-wafer growth of highly uniform InGaP/GaAs by low pressure MOVPE

    Science.gov (United States)

    McKee, M. A.; McGivney, T.; Walker, D.; Capuder, K.; Norris, P. E.; Stall, R. A.; Rose, B. C.

    1992-03-01

    This paper reports on the large area growth of InGaP/GaAs heterostructures for short wavelength applications (λ ˜ 650 nm) by low pressure MOVPE in a vertical, high speed, rotating disk reactor. Highly uniform films were obtained both on a single 50 mm diam wafer at the center of a 5 inch diam wafer platter and on three, 50 mm diameter GaAs wafers symmetrically placed on a 5 inch diam platter. Characterization was performed by x-ray diffraction, SEM, and room temperature photoluminescence (PL) mapping. For the single wafer growth, PL mapping results show that the total range on wavelength was ±2 nm with a 2 mm edge exclusion. The standard deviation of the peak wavelength, σ w , is 0.7 nm. Thickness uniformity, measured by SEM, is less than 2%. Similar results were obtained for the multi-wafer runs. Each individual wafer has a σ w of 1.1 nm. The wafers have nearly identical PL maps with the variation of the average wavelength from the three wafers within ±0.1 nm.

  8. Switchable static friction of piezoelectric composite-silicon wafer contacts

    NARCIS (Netherlands)

    Ende, D.A. van den; Fischer, H.R.; Groen, W.A.; Zwaag, S. van der

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  9. Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

    Science.gov (United States)

    2014-08-01

    hygroscopic nature of the oxidizer. Parylene films are generally known to be impervious to moisture and liquids , which make them attractive for hermetic...Energetic materials that are hygroscopic in nature need to be protected from the environment during storage to improved ignition lifetime. Parylene...surfaces. Our existing deposition chamber is approximately 10 inches in diameter and 12 inches high. A liquid nitrogen cold trap, located between the

  10. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    Administrator

    microelectronic and optoelectronic devices (Ino et al. 1994). It is used as gate dielectric in MOS components. (Tsividis 1999) and also applied in the fabrication of micro- electromechanical systems (MEMS) (Kaushik et al. 2005). In photovoltaic field, SiN has the function of defects passivation (Sopori et al 1996) and light anti-.

  11. A Theoretical Study of a Novel Single-Electron Refrigerator Fabricated from Semiconductor Materials

    Science.gov (United States)

    Ikeda, Hiroya; Salleh, Faiz

    2011-06-01

    We propose a novel single-electron refrigerator (SER) that can be fabricated from semiconductor materials such as a silicon-on-insulator wafer. The SER consists of a single-electron box and a single-electron pump (SEP). An equivalent circuit of the SEP refrigerator was derived. Its stability diagram (Coulomb diamond) was theoretically calculated and found to have a distorted honeycomb structure. In addition, a Monte Carlo simulation based on the orthodox theory for the Coulomb blockade phenomenon predicts successful single-electron extraction and injection.

  12. Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

    Science.gov (United States)

    Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

    2017-06-01

    In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

  13. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  14. Comparative investigation on designs of light absorption enhancement of ultrathin crystalline silicon for photovoltaic applications

    Science.gov (United States)

    Huang, Yi; Wang, Wei; Pan, Wu; Chen, Weizhong; Wang, Zhen; Tan, Xinyu; Yan, Wensheng

    2016-10-01

    Ultrathin crystalline silicon wafers for photovoltaic applications have attracted intensive attention because of potential benefits in cost-effectiveness. Structural design with high light absorption is important for photovoltaics because planar ultrathin silicon is poor in absorption. We conduct a comparative investigation on designs of light absorption enhancement for 2-μm-thick ultrathin crystalline silicon, where the front texture is a nanopyramidal structure and the rear adopts several designs. Our calculation results show that both of the ultrathin silicon with front nanopyramids and rear silver nanoarrays and the ultrathin silicon with two-sided nanopyramids are promising for photovoltaic applications. For the latter design, the calculated photocurrent achieves the highest value of 35.1 mA/cm2 when a perfect electric conductor layer is applied at the bottom. In contrast, the former design has a lower photocurrent value of 31.2 mA/cm2. But, this design is of practical significance because the majority of experimental reports on ultrathin crystalline silicon solar cells are single-sided front-textured at present and the fabrication techniques of plasmonic Ag nanoarrays are matured. Compared with previous reports, the present work offers a multiple option of structural designs for ultrathin crystalline silicon to enhance the light absorption for photovoltaic applications.

  15. Field induced decrystallization of silicon: Evidence of a microwave non-thermal effect

    Science.gov (United States)

    Nozariasbmarz, Amin; Dsouza, Kelvin; Vashaee, Daryoosh

    2018-02-01

    It is rather strange and not fully understood that some materials decrystallize when exposed to microwave radiation, and it is still debatable if such a transformation is a thermal or non-thermal effect. We hereby report experimental evidences that weight the latter effect. First, a single crystal silicon wafer exposed to microwaves showed strong decrystallization at high temperature. Second, when some areas of the wafer were masked with metal coating, only the exposed areas underwent decrystallization. Transmission electron microscopy analysis, x-ray diffraction data, and thermal conductivity measurements all indicated strong decrystallization, which occurred in the bulk of the material and was not a surface effect. These observations favor the existence of a non-thermal microwave effect.

  16. All-in-polymer injection molded device for single cell capture using multilevel silicon master fabrication

    DEFF Research Database (Denmark)

    Tanzi, S.; Larsen, S.T.; Matteucci, M.

    2012-01-01

    This work demonstrates a novel all-in-polymer device for single cell capture applicable for biological recordings. The chip is injection molded and comprises a "cornered" (non planar) aperture. It has been demonstrated how cornered apertures are straightforward to mold in PDMS [1,2]. In this stud...... defects during demolding. Capturing of single PC12 cells has been demonstrated.......This work demonstrates a novel all-in-polymer device for single cell capture applicable for biological recordings. The chip is injection molded and comprises a "cornered" (non planar) aperture. It has been demonstrated how cornered apertures are straightforward to mold in PDMS [1,2]. In this study...

  17. Optical coating uniformity of 200mm (8") diameter precut wafers

    Science.gov (United States)

    Burt, Travis C.; Fisher, Mark; Brown, Dean; Troiani, David

    2017-02-01

    Automated spectroscopic profiling (mapping) of a 200 mm diameter near infrared high reflector (centered at 1064 nm) are presented. Spatial resolution at 5 mm or less was achieved using a 5 mm × 1.5 mm monochromatic beam. Reflection changes of 1.0% across the wafer diameter were observed under s-polarized and p- polarized conditions. Redundancy was established for each chord by re-measuring the center of the wafer and reproducibility of approximately used to measure the reflectance and transmittance of a sample across a range of angles (θi) at near normal angles of incidence (AOI). A recent development by Agilent Technologies, the Cary 7000 Universal Measurement Spectrophotometer (UMS) combines both reflection and transmission measurements from the same patch of a sample's surface in a single automated platform for angles of incidence in the range 5°use of MPS on the Cary 7000 UMS with rotational (Φ) and vertical (z) sample positioning control. MPS(θi,Φ,z) provides for automated unattended multi-angle R/T analysis of at 200 mm diameter samples with the goal to provide better spectroscopic measurement feedback into large wafer manufacturing to ensure yields are maximized, product quality is better controlled and waste is reduced before further down-stream processing.

  18. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  19. Single-event upset and snapback in silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Dodd, Paul E.; Shaneyfelt, Marty R.; Schwank, James R.; Hash, Gerald L.; Draper, Bruce L.; Winokur, Peter S.

    2000-01-01

    SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed

  20. Harnessing light energy with a planar transparent hybrid of graphene/single wall carbon nanotube/n-type silicon heterojunction solar cell

    DEFF Research Database (Denmark)

    Chen, Leifeng; Yu, Hua; Zhong, Jiasong

    2015-01-01

    The photovoltaic conversion efficiency of a solar cell fabricated by a simple electrophoretic method with a planar transparent hybrid of graphenes (GPs) and single wall carbon nanotubes (SCNTs)/n-type silicon heterojunction was significantly increased compared to GPs/n-Si and SCNTs/n-Si solar cells...

  1. Modelling of heating and photoexcitation of single-crystal silicon under multipulse irradiation by a nanosecond laser at 1.06 μm

    Science.gov (United States)

    Polyakov, D. S.; Yakovlev, E. B.

    2018-03-01

    We report a theoretical study of heating and photoexcitation of single-crystal silicon by nanosecond laser radiation at a wavelength of 1.06 μm. The proposed physicomathematical model of heating takes into account the complex nonlinear dynamics of the interband absorption coefficient of silicon and the contribution of the radial heat removal to the cooling of silicon between pulses under multipulse irradiation, which allows one to obtain a satisfactory agreement between theoretical predictions of silicon melting thresholds at different nanosecond pulse durations and experimental data (both under single-pulse and multipulse irradiation). It is found that under irradiation by nanosecond pulses at a wavelength of 1.06 μm, the dynamic Burshtein–Moss effect can play an important role in processes of photoexcitation and heating. It is shown that with the regimes typical for laser multipulse microprocessing of silicon (the laser spot diameter is less than 100 μm, and the repetition rate of pulses is about 100 kHz), the radial heat removal cannot be neglected in the analysis of heat accumulation processes.

  2. SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

    Science.gov (United States)

    Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

    2016-10-01

    Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

  3. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  4. Single Photon Counting UV Solar-Blind Detectors Using Silicon and III-Nitride Materials

    Directory of Open Access Journals (Sweden)

    Shouleh Nikzad

    2016-06-01

    Full Text Available Ultraviolet (UV studies in astronomy, cosmology, planetary studies, biological and medical applications often require precision detection of faint objects and in many cases require photon-counting detection. We present an overview of two approaches for achieving photon counting in the UV. The first approach involves UV enhancement of photon-counting silicon detectors, including electron multiplying charge-coupled devices and avalanche photodiodes. The approach used here employs molecular beam epitaxy for delta doping and superlattice doping for surface passivation and high UV quantum efficiency. Additional UV enhancements include antireflection (AR and solar-blind UV bandpass coatings prepared by atomic layer deposition. Quantum efficiency (QE measurements show QE > 50% in the 100–300 nm range for detectors with simple AR coatings, and QE ≅ 80% at ~206 nm has been shown when more complex AR coatings are used. The second approach is based on avalanche photodiodes in III-nitride materials with high QE and intrinsic solar blindness.

  5. Flexible Thermoelectric Generators on Silicon Fabric

    KAUST Repository

    Sevilla, Galo T.

    2012-11-01

    In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

  6. Low temperature spalling of silicon: A crack propagation study

    Energy Technology Data Exchange (ETDEWEB)

    Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

    2017-06-08

    Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.

  7. Mimicking both petal and lotus effects on a single silicon substrate by tuning the wettability of nanostructured surfaces.

    Science.gov (United States)

    Dawood, M K; Zheng, H; Liew, T H; Leong, K C; Foo, Y L; Rajagopalan, R; Khan, S A; Choi, W K

    2011-04-05

    We describe a new method of fabricating large-area, highly scalable, "hybrid" superhydrophobic surfaces on silicon (Si) substrates with tunable, spatially selective adhesion behavior by controlling the morphologies of Si nanowire arrays. Gold (Au) nanoparticles were deposited on Si by glancing-angle deposition, followed by metal-assisted chemical etching of Si to form Si nanowire arrays. These surfaces were chemically modified and rendered hydrophobic by fluorosilane deposition. Au nanoparticles with different size distributions resulted in the synthesis of Si nanowires with very different morphologies (i.e., clumped and straight nanowire surfaces). The difference in nanowire morphology is attributed to capillary force-induced nanocohesion, which is due to the difference in nanowire porosity. The clumped nanowire surface demonstrated the lotus effect, and the straighter nanowires demonstrated the ability to pin water droplets while maintaining large contact angles (i.e., the petal effect). The high contact angles in both cases are explained by invoking the Cassie-Baxter wetting state. The high adhesion behavior of the straight nanowire surface may be explained by a combination of attractive van der Waals forces and capillary adhesion. We demonstrate the spatial patterning of both low- and high-adhesion superhydrophobicity on the same substrate by the simultaneous synthesis of clumped and straight silicon nanowires. The demonstration of hybrid superhydrophobic surfaces with spatially selective, tunable adhesion behavior on single substrates paves the way for future applications in microfluidic channels, substrates for biologically and chemically based analysis and detection where it is necessary to analyze a particular droplet in a defined location on a surface, and as a platform to study in situ chemical mixing and interfacial reactions of liquid pearls.

  8. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  9. Microchannel-connected SU-8 honeycombs by single-step projection photolithography for positioning cells on silicon oxide nanopillar arrays

    International Nuclear Information System (INIS)

    Larramendy, Florian; Paul, Oliver; Blatche, Marie Charline; Mazenq, Laurent; Laborde, Adrian; Temple-Boyer, Pierre

    2015-01-01

    We report on the fabrication, functionalization and testing of SU-8 microstructures for cell culture and positioning over large areas. The microstructure consists of a honeycomb arrangement of cell containers interconnected by microchannels and centered on nanopillar arrays designed for promoting cell positioning. The containers have been dimensioned to trap single cells and, with a height of 50 µm, prevent cells from escaping. The structures are fabricated using a single ultraviolet photolithography exposure with focus depth in the lower part of the SU-8 resist. With optimized process parameters, microchannels of various aspect ratios are thus produced. The cell containers and microchannels serve for the organization of axonal growth between neurons. The roughly 2 µm-high and 500 nm-wide nanopillars are made of silicon oxide structured by deep reactive ion etching. In future work, beyond their cell positioning purpose, the nanopillars could be functionalized as sensors. The proof of concept of the novel microstructure for organized cell culture is given by the successful growth of interconnected PC12 cells. Promoted by the honeycomb geometry, a dense network of interconnections between the cells has formed and the intended intimate contact of cells with the nanopillar arrays was observed by scanning electron microscopy. This proves the potential of these new devices as tools for the controlled cell growth in an interconnected container system with well-defined 3D geometry. (paper)

  10. Friction and wear of metals with a single-crystal abrasive grit of silicon carbide: Effect of shear strength of metal

    Science.gov (United States)

    Miyoshi, K.; Buckley, D. H.

    1978-01-01

    Sliding friction experiments were conducted with spherical, single-crystal silicon carbide riders in contact with various metals and with metal riders in contact with silicon carbide flats. Results indicate that: (1) the friction force in the plowing of metal and (2) the groove height (corresponding to the volume of the groove) are related to the shear strength of the metal. That is, they decrease linearly as the shear strength of the bulk metal increases. Grooves are formed in metals primarily from plastic deformation, with occasional metal removal. The relation between the groove width D and the load W can be expressed by W = kD, superscript n which satisfies Meyer's law.

  11. Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

    International Nuclear Information System (INIS)

    Balpande, Suresh S.; Pande, Rajesh S.

    2016-01-01

    Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of

  12. Single atom doping for quantum device development in diamond and silicon

    NARCIS (Netherlands)

    Weis, C.D.; Schuh, A.; Batra, A.; Persaud, A.; Rangelow, I.W.; Bokor, J.; Lo, C.C.; Cabrini, S.; Sideras-Haddad, E.; Fuchs, G.D.; Hanson, R.; Awschalom, D.D.; Schenkel, T.

    2008-01-01

    The ability to inject dopant atoms with high spatial resolution, flexibility in dopant species, and high single ion detection fidelity opens opportunities for the study of dopant fluctuation effects and the development of devices in which function is based on the manipulation of quantum states in

  13. Ternary logic implemented on a single dopant atom field effect silicon transistor

    NARCIS (Netherlands)

    Klein, M.; Mol, J.A.; Verduijn, J.; Lansbergen, G.P.; Rogge, S.; Levine, R.D.; Remacle, F.

    2010-01-01

    We provide an experimental proof of principle for a ternary multiplier realized in terms of the charge state of a single dopant atom embedded in a fin field effect transistor (Fin-FET). Robust reading of the logic output is made possible by using two channels to measure the current flowing through

  14. Floating Silicon Method

    Energy Technology Data Exchange (ETDEWEB)

    Kellerman, Peter

    2013-12-21

    The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

  15. Silicon Qubits

    Energy Technology Data Exchange (ETDEWEB)

    Ladd, Thaddeus D. [HRL Laboratories, LLC, Malibu, CA (United States); Carroll, Malcolm S. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2018-02-28

    Silicon is a promising material candidate for qubits due to the combination of worldwide infrastructure in silicon microelectronics fabrication and the capability to drastically reduce decohering noise channels via chemical purification and isotopic enhancement. However, a variety of challenges in fabrication, control, and measurement leaves unclear the best strategy for fully realizing this material’s future potential. In this article, we survey three basic qubit types: those based on substitutional donors, on metal-oxide-semiconductor (MOS) structures, and on Si/SiGe heterostructures. We also discuss the multiple schema used to define and control Si qubits, which may exploit the manipulation and detection of a single electron charge, the state of a single electron spin, or the collective states of multiple spins. Far from being comprehensive, this article provides a brief orientation to the rapidly evolving field of silicon qubit technology and is intended as an approachable entry point for a researcher new to this field.

  16. Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

    Directory of Open Access Journals (Sweden)

    Liu Haijun

    2015-12-01

    Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

  17. Proof of concept of an epitaxy-free layer-transfer process for silicon solar cells based on the reorganisation of macropores upon annealing

    International Nuclear Information System (INIS)

    Depauw, V.; Gordon, I.; Beaucarne, G.; Poortmans, J.; Mertens, R.; Celis, J.-P.

    2009-01-01

    To answer the challenge of less expensive renewable electricity, the photovoltaics community is focusing on producing thinner silicon solar cells. A few years ago, in the field of silicon-on-nothing structures, micron-thick monocrystalline layers suspended over their parent wafer were produced by high-temperature annealing of specific arrays of macropores. Those macropores reorganise into one single void and leave a thin overlayer on top. Since this method may be an inexpensive way of fabricating high-quality silicon films, this paper investigates its potential for photovoltaic applications. In particular, we investigated if large surfaces can be produced and transferred to foreign substrates with this method. We fabricated basic solar cells, without rear-surface passivation, on 5 cm x 5 cm-large and 1-μm-thick films transferred to glass, that showed energy-conversion efficiencies up to 2.6%. These cells demonstrate the feasibility of the presented concept as a layer-transfer process for solar-cell application. After formation by annealing, the film is only barely attached to its parent wafer, but can still safely be handled provided that any abrupt gas flow or pumping to vacuum is avoided. After transfer and permanent bonding, the sample can be handled as any bulk wafer.

  18. Development of Screen-Printed Texture-Barrier Paste for Single-Side Texturization of Interdigitated Back-Contact Silicon Solar Cell Applications

    Directory of Open Access Journals (Sweden)

    Chi-Cheng Chen

    2013-10-01

    Full Text Available Continuous cost reduction of silicon-based solar cells is needed to lower the process time and increase efficiency. To achieve lower costs, screen-printed texture-barrier (SPTB paste was first developed for single-side texturization (ST of the interdigitated back-contact (IBC for silicon-based solar cell applications. The SPTB paste was screen-printed on silicon substrates. The SPTB paste was synthesized from intermixed silicate glass (75 wt %, a resin binder (ethyl cellulose ethoce: 20 wt %, and a dispersing agent (fatty acid: 5 wt %. The silicate glass is a necessity for contact formation during firing. A resin binder and a dispersing agent determine the rheology of the SPTB paste. In this work, by modulating various parameters, including post SPTB firing, alkali texturing, and removal of the SPTB, the ST of IBC silicon solar cells was achieved. Since the advantages of the SPTB paste include low toxicity and prompt formation of the texture-barrier, SPTB is potentially suited for simple fabrication at low-cost for solar cell applications. The cost of the SPTB is around $100/kg which is lower than the SiH4/NH3 gas ambient used in plasma-enhanced chemical vapor deposition (PECVD. Thus, the expensive Si3N4 film deposited by PECVD using SiH4 and NH3 gas ambient for silicon solar cells can be replaced by this SPTB.

  19. Development of Screen-Printed Texture-Barrier Paste for Single-Side Texturization of Interdigitated Back-Contact Silicon Solar Cell Applications.

    Science.gov (United States)

    Chiu, Yu-Shun; Cheng, Chin-Lung; Whang, Thou-Jen; Chen, Chi-Cheng

    2013-10-17

    Continuous cost reduction of silicon-based solar cells is needed to lower the process time and increase efficiency. To achieve lower costs, screen-printed texture-barrier (SPTB) paste was first developed for single-side texturization (ST) of the interdigitated back-contact (IBC) for silicon-based solar cell applications. The SPTB paste was screen-printed on silicon substrates. The SPTB paste was synthesized from intermixed silicate glass (75 wt %), a resin binder (ethyl cellulose ethoce: 20 wt %), and a dispersing agent (fatty acid: 5 wt %). The silicate glass is a necessity for contact formation during firing. A resin binder and a dispersing agent determine the rheology of the SPTB paste. In this work, by modulating various parameters, including post SPTB firing, alkali texturing, and removal of the SPTB, the ST of IBC silicon solar cells was achieved. Since the advantages of the SPTB paste include low toxicity and prompt formation of the texture-barrier, SPTB is potentially suited for simple fabrication at low-cost for solar cell applications. The cost of the SPTB is around $100/kg which is lower than the SiH₄/NH₃ gas ambient used in plasma-enhanced chemical vapor deposition (PECVD). Thus, the expensive Si₃N₄ film deposited by PECVD using SiH₄ and NH₃ gas ambient for silicon solar cells can be replaced by this SPTB.

  20. All-in-polymer injection molded device for single cell capture using multilevel silicon master fabrication

    DEFF Research Database (Denmark)

    Tanzi, S.; Larsen, S.T.; Matteucci, M.

    2012-01-01

    This work demonstrates a novel all-in-polymer device for single cell capture applicable for biological recordings. The chip is injection molded and comprises a "cornered" (non planar) aperture. It has been demonstrated how cornered apertures are straightforward to mold in PDMS [1,2]. In this study...... we demonstrate cornered apertures made in a thermoplastic polymer. One of the advantages of cornered apertures is the ease of microscopy under a standard inverted optical microscope, when using transparent materials. After the part is injection molded, the sealing of the chip is performed by thermal...

  1. Correction of Dopant Concentration Fluctuation Effects in Silicon Drift Detectors

    CERN Document Server

    Nouais, D; Bonvicini, V; Cerello, P G; Crescio, E; Giubellino, P; Hernández-Montoya, R; Kolojvari, A A; Montaño-Zetina, L M; Nilsen, B S; Piemonte, C; Rachevsky, A; Tosello, F; Vacchi, A; Wheadon, R

    2001-01-01

    Dopant fluctuations in silicon wafers are responsible for systematic errors in the determination of the particle crossing point in silicon drift detectors. In this paper, we report on the first large scale measurement of this effect by means of a particle beam. A significant improvement of the anodic resolution has been obtained by correcting for these systematic deviations.

  2. Light management in thin-film silicon solar cells

    NARCIS (Netherlands)

    Isabella, O.

    2013-01-01

    Solar energy can fulfil mankind’s energy needs and secure a more balanced distribution of primary sources of energy. Wafer-based and thin-film silicon solar cells dominate todays’ photovoltaic market because silicon is a non-toxic and abundant material and high conversion efficiencies are achieved

  3. Design, fabrication, testing and packaging of a silicon ...

    Indian Academy of Sciences (India)

    In this paper, we describe the fabrication, wafer level test- ing and packaging of a silicon on glass based RF MEMS switch fabricated using DRIE. The device is a SPST direct contact series switch. The silicon on glass fabrication process has been suc- cessfully adapted by a number of groups to fabricate MEMS devices such ...

  4. The impact of silicon feedstock on the PV module cost

    NARCIS (Netherlands)

    del Coso, G.; del Cañizo, C.; Sinke, W.C.

    2010-01-01

    The impact of the use of new (solar grade) silicon feedstock materials on the manufacturing cost of wafer-based crystalline silicon photovoltaic modules is analyzed considering effects of material cost, efficiency of utilisation, and quality. Calculations based on data provided by European industry

  5. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  6. A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

    Energy Technology Data Exchange (ETDEWEB)

    Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

    2016-12-15

    In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  7. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    International Nuclear Information System (INIS)

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  8. The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

    International Nuclear Information System (INIS)

    Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

    2004-01-01

    We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

  9. A micromachined silicon valve driven by a miniature bi-stable electro-magnetic actuator

    NARCIS (Netherlands)

    Bohm, S.; Burger, G.J.; Burger, G.J.; Korthorst, M.T.; Roseboom, F.

    2000-01-01

    In this paper a novel combination of a micromachined silicon valve with low dead volume and a bi-stable electromagnetic actuator produced by conventional machining is presented. The silicon valve part, 7×7×1 mm3 in dimensions, is a sandwich construction of two KOH etched silicon wafers with a layer

  10. Features of polyatomic ion emission under sputtering of a silicon single crystal by Au sub m sup - cluster ions

    CERN Document Server

    Akhunov, S; Rasulev, U K

    2003-01-01

    Comparative studies of the emission of secondary cluster Si sub n sup + ions (n=1-11) and polyatomic Si sub n X sub l Y sub k sup + ions (X, Y are Au, B, C, N), as well as doubly charged Si sup 2 sup + ions under bombardment of single crystalline silicon by cluster Au sub m sup - (m=1-5) ions with energy E sub 0 =4-18 keV have been carried out. High non-additivity enhancement of the yield of the Si sub n sup + ions and most polyatomic ones has been observed with an increase of the number of atoms in the projectiles. For Si sup 2 sup + ions the negative non-additive effect has been observed. The increase in the yield of impurity-containing cluster Si sub n X sup + ions allows for an increase by a factor of 100-1000 for the sensitivity of the SIMS analysis of the Au, B, C, N impurities in Si with the use of cluster ions as primary and secondary ones.

  11. Silicon-Vacancy Spin Qubit in Diamond: A Quantum Memory Exceeding 10 ms with Single-Shot State Readout

    Science.gov (United States)

    Sukachev, D. D.; Sipahigil, A.; Nguyen, C. T.; Bhaskar, M. K.; Evans, R. E.; Jelezko, F.; Lukin, M. D.

    2017-12-01

    The negatively charged silicon-vacancy (SiV- ) color center in diamond has recently emerged as a promising system for quantum photonics. Its symmetry-protected optical transitions enable the creation of indistinguishable emitter arrays and deterministic coupling to nanophotonic devices. Despite this, the longest coherence time associated with its electronic spin achieved to date (˜250 ns ) has been limited by coupling to acoustic phonons. We demonstrate coherent control and suppression of phonon-induced dephasing of the SiV- electronic spin coherence by 5 orders of magnitude by operating at temperatures below 500 mK. By aligning the magnetic field along the SiV- symmetry axis, we demonstrate spin-conserving optical transitions and single-shot readout of the SiV- spin with 89% fidelity. Coherent control of the SiV- spin with microwave fields is used to demonstrate a spin coherence time T2 of 13 ms and a spin relaxation time T1 exceeding 1 s at 100 mK. These results establish the SiV- as a promising solid-state candidate for the realization of quantum networks.

  12. DNA Physical Mapping via the Controlled Translocation of Single Molecules through a 5-10nm Silicon Nitride Nanopore

    Science.gov (United States)

    Stein, Derek; Reisner, Walter; Jiang, Zhijun; Hagerty, Nick; Wood, Charles; Chan, Jason

    2009-03-01

    The ability to map the binding position of sequence-specific markers, including transcription-factors, protein-nucleic acids (PNAs) or deactivated restriction enzymes, along a single DNA molecule in a nanofluidic device would be of key importance for the life-sciences. Such markers could give an indication of the active genes at particular stage in a cell's transcriptional cycle, pinpoint the location of mutations or even provide a DNA barcode that could aid in genomics applications. We have developed a setup consisting of a 5-10 nm nanopore in a 20nm thick silicon nitride film coupled to an optical tweezer setup. The translocation of DNA across the nanopore can be detected via blockades in the electrical current through the pore. By anchoring one end of the translocating DNA to an optically trapped microsphere, we hope to stretch out the molecule in the nanopore and control the translocation speed, enabling us to slowly scan across the genome and detect changes in the baseline current due to the presence of bound markers.

  13. Performance enhancement of a silicon MEMS piezoresistive single axis accelerometer with electroplated gold on a proof mass

    Science.gov (United States)

    Sankar, A. Ravi; Lahiri, S. K.; Das, S.

    2009-02-01

    Performance enhancement of a silicon MEMS piezoresistive single axis accelerometer with electroplated gold on a proof mass is presented in this paper. The fabricated accelerometer device consists of a heavy proof mass supported by four thin flexures. Boron-diffused piezoresistors located near the fixed ends of the flexures are used for sensing the developed stress and hence acceleration. Performance enhancement is achieved by electroplating a gold mass of 20 µm thickness on top of the proof mass. A commercially available sulfite-based solution TSG-250™ was used for the electroplating process. Aluminum metal lines were used to form a Wheatstone bridge for signal pick-up. To avoid galvanic corrosion between two dissimilar metals having contact in an electrolyte, a shadow mask technique was used to selectively deposit a Cr/Au seed layer on an insulator atop the proof mass for subsequent electrodeposition. Bulk micromachining was performed using a 5% dual-doped TMAH solution. Fabricated devices with different electroplated gold areas were tested up to ±13 g acceleration. For electroplated gold dimensions of 2500 µm × 2500 µm × 20 µm on a proof mass, sensitivity along the Z-axis is increased by 21.8% as compared to the structure without gold. Off-axis sensitivities along the X- and Y-axes are reduced by 7.6% and 6.9%, respectively.

  14. Silicon materials outlook study for 1980-85 calendar years

    Energy Technology Data Exchange (ETDEWEB)

    Costogue, E.; Ferber, R.; Hasbach, W.; Pellin, R.; Yaws, C.

    1979-11-01

    Photovoltaic solar cell arrays converting solar energy into electrical energy can become a cost-effective, alternative energy source provided that an adequate supply of low-priced solar cell materials and automated fabrication techniques are available. Presently, the photovoltaic industry is dependent upon polycrystalline silicon which is produced primarily for the discrete semiconductor device industry. This dependency is expected to continue until DOE-sponsored new technology developments mature. Recent industry forecasts have predicted a limited supply of polycrystalline silicon material and a shortage could occur in the early 80's. The Jet Propulsion Laboratory's Technology Development and Application Lead Center formed an ad hoc committee at JPL, SERI and consultant personnel to conduct interviews with key polycrystalline manufacturers and a large cross-section of single crystal ingot growers and wafer manufacturers. Industry consensus and conclusions reached from the analysis of the data obtained by the committee are reported. The highlight of the study is that there is a high probability of polycrystalline silicon shortage by the end of CY 1982 and a strong seller's market after CY 1981 which will foster price competition for available silicon.

  15. Future application of Czochralski crystal pulling for silicon

    Science.gov (United States)

    Matlcok, J. H.

    1985-08-01

    Czochralski (Cz) crystal pulling has been the predominant method used for preparing silicon single crystal for the past twenty years. The fundamental technology used has changed little. However, great strides have been made in learning how to make the crystals bigger and of better quality at ever increasing productivity rates. Currently charge sizes of 50 kg of polycrystal silicon are being used for production and crystals up to ten inches in diameter have been grown without major difficulty. The largest material actually being processed in silicon wafer form is 150 mm (6 inches) in diameter. Growing of crystals in a magnetic field has proved to be particularly useful for microscopic impurity control. Major developments in past years on equipment for Cz crystal pulling have included the automatic growth control of the diameter as well as the starting core of the crystal, the use of magnetic fields and around the crystal puller to supress convection, various recharging schemes for dopant control and the use of continuous liquid feed in the crystal puller. The latter, while far from being a reliable production process, is ideal in concept for major improvement in Cz crystal pulling. The Czochralski process will maintain its dominance of silicon crystal production for many years.

  16. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  17. Stencil print applications and progress for crystalline silicon solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Hoornstra, J.; Heurtault, B. [ECN Solar Energy, Petten (Netherlands)

    2009-09-15

    This paper describes laboratory testing to research the capabilities of stencil printing, as compared to screen printing, with a focus on fine line high aspect ratio printing on crystalline silicon wafer material. Scanning of potential of screen and stencil printing moving to finer fingers shows advantages for stencil printing. Testing of electroformed, laser cut, single and double layer stencils, and using various pastes, demonstrates the need for improved paste rheology. Optimal line definition with an aspect ratio of 0.37 was obtained with single layer stencils with fully open fingers. In a two step process, with a stencil for only fingers, followed by screen print of the busbars, +0.4% efficiency gain was reached for industrial type mc-Si cells.

  18. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    International Nuclear Information System (INIS)

    Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

    2014-01-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  20. A depth-encoding PET detector that uses light sharing and single-ended readout with silicon photomultipliers.

    Science.gov (United States)

    Kuang, Zhonghua; Yang, Qian; Wang, Xiaohui; Fu, Xin; Ren, Ning; Sang, Ziru; Wu, San; Zheng, Yunfei; Zhang, Xianming; Hu, Zhanli; Du, Junwei; Liang, Dong; Liu, Xin; Zheng, Hairong; Yang, Yongfeng

    2018-02-13

    Detectors with depth-encoding capability and good timing resolution are required to develop high-performance whole-body or total-body PET scanners. In this work, depth-encoding PET detectors that use light sharing between two discrete crystals and single-ended readout with silicon photomultipliers (SiPMs) were manufactured and evaluated. The detectors consisted of two unpolished 3  ×  3  ×  20 mm 3 LYSO crystals with different coupling materials between them and were read out by Hamamatsu 3  ×  3 mm 2 SiPMs with one-to-one coupling. The ratio of the energy of one SiPM to the total energy of two SiPMs was used to measure the depth of interaction (DOI). Detectors with different coupling materials in-between the crystals were measured in the singles mode in an effort to obtain detectors that can provide good DOI resolution. The DOI resolution and energy resolution of three types of detector were measured and the timing resolution was measured for the detector with the best DOI and energy resolution. The optimum detector, with 5 mm optical glue, a 9 mm triangular ESR and a 6 mm rectangular ESR in-between the unpolished crystals, provides a DOI resolution of 2.65 mm, an energy resolution of 10.0% and a timing resolution of 427 ps for events of E  >  400 keV. The detectors simultaneously provide good DOI and timing resolution, and show great promise for the development of high-performance whole-body and total-body PET scanners.

  1. A depth-encoding PET detector that uses light sharing and single-ended readout with silicon photomultipliers

    Science.gov (United States)

    Kuang, Zhonghua; Yang, Qian; Wang, Xiaohui; Fu, Xin; Ren, Ning; Sang, Ziru; Wu, San; Zheng, Yunfei; Zhang, Xianming; Hu, Zhanli; Du, Junwei; Liang, Dong; Liu, Xin; Zheng, Hairong; Yang, Yongfeng

    2018-02-01

    Detectors with depth-encoding capability and good timing resolution are required to develop high-performance whole-body or total-body PET scanners. In this work, depth-encoding PET detectors that use light sharing between two discrete crystals and single-ended readout with silicon photomultipliers (SiPMs) were manufactured and evaluated. The detectors consisted of two unpolished 3  ×  3  ×  20 mm3 LYSO crystals with different coupling materials between them and were read out by Hamamatsu 3  ×  3 mm2 SiPMs with one-to-one coupling. The ratio of the energy of one SiPM to the total energy of two SiPMs was used to measure the depth of interaction (DOI). Detectors with different coupling materials in-between the crystals were measured in the singles mode in an effort to obtain detectors that can provide good DOI resolution. The DOI resolution and energy resolution of three types of detector were measured and the timing resolution was measured for the detector with the best DOI and energy resolution. The optimum detector, with 5 mm optical glue, a 9 mm triangular ESR and a 6 mm rectangular ESR in-between the unpolished crystals, provides a DOI resolution of 2.65 mm, an energy resolution of 10.0% and a timing resolution of 427 ps for events of E  >  400 keV. The detectors simultaneously provide good DOI and timing resolution, and show great promise for the development of high-performance whole-body and total-body PET scanners.

  2. Fabrication and Probabilistic Fracture Strength Prediction of High-Aspect-Ratio Single Crystal Silicon Carbide Microspecimens With Stress Concentration

    Science.gov (United States)

    Nemeth, Noel N.; Evans, Laura J.; Jadaan, Osama M.; Sharpe, William N., Jr.; Beheim, Glenn M.; Trapp, Mark A.

    2005-01-01

    Single crystal silicon carbide micro-sized tensile specimens were fabricated with deep reactive ion etching (DRIE) in order to investigate the effect of stress concentration on the room-temperature fracture strength. The fracture strength was defined as the level of stress at the highest stressed location in the structure at the instant of specimen rupture. Specimens with an elliptical hole, a circular hole, and without a hole (and hence with no stress concentration) were made. The average fracture strength of specimens with a higher stress concentration was larger than the average fracture strength of specimens with a lower stress concentration. Average strength of elliptical-hole, circular-hole, and without-hole specimens was 1.53, 1.26, and 0.66 GPa, respectively. Significant scatter in strength was observed with the Weibull modulus ranging between 2 and 6. No fractographic examination was performed but it was assumed that the strength controlling flaws originated from etching grooves along the specimen side-walls. The increase of observed fracture strength with increasing stress concentration was compared to predictions made with the Weibull stress-integral formulation by using the NASA CARES/Life code. In the analysis isotropic material and fracture behavior was assumed - hence it was not a completely rigorous analysis. However, even with these assumptions good correlation was achieved for the circular-hole specimen data when using the specimen data without stress concentration as a baseline. Strength was over predicted for the elliptical-hole specimen data. Significant specimen-to-specimen dimensional variation existed in the elliptical-hole specimens due to variations in the nickel mask used in the etching. To simulate the additional effect of the dimensional variability on the probabilistic strength response for the single crystal specimens the ANSYS Probabilistic Design System (PDS) was used with CARES/Life.

  3. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  4. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  5. Micromachining of buried micro channels in silicon

    NARCIS (Netherlands)

    de Boer, Meint J.; Tjerkstra, R.W.; Berenschot, Johan W.; Jansen, Henricus V.; Burger, G.J.; Burger, G.J.; Gardeniers, Johannes G.E.; Elwenspoek, Michael Curt; van den Berg, Albert

    A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the

  6. Fabrication and Characterization of Silicon Micro-Funnels and Tapered Micro-Channels for Stochastic Sensing Applications

    Directory of Open Access Journals (Sweden)

    Frances S. Ligler

    2008-06-01

    Full Text Available We present a simplified, highly reproducible process to fabricate arrays of tapered silicon micro-funnels and micro-channels using a single lithographic step with a silicon oxide (SiO2 hard mask on at a wafer scale. Two approaches were used for the fabrication. The first one involves a single wet anisotropic etch step in concentrated potassium hydroxide (KOH and the second one is a combined approach comprising Deep Reactive Ion Etch (DRIE followed by wet anisotropic etching. The etching is performed through a 500 mm thick silicon wafer, and the resulting structures are characterized by sharp tapered ends with a sub-micron cross-sectional area at the tip. We discuss the influence of various parameters involved in the fabrication such as the size and thickness variability of the substrate, dry and wet anisotropic etching conditions, the etchant composition, temperature, diffusion and micro-masking effects, the quality of the hard mask in the uniformity and reproducibility of the structures, and the importance of a complete removal of debris and precipitates. The presence of apertures at the tip of the structures is corroborated through current voltage measurements and by the translocation of DNA through the apertures. The relevance of the results obtained in this report is discussed in terms of the potential use of these structures for stochastic sensing.

  7. Effect of radiation-induced lattice defects in silicon single crystals on the characteristic states of an intersticial muonium atom

    International Nuclear Information System (INIS)

    Barsov, S.G.; Getalov, A.L.; Gordeev, V.A.

    1983-01-01

    It is observed experimentally that radiation defects affect normal and anomalous muonium in silicon differently. It is shown that the mobilities of these two states of muonium in the lattice of the specimen differ considerably

  8. Lifetime of Nano-Structured Black Silicon for Photovoltaic Applications

    DEFF Research Database (Denmark)

    Plakhotnyuk, Maksym; Davidsen, Rasmus Schmidt; Schmidt, Michael Stenbæk

    2016-01-01

    properties. We applied reactive ion etching technology at -20ºC to create nano-structures on silicon samples and obtained an average reflectance below 0.5%. For passivation purposes, we used 37 nm ALD Al2O3 films. Lifetime measurements resulted in 1220 µs and to 4170 µs for p- and ntype CZ silicon wafers......, respectively. This is promising for use of black silicon RIE nano-structuring in a solar cell process flow...

  9. Simulation of Single Particle Displacement Damage in Silicon – Part II: Generation and Long-Time Relaxation of Damage Structure

    OpenAIRE

    Jay , Antoine; Raine , Melanie; Richard , Nicolas; Mousseau , Normand; Goiffon , Vincent; Hémeryck , Anne; Magnan , Pierre

    2017-01-01

    International audience; A statistical study of displacement cascades induced by silicon Primary Knock-on Atoms (PKA) in bulk silicon is performed by running a large number of molecular dynamics (MD) simulations. The choice of the PKA species and energy varying from 1 to 100 keV comes from a previous particle-matter simulation [1]. The electronic stopping power missing in standard MD simulations is here taken into account using the Two Temperature Model (TTM). This prevents from overestimating...

  10. TXRF analysis of trace metals in thin silicon nitride films

    International Nuclear Information System (INIS)

    Vereecke, G.; Arnauts, S.; Verstraeten, K.; Schaekers, M.; Heyrts, M.M.

    2000-01-01

    As critical dimensions of integrated circuits continue to decrease, high dielectric constant materials such as silicon nitride are being considered to replace silicon dioxide in capacitors and transistors. The achievement of low levels of metal contamination in these layers is critical for high performance and reliability. Existing methods of quantitative analysis of trace metals in silicon nitride require high amounts of sample (from about 0.1 to 1 g, compared to a mass of 0.2 mg for a 2 nm thick film on a 8'' silicon wafer), and involve digestion steps not applicable to films on wafers or non-standard techniques such as neutron activation analysis. A novel approach has recently been developed to analyze trace metals in thin films with analytical techniques currently used in the semiconductor industry. Sample preparation consists of three steps: (1) decomposition of the silicon nitride matrix by moist HF condensed at the wafer surface to form ammonium fluosilicate. (2) vaporization of the fluosilicate by a short heat treatment at 300 o C. (3) collection of contaminants by scanning the wafer surface with a solution droplet (VPD-DSC procedure). The determination of trace metals is performed by drying the droplet on the wafer and by analyzing the residue by TXRF, as it offers the advantages of multi-elemental analysis with no dilution of the sample. The lower limits of detection for metals in 2 nm thick films on 8'' silicon wafers range from about 10 to 200 ng/g. The present study will focus on the matrix effects and the possible loss of analyte associated with the evaporation of the fluosilicate salt, in relation with the accuracy and the reproducibility of the method. The benefits of using an internal standard will be assessed. Results will be presented from both model samples (ammonium fluoride contaminated with metallic salts) and real samples (silicon nitride films from a production tool). (author)

  11. Raman characterization of hydrogen ion implanted silicon: 'High-dose effect'?

    International Nuclear Information System (INIS)

    Ovsyannikov, Sergey V.; Shchennikov, Vsevolod V.; Shchennikov, Vladimir V.; Ponosov, Yuri S.; Antonova, Irina V.; Smirnov, Sergey V.

    2008-01-01

    The Raman spectra of nanostructures formed on silicon Si single-crystalline wafers by implantation with hydrogen ions of fluencies ranging within D∼2x10 16 -3x10 17 cm -2 are reported. The presence of both crystalline and amorphous silicon phases were found in the spectra. A non-monotonic growth in the intensities of the peaks originating from the crystalline and the amorphous phases with a dose of the implantation was registered. A ratio of the intensities of the main peaks of the amorphous to the crystalline Si phases also demonstrated a non-monotonic behaviour ('high-dose effect'). Possible reasons and mechanisms of the non-monotonic dependence of a 'degree' of amorphization on a dose of the implantation (or irradiation) are discussed

  12. Sprayed and Spin-Coated Multilayer Antireflection Coating Films for Nonvacuum Processed Crystalline Silicon Solar Cells

    Directory of Open Access Journals (Sweden)

    Abdullah Uzum

    2017-01-01

    Full Text Available Using the simple and cost-effective methods, spin-coated ZrO2-polymer composite/spray-deposited TiO2-compact multilayer antireflection coating film was introduced. With a single TiO2-compact film on the surface of a crystalline silicon wafer, 5.3% average reflectance (the reflectance average between the wavelengths of 300 nm and 1100 nm was observed. Reflectance decreased further down to 3.3% after forming spin-coated ZrO2 on the spray-deposited TiO2-compact film. Silicon solar cells were fabricated using CZ-Si p-type wafers in three sets: (1 without antireflection coating (ARC layer, (2 with TiO2-compact ARC film, and (3 with ZrO2-polymer composite/TiO2-compact multilayer ARC film. Conversion efficiency of the cells improved by a factor of 0.8% (from 15.19% to 15.88% owing to the multilayer ARC. Jsc was improved further by 2 mA cm−2 (from 35.3 mA cm−2 to 37.2 mA cm−2 when compared with a single TiO2-compact ARC.

  13. Effectiveness of the custom-mold room temperature vulcanizing silicone toe separator on hallux valgus: A prospective, randomized single-blinded controlled trial.

    Science.gov (United States)

    Chadchavalpanichaya, Navaporn; Prakotmongkol, Voraluck; Polhan, Nattapong; Rayothee, Pitchaya; Seng-Iad, Sirirat

    2018-04-01

    Silicone toe separator is considered as a conservative treatment for hallux valgus. The prefabricated toe separator does not fit all. However, effectiveness in prescription of the custom-mold toe separator is still unknown. To investigate the effect of using a custom-mold room temperature vulcanizing silicone toe separator to decrease hallux valgus angle and hallux pain. The compliances, complications, and satisfactions of toe separator were also explored. A prospective, randomized single-blinded controlled trial. A total of 90 patients with a moderate degree of hallux valgus were enrolled in a study at the Foot Clinic, Siriraj Hospital, Thailand. Patients were randomized into two groups; the study group was prescribed a custom-mold room temperature vulcanizing silicone toe separator for 6 h per night for 12 months. Patients in both groups received proper foot care and shoes and were permitted to continue drug treatment. In total, 40 patients in the study group and 39 patients in the control group completed the study. The hallux valgus angle was obtained through radiographic measurement. At month 12, both groups had significant differences in mean hallux valgus angle with a decrease of 3.3° ± 2.4° for the study group and increase of 1.9° ± 1.9° for the control group. There were statistically significant differences of hallux valgus angle between the two groups ( p Hallux pain was decreased in the study group. A custom-mold room temperature vulcanizing silicone toe separator can decrease hallux valgus angle and pain with no serious complications. Clinical relevance The custom-mold room temperature vulcanizing silicone toe separator for treatment of hallux valgus reduces deformity and hallux pain.

  14. Devices using resin wafers and applications thereof

    Science.gov (United States)

    Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL; Martin, Edward [Libertyville, IL; Arora, Michelle [Woodridge, IL; de la Garza, Linda [Woodridge, IL

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  15. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  16. Carbon dioxide capture using resin-wafer electrodeionization

    Energy Technology Data Exchange (ETDEWEB)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  17. NTD Silicon; Product Characteristics, Main Uses and Growth Potential

    International Nuclear Information System (INIS)

    Hansen, M. G.; Bjorling, C. F.

    2013-01-01

    Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain

  18. Rinsing of wafers after wet processing: Simulation and experiments

    Science.gov (United States)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second

  19. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  20. Wafer level test solutions for IR sensors

    Science.gov (United States)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  1. On the evolution of wafer level cameras

    Science.gov (United States)

    Welch, H.

    2011-02-01

    The introduction of small cost effective cameras based on CMOS image sensor technology has played an important role in the revolution in mobile devices of the last 10 years. Wafer-based optics manufacturing leverages the same fabrication equipment used to produce CMOS sensors. The natural integration of these two technologies allows the mass production of very low cost surface mount cameras that can fit into ever thinner mobile devices. Nano Imprint Lithography (NIL) equipment has been adapted to make precision aspheres that can be stacked using wafer bonding techniques to produce multi-element lens assemblies. This, coupled with advances in mastering technology, allows arrays of lenses with prescriptions not previously possible. A primary motivation for these methods is that it allows the consolidation of the supply chain. Image sensor manufacturers envision creating optics by simply adding layers to their existing sensor fabrication lines. Results thus far have been promising. The current alternative techniques for creating VGA cameras are discussed as well as the prime cost drivers for lens to sensor integration. Higher resolution cameras face particularly difficult challenges, but can greatly simplify the critical tilt and focus steps needed to assemble cameras that produce quality images. Finally, we discuss the future of wafer-level cameras and explore several of the novel concepts made possible by the manufacturing advantages of photolithography.

  2. Signal development in irradiated silicon detectors

    CERN Document Server

    Kramberger, Gregor; Mikuz, Marko

    2001-01-01

    This work provides a detailed study of signal formation in silicon detectors, with the emphasis on detectors with high concentration of irradiation induced defects in the lattice. These defects give rise to deep energy levels in the band gap. As a consequence, the current induced by charge motion in silicon detectors is signifcantly altered. Within the framework of the study a new experimental method, Charge correction method, based on transient current technique (TCT) was proposed for determination of effective electron and hole trapping times in irradiated silicon detectors. Effective carrier trapping times were determined in numerous silicon pad detectors irradiated with neutrons, pions and protons. Studied detectors were fabricated on oxygenated and non-oxygenated silicon wafers with different bulk resistivities. Measured effective carrier trapping times were found to be inversely proportional to fuence and increase with temperature. No dependence on silicon resistivity and oxygen concentration was observ...

  3. Room temperature wafer direct bonding of smooth Si surfaces recovered by Ne beam surface treatments

    Science.gov (United States)

    Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki

    2013-06-01

    We examined the applicability of a Ne fast atom beam (FAB) to surface activated bonding of Si wafers at room temperature. With etching depth more than 1.5 nm, the bonding strength comparable to Si bulk strength was attained. Moreover, we found the improvement of the bonding strength by surface smoothing effect of the Ne FAB. Silicon surface roughness decreased from 0.40 to 0.17 nm rms by applying a Ne FAB of 30 nm etching depth. The bonding strength between surfaces recovered by Ne FAB surface smoothing was largely improved and finally became equivalent to Si bulk strength.

  4. Mechanically flexible optically transparent porous mono-crystalline silicon substrate

    KAUST Repository

    Rojas, Jhonathan Prieto

    2012-01-01

    For the first time, we present a simple process to fabricate a thin (≥5μm), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon <100> wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates. © 2012 IEEE.

  5. Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

    Directory of Open Access Journals (Sweden)

    Azrul Azlan Hamzah

    2008-11-01

    Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

  6. Bias-assisted KOH etching of macroporous silicon membranes

    International Nuclear Information System (INIS)

    Mathwig, K; Geilhufe, M; Müller, F; Gösele, U

    2011-01-01

    This paper presents an improved technique to fabricate porous membranes from macroporous silicon as a starting material. A crucial step in the fabrication process is the dissolution of silicon from the backside of the porous wafer by aqueous potassium hydroxide to open up the pores. We improved this step by biasing the silicon wafer electrically against the KOH. By monitoring the current–time characteristics a good control of the process is achieved and the yield is improved. Also, the etching can be stopped instantaneously and automatically by short-circuiting Si and KOH. Moreover, the bias-assisted etching allows for the controlled fabrication of silicon dioxide tube arrays when the silicon pore walls are oxidized and inverted pores are released.

  7. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  8. Low cost back contact heterojunction solar cells on thin c-Si wafers. Integrating laser and thin film processing for improved manufacturability

    Energy Technology Data Exchange (ETDEWEB)

    Hegedus, Steven S. [Univ. of Delaware, Newark, DE (United States)

    2015-09-08

    An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerfless techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to

  9. Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

    Energy Technology Data Exchange (ETDEWEB)

    Hegedus, Steven S. [Univ. of Delaware, Newark, DE (United States)

    2015-09-08

    An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerfless techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to

  10. Surface recombination analysis in silicon-heterojunction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Barrio, R.; Gandia, J.J.; Carabe, J.; Gonzalez, N.; Torres, I. [CIEMAT, Madrid (Spain); Munoz, D.; Voz, C. [Universitat Politecnica de Catalunya, Barcelona (Spain)

    2010-02-15

    The origin of this work is the understanding of the correlation observed between efficiency and emitter-deposition temperature in single silicon-heterojunction solar cells prepared by depositing an n-doped hydrogenated-amorphous-silicon thin film onto a p-type crystalline-silicon wafer. In order to interpret these results, surface-recombination velocities have been determined by two methods, i.e. by fitting the current-voltage characteristics to a theoretical model and by means of the Quasi-Steady-State Photoconductance Technique (QSSPC). In addition, effective diffusion lengths have been estimated from internal quantum efficiencies. The analysis of these data has led to conclude that the performance of the cells studied is limited by back-surface recombination rather than by front-heterojunction quality. A 12%-efficient cell has been prepared by combining optimum emitter-deposition conditions with back-surface-field (BSF) formation by vacuum annealing of the back aluminium contact. This result has been achieved without using any transparent conductive oxide. (author)

  11. High Throughput Nanofabrication of Silicon Nanowire and Carbon Nanotube Tips on AFM Probes by Stencil-Deposited Catalysts

    DEFF Research Database (Denmark)

    Engstrøm, Daniel Southcott; Savu, Veronica; Zhu, Xueni

    2011-01-01

    A new and versatile technique for the wafer scale nanofabrication of silicon nanowire (SiNW) and multiwalled carbon nanotube (MWNT) tips on atomic force microscope (AFM) probes is presented. Catalyst material for the SiNW and MWNT growth was deposited on prefabricated AFM probes using aligned wafer...

  12. Electric field reduced charging energies and two-electron bound excited states of single donors in silicon

    NARCIS (Netherlands)

    Rahman, R.; Lansbergen, G.P.; Verduijn, J.; Tettamanzi, G.C.; Park, S.H.; Collaert, N.; Biesemans, S.; Klimeck, G.; Hollenberg, L.C.L.; Rogge, S.

    2011-01-01

    We present atomistic simulations of the D0 to D? charging energies of a gated donor in silicon as a function of applied fields and donor depths and find good agreement with experimental measurements. A self-consistent field large-scale tight-binding method is used to compute the D? binding energies

  13. Micro-morphology of single crystalline silicon surfaces during anisotropic wet chemical etching in KOH: velocity source forests

    NARCIS (Netherlands)

    van Veenendaal, E.; Sato, K.; Shikida, M.; Shikida, M.; Nijdam, A.J.; van Suchtelen, J.

    2001-01-01

    For silicon etched in KOH the micro-morphology of any surface, no matter the crystallographic orientation, is defined by some sort of persistent corrugations. As a matter of principle, the occurrence of these corrugations is incompatible with the classical kinematic wave theory for the evolution of

  14. A New Analytical Subthreshold Behavior Model for Single-Halo, Dual-Material Gate Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

    Science.gov (United States)

    Chiang, Te-Kuang

    2008-11-01

    On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the single-halo, dual-material gate (SHDMG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is developed. The model is verified by the good agreement with a numerical simulation using the device simulator MEDICI. The model not only offers a physical insight into device physics but is also an efficient device model for the circuit simulation.

  15. Particle precipitation in connection with KOH etching of silicon

    DEFF Research Database (Denmark)

    Nielsen, Christian Bergenstof; Christensen, Carsten; Pedersen, Casper

    2004-01-01

    This paper considers the precipitation of iron oxide particles in connection with the KOH etching of cavities in silicon wafers. The findings presented in this paper suggest that the source to the particles is the KOH pellets used for making the etching solution. Experiments show...... that the precipitation is independent of KOH etching time, but that the amount of deposited material varies with dopant type and dopant concentration. The experiments also suggest that the precipitation occurs when the silicon wafers are removed from the KOH etching solution and not during the etching procedure. When...

  16. A deep etching mechanism for trench-bridging silicon nanowires

    International Nuclear Information System (INIS)

    Tasdemir, Zuhal; Alaca, B Erdem; Wollschläger, Nicole; Österle, Werner; Leblebici, Yusuf

    2016-01-01

    Introducing a single silicon nanowire with a known orientation and dimensions to a specific layout location constitutes a major challenge. The challenge becomes even more formidable, if one chooses to realize the task in a monolithic fashion with an extreme topography, a characteristic of microsystems. The need for such a monolithic integration is fueled by the recent surge in the use of silicon nanowires as functional building blocks in various electromechanical and optoelectronic applications. This challenge is addressed in this work by introducing a top-down, silicon-on-insulator technology. The technology provides a pathway for obtaining well-controlled silicon nanowires along with the surrounding microscale features up to a three-order-of-magnitude scale difference. A two-step etching process is developed, where the first shallow etch defines a nanoscale protrusion on the wafer surface. After applying a conformal protection on the protrusion, a deep etch step is carried out forming the surrounding microscale features. A minimum nanowire cross-section of 35 nm by 168 nm is demonstrated in the presence of an etch depth of 10 μm. Nanowire cross-sectional features are characterized via transmission electron microscopy and linked to specific process steps. The technology allows control on all dimensional aspects along with the exact location and orientation of the silicon nanowire. The adoption of the technology in the fabrication of micro and nanosystems can potentially lead to a significant reduction in process complexity by facilitating direct access to the nanowire during surface processes such as contact formation and doping. (paper)

  17. Wafer-Scale Nanopillars Derived from Block Copolymer Lithography for Surface-Enhanced Raman Spectroscopy

    DEFF Research Database (Denmark)

    Li, Tao; Wu, Kaiyu; Rindzevicius, Tomas

    2016-01-01

    We report a novel nanofabrication process via block copolymer lithography using solvent vapor annealing. The nanolithography process is facile and scalable, enabling fabrication of highly ordered periodic patterns over entire wafers as substrates for surface-enhanced Raman spectroscopy (SERS......). Direct silicon etching with high aspect ratio templated by the block copolymer mask is realized without any intermediate layer or external precursors. Uniquely, an atomic layer deposition (ALD)-assisted method is introduced to allow reversing of the morphology relative to the initial pattern. As a result......, highly ordered silicon nanopillar arrays are fabricated with controlled aspect ratios. After metallization, the resulting nanopillar arrays are suitable for SERS applications. These structures readily exhibit an average SERS enhancement factor of above 108, SERS uniformities of 8.5% relative standard...

  18. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  19. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  20. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.