WorldWideScience

Sample records for single poly cmos

  1. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  2. An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags

    International Nuclear Information System (INIS)

    Jia Xiaoyun; Feng Peng; Zhang Shengguang; Wu Nanjian; Zhao Baiqin; Liu Su

    2013-01-01

    This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler—Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm 2 and 0.12 mm 2 , respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s). (semiconductor integrated circuits)

  3. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  4. Future challenges in single event effects for advanced CMOS technologies

    International Nuclear Information System (INIS)

    Guo Hongxia; Wang Wei; Luo Yinhong; Zhao Wen; Guo Xiaoqiang; Zhang Keying

    2010-01-01

    SEE have became a substantial Achilles heel for the reliability of space-based advanced CMOS technologies with features size downscaling. Future space and defense systems require identification and understanding of single event effects to develop hardening approaches for advanced technologies, including changes in device geometry and materials affect energy deposition, charge collection,circuit upset, parametric degradation devices. Topics covered include the impact of technology scaling on radiation response, including single event transients in high speed digital circuits, evidence for single event effects caused by proton direct ionization, and the impact for SEU induced by particle energy effects and indirect ionization. The single event effects in CMOS replacement technologies are introduced briefly. (authors)

  5. Single atom imaging with an sCMOS camera

    Science.gov (United States)

    Picken, C. J.; Legaie, R.; Pritchard, J. D.

    2017-10-01

    Single atom imaging requires discrimination of weak photon count events above the background and has typically been performed using electron-multiplying charge-coupled device cameras, photomultiplier tubes, or single photon counting modules. A scientific complementary metal-oxide semiconductor (sCMOS) provides a cost effective and highly scalable alternative to other single atom imaging technologies, offering fast readout and larger sensor dimensions. We demonstrate single atom resolved imaging of two site-addressable optical traps separated by 10 μm using an sCMOS camera, offering a competitive signal-to-noise ratio at intermediate count rates to allow high fidelity readout discrimination (error <10-6) and sub-μm spatial resolution for applications in quantum technologies.

  6. Single-photon imaging in CMOS

    NARCIS (Netherlands)

    Charbon, E.

    2010-01-01

    We report on the architectural design and fabrication of medium and large arrays of single-photon avalanche diodes (SPADs) for a variety of applications in physics, medicine, and the life sciences. Due to dynamic nature of SPADs, designs featuring a large number of SPADs require careful analysis of

  7. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  8. Scaling Beyond Moore: Single Electron Transistor and Single Atom Transistor Integration on CMOS

    OpenAIRE

    Deshpande , Veeresh

    2012-01-01

    Continuous scaling of MOSFET dimensions has led us to the era of nanoelectronics. Multigate FET (MuGFET) architecture with 'nanowire channel'is being considered as one feasible enabler of MOSFET scaling to end-of-roadmap. Alongside classical CMOS or Moore's law scaling, many novel device proposals exploiting nanoscale phenomena have been made. Single Electron Transistor (SET), with its unique 'Coulomb Blockade' phenomena, and Single Atom Transistor (SAT), as an ultimately scaled transistor, a...

  9. Low light CMOS contact imager with an integrated poly-acrylic emission filter for fluorescence detection.

    Science.gov (United States)

    Dattner, Yonathan; Yadid-Pecht, Orly

    2010-01-01

    This study presents the fabrication of a low cost poly-acrylic acid (PAA) based emission filter integrated with a low light CMOS contact imager for fluorescence detection. The process involves the use of PAA as an adhesive for the emission filter. The poly-acrylic solution was chosen due its optical transparent properties, adhesive properties, miscibility with polar protic solvents and most importantly its bio-compatibility with a biological environment. The emission filter, also known as an absorption filter, involves dissolving an absorbing specimen in a polar protic solvent and mixing it with the PAA to uniformly bond the absorbing specimen and harden the filter. The PAA is optically transparent in solid form and therefore does not contribute to the absorbance of light in the visible spectrum. Many combinations of absorbing specimen and polar protic solvents can be derived, yielding different filter characteristics in different parts of the spectrum. We report a specific combination as a first example of implementation of our technology. The filter reported has excitation in the green spectrum and emission in the red spectrum, utilizing the increased quantum efficiency of the photo sensitive sensor array. The thickness of the filter (20 μm) was chosen by calculating the desired SNR using Beer-Lambert's law for liquids, Quantum Yield of the fluorophore and the Quantum Efficiency of the sensor array. The filters promising characteristics make it suitable for low light fluorescence detection. The filter was integrated with a fully functional low noise, low light CMOS contact imager and experimental results using fluorescence polystyrene micro-spheres are presented.

  10. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  11. Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

    Science.gov (United States)

    Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

    2005-04-01

    We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

  12. Volumetric imaging using single chip integrated CMUT-on-CMOS IVUS array.

    Science.gov (United States)

    Tekes, Coskun; Zahorian, Jaime; Gurun, Gokce; Satir, Sarp; Xu, Toby; Hochman, Michael; Degertekin, F Levent

    2012-01-01

    An intravascular ultrasound (IVUS) catheter that can provide forward viewing volumetric ultrasound images would be an invaluable clinical tool for guiding interventions. Single chip integration of front-end electronics with capacitive micromachined ultrasonic transducers (CMUTs) is highly desirable to reduce the interconnection complexity and enable miniaturization in IVUS catheters. For this purpose we use the monolithic CMUT-on-CMOS integration where CMUTs are fabricated directly on top of pre-processed CMOS wafers. This minimizes parasitic capacitances associated with connection lines. We have recently implemented a system design including all the required electronics using 0.35-µm CMOS process integrated with a 1.4-mm diameter CMUT array. In this study, we present the experimental volumetric imaging results from an ex-vivo chicken heart phantom. The imaging results demonstrate that the single-chip forward looking IVUS (FL-IVUS) system with monolithically integrated electronics has potential to visualize the front view of coronary arteries.

  13. A new single-photon avalanche diode in 90nm standard CMOS technology

    NARCIS (Netherlands)

    Karami, M.A.; Gersbach, M.; Charbon, E.

    2010-01-01

    A single-photon avalanche diode (SPAD) fabricated in a 90nm standard CMOS process is reported. The detector comprises an octagonal multiplication region and a guard ring to prevent premature edge breakdown using exclusively standard layers. The proposed structure is the result of a systematic study

  14. Characterization of Single-Photon Avalanche Diodes in Standard 140-nm SOI CMOS Technology

    NARCIS (Netherlands)

    Lee, M.J.; Sun, P.; Charbon, E.

    2015-01-01

    We report on the characterization of single-photon avalanche diodes (SPADs) fabricated in standard 140-nm silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. As a methodology for SPAD optimization, a test structure array, called SPAD farm, was realized with several

  15. Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Fang Tang

    2014-01-01

    Full Text Available Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

  16. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  17. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

    International Nuclear Information System (INIS)

    Bonacini, S.

    2007-11-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

  18. A 4-8GHz CMOS active balun using a compensated single-FET topology

    Science.gov (United States)

    Milner, Leigh

    2007-12-01

    A single-FET active balun has been developed with a phase imbalance of less than +/-1.5° and amplitude imbalance less than +/-0.6dB from 4 to 8 GHz using 0.25μm silicon-on-sapphire CMOS. The source terminal of the transistor has been compensated with a shunt capacitance to ground and increased value for the source resistance. The compensation network has improved the phase imbalance by 29° at 8 GHz. The circuit dissipates 15mW and is 260×300μm including AC coupling capacitors.

  19. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  20. Design and analysis of CMOS single photon counting avalanche photodiodes integrated with active quenching circuits

    International Nuclear Information System (INIS)

    Kim, Kwang Hyun; Kim, Young Soo

    2008-01-01

    The CMOS SPADs (Single Photon Avalanche Diodes) integrated with active quenching circuits were fabricated on same chip using AMIS 0.7 μm high voltage CMOS process without any process modifications. The SPADs have N+/P-substrate structure and their diameter of photo sensing area are 25 μm, 50 μm, 100 μm, 400 μm, and 800 μm. The avalanche multiplication is occurred at 10.7 V, and the photocurrent gain at 11 V reverse bias voltage is about 1000. In zero bias condition, the maximum quantum efficiency appears at 650 nm wavelength, and it corresponds to around 30%. The active quenching circuit is composed to a comparator, three monostable, and two MOS switch. As a circuit simulation results, the comparator and the monostable generate ∼22 nsec and ∼1 nsec delayed output pulse, respectively. The dead time of the active quenching circuits integrated with SPADs is about 100 nsec as a measured result. (author)

  1. Comparison of analytical models and experimental results for single-event upset in CMOS SRAMs

    International Nuclear Information System (INIS)

    Mnich, T.M.; Diehl, S.E.; Shafer, B.D.

    1983-01-01

    In an effort to design fully radiation-hardened memories for satellite and deep-space applications, a 16K and a 2K CMOS static RAM were modeled for single-particle upset during the design stage. The modeling resulted in the addition of a hardening feedback resistor in the 16K remained tentatively unaltered. Subsequent experiments, using the Lawrence Berkeley Laboratories' 88-inch cyclotron to accelerate krypton and oxygen ions, established an upset threshold for the 2K and the 16K without resistance added, as well as a hardening threshold for the 16K with feedback resistance added. Results for the 16K showed it to be hardenable to the higher level than previously published data for other unhardened 16K RAMs. The data agreed fairly well with the modeling results; however, a close look suggests that modification of the simulation methodology is required to accurately predict the resistance necessary to harden the RAM cell

  2. pH sensing through a single optical fibre using SERS and CMOS SPAD line arrays.

    Science.gov (United States)

    Ehrlich, K; Kufcsák, A; McAughtrie, S; Fleming, H; Krstajic, N; Campbell, C J; Henderson, R K; Dhaliwal, K; Thomson, R R; Tanner, M G

    2017-12-11

    Full exploitation of fibre Raman probes has been limited by the obstruction of weak Raman signals by background fluorescence of the sample and the intrinsic Raman signal of the delivery fibre. Here we utilised functionalised gold nanoshells (NS) to take advantage of the surface-enhanced Raman spectroscopy (SERS) effect to enhance the pH responsive spectrum of 4-mercaptobenzoic acid (MBA). However, the fibre background is still dominant. Using the photon arrival time-resolving capability of a CMOS single-photon avalanche diode (SPAD) based line sensor, we recover the SERS spectrum without a fibre background in a 10 s measurement. In this manner, pH sensing through a multimode fibre at a low excitation power that is safe for future in vivo applications, with short acquisition times (10 or 60 s), is demonstrated. A measurement precision of ± 0.07 pH units is thus achieved.

  3. A single-ended CMOS sensing circuit for MEMS gyroscope with noise cancellation

    KAUST Repository

    Elsayed, Mohannad Yomn

    2010-06-01

    In this work, a complete single-ended readout circuit for capacitive MEMS gyroscope using chopper stabilization technique is presented. A novel noise cancellation technique is used to get rid of the bias noise. The circuit offers superior performance over state of the art readout circuits in terms of cost, gain, and noise for the given area and power consumption. The full circuit exhibits a gain of 58dB, a power dissipation of 1.3mW and an input referred noise of 12nV/√Hz. This would significantly improve the overall sensitivity of the gyroscope. The full circuit has been fabricated in 0.6um CMOS technology and it occupies an area of 0.4mm × 1mm. © 2010 IEEE.

  4. A wide spectral range single-photon avalanche diode fabricated in an advanced 180 nm CMOS technology

    NARCIS (Netherlands)

    Mandai, S.; Fishburn, M.W.; Maruyama, Y.; Charbon, E.

    2012-01-01

    We present a single-photon avalanche diode (SPAD) with a wide spectral range fabricated in an advanced 180 nm CMOS process. The realized SPAD achieves 20 % photon detection probability (PDP) for wavelengths ranging from 440 nm to 820 nm at an excess bias of 4V, with 30 % PDP at wavelengths from 520

  5. A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems

    Directory of Open Access Journals (Sweden)

    Daehyeok Kim

    2017-06-01

    Full Text Available In this paper, we present a multi-resolution mode CMOS image sensor (CIS for intelligent surveillance system (ISS applications. A low column fixed-pattern noise (CFPN comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution with supply voltages of 3.3 V (analog and 1.8 V (digital and 14 frame/s of frame rates.

  6. AC signal characterization for optimization of a CMOS single-electron pump

    Science.gov (United States)

    Murray, Roy; Perron, Justin K.; Stewart, M. D., Jr.; Zimmerman, Neil M.

    2018-02-01

    Pumping single electrons at a set rate is being widely pursued as an electrical current standard. Semiconductor charge pumps have been pursued in a variety of modes, including single gate ratchet, a variety of 2-gate ratchet pumps, and 2-gate turnstiles. Whether pumping with one or two AC signals, lower error rates can result from better knowledge of the properties of the AC signal at the device. In this work, we operated a CMOS single-electron pump with a 2-gate ratchet style measurement and used the results to characterize and optimize our two AC signals. Fitting this data at various frequencies revealed both a difference in signal path length and attenuation between our two AC lines. Using this data, we corrected for the difference in signal path length and attenuation by applying an offset in both the phase and the amplitude at the signal generator. Operating the device as a turnstile while using the optimized parameters determined from the 2-gate ratchet measurement led to much flatter, more robust charge pumping plateaus. This method was useful in tuning our device up for optimal charge pumping, and may prove useful to the semiconductor quantum dot community to determine signal attenuation and path differences at the device.

  7. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  8. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  9. Numerical simulation study into the effect of a single heavy ion on a sub-micron CMOS device

    International Nuclear Information System (INIS)

    Detcheverry, C.; Lorfevre, E.; Bruguier, G.; Palau, J.M.; Gasiot, J.; Ecoffet, R.

    1997-01-01

    This article discusses coupling between the MEDICI component simulator and the SPICE circuit simulator to study single-event-upset phenomena caused by a single ion on a 0.6 μm CMOS device. Results conforming closely to experimental values were obtained by adopting an appropriate mesh size, a hydrodynamic charge transport model (rather than a diffusion-conduction model), and realistic simulation of photon-induced carrier generation, to accurately model the ion passage and trajectory. (authors)

  10. A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS

    Science.gov (United States)

    Yuxiao, Lu; Lu, Sun; Zhe, Li; Jianjun, Zhou

    2014-04-01

    This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 × 200 μm2 is occupied.

  11. Single InAs/GaSb nanowire low-power CMOS inverter.

    Science.gov (United States)

    Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

    2012-11-14

    III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

  12. A 0.18 {mu}m CMOS single-inductor single-stage quadrature frontend for GNSS receiver

    Energy Technology Data Exchange (ETDEWEB)

    Li Bing; Zhuang Yiqi; Han Yeqi; Xing Xiaoling; Li Zhenrong; Long Qiang, E-mail: waxmax@126.com [Key Laboratory of the Ministry of Education for Wide Bandgap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2011-09-15

    This paper presents an improved merged architecture for a low-IF GNSS receiver frontend, where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO. Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented. The gain plan and noise figure are discussed. The phase noise, quadrature accuracy and power consumption are improved. The test chip is fabricated though a 0.18 {mu}m RF CMOS process. The measured noise figure is 5.4 dB on average, with a gain of 43 dB and a IIP3 of -39 dBm. The measured phase noise is better than -105 dBc/Hz at 1 MHz offset. The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications. (semiconductor integrated circuits)

  13. Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

    Energy Technology Data Exchange (ETDEWEB)

    Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica; Tisa, Simone; Zappa, Franco [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

    2013-12-15

    We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

  14. A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

    Directory of Open Access Journals (Sweden)

    Chia-Hua Ho

    2012-03-01

    Full Text Available This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs in the conventional Complementary Metal-Oxide Semiconductor (CMOS-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH and sensitive deoxyribonucleic acid (DNA detection ability (100 pM at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window. The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  15. A CMOS-compatible poly-Si nanowire device with hybrid sensor/memory characteristics for System-on-Chip applications.

    Science.gov (United States)

    Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

    2012-01-01

    This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically V(th)-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady V(th) adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  16. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    KAUST Repository

    Nayak, Pradipta K.

    2014-04-14

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

  17. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    OpenAIRE

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2011-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and ...

  18. Effects of drain-wall in mitigating N-hit single event transient via 45 nm CMOS process

    International Nuclear Information System (INIS)

    Xu, X Y; Tang, M H; Xiao, Y G; Yan, S A; Zhang, W L; Li, Z; Xiong, Y; Zhao, W; Guo, H X

    2015-01-01

    A three-dimensional (3D) technology computer-aided design (TCAD) simulation in a novel layout technique for N-hit single event transient (SET) mitigation based on drain-wall layout technique is proposed. Numerical simulations of both single-device and mixed-mode show that the proposed layout technique designed with 45 nm CMOS process can efficiently reduce not only charge collection but also SET pulse widths (W SET ). What is more, simulations show that impacts caused by part of ion-incidents can be shielded with this novel layout technique. When compared with conventional layout technique and guard drain layout technique, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in effective area. (paper)

  19. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  20. Single-silicon CCD-CMOS platform for multi-spectral detection from terahertz to x-rays.

    Science.gov (United States)

    Shalaby, Mostafa; Vicario, Carlo; Hauri, Christoph P

    2017-11-15

    Charge-coupled devices (CCDs) are a well-established imaging technology in the visible and x-ray frequency ranges. However, the small quantum photon energies of terahertz radiation have hindered the use of this mature semiconductor technological platform in this frequency range, leaving terahertz imaging totally dependent on low-resolution bolometer technologies. Recently, it has been shown that silicon CCDs can detect terahertz photons at a high field, but the detection sensitivity is limited. Here we show that silicon, complementary metal-oxide-semiconductor (CMOS) technology offers enhanced detection sensitivity of almost two orders of magnitude, compared to CCDs. Our findings allow us to extend the low-frequency terahertz cutoff to less than 2 THz, nearly closing the technological gap with electronic imagers operating up to 1 THz. Furthermore, with the silicon CCD/CMOS technology being sensitive to mid-infrared (mid-IR) and the x-ray ranges, we introduce silicon as a single detector platform from 1 EHz to 2 THz. This overcomes the present challenge in spatially overlapping a terahertz/mid-IR pump and x-ray probe radiation at facilities such as free electron lasers, synchrotron, and laser-based x-ray sources.

  1. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR......In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 5 nV/√Hz. The amplifier power consumption is 275 μW....

  2. Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

    CERN Document Server

    Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

    2010-01-01

    We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

  3. Characterization of an industry-grade CMOS camera well suited for single molecule localization microscopy - high performance super-resolution at low cost.

    Science.gov (United States)

    Diekmann, Robin; Till, Katharina; Müller, Marcel; Simonis, Matthias; Schüttpelz, Mark; Huser, Thomas

    2017-10-31

    Many commercial as well as custom-built fluorescence microscopes use scientific-grade cameras that represent a substantial share of the instrument's cost. This holds particularly true for super-resolution localization microscopy where high demands are placed especially on the detector with respect to sensitivity, noise, and also image acquisition speed. Here, we present and carefully characterize an industry-grade CMOS camera as a cost-efficient alternative to commonly used scientific cameras. Direct experimental comparison of these two detector types shows widely similar performance for imaging by single molecule localization microscopy (SMLM). Furthermore, high image acquisition speeds are demonstrated for the CMOS detector by ultra-fast SMLM imaging.

  4. Compact laser radar based on a subnanosecond laser diode transmitter and a two-dimensional CMOS single-photon receiver

    Science.gov (United States)

    Huikari, Jaakko; Jahromi, Sahba; Jansson, Jussi-Pekka; Kostamovaara, Juha

    2018-02-01

    A pulsed TOF laser radar utilizing the single-photon detection mode has been implemented, and its performance is characterized. The transmitter employs a QW double-heterostructure laser diode producing 0.6 nJ/100 ps laser pulses at a central wavelength of ˜810 nm. The detector is a single-chip IC manufactured in the standard 0.35-μm HV CMOS process, including a 9×9 single-photon avalanche diode (SPAD) array and a 10-channel time-to-digital converter (TDC) circuit. Both the SPAD array and the TDC circuit support a time gating feature allowing photon detection to occur only within a predefined time window. The SPAD array also supports a 3×3 SPADs subarray selection feature to respond to the laser spot wandering effect due to the paraxial optics and to reduce background radiation-induced detections. The characterization results demonstrate a distance measurement accuracy of +/-0.5 mm to a target at 34 m having 11% reflectivity. The signal detection rate is 28% at a laser pulsing rate of 100 kHz. The single-shot precision of the laser radar is ˜20 mm (FWHM). The deteriorating impact of high-level background radiation conditions on the SNR is demonstrated, as also is a scheme to improve this by means of detector time gating.

  5. Poly-silicon quantum-dot single-electron transistors

    International Nuclear Information System (INIS)

    Kang, Kwon-Chil; Lee, Joung-Eob; Lee, Jung-Han; Lee, Jong-Ho; Shin, Hyung-Cheol; Park, Byung-Gook

    2012-01-01

    For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also, to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.

  6. Study of Single Event Effects induced by highly energetic charged particles of the space environment in CMOS image Sensors

    International Nuclear Information System (INIS)

    Lalucaa, Valerian

    2013-01-01

    This thesis studies the single event effects of space environment in CMOS image sensors (CIS). This work focuses on the effects of heavy ions on 3T standard photodiode pixels, and 4T and 5T pinned photodiode pixels. The first part describes the space radioactive environment and the sensor architecture. The most harmful events (SEL and SETs) are identified thanks to the scientific literature. The experimentally tested sensors agree with the theoretical work. SETs are compared to STARDUST simulations with a good agreement for all ions and sensors. The work explains why the SETs on 3T pixels are insensitive to the various photodiode designs, and they are decreased when an epitaxial substrate is used. A method using anti-blooming was successfully used in 4T and 5T pixels to prevent the spread of the SETs. The mechanism of latch-up in 4T pixel sensors is described. All the identified mechanisms are very useful to provide hardening methods for the CISs. (author) [fr

  7. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  8. Flexible ultrathin-body single-photon avalanche diode sensors and CMOS integration

    NARCIS (Netherlands)

    Sun, P.; Ishihara, R.; Charbon, E.

    2016-01-01

    We proposed the world’s first flexible ultrathin-body single-photon avalanche diode (SPAD) as photon counting device providing a suitable solution to advanced implantable bio-compatible chronic medical monitoring, diagnostics and other applications. In this paper, we investigate the Geiger-mode

  9. Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2013-08-01

    Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

  10. Frustration and single crystal morphology of isotactic poly(2-vinylpyridine)

    NARCIS (Netherlands)

    Okihara, T; Cartier, L; van Ekenstein, GORA; Lotz, B

    The crystal structure of isotactic poly(2-vinylpyridine) (iP2VP) established in 1977 by Puterman et al. is shown to conform to a recently proposed frustrated packing scheme which involves three isochiral three-fold helices packed in a trigonal unit-cell, and observed in a number of polymers and

  11. A novel offset cancellation based on parasitic-insensitive switched-capacitor sensing circuit for the out-of-plane single-Gimbaled decoupled CMOS-MEMS gyroscope.

    Science.gov (United States)

    Chang, Ming-Hui; Huang, Han-Pang

    2013-03-14

    This paper presents a novel parasitic-insensitive switched-capacitor (PISC) sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG). According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement.

  12. A Novel Offset Cancellation Based on Parasitic-Insensitive Switched-Capacitor Sensing Circuit for the Out-of-Plane Single-Gimbaled Decoupled CMOS-MEMS Gyroscope

    Science.gov (United States)

    Chang, Ming-Hui; Huang, Han-Pang

    2013-01-01

    This paper presents a novel parasitic-insensitive switched-capacitor (PISC) sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG). According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement. PMID:23493122

  13. Probing the cooperative nature of the conductive components in polystyrene/poly(3,4-ethylenedioxythiophene):Poly(styrene sulfonate)-single- walled carbon nanotube composites

    NARCIS (Netherlands)

    Hermant, M. -C; van der Schoot, P. P. A. M.; Klumperman, B.; Koning, C. E.

    2010-01-01

    The percolation threshold of single-walled carbon nanotubes (SWCNTs) introduced into polystyrene (PS) via a latex-based route has been reduced by using conductive surfactants. The use of the conductive polymeric latex, poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), in

  14. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  15. CCD and CMOS sensors

    Science.gov (United States)

    Waltham, Nick

    The charge-coupled device (CCD) has been developed primarily as a compact image sensor for consumer and industrial markets, but is now also the preeminent visible and ultraviolet wavelength image sensor in many fields of scientific research including space-science and both Earth and planetary remote sensing. Today"s scientific or science-grade CCD will strive to maximise pixel count, focal plane coverage, photon detection efficiency over the broadest spectral range and signal dynamic range whilst maintaining the lowest possible readout noise. The relatively recent emergence of complementary metal oxide semiconductor (CMOS) image sensor technology is arguably the most important development in solid-state imaging since the invention of the CCD. CMOS technology enables the integration on a single silicon chip of a large array of photodiode pixels alongside all of the ancillary electronics needed to address the array and digitise the resulting analogue video signal. Compared to the CCD, CMOS promises a more compact, lower mass, lower power and potentially more radiation tolerant camera.

  16. Grafting of Single, Stimuli-Responsive Poly(ferrocenylsilane) Polymer Chains to Gold Surfaces

    NARCIS (Netherlands)

    Zou, S(han); Ma, Y.; Hempenius, Mark A.; Schönherr, Holger; Vancso, Gyula J.

    2004-01-01

    Redox-responsive poly(ferrocenylsilane) (PFS) polymer molecules were attached individually to gold surfaces for force spectroscopy experiments on the single molecule level. By grafting ethylenesulfide-functionalized PFS into the defects of preformed self-assembled monolayers (SAMs) of different

  17. A 64 single photon avalanche diode array in 0.18 µm CMOS standard technology with versatile quenching circuit for quick prototyping

    Science.gov (United States)

    Uhring, Wilfried; Le Normand, Jean-Pierre; Zint, Virginie; Dumas, Norbert; Dadouche, Foudil; Malasse, Imane; Scholz, Jeremy

    2012-04-01

    Several works have demonstrated the successfully integration of Single-photon avalanche photodiodes (SPADs) operating in Geiger mode in a standard CMOS circuit for the last 10 years. These devices offer an exceptional temporal resolution as well as a very good optical sensitivity. Nevertheless, it is difficult to predict the expected performances of such a device. Indeed, for a similar structure of SPAD, some parameter values can differ by two orders of magnitude from a technology to another. We proposed here a procedure to identify in just one or two runs the optimal structure of SPAD available for a given technology. A circuit with an array of 64 SPAD has been realized in the Tower-Jazz 0.18 μm CMOS image sensor process. It encompasses an array of 8 different structures of SPAD reproduced in 8 diameters in the range from 5 μm up to 40 μm. According to the SPAD structures, efficient shallow trench insulator and/or P-Well guard ring are used for preventing edge breakdown. Low dark count rate of about 100 Hz are expected thanks to the use of buried n-well layer and a high resistivity substrate. Each photodiode is embedded in a pixel which includes a versatile quenching circuitry and an analog output of its cathode voltage. The quenching system is configurable in four operation modes; the SPAD is disabled, the quenching is completely passive, the reset of the photodiode is active and the quenching is fully active. The architecture of the array makes possible the characterization of every single photodiode individually. The parameters to be measured for a SPAD are the breakdown avalanche voltage, the dark count rate, the dead time, the timing jitter, the photon detection probability and the after-pulsing rate.

  18. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  19. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...... distortion is not achievable with CMOS current mirrors...

  20. Poly(vinylidene fluoride)-functionalized single-walled carbon nanotubes for the preparation of composites with improved conductivity

    NARCIS (Netherlands)

    Vukićević, R.; Vukovic, I.; Stoyanov, H.; Korwitz, A.; Pospiech, D.; Kofod, G.; Loos, K.; Brinke, G. ten; Beuermann, S.

    2012-01-01

    The surface of single-walled carbon nanotubes (SWCNTs) was functionalized with azide-terminated poly(vinylidene fluoride) (PVDF). Functionalization was confirmed by dispersibility, Raman spectroscopy, and thermogravimetric analyses. Raman spectra show disordering of the SWCNTs, thus, strongly

  1. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  2. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  3. Single-chip ring resonator-based 1 x 8 optical beam forming network in CMOS-compatible waveguide technology

    NARCIS (Netherlands)

    Zhuang, L.; Roeloffzen, C.G.H.; Heideman, Rene; Borreman, A.; Meijerink, Arjan; van Etten, Wim

    2007-01-01

    Optical ring resonators (ORRs) are good candidates to provide continuously tunable delay in optical beam forming networks (OBFNs) for phased array antenna systems. Delay and splitting/combining elements can be integrated on a single optical chip to form an OBFN. A state-of-the-art ring resonator-

  4. 25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

    Directory of Open Access Journals (Sweden)

    Sangyong Park

    2018-01-01

    Full Text Available This paper presents two single-pole, double-throw (SPDT mm-wave switches for Ka-band phased-array transceivers, fabricated with a 65-nm complementary metal oxide semiconductor (CMOS process. One switch employs cross-biasing (CB control with a single supply, while the other uses dual-supply biasing (DSB control with positive and negative voltages. Negative voltages were generated internally, using a ring oscillator and a charge pump. Identical gate and body floated N-type metal oxide semiconductor field effect transistors (N-MOSFETs in a triple well were used as the switch core transistors. Inductors were used to improve the isolation between the transmitter (TX and receiver (RX, as well as insertion loss, by canceling the parasitic capacitance of the switch core transistors at resonance. The size of the proposed radio frequency (RF switch is 260 μm × 230 μm, excluding all pads. The minimum insertion losses of the CB and DSB switches were 2.1 dB at 28 GHz and 1.93 dB at 24 GHz, respectively. Between 25 GHz and 34 GHz, the insertion losses were less than 2.3 dB and 2.5 dB, the return losses were less than 16.7 dB and 17.3 dB, and the isolation was over 18.4 dB and 15.3 dB, respectively. The third order input intercept points (IIP3 of the CB and DSB switches were 38.4 dBm and 39 dBm at 28 GHz, respectively.

  5. Interaction of Zn2+ Ions with Single-Stranded PolyU and PolyC in Neutral Solutions

    Czech Academy of Sciences Publication Activity Database

    Sorokin, V. A.; Usenko, E. L.; Valeev, V. A.; Berezniak, E. G.; Andrushchenko, Valery

    2015-01-01

    Roč. 119, č. 12 (2015), s. 4409-4416 ISSN 1520-6106 R&D Projects: GA ČR GAP208/11/0105; GA ČR GA15-09072S Institutional support: RVO:61388963 Keywords : metal ions * polyU * polyC * metallized DNA * differential UV spectroscopy * thermal denaturation * phase diagram Subject RIV: CF - Physical ; Theoretical Chemistry Impact factor: 3.187, year: 2015

  6. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    Science.gov (United States)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  7. Detection of single electrons by means of a Micromegas-covered Medi Pix2 pixel CMOS readout circuit

    CERN Document Server

    Campbell, Michael; Colas, Paul; Colijn, Auke Pieter; Fornaini, Alessandro; Giomataris, Ioanis; Heijne, Erik H M; Kluit, Peter; Llopart-Cudie, Xavier; Schmitz, Jurriaan; Timmermans, J; Visschers, Jan L; Van der Graaf, Harry

    2005-01-01

    A small drift chamber was read out by means of a MediPix2 readout chip as a direct anode. A Micromegas foil was placed 50 mu m above the chip, and electron multiplication occurred in the gap. With a He /isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90 %. We recorded many frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as delta -rays.

  8. Investigation of a new low cost and low consumption single poly-silicon memory

    Directory of Open Access Journals (Sweden)

    Patrick Calenzo

    2010-10-01

    Full Text Available In this paper is presented an investigation on a new low cost and voltage consumption single poly-silicon memory cell for passive RFID (Radio Frequency IDentificationapplications. This structure is low cost due to its single poly-silicon design. This memory cell has two particularities : the first one is that no deported capacitor is necessary to program this cell which allows to reduce the structure size to 1.1μm². The second one is the way the cell is erased. A Zener diode is used to generate carriers in order to be injected into the floating gate. This Zener diode is one of the key points for the functionality that has to be validated with some electrical trials. These trials permit to integrate and use the Zener diodes measured in simulations of the complete memory cell. This is done to validate the best candidate between the Zener diodes used for the cell and highlight the efficiency in consumption and rapidity to erase the cell. Besides, the writing and the reading cases are simulated in order to show the low consumption required by the cell during these phases.

  9. On the elastic properties of single-walled carbon nanotubes/poly(ethylene oxide) nanocomposites using molecular dynamics simulations.

    Science.gov (United States)

    Rouhi, S; Alizadeh, Y; Ansari, R

    2016-01-01

    Molecular dynamics simulations are used to study the physical and mechanical properties of single-walled carbon nanotubes/poly(ethylene oxide) nanocomposites. The effects of nanotube atomic structure, diameter, and volume fraction on the polymer density distribution, polymer atom distribution, stress-strain curves of nanocomposites and Young's, and shear moduli of single-walled carbon nanotubes/poly(ethylene oxide) nanocomposites are explored. It is shown that the density of polymer, surrounding the nanotube surface, has a peak near the nanotube surface. However, increasing distance leads to dropping it to the value near the density of pure polymer. It is seen that for armchair nanotubes, the average polymer atoms distances from the single-walled carbon nanotubes are larger than the polymer atom distance from zigzag nanotubes. It further is shown that zigzag nanotubes are better candidates to reinforce poly (ethylene oxide) than their armchair counterparts.

  10. Real-time fluorescence lifetime imaging system with a 32 × 32 0.13?m CMOS low dark-count single-photon avalanche diode array

    NARCIS (Netherlands)

    Li, D.U.; Arlt, J.; Richardson, J.; Walker, R.; Buts, A.; Stoppa, D.; Charbon, E.; Henderson, R.

    2010-01-01

    A compact real-time fluorescence lifetime imaging microscopy (FLIM) system based on an array of low dark count 0.13?m CMOS singlephoton avalanche diodes (SPADs) is demonstrated. Fast background-insensitive fluorescence lifetime determination is achieved by use of a recently proposed algorithm called

  11. A microfluidic approach to fabricate monodisperse hollow or porous poly(HEMA-MMA) microspheres using single emulsions as templates.

    Science.gov (United States)

    Zhang, Hao; Ju, Xiao-Jie; Xie, Rui; Cheng, Chang-Jing; Ren, Ping-Wei; Chu, Liang-Yin

    2009-08-01

    We have successfully developed a novel and simple method to controllably prepare monodisperse poly(hydroxyethyl methacrylate-methyl methacrylate) (poly(HEMA-MMA)) microspheres with two distinct structures using single emulsions as templates. By employing a microfluidic emulsification approach to fabricate monomer-contained oil-in-water (O/W) emulsions as templates, and introducing proper initiators and different types of porogens, poly(HEMA-MMA) microspheres with hollow or porous structure are prepared in a controllable way. The shell thickness of hollow microspheres or the porosity of porous microspheres is controllably achieved by simply adjusting the porogen concentration. The prepared poly(HEMA-MMA) microspheres with controllable hollow or porous structures are favored for various potential applications. Furthermore, by using the simple preparation methodology proposed in this study, fabrication of monodisperse porous microspheres or hollow microcapsules with other materials can also be easily achieved.

  12. Scattering Study of Conductive-Dielectric Nano/Micro-Grained Single Crystals Based on Poly(ethylene glycol, Poly(3-hexyl thiophene and Polyaniline

    Directory of Open Access Journals (Sweden)

    Samira Agbolaghi

    2017-12-01

    Full Text Available Two types of rod-coil block copolymers including poly(3-hexylthiophene-block-poly(ethylene glycol (P3HT-b-PEG and PEG-block-polyaniline (PANI were synthesized using Grignard metathesis polymerization, Suzuki coupling, and interfacial polymerization. Afterward, two types of single crystals were grown by self-seeding methodology to investigate the coily and rod blocks in grafted brushes and ordered crystalline configurations. The conductive P3HT fibrillar single crystals covered by the dielectric coily PEG oligomers were grown from toluene, xylene, and anisole, and characterized by atomic force microscopy (AFM and grazing wide angle X-ray scattering (GIWAXS. Longer P3HT backbones resulted in folding, whereas shorter ones had a high tendency towards backbone lamination. The effective factors on folding of long P3HT backbones in the single crystal structures were the solvent quality and crystallization temperature. Better solvents due to decelerating the growth condition led to a higher number of foldings. Via increasing the crystallization temperature, the system decreased the folding number to maintain its stability. Poorer solvents also reflected a higher stacking in hexyl side chain and π-π stacking directions. The dielectric lamellar PEG single crystals sandwiched between the PANI nanorods were grown from amyl acetate, and analyzed using the interface distribution function (IDF of SAXS and AFM. The molecular weights of PANI and PEG blocks and crystallization temperature were focused while studying the grown single crystals.

  13. Crystallization behavior of single isotactic poly(methyl methacrylate) chains visualized by atomic force microscopy.

    Science.gov (United States)

    Anzai, Takahiro; Kawauchi, Mariko; Kawauchi, Takehiro; Kumaki, Jiro

    2015-01-08

    We have, for the first time, successfully visualized the crystallization behavior of a single isolated polymer chain at the molecular level by atomic force microscopy (AFM). Previously, we found that isotactic poly(methyl methacrylate) (it-PMMA) formed two-dimensional folded chain crystals composed of double-stranded helices upon compression of its Langmuir monolayer on a water surface, and the molecular images of the crystals deposited on mica were clearly visualized by AFM (Kumaki, J.; et al. J. Am. Chem. Soc. 2005, 127, 5788). In the present study, a high-molecular-weight it-PMMA was diluted in a monolayer of an it-PMMA oligomer which cannot crystallize at the experimental temperature due to its low molecular weight. At a low surface pressure, isolated amorphous chains of the high-molecular-weight it-PMMA solubilized in the oligomer monolayer were observed. On compression, the isolated chains converted to crystals composed of a single chain, typically some small crystallites linked by an amorphous chain like a necklace. Detailed AFM observations of the crystals indicated that the crystalline nuclei preferentially formed at the ends of the chains, and the size of the nuclei was almost independent of the molecular weight of it-PMMA over a wide range. At an extremely slow compression, crystallization was promoted, resulting in crystallization of the whole chain. The crystallization behavior of a single isolated chain provides new insights in understanding the polymer crystallization process.

  14. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  15. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  16. Mass transfer ranking of polylysine, poly-ornithine and poly-methylene-co-guanidine microcapsule membranes using a single low molecular mass marker

    Directory of Open Access Journals (Sweden)

    Rosinski Stefan

    2003-01-01

    Full Text Available On the long way to clinical transplantable hybrid systems, comprising of cells, acting as immuno-protected bioreactors microencapsulated in a polymeric matrix and delivering desired factors (proteins, hormones, enzymes etc to the patient's body, an important step is the optimization of the microcapsule. This topic includes the selection of a proper coating membrane which could fulfil, first of all, the mass transfer as well as biocompatibility, stability and durability requirements. Three different membranes from polymerised aminoacids, formed around exactly identical alginate gel cores, were considered, concerning their mass transport properties, as potential candidates in this task. The results of the evaluation of the mass ingress and mass transfer coefficient h for the selected low molecular mass marker, vitamin B12, in poly-L-lysine (HPLL poly-L-ornithine (HPLO and poly-methylene-co-guanidine hydrochloride (HPMCG membrane alginate microcapsules demonstrate the advantage of using the mass transfer approach to a preliminary screening of various microcapsule formulations. Applying a single marker and evaluating mass transfer coefficients can help to quickly rank the investigated membranes and microcapsules according to their permeability. It has been demonstrated that HPLL, HPLO and HPMCG microcapsules differ from each other by a factor of two concerning the rate of low molecular mass marker transport. Interesting differences in mass transfer through the membrane in both directions in-out was also found, which could possibly be related to the membrane asymmetry.

  17. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  18. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  19. Single-Chain Conformation for Interacting Poly(N-isopropylacrylamide in Aqueous Solution

    Directory of Open Access Journals (Sweden)

    Boualem Hammouda

    2015-04-01

    Full Text Available The demixing phase behavior of Poly(N-isopropylacrylamide (PNIPAM aqueous solution is investigated using small-angle neutron scattering. This polymer phase separates upon heating and demixes around 32 °C. The pre-transition temperature range is characterized by two scattering modes; a low-Q (large-scale signal and a high-Q dissolved chains signal. In order to get insight into this pre-transition region, especially the origin of the low-Q (large-scale structure, the zero average contrast method is used in order to isolate single-chain conformations even in the demixing polymers transition region. This method consists of measuring deuterated and non-deuterated polymers dissolved in mixtures of deuterated and non-deuterated water for which the polymer scattering length density matches the solvent scattering length density. A fixed 4% polymer mass fraction is used in a contrast variation series where the d-water/h-water fraction is varied in order to determine the match point. The zero average contrast (match point sample displays pure single-chain scattering with no interchain contributions. Our measurements prove that the large scale structure in this polymer solution is due to a transient polymer network formed through hydrophobic segment-segment interactions. Scattering intensity increases when the temperature gets close to the phase boundary. While the apparent radius of gyration increases substantially at the Lower Critical Solution Temperature (LCST transition due to strong interchain correlation, the single-chain true radius of gyration has been found to decrease slightly with temperature when approaching the transition.

  20. Poly(ethylene oxide) Crystallization in Single Walled Carbon Nanotube Based Nanocomposites: Kinetics and Structural Consequences

    Energy Technology Data Exchange (ETDEWEB)

    T Chatterjee; A Lorenzo; R Krishnamoorti

    2011-12-31

    The overall isothermal crystallization behavior of poly(ethylene oxide) (PEO) in single walled carbon nanotube (SWNT) based nanocomposites is studied with a focus on growth kinetics and morphological evolution of PEO using differential scanning calorimetry and in-situ small angle x-ray scattering measurements respectively. The characteristic time for crystallization of PEO increases due to the presence of lithium dodecyl sulfate (LDS) stabilized carbon nanotubes. Further, analysis of crystallization data using the Lauritzen-Hoffman regime theory of crystal growth shows the PEO chains stiffen in presence of LDS with an increased energy barrier associated with the nucleation and crystal growth, and the nanotubes further act as a barrier to chain transport or enhance the efficacy of the LDS action. The energy penalty and diffusional barrier to chain transport in the nanocomposites disrupt the crystalline PEO helical conformation. This destabilization leads to preferential growth of local nuclei resulting in formation of thinner crystal lamellae and suggests that the crystallization kinetics is strongly affected by the nucleation and crystal growth events. This study is particularly interesting considering the suppression of the PEO crystallinity in presence of small fraction of Lithium ion based surfactant and carbon nanotubes.

  1. PolyMUMPs MEMS device to measure mechanical stiffness of single cells in aqueous media

    Science.gov (United States)

    Warnat, S.; King, H.; Forbrigger, C.; Hubbard, T.

    2015-02-01

    A method of experimentally determining the mechanical stiffness of single cells by using differential displacement measurements in a two stage spring system is presented. The spring system consists of a known MEMS reference spring and an unknown cellular stiffness: the ratio of displacements is related to the ratio of stiffness. A polyMUMPs implementation for aqueous media is presented and displacement measurements made from optical microphotographs using a FFT based displacement method with a repeatability of ~20 nm. The approach was first validated on a MEMS two stage spring system of known stiffness. The measured stiffness ratios of control structures (i) MEMS spring systems and (ii) polystyrene microspheres were found to agree with theoretical values. Mechanical tests were then performed on Saccharomyces cerevisiae (Baker’s yeast) in aqueous media. Cells were placed (using a micropipette) inside MEMS measuring structures and compressed between two jaws using an electrostatic actuator and displacements measured. Tested cells showed stiffness values between 5.4 and 8.4 N m-1 with an uncertainty of 11%. In addition, non-viable cells were tested by exposing viable cells to methanol. The resultant mean cell stiffness dropped by factor of 3 × and an explicit discrimination between viable and non-viable cells based on mechanical stiffness was seen.

  2. Integrated tunable CMOS laser.

    Science.gov (United States)

    Creazzo, Timothy; Marchena, Elton; Krasulick, Stephen B; Yu, Paul K L; Van Orden, Derek; Spann, John Y; Blivin, Christopher C; He, Lina; Cai, Hong; Dallesasse, John M; Stone, Robert J; Mizrahi, Amit

    2013-11-18

    An integrated tunable CMOS laser for silicon photonics, operating at the C-band, and fabricated in a commercial CMOS foundry is presented. The III-V gain medium section is embedded in the silicon chip, and is hermetically sealed. The gain section is metal bonded to the silicon substrate creating low thermal resistance into the substrate and avoiding lattice mismatch problems. Optical characterization shows high performance in terms of side mode suppression ratio, relative intensity noise, and linewidth that is narrow enough for coherent communications.

  3. Selective binding and reverse transcription inhibition of single-strand poly(A) RNA by metal TMPyP complexes.

    Science.gov (United States)

    Zhou, Zhu-Xin; Gao, Feng; Chen, Xing; Tian, Xiang-Jing; Ji, Liang-Nian

    2014-10-06

    Ni-, Cu-, and Zn-TMPyP are capable of binding to single-strand poly(A) RNA with high preference and affinity and inhibiting the reverse transcription of RNA by both M-MuLV and HIV-1 reverse transcriptase. With 10 nM azidothymidine, the IC50 value of M-TMPyP could be lowered to 10(-1) μM order.

  4. RF CMOS reliability simulations

    NARCIS (Netherlands)

    Sasse, G.T.; Acar, M.; Kuper, F.G.; Schmitz, Jurriaan

    2008-01-01

    We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events.

  5. Hyperspectral CMOS imager

    Science.gov (United States)

    Jerram, P. A.; Fryer, M.; Pratlong, J.; Pike, A.; Walker, A.; Dierickx, B.; Dupont, B.; Defernez, A.

    2017-11-01

    CCDs have been used for many years for Hyperspectral imaging missions and have been extremely successful. These include the Medium Resolution Imaging Spectrometer (MERIS) [1] on Envisat, the Compact High Resolution Imaging Spectrometer (CHRIS) on Proba and the Ozone Monitoring Instrument operating in the UV spectral region. ESA are also planning a number of further missions that are likely to use CCD technology (Sentinel 3, 4 and 5). However CMOS sensors have a number of advantages which means that they will probably be used for hyperspectral applications in the longer term. There are two main advantages with CMOS sensors: First a hyperspectral image consists of spectral lines with a large difference in intensity; in a frame transfer CCD the faint spectral lines have to be transferred through the part of the imager illuminated by intense lines. This can lead to cross-talk and whilst this problem can be reduced by the use of split frame transfer and faster line rates CMOS sensors do not require a frame transfer and hence inherently will not suffer from this problem. Second, with a CMOS sensor the intense spectral lines can be read multiple times within a frame to give a significant increase in dynamic range. We will describe the design, and initial test of a CMOS sensor for use in hyperspectral applications. This device has been designed to give as high a dynamic range as possible with minimum cross-talk. The sensor has been manufactured on high resistivity epitaxial silicon wafers and is be back-thinned and left relatively thick in order to obtain the maximum quantum efficiency across the entire spectral range

  6. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  7. Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

    Science.gov (United States)

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

    2012-01-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

  8. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  9. Local piezoelectric activity of single poly(L-lactic acid) (PLLA) microfibers

    Science.gov (United States)

    Sencadas, V.; Ribeiro, C.; Heredia, A.; Bdikin, I. K.; Kholkin, A. L.; Lanceros-Mendez, S.

    2012-10-01

    Local piezoelectric properties of the poly(L-lactic acid) individual electrospun fibers have been studied by Piezoresponse Force Microscopy. Piezoelectric response, polarization switching, and nanoscale patterning of the fibers have been demonstrated in this important biomaterial, thus opening interesting possibilities for tissue engineering and sensing/actuating applications.

  10. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  11. Surface Adsorption and Replacement of Acid-Oxidized Single-Walled Carbon Nanotubes and Poly(vinyl pyrrolidone Chains

    Directory of Open Access Journals (Sweden)

    Wei Chen

    2007-01-01

    Full Text Available Quartz crystal microbalance (QCM was used to investigate the adsorption of acid-oxidized single-walled carbon nanotubes (Ox-SWNTs and poly(vinyl pyrrolidone, PVP. It was found for the first time that Ox-SWNTs adsorbed onto the QCM electrode can be effectively replaced by PVP chains in an aqueous solution. This replacement process was also investigated by atomic force miscroscopic (AFM imaging, which shows good agreement with the QCM measurements. This study provides powerful tools for fundamental investigation of polymer-nanotube interactions and for controlled design/fabrication of functional polymer-nanotube surfaces for potential applications.

  12. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process †

    Science.gov (United States)

    Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

    2018-01-01

    To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach. PMID:29329210

  13. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process.

    Science.gov (United States)

    Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

    2018-01-12

    To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke - . Readout noise under the highest pixel gain condition is 1 e - with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7", 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach.

  14. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process

    Directory of Open Access Journals (Sweden)

    Isao Takayanagi

    2018-01-01

    Full Text Available To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR approach.

  15. Single-ion triblock copolymer electrolytes based on poly(ethylene oxide) and methacrylic sulfonamide blocks for lithium metal batteries

    Science.gov (United States)

    Porcarelli, Luca; Aboudzadeh, M. Ali; Rubatat, Laurent; Nair, Jijeesh R.; Shaplov, Alexander S.; Gerbaldi, Claudio; Mecerreyes, David

    2017-10-01

    Single-ion conducting polymer electrolytes represent the ideal solution to reduce concentration polarization in lithium metal batteries (LMBs). This paper reports on the synthesis and characterization of single-ion ABA triblock copolymer electrolytes comprising PEO and poly(lithium 1-[3-(methacryloyloxy)propylsulfonyl]-1-(trifluoromethylsulfonyl)imide) blocks, poly(LiMTFSI). Block copolymers are prepared by reversible addition-fragmentation chain transfer polymerization, showing low glass transition temperature (-55 to 7 °C) and degree of crystallinity (51-0%). Comparatively high values of ionic conductivity are obtained (up to ≈ 10-4 S cm-1 at 70 °C), combined with a lithium-ion transference number close to unity (tLi+ ≈ 0.91) and a 4 V electrochemical stability window. In addition to these promising features, solid polymer electrolytes are successfully tested in lithium metal cells at 70 °C providing long lifetime up to 300 cycles, and stable charge/discharge cycling at C/2 (≈100 mAh g-1).

  16. Fabrication of single walled carbon nanotubes/poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) layers under enhanced gravity drying

    International Nuclear Information System (INIS)

    Rincón, M.E.; Alvarado-Tenorio, G.; Vargas, M.G.; Ramos, E.; Sánchez-Tizapa, M.

    2015-01-01

    In this contribution, we explore the use of enhanced gravity in order to achieve composite films of single walled carbon nanotubes (SWCNTs)/poly(3,4-ethylenedioxythiophene):polystyrenesulfonate (PEDOT:PSS) with improved properties. The samples were characterized by atomic force microscopy, scanning electron microscopy, and electrochemical impedance spectroscopy, in order to determine the differences caused by the enhanced gravity. Impedance spectroscopy results show that there is an improvement of the electrical properties of the SWCNT/PEDOT:PSS junction, manifested as lower contact resistance, modified chemical capacitance, and induced p-type doping. A force-induced interpenetration of the polymer into the SWCNT network and the efficient removal of water and PSS are proposed to explain the results. The transparency and electrical properties of these films forecast their application as a buffer layer in organic solar cell heterojunctions, or as hole transporting materials in perovskite-based solar cells. - Highlights: • A technique to fabricate conductive films of SWCNT/PEDOT:PSS is presented. • The technique is based on enhanced gravity drying. • Improved interpenetration of the bilayer SWCNT/PEDOT:PSS system • Enhanced gravity increases the p-type conductivity of the film. • Impedance spectroscopy confirms the improvement on the electrical properties.

  17. A single-walled carbon nanotubes/poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate)/copper hexacyanoferrate hybrid film for high-volumetric performance flexible supercapacitors

    Science.gov (United States)

    Li, Jianmin; Li, Haizeng; Li, Jiahui; Wu, Guiqing; Shao, Yuanlong; Li, Yaogang; Zhang, Qinghong; Wang, Hongzhi

    2018-05-01

    Volumetric energy density is generally considered to be detrimental to the actual application of supercapacitors, which has provoked a range of research work on increasing the packing density of electrodes. Herein, we fabricate a free-standing single-walled carbon nanotubes (SWCNTs)/poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS)/copper hexacyanoferrate (CuHCF) nanoparticles (NPs) composite supercapacitor electrode, with a high packing density of 2.67 g cm-3. The pseudocapacitive CuHCF NPs are decorated onto the SWCNTs/PEDOT:PSS networks and filled in interspace to increase both of packing density and specific capacitance. This hybrid electrode exhibits a series of outstanding performances, such as high electric conductivity, ultrahigh areal and volumetric capacitances (969.8 mF cm-2 and 775.2 F cm-3 at scan rate of 5 mV s-1), long cycle life and superior rate capability. The asymmetric supercapacitor built by using the SWCNTs/PEDOT:PSS/CuHCF film as positive electrode and Mo-doped WO3/SWCNTs film as negative electrode, can deliver a high energy density of 30.08 Wh L-1 with a power density of 4.25 kW L-1 based on the total volume of the device. The approach unveiled in this study could provide important insights to improving the volumetric performance of energy storage devices and help to reach the critical targets for high rate and high power density demand applications.

  18. Fabrication of single walled carbon nanotubes/poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) layers under enhanced gravity drying

    Energy Technology Data Exchange (ETDEWEB)

    Rincón, M.E.; Alvarado-Tenorio, G. [Instituto de Energías Renovables, Universidad Nacional Autónoma de México, Apartado Postal 34, 62580 Temixco, Mor. (Mexico); Vargas, M.G. [Instituto Tecnológico de Zacatepec, Calzada Tecnológico 27, 62780 Zacatepec, Mor. (Mexico); Ramos, E. [Instituto de Energías Renovables, Universidad Nacional Autónoma de México, Apartado Postal 34, 62580 Temixco, Mor. (Mexico); Sánchez-Tizapa, M., E-mail: msanchez@valles.udg.mx [Centro Universitario de los Valles, Universidad de Guadalajara, Carretera Guadalajara-Ameca, Km 45.5, C.P. 46600, Ameca, Jalisco (Mexico)

    2015-12-31

    In this contribution, we explore the use of enhanced gravity in order to achieve composite films of single walled carbon nanotubes (SWCNTs)/poly(3,4-ethylenedioxythiophene):polystyrenesulfonate (PEDOT:PSS) with improved properties. The samples were characterized by atomic force microscopy, scanning electron microscopy, and electrochemical impedance spectroscopy, in order to determine the differences caused by the enhanced gravity. Impedance spectroscopy results show that there is an improvement of the electrical properties of the SWCNT/PEDOT:PSS junction, manifested as lower contact resistance, modified chemical capacitance, and induced p-type doping. A force-induced interpenetration of the polymer into the SWCNT network and the efficient removal of water and PSS are proposed to explain the results. The transparency and electrical properties of these films forecast their application as a buffer layer in organic solar cell heterojunctions, or as hole transporting materials in perovskite-based solar cells. - Highlights: • A technique to fabricate conductive films of SWCNT/PEDOT:PSS is presented. • The technique is based on enhanced gravity drying. • Improved interpenetration of the bilayer SWCNT/PEDOT:PSS system • Enhanced gravity increases the p-type conductivity of the film. • Impedance spectroscopy confirms the improvement on the electrical properties.

  19. Poly(acrylic acid)-directed synthesis of colloidally stable single domain magnetite nanoparticles via partial oxidation

    Energy Technology Data Exchange (ETDEWEB)

    Altan, Cem L. [Department of Chemical Engineering, Yeditepe University, Istanbul 34755 (Turkey); Laboratory of Materials and Interface Chemistry & Soft Matter cryoTEM Research Unit, Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, Eindhoven 5600 MB (Netherlands); Gurten, Berna [Department of Chemical Engineering, Yeditepe University, Istanbul 34755 (Turkey); Sadza, Roel [Laboratory of Materials and Interface Chemistry & Soft Matter cryoTEM Research Unit, Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, Eindhoven 5600 MB (Netherlands); Yenigul, Elcin [Department of Chemical Engineering, Yeditepe University, Istanbul 34755 (Turkey); Sommerdijk, Nico A.J.M., E-mail: n.sommerdijk@tue.nl [Laboratory of Materials and Interface Chemistry & Soft Matter cryoTEM Research Unit, Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, Eindhoven 5600 MB (Netherlands); Institute for Complex Molecular Systems, Eindhoven University of Technology, Eindhoven 5600 MB (Netherlands); Bucak, Seyda, E-mail: seyda@yeditepe.edu.tr [Department of Chemical Engineering, Yeditepe University, Istanbul 34755 (Turkey)

    2016-10-15

    Octahedral, single domain magnetite nanoparticles with average size of ~55 nm were synthesized through oxidative aging of a ferrous hydroxide (Fe(OH){sub 2}) precursor at high pH in water. The synthesis was also carried out in the presence of the hydrophilic polymer poly(acrylic acid). Presence of the polymer changed the particle morphology from octahedral to spherical while average size decreased to 40–50 nm. Although these particles have a tendency to precipitate due to their high magnetic moment, dispersions of these particles were obtained in the presence of this particular polymer which made the particles stable in water for several days making them suitable for various biotechnological applications such as cell separation owing to their low toxicity. - Highlights: • Stable, single domain magnetite nanoparticles are synthesized via partial oxidation. • Particles are readily stabilized in water by a biocompatible polymer. • Steric barrier is essential for the stabilization of large magnetite nanoparticles.

  20. Regio-Regular Oligo and Poly(3-hexyl thiophene): Precise Structural Markers from the Vibrational Spectra of Oligomer Single Crystals.

    KAUST Repository

    Brambilla, Luigi

    2014-10-14

    © 2014 American Chemical Society. In this work, we report a comparative analysis of the infrared and Raman spectra of octa(3-hexylthiophene) (3HT)8, trideca(3-hexylthiophene) (3HT)13, and poly(3-hexylthiophene) P3HT recorded in various phases, namely, amorphous, semicrystalline, polycrystalline and single crystal. We have based our analysis on the spectra of the (3HT)8 single crystal (whose structure has been determined by selected area electron diffraction) taken as reference and on the results of DFT calculations and molecular vibrational dynamics. New and precise spectroscopic markers of the molecular structures show the existence of three phases, namely: hairy (phase 1), ordered (phase 2), and disordered/amorphous (phase 3). Conceptually, the identified markers can be used for the molecular structure analysis of other similar systems.

  1. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  2. Video-rate fluorescence lifetime imaging camera with CMOS single-photon avalanche diode arrays and high-speed imaging algorithm

    NARCIS (Netherlands)

    Li, D.D.U.; Arlt, J.; Tyndall, D.; Walker, R.; Richardson, J.; Stoppa, D.; Charbon, E.; Henderson, R.K.

    2011-01-01

    A high-speed and hardware-only algorithm using a center of mass method has been proposed for single-detector fluorescence lifetime sensing applications. This algorithm is now implemented on a field programmable gate array to provide fast lifetime estimates from a 32 × 32 low dark count 0.13 ?m

  3. Probing the Kinetic Anabolism of Poly-Beta-Hydroxybutyrate in Cupriavidus necator H16 Using Single-Cell Raman Spectroscopy

    Directory of Open Access Journals (Sweden)

    Zhanhua Tao

    2016-08-01

    Full Text Available Poly-beta-hydroxybutyrate (PHB can be formed in large amounts in Cupriavidus necator and is important for the industrial production of biodegradable plastics. In this investigation, laser tweezers Raman spectroscopy (LTRS was used to characterize dynamic changes in PHB content—as well as in the contents of other common biomolecule—in C. necator during batch growth at both the population and single-cell levels. PHB accumulation began in the early stages of bacterial growth, and the maximum PHB production rate occurred in the early and middle exponential phases. The active biosynthesis of DNA, RNA, and proteins occurred in the lag and early exponential phases, whereas the levels of these molecules decreased continuously during the remaining fermentation process until the minimum values were reached. The PHB content inside single cells was relatively homogenous in the middle stage of fermentation; during the late growth stage, the variation in PHB levels between cells increased. In addition, bacterial cells in various growth phases could be clearly discriminated when principle component analysis was performed on the spectral data. These results suggest that LTRS is a valuable single-cell analysis tool that can provide more comprehensive information about the physiological state of a growing microbial population.

  4. Highly Sensitive Ammonia Gas Sensor Based on Single-Crystal Poly(3-hexylthiophene) (P3HT) Organic Field Effect Transistor.

    Science.gov (United States)

    Mun, Seohyun; Park, Yoonkyung; Lee, Yong-Eun Koo; Sung, Myung Mo

    2017-11-28

    A highly sensitive organic field-effect transistor (OFET)-based sensor for ammonia in the range of 0.01 to 25 ppm was developed. The sensor was fabricated by employing an array of single-crystal poly(3-hexylthiophene) (P3HT) nanowires as the organic semiconductor (OSC) layer of an OFET with a top-contact geometry. The electrical characteristics (field-effect mobility, on/off current ratio) of the single-crystal P3HT nanowire OFET were about 2 orders of magnitude larger than those of the P3HT thin film OFET with the same geometry. The P3HT nanowire OFET showed excellent sensitivity to ammonia, about 3 times higher than that of the P3HT thin film OFET at 25 ppm ammonia. The ammonia response of the OFET was reversible and was not affected by changes in relative humidity from 45 to 100%. The high ammonia sensitivity of the P3HT nanowire OFET is believed to result from the single crystal nature and high surface/volume ratio of the P3HT nanowire used in the OSC layer.

  5. Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

    Science.gov (United States)

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

    2011-12-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

  6. An inductorless CMOS realization of Chua's circuit

    CERN Document Server

    Radwan, A G; El-Sedeek, A L

    2003-01-01

    In this paper, an inductorless CMOS realization of Chua's circuit [IEEE Trans. Circ. Syst.--I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua's circuit and can generate Rossler or double-scroll attractors by changing a single capacitor's value. Variables are represented in the current domain to facilitate adding or subtracting variables. New G sub m -C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as +-1.5 V. Transistor-level simulation results using PSpice in 0.5 mu m Mietec process are presented.

  7. Modular high-performance 2-μm CCD-BiCMOS process technology for application-specific image sensors and image sensor systems on a chip

    Science.gov (United States)

    Guidash, R. Michael; Lee, P. P. K.; Andrus, J. M.; Ciccarelli, Antonio S.; Erhardt, H. J.; Fischer, J. R.; Meisenzahl, Eric J.; Philbrick, Robert H.; Kenney, Timothy J.

    1995-04-01

    A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.

  8. Electrochemical characterization of mixed self-assembled films of water-soluble single-walled carbon nanotube-poly(m-aminobenzene sulfonic acid) and Iron(II) tetrasulfophthalocyanine

    CSIR Research Space (South Africa)

    Agboola, BO

    2010-09-01

    Full Text Available The redox activities of water-soluble iron(II) tetrasulfophthalocyanine (FeTSPc) and single-walled carbon nanotube-poly(m-aminobenzene sulfonic acid) (SWCNT-PABS) adsorbed on a gold surface precoated with a self-assembled monolayer (SAM) of 2...

  9. Single step natural poly(tannic acid) particle preparation as multitalented biomaterial.

    Science.gov (United States)

    Sahiner, Nurettin; Sagbas, Selin; Aktas, Nahit

    2015-04-01

    In this study, we report the preparation of poly(tannic acid) (p(TA)) particles by crosslinking with glycerol diglycidyl ether (GDE) and trimethylolpropane triglycidyl ether (TMPGDE). The p(TA) particles are negatively charged as obtained by the zeta potential measurements, -27mV. P(TA) particles are found to be an effective antioxidant material as 170mgL(-1) of p(TA) particle demonstrated the antioxidant equivalency of 82.5±7.2mgL(-1) of gallic acid (GA), used as standard in Folin-Ciocalteau (FC) method. Additionally, TA and p(TA) particles have a strong antimicrobial effect against Escherichia coli ATCC 8739, Staphylococcus aureus ATCC 6538, and Bacillus subtilis ATCC 6633. Furthermore, p(TA) particles were used as drug delivery materials by using model drugs such as TA itself, and GA in the release studies in PBS at pH7.4 at 37.5°C, and found that p(TA) particles can release 80.8 and 87.4% of the loaded TA and GA, respectively. Interestingly, p(TA) maintained its fluorescent property upon crosslinking of TA units. It is further demonstrated that p(TA) particles are as effective as cisplatin (a cancer drug) against A549 cancerous cells that both showed about 36 and 34% cell viability, respectively whereas linear TA showed 66% cell viability at 37.5μgmL(-1) concentration. Above this concentration p(TA) and cisplatin showed almost the same toxicity against A549 cancerous cells. Additionally, p(TA) particles are found to be much more biocompatible against L929 Fibroblast cells, about 84% cell viability in comparison to linear TA with about 53% at 75μgmL(-1) concentration. Copyright © 2015 Elsevier B.V. All rights reserved.

  10. CMOS IMAGING SENSOR TECHNOLOGY FOR AERIAL MAPPING CAMERAS

    Directory of Open Access Journals (Sweden)

    K. Neumann

    2016-06-01

    Full Text Available In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  11. Dynamic encapsulation of hydrophilic nisin in hydrophobic poly (lactic acid) particles with controlled morphology by a single emulsion process.

    Science.gov (United States)

    Ji, Shaowen; Lu, Jue; Liu, Zhiguo; Srivastava, Devesh; Song, Anna; Liu, Yan; Lee, Ilsoon

    2014-06-01

    Hydrophilic nisin-loaded hydrophobic poly (lactic acid) (PLA) particles with controlled size and shape were successfully produced utilizing a one-step single emulsification method. Preliminary shear stress and temperature tests showed that there was no significant loss in the nisin inhibition activity during this process. PLA/nisin composite particles were prepared into solid nanocomposite spheres (50-200 nm) or hollow microcomposite spheres (1-5 μm) under the operative conditions developed in our previous study, in which the hydrophilic nisin in the aqueous phase solution could be entrapped in the hydrophobic polymer in the emulsification process generating either single or multiple emulsions. The incorporation of nisin in PLA had little effect on key processing conditions, which allows the dynamic control of the morphology and property of resulting particles. Microscopic and surface analyses suggested that nisin was dispersed uniformly inside the polymer matrix and adsorbed on the particle surface. The encapsulation amount and efficiency were enhanced with the increase in nisin loading in the aqueous solution. Unique reversible control of particle size and shape by this process was successfully applied in the nisin encapsulation. Alternating temperature in the repeating emulsification steps improved the encapsulation efficiency while generated particles in desired size and shape. Copyright © 2014 Elsevier Inc. All rights reserved.

  12. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  13. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    Science.gov (United States)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; hide

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  14. The power conversion efficiency of visible light emitting devices in standard BiCMOS processes

    NARCIS (Netherlands)

    Kuindersma, P.; Hoang, T.; Schmitz, Jurriaan; Vijayaraghavan, M.N.; Dijkstra, Mindert; Dijkstra, M.; van Noort, W.A.; Vanhoucke, T.; Peters, W.C.M.; Kramer, M.C.J.C.M.

    2008-01-01

    We present experimental and theoretical proof for a single and unique relationship between the breakdown voltage and power efficiency of visible light emitting devices fabricated in standard BiCMOS processes.

  15. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  16. Accuracy of Motor Axon Regeneration Across Autograft, Single Lumen, and Multichannel Poly(lactic-co-glycolic Acid) (PLGA) Nerve Tubes

    Science.gov (United States)

    de Ruiter, Godard C.; Spinner, Robert J.; Malessy, Martijn J. A.; Moore, Michael J.; Sorenson, Eric J.; Currier, Bradford L.; Yaszemski, Michael J.; Windebank, Anthony J.

    2012-01-01

    Objective Accuracy of motor axon regeneration becomes an important issue in the development of a nerve tube for motor nerve repair. Dispersion of regeneration across the nerve tube may lead to misdirection and polyinnervation. In this study, we present a series of methods to investigate the accuracy of regeneration, which we used to compare regeneration across autografts and single lumen poly(lactic-co-glycolic acid) (PLGA) nerve tubes. We also present the concept of the multichannel nerve tube that may limit dispersion by separately guiding groups of regenerating axons. Methods Simultaneous tracing of the tibial and peroneal nerves with fast blue (FB) and diamidino yellow (DY), 8 weeks after repair of a 1-cm nerve gap in the rat sciatic nerve, was performed to determine the percentage of double-projecting motoneurons. Sequential tracing of the peroneal nerve with DY 1 week before and FB 8 weeks after repair was performed to determine the percentage of correctly directed peroneal motoneurons. Results In the cases in which there was successful regeneration across single lumen nerve tubes, more motoneurons had double projections to both the tibial and peroneal nerve branches after single lumen nerve tube repair (21.4%) than after autograft repair (5.9%). After multichannel nerve tube repair, this percentage was slightly reduced (16.9%), although not significantly. The direction of regeneration was nonspecific after all types of repair. Conclusion Retrograde tracing techniques provide new insights into the process of regeneration across nerve tubes. The methods and data presented in this study can be used as a basis in the development of a nerve tube for motor nerve repair. PMID:18728579

  17. Mechanical characterization of poly-SiGe layers for CMOS–MEMS integrated application

    International Nuclear Information System (INIS)

    Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; De Wolf, Ingrid; Puers, Robert

    2010-01-01

    Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups

  18. Mechanism and modelling of source/drain asymmetry variation in 65 nm CMOS devices for SRAM and logic applications

    International Nuclear Information System (INIS)

    Lee, T H; Fang, Y K; Chiang, Y T; Lin, C T; Chen, M S; Cheng, O

    2008-01-01

    The source/drain asymmetry variation of 65 nm CMOS devices for SRAM and logic applications has been investigated in detail. For the first time, we observe that the asymmetry variation is proportional to the inverse of the root square of the device area. In other words, the asymmetry variation should become worse for future advanced CMOS technologies. Fortunately, through the T-CAD simulations and experiments, we find the variation can be improved significantly with the optimization of the poly-gate grain size, extra laser annealing and using a vertical profile poly-gate. Furthermore, the improvement in asymmetry variation leads to a better static noise margin of SRAM

  19. Poly(N-isopropylacrylamide) brushes grafted from cellulose nanocrystals via surface-initiated single-electron transfer living radical polymerization.

    Science.gov (United States)

    Zoppe, Justin O; Habibi, Youssef; Rojas, Orlando J; Venditti, Richard A; Johansson, Leena-Sisko; Efimenko, Kirill; Osterberg, Monika; Laine, Janne

    2010-10-11

    Cellulose nanocrystals (CNCs) or nanowhiskers produced from sulfuric acid hydrolysis of ramie fibers were used as substrates for surface chemical functionalization with thermoresponsive macromolecules. The CNCs were grafted with poly(N-isopropylacrylamide) brushes via surface-initiated single-electron transfer living radical polymerization (SI-SET-LRP) under various conditions at room temperature. The grafting process was confirmed via Fourier transform IR spectroscopy and X-ray photoelectron spectroscopy and the different molecular masses of the grafts were quantified and found to depend on the initiator and monomer concentrations used. No observable damage occurred to the CNCs after grafting, as determined by X-ray diffraction. Size exclusion chromatography analyses of polymer chains cleaved from the cellulose nanocrystals indicated that a higher degree of polymerization was achieved by increasing initiator or monomer loading, most likely caused by local heterogeneities yielding higher rates of polymerization. It is expected that suspension stability, interfacial interactions, friction, and other properties of grafted CNCs can be controlled by changes in temperature and provide a unique platform for further development of stimuli-responsive nanomaterials.

  20. Surface-Anchored Poly(4-vinylpyridine)–Single-Walled Carbon Nanotube–Metal Composites for Gas Detection

    KAUST Repository

    Yoon, Bora

    2016-08-05

    A platform for chemiresistive gas detectors based upon single-walled carbon nanotube (SWCNT) dispersions stabilized by poly(4-vinylpyridine) (P4VP) covalently immobilized onto a glass substrate was developed. To fabricate these devices, a glass substrate with gold electrodes is treated with 3-bromopropyltrichlorosilane. The resulting alkyl bromide coating presents groups that can react with the P4VP to covalently bond (anchor) the polymer–SWCNT composite to the substrate. Residual pyridyl groups in P4VP not consumed in this quaternization reaction are available to coordinate metal nanoparticles or ions chosen to confer selectivity and sensitivity to target gas analytes. Generation of P4VP coordinated to silver nanoparticles produces an enhanced response to ammonia gas. The incorporation of soft Lewis acidic Pd2+ cations by binding PdCl2 to P4VP yields a selective and highly sensitive device that changes resistance upon exposure to vapors of thioethers. The latter materials have utility for odorized fuel leak detection, microbial activity, and breath diagnostics. A third demonstration makes use of permanganate incorporation to produce devices with large responses to vapors of volatile organic compounds that are susceptible to oxidation.

  1. Charge transport and glassy dynamics of poly(ethylene oxide)-based single-ion conductors under geometrical confinement

    Science.gov (United States)

    Runt, James; Iacob, Ciprian

    2015-03-01

    Segmental and local dynamics as well as charge transport are investigated in a series of poly(ethylene oxide)-based single-ion conductors (ionomers) with varying counterions (Li +, Na +) confined in uni-directional nanoporous silica membranes. The dynamics are explored over a wide frequency and temperature range by broadband dielectric relaxation spectroscopy. Slowing of segmental dynamics and a decrease in dc conductivity (strongly coupled with segmental relaxation) of the confined ionomers are associated with surface effects - resulting from interfacial hydrogen bonding between the host nanoporous silica membrane and the guest ionomers. These effects are significantly reduced or eliminated upon pore surface modification through silanization. The primary transport properties for the confined ionomers decrease by about one decade compared to the bulk ionomer. A model assuming reduced mobility of an adsorbed layer at the pore wall/ionomer interface is shown to provide a quantitative explanation for the decrease in effective transport quantities in non-silanized porous silica membranes. Additionally, the effect of confinement on ion aggregation in ionomers by using X-ray scattering will also be discussed. Supported by the National Science Foundation, Polymers Program.

  2. Dually cross-linked single network poly(acrylic acid) hydrogels with superior mechanical properties and water absorbency.

    Science.gov (United States)

    Zhong, Ming; Liu, Yi-Tao; Liu, Xiao-Ying; Shi, Fu-Kuan; Zhang, Li-Qin; Zhu, Mei-Fang; Xie, Xu-Ming

    2016-06-28

    Poly(acrylic acid) (PAA) hydrogels with superior mechanical properties, based on a single network structure with dual cross-linking, are prepared by one-pot free radical polymerization. The network structure of the PAA hydrogels is composed of dual cross-linking: a dynamic and reversible ionic cross-linking among the PAA chains enabled by Fe(3+) ions, and a sparse covalent cross-linking enabled by a covalent cross-linker (Bis). Under deformation, the covalently cross-linked PAA chains remain intact to maintain their original configuration, while the Fe(3+)-enabled ionic cross-linking among the PAA chains is broken to dissipate energy and then recombined. It is found that the mechanical properties of the PAA hydrogels are significantly influenced by the contents of covalent cross-linkers, Fe(3+) ions and water, which can be adjusted within a substantial range and thus broaden the applications of the hydrogels. Meanwhile, the PAA hydrogels have excellent recoverability based on the dynamic and reversible ionic cross-linking enabled by Fe(3+) ions. Moreover, the swelling capacity of the PAA hydrogels is as high as 1800 times in deionized water due to the synergistic effects of ionic and covalent cross-linkings. The combination of balanced mechanical properties, efficient recoverability, high swelling capacity and facile preparation provides a new method to obtain high-performance hydrogels.

  3. Advanced CMOS device technologies for 45 nm node and below

    Directory of Open Access Journals (Sweden)

    A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

    2007-01-01

    Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

  4. Reliability in CMOS IC processing

    Science.gov (United States)

    Shreeve, R.; Ferrier, S.; Hall, D.; Wang, J.

    1990-01-01

    Critical CMOS IC processing reliability monitors are defined in this paper. These monitors are divided into three categories: process qualifications, ongoing production workcell monitors, and ongoing reliability monitors. The key measures in each of these categories are identified and prioritized based on their importance.

  5. A CMOS Switched Transconductor Mixer

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Louwsma, S.M.; Wienk, Gerhardus J.M.; Nauta, Bram

    A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled

  6. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    of wafer through-holes the main challenge is to protect the CMOS wafer during etching. In the case of DRIE etching of the wafer through-holes the main challenges are proper insulation of the wafer through-holes, conformal deposition of via metal and structuring of the deposited metal. This thesis discusses...

  7. CMOS Analog IC Design: Fundamentals

    DEFF Research Database (Denmark)

    Bruun, Erik

    This book is intended for use as the main textbook for an introductory course in CMOS analog integrated circuit design. It is aimed at electronics engineering students who have followed basic courses in mathematics, physics, circuit theory, electronics and signal processing. It takes the students...

  8. Photon detection with CMOS sensors for fast imaging

    International Nuclear Information System (INIS)

    Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

    2009-01-01

    Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e - , and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100μs have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

  9. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  10. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  11. Remarkable crystallization morphologies of poly(4-vinylpyridine on single-walled carbon nanotubes in CO2-expanded liquids

    Directory of Open Access Journals (Sweden)

    Y. N. Wei

    2011-12-01

    Full Text Available Poly(4-vinylpyridine (P4VP is a widely studied polymer for applications in catalysis, humidity sensitive and antimicrobial materials due to its pyridine group exhibiting coordinative reactivity with transition metals. In this work, the non-covalent functionalization of single-walled carbon nanotubes (SWCNTs with P4VP in CO2-expanded liquids (CXLs is reported. It is found that P4VP stabilized SWCNTs show good dispersion in both organic solvent and aqueous solution (pH = 2. The ability to manipulate the dispersion state of CNTs in water with P4VP will likely benefit many biological applications, such as drug delivery and optical sensors. Furthermore, the structure and morphology of P4VP/SWCNTs composite are examined, with the focus on molecular weight of P4VP (MW-P4VP, the pressure of CXLs and the concentration of P4VP. It is amazing that the P4VP15470 wrapping patterns undergo a notable morphological evolution from dotlike crystals to bottle brush-like, then to compact kebab-like, and then to widely-spaced dotted kebab patterns by facile pressure tuning in the higher polymer concentration series. In other words, the CXLs method enables superior control of the P4VP crystallization patterns on SWCNTs. Meanwhile, the CXL-assisted P4VP crystal growth mechanism on SWCNT is investigated, and the dominating growth mechanism is attributed to ‘size dependent soft epitaxy’ in P4VP15470/SWCNTs composites. We believe these studies would r

  12. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  13. CMOS optimization for radiation hardness

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Fossum, J.G.

    1975-01-01

    Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

  14. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  15. Effect of Zn2+ and temperature on the conformational equilibrium of single-stranded polyA in neutral solutions

    Czech Academy of Sciences Publication Activity Database

    Sorokin, V. A.; Valeev, V. A.; Usenko, E. L.; Andrushchenko, Valery

    2013-01-01

    Roč. 61, Oct (2013), s. 448-452 ISSN 0141-8130 R&D Projects: GA ČR GAP208/10/0559 Institutional support: RVO:61388963 Keywords : metal ions * polyA * metal lized form * differential UV spectroscopy * thermal denaturation * phase diagram Subject RIV: CE - Biochemistry Impact factor: 3.096, year: 2013

  16. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  17. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    . The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  18. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  19. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  20. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  1. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

    International Nuclear Information System (INIS)

    Feng Peng; Zhang Qi; Wu Nanjian

    2011-01-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma—delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm 2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is −10.7 dBm/−8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is −0.6 °C/0.5 °C (−1.0 °C/1.2 °C) in the operating range from 5 to 15 °C in high resolution mode (−30 to 50 °C in low resolution mode). The resolution of the sensor achieves 0.02 °C (0.18 °C) in high (low) resolution mode. (semiconductor integrated circuits)

  2. Two transistor cluster DICE Cells with the minimum area for a hardened 28-nm CMOS and 65-nm SRAM layout design

    International Nuclear Information System (INIS)

    Stenin, V.Ya.; Stepanov, P.V.

    2015-01-01

    A hardened DICE cell layout design is based on the two spaced transistor clusters of the DICE cell each consisting of four transistors. The larger the distance between these two CMOS transistor clusters, the more robust the hardened DICE SRAM to Single Event Upsets. Some versions of the 28-nm and 65-nm DICE CMOS SRAM block composition have been suggested with minimum cluster distances of 2.27-2.32 mkm. The area of hardened 28-nm DICE CMOS cells is larger than the area of 28-nm 6T CMOS cells by a factor of 2.1 [ru

  3. A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

    Science.gov (United States)

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

  4. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    Directory of Open Access Journals (Sweden)

    Mohd Haris Md Khir

    2011-08-01

    Full Text Available This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

  5. A Radiation Hard Current Reference Circuit in a Standard 0.13μm CMOS Technology.

    CERN Document Server

    Gromov, V

    2008-01-01

    A CMOS bandgap current reference circuit has been developed in a 0.13 um CMOS technology. The circuit exhibits low sensitivity to temperature- and power supply variations. The combination of the natural properties of thin gate oxide MOS transistors with a gate-all-around layout approach makes stable operation in harsh radiation environment possible. In the present design we utilize only MOS structures and poly-silicon resistors. The output current varies in the range 0.9 % when the circuit is being irradiated up to a 200 Mrad.

  6. Design and Simulation of 1-bit Sigma Delta ADC in 0.18um CMOS Technology

    OpenAIRE

    Jaydip H. Chaudhari

    2013-01-01

    This paper presents the design of a first order single bit Sigma-Delta ADC which is realized using CMOS technology. In this paper, a first Order Sigma-Delta ADC is implemented in a standard 0.18um CMOS technology. The Design and Simulation of the Modulator is done using Mentor Graphics Tool. First order single bit Sigma Delta ADC Modulator is implemented using ±1.8 power supply and simulation results are plotted using Mentor Graphics Tool. This paper firstly elaborate about ADC types and Clas...

  7. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  8. Nanopore-CMOS Interfaces for DNA Sequencing.

    Science.gov (United States)

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-08-06

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

  9. A CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) oscillator

    Science.gov (United States)

    Chin, Chi-Hang; Li, Ming-Huang; Chen, Chao-Yu; Wang, Yu-Lin; Li, Sheng-Shian

    2015-11-01

    A high-frequency CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) fabricated by a standard 0.35 μm 2-poly-4-metal CMOS-MEMS platform is implemented to enable a Pierce-type oscillator. The proposed arrayed RGFET exhibits low motional impedance of only 5 kΩ under a purely capacitive transduction and decent power handling capability. With such features, the implemented oscillator shows impressive phase noise of  -117 dBc Hz-1 at the far-from-carrier offset (1 MHz). In this work, we design a clamped-clamped beam (CCB) arrayed resonator utilizing a high-velocity mechanical coupling scheme to serve as the resonant-gate array. To achieve a functional arrayed RGFET, a corresponding FET array is directly placed underneath the resonant gate array to convert the motional current on the resonant-gate array into a voltage output with a tunable transconductance gain. To understand the behavior of the proposed device, an equivalent circuit model consisting of the resonant unit and FET is also provided. To verify the effects of the post-CMOS process on device performance, a conventional MOS I D current measurement is carried out. Finally, a CMOS-MEMS arrayed RGFET oscillator is realized by utilizing a Pierce oscillator architecture, showing decent phase noise performance that benefits from the array design to alleviate the nonlinear effect of the resonant gate.

  10. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  11. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  12. Latch-up in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Estreich, D.B.; Dutton, R.W.

    1978-04-01

    An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

  13. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  14. Copper(0) Mediated Single Electron Transfer Controlled Radical Polymerization toward CF Bonds on Poly(vinylidene fluoride).

    Science.gov (United States)

    Tan, Shaobo; Zhang, Yanan; Niu, Zhijing; Zhang, Zhicheng

    2018-02-01

    The first copper(0) mediated controlled radical polymerization (CRP) of methyl methacrylate (MMA) toward CF bonds onto poly(vinylidene fluoride) (PVDF) is reported with rather high activity. By avoiding the halogen exchange, Cu 0 instead of Cu I complexes utilized as catalyst is responsible for the significantly improved polymerization activity. Using FH decoupled nuclear magnetic resonance technique, the grafting sites onto PVDF are finely located. From this, detailed topologic information including the grafting density, average length of each side chain, along with the overall grafted content of PMMA, is detected by tracking the polymerization as a function of time. This work offers not only a facile CRP strategy based on inactive CF bonds but also a deep insight into the cleavage of F-bearing compounds in organic chemistry. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  15. Synthesis, Characterization and Application of Poly (Styrene-4- Vinyl Pyridine) Membranes Assembled With Single-Wall Carbon Nanotubes

    KAUST Repository

    He, Haoze

    2011-06-01

    Poly(styrene‐4‐vinylpyridine) (PS‐P4VP) isoporous membranes were prepared and their properties were evaluated in this research. The solution was prepared by dissolving PS‐P4VP polymer with necessary additives into a 1:1:1 1,4‐dioxane – N,N‐dimethyl formamide – tetrahydrofuran (DOX‐DMF‐THF, DDT) solvent. Then 0.5‐1.0 mL of the primary solution was cast onto the non‐woven substrate membrane on a glass slide, evaporated for 15‐20 sec and immersed into de‐ionized water for more than 30 min for the solidification of isoporous structure and for the formation of the primary films, which could be post‐processed in different ways for different tests. The membrane surface presents a well‐ordered, hexagonal self‐assembly structure, which is fit for aqueous and gaseous filtration. The pore size of the isoporous surface is 30~40 nm. The pore size is also sensitive to [H+] in the solution and a typical pair of S‐shape pH‐correlation curves with significant hysteresis was found. Four techniques were tried to improve the properties of the membranes in this research: 1) 1,4‐diiodobutane was introduced to chemically change the structure as a cross‐linking agent. 2) single‐wall carbon nanotube (SWCNT) was linked to the membranes in order to strengthen the stability and rigidity and to reduce the hysteresis. 3) Homo‐poly(4‐vinylpyridine) (homo‐P4VP) was added and inserted into the PS‐P4VP micelles to affect the pore size and surface structure. 4) Copper acetate (Cu(Ac)2) was used as substitute of dioxane to prepare the Cu(Ac)2‐DMF‐THF (CDT) mixed solvent, for a better SWCNT dispersion. All the possible improvements were judged by the atomic force microscopy (AFM) images, water and gas flux tests and pH‐correlation curves. The introduction of SWCNT was the most important innovation in this research and is promising in future applications.

  16. Photoinduced synthesis of single-digit micrometer-size spheroidal calcite composites in the presence of partially hydrolyzed poly(vinyl alcohol)

    Science.gov (United States)

    Nishio, Takashi; Naka, Kensuke

    2015-06-01

    Photoinduced crystallization of calcium carbonate (CaCO3), which was based on the photodecarboxylation of ketoprofen (KP, 2-(3-benzoylphyenyl)propionic acid) under alkaline conditions of pH 8.4 and 10 was studied for preparation of CaCO3 composite particles in single-digit micrometer-sizes. In this method, a homogeneous solution comprising KP, calcium chloride, ammonia, and partially hydrolyzed poly(vinyl alcohol) (PVAPS, degree of saponification: 86.5-89.0 mol%) was used as a precursor solution and was exposed to ultraviolet (UV) irradiation for different time periods. After the UV irradiation for 50 min, calcite spheroids in single-digit micrometer-sizes were obtained as major products at pH 8.4. The obtained calcite spheroids contained organic components of about 10 wt%. The comparison of the characteristics of the CaCO3 obtained at pH 8.4 and 10 suggests that the nucleation and crystallization of both vaterite and calcite continuously took place in a moderated supersaturation owing to the CO2 hydration equilibrium as long as the photodecarboxylation of KP continued. Consequently, the aggregation-based crystal growth in the presence of PVAPS seemed to enable the formation of the spheroidal composites of calcite in single-digit micrometer-sizes.

  17. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  18. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  19. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    CERN Document Server

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  20. Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

    Science.gov (United States)

    Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

    2016-11-01

    2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. Single-Blind Randomized Controlled Trial of Poly-Herbal Formula Sahatsatara for Acute Low Back Pain: A Pilot Study

    Directory of Open Access Journals (Sweden)

    Thiyapha Verayachankul

    2016-01-01

    Full Text Available Objective: To evaluate the efficacy and safety of poly-herbal formula Sahatsatara (SHT in pain reduction in acute low back pain (LBP patients. Methods: Twenty-nine patients aged 18-65 years with a history of moderate to severe acute LBP ≤3-day (score ≥4 on a 0-10 numeric rating scale [NRS] were enrolled and randomized to receive an ibuprofen (400 mg after meals three times daily or SHT (1,350 mg before meals three times daily for 7 days. The non-inferiority trial margin was set at ±10 percentage points. The outcomes were measured on pain intensity on the 0-10 NRS, disability on the Thai version of the Oswestry disability index [ODI], total analgesic consumption, patient satisfaction, and safety. Results: Fourteen patients and 15 patients were randomly allocated to ibuprofen and SHT groups, respectively. The mean difference in pain intensity and disability between the two groups at day 7 adjusted according to baseline was within ±1 for pain (-0.3; 95% CI, -1.48 to 0.96 and ±10% (-4.9%; 95% CI, -14.86% to 5.02% for the NRS and ODI scores, respectively. One patient in the SHT group and 5 in the ibuprofen group had gastrointestinal irritation, but the difference was not statistically significant. Conclusion: SHT was not inferior to ibuprofen in pain relieving and disability in patients with acute LBP. The result suggests a role for SHT as an alternative analgesic in acute LBP. (Thai Clinical Trials Registry number 20141027001

  2. Fibrous polymer grafted magnetic chitosan beads with strong poly(cation-exchange) groups for single step purification of lysozyme.

    Science.gov (United States)

    Bayramoglu, Gulay; Tekinay, Turgay; Ozalp, V Cengiz; Arica, M Yakup

    2015-05-15

    Lysozyme is an important polypetide used in medical and food applications. We report a novel magnetic strong cation exchange beads for efficient purification of lysozyme from chicken egg white. Magnetic chitosan (MCHT) beads were synthesized via phase inversion method, and then grafted with poly(glycidyl methacrylate) (p(GMA)) via the surface-initiated atom transfer radical polymerization (SI-ATRP). Epoxy groups of the grafted polymer, were modified into strong cation-exchange groups (i.e., sulfonate groups) in the presence of sodium sulfite. The MCTH and MCTH-g-p(GMA)-SO3H beads were characterized by ATR-FTIR, SEM, and VSM. The sulphonate groups content of the modified MCTH-g-p(GMA)-4 beads was found to be 0.53mmolg(-1) of beads by the potentiometric titration method. The MCTH-g-p(GMA)-SO3H beads were first used as an ion-exchange support for adsorption of lysozyme from aqueous solution. The influence of different experimental parameters such as pH, contact time, and temperature on the adsorption process was evaluated. The maximum adsorption capacity was found to be 208.7mgg(-1) beads. Adsorption of lysozyme on the MCTH-g-p(GMA)-SO3H beads fitted to Langmuir isotherm model and followed the pseudo second-order kinetic. More than 93% of the adsorbed lysozyme was desorbed using Na2CO3 solution (pH 11.0). The purity of the lysozyme was checked by HPLC and SDS gel electrophoresis. In addition, the MCTH-g-p(GMA)-SO3H beads prepared in this work showed promising potential for separation of various anionic molecules. Copyright © 2015 Elsevier B.V. All rights reserved.

  3. Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

    Energy Technology Data Exchange (ETDEWEB)

    Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

    2017-07-01

    We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

  4. Monolithic Composite “Pressure + Acceleration + Temperature + Infrared” Sensor Using a Versatile Single-Sided “SiN/Poly-Si/Al” Process-Module

    Science.gov (United States)

    Ni, Zao; Yang, Chen; Xu, Dehui; Zhou, Hong; Zhou, Wei; Li, Tie; Xiong, Bin; Li, Xinxin

    2013-01-01

    We report a newly developed design/fabrication module with low-cost single-sided “low-stress-silicon-nitride (LS-SiN)/polysilicon (poly-Si)/Al” process for monolithic integration of composite sensors for sensing-network-node applications. A front-side surface-/bulk-micromachining process on a conventional Si-substrate is developed, featuring a multifunctional SiN/poly-Si/Al layer design for diverse sensing functions. The first “pressure + acceleration + temperature + infrared” (PATIR) composite sensor with the chip size of 2.5 mm × 2.5 mm is demonstrated. Systematic theoretical design and analysis methods are developed. The diverse sensing components include a piezoresistive absolute-pressure sensor (up to 700 kPa, with a sensitivity of 49 mV/MPa under 3.3 V supplied voltage), a piezoresistive accelerometer (±10 g, with a sensitivity of 66 μV/g under 3.3 V and a −3 dB bandwidth of 780 Hz), a thermoelectric infrared detector (with a responsivity of 45 V/W and detectivity of 3.6 × 107 cm·Hz1/2/W) and a thermistor (−25–120 °C). This design/fabrication module concept enables a low-cost monolithically-integrated “multifunctional-library” technique. It can be utilized as a customizable tool for versatile application-specific requirements, which is very useful for small-size, low-cost, large-scale sensing-network node developments. PMID:23325169

  5. Single-Step Fabrication Using a Phase Inversion Method of Poly(vinylidene fluoride) (PVDF) Activated Carbon Air Cathodes for Microbial Fuel Cells

    KAUST Repository

    Yang, Wulin

    2014-10-14

    Air cathodes used in microbial fuel cells (MFCs) need to have high catalytic activity for oxygen reduction, but they must also be easy to manufacture, inexpensive, and watertight. A simple one-step, phase inversion process was used here to construct an inexpensive MFC cathode using a poly(vinylidene fluoride) (PVDF) binder and an activated carbon catalyst. The phase inversion process enabled cathode preparation at room temperatures, without the need for additional heat treatment, and it produced for the first time a cathode that did not require a separate diffusion layer to prevent water leakage. MFCs using this new type of cathode produced a maximum power density of 1470 ± 50 mW m–2 with acetate as a substrate, and 230 ± 10 mW m–2 with domestic wastewater. These power densities were similar to those obtained using cathodes made using more expensive materials or more complex procedures, such as cathodes with a polytetrafluoroethylene (PTFE) binder and a poly(dimethylsiloxane) (PDMS) diffusion layer, or a Pt catalyst. Even though the PVDF cathodes did not have a diffusion layer, they withstood up to 1.22 ± 0.04 m of water head (∼12 kPa) without leakage, compared to 0.18 ± 0.02 m for cathodes made using PTFE binder and PDMS diffusion layer. The cost of PVDF and activated carbon ($3 m–2) was less than that of the stainless steel mesh current collector ($12 m–2). PVDF-based AC cathodes therefore are inexpensive, have excellent performance in terms of power and water leakage, and they can be easily manufactured using a single phase inversion process at room temperature.

  6. Monolithic Composite “Pressure + Acceleration + Temperature + Infrared” Sensor Using a Versatile Single-Sided “SiN/Poly-Si/Al” Process-Module

    Directory of Open Access Journals (Sweden)

    Xinxin Li

    2013-01-01

    Full Text Available We report a newly developed design/fabrication module with low-cost single-sided “low-stress-silicon-nitride (LS-SiN/polysilicon (poly-Si/Al” process for monolithic integration of composite sensors for sensing-network-node applications. A front-side surface-/bulk-micromachining process on a conventional Si-substrate is developed, featuring a multifunctional SiN/poly-Si/Al layer design for diverse sensing functions. The first “pressure + acceleration + temperature + infrared” (PATIR composite sensor with the chip size of 2.5 mm × 2.5 mm is demonstrated. Systematic theoretical design and analysis methods are developed. The diverse sensing components include a piezoresistive absolute-pressure sensor (up to 700 kPa, with a sensitivity of 49 mV/MPa under 3.3 V supplied voltage, a piezoresistive accelerometer (±10 g, with a sensitivity of 66 μV/g under 3.3 V and a −3 dB bandwidth of 780 Hz, a thermoelectric infrared detector (with a responsivity of 45 V/W and detectivity of 3.6 × 107 cm·Hz1/2/W and a thermistor (−25–120 °C. This design/fabrication module concept enables a low-cost monolithically-integrated “multifunctional-library” technique. It can be utilized as a customizable tool for versatile application-specific requirements, which is very useful for small-size, low-cost, large-scale sensing-network node developments.

  7. Structural and morphological studies on poly(3-hydroxybutyrate acid) (PHB)/chitosan drug releasing microspheres prepared by both single and double emulsion processes

    Energy Technology Data Exchange (ETDEWEB)

    Shih, W.-J. [Department of Materials Science and Engineering, National Cheng Kung University, 1 Ta-Hsueh Road, Tainan 70101, Taiwan (China); Chen, Y.-H. [Department of Mechanical Engineering, National Kaohsiung University of Applied Sciences, 415 Chien-kung Road, Kaohsiung 80782, Taiwan (China); Shih, C.-J. [Faculty of Fragrance and Cosmetics, Kaohsiung Medical University, No. 100, Shih-Chuang 1st Rd., Sanmin District, Kaohsiung 80708, Taiwan (China); Hon, M.-H. [Department of Materials Science and Engineering, National Cheng Kung University, 1 Ta-Hsueh Road, Tainan 70101, Taiwan (China); Dayeh University, 112 Shan-Jiau Road, Da-Tsuen, Changhua 515, Taiwan (China); Wang, M.-C. [Department of Mechanical Engineering, National Kaohsiung University of Applied Sciences, 415 Chien-kung Road, Kaohsiung 80782, Taiwan (China) and Department of Materials Science and Engineering, National United University, 1 Lien-Da Road, Kung-ching Li, Miao Li 360, Taiwan (China)]. E-mail: mcwang@cc.kuas.edu.tw

    2007-05-31

    Drug releasing microspheres of poly(3-hydroxybutyric acid)/chitosan (PHB/CTS) with various compositions have been synthesized by both single and double emulsion methods, and collected by a freeze-drying process. In this study, gentamicin was used as an antibacterial medicine coated with PHB. The PHB/CTS microspheres of various compositions prepared by a single emulsion process (SEP) were identified as the major PHB phase together with a minor unknown Phase X by X-ray diffraction (XRD) and FT-IR. However, in the microspheres prepared using a double emulsion process (DEP) the dominant Phase was X and the minor phase was PHB. The size of the PHB/CTS microspheres prepared by SEP increased with the PHB/CTS ratio from 1 {mu}m for 1:1 to 2 {mu}m for 5:1. However, the size of the PHB/CTS microspheres prepared by DEP decreased with the PHB/CTS ratio from 1 {mu}m for 1:1 to 800 nm for 5:1.

  8. Structural and morphological studies on poly(3-hydroxybutyrate acid) (PHB)/chitosan drug releasing microspheres prepared by both single and double emulsion processes

    International Nuclear Information System (INIS)

    Shih, W.-J.; Chen, Y.-H.; Shih, C.-J.; Hon, M.-H.; Wang, M.-C.

    2007-01-01

    Drug releasing microspheres of poly(3-hydroxybutyric acid)/chitosan (PHB/CTS) with various compositions have been synthesized by both single and double emulsion methods, and collected by a freeze-drying process. In this study, gentamicin was used as an antibacterial medicine coated with PHB. The PHB/CTS microspheres of various compositions prepared by a single emulsion process (SEP) were identified as the major PHB phase together with a minor unknown Phase X by X-ray diffraction (XRD) and FT-IR. However, in the microspheres prepared using a double emulsion process (DEP) the dominant Phase was X and the minor phase was PHB. The size of the PHB/CTS microspheres prepared by SEP increased with the PHB/CTS ratio from 1 μm for 1:1 to 2 μm for 5:1. However, the size of the PHB/CTS microspheres prepared by DEP decreased with the PHB/CTS ratio from 1 μm for 1:1 to 800 nm for 5:1

  9. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  10. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  11. 60-GHz CMOS phase-locked loops

    CERN Document Server

    Cheema, Hammad M; van Roermund, Arthur HM

    2010-01-01

    The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. ""60-GHz CMOS Phase-Locked Loops"" focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of i

  12. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  13. Challenges & Roadmap for Beyond CMOS Computing Simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-12-01

    Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

  14. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  15. A study of the sensitivity to cosmic rays and integrated dose of bit slice microprocessors in CMOS and CMOS on insulator technologies (CMOS/SOI)

    International Nuclear Information System (INIS)

    Leray, J.L.; Musseau, O.; Dupont-Nivet, E.; Pere, J.F.; Coic, Y.M.

    1988-01-01

    SOI is a promising technique to achieve both high-speed and high-level hardened VLSI-ULSI circuits. However, such aims still need a full demonstration. First, the radiation effects basic phenomena will be emphasized, in relation with the device structure relevant to the SOI. These results can be compared with those from the literature, based on SIMOX or other SOI structures, and to similar microprocessors made in CMOS technologies, by means of a kit of circuits containing 4 and 16-bits microprocessors. Actual performances in term of ionizing dose vulnerability are presented. Specific properties of SIMOX oxide are also described in term of total dose and single cosmic ion strike [fr

  16. Efficacy of poly(lactic acid)/carvacrol electrospun membranes against Staphylococcus aureus and Candida albicans in single and mixed cultures.

    Science.gov (United States)

    Scaffaro, Roberto; Lopresti, Francesco; D'Arrigo, Manuela; Marino, Andreana; Nostro, Antonia

    2018-03-13

    Carvacrol (CAR) is one of the most promising essential oil components with antimicrobial activity. New technologies aimed to incorporate this active molecule into carrier matrix to improve the stability and prolong the biological activity. The goal of this study was to investigate the feasibility of incorporating CAR into electrospun membranes of poly(lactic acid) (PLA) for potential applications as active antimicrobial system. To this end, PLA membranes containing homogeneously dispersed CAR were successfully prepared and a series of systematic tests including morpho-mechanical properties, in vitro release rate, and antimicrobial/antibiofilm activities against Staphylococcus aureus and Candida albicans were carried out. The results revealed that CAR has a good compatibility with PLA and acts as a plasticizer, improving flexibility and extensibility of the matrix. The gradual release of CAR from PLA membranes warranted a significant antimicrobial activity up to 144 h and reduced the biofilm production by 92-96 and 88-95% of S. aureus and C. albicans in single and mixed cultures. A strong decrease of cell count, biomass, metabolic activity, and vitality of established 24- and 48-h biofilms were also demonstrated. In conclusion, this work highlights the potential of electrospun nanofibrous membranes as efficient stabilizers-carriers of CAR and opens up interesting perspectives on the use of this system as new tool for skin and wound bacterial-fungal infections.

  17. Electrochemical detection of Hg(II in water using self-assembled single walled carbon nanotube-poly(m-amino benzene sulfonic acid on gold electrode

    Directory of Open Access Journals (Sweden)

    Gauta Gold Matlou

    2016-09-01

    Full Text Available This work reports on the detection of mercury using single walled carbon nanotube-poly (m-amino benzene sulfonic acid (SWCNT-PABS modified gold electrode by self-assembled monolayers (SAMs technique. A thiol containing moiety (dimethyl amino ethane thiol (DMAET was used to facilitate the assembly of the SWCNT-PABS molecules onto the Au electrode surface. The successfully assembled monolayers were characterised using atomic force microscopy (AFM. Cyclic voltammetric and electrochemical impedance spectroscopic studies of the modified electrode (Au-DMAET-(SWCNT-PABS showed improved electron transfer over the bare Au electrode and the Au-DMAET in [Fe (CN6]3−/4− solution. The Au-DMAET-(SWCNT-PABS was used for the detection of Hg in water by square wave anodic stripping voltammetry (SWASV analysis at the following optimized conditions: deposition potential of −0.1 V, deposition time of 30 s, 0.1 M HCl electrolyte and pH 3. The sensor showed a good sensitivity and a limit of detection of 0.06 μM with a linear concentration range of 20 ppb to 250 ppb under the optimum conditions. The analytical applicability of the proposed method with the sensor electrode was tested with real water sample and the method was validated with inductively coupled plasma – optical emission spectroscopy. Keywords: Self-assembly, Gold electrode, Carbon nanotubes, Electrochemical detection, Mercury

  18. A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

    Science.gov (United States)

    Kaiming, Nie; Suying, Yao; Jiangtao, Xu; Zhaorui, Jiang

    2014-03-01

    A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0:12/-0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μW with a 1.8 V supply, and its area is 0.03 × 0.8 mm2.

  19. Transmission Lines in CMOS: An Explorative Study

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Kreienkamp, R.; Ellermeyer, T.; Langmann, U.

    On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important

  20. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, H.; Klumperink, Eric A.M.; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel

  1. Low energy CMOS for space applications

    Science.gov (United States)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  2. Different mathematical relations with CMOS VLSI circuits

    International Nuclear Information System (INIS)

    Chible, H.; Ghandour, A.

    2007-01-01

    In this paper, Analog VLSI CMOS circuits that implements different mathematical functions, equations, or relations such as ''Addition, Subtraction, Multiplier, Quadratic, Square Root, Linear, and Hyperbolic Tangent relations'' with limited and wide range variations are presented. These relations and functions are useful for analog neural network hardware and analog signal processing implementation (author)

  3. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  4. Low noise monolithic CMOS front end electronics

    International Nuclear Information System (INIS)

    Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

    1987-01-01

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  5. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  6. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation i...

  7. CMOS Compatible Ultra-Compact Modulator

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss <1dB at telecommunication wavelengths....

  8. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  9. Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

    Science.gov (United States)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  10. HV-CMOS detectors in BCD8 technology

    Science.gov (United States)

    Andreazza, A.; Castoldi, A.; Ceriale, V.; Chiodini, G.; Citterio, M.; Darbo, G.; Gariano, G.; Gaudiello, A.; Guazzoni, C.; Joshi, A.; Liberali, V.; Passadore, S.; Ragusa, F.; Ruscino, E.; Sbarra, C.; Shrimali, H.; Sidoti, A.; Stabile, A.; Yadav, I.; Zaffaroni, E.

    2016-11-01

    This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm2. To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

  11. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  12. Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

    Science.gov (United States)

    Wei, Liping; Yan, Wenrong; Ho, Derek

    2017-12-04

    Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

  13. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    International Nuclear Information System (INIS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  14. Fundamental and harmonic soliton mode-locked erbium-doped fiber laser using single-walled carbon nanotubes embedded in poly (ethylene oxide) film saturable absorber

    Science.gov (United States)

    Rosdin, R. Z. R. R.; Zarei, A.; Ali, N. M.; Arof, H.; Ahmad, H.; Harun, S. W.

    2015-01-01

    This paper presents a simple, compact and low cost mode-locked Erbium-doped fiber laser (EDFL) using a single-walled carbon nanotubes (SWCNTs) embedded in poly(ethylene oxide) (PEO) film as a passive saturable absorber. The film was fabricated using a prepared homogeneous SWCNT solution, which was mixed with a diluted PEO solution and casted onto a glass petri dish to form a thin film by evaporation technique. The film, with a thickness of 50 μm, is sandwiched between two fiber connectors to construct a saturable absorber, which is then integrated in an EDFL cavity to generate a self-started stable soliton pulses operating at 1560.8 nm. The soliton pulse starts to lase at 1480 nm pup power threshold of 12.3 mW to produce pulse train with repetition rate of 11.21 MHz, pulse width of 1.02 ps, average output power of 0.65 mW and pulse energy of 57.98 pJ. Then, we observed the 4th, 7th and 15th harmonic of fundamental cavity frequency start to occur when the pump powers are further increased to 14.9, 17.5 and 20.1 mW, respectively. The 4th harmonic pulses are characterized in detail with a repetition rate of 44.84 MHz, a transform-limited pulse width of 1.19 ps, side-mode suppression ratio of larger than 20 dB and pulse energy of 9.14 pJ.

  15. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process

    OpenAIRE

    Isao Takayanagi; Norio Yoshimura; Kazuya Mori; Shinichiro Matsuo; Shunsuke Tanaka; Hirofumi Abe; Naoto Yasuda; Kenichiro Ishikawa; Shunsuke Okura; Shinji Ohsawa; Toshinori Otaka

    2018-01-01

    To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circu...

  16. CMOS capacitive biosensors for highly sensitive biosensing applications.

    Science.gov (United States)

    Chang, An-Yu; Lu, Michael S-C

    2013-01-01

    Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

  17. Resizing methodology for CMOS analog circuits

    Science.gov (United States)

    Levi, Timothée; Tomas, Jean; Lewis, Noëlle; Fouillat, Pascal

    2007-05-01

    This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. This methodology is applied to both linear and non-linear examples: an OTA and a ring oscillator. The results are compared on three CMOS processes whose minimum length is 0.8 μm, 0.35 μm, 0.25 μm.

  18. Resizing methodology for CMOS analog circuit

    OpenAIRE

    Levi, Timothée; Tomas, J.; Lewis, N.; Fouillat, P.

    2007-01-01

    International audience; This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain...

  19. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    International Nuclear Information System (INIS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-01-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus TM X-ray machine, two scintillators of Lanex TM Fine and Regular, and two CMOS APS array of RadEye TM were used under the conditions of 50 kV p /1 mAs and 100 kV p /1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS

  20. On-chip deposition of carbon nanotubes using CMOS microhotplates

    International Nuclear Information System (INIS)

    Haque, M S; Teo, K B K; Rupensinghe, N L; Ali, S Z; Haneef, I; Maeng, Sunglyul; Park, J; Udrea, F; Milne, W I

    2008-01-01

    The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 deg. C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required

  1. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  2. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  3. Behavior of faulty double BJT BiCMOS logic gates

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  4. Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials

    OpenAIRE

    Mollazadeh, Mohsen; Murari, Kartikeya; Cauwenberghs, Gert; Thakor, Nitish

    2009-01-01

    Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 μm 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to...

  5. A robust 43-GHz VCO in CMOS for OC-768 SONET applications

    NARCIS (Netherlands)

    van der Wel, A.P.; Gierkink, Sander L.J.; Gierink, Sander L.J.; Frye, Robert C.; Boccuzzi, Vito; Nauta, Bram

    In this paper, we present a 43-GHz LC-VCO in 0.13-μm CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 Vp-p (single-ended) into a 90-fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90

  6. Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

    Science.gov (United States)

    Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

    2016-02-01

    Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

  7. Fundamental performance differences of CMOS and CCD imagers: part V

    Science.gov (United States)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  8. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  9. Single-Crystalline InGaAs/InP Dense Micro-Pillar Forest on Poly-Silicon Substrates for Low-Cost High-Efficiency Solar Cells

    Energy Technology Data Exchange (ETDEWEB)

    Chang-Hasnain, Constance

    2015-05-04

    The ultimate goal of this project is to develop a photovoltaic system high conversion efficiency (>20%) using high quality III-V compound-based three-dimensional micro-structures on silicon and poly-silicon. Such a PV-system could be of very low cost due to minimum usages of III-V materials. This project will address the barriers that currently hamper the performance of solar cells based on three-dimensional micro-structures. To accomplish this goal the project is divided into 4 tasks, each dealing with a different aspect of the project: materials quality, micropillar growth control, light management, and pillar based solar cells. Materials Quality: the internal quantum efficiency (IQE) - by which is meant here the internal fluorescence yield - of the micro-pillars has to be increased. We aim at achieving an IQE of 45% by the end of the first year. By the end of the second year there will be a go-no-go milestone of 65% IQE. By the end of year 3 and 4 we aim to achieve 75% and 90% IQE, respectively. Micropillar growth control: dense forests of micropillars with high fill ratios need to be grown. Pillars within forests should show minimum variations in size. We aim at achieving fill ratios of 2%, 10%, >15%, >20% in years 1, 2, 3, and 4, respectively. Variations in dimension should be minimized by site-controlled growth of pillars. By the end of year 1 we will aim at achieving site-controlled growth with > 15% yield. By end of year 2 the variation of critical pillar dimensions should be less than 25%. Light management: high light absorption in the spectral range of the sun has been to be demonstrated for the micropillar forests. By the end of year 1 we will employ FDTD simulation techniques to demonstrate that pillar forests with fill ratios <20% can achieve 99% light absorption. By end of year 2 our original goal was to demonstrate >85% absorption. By end of year 3 > 90% absorption should be demonstrated. Pillar based solar cells: devices will be studied to explore

  10. Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

    International Nuclear Information System (INIS)

    Dixit, Pradeep; Vehmas, Tapani; Vähänen, Sami; Monnoyer, Philippe; Henttinen, Kimmo

    2012-01-01

    This paper presents the fabrication and the electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 µm thin silicon device wafer, bonded to a handle wafer by plasma activated oxide-to-silicon bonding. Heavily doped poly-Si was used as interconnection material, which was deposited by low-pressure chemical vapor deposition. Two different via geometries, i.e. stadium shaped, and circular shaped, were tried. Sputtered aluminum metallization layers as double-side redistribution lines and contact pads, were used. Both Kelvin structures and daisy chains were fabricated and their electrical resistances were measured. The electrical resistance of a single stadium-shaped via was measured to be about 24 Ω. The electrical resistance was varying from 60 Ω to 90 Ω for two-vias daisy chains. Measured results indicate that this via-first technology can be used for varying range of sensor applications like microphone, oscillator, resonator, etc where CMOS compatibility and high temperature processing are the prime requirements. (paper)

  11. Probing the Morphology and Nanoscale Mechanics of Single Poly(N-isopropylacrylamide) Microgels Across the Lower-Critical-Solution Temperature by Atomic Force Microscopy

    NARCIS (Netherlands)

    Tagit, O.; Tomczak, N.; Vancso, Gyula J.

    2008-01-01

    Submicrometer-sized particles of poly(N-isopropylacrylamide) (PNIPAM) are synthesized by surfactant-free radical polymerization. The morphology and nanomechanical properties of individual, isolated PNIPAM microgel particles at the silicon/air and silicon/water interfaces, below and above the PNIPAM

  12. CMOS Monolithic Active Pixel Sensors (MAPS): developments and future outlook

    NARCIS (Netherlands)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J.A.; Metaxas, M.G.; Royle, G.J.; Speller, R.; Venanzi, C.; van der Stelt, P.F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J.M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-01-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end

  13. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process...

  14. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  15. Charge-Transfer CMOS Image Sensors : Device and Radiation Aspects

    NARCIS (Netherlands)

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-?m CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of

  16. CMOS current controlled fully balanced current conveyor

    Science.gov (United States)

    Chunhua, Wang; Qiujing, Zhang; Haiguang, Liu

    2009-07-01

    This paper presents a current controlled fully balanced second-generation current conveyor circuit (CF-BCCII). The proposed circuit has the traits of fully balanced architecture, and its X-Y terminals are current controllable. Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications. The CFBCCII circuits and the two filters were fabricated with chartered 0.35-μm CMOS technology; with ±1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW. Comparisons between measured and HSpice simulation results are also given.

  17. Analysis of bipolar and CMOS amplifiers

    CERN Document Server

    Sodagar, Amir M

    2007-01-01

    The classical approach to analog circuit analysis is a daunting prospect to many students, requiring tedious enumeration of contributing factors and lengthy calculations. Most textbooks apply this cumbersome approach to small-signal amplifiers, which becomes even more difficult as the number of components increases. Analysis of Bipolar and CMOS Amplifiers offers students an alternative that enables quick and intuitive analysis and design: the analysis-by-inspection method.This practical and student-friendly text demonstrates how to achieve approximate results that fall within an acceptable ran

  18. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  19. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  20. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  1. On the integration of memristors with CMOS using nanoimprint lithography

    Science.gov (United States)

    Xia, Qiangfei; Tong, W. M.; Wu, W.; Yang, J. J.; Li, X.; Robinett, W.; Cardinali, T.; Cumbie, M.; Ellenson, J. E.; Kuekes, P.; Williams, R. S.

    2009-03-01

    Memristors were vertically integrated with CMOS circuits using nanoimprint lithography (NIL), making a transistor/memeristor hybrid circuit. Several planarization technologies were developed for the CMOS substrates to meet the surface planarity requirement for NIL. Accordingly, different integration schemes were developed and optimized. UV-curable NIL (UV-NIL) using a double layer spin-on resists was carried out to pattern the electrodes for memristors. This is the first demonstration of NIL on active CMOS substrates that are fabricated in a CMOS fab. Our work demonstrates that NIL is compatible with commercial IC fabrication process. It was also demonstrated that the memristors are integratable with traditional CMOS to make hybrid circuits without changing the current infrastructure in IC industry.

  2. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  3. A CMOS high speed imaging system design based on FPGA

    Science.gov (United States)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  4. A novel colour-sensitive CMOS detector

    International Nuclear Information System (INIS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-01-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  5. CMOS preamplifier for low-capacitance detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gramegna, G. [Politecnico di Bari (Italy); O`Connor, P. [Brookhaven National Lab., Upton, NY (United States); Rehak, P. [Brookhaven National Lab., Upton, NY (United States); Hart, S. [Wayne State Univ. (United States)

    1997-05-01

    We present a new CMOS preamplifier and shaper, optimized for charge measurements with detectors of 0.1-1 pF capacitance. A self-adaptive biasing scheme with nonlinear pole-zero cancellation allows us to use an MOS device operated in the triode region as the DC feedback element while eliminating nonlinearity and sensitivity to supply, temperature, and process variations and accepting up to several {mu}A leakage current. The circuit is continuously sensitive and requires no external adjustments to set the feedback resistance. Secondary sources of noise are minimized subject to a power dissipation constraint. Implemented in a 1.2 {mu}m CMOS process, the preamplifier achieves an ENC of 35 e{sup -} + 58 e{sup -}/pF at 23 {mu}s shaping time at a power consumption of about 3.2 mW. The integrated preamp/shaper has 50 ns shaping time and the ENC is 120 e{sup -}. It has 0.3% nonlinearity over an input dynamic range of 0-5 fC. (orig.).

  6. Challenges of nickel silicidation in CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Breil, Nicolas [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Lavoie, Christian [IBM T.J. Watson Research Center, Yorktown Heights, NY (United States); Ozcan, Ahmet [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Baumann, Frieder [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Klymko, Nancy [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Nummy, Karen [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Sun, Bing [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Jordan-Sweet, Jean [IBM T.J. Watson Research Center, Yorktown Heights, NY (United States); Yu, Jian [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Zhu, Frank [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Narasimha, Shreesh [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Chudzik, Michael [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States)

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  7. Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

    Science.gov (United States)

    Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

    2015-07-21

    Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

  8. Intégration de transistor mono-électronique et transistor à atome unique sur CMOS

    OpenAIRE

    Deshpande, Veeresh

    2012-01-01

    Continuous scaling of MOSFET dimensions has led us to the era of nanoelectronics. Multigate FET (MuGFET) architecture with ‘nanowire channel' is being considered as one feasible enabler of MOSFET scaling to end-of-roadmap. Alongside classical CMOS or Moore's law scaling, many novel device proposals exploiting nanoscale phenomena have been made either. Single Electron Transistor (SET), with its unique ‘Coulomb Blockade' phenomena, and Single Atom Transistor (SAT), as an ultimately scaled trans...

  9. Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology

    OpenAIRE

    Tesanovic, Goran

    2003-01-01

    0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18...

  10. Corrosão por plasma para tecnologias CMOS e microssistemas

    OpenAIRE

    Claudia Reyes Betanzo

    2003-01-01

    Resumo: Esta tese apresenta os resultados do desenvolvimento e da otimização de uma tecnologia própria na área de fabricação de dispositivos CMOS e Microssistemas, realizados no Centro de Componentes Semicondutores da UNICAMP, pretendendo desenvolver processos em uma das técnicas mais críticas da microfabricação: corrosão de materiais por plasmas. Neste trabalho foram desenvolvidos processos de corrosão dos seguintes materiais: nitreto de silício (SiNx), óxido de silício (SiO2) e silício poli...

  11. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  12. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  13. Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

    Science.gov (United States)

    Li, Shu; Zhang, Tong

    2008-05-07

    Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

  14. CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography

    International Nuclear Information System (INIS)

    Esposito, M.; Waltham, C.; Allinson, N.M.; Anaxagoras, T.; Evans, P.M.; Poludniowski, G.; Green, S.; Parker, D.J.; Price, T.; Manolopoulos, S.; Nieto-Camero, J.

    2015-01-01

    Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs

  15. CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Evans, P M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Poludniowski, G; Price, T; Waltham, C; Allinson, N M

    2015-06-03

    Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs.

  16. Theoretical and experimental study of single particle tracking in extreme conditions: single photon imaging

    International Nuclear Information System (INIS)

    Cajgfinger, T.

    2012-10-01

    This manuscript presents my thesis on the high frame rate (500 frames / second) single-photon detector electron-bombarded CMOS (ebCMOS). The first section compares three ultra-sensitive detectors and their methods for improving photon sensitivity: the CMOS low noise (sCMOS), the electron-multiplying CCD (emCCD) with signal multiplication by pixel and the ebCMOS with amplification by applied electric field. The method developed to detect single photon impacts with intra-pixel resolution on the ebCMOS sensor is presented. The second section compares the localization accuracy of these detectors in extreme conditions of very low photon flux (<10 photons/frame). First the theoretical limit is calculated using the Cramer-Rao lower bound for significant parameter sets. An experimental comparison of the detectors is then described. The setup provides one or more point sources controlled in position, signal and background noise. The results allow a comparison of the experimental effectiveness, purity and localization accuracy. The last section describes two experiments with the ebCMOS camera. The first aims at tracking hundreds of quantum dots simultaneously at the Nanoptec center. The second focuses on the swimming of bacteria at the surface at the Joliot Curie Institute. The point sources tracking algorithm using single photons and the Kalman filter implementation developed for these experiments is also described. (author)

  17. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  18. Development of a CMOS process using high energy ion implantation

    International Nuclear Information System (INIS)

    Stolmeijer, A.

    1986-01-01

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  19. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  20. A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

    Science.gov (United States)

    Lauxtermann, Stefan; Fisher, John; McDougal, Michael

    2014-06-01

    In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

  1. Noise Properties of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1996-01-01

    model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model...... is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current...... sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current...

  2. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    Energy Technology Data Exchange (ETDEWEB)

    Cha, Bo Kyung, E-mail: goldrain99@kaist.ac.kr [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Jeon, Seongchae [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Seo, Chang-Woo [Department of Radiological Science, Yonsei University, Gangwon-do 220-710 (Korea, Republic of)

    2016-09-21

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd{sub 2}O{sub 2}S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  3. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    Science.gov (United States)

    Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

    2016-09-01

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 μm 1-poly/4-metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd2O2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  4. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    Science.gov (United States)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  5. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    consideration. In this work, delay and power metrics for both MCML and CMOS have been studied and a broader analysis of MCML is presented. Near minimum sized transistors are used and power consumption is measured for a wide variety of circuit blocks. The most important goal of this project is to evaluate......Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand...

  6. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  7. A safety monitoring system for taxi based on CMOS imager

    Science.gov (United States)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  8. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  9. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

    2016-12-31

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  10. Monolithic integration of a plasmonic sensor with CMOS technology

    Science.gov (United States)

    Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

    2017-02-01

    Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

  11. Depleted CMOS pixels for LHC proton–proton experiments

    International Nuclear Information System (INIS)

    Wermes, N.

    2016-01-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  12. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  13. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  14. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  15. Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

    Directory of Open Access Journals (Sweden)

    Hang Song

    2017-01-01

    Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

  16. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  17. Smart CMOS sensor for wideband laser threat detection

    Science.gov (United States)

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  18. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  19. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  20. Silicon CMOS architecture for a spin-based quantum computer.

    Science.gov (United States)

    Veldhorst, M; Eenink, H G J; Yang, C H; Dzurak, A S

    2017-12-15

    Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

  1. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  2. Modeling and simulation of TDI CMOS image sensors

    Science.gov (United States)

    Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

    2013-09-01

    In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

  3. The Effect of Home based Exercise on Treatment of Women with Poly Cystic Ovary Syndrome; a single-Blind Randomized Controlled Trial

    Directory of Open Access Journals (Sweden)

    Farzaneh Vasheghani-Farahani

    2017-01-01

    Full Text Available Background: The most common reproductive endocrine disorder of reproductive age women is a Poly cystic ovary syndrome (PCOS Metabolic syndrome has been more reported in patients with PCOS in comparison to general population. Few investigations have been performed to evaluate the independent effect of exercise on biochemical and clinical symptoms of patients with PCOS. The aim of the study was to find the effect of home base aerobic-strengthening exercises on anthropometric and hormonal variables of patients with PCOS.MaterialsandMethods:In this randomized controlled trial twenty women in the exercise group performed aerobic, strengthening exercises; the other 20 participants in the control group were advised to continue their previous physical activity pattern. Blood pressure, Waist to Hip ratio (WHR, BMI along with hormonal variables(including insulin related factors, sexual hormones and inflammatory factors were assessed at baselineand after the 12 week intervention.Results:16patients in the exercise group and 14 patients in control group finished the study. TheWHR (p<0.001 along with the blood level of insulin (p=0.016, FBS (p=0.044, Prolactine (p=0.022 and hsCRP (p=0.035 and HOMA index (p=0.009 were decreased significantly in the exercise group compared with the control group. No significant differences were found in lipid profile and sexual hormones between groups at the end of the study.Conclusion:We can conclude that 12 weeks combined aerobic-strengthening exercise program in women with poly cystic ovary syndrome can lead to a reduction of waist to hip ratio (WHR and some cardiovascular risk factors (including insulin, FBS, HOMA index and HsCRP along with an increase of prolactine level in these patients.

  4. A high-speed CMOS current op amp for very low supply voltage operation

    DEFF Research Database (Denmark)

    Bruun, Erik

    1994-01-01

    A CMOS implementation of a high-gain current mode operational amplifier (op amp) with a single-ended input and a differential output is described. This configuration is the current mode counterpart of the traditional voltage mode op amp. In order to exploit the inherent potential for high speed......, low voltage operation normally associated with current mode analog signal processing, the op amp has been designed to operate off a supply voltage of 1.5 V, and the signal path has been confined to N-channel transistors. With this design, a gain of 94 dB and a gain-bandwidth product of 65 MHz has been...

  5. CMOS circuits for piezoelectric energy harvesters efficient power extraction, interface modeling and loss analysis

    CERN Document Server

    Hehn, Thorsten

    2014-01-01

    This book deals with the challenge of exploiting ambient vibrational energy which can be used to power small and low-power electronic devices, e.g. wireless sensor nodes. Generally, particularly for low voltage amplitudes, low-loss rectification is required to achieve high conversion efficiency. In the special case of piezoelectric energy harvesting, pulsed charge extraction has the potential to extract more power compared to a single rectifier. For this purpose, a fully autonomous CMOS integrated interface circuit for piezoelectric generators which fulfills these requirements is presented.Due

  6. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  7. Total dose and dose rate radiation characterization of EPI-CMOS radiation hardened memory and microprocessor devices

    International Nuclear Information System (INIS)

    Gingerich, B.L.; Hermsen, J.M.; Lee, J.C.; Schroeder, J.E.

    1984-01-01

    The process, circuit discription, and total dose radiation characteristics are presented for two second generation hardened 4K EPI-CMOS RAMs and a first generation 80C85 microprocessor. Total dose radiation performance is presented to 10M rad-Si and effects of biasing and operating conditions are discussed. The dose rate sensitivity of the 4K RAMs is also presented along with single event upset (SEU) test data

  8. A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS.

    Science.gov (United States)

    Cruz, Hugo; Huang, Hong-Yi; Luo, Ching-Hsing; Lee, Shuenn-Yuh

    2017-04-01

    This paper presents a 10-channel time-of-flight application-specific integrated circuit (ASIC) for positron emission tomography in a 90 nm standard CMOS process. To overcome variations in channel-to-channel timing resolution caused by mismatch and process variations, adaptive biases and a digital-to-analog converter (DAC) are utilized. The main contributions of this work are as follows. First, multistage architectures reduce the total power consumption, and detection bandwidths of analog preamplifiers and comparators are increased to 1 and 1.5 GHz, respectively, relative to those in previous studies. Second, a total intrinsic electronic timing resolution of 9.71 ps root-mean-square (RMS) is achieved (13.88 ps peak and 11.8 ps average of the 10 channels in 5 ASICs). Third, the proposed architecture reduces variations in channel-to-channel timing resolution to 2.6 bits (equivalent to 4.17 ps RMS) by calibrating analog comparator threshold levels. A 181.5 ps full-width-at-half-maximum timing resolution is measured with an avalanche photo diode and a laser setup. The power consumption is 2.5 mW using 0.5 and 1.2 V power supplies. The proposed ASIC is implemented in a 90 nm TSMC CMOS process with a total area of 3.3 mm × 2.7 mm.

  9. Two- and multi-terminal CMOS/BiCMOS Si LED’s

    Science.gov (United States)

    du Plessis, Monuko; Aharoni, Herzl; Snyman, Lukas W.

    2005-02-01

    Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented. The differences observed between avalanche and low-voltage field emission LED performance are presented. It is shown that the low-voltage devices exhibit a square-law light intensity vs. reverse current non-linearity at low-current levels, but a linear dependency at higher currents, compared to the linear behaviour of avalanche devices at all current levels. The detail spectral characteristics of the field emission devices are investigated, showing that in the non-linear region of operation, the shape of the emitted spectrum changes, with reduced short wavelength generation at lower current levels. Bipolar junction transistor (BJT) multi-terminal devices are also discussed, and the square-law behaviour of these devices is presented.

  10. Aptameric Recognition-Modulated Electroactivity of Poly(4-Styrenesolfonic Acid)-Doped Polyaniline Films for Single-Shot Detection of Tetrodotoxin

    Science.gov (United States)

    Fomo, Gertrude; Waryo, Tesfaye T.; Sunday, Christopher E.; Baleg, Abd A.; Baker, Priscilla G.; Iwuoha, Emmanuel I.

    2015-01-01

    The work being reported is the first electrochemical sensor for tetrodotoxin (TTX). It was developed on a glassy carbon electrodes (C) that was modified with poly(4-styrenesolfonic acid)-doped polyaniline film (PANI/PSSA). An amine-end functionalized TTX-binding aptamer, 5′-NH2-AAAAATTTCACACGGGTGCCTCGGCTGTCC-3′ (NH2-Apt), was grafted via covalent glutaraldehyde (glu) cross-linking. The resulting aptasensor (C//PANI+/PSSA-glu-NH2-Apt) was interrogated by cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS) in sodium acetate buffer (NaOAc, pH 4.8) before and after 30 min incubation in standard TTX solutions. Both CV and EIS results confirmed that the binding of the analyte to the immobilized aptamer modulated the electrochemical properties of the sensor: particularly the charge transfer resistance (Rct) of the PANI+/PSSA film, which served as a signal reporter. Based on the Rct calibration curve of the TTX aptasensor, the values of the dynamic linear range (DLR), sensitivity and limit of detection (LOD) of the sensor were determined to be 0.23–1.07 ng·mL−1 TTX, 134.88 ± 11.42 Ω·ng·mL−1 and 0.199 ng·mL−1, respectively. Further studies are being planned to improve the DLR as well as to evaluate selectivity and matrix effects in real samples. PMID:26370994

  11. A low-power, high-speed, 9-channel germanium-silicon electro-absorption modulator array integrated with digital CMOS driver and wavelength multiplexer.

    Science.gov (United States)

    Krishnamoorthy, A V; Zheng, X; Feng, D; Lexau, J; Buckwalter, J F; Thacker, H D; Liu, F; Luo, Y; Chang, E; Amberg, P; Shubin, I; Djordjevic, S S; Lee, J H; Lin, S; Liang, H; Abed, A; Shafiiha, R; Raj, K; Ho, R; Asghari, M; Cunningham, J E

    2014-05-19

    We demonstrate the first germanium-silicon C-band electro-absorption based waveguide modulator array and echelle-grating-based silicon wavelength multiplexer integrated with a digital CMOS driver circuit. A 9-channel, 10Gbps SiGe electro-absorption wavelength-multiplexed modulator array consumed a power of 5.8mW per channel while being modulated at 10.25Gbps by 40nm CMOS drivers delivering peak-to-peak voltage swings of 2V, achieving a modulation energy-efficiency of ~570fJ/bit including drivers. Performance up to 25Gbps on a single-channel SiGe modulator and CMOS driver is also reported.

  12. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  13. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  14. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Orit Skorka

    2011-04-01

    Full Text Available Technologies to fabricate integrated circuits (IC with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  15. Design and fabrication of vertically-integrated CMOS image sensors.

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  16. Negative charge induced degradation of PMOSFETs with BF2-implanted p+-poly gate

    International Nuclear Information System (INIS)

    Lu, C.Y.; Sung, J.M.

    1989-01-01

    A new degradation phenomenon on thin gate oxide PMOS-FETs with BF 2 implanted p + -poly gate has been demonstrated and investigated. The cause of this type of degradation is a combination of the boron penetration through the gate oxide and charge trap generation due to the presence of fluorine in the gate oxide and some other processing-induced effects. The negative charge-induced degradation other than enhanced boron diffusion has been studied in detail here. The impact of this process-sensitive p + -poly gate structure on deep submicron CMOS process integration has been discussed. (author)

  17. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  18. CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

    National Research Council Canada - National Science Library

    An, S

    2001-01-01

    .... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

  19. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  20. Ostertagia spp., rumen fluke and liver fluke single- and poly-infections in cattle: An abattoir study of prevalence and production impacts in England and Wales.

    Science.gov (United States)

    Bellet, C; Green, M J; Vickers, M; Forbes, A; Berry, E; Kaler, J

    2016-09-15

    This study aims at investigating the occurrence, risk factors and production impacts on beef carcass parameters of three of the most important cattle helminth infections in England and Wales. Abomasa, reticulorumens and livers from healthy cattle were collected and examined post-mortem quarterly over a one year period in an abattoir in South-West England. Specific viscera from 974 cattle were collected, examined and scored for Ostertagia spp., adult rumen fluke and liver fluke lesions/presence. A total of 89%, 25% and 29% of the carcasses had lesions/presence of Ostertagia spp., rumen fluke and liver fluke, respectively, and 39% had presence of helminth co-infection. Animal demographic and carcass parameters associated with helminth infections were investigated using multilevel multinomial and multilevel linear mixed models respectively. After adjusting for other factors, significant differences in the distribution of helminth infections were observed among cattle by type of breed, animal category (cow, heifer, steer and young bull), age, season and concurrent helminth infections. Compared to carcasses free of helminths, carcasses presenting solely Ostertagia Spp. lesions or adult rumen fluke had significantly lower cold carcass weight (coef.: -30.58 [-50.92;-10.24] and -50.34 [-88.50;-12.18]) and fat coverage (coef.: -3.28 [-5.56;-1.00] and -5.49 [-10.28;-0.69]) and carcasses presenting solely liver fluke lesions had significantly lower conformation grade (coef.: -3.65 [-6.98;-0.32]). Presence of helminth poly-infections was negatively associated with cold carcass weight. Copyright © 2016 Elsevier B.V. All rights reserved.

  1. Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Aunet, Snorre

    2002-06-01

    This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

  2. Dense Heterogeneous Integration for InP Bi-CMOS Technology

    Science.gov (United States)

    2009-05-01

    many mixed signal applications, having circuits composed of both Si CMOS, which possesses low power dissipation and high transistor count, and...compound semiconductor transistors with high-speed high-voltage swing performance would be advantageous. In general, heterogeneous integration (HI) of...Fastest CMOS and HBTs  / >109LowHighCoSMOS Lags latest CMOS᝺ 6ModModSiGe HBT No precision fast device, low drive >109LowModCMOS BJT only

  3. A 12-bit 500KSPS cyclic ADC for CMOS image sensor

    Science.gov (United States)

    Li, Zhaohan; Wang, Gengyun; Peng, Leli; Ma, Cheng; Chang, Yuchun

    2015-03-01

    At present, single-slope analog-to-digital convertor (ADC) is widely used in the readout circuits of CMOS image sensor (CIS) while its main drawback is the high demand for the system clock frequency. The more pixels and higher ADC resolution the image sensor system needs, the higher system clock frequency is required. To overcome this problem in high dynamic range CIS system, this paper presents a 12-bit 500-KS/s cyclic ADC, in which the system clock frequency is 5MHz. Therefore, comparing with the system frequency of 2N×fS for the single-slope ADC, where fS, N is the sampling frequency and resolution, respectively, the higher ADC resolution doesn't need the higher system clock frequency. With 0.18μm CMOS process, the circuit layout is realized and occupies an area of 8μm×374μm. Post simulation results show that Signal-to-Noise-and-Distortion-Ratio (SNDR) and Efficient Number of Bit (ENOB) reaches 63.7dB and 10.3bit, respectively.

  4. Heavy ion-induced SEEs on 130 nm CMOS technology for LHC application - status and challenges

    International Nuclear Information System (INIS)

    Gabrielli, A.

    2011-01-01

    This work summarizes the status of the art of electronic designs, using CMOS technologies, to stand LHC and S-LHC radiation-hard environments. Radiation effects can be divided into Single Event Effects and Total Ionizing Dose effects, which are consequences of different interaction effects within the silicon and the electronics. These types of effects are commonly investigated and faced separately. The commercial 130 nm CMOS technology, today primarily proposed for SLHC electronic upgrades, only implements redundancies against the Single Event Effects'. On the contrary, the 250 nm technology node used in the past years for LHC experiments, was also hardened against the Total Ionizing Dose. Hence, the choice of the technology to be used for high-energy experiments is very crucial as it implies huge efforts in the designs of the components. In addition, an unavoidable technology scaling keeps moving toward ever-smaller sizes and this affects the availability of the silicon process for medium and long-term experiments.

  5. CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications

    Science.gov (United States)

    Broennimann, Christian

    2009-03-01

    Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

  6. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  7. Analytic models of CMOS logic in various regimes

    Directory of Open Access Journals (Sweden)

    Dokić Branko

    2014-01-01

    Full Text Available In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.

  8. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    Science.gov (United States)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J. A.; Metaxas, M. G.; Royle, G. J.; Speller, R.; Venanzi, C.; van der Stelt, P. F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J. M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS).

  9. Ultra High-Speed CMOS Circuits Beyond 100 GHz

    CERN Document Server

    Gharavi, Sam

    2012-01-01

    The book covers the CMOS-based millimeter wave circuits and devices and presents methods and design techniques to use CMOS technology for circuits operating beyond 100 GHz.� Coverage includes a detailed description of both active and passive devices, including modeling techniques and performance optimization. Various mm-wave circuit blocks are discussed, emphasizing their design distinctions from low-frequency design methodologies. This book also covers a device-oriented circuit design technique that is essential for ultra high speed circuits and gives some examples of device/circuit co-design that can be used for mm-wave technology. Offers a detailed description of high frequency device modeling from a circuit designer perspective; Presents a set of techniques for optimizing the performance of CMOS for mm-wave technology, including noise and low noise design for mm-wave; Introduces circuit/device co-design techniques. �

  10. High-speed nonvolatile CMOS/MNOS RAM

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

    1979-01-01

    A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

  11. Study by TCAD simulation of design and temperature effects of a CMOS inverter on the Latch-up sensitivity

    International Nuclear Information System (INIS)

    Al Youssef, Ahmad; Artola, Laurent; Hubert, Guillaume; Ducret, Samuel; Perrier, Franck

    2016-05-01

    The authors report a study by simulation of the electrical characteristics of a CMOS inverter with respect to the Latch-up phenomenon (SEL, single-event latch-up) by using the TCAD simulator (Technology Computer Aided Design). Triggering mechanisms of the Latch-up phenomenon have been studied, and this allowed sensitivity trends to be deduced with respect to the CMOS inverter geometrical parameters. A specific physical analysis of mechanisms in very low temperature resulted in the definition of a set of physical models (Shallow Level Impact Ionization, and so on) necessary for the modelling of the unexpected increase of SEL sensitivity. Results obtained under low temperature are in very good agreement with experimental measurements

  12. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  13. A mathematical model of the inline CMOS matrix sensor for investigation of particles in hydraulic liquids

    Science.gov (United States)

    Kornilin, DV; Kudryavtsev, IA

    2016-10-01

    One of the most effective ways to diagnose the state of hydraulic system is an investigation of the particles in their liquids. The sizes of such particles range from 2 to 200 gm and their concentration and shape reveal important information about the current state of equipment and the necessity of maintenance. In-line automatic particle counters (APC), which are built into hydraulic system, are widely used for determination of particle size and concentration. These counters are based on a single photodiode and a light emitting diode (LED); however, samples of liquid are needed for analysis using microscope or industrial video camera in order to get information about particle shapes. The act of obtaining the sample leads to contamination by other particles from the air or from the sample tube, meaning that the results are usually corrupted. Using the CMOS or CCD matrix sensor without any lens for inline APC is the solution proposed by authors. In this case the matrix sensors are put into the liquid channel of the hydraulic system and illuminated by LED. This system could be stable in arduous conditions like high pressure and the vibration of the hydraulic system; however, the image or signal from that matrix sensor needs to be processed differently in comparison with the signal from microscope or industrial video camera because of relatively short distance between LED and sensor. This paper introduces mathematical model of a sensor with CMOS and LED, which can be built into hydraulic system. It is also provided a computational algorithm and results, which can be useful for calculation of particle sizes and shapes using the signal from the CMOS matrix sensor.

  14. An introduction to deep submicron CMOS for vertex applications

    CERN Document Server

    Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

    2001-01-01

    Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

  15. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  16. Two CMOS BGR using CM and DTMOST techniques

    International Nuclear Information System (INIS)

    Mohd-Yasin, F.; Teh, Y.K.; Choong, F.; Reaz, M.B.I.

    2009-06-01

    Two CMOS BGR using current mode (0.044mm 2 ) and Dynamic Threshold MOST (0.017mm 2 ) techniques are designed on CMOS 0.18μm process. On-wafer measurement shows both circuits have minimum operating V DD 1.28V at 25 o C; taking 2.1μA and 0.5μA (maximum current 3.1μA and 1.1μA) and output voltage of 514mV and 457mV. Both circuits could support V DD range up to 4V required by passive UHF RFID. (author)

  17. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  18. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  19. On the Wrapping of Polyglycolide, Poly(Ethylene Oxide), and Polyketone Polymer Chains Around Single-Walled Carbon Nanotubes Using Molecular Dynamics Simulations

    Science.gov (United States)

    Rouhi, S.; Alizadeh, Y.; Ansari, R.

    2015-02-01

    By using molecular dynamics simulations, the interaction between a single-walled carbon nanotube and three different polymers has been studied in this work. The effects of various parameters such as the nanotube geometry and temperature on the interaction energy and radius of gyration of polymers have been explored. By studying the snapshots of polymers along the single-walled carbon nanotube, it has been shown that 50 ps can be considered as a suitable time after which the shape of polymer chains around the nanotube remains almost unchanged. It is revealed that the effect of temperature on the interaction energy and radius of gyration of polymers in the range of 250 to 500 K is not significant Also, it is shown that the interaction energy depends on the nanotube diameter.

  20. Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

    KAUST Repository

    Hussain, Aftab M.

    2016-12-01

    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

  1. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  2. Monolithic CMOS pixel detector for international linear collider ...

    Indian Academy of Sciences (India)

    the vertex detector elements and thus existing CCDs are not adequate. New CCD architectures are ... sizes of the 292 detector elements (chips) are summarized in tables 1 and 2. The baseline time structure of ... an R&D contract, we developed a conceptual design for a monolithic CMOS device. (chip) that achieves the ILC ...

  3. Monolithic CMOS pixel detector for international linear collider ...

    Indian Academy of Sciences (India)

    Toggle navigation. Logo of the Indian Academy of Sciences. Indian Academy of Sciences. Home · About ... Home; Journals; Pramana – Journal of Physics; Volume 69; Issue 6. Monolithic CMOS pixel detector for international linear ... Keywords. Vertex detector; international linear collider; linear collider; high energy physics.

  4. Direct readout of gaseous detectors with tiled CMOS circuits

    International Nuclear Information System (INIS)

    Visschers, J.L.; Blanco Carballo, V.; Chefdeville, M.; Colas, P.; Graaf, H. van der; Schmitz, J.; Smits, S.; Timmermans, J.

    2007-01-01

    A coordinated design effort is underway, exploring the three-dimensional direct readout of gaseous detectors by an anode plate equipped with a tiled array of many CMOS pixel readout ASICs, having amplification grids integrated on their topsides and being contacted on their backside

  5. Characterisation of a CMOS charge transfer device for TDI imaging

    International Nuclear Information System (INIS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-01-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques

  6. Quantification of Shallow-junction Dopant Loss during CMOS Process

    International Nuclear Information System (INIS)

    Buh, G.H.; Park, T.; Jee, Y.; Hong, S.J.; Ryoo, C.; Yoo, J.; Lee, J.W.; Yon, G.H.; Jun, C.S.; Shin, Y.G.; Chung, U.-In; Moon, J.T.

    2005-01-01

    We analyzed dopant concentration and profiles in source drain extension (SDE) by using in-line low energy electron induced x-ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet-resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet-etching removal during photo resist cleaning, 2) out-diffusion, and 3) deactivation by post-thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively

  7. Design for manufacturability and yield for nano-scale CMOS

    CERN Document Server

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  8. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  9. High-temperature complementary metal oxide semiconductors (CMOS)

    International Nuclear Information System (INIS)

    McBrayer, J.D.

    1979-10-01

    Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

  10. A CMOS rail-to-rail linear VI-converter

    NARCIS (Netherlands)

    Vervoort, P.P.; Vervoort, P.P.; Wassenaar, R.F.

    1995-01-01

    A linear CMOS VI-converter operating in strong inversion with a common-mode input range from the negative to the positive supply rail is presented. The circuit consists of three linear VI-converters based on the difference of squares principle. Two of these perform the actual V to I conversion,

  11. High-temperature complementary metal oxide semiconductors (CMOS)

    Energy Technology Data Exchange (ETDEWEB)

    McBrayer, J.D.

    1979-10-01

    Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300/sup 0/C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed.

  12. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

  13. A CMOS four-quadrant analog current multiplier

    NARCIS (Netherlands)

    Wiegerink, Remco J.

    1991-01-01

    A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual

  14. CMOS-based avalanche photodiodes for direct particle detection

    International Nuclear Information System (INIS)

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-01-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

  15. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  16. Monolithic CMOS pixel detector for international linear collider ...

    Indian Academy of Sciences (India)

    the vertex detector elements and thus existing CCDs are not adequate. New CCD architectures are under development [2] but have yet to achieve the required perfor- mance. For these reasons there is an increased importance on the development of monolithic CMOS pixel detectors that allow extremely fast non-sequential ...

  17. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  18. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2017-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  19. CMOS monolithic pixel sensors research and development at LBNL

    Indian Academy of Sciences (India)

    Abstract. This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS ...

  20. 65 nm CMOS Monolithically Integrated sub-THz transmitter

    NARCIS (Netherlands)

    Hu, X.; Tripodi, L.; Matters-Kammerer, M.K.; Cheng, S.; Rydberg, A.

    2011-01-01

    This letter presents a transmitter for sub-THz radiation (up to 160GHz), which consists of a nonlinear transmission line (NLTL) and anextremely wideband (EWB) slot antenna on a silicon substrate of lowresistivity (10 Ohms•cm). The fabrication was realized using a commercially available 65 nm CMOS

  1. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  2. A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

    Science.gov (United States)

    Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

    2014-10-01

    This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

  3. Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

    Science.gov (United States)

    Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

    2014-01-01

    This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  4. Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

    Science.gov (United States)

    Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

    2008-02-01

    Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

  5. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  6. A study of phase noise in colpitts and LC-tank CMOS oscillators

    DEFF Research Database (Denmark)

    Andreani, Pietro; Wang, Xiaoyan; Vandi, Luca

    2005-01-01

    very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise figure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypes......This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f(2) phase-noise region are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under...... of both Colpitts and LC-tank oscillators have been implemented in a 0.35-mu m CMOS process. The best performance of the LC-tank oscillators shows a phase noise of -142 dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of similar to 189 d...

  7. Using a large area CMOS APS for direct chemiluminescence detection in Western blotting electrophoresis

    Science.gov (United States)

    Esposito, Michela; Newcombe, Jane; Anaxagoras, Thalis; Allinson, Nigel M.; Wells, Kevin

    2012-03-01

    Western blotting electrophoretic sequencing is an analytical technique widely used in Functional Proteomics to detect, recognize and quantify specific labelled proteins in biological samples. A commonly used label for western blotting is Enhanced ChemiLuminescence (ECL) reagents based on fluorescent light emission of Luminol at 425nm. Film emulsion is the conventional detection medium, but is characterized by non-linear response and limited dynamic range. Several western blotting digital imaging systems have being developed, mainly based on the use of cooled Charge Coupled Devices (CCDs) and single avalanche diodes that address these issues. Even so these systems present key drawbacks, such as a low frame rate and require operation at low temperature. Direct optical detection using Complementary Metal Oxide Semiconductor (CMOS) Active Pixel Sensors (APS)could represent a suitable digital alternative for this application. In this paper the authors demonstrate the viability of direct chemiluminescent light detection in western blotting electrophoresis using a CMOS APS at room temperature. Furthermore, in recent years, improvements in fabrication techniques have made available reliable processes for very large imagers, which can be now scaled up to wafer size, allowing direct contact imaging of full size western blotting samples. We propose using a novel wafer scale APS (12.8 cm×13.2 cm), with an array architecture using two different pixel geometries that can deliver an inherently low noise and high dynamic range image at the same time representing a dramatic improvement with respect to the current western blotting imaging systems.

  8. An investigation into the use of CMOS active pixel technology in image-guided radiotherapy

    International Nuclear Information System (INIS)

    Osmond, J P F; Holland, A D; Harris, E J; Ott, R J; Evans, P M; Clark, A T

    2008-01-01

    The increased intelligence, read-out speed, radiation hardness and potential large size of CMOS active pixel sensors (APS) gives them a potential advantage over systems currently used for verification of complex treatments such as IMRT and the tracking of moving tumours. The aim of this work is to investigate the feasibility of using an APS-based system to image the megavoltage treatment beam produced by a linear accelerator (Linac), and to demonstrate the logic which may ultimately be incorporated into future sensor and FPGA design to evaluate treatment and track motion. A CMOS APS was developed by the MI 3 consortium and incorporated into a megavoltage imaging system using the standard lens and mirror configuration employed in camera-based EPIDs. The ability to resolve anatomical structure was evaluated using an Alderson RANDO head phantom, resolution evaluated using a quality control (QC3) phantom and contrast using an in-house developed phantom. A complex intensity-modulated radiotherapy (IMRT) treatment was imaged and two algorithms were used to determine the field-area and delivered dose, and the position of multi-leaf collimator (MLC) leaves off-line. Results were compared with prediction from the prescription and found to agree within a single image frame time for dose delivery and 0.02-0.03 cm for the position of collimator leaves. Such a system therefore shows potential as the basis for an on-line verification system capable of treatment verification and monitoring patient motion

  9. An investigation into the use of CMOS active pixel technology in image-guided radiotherapy

    Science.gov (United States)

    Osmond, J. P. F.; Harris, E. J.; Clark, A. T.; Ott, R. J.; Holland, A. D.; Evans, P. M.

    2008-06-01

    The increased intelligence, read-out speed, radiation hardness and potential large size of CMOS active pixel sensors (APS) gives them a potential advantage over systems currently used for verification of complex treatments such as IMRT and the tracking of moving tumours. The aim of this work is to investigate the feasibility of using an APS-based system to image the megavoltage treatment beam produced by a linear accelerator (Linac), and to demonstrate the logic which may ultimately be incorporated into future sensor and FPGA design to evaluate treatment and track motion. A CMOS APS was developed by the MI3 consortium and incorporated into a megavoltage imaging system using the standard lens and mirror configuration employed in camera-based EPIDs. The ability to resolve anatomical structure was evaluated using an Alderson RANDO head phantom, resolution evaluated using a quality control (QC3) phantom and contrast using an in-house developed phantom. A complex intensity-modulated radiotherapy (IMRT) treatment was imaged and two algorithms were used to determine the field-area and delivered dose, and the position of multi-leaf collimator (MLC) leaves off-line. Results were compared with prediction from the prescription and found to agree within a single image frame time for dose delivery and 0.02-0.03 cm for the position of collimator leaves. Such a system therefore shows potential as the basis for an on-line verification system capable of treatment verification and monitoring patient motion.

  10. Advancing the technology of monolithic CMOS detectors for use as x-ray imaging spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Amato, Stephen

    2017-08-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff has been engaged in a multi year effort to advance the technology of monolithic back-thinned CMOS detectors for use as X-ray imaging spectrometers. The long term goal of this campaign is to produce X-ray Active Pixel Sensor (APS) detectors with Fano limited performance over the 0.1-10keV band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Such devices would be ideal for candidate post 2020 decadal missions such as LYNX and for smaller more immediate applications such as CubeX. Devices from a recent fabrication have been back-thinned, packaged and tested for soft X-ray response. These devices have 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels with ˜135μV/electron sensitivity and a highly parallel signal chain. These new detectors are fabricated on 10μm epitaxial silicon and have a 1k by 1k format. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting X-ray astronomy. These features include read noise, X-ray spectral response and quantum efficiency.

  11. An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

    International Nuclear Information System (INIS)

    Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin'an

    2009-01-01

    One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 x 200 μm 2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

  12. Photoluminescence spectral study of single cadmium selenide/zinc sulfide colloidal nanocrystals in poly(methyl methacrylate) and quantum dots molecules

    Science.gov (United States)

    Shen, Yaoming

    Quantum dots (QDs)and Nano-crystals (NCs) have been studies for decades. Because of the nanoscale quantum confinement, delta shape like energy density states and narrowband emitters properties, they hold great promise for numerous optoelectronics and photonics applications. They could be used for tunable lasers, white LED, Nano-OLED, non-volatile memory and solar cells. They are also the most promising candidates for the quantum computing. The benefits for NCs over QDs is that NCs can be incorporated into a variety of polymers as well as thin films of bulk semiconductors. These exceptional flexibility and structural control distinguish NCs from the more traditional QD structures fabricated using epitaxial growth techniques. In my research of work, I studied the photoluminescence (PL) and absorption character of ensemble NCs incorporated in Polymethyl methacrylate (PMMA). To understand the behavior of the NCs in PMMA, it is important to measure a singe NC to avoid the inhomogenous broading of many NCs. So I particularly studied the behavior of a single NC in PMMA matrix. A microphotoluminescence setup to optically isolate a single nanocrystal is used. Random spectral shift and blinking behavior (on and off) are found. Addition to that, two color spectral shifting, is a major phenomena found in the system. Other interesting results such as PL intensity changes (decreasing or increasing with time) and quenching effect are observed and explained too. From the correlation function, we can distinguish the phonon replicas. The energy of these phonons can be calculated very accurately from the experiment result. The Huang-Rhys factors can be estimated too. Self-assembled semiconductor quantum dots (QDs), from highly strained-layer heteroepitaxy in the Stranski-Krastanow (S-K) growth mode, have been intensively studied because of the delta-function-like density of states, which is significant for optoelectronic applications. Spontaneous formation of semiconductor quantum

  13. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  14. Selective Determination of Serotonin on Poly(3,4-ethylenedioxy pyrrole)-single-walled Carbon Nanotube-Modified Glassy Carbon Electrodes

    International Nuclear Information System (INIS)

    Kim, Seul Ki; Bae, Si Ra; Ahmed, Mohammad Shamsuddin; You, Jung Min; Jeon, Seung Won

    2011-01-01

    An electrochemically-modified electrode [P(EDOP-SWNTs)/GCE] was prepared by electropolymerization of 3,4-ethylenedioxy pyrrole (EDOP) single-walled carbon nanotubes (SWNTs) on the surface of a glassy carbon electrode (GCE) and characterized by SEM, CV, and DPV. This modified electrode was employed as an electrochemical biosensor for the selective determination of serotonin concentrations at pH 7.4 and exhibited a typical enhanced effect on the current response of serotonin with a lower oxidation overpotential. The linear response was in the range of 1.0 x 10 -7 to 1.0 x 10 -5 M, with a correlation coefficient of 0.998 on the anodic current. The lower detection limit was calculated as 5.0 nM. Due to the relatively low currents and difference of potentials in the electrochemical responses of uric acid (UA), ascorbic acid (AA), and dopamine (DA), the modified electrode was a useful and effective sensing device for the selective and sensitive serotonin determination in the presence of UA, AA, and DA

  15. Selective Determination of Serotonin on Poly(3,4-ethylenedioxy pyrrole)-single-walled Carbon Nanotube-Modified Glassy Carbon Electrodes

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Seul Ki; Bae, Si Ra; Ahmed, Mohammad Shamsuddin; You, Jung Min; Jeon, Seung Won [Chonnam National University, Gwangju (Korea, Republic of)

    2011-04-15

    An electrochemically-modified electrode [P(EDOP-SWNTs)/GCE] was prepared by electropolymerization of 3,4-ethylenedioxy pyrrole (EDOP) single-walled carbon nanotubes (SWNTs) on the surface of a glassy carbon electrode (GCE) and characterized by SEM, CV, and DPV. This modified electrode was employed as an electrochemical biosensor for the selective determination of serotonin concentrations at pH 7.4 and exhibited a typical enhanced effect on the current response of serotonin with a lower oxidation overpotential. The linear response was in the range of 1.0 x 10{sup -7} to 1.0 x 10{sup -5} M, with a correlation coefficient of 0.998 on the anodic current. The lower detection limit was calculated as 5.0 nM. Due to the relatively low currents and difference of potentials in the electrochemical responses of uric acid (UA), ascorbic acid (AA), and dopamine (DA), the modified electrode was a useful and effective sensing device for the selective and sensitive serotonin determination in the presence of UA, AA, and DA.

  16. Combined single-crystal X-ray and neutron diffraction analysis of the structure of the (Zr6CI18H5)3- poly-anion

    International Nuclear Information System (INIS)

    Cotton, F.A.; Chen, L.; Schultz, A.J.

    1996-01-01

    The octahedral hexa zirconium compound (Ph 4 P) 3 [Zr 6 Cl 18 H 5 ] has been structurally characterized by a combined analysis of single-crystal X-ray and time-of-flight (TOF) neutron diffraction data. The space group is tetragonal, I4 1 /a, Z = 8, with lattice constants at 123 K of a = 32.957(8), c 15.001(3) Angstrom, V = 16,294(6) Angstrom 3 . Difference Fourier maps based on the neutron data exhibited negative troughs on the triangular faces of the hexa zirconium octahedron which were introduced into the structure as hydrogen atoms. Refinement of the atomic positional and occupancy parameters for the hydrogen atoms resulted in about 0.7 H atoms on each triangular face for a total of 5.47(15) hydrogen atoms atoms per hexa zirconium cluster, in good accord with the 1 H NMR measurement (5.0) and the theoretical expectation of 5. The Zr - (μ 3 H) distances range from 1.8 to 2.1 Angstrom. (authors)

  17. Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

    Science.gov (United States)

    Kenter, Almus

    The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

  18. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    Directory of Open Access Journals (Sweden)

    Chang-Hung Lee

    2014-05-01

    Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  19. Poly-Frobenius-Euler polynomials

    Science.gov (United States)

    Kurt, Burak

    2017-07-01

    Hamahata [3] defined poly-Euler polynomials and the generalized poly-Euler polynomials. He proved some relations and closed formulas for the poly-Euler polynomials. By this motivation, we define poly-Frobenius-Euler polynomials. We give some relations for this polynomials. Also, we prove the relationships between poly-Frobenius-Euler polynomials and Stirling numbers of the second kind.

  20. Applications of Si/SiGe heterostructures to CMOS devices

    International Nuclear Information System (INIS)

    Sidek, R.M.

    1999-03-01

    For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

  1. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  2. Oriented Poly(dialkylstannane)s

    DEFF Research Database (Denmark)

    Choffat, Fabien; Fornera, Sara; Smith, Paul

    2008-01-01

    The inorganic (or 'organometallic') polymers poly(dibutylstannane), poly(dioctylstannane), and poly(didodecylstannane) have been oriented by shear forces, the tensile drawing of blends with polyethylene, and deposition from solution onto glass slides coated with all oriented, friction...

  3. A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

    International Nuclear Information System (INIS)

    Zheng Yongzheng; Xia Lingli; Li Weinan; Huang Yumei; Hong Zhiliang

    2009-01-01

    A fast-hopping 3-band (mode 1) multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 x 1.8 mm 2 .

  4. A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

    International Nuclear Information System (INIS)

    Chen Pufeng; Li Zhiqiang; Wang Xiaosong; Zhang Haiying; Ye Tianchun

    2010-01-01

    An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time. It incorporates two phase-locked loops and one single-sideband (SSB) mixer. A 2-to-1 multiplexer with high linearity is proposed. A modified wideband SSB mixer, quadrature VCO, and layout techniques are also employed. The synthesizer is fabricated in a 0.18 μm CMOS process and operates at 1.5-1.8 V while consuming 40 mA current. The measured phase noise is -128 dBc/Hz at 10 MHz offset, and the sideband rejection is -22 dBc at 7.656 GHz.

  5. A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

    Energy Technology Data Exchange (ETDEWEB)

    Chen Pufeng; Li Zhiqiang; Wang Xiaosong; Zhang Haiying; Ye Tianchun, E-mail: chenpufeng@ime.ac.c [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2010-07-15

    An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time. It incorporates two phase-locked loops and one single-sideband (SSB) mixer. A 2-to-1 multiplexer with high linearity is proposed. A modified wideband SSB mixer, quadrature VCO, and layout techniques are also employed. The synthesizer is fabricated in a 0.18 {mu}m CMOS process and operates at 1.5-1.8 V while consuming 40 mA current. The measured phase noise is -128 dBc/Hz at 10 MHz offset, and the sideband rejection is -22 dBc at 7.656 GHz.

  6. A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

    Energy Technology Data Exchange (ETDEWEB)

    Zheng Yongzheng; Xia Lingli; Li Weinan; Huang Yumei; Hong Zhiliang, E-mail: yumeihuang@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-09-15

    A fast-hopping 3-band (mode 1) multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 {mu}m CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 x 1.8 mm{sup 2}.

  7. Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

    Science.gov (United States)

    You, Y.; Huang, D.; Chen, J.; Gong, D.; Liu, T.; Ye, J.

    2014-01-01

    We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.

  8. Analytical Expressions for Harmonic Distortion at Low Frequencies due to Device Mismatch in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1999-01-01

    One of the origins of harmonic distortion in current mirrors is the inevitable mismatch between the mirror transistors. In this brief we examine both single current mirrors and complementary class AB current mirrors and develop analytical expressions for the mismatch induced harmonic distortion....... The expressions are verified through simulations and are used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. The distortion model is combined with well known statistical models for the device mismatch in order to establish a relation between geometrical...... parameters, distortion and production yield. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low distortion is not achievable....

  9. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    KAUST Repository

    Wang, Zhenwei

    2015-04-20

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

  10. CMOS compatible route for GaAs based large scale flexible and transparent electronics

    KAUST Repository

    Nour, Maha A.

    2014-08-01

    Flexible electronics using gallium arsenide (GaAs) for nano-electronics with high electron mobility and optoelectronics with direct band gap are attractive for many applications. Here we describe a state-of-the-art CMOS compatible batch fabrication process of transforming traditional electronic circuitry into large-area flexible, semitransparent platform. We show a simple release process for peeling off 200 nm of GaAs from 200 nm GaAs/300 nm AlAs stack on GaAs substrate using diluted hydrofluoric acid (HF). This process enables releasing a single top layer compared to peeling off all layers with small sizes at the same time. This is done utilizing a network of release holes which contributes to the better transparency (45 % at 724 nm wavelength) observed.

  11. Integrating Metal-Oxide-Decorated CNT Networks with a CMOS Readout in a Gas Sensor

    Directory of Open Access Journals (Sweden)

    Suhwan Kim

    2012-02-01

    Full Text Available We have implemented a tin-oxide-decorated carbon nanotube (CNT network gas sensor system on a single die. We have also demonstrated the deposition of metallic tin on the CNT network, its subsequent oxidation in air, and the improvement of the lifetime of the sensors. The fabricated array of CNT sensors contains 128 sensor cells for added redundancy and increased accuracy. The read-out integrated circuit (ROIC was combined with coarse and fine time-to-digital converters to extend its resolution in a power-efficient way. The ROIC is fabricated using a 0.35 µm CMOS process, and the whole sensor system consumes 30 mA at 5 V. The sensor system was successfully tested in the detection of ammonia gas at elevated temperatures.

  12. Micromachined high-performance RF passives in CMOS substrate

    International Nuclear Information System (INIS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-01-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

  13. Digital autoradiography using room temperature CCD and CMOS imaging technology

    International Nuclear Information System (INIS)

    Cabello, Jorge; Bailey, Alexis; Kitchen, Ian; Prydderch, Mark; Clark, Andy; Turchetta, Renato; Wells, Kevin

    2007-01-01

    CCD (charged coupled device) and CMOS imaging technologies can be applied to thin tissue autoradiography as potential imaging alternatives to using conventional film. In this work, we compare two particular devices: a CCD operating in slow scan mode and a CMOS-based active pixel sensor, operating at near video rates. Both imaging sensors have been operated at room temperature using direct irradiation with images produced from calibrated microscales and radiolabelled tissue samples. We also compare these digital image sensor technologies with the use of conventional film. We show comparative results obtained with 14 C calibrated microscales and 35 S radiolabelled tissue sections. We also present the first results of 3 H images produced under direct irradiation of a CCD sensor operating at room temperature. Compared to film, silicon-based imaging technologies exhibit enhanced sensitivity, dynamic range and linearity

  14. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A. Jr.; Estreich, D.B.; Dawes, W.R. Jr.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

  15. Submicron CMOS technologies for high energy physics and space applications

    CERN Document Server

    Anelli, G; Faccio, F; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W

    2001-01-01

    The radiation environment present in some of today's High-Energy Physics (HEP) experiments and in space has a detrimental influence on the integrated circuits working in these environments. Special technologies, called radiation hardened, have been used in the past to prevent the radiation-induced degradation. In the last decades, the market of these special technologies has undergone a considerable shrinkage, rendering them less reliably available and far more expensive than today's mainstream technologies. An alternative approach is to use a deep submicron CMOS technology. The most sensitive part to radiation effects in a MOS transistor is the gate oxide. One way to reduce the effects of ionizing radiation in the gate oxide is to reduce its thickness, which is a natural trend in modern technologies. Submicron CMOS technologies seem therefore a good candidate for implementing radiation-hardened integrated circuits using a commercial, inexpensive technology. Nevertheless, a certain number of radiation-induced...

  16. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  17. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  18. A toroidal inductor integrated in a standard CMOS process

    DEFF Research Database (Denmark)

    Vandi, Luca; Andreani, Pietro; Temporiti, Enrico

    2007-01-01

    This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches are......H and 1.1 nH up to 20 GHz (physical limit for the measurement equipment) and a quality factor approaching 10 at 15 GHz. No self-resonance is observed within the measurement range.......This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches...

  19. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    CERN Document Server

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  20. Smart CMOS image sensor for lightning detection and imaging

    OpenAIRE

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-01-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel fra...

  1. Loss Optimization of Coplanar Strips for CMOS RFICs

    OpenAIRE

    Arif, Muhammad S; Peroulis, Dimitrios

    2009-01-01

    An optimization scheme for minimizing substrate losses in coplanar strips (CPS) transmission line on CMOS grade low resistivity silicon substrate with SU-8 polymer as dielectric interface layer, is presented. It is shown that through careful selection of CPS linewidth, the substrate losses can be sufficiently reduced for a given dielectric layer thickness. For a 100 Omega CPS line with SU-8 polymer as dielectric, the optimized linewidth has been found to be around three times the SU-8 layer t...

  2. Performance Analysis of Visible Light Communication Using CMOS Sensors.

    Science.gov (United States)

    Do, Trong-Hop; Yoo, Myungsik

    2016-02-29

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis.

  3. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  4. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6...

  5. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  6. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers.

    Science.gov (United States)

    Doll, Joseph C; Petzold, Bryan C; Ninan, Biju; Mullapudi, Ravi; Pruitt, Beth L

    2010-01-01

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d(33f), d(31) and d(33) of up to 2.9, -1.9 and 6.5 pm V(-1), respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

  7. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A.

    2017-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  8. CMOS integration of inkjet-printed graphene for humidity sensing.

    Science.gov (United States)

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-11-30

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  9. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  10. CMOS integration of inkjet-printed graphene for humidity sensing

    Science.gov (United States)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  11. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

    2017-09-01

    This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

  12. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  13. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  14. Poly(furfuryl alcohol)

    Indian Academy of Sciences (India)

    This paper describes a facile hydrothermal approach to the large-scale synthesis of well-dispersed poly(furfuryl alcohol) (PFA) nanospheres with an average diameter of 350 nm in the presence of poly(vinyl pyrrolidone) (PVP). Scanning electron microscopy and transmission electron microscopy studies showed that ...

  15. Novel processes for modular integration of silicon-germanium MEMS with CMOS electronics

    Science.gov (United States)

    Low, Carrie Wing-Zin

    Equipment control, process development and materials characterization for LPCVD poly-SiGe for MEMS applications are investigated in this work. In order to develop a repeatable process in an academic laboratory, equipment monitoring methods are implemented and new process gases are explored. With the dopant gas BCl3, the design-of-experiments technique is used to study the dependencies of deposition rate, resistivity, average residual stress, strain gradient and wet etch rate in hydrogen-peroxide. Structural layer requirements for general MEMS applications are met within the process temperature constraint imposed by CMOS electronics. However, the strain gradient required for inertial sensor applications is difficult to achieve with as-deposited films. Approaches to reduce the strain gradient of LPCVD poly-SiGe are investigated. Correlation between the strain gradient and film microstructure is found using stress-depth profiling and cross-sectional TEM analysis. The effects of film deposition conditions on film microstructure are also determined. Boron-doped poly-SiGe films generally have vertically oriented grains---either conical or columnar in shape. Films with conical grain structure have large strain gradient due to highly compressive stress in the lower (initially deposited) region of the film. Films with small strain gradient usually have columnar grain structure with low defect density. It is also found that the uniformity of films deposited in a batch LPCVD reactor can be improved by increasing the deposited film thickness, using a proper seeding layer, and/or depositing the film in multiple layers. The best strain gradient achieved in our academic research laboratory is 1.1x10-6 mum-1 for a ˜3.5 mum thick film deposited at 410°C in 8 hours, with a worst-case variation across a 150 mm-diameter wafer of 1.6x10 -5 mum-1 and a worse-case variation across a load of twenty-five wafers of 7x10-5 mum-1. The effects of post-deposition annealing and argon

  16. The design, simulation, and fabrication of a BiCMOS VLSI digitally programmable GIC filter

    OpenAIRE

    Milne, Paul R.

    2001-01-01

    This thesis used a previously-designed programmable GIC filter as a basis in which to incorporate a BiCMOS operational amplifier. An NPN bipolar transistor layout was designed and incorporated into an opamp layout, which was a modified version of a CMOS-only design. The BiCMOS opamp was simulated using Silvaco SmartSpice and showed considerable improvement over its CMOS equivalent. Additional improvements were made to the GIC filter to include a passgate with reduced resistance, and a correct...

  17. Optimization of CMOS active pixels for high resolution digital radiography

    International Nuclear Information System (INIS)

    Kim, Young Soo

    2007-02-01

    CMOS image sensors have poorer performance compared to conventional charge coupled devices (CCDs). Since CMOS Active Pixel Sensors (APSs) in general have higher temporal noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range and superior signal-to-noise ratio as CCDs. In view of electronic noise, the main source for the CMOS APS is the pixel, along with other signal processing blocks such as row and column decoder, analog signal processor (ASP), analog-to-digital converter (ADC), and timing and control logic circuitry. Therefore, it is important and necessary to characterize noise of the active pixels in CMOS APSs. We developed our theoretical noise model to account for the temporal noise in active pixels, and then found out the optimum design parameters such as fill actor, each size of the three transistors (source follower, row selection transistor, bias transistor) comprising active pixels, bias current, and load capacitance that can have the maximum signal-to-noise ratio. To develop the theoretical noise model in active pixels, we considered the integration noise of the photodiode and the readout noise of the transistors related to readout. During integration, the shot noise due to the dark current and photocurrent, during readout, the thermal and flicker noise were considered. The developed model can take the input variables such as photocurrent, capacitance of the photodiode, integration time, transconductance of the transistors, channel resistance of the transistors, gate-to-source capacitance of the follower, and load capacitance etc. To validate our noise model, two types of test structures have been realized. Firstly, four types of photodiodes (n diffusion /p substrate , n well /p substrate , n diffusion /p epitaxial /p substrate , n well /p epitaxial /p substrate ) used in CMOS active pixels were fabricated in order to choose the photodiode type having the best SNR

  18. A novel high reliability CMOS SRAM cell

    Energy Technology Data Exchange (ETDEWEB)

    Xie Chengmin; Wang Zhongfang; Wu Longsheng; Liu Youbao, E-mail: hglnew@sina.com [Computer Research and Design Department, Xi' an Microelectronic Technique Institutes, Xi' an 710054 (China)

    2011-07-15

    A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor, the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell. So the hold, read SNM and critical charge increase greatly. The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors. The hold and read SNM of the new cell increase by 72% and 141.7%, respectively, compared to the 6T design, but it has a 54% area overhead and read performance penalty. According to these features, this novel cell suits high reliability applications, such as aerospace and military. (semiconductor integrated circuits)

  19. Large-area CMOS solid-state photomultipliers and recent developments

    Energy Technology Data Exchange (ETDEWEB)

    Johnson, Erik B., E-mail: ejohnson@rmdinc.com [Radiation Monitoring Devices, Inc., 44 Hunt Street, Watertown, MA 02472 (United States); Stapels, Christopher J.; Xiao Jiechen [Radiation Monitoring Devices, Inc., 44 Hunt Street, Watertown, MA 02472 (United States); Augustine, Frank L. [Augustine Engineering, 2115 Park Dale Lane, Encinitas, CA 92024 (United States); Christian, James F. [Radiation Monitoring Devices, Inc., 44 Hunt Street, Watertown, MA 02472 (United States)

    2011-10-01

    The CMOS solid-state photomultiplier (SSPM) is an array of Geiger avalanche photodiodes (GPD) read out in parallel. These devices are not susceptible to magnetic fields, less expensive to fabricate than many other photodetector technologies, compact, and allow for on-chip integration of signal processing circuits. A number of nuclear detection applications require detector sizes on the order of 1 cm. Standard silicon fabrication technology limits the size of the SSPM die, and tiling of the silicon die can result in large-area devices but results in dead space between die for bonding purposes. Radiation Monitoring Devices (RMD) has fabricated 1x1 cm SSPM arrays on a single die. The size of these devices is large enough to provide an alternative detector for scintillation detector applications compared to photomultiplier tubes. Although the size increases the dark noise, we will demonstrate that the large-area SSPM can provide a PMT-like response for {sup 22}Na gamma rays using an LYSO crystal. Each of the noise terms associated with the large-area SSPM is discussed, quantifying the cross talk and after pulse multipliers, which are scaling factors to the gain to account for the additional output charge from the SSPM. The excess noise factor associated with cross talk and after pulsing has a linear dependence on the multiplier term. The signal and noise terms have been compiled to provide the best operating voltage of roughly 6 V above breakdown for a 1x1 cm CMOS SSPM to be operated with a short integration time (<10 ns) and at 0 deg. C.

  20. Analytische Modellierung des Zeitverhaltens und der Verlustleistung von CMOS-Gattern

    Directory of Open Access Journals (Sweden)

    R. Geißler

    2003-01-01

    Full Text Available In modernen CMOS-Technologien werden die Verzögerungszeit, die Ausgangsflankensteilheit und der Querstrom eines Gatters sowohl durch die Lastkapazität als auch durch die Steilheit des Eingangssignals beeinflusst. Die heute verwendeten Technologiebibliotheken beinhalten Tabellenmodelle mit 25 oder mehr Stützpunkten dieser Abhängigkeiten, woraus durch Interpolation die benötigten Zwischenwerte berechnet werden. Bisherige Versuche, analytische Modelle abzuleiten beruhten darauf, den Querstrom zu vernachlässigen oder Transistorströme als stückweise linear anzunähern. Der hier gezeigte Ansatz beruht auf einer näherungsweisen Lösung der Differentialgleichung, die aus den beiden Transistorströmen und einer Lastkapazität besteht und damit das Schaltverhalten eines Inverters beschreibt. Mit wenigen Technologieparametern können daraus für einen beliebig dimensionierten Inverter die für eine Timing- und Verlustleistungsanalyse notwendigen Größen berechnet werden. Das Modell erreicht bei einem Vergleich zu Referenzwerten aus SPICE Simulationen eine Genauigkeit von typischerweise 5%.In modern CMOS-technologies the gate delay, output transition time and the short-circuit current depend on the capacitive load as well as on the input transition time. Today’s technology libraries use table models with 25 or more samples for these dependencies. Intermediate values have to be calculated through interpolation. Attempts to derive analytical models are based on neglecting the short-circuit current or approximating it by piecewise linear functions. The approach shown in this paper provides an approximate solution for the differential equation describing the dynamic behavor of an inverter circuit. It includes the influence of both transistor currents and a single load capacitance. The required values for timing and power analysis can be calculated with a small set of technology parameters for an arbitrary designed inverter. Compared to reference

  1. High dynamic range CMOS-based mammography detector for FFDM and DBT

    Science.gov (United States)

    Peters, Inge M.; Smit, Chiel; Miller, James J.; Lomako, Andrey

    2016-03-01

    Digital Breast Tomosynthesis (DBT) requires excellent image quality in a dynamic mode at very low dose levels while Full Field Digital Mammography (FFDM) is a static imaging modality that requires high saturation dose levels. These opposing requirements can only be met by a dynamic detector with a high dynamic range. This paper will discuss a wafer-scale CMOS-based mammography detector with 49.5 μm pixels and a CsI scintillator. Excellent image quality is obtained for FFDM as well as DBT applications, comparing favorably with a-Se detectors that dominate the X-ray mammography market today. The typical dynamic range of a mammography detector is not high enough to accommodate both the low noise and the high saturation dose requirements for DBT and FFDM applications, respectively. An approach based on gain switching does not provide the signal-to-noise benefits in the low-dose DBT conditions. The solution to this is to add frame summing functionality to the detector. In one X-ray pulse several image frames will be acquired and summed. The requirements to implement this into a detector are low noise levels, high frame rates and low lag performance, all of which are unique characteristics of CMOS detectors. Results are presented to prove that excellent image quality is achieved, using a single detector for both DBT as well as FFDM dose conditions. This method of frame summing gave the opportunity to optimize the detector noise and saturation level for DBT applications, to achieve high DQE level at low dose, without compromising the FFDM performance.

  2. Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

    Science.gov (United States)

    Nam, Ilku; Moon, Hyunwon; Woo, Doo Hyung

    In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

  3. An integrated CMOS quantitative-polymerase-chain-reaction lab-on-chip for point-of-care diagnostics.

    Science.gov (United States)

    Norian, Haig; Field, Ryan M; Kymissis, Ioannis; Shepard, Kenneth L

    2014-10-21

    Considerable effort has recently been directed toward the miniaturization of quantitative-polymerase-chain-reaction (qPCR) instrumentation in an effort to reduce both cost and form factor for point-of-care applications. Considerable gains have been made in shrinking the required volumes of PCR reagents, but resultant prototypes retain their bench-top form factor either due to heavy heating plates or cumbersome optical sensing instrumentation. In this paper, we describe the use of complementary-metal-oxide semiconductor (CMOS) integrated circuit (IC) technology to produce a fully integrated qPCR lab-on-chip. Exploiting a 0.35 μm high-voltage CMOS process, the IC contains all of the key components for performing qPCR. Integrated resistive heaters and temperature sensors regulate the surface temperature of the chip to an accuracy of 0.45 °C. Electrowetting-on-dielectric microfluidics are actively driven from the chip surface, allowing for droplet generation and transport down to volumes less than 1.2 nanoliter. Integrated single-photon avalanche diodes (SPADs) are used for fluorescent monitoring of the reaction, allowing for the quantification of target DNA with more than four-orders-of-magnitude of dynamic range and sensitivities down to a single copy per droplet. Using this device, reliable and sensitive real-time proof-of-concept detection of Staphylococcus aureus (S. aureus) is demonstrated.

  4. Bioinspired Poly(2-oxazolines

    Directory of Open Access Journals (Sweden)

    Helmut Schlaad

    2011-02-01

    Full Text Available Poly(2-oxazolines are regarded as pseudopeptides, thus bioinspired polymers, due to their structural relationship to polypeptides. Materials and solution properties can be tuned by varying the side-chain (hydrophilic-hydrophobic, chiral, bioorganic, etc., opening the way to advanced stimulus-responsive materials and complex colloidal structures. The bioinspired “smart” solution and aggregation behavior of poly(2-oxazolines in aqueous environments are discussed in this review.

  5. A CMOS transconductance-C filter technique for very high frequencies

    NARCIS (Netherlands)

    Nauta, Bram

    1992-01-01

    CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters

  6. AzCam: A Windows-based CCD/CMOS Client/Server Data Acquisition System

    Science.gov (United States)

    Lesser, M.; Parthasarathy, M.

    AzCam is a software package developed to utilize a common architecture for the characterization of CCD and CMOS imagers in both laboratory and astronomical observatory environments. It follows a standard client/server model in which the server runs on a PC under the Microsoft Windows operating system to allow easy integration with the many CMOS imager cameras.

  7. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  8. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Science.gov (United States)

    2016-01-20

    Digital CMOS Circuits* *This work was sponsored by the Assistant Secretary of Defense...control. The ultimate sensitivity limitation of a CCD is set by the readout noise of the output amplifier that senses the charge packets and...all‐ digital CMOS readout circuits. The term "photon counting" is used broadly here to mean digital recording of a photon arrival within the

  9. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  10. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    Science.gov (United States)

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  11. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    OpenAIRE

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance valu...

  12. CMOS RF switched capacitor bandpass filter tuned by ring VCO

    OpenAIRE

    El Oualkadi, Ahmed; Paillot, Jean-Marie; Guegnaud, Hervé; Allam, Rachid

    2005-01-01

    International audience; A new RF switched capacitor bandpass filter and its command circuit made up of a ring voltage controlled oscillator with 'XOR' gates are proposed. Implemented in a standard 0.35 m CMOS technology, this circuit is intended to be used in a subset of professional mobile phone applications [380-520 MHz]. Experiments carried out on a prototype show a tunable center frequency range of 260MHz [240-500 MHz], with a quality factor that can be as high as 300.

  13. Radiation-hard silicon gate bulk CMOS cell family

    International Nuclear Information System (INIS)

    Gibbon, C.F.; Habing, D.H.; Flores, R.S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved

  14. Performance Analysis of Visible Light Communication Using CMOS Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hop Do

    2016-02-01

    Full Text Available This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR, is formulated. Finally, a simulation is conducted to verify the analysis.

  15. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Directory of Open Access Journals (Sweden)

    John-Ojur Dennis

    2015-07-01

    Full Text Available This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2 nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that

  16. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  17. CMOS realization of a 2-layer CNN universal machine chip.

    Science.gov (United States)

    Carmona, R; Jiménez-Garrido, F; Domínguez-Castro, R; Espejo, S; Rodríguez-Vázquez, A

    2003-12-01

    Some features of the biological retina can be modelled by a 2-layer cellular neural network (CNN) composed of locally connected elementary nonlinear processors. In order to explore these complex spatiotemporal dynamics for image processing, a prototype chip has been designed and fabricated in a 0.5 microm CMOS technology. Design challenges, trade-offs, the building blocks and the tests results for this system with 0.5 x 10(6) transistors, most of them operating in analog mode, are presented in this paper.

  18. Preparation of gold nanosheets using poly(ethylene oxide)-poly(propylene oxide)-poly(ethylene oxide) block copolymers via photoreduction

    International Nuclear Information System (INIS)

    Cha, Sang-Ho; Kim, Jong-Uk; Kim, Ki-Hyun; Lee, Jong-Chan

    2007-01-01

    Gold nanosheets having single crystalline structure were successfully synthesized using the bulk phase mixture of HAuCl 4 and poly(ethylene oxide)-poly(propylene oxide)-poly(ethylene oxide) block copolymers through the irradiation of a glow lamp for 5 days. When the molar ratio of propylene oxide to ethylene oxide block units in the block copolymer is about 1.75, mostly gold nanosheets were obtained. Gold nanosheets with an average width of 8 and 5 μm were obtained from the when the molar ratio of gold salt to the ethylene oxide units in the block copolymer were 1/80 and 1/160, respectively

  19. An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

    Science.gov (United States)

    Torres, Erick Omar

    Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz

  20. Actinic radiation-curable formulations from the reaction product of organic isocyanate, poly(alkylene oxide) polyol and an unsaturated addition-polymerizable monomeric compound having a single isocyanate-reactive hydrogen group

    International Nuclear Information System (INIS)

    Howard, D.D.

    1979-01-01

    Energy-curable compositions which can be cured in the presence of air by exposure to actinic radiation contain at least one unsaturated urethane oligomer. The oligomer comprises the reaction product of at least one poly(alkylene oxide) polyol, at least one polyisocyanate, and at least one unsaturated active hydrogen-containing compound

  1. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  2. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  3. A CMOS smart temperature and humidity sensor with combined readout.

    Science.gov (United States)

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  4. A Review on Energy Efficient CMOS Digital Logic

    Directory of Open Access Journals (Sweden)

    B. L. Dokic

    2013-12-01

    Full Text Available Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt and power supply voltage (Vdd on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL, complementary pass logic (CPL, push-pull pass logic (PPL and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

  5. High resolution CMOS capacitance-frequency converter for biosensor applications

    Science.gov (United States)

    Ghoor, I. S.; Land, K.; Joubert, T.-H.

    2016-02-01

    This paper presents the design of a low-complexity, linear and sub-pF CMOS capacitance-frequency converter for reading out a capacitive bacterial bio/sensors with the endeavour of creating a universal bio/sensor readout module. Therefore the priority design objectives are a high resolution as well as an extensive dynamic range. The circuit is based on a method which outputs a digital frequency signal directly from a differential capacitance by the accumulation of charges produced by repetitive charge integration and charge preservation1. A prototype has been designed for manufacture in the 0.35 μm, 3.3V ams CMOS technology. At a 1MHz clock speed, the most pertinent results obtained for the designed converter are: (i) power consumption of 1.37mW; (ii) a resolution of at least 5 fF for sensitive capacitive transduction; and (iii) an input dynamic range of at least 43.5 dB from a measurable capacitance value range of 5 - 750 fF (iv) and a Pearson's coefficient of linearity of 0.99.

  6. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

    Directory of Open Access Journals (Sweden)

    Elnaz Ghodsevali

    2017-04-01

    Full Text Available A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µV rms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter.

  7. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications.

    Science.gov (United States)

    Ghodsevali, Elnaz; Morneau-Gamache, Samuel; Mathault, Jessy; Landari, Hamza; Boisselier, Élodie; Boukadoum, Mounir; Gosselin, Benoit; Miled, Amine

    2017-04-10

    A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µV rms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter.

  8. Si light-emitting device in integrated photonic CMOS ICs

    Science.gov (United States)

    Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

    2017-07-01

    The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

  9. Power pulsing of the CMOS sensor Mimosa 26

    International Nuclear Information System (INIS)

    Kuprash, Oleg

    2013-01-01

    Mimosa 26 is a monolithic active pixel sensor developed by IPHC (Strasbourg) and IRFU (Saclay) as a prototype for the ILC vertex detector studies. The resolution requirements for the ILC tracking detector are very extreme, demanding very low material in the detector, thus only air cooling can be considered. Power consumption has to be reduced as far as possible. The beam structure of the ILC allows the possibility of power pulsing: only for about the 1 ms long bunch train full power is required, and during the 199 ms long pauses between the bunch trains the power can be reduced to a minimum. Not being adapted for the power pulsing, the sensor shows in laboratory tests a good performance under power pulsing. The power pulsing allows to significantly reduce the heating of the chip and divides power consumption approximately by a factor of 6. In this report a summary of power pulsing studies using the digital readout of Mimosa 26 is given. -- Highlights: • First power pulsing studies using digital readout of Mimosa 26 CMOS sensor were done. • Fake hit rates under power pulsing conditions and under normal conditions were compared. • The measurements demonstrate that there is so far no showstopper to operate CMOS pixel sensors in power pulsing mode

  10. Performance of Very Small Robotic Fish Equipped with CMOS Camera

    Directory of Open Access Journals (Sweden)

    Yang Zhao

    2015-10-01

    Full Text Available Underwater robots are often used to investigate marine animals. Ideally, such robots should be in the shape of fish so that they can easily go unnoticed by aquatic animals. In addition, lacking a screw propeller, a robotic fish would be less likely to become entangled in algae and other plants. However, although such robots have been developed, their swimming speed is significantly lower than that of real fish. Since to carry out a survey of actual fish a robotic fish would be required to follow them, it is necessary to improve the performance of the propulsion system. In the present study, a small robotic fish (SAPPA was manufactured and its propulsive performance was evaluated. SAPPA was developed to swim in bodies of freshwater such as rivers, and was equipped with a small CMOS camera with a wide-angle lens in order to photograph live fish. The maximum swimming speed of the robot was determined to be 111 mm/s, and its turning radius was 125 mm. Its power consumption was as low as 1.82 W. During trials, SAPPA succeeded in recognizing a goldfish and capturing an image of it using its CMOS camera.

  11. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  12. An integrated CMOS high data rate transceiver for video applications

    Science.gov (United States)

    Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

    2012-07-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  13. CMOS: Efficient Clustered Data Monitoring in Sensor Networks

    Directory of Open Access Journals (Sweden)

    Jun-Ki Min

    2013-01-01

    Full Text Available Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs. The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique.

  14. CMOS: efficient clustered data monitoring in sensor networks.

    Science.gov (United States)

    Min, Jun-Ki

    2013-01-01

    Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs). The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique.

  15. Power pulsing of the CMOS sensor Mimosa 26

    Energy Technology Data Exchange (ETDEWEB)

    Kuprash, Oleg, E-mail: oleg.kuprash@desy.de

    2013-12-21

    Mimosa 26 is a monolithic active pixel sensor developed by IPHC (Strasbourg) and IRFU (Saclay) as a prototype for the ILC vertex detector studies. The resolution requirements for the ILC tracking detector are very extreme, demanding very low material in the detector, thus only air cooling can be considered. Power consumption has to be reduced as far as possible. The beam structure of the ILC allows the possibility of power pulsing: only for about the 1 ms long bunch train full power is required, and during the 199 ms long pauses between the bunch trains the power can be reduced to a minimum. Not being adapted for the power pulsing, the sensor shows in laboratory tests a good performance under power pulsing. The power pulsing allows to significantly reduce the heating of the chip and divides power consumption approximately by a factor of 6. In this report a summary of power pulsing studies using the digital readout of Mimosa 26 is given. -- Highlights: • First power pulsing studies using digital readout of Mimosa 26 CMOS sensor were done. • Fake hit rates under power pulsing conditions and under normal conditions were compared. • The measurements demonstrate that there is so far no showstopper to operate CMOS pixel sensors in power pulsing mode.

  16. Multifunctional poly(alkyl methacrylate) films for dental care

    Energy Technology Data Exchange (ETDEWEB)

    Nielsen, Birthe V; Nevell, Thomas G; Barbu, Eugen; Smith, James R; Tsibouklis, John [School of Pharmacy and Biomedical Sciences, University of Portsmouth, Portsmouth, Hampshire, PO1 2DT (United Kingdom); Rees, Gareth D [GlaxoSmithKline R and D, St George' s Avenue, Weybridge, Surrey, KT13 0DE (United Kingdom)

    2011-02-15

    Towards the evaluation of non-permanent dental coatings for their capacity to impart dental-care benefits, thin films of a homologous series of comb-like poly(alkyl methacrylate)s (ethyl to octadecyl) have been deposited, from aqueous latex formulations, onto dentally relevant substrates. AFM studies have shown that the thickness (40-300 nm) and surface roughness (8-12 nm) of coherent polymer films are influenced by the degree of polymerization and by the length of the pendant chain. Of the polymers under consideration, poly(butyl methacrylate) formed a close-packed film that conferred to dental substrates a high degree of inhibition to acid-mediated erosion (about 27%), as evaluated by released-phosphate determinations. The potential utility of the coatings to act as anti-sensitivity barriers has been evaluated by determining the hydraulic conductance of coated bovine-dentine substrates; single treatments of dentine discs with poly(butyl methacrylate) or with poly(ethyl methacrylate) effected mean respective reductions in fluid flow of about 23% with respect to water-treated controls; repeated applications of the poly(butyl methacrylate) latex led to mean reductions in fluid flow of about 80%. Chromometric measurements have shown that pellicle-coated hydroxyapatite discs treated with poly(butyl methacrylate), poly(hexyl methacrylate) or poly(lauryl methacrylate) exhibit significant resistance to staining by food chromogens.

  17. Studies on Design Automation and Arithmetic Circuit Design for Single-Flux-Quantum Digital Circuits

    OpenAIRE

    小畑, 幸嗣; Obata, Koji

    2008-01-01

    Superconductive single-flux-quantum (SFQ) circuit technology attracts attention as a nextgeneration technology of integrated circuits because of its ultra-fast computation speedand low power consumption. In SFQ digital circuits, unlike CMOS digital circuits, apulse is used as a carrier of information and the representation of the logic values isdifferent from that in CMOS digital circuits. Therefore, design automation algorithms andstructure of arithmetic circuits suitable for SFQ digital cir...

  18. Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50 micron pitch

    CERN Document Server

    Bellazzini, R; Minuti, M; Baldini, L; Brez, A; Cavalca, F; Latronico, L; Omodei, N; Massai, M M; Sgro, C; Costa, E; Krummenacher, P S F; De Oliveira, R

    2006-01-01

    We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50 micron pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and two poly-silicon layers of a 0.18 micron VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The ve...

  19. Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

    Directory of Open Access Journals (Sweden)

    Subodh Wairya

    2012-01-01

    Full Text Available This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP, and energy delay product (EDP. Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

  20. Design and characterization of a p+/n-well SPAD array in 150nm CMOS process.

    Science.gov (United States)

    Xu, Hesong; Pancheri, Lucio; Betta, Gian-Franco Dalla; Stoppa, David

    2017-05-29

    This paper reports on characterization results of a single-photon avalanche diode (SPAD) array in standard CMOS 150nm technology. The array is composed by 25 (5 × 5) SPADs, based on p + /n-well active junction along with a retrograde deep n-well guard ring. The square-shaped SPAD has a 10µm active diameter and 15.6µm pitch size, achieving a 39.9% array fill factor. Characterization results show a good breakdown voltage uniformity (40mV max-min) within each chip and 17mV/°C temperature coefficient. The median DCR is 0.4Hz/µm 2 , and the afterpulsing probability is 0.85% for a dead time of 150ns at 3V excess bias voltage. The peak PDP is 31% at 450nm wavelength and a good uniformity (1.1% standard deviation) is observed for the array at 5V excess bias. The single SPADs exhibit a timing jitter of 52ps (FWHM) and 42ps (FWHM) under a 468-nm and a 831-nm laser, respectively. The crosstalk probability as a function of pixel-to-pixel distance and excess bias voltage is presented, and random telegraph signal (RTS) noise is also discussed in detail.

  1. Thermoplastic elastomers based on poly(lactide)-poly(trimethylene carbonate-co-caprolactone)-poly(lactide) triblock copolymers and their stereocomplexes

    NARCIS (Netherlands)

    Zhang Zheng, Z.Z.; Grijpma, Dirk W.; Feijen, Jan

    2006-01-01

    Triblock copolymers of poly(l-lactide)–poly(trimethylene carbonate-co-caprolactone)–poly(l-lactide) and poly(d-lactide)–poly(trimethylene carbonate-co-caprolactone)–poly(d-lactide) were prepared by sequential ring-opening polymerizations. These polymers are thermoplastic elastomers (TPEs) with good

  2. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  3. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    digital base-band processing on the same chip. Presently, only few examples of CMOS used for RF front-end circuits have been presented by academia, and so far no commercial products exist. The approach has been to do a CMOS block by block replacement of the blocks in traditional transceiver architectures......This paper is a survey paper presenting the Nordic CONFRONT project and reporting some results from the group at CIE/DTU, Denmark. The objective of the project is to demonstrate the feasibility of sub-micron CMOS for the realisation of RF front-end circuits operating at frequencies in the 1...... circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  4. Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

    Science.gov (United States)

    Li, Lin; Yin, Heyu; Mason, Andrew J

    2018-04-01

    The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

  5. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

    Science.gov (United States)

    De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  6. Compact characterization of liquid absorption and emission spectra using linear variable filters integrated with a CMOS imaging camera.

    Science.gov (United States)

    Wan, Yuhang; Carlson, John A; Kesler, Benjamin A; Peng, Wang; Su, Patrick; Al-Mulla, Saoud A; Lim, Sung Jun; Smith, Andrew M; Dallesasse, John M; Cunningham, Brian T

    2016-07-08

    A compact analysis platform for detecting liquid absorption and emission spectra using a set of optical linear variable filters atop a CMOS image sensor is presented. The working spectral range of the analysis platform can be extended without a reduction in spectral resolution by utilizing multiple linear variable filters with different wavelength ranges on the same CMOS sensor. With optical setup reconfiguration, its capability to measure both absorption and fluorescence emission is demonstrated. Quantitative detection of fluorescence emission down to 0.28 nM for quantum dot dispersions and 32 ng/mL for near-infrared dyes has been demonstrated on a single platform over a wide spectral range, as well as an absorption-based water quality test, showing the versatility of the system across liquid solutions for different emission and absorption bands. Comparison with a commercially available portable spectrometer and an optical spectrum analyzer shows our system has an improved signal-to-noise ratio and acceptable spectral resolution for discrimination of emission spectra, and characterization of colored liquid's absorption characteristics generated by common biomolecular assays. This simple, compact, and versatile analysis platform demonstrates a path towards an integrated optical device that can be utilized for a wide variety of applications in point-of-use testing and point-of-care diagnostics.

  7. Integrated X-ray and charged particle active pixel CMOS sensor arrays using an epitaxial silicon sensitive region

    Energy Technology Data Exchange (ETDEWEB)

    Kleinfelder, Stuart; Bichsel, Hans; Bieser, Fred; Matis, Howard S.; Rai, Gulshan; Retiere, Fabrice; Weiman, Howard; Yamamoto, Eugene

    2002-07-01

    Integrated CMOS Active Pixel Sensor (APS) arrays have been fabricated and tested using X-ray and electron sources. The 128 by 128 pixel arrays, designed in a standard 0.25 micron process, use a {approx}10 micron epitaxial silicon layer as a deep detection region. The epitaxial layer has a much greater thickness than the surface features used by standard CMOS APS, leading to stronger signals and potentially better signal-to-noise ratio (SNR). On the other hand, minority carriers confined within the epitaxial region may diffuse to neighboring pixels, blur images and reduce peak signal intensity. But for low-rate, sparse-event images, centroid analysis of this diffusion may be used to increase position resolution. Careful trade-offs involving pixel size and sense-node area verses capacitance must be made to optimize overall performance. The prototype sensor arrays, therefore, include a range of different pixel designs, including different APS circuits and a range of different epitaxial layer contact structures. The fabricated arrays were tested with 1.5 GeV electrons and Fe-55 X-ray sources, yielding a measured noise of 13 electrons RMS and an SNR for single Fe-55 X-rays of greater than 38.

  8. Single VDTA Based Dual Mode Single Input Multioutput Biquad Filter

    Directory of Open Access Journals (Sweden)

    Rajeshwari Pandey

    2016-01-01

    Full Text Available This paper presents a dual mode, single input multioutput (SIMO biquad filter configuration using single voltage differencing transconductance amplifier (VDTA, three capacitors, and a grounded resistor. The proposed topology can be used to synthesize low pass (LP, high pass (HP, and band pass (BP filter functions. It can be configured as voltage mode (VM or current mode (CM structure with appropriate input excitation choice. The angular frequency (ω0 of the proposed structure can be controlled independently of quality factor (Q0. Workability of the proposed biquad configuration is demonstrated through PSPICE simulations using 0.18 μm TSMC CMOS process parameters.

  9. AN ARRAY OF MONOLITHIC FBAR-CMOS OSCILLATORS FOR MASS-SENSING APPLICATIONS.

    Science.gov (United States)

    Johnston, M L; Kymissis, I; Shepard, K L

    2009-06-21

    We present a monolithic, solidly-mounted CMOS-FBAR oscillator array for mass sensing applications. Thin-film bulk acoustic resonators (FBAR) are an effective platform for sensitive biological and chemical detection, where their high operating frequencies make them many times more sensitive than a quartz crystal microbalance. By monolithic integration with CMOS drive circuitry, we aim to overcome the spatial limitations of externally-coupled resonators to build dense sensor arrays without specialized fabrication techniques. The sensors in this work are constructed in a 6 × 4 array atop a 0.18μm CMOS active substrate, and mass sensitivity comparable to off-chip FBAR sensors is demonstrated.

  10. Developing CMOS Camera and USB Device Drivers in Linux 2.6.32

    OpenAIRE

    CH. P. N. S. Sujitha; DVSR Sesidhar

    2013-01-01

    —This paper proposes CMOS camera and USB device drivers implementation on S3C2440 using LINUX 2.6.32. The CMOS camera driver is used for video acquisition applications, which implements image-sensor technology and USB driver is used for data acquisition applications, establishes communication between host computer and a number of peripheral devices. OV9650 CMOS camera is implemented in linux 2.6.32, uses V4L2 protocol for complying. Similarly USB device in LINUX kernel uses struct urb structu...

  11. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

    Science.gov (United States)

    Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

    2012-01-11

    Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

  12. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Directory of Open Access Journals (Sweden)

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  13. Electrochemical synthesis and characterization of bilayers of poly(O ...

    African Journals Online (AJOL)

    Using simple electrosynthesis methods a single and bilayer of conducting polymers, polypyrrole and poly(o-aminophenol) with biopolymer lignin hybrid composites were formed on gold electrodes. The specific capacitance of the single polymer-lignin composite value of 400 F/g obtained from galvanostatic ...

  14. A low-power CMOS frequency synthesizer for GPS receivers

    International Nuclear Information System (INIS)

    Yu Yunfeng; Xiao Shimao; Zhuang Haixiao; Ma Chengyan; Ye Tianchun; Yue Jianlian

    2010-01-01

    A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 . (semiconductor integrated circuits)

  15. Low-temperature mobility measurements on CMOS devices

    International Nuclear Information System (INIS)

    Hairpetian, A.; Gitlin, D.; Viswanathan, C.R.

    1989-01-01

    The surface channel mobility of carriers in eta- and rho-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 Κ. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP), which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appears to have different temperature dependence for eta- and rho-channel devices. The electron mobility increases with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibits a different temperature behavior depending upon whether the gate voltage corresponds to strong inversion or is near threshold

  16. Pulse processing CMOS ASIC for Si-strip/PIN detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2004-01-01

    The paper presents the design of an 8-channel front-end signal processing ASIC for Si-strip detectors with capacitance from 1 to 40 pf. Each channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a track-hold stage. The channel outputs are connected to an analog multiplexer which is controlled by an external clock for serial readout. The peaking time is adjustable over 500 ns-1.2us in steps by external control. There is provision for changing gain and polarity. The circuit has a power dissipation of 16 mw per channel and is designed to fabricate in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 5 by 5 mm with target package 48 pin CLCC. (author)

  17. Voltage-to-frequency converters CMOS design and implementation

    CERN Document Server

    Azcona Murillo, Cristina; Pueyo, Santiago Celma

    2013-01-01

    This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

  18. Triple inverter pierce oscillator circuit suitable for CMOS

    Science.gov (United States)

    Wessendorf,; Kurt, O [Albuquerque, NM

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  19. Analysis of the Noise Characteristics of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1997-01-01

    is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches...... to an optimization of the noise performance are discussed. It is concluded that a class AB implementation can yield a lower noise output for the same dynamic range than a class A implementation. For both the class A implementation and the class AB implementation it is essential to design low noise current mirrors......The definition of the current conveyor is reviewed and a multiple-output second generation current conveyor (CCII) is shown to combine the different generations of current conveyors presently existing. Next, noise sources are introduced, and a general noise model for the current conveyor...

  20. A CMOS low-noise instrumentation amplifier using chopper modulation

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Bruun, Erik

    2005-01-01

    This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal...... band hereby ensuring overall low noise performance. The resulting equivalent input referred noise is approximately 7 nV/rootHz for a chopping frequency of 20 kHz. The amplifier operates from a modest supply voltage of 1.8 V, drawing 136 muA of current thus consuming 245 muW of power. The gain is 72.5 d...

  1. An RF Power Amplifier in a Digital CMOS Process

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck; Fallesen, Carsten

    2002-01-01

    A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor...... is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA...... is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3 pi /8-8PSK) modulated signal....

  2. CMOS APS detector characterization for quantitative X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Endrizzi, Marco, E-mail: m.endrizzi@ucl.ac.uk [Dipartimento di Fisica, Università di Siena, Via Roma 56, 53100 Siena (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy); Oliva, Piernicola [Dipartimento di Chimica e Farmacia, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Golosio, Bruno [Sezione di Matematica, Fisica e Ingegneria dell' Informazione, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Delogu, Pasquale [Dipartimento di Fisica “E. Fermi”, Università di Pisa, Largo B. Pontecorvo 3, 56127 Pisa (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy)

    2013-03-01

    An X-ray Imaging detector based on CMOS Active Pixel Sensor and structured scintillator is characterized for quantitative X-ray imaging in the energy range 11–30 keV. Linearity, dark noise, spatial resolution and flat-field correction are the characteristics of the detector subject of investigation. The detector response, in terms of mean Analog-to-Digital Unit and noise, is modeled as a function of the energy and intensity of the X-rays. The model is directly tested using monochromatic X-ray beams and it is also indirectly validated by means of polychromatic X-ray-tube spectra. Such a characterization is suitable for quantitative X-ray imaging and the model can be used in simulation studies that take into account the actual performance of the detector.

  3. Radiation-hardened CMOS/SOS LSI circuits

    International Nuclear Information System (INIS)

    Aubuchon, K.G.; Peterson, H.T.; Shumake, D.P.

    1976-01-01

    The recently developed technology for building radiation-hardened CMOS/SOS devices has now been applied to the fabrication of LSI circuits. This paper describes and presents results on three different circuits: an 8-bit adder/subtractor (Al gate), a 256-bit shift register (Si gate), and a polycode generator (Al gate). The 256-bit shift register shows very little degradation after 1 x 10 6 rads (Si), with an increase from 1.9V to 2.9V in minimum operating voltage, a decrease of about 20% in maximum frequency, and little or no change in quiescent current. The p-channel thresholds increase from -0.9V to -1.3V, while the n-channel thresholds decrease from 1.05 to 0.23V, and the n-channel leakage remains below 1nA/mil. Excellent hardening results were also obtained on the polycode generator circuit. Ten circuits were irradiated to 1 x 10 6 rads (Si), and all continued to function well, with an increase in minimum power supply voltage from 2.85V to 5.85V and an increase in quiescent current by a factor of about 2. Similar hardening results were obtained on the 8-bit adder, with the minimum power supply voltage increasing from 2.2V to 4.6V and the add time increasing from 270 to 350 nsec after 1 x 10 6 rads (Si). These results show that large CMOS/SOS circuits can be hardened to above 1 x 10 6 rads (Si) with either the Si gate or Al gate technology. The paper also discusses the relative advantages of the Si gate versus the Al gate technology

  4. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  5. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    Science.gov (United States)

    Rimoldi, M.

    2017-12-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

  6. Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Q [Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA94720 (United States); Van Duzer, T [Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA94720 (United States); Fujiwara, K [Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA94720 (United States); Yoshikawa, N [Department of Electrical and Computer Engineering, Yokohama National University, Hodogaya, Yokohama (Japan)

    2006-06-01

    Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 {mu}m CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm{sup 2} technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory.

  7. High-End CMOS Active Pixel Sensors For Space-Borne Imaging Instruments

    National Research Council Canada - National Science Library

    Bogaerts, Jan; Lepage, Gerald; Dantes, Didier

    2005-01-01

    ...) offer great promise for use in space-borne imaging instruments. This paper highlights present-day high-end CMOS APS sensors and sketches their advantages with respect to their CCD counterparts...

  8. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Risti{c}, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  9. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Gaudiello, Andrea; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  10. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II SBIR project a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at sub 1 micro-g levels...

  11. Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

    International Nuclear Information System (INIS)

    Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

    2006-01-01

    Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

  12. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This Phase I SBIR effort initiates development of a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at...

  13. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  14. Merits of CMOS/SIMOX technology for low-voltage SRAM macros

    CERN Document Server

    Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

    1999-01-01

    A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

  15. Poly (acrylonitrile-co-itaconic acid)–poly (3, 4 ...

    Indian Academy of Sciences (India)

    Keywords. Poly(acrylonitrile-co-itaconic acid); poly(3, 4-ethylenedioxythiophene); poly(3-methoxythiophene); nanoparticle; nanofibre; nanocomposite structure; emulsion polymerization; electrospinning.

  16. Phase diagram of Ni2+ ions complexes with polyU×polyA×polyU

    Directory of Open Access Journals (Sweden)

    Usenko E. L.

    2009-06-01

    Full Text Available Aim. To investigate Ni2+ ion effect on the conformational equilibrium of the three-stranded polynucleotide polyU×polyA×polyU and to ascertain thermodynamic parameters of the metal complex formation. Methods. The differential UV spectroscopy and thermal denaturation. Results. Dependences of conformational transition (Tm of polypolyA×polyU (A2U on Ni2+ ion con- centration (up to 0.001 M under conditions close to physiological ones (0.1 M Na+, pH 7 were obtained. At [Ni2+] < 3×10–4 M two branches are observed in the phase diagram, corresponding to A2U → polyA×polyU (AU + polyU (3→2 and AU→polyA + polyU (2→1 transitions. Only A2U→polyU + polyA + polyU (3→1 transition is realized at higher Ni2+ concentrations and upon A2U heating. Effective binding constants are determined for Ni2+ ions with AU (850 M–1 and A2U (1300 M–1 as well as 3→2 transition enthalpy (DH3→2 = 4±1 kcal/mol×triplet. Conclusions. By the equilibrium binding theory the thermodynamic nature of (Tm2→3 different behavior in the phase diagram of AU in the presence of Mg2+ and Ni2+ ions was determined. A larger difference of the magnesium affinity to A2U and AU as compared with that to AU and poly A results in (Tm2→3 decrease whereas the opposite ratio of Ni2+ ion binding constants induces its increasing

  17. Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

    CERN Document Server

    Duzer, T V; Meng Xiao Fan; Whiteley, S R; Yoshikawa, N

    2002-01-01

    The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented.

  18. Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

    Energy Technology Data Exchange (ETDEWEB)

    Duzer, Theodore van [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Feng Yijun [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Meng Xiaofan [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Whiteley, Stephen R [Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA (United States); Yoshikawa, Nobuyuki [Department of Electrical and Computer Engineering, Yokohama National University (Japan)

    2002-12-01

    The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented.

  19. A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance

    DEFF Research Database (Denmark)

    Andreani, Pietro; Fard, Ali

    2006-01-01

    The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3mum CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V...

  20. Synchronous and asynchronous detection of ultra-law light levels using CMOS-compatible semiconductor technologies

    OpenAIRE

    Lotto, Christian; Seitz, Peter; Charbon, Edoardo; Enz, Christian; Farine, Pierre-André

    2011-01-01

    This work presents significant improvements of noise performance in synchronous CMOS image sensors and in asynchronous energy-sensitive singlephoton X-ray imaging systems. A detailed analysis of synchronous CMOS low-noise image sensors using conventional architectures reveals room for potential noise performance improvements, namely noise in switched-capacitor column-parallel amplifiers as well as imperfections in the low-pass filtering properties provided by such switched-capacitor amplifier...

  1. Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

    International Nuclear Information System (INIS)

    Duzer, Theodore van; Feng Yijun; Meng Xiaofan; Whiteley, Stephen R; Yoshikawa, Nobuyuki

    2002-01-01

    The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented

  2. An ebCMOS camera system for marine bioluminescence observation: The LuSEApher prototype

    Energy Technology Data Exchange (ETDEWEB)

    Dominjon, A., E-mail: a.dominjon@ipnl.in2p3.fr [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Ageron, M. [CNRS/IN2P3, Centre de Physique des Particules de Marseille, Marseille, F-13288 (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Billault, M.; Brunner, J. [CNRS/IN2P3, Centre de Physique des Particules de Marseille, Marseille, F-13288 (France); Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Calabria, P. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Chabanat, E. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Chaize, D.; Doan, Q.T.; Guerin, C.; Houles, J.; Vagneron, L. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France)

    2012-12-11

    The ebCMOS camera, called LuSEApher, is a marine bioluminescence recorder device adapted to extreme low light level. This prototype is based on the skeleton of the LUSIPHER camera system originally developed for fluorescence imaging. It has been installed at 2500 m depth off the Mediterranean shore on the site of the ANTARES neutrino telescope. The LuSEApher camera is mounted on the Instrumented Interface Module connected to the ANTARES network for environmental science purposes (European Seas Observatory Network). The LuSEApher is a self-triggered photo detection system with photon counting ability. The presentation of the device is given and its performances such as the single photon reconstruction, noise performances and trigger strategy are presented. The first recorded movies of bioluminescence are analyzed. To our knowledge, those types of events have never been obtained with such a sensitivity and such a frame rate. We believe that this camera concept could open a new window on bioluminescence studies in the deep sea.

  3. A 65 nm CMOS analog processor with zero dead time for future pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L., E-mail: luigi.gaioni@unibg.it [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Braga, D.; Christian, D.C.; Deptuch, G.; Fahim, F. [Fermi National Accelerator Laboratory, Batavia IL (United States); Nodari, B. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Centre National de Recherche Scientifique, APC/IN2P3, Paris (France); Ratti, L. [Università di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Re, V. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Zimmerman, T. [Fermi National Accelerator Laboratory, Batavia IL (United States)

    2017-02-11

    Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10{sup 34} cm{sup −2} s{sup −1} in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

  4. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    Science.gov (United States)

    Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

    2015-10-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

  5. An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

    Science.gov (United States)

    DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

    2016-01-01

    This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

  6. An All-Solution-Based Hybrid CMOS-Like Quantum Dot/Carbon Nanotube Inverter.

    Science.gov (United States)

    Shulga, Artem G; Derenskyi, Vladimir; Salazar-Rios, Jorge Mario; Dirin, Dmitry N; Fritsch, Martin; Kovalenko, Maksym V; Scherf, Ullrich; Loi, Maria A

    2017-09-01

    The development of low-cost, flexible electronic devices is subordinated to the advancement in solution-based and low-temperature-processable semiconducting materials, such as colloidal quantum dots (QDs) and single-walled carbon nanotubes (SWCNTs). Here, excellent compatibility of QDs and SWCNTs as a complementary pair of semiconducting materials for fabrication of high-performance complementary metal-oxide-semiconductor (CMOS)-like inverters is demonstrated. The n-type field effect transistors (FETs) based on I - capped PbS QDs (V th = 0.2 V, on/off = 10 5 , S S-th = 114 mV dec -1 , µ e = 0.22 cm 2 V -1 s -1 ) and the p-type FETs with tailored parameters based on low-density random network of SWCNTs (V th = -0.2 V, on/off > 10 5 , S S-th = 63 mV dec -1 , µ h = 0.04 cm 2 V -1 s -1 ) are integrated on the same substrate in order to obtain high-performance hybrid inverters. The inverters operate in the sub-1 V range (0.9 V) and have high gain (76 V/V), large maximum-equal-criteria noise margins (80%), and peak power consumption of 3 nW, in combination with low hysteresis (10 mV). © 2017 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. Dynamic testing for radiation induced failures in a standard CMOS submicron technology pixel front-end

    International Nuclear Information System (INIS)

    Venuto, D. de; Corsi, F.; Ohletz, M.J.

    1999-01-01

    A testing method for the detection of performance degradation induced by high-dose irradiation in high-energy experiments has been developed. The method used is based on a fault signature generation defined on the basis of the state-space analysis for linear circuits. By sampling the response of the circuit under test (CUT) to a single rectangular pulse, a set of parameters α are evaluated which are functions of the circuit singularities and constitute a signature for the CUT. Amplitude perturbations of these parameters engendered by element drift failure indicate a possible faulty condition. The effects of radiation induced faults in the analogue CMOS front-end of a silicon pixel detector employed in high energy physics experiments has been investigated. The results show that, even for the 800 krad dose, the test devised is able to detect the degradation of the amplifier performances. The results show also that hardened devices do not necessarily produce high circuit immunity to radiation and the proposed test method provides a mean to detect these performance deviations and to monitor them during the operating life of the chip. (A.C.)

  8. Real-time imaging of microparticles and living cells with CMOS nanocapacitor arrays

    Science.gov (United States)

    Laborde, C.; Pittino, F.; Verhoeven, H. A.; Lemay, S. G.; Selmi, L.; Jongsma, M. A.; Widdershoven, F. P.

    2015-09-01

    Platforms that offer massively parallel, label-free biosensing can, in principle, be created by combining all-electrical detection with low-cost integrated circuits. Examples include field-effect transistor arrays, which are used for mapping neuronal signals and sequencing DNA. Despite these successes, however, bioelectronics has so far failed to deliver a broadly applicable biosensing platform. This is due, in part, to the fact that d.c. or low-frequency signals cannot be used to probe beyond the electrical double layer formed by screening salt ions, which means that under physiological conditions the sensing of a target analyte located even a short distance from the sensor (∼1 nm) is severely hampered. Here, we show that high-frequency impedance spectroscopy can be used to detect and image microparticles and living cells under physiological salt conditions. Our assay employs a large-scale, high-density array of nanoelectrodes integrated with CMOS electronics on a single chip and the sensor response depends on the electrical properties of the analyte, allowing impedance-based fingerprinting. With our platform, we image the dynamic attachment and micromotion of BEAS, THP1 and MCF7 cancer cell lines in real time at submicrometre resolution in growth medium, demonstrating the potential of the platform for label/tracer-free high-throughput screening of anti-tumour drug candidates.

  9. Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    J. Sturm

    2014-04-01

    Full Text Available The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends.

  10. A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

    Science.gov (United States)

    Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

    2013-03-01

    Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

  11. Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

    Science.gov (United States)

    Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

    2017-11-26

    Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

  12. A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

    International Nuclear Information System (INIS)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing

    2011-01-01

    A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  13. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  14. Experimental study on reactor neutron induced effect of deep sub-micron CMOS static random access memory

    International Nuclear Information System (INIS)

    Yang Shanchao; Guo Xiaoqiang; Lin Dongsheng; Chen Wei; Li Ruibin; Bai Xiaoyan; Wang Guizhen

    2010-01-01

    This paper investigates neutron irradiation effects of two kinds of commercial CMOS SRAM (static random access memory), of which one is 4M memory with the feature size of 0.25 μm and the other is 16M memory with the feature size of 0.13 μm. We designed a memory testing system of irradiation effects and performed the neutron irradiation experiment using the Xi'an Pulse Reactor. The upset of two kinds of memory cells did not present a threshold versus the increase of neutron fluence. The results showed that deep sub-micron SRAM behaved single-event upset (SEU) effect in neutron irradiation environment. The SEU effect of SRAM with smaller size and higher integrated level tends to upset is considered to be related to the reduction of the device feature size, and fewer charges for upsets of the memory cell also lead to the SEU effect. (authors)

  15. A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process

    CERN Document Server

    França-Santos, Hugo

    2009-01-01

    This paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was implemented with switched capacitor circuits in eight 1.5-bit stages followed by a 2-bit stage. The power consumption is adjustable with the conversion rate and varies between 15 and 34mW for a 15 to 40MS/s conversion speed. The ADC occupies a silicon area of 0.7mm2 in a 0.13μm CMOS process and operates from a single 1.5V supply.

  16. A CMOS 0.13 mu m, 5-Gb/s laser driver for high energy physics applications

    CERN Document Server

    Mazza, G; Moreira, P; Rivetti, A; Soos, C; Troska, J; Wyllie, K

    2012-01-01

    The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC designed to drive both edge emitting lasers and VCSELs at data rates up to 5 Gb/s. It is part of the GigaBit Transceiver (GBT) and Versatile Link projects, which are designing a bi-directional optical data transmission system capable of operating in the radiation environment of a typical HEP experiment. The GBLD can provide laser diode modulation currents up to 24 mA and laser bias currents up to 43 mA. Pre- and de-emphasis functions are implemented to compensate for high external capacitive loads and asymmetric laser response. The chip, designed in a 0.13 $\\mu$m CMOS technology, is powered by a single 2.5 V power supply and can be programmed via an $I2C$ interface.

  17. A CMOS 0.13 μm, 5 Gb/s Laser Driver for High Energy Physics Applications

    Science.gov (United States)

    Mazza, Giovanni; Gui, Ping; Moreira, Paulo; Rivetti, Angelo; Soos, Csaba; Troska, Jan; Wyllie, Ken

    2012-12-01

    The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC designed to drive both edge emitting lasers and VCSELs at data rates up to 5 Gb/s. It is part of the GigaBit Transceiver (GBT) and Versatile Link projects, which are designing a bi-directional optical data transmission system capable of operating in the radiation environment of a typical HEP experiment. The GBLD can provide laser diode modulation currents up to 24 mA and laser bias currents up to 43 mA. Pre- and de-emphasis functions are implemented to compensate for high external capacitive loads and asymmetric laser response. The chip, designed in a 0.13 μm CMOS technology, is powered by a single 2.5 V power supply and can be programmed via an I2C interface.

  18. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    2018-02-02

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  19. Counting neutrons with a commercial S-CMOS camera

    Directory of Open Access Journals (Sweden)

    Patrick Van Esch

    2018-01-01

    Full Text Available It is possible to detect individual flashes from thermal neutron impacts in a ZnS scintillator using a CMOS camera looking at the scintillator screen, and off line image processing. Some preliminary results indicated that the efficiency of recognition could be improved by optimizing the light collection and the image processing. We will report on this ongoing work which is a result from the collaboration between ESS Bilbao and the ILL. The main progress to be reported is situated on the level of the on-line treatment of the imaging data. If this technology is to work on a genuine scientific instrument, it is necessary that all the processing happens on line, to avoid the accumulation of large amounts of image data to be analyzed off line. An FPGA-based real-time full-deca mode VME-compatible CameraLink board has been developed at the SCI of the ILL, which is able to manage the data flow from the camera and convert it in a reasonable “neutron impact” data flow like from a usual neutron counting detector. The main challenge of the endeavor is the optical light collection from the scintillator. While the light yield of a ZnS scintillator is a priori rather important, the amount of light collected with a photographic objective is small. Different scintillators and different light collection techniques have been experimented with and results will be shown for different setups improving upon the light recuperation on the camera sensor. Improvements on the algorithm side will also be presented. The algorithms have to be at the same time efficient in their recognition of neutron signals, in their rejection of noise signals (internal and external to the camera but also have to be simple enough to be easily implemented in the FPGA. The path from the idea of detecting individual neutron impacts with a CMOS camera to a practical working instrument detector is challenging, and in this paper we will give an overview of the part of the road that has

  20. Counting neutrons with a commercial S-CMOS camera

    Science.gov (United States)

    Patrick, Van Esch; Paolo, Mutti; Emilio, Ruiz-Martinez; Estefania, Abad Garcia; Marita, Mosconi; Jon, Ortega

    2018-01-01

    It is possible to detect individual flashes from thermal neutron impacts in a ZnS scintillator using a CMOS camera looking at the scintillator screen, and off line image processing. Some preliminary results indicated that the efficiency of recognition could be improved by optimizing the light collection and the image processing. We will report on this ongoing work which is a result from the collaboration between ESS Bilbao and the ILL. The main progress to be reported is situated on the level of the on-line treatment of the imaging data. If this technology is to work on a genuine scientific instrument, it is necessary that all the processing happens on line, to avoid the accumulation of large amounts of image data to be analyzed off line. An FPGA-based real-time full-deca mode VME-compatible CameraLink board has been developed at the SCI of the ILL, which is able to manage the data flow from the camera and convert it in a reasonable "neutron impact" data flow like from a usual neutron counting detector. The main challenge of the endeavor is the optical light collection from the scintillator. While the light yield of a ZnS scintillator is a priori rather important, the amount of light collected with a photographic objective is small. Different scintillators and different light collection techniques have been experimented with and results will be shown for different setups improving upon the light recuperation on the camera sensor. Improvements on the algorithm side will also be presented. The algorithms have to be at the same time efficient in their recognition of neutron signals, in their rejection of noise signals (internal and external to the camera) but also have to be simple enough to be easily implemented in the FPGA. The path from the idea of detecting individual neutron impacts with a CMOS camera to a practical working instrument detector is challenging, and in this paper we will give an overview of the part of the road that has already been walked.

  1. Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale

    OpenAIRE

    Zhou , Yang

    2014-01-01

    This thesis focuses on the development of a CMOS monolithic pixel sensor used for space ionizingparticles identification and counting in high flux. A new concept for single particle identification isproposed in this study, which is based on the analysis of particle triggered clusters. To validate thisnew concept, a full size sensor including the sensitive pixel matrix, an analogue signal processingchain, a 3-bit analogue to digital converter, and a digital processing stage was designed in a 0...

  2. A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

    International Nuclear Information System (INIS)

    Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

    2011-01-01

    The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

  3. A platform for European CMOS image sensors for space applications

    Science.gov (United States)

    Minoglou, K.; San Segundo Bello, D.; Sabuncuoglu Tezcan, D.; Haspeslagh, L.; Van Olmen, J.; Merry, B.; Cavaco, C.; Mazzamuto, F.; Toqué-Trésonne, I.; Moirin, R.; Brouwer, M.; Toccafondi, M.; Preti, G.; Rosmeulen, M.; De Moor, P.

    2017-11-01

    Both ESA and the EC have identified the need for a supply chain of CMOS imagers for space applications which uses solely European sources. An essential requirement on this supply chain is the platformization of the process modules, in particular when it comes to very specific processing steps, such as those required for the manufacturing of backside illuminated image sensors. This is the goal of the European (EC/FP7/SPACE) funded project EUROCIS. All EUROCIS partners have excellent know-how and track record in the expertise fields required. Imec has been leading the imager chip design and the front side and backside processing. LASSE, as a major player in the laser annealing supplier sector, has been focusing on the optimization of the process related to the backside passivation of the image sensors. TNO, known worldwide as a top developer of instruments for scientific research, including space research and sensors for satellites, has contributed in the domain of optical layers for space instruments and optimized antireflective coatings. Finally, Selex ES, as a world-wide leader for manufacturing instruments with expertise in various space missions and programs, has defined the image sensor specifications and is taking care of the final device characterization. In this paper, an overview of the process flow, the results on test structures and imagers processed using this platform will be presented.

  4. Radiation-hardened bulk Si-gate CMOS microprocessor family

    International Nuclear Information System (INIS)

    Stricker, R.E.; Dingwall, A.G.F.; Cohen, S.; Adams, J.R.; Slemmer, W.C.

    1979-01-01

    RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 10 6 rads (Si) and transient upset hardness of 5 x 10 8 rads (Si)/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor, the CDP-1834 ROM, the CDP-1852 8-bit I/O port, the CDP-1856 N-bit 1 of 8 decoder, and the TCC-244 256 x 4 Static RAM. The paper is divided into three parts. In the first section, the basic fundamentals of the non-hardened C 2 L technology used for the CDP-1800 series microprocessor parts is discussed along with the primary reasons for hardening this technology. The second section discusses the major changes in the fabrication sequence that are required to produce radiation-hardened devices. The final section details the electrical performance characteristics of the hardened devices as well as the effects of radiation on device performance. Also included in this section is a discussion of the TCC-244 256 x 4 Static RAM designed jointly by RCA and Sandia Laboratories for this application

  5. CMOS indoor light energy harvesting system for wireless sensing applications

    CERN Document Server

    Ferreira Carvalho, Carlos Manuel

    2016-01-01

    This book discusses in detail the CMOS implementation of energy harvesting.  The authors describe an integrated, indoor light energy harvesting system, based on a controller circuit that dynamically and automatically adjusts its operation to meet the actual light circumstances of the environment where the system is placed.  The system is intended to power a sensor node, enabling an autonomous wireless sensor network (WSN). Although designed to cope with indoor light levels, the system is also able to work with higher levels, making it an all-round light energy harvesting system.  The discussion includes experimental data obtained from an integrated manufactured prototype, which in conjunction with a photovoltaic (PV) cell, serves as a proof of concept of the desired energy harvesting system.  ·         Discusses several energy sources which can be used to power energy harvesting systems and includes an overview of PV cell technologies  ·         Includes an introduction to voltage step-...

  6. Digital characteristics of CMOS devices at cryogenic temperatures

    International Nuclear Information System (INIS)

    Deen, M.J.

    1989-01-01

    This paper presents the results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and a supply voltage between 3 and 20 V. Using a fixed supply of 5 V, the low noise margin (NM L decreased from 2.54 to 2.11 V, but the high noise margin NM H ) increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V 1L and V 1H increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity, V H - V L , and V 1H - V 1L all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained as due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β N /β rho ratio as the temperature is lowered

  7. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2015-03-01

    Full Text Available This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  8. Radiation Tolerant Design with 0.18-micron CMOS Technology

    CERN Document Server

    Chen, Li; Durdle , Nelson G.

    This thesis discusse s th e issues r elated to the us e of enclosed-gate layou t trans isto rs and guard rings in a 0.18 μ m CMOS technology in order to im prove the radiation tolerance of ASICs. The thin gate oxides of subm icron technologies ar e inherently m ore radiation tole rant tha n the thick er oxides present in less advanced technologies. Using a commercial deep subm icron technology to bu ild up radiation-ha rdened circuits introduces several advantages com pared to a dedicated radiation-ha rd technology, such as speed, power, area, stability, and expense. Som e novel aspects related to the use of encl osed-gate layout transist ors are presented in this th esis. A m odel to calculate the aspect ratio is introduced and verified. Some im portant electrica l par ameters of the tran sistors such as threshold voltage, leakage current, subthreshold slope, and transconducta nce are studied before and afte...

  9. CMOS Image Sensor with a Built-in Lane Detector

    Directory of Open Access Journals (Sweden)

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  10. Edge-TCT measurements on irradiated HV CMOS sensors

    CERN Document Server

    Weisser, Constantin

    2014-01-01

    Passive $100 \\times 100 \\,\\mu$m test diodes in an unirradiated and an irradiated HV2FEI4v3 HV-CMOS silicon sensor were analysed using the edge TCT technique. To integrate the sensor into the setup a PCB was designed to extract the signals, a cooling mechanism was constructed and the system housed in a shielding box. The observed signal had fast and slow contributions, that were interpreted as drift and diffusion. The former peaked in a region, that was interpreted as the depletion region, while the latter peaked further in the bulk material. Raising the bias voltage increased the depth of the former region, while pushing the latter region further into the bulk. The irradiated sample lost signal strength mainly in its slow part compared to the unirradiated sample, while its quick signal remained largely unaffected. As only the signal interpreted as drift is fast enough to be useful in LHC operation the investigated sensors could be considered radiation hard for this purpose. This gives further promise to ...

  11. CMOS based capacitance to digital converter circuit for MEMS sensor

    Science.gov (United States)

    Rotake, D. R.; Darji, A. D.

    2018-02-01

    Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

  12. Passive radiation detection using optically active CMOS sensors

    Science.gov (United States)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and β particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  13. Novel integrated CMOS pixel structures for vertex detectors

    Energy Technology Data Exchange (ETDEWEB)

    Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

    2003-10-29

    Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

  14. Fabrication of Wireless Micro Pressure Sensor Using the CMOS Process

    Directory of Open Access Journals (Sweden)

    Chienliu Chang

    2009-10-01

    Full Text Available In this study, we fabricated a wireless micro FET (field effect transistor pressure sensor based on the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The wireless micro pressure sensor is composed of a FET pressure sensor, an oscillator, an amplifier and an antenna. The oscillator is adopted to generate an ac signal, and the amplifier is used to amplify the sensing signal of the pressure sensor. The antenna is utilized to transmit the output voltage of the pressure sensor to a receiver. The pressure sensor is constructed by 16 sensing cells in parallel. Each sensing cell contains an MOS (metal oxide semiconductor and a suspended membrane, which the gate of the MOS is the suspended membrane. The postprocess employs etchants to etch the sacrificial layers in the pressure sensor for releasing the suspended membranes, and a LPCVD (low pressure chemical vapor deposition parylene is adopted to seal the etch holes in the pressure. Experimental results show that the pressure sensor has a sensitivity of 0.08 mV/kPa in the pressure range of 0–500 kPa and a wireless transmission distance of 10 cm.

  15. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

    Directory of Open Access Journals (Sweden)

    Michele Grassi

    2009-06-01

    Full Text Available This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively.

  16. Gamma and Proton-Induced Dark Current Degradation of 5T CMOS Pinned Photodiode 0.18 mu{m} CMOS Image Sensors

    Science.gov (United States)

    Martin, E.; Nuns, T.; David, J.-P.; Gilard, O.; Vaillant, J.; Fereyre, P.; Prevost, V.; Boutillier, M.

    2014-02-01

    The radiation tolerance of a 0.18 μm technology CMOS commercial image sensor has been evaluated with Co60 and proton irradiations. The effects of protons on the hot pixels and dynamic bias and duty cycle conditions during gamma irradiations are studied.

  17. Higher cytoplasmic and nuclear poly(ADP-ribose) polymerase expression in familial than in sporadic breast cancer

    NARCIS (Netherlands)

    Klauke, M.L.; Hoogerbrugge-van der Linden, N.; Budczies, J.; Bult, P.; Prinzler, J.; Radke, C.; van Krieken, J.H.; Dietel, M.; Denkert, C.; Muller, B.M.

    2012-01-01

    Poly(ADP-ribose) polymerase 1 (PARP) is a key element of the single-base excision pathway for repair of DNA single-strand breaks. To compare the cytoplasmic and nuclear poly(ADP-ribose) expression between familial (BRCA1, BRCA2, or non BRCA1/2) and sporadic breast cancer, we investigated 39 sporadic

  18. Implementation of a new Cryopad on the diffractometer POLI at MLZ.

    Science.gov (United States)

    Hutanu, V; Luberstetter, W; Bourgeat-Lami, E; Meven, M; Sazonov, A; Steffen, A; Heger, G; Roth, G; Lelièvre-Berna, E

    2016-10-01

    A new polarized neutron single crystal diffractometer POLI (Polarization Investigator) has been developed at the Maier-Leibnitz Zentrum, Garching, Germany. After reviewing existing devices, spherical neutron polarimetry has been implemented on POLI as a main experimental technique using a third-generation cryogenic polarization analysis device (Cryopad) built in cooperation between RWTH University and Institut Laue-Langevin. In this report we describe the realization and present the performance of the new Cryopad on POLI. Some improvements in the construction as well as details regarding calibrations of Cryopad and its practical use are discussed. The reliable operation of the new Cryopad on POLI is also demonstrated.

  19. Homogeneous 2D MoTe2p-n Junctions and CMOS Inverters formed by Atomic-Layer-Deposition-Induced Doping.

    Science.gov (United States)

    Lim, June Yeong; Pezeshki, Atiye; Oh, Sehoon; Kim, Jin Sung; Lee, Young Tack; Yu, Sanghyuck; Hwang, Do Kyung; Lee, Gwan-Hyoung; Choi, Hyoung Joon; Im, Seongil

    2017-08-01

    Recently, α-MoTe 2 , a 2D transition-metal dichalcogenide (TMD), has shown outstanding properties, aiming at future electronic devices. Such TMD structures without surface dangling bonds make the 2D α-MoTe 2 a more favorable candidate than conventional 3D Si on the scale of a few nanometers. The bandgap of thin α-MoTe 2 appears close to that of Si and is quite smaller than those of other typical TMD semiconductors. Even though there have been a few attempts to control the charge-carrier polarity of MoTe 2 , functional devices such as p-n junction or complementary metal-oxide-semiconductor (CMOS) inverters have not been reported. Here, we demonstrate a 2D CMOS inverter and p-n junction diode in a single α-MoTe 2 nanosheet by a straightforward selective doping technique. In a single α-MoTe 2 flake, an initially p-doped channel is selectively converted to an n-doped region with high electron mobility of 18 cm 2 V -1 s -1 by atomic-layer-deposition-induced H-doping. The ultrathin CMOS inverter exhibits a high DC voltage gain of 29, an AC gain of 18 at 1 kHz, and a low static power consumption of a few nanowatts. The results show a great potential of α-MoTe 2 for future electronic devices based on 2D semiconducting materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Transport properties of poly(GACT)–poly(CTGA)

    Indian Academy of Sciences (India)

    In this paper, based on the tight-binding Hamiltonian model and within the framework of a generalized Green's function technique, the electronic conduction through the poly(GACT)–poly(CTGA) DNA molecule in SWNT/DNA/SWNT structure has been numerically investigated. In a ladder model, we consider DNA as a ...