Single-Photon Avalanche Diodes (SPAD) in CMOS 0.35 µm technology

Energy Technology Data Exchange (ETDEWEB)

Pellion, D.; Jradi, K.; Brochard, N. [Le2i – CNRS/Univ. de Bourgogne, Dijon (France); Prêle, D. [APC – CNRS/Univ. Paris Diderot, Paris (France); Ginhac, D. [Le2i – CNRS/Univ. de Bourgogne, Dijon (France)

2015-07-01

Some decades ago single photon detection used to be the terrain of photomultiplier tube (PMT), thanks to its characteristics of sensitivity and speed. However, PMT has several disadvantages such as low quantum efficiency, overall dimensions, and cost, making them unsuitable for compact design of integrated systems. So, the past decade has seen a dramatic increase in interest in new integrated single-photon detectors called Single-Photon Avalanche Diodes (SPAD) or Geiger-mode APD. SPAD are working in avalanche mode above the breakdown level. When an incident photon is captured, a very fast avalanche is triggered, generating an easily detectable current pulse. This paper discusses SPAD detectors fabricated in a standard CMOS technology featuring both single-photon sensitivity, and excellent timing resolution, while guaranteeing a high integration. In this work, we investigate the design of SPAD detectors using the AMS 0.35 µm CMOS Opto technology. Indeed, such standard CMOS technology allows producing large surface (few mm{sup 2}) of single photon sensitive detectors. Moreover, SPAD in CMOS technologies could be associated to electronic readout such as active quenching, digital to analog converter, memories and any specific processing required to build efficient calorimeters (Silicon PhotoMultiplier – SiPM) or high resolution imagers (SPAD imager). The present work investigates SPAD geometry. MOS transistor has been used instead of resistor to adjust the quenching resistance and find optimum value. From this first set of results, a detailed study of the dark count rate (DCR) has been conducted. Our results show a dark count rate increase with the size of the photodiodes and the temperature (at T=22.5 °C, the DCR of a 10 µm-photodiode is 2020 count s{sup −1} while it is 270 count s{sup −1} at T=−40 °C for a overvoltage of 800 mV). A small pixel size is desirable, because the DCR per unit area decreases with the pixel size. We also found that the adjustment

Pt silicide/poly-Si Schottky diodes as temperature sensors for bolometers

Energy Technology Data Exchange (ETDEWEB)

Yuryev, V. A., E-mail: vyuryev@kapella.gpi.ru; Chizh, K. V.; Chapnin, V. A.; Mironov, S. A.; Dubkov, V. P.; Uvarov, O. V.; Kalinushkin, V. P. [A. M. Prokhorov General Physics Institute of the Russian Academy of Sciences, 38 Vavilov Street, Moscow 119991 (Russian Federation); Senkov, V. M. [P. N. Lebedev Physical Institute of the Russian Academy of Sciences, 53 Leninskiy Avenue, Moscow 119991 (Russian Federation); Nalivaiko, O. Y. [JSC “Integral” – “Integral” Holding Management Company, 121A, Kazintsa I. P. Street, Minsk 220108 (Belarus); Novikau, A. G.; Gaiduk, P. I. [Belarusian State University, 4 Nezavisimosti Avenue, 220030 Minsk (Belarus)

2015-05-28

Platinum silicide Schottky diodes formed on films of polycrystalline Si doped by phosphorus are demonstrated to be efficient and manufacturable CMOS-compatible temperature sensors for microbolometer detectors of radiation. Thin-film platinum silicide/poly-Si diodes have been produced by a CMOS-compatible process on artificial Si{sub 3}N{sub 4}/SiO{sub 2}/Si(001) substrates simulating the bolometer cells. Layer structure and phase composition of the original Pt/poly-Si films and the Pt silicide/poly-Si films synthesized by a low-temperature process have been studied by means of the scanning transmission electron microscopy; they have also been explored by means of the two-wavelength X-ray structural phase analysis and the X-ray photoelectron spectroscopy. Temperature coefficient of voltage for the forward current of a single diode is shown to reach the value of about −2%/ °C in the temperature interval from 25 to 50 °C.

Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

Energy Technology Data Exchange (ETDEWEB)

Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica; Tisa, Simone; Zappa, Franco [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

2013-12-15

We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

CMOS single-stage input-powered bridge rectifier with boost switch and duty cycle control

Science.gov (United States)

Radzuan, Roskhatijah; Mohd Salleh, Mohd Khairul; Hamzah, Mustafar Kamal; Ab Wahab, Norfishah

2017-06-01

This paper presents a single-stage input-powered bridge rectifier with boost switch for wireless-powered devices such as biomedical implants and wireless sensor nodes. Realised using CMOS process technology, it employs a duty cycle switch control to achieve high output voltage using boost technique, leading to a high output power conversion. It has only six external connections with the boost inductance. The input frequency of the bridge rectifier is set at 50 Hz, while the switching frequency is 100 kHz. The proposed circuit is fabricated on a single 0.18-micron CMOS die with a space area of 0.024 mm2. The simulated and measured results show good agreement.

Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

International Nuclear Information System (INIS)

Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

2015-01-01

The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

Science.gov (United States)

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Single-chip RF communications systems in CMOS

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

International Nuclear Information System (INIS)

Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

2014-01-01

The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10 14 cm −2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

Science.gov (United States)

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Toward CMOS image sensor based glucose monitoring.

Science.gov (United States)

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

Gate current for p+-poly PMOS devices under gate injection conditions

NARCIS (Netherlands)

Hof, A.J.; Holleman, J.; Woerlee, P.H.

2001-01-01

In current CMOS processing both n+-poly and p+-poly gates are used. The I-V –relationship and reliability of n+-poly devices are widely studied and well understood. Gate currents and reliability for p+-poly PMOS devices under gate injection conditions are not well understood. In this paper, the

CMOS SPAD-based image sensor for single photon counting and time of flight imaging

OpenAIRE

Dutton, Neale Arthur William

2016-01-01

The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications....

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

International Nuclear Information System (INIS)

Bonacini, S.

2007-11-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

OpenAIRE

Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

Gun muzzle flash detection using a CMOS single photon avalanche diode

Science.gov (United States)

Merhav, Tomer; Savuskan, Vitali; Nemirovsky, Yael

2013-10-01

Si based sensors, in particular CMOS Image sensors, have revolutionized low cost imaging systems but to date have hardly been considered as possible candidates for gun muzzle flash detection, due to performance limitations, and low SNR in the visible spectrum. In this study, a CMOS Single Photon Avalanche Diode (SPAD) module is used to record and sample muzzle flash events in the visible spectrum, from representative weapons, common on the modern battlefield. SPADs possess two crucial properties for muzzle flash imaging - Namely, very high photon detection sensitivity, coupled with a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. This enables high sampling frequencies in the kilohertz range without SNR degradation, in contrast to regular CMOS image sensors. To date, the SPAD has not been utilized for flash detection in an uncontrolled environment, such as gun muzzle flash detection. Gun propellant manufacturers use alkali salts to suppress secondary flashes ignited during the muzzle flash event. Common alkali salts are compounds based on Potassium or Sodium, with spectral emission lines around 769nm and 589nm, respectively. A narrow band filter around the Potassium emission doublet is used in this study to favor the muzzle flash signal over solar radiation. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength under the specified imaging conditions. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics.

Single Photon Counting Performance and Noise Analysis of CMOS SPAD-Based Image Sensors

Science.gov (United States)

Dutton, Neale A. W.; Gyongy, Istvan; Parmesan, Luca; Henderson, Robert K.

2016-01-01

SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed. PMID:27447643

Wideband CMOS receivers

CERN Document Server

Oliveira, Luis

2015-01-01

This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

Mechanical characterization of poly-SiGe layers for CMOS–MEMS integrated application

International Nuclear Information System (INIS)

Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; De Wolf, Ingrid; Puers, Robert

2010-01-01

Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

Science.gov (United States)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

NARCIS (Netherlands)

Chen, Y.; Theuwissen, A.J.P.; Chae, Y.

2011-01-01

This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as photon detector. The test sensor was

CMOS test and evaluation a physical perspective

CERN Document Server

Bhushan, Manjul

2015-01-01

This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

Large area CMOS image sensors

International Nuclear Information System (INIS)

Turchetta, R; Guerrini, N; Sedgwick, I

2011-01-01

CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

A 5.4mW GPS CMOS quadrature front-end based on a single-stage LNA-mixer-VCO

DEFF Research Database (Denmark)

Liscidini, Amtonio; Mazzanti, Andrea; Tonietto, Riccardo

2006-01-01

A GPS RF front-end combines the LNA, mixer, and VCO in a single stage and can operate from a 1.2V supply. The chip is implemented in a 0.13um CMOS process and occupies 1.5mm2 active area. It consumes 5.4mW with a 4.8dB NF, 36dB gain, and a P1dB of -31dBm.......A GPS RF front-end combines the LNA, mixer, and VCO in a single stage and can operate from a 1.2V supply. The chip is implemented in a 0.13um CMOS process and occupies 1.5mm2 active area. It consumes 5.4mW with a 4.8dB NF, 36dB gain, and a P1dB of -31dBm....

Mechanism and modelling of source/drain asymmetry variation in 65 nm CMOS devices for SRAM and logic applications

International Nuclear Information System (INIS)

Lee, T H; Fang, Y K; Chiang, Y T; Lin, C T; Chen, M S; Cheng, O

2008-01-01

The source/drain asymmetry variation of 65 nm CMOS devices for SRAM and logic applications has been investigated in detail. For the first time, we observe that the asymmetry variation is proportional to the inverse of the root square of the device area. In other words, the asymmetry variation should become worse for future advanced CMOS technologies. Fortunately, through the T-CAD simulations and experiments, we find the variation can be improved significantly with the optimization of the poly-gate grain size, extra laser annealing and using a vertical profile poly-gate. Furthermore, the improvement in asymmetry variation leads to a better static noise margin of SRAM

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

International Nuclear Information System (INIS)

Walther, S.; Lenoble, D.; Lallement, F.; Grouillet, A.; Erokhin, Y.; Singh, V.; Testoni, A.

2005-01-01

For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2-5x higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65 nm CMOS devices. Specifically, p + /n ultra-shallow junctions formed with BF 3 plasma doping have superior X j /R s characteristics to beamline implants and yield up to 30% lower R s for 20 nm X j while using standard spike anneal with ramp-up rate of 75 deg. C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65 nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65 nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior V t roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65 nm devices with PLAD SDE implants while still achieving V t roll-off and I on -I off performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65 nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity

A CMOS/SOI Single-input PWM Discriminator for Low-voltage Body-implanted Applications

Directory of Open Access Journals (Sweden)

Jader A. De Lima

2002-01-01

Full Text Available A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 μm single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm2. Measured resolution of encoding parameter α is better than 10% at 6 MHz and VDD = 3.3 V. Idle-mode consumption is 340 μW. Pulses of frequencies up to15 MHz and α =10% can be discriminated for 2.3 V ≤ VDD ≤ 3.3 V. Such an excellent immunity to VDD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

Science.gov (United States)

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Experimental single-chip color HDTV image acquisition system with 8M-pixel CMOS image sensor

Science.gov (United States)

Shimamoto, Hiroshi; Yamashita, Takayuki; Funatsu, Ryohei; Mitani, Kohji; Nojiri, Yuji

2006-02-01

We have developed an experimental single-chip color HDTV image acquisition system using 8M-pixel CMOS image sensor. The sensor has 3840 × 2160 effective pixels and is progressively scanned at 60 frames per second. We describe the color filter array and interpolation method to improve image quality with a high-pixel-count single-chip sensor. We also describe an experimental image acquisition system we used to measured spatial frequency characteristics in the horizontal direction. The results indicate good prospects for achieving a high quality single chip HDTV camera that reduces pseudo signals and maintains high spatial frequency characteristics within the frequency band for HDTV.

Application of RADSAFE to Model Single Event Upset Response of a 0.25 micron CMOS SRAM

Science.gov (United States)

Warren, Kevin M.; Weller, Robert A.; Sierawski, Brian; Reed, Robert A.; Mendenhall, Marcus H.; Schrimpf, Ronald D.; Massengill, Lloyd; Porter, Mark; Wilkerson, Jeff; LaBel, Kenneth A.;

Detecting single-abasic residues within a DNA strand immobilized in a biological nanopore using an integrated CMOS sensor.

Science.gov (United States)

Kim, Jungsuk; Maitra, Raj D; Pedrotti, Ken; Dunbar, William B

2013-02-01

In this paper, we demonstrate the application of a novel current-measuring sensor (CMS) customized for nanopore applications. The low-noise CMS is fabricated in a 0.35μm CMOS process and is implemented in experiments involving DNA captured in an α-hemolysin (α-HL) nanopore. Specifically, the CMS is used to build a current amplitude map as a function of varying positions of a single-abasic residue within a homopolymer cytosine single-stranded DNA (ssDNA) that is captured and held in the pore. Each ssDNA is immobilized using a biotin-streptavidin linkage. Five different DNA templates are measured and compared: one all-cytosine ssDNA, and four with a single-abasic residue substitution that resides in or near the ~1.5nm aperture of the α-HL channel when the strand is immobilized. The CMOS CMS is shown to resolves the ~5Å displacements of the abasic residue within the varying templates. The demonstration represents an advance in application-specific circuitry that is optimized for small-footprint nanopore applications, including genomic sequencing.

High efficiency grating couplers based on shared process with CMOS MOSFETs

International Nuclear Information System (INIS)

Qiu Chao; Sheng Zhen; Wu Ai-Min; Wang Xi; Zou Shi-Chang; Gan Fu-Wan; Li Le; Albert Pang

2013-01-01

Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers. In this work, a high-efficiency and complementary metal—oxide—semiconductor (CMOS) process compatible grating coupler is proposed. The poly-Si layer used as a gate in the CMOS metal—oxide—semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler, which greatly enhances its coupling efficiency. With optimal structure parameters, a coupling efficiency can reach as high as ∼ 70% at a wavelength of 1550 nm as indicated by simulation. From the angle of fabrication, all masks and etching steps are shared between MOSFETs and grating couplers, thereby making the high performance grating couplers easily integrated with CMOS circuits. Fabrication errors such as alignment shift are also simulated, showing that the device is quite tolerant in fabrication. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

A novel multi-actuation CMOS RF MEMS switch

Science.gov (United States)

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

Fully CMOS-compatible titanium nitride nanoantennas

Energy Technology Data Exchange (ETDEWEB)

Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

2016-02-01

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

Photon detection with CMOS sensors for fast imaging

International Nuclear Information System (INIS)

Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

2009-01-01

Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e - , and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100μs have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

Directory of Open Access Journals (Sweden)

Diwei He

2015-07-01

Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

Science.gov (United States)

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

Technology CAD for germanium CMOS circuit

Energy Technology Data Exchange (ETDEWEB)

Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

2006-12-15

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

Technology CAD for germanium CMOS circuit

International Nuclear Information System (INIS)

Saha, A.R.; Maiti, C.K.

2006-01-01

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

Microbeam mapping of single event latchups and single event upsets in CMOS SRAMs

International Nuclear Information System (INIS)

Barak, J.; Adler, E.; Fischer, B.E.; Schloegl, M.; Metzger, S.

1998-01-01

The first simultaneous microbeam mapping of single event upset (SEU) and latchup (SEL) in the CMOS RAM HM65162 is presented. The authors found that the shapes of the sensitive areas depend on V DD , on the ions being used and on the site on the chip being hit by the ion. In particular, they found SEL sensitive sites close to the main power supply lines between the memory-bit-arrays by detecting the accompanying current surge. All these SELs were also accompanied by bit-flips elsewhere in the memory (which they call indirect SEUs in contrast to the well known SEUs induced in the hit memory cell only). When identical SEL sensitive sites were hit farther away from the supply lines only indirect SEL sensitive sites could be detected. They interpret these events as latent latchups in contrast to the classical ones detected by their induced current surge. These latent SELs were probably decoupled from the main supply lines by the high resistivity of the local supply lines

CMOS-sensors for energy-resolved X-ray imaging

International Nuclear Information System (INIS)

Doering, D.; Amar-Youcef, S.; Deveaux, M.; Linnik, B.; Müntz, C.; Stroth, Joachim; Baudot, J.; Dulinski, W.; Kachel, M.

2016-01-01

Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

A single-ended CMOS sensing circuit for MEMS gyroscope with noise cancellation

KAUST Repository

Elsayed, Mohannad Yomn

2010-06-01

In this work, a complete single-ended readout circuit for capacitive MEMS gyroscope using chopper stabilization technique is presented. A novel noise cancellation technique is used to get rid of the bias noise. The circuit offers superior performance over state of the art readout circuits in terms of cost, gain, and noise for the given area and power consumption. The full circuit exhibits a gain of 58dB, a power dissipation of 1.3mW and an input referred noise of 12nV/√Hz. This would significantly improve the overall sensitivity of the gyroscope. The full circuit has been fabricated in 0.6um CMOS technology and it occupies an area of 0.4mm × 1mm. © 2010 IEEE.

A single-ended CMOS sensing circuit for MEMS gyroscope with noise cancellation

KAUST Repository

Elsayed, Mohannad Yomn; Emira, Ahmed; Sedky, Sherif M.; Habib, S. E. D.

2010-01-01

In this work, a complete single-ended readout circuit for capacitive MEMS gyroscope using chopper stabilization technique is presented. A novel noise cancellation technique is used to get rid of the bias noise. The circuit offers superior performance over state of the art readout circuits in terms of cost, gain, and noise for the given area and power consumption. The full circuit exhibits a gain of 58dB, a power dissipation of 1.3mW and an input referred noise of 12nV/√Hz. This would significantly improve the overall sensitivity of the gyroscope. The full circuit has been fabricated in 0.6um CMOS technology and it occupies an area of 0.4mm × 1mm. © 2010 IEEE.

CMOS Integrated Carbon Nanotube Sensor

International Nuclear Information System (INIS)

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

2009-01-01

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Advanced CMOS device technologies for 45 nm node and below

Directory of Open Access Journals (Sweden)

A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

2007-01-01

Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

Poly-silicon quantum-dot single-electron transistors

International Nuclear Information System (INIS)

Kang, Kwon-Chil; Lee, Joung-Eob; Lee, Jung-Han; Lee, Jong-Ho; Shin, Hyung-Cheol; Park, Byung-Gook

2012-01-01

For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also, to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

Energy Technology Data Exchange (ETDEWEB)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-11-15

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

International Nuclear Information System (INIS)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

2012-01-01

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

CMOS serial link for fully duplexed data communication

Science.gov (United States)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

Science.gov (United States)

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ultrasonic Fingerprint Sensor With Transmit Beamforming Based on a PMUT Array Bonded to CMOS Circuitry.

Science.gov (United States)

Jiang, Xiaoyue; Tang, Hao-Yen; Lu, Yipeng; Ng, Eldwin J; Tsai, Julius M; Boser, Bernhard E; Horsley, David A

2017-09-01

In this paper, we present a single-chip 65 ×42 element ultrasonic pulse-echo fingerprint sensor with transmit (TX) beamforming based on piezoelectric micromachined ultrasonic transducers directly bonded to a CMOS readout application-specific integrated circuit (ASIC). The readout ASIC was realized in a standard 180-nm CMOS process with a 24-V high-voltage transistor option. Pulse-echo measurements are performed column-by-column in sequence using either one column or five columns to TX the ultrasonic pulse at 20 MHz. TX beamforming is used to focus the ultrasonic beam at the imaging plane where the finger is located, increasing the ultrasonic pressure and narrowing the 3-dB beamwidth to [Formula: see text], a factor of 6.4 narrower than nonbeamformed measurements. The surface of the sensor is coated with a poly-dimethylsiloxane (PDMS) layer to provide good acoustic impedance matching to skin. Scanning laser Doppler vibrometry of the PDMS surface was used to map the ultrasonic pressure field at the imaging surface, demonstrating the expected increase in pressure, and reduction in beamwidth. Imaging experiments were conducted using both PDMS phantoms and real fingerprints. The average image contrast is increased by a factor of 1.5 when beamforming is used.

Effects of drain-wall in mitigating N-hit single event transient via 45 nm CMOS process

International Nuclear Information System (INIS)

Xu, X Y; Tang, M H; Xiao, Y G; Yan, S A; Zhang, W L; Li, Z; Xiong, Y; Zhao, W; Guo, H X

2015-01-01

A three-dimensional (3D) technology computer-aided design (TCAD) simulation in a novel layout technique for N-hit single event transient (SET) mitigation based on drain-wall layout technique is proposed. Numerical simulations of both single-device and mixed-mode show that the proposed layout technique designed with 45 nm CMOS process can efficiently reduce not only charge collection but also SET pulse widths (W SET ). What is more, simulations show that impacts caused by part of ion-incidents can be shielded with this novel layout technique. When compared with conventional layout technique and guard drain layout technique, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in effective area. (paper)

CMOS-based active RC sinusoidal oscillator with four-phase quadrature outputs and single-resistance-controlled (SRC) tuning laws

OpenAIRE

Lahiri, Abhirup; Herencsár, Norbert

2012-01-01

This paper proposes a very compact CMOS realization of active RC sinusoidal oscillator capable of generating four quadrature voltage outputs. The oscillator is based on the cascade of lossless and lossy integrators in loop. The governing laws for the condition of oscillation (CO) and the frequency of oscillation (FO) are single-resistance-controlled (SRC) and which allow independent FO tuning. Unlike previously reported SRC-based sinusoidal oscillators based on the active building block (ABB)...

Low mass MEMS/NEMS switch for a substitute of CMOS transistor using single-walled carbon nanotube thin film

Science.gov (United States)

Jang, Min-Woo

Power dissipation is a key factor for mobile devices and other low power applications. Complementary metal oxide semiconductor (CMOS) is the dominant integrated circuit (IC) technology responsible for a large part of this power dissipation. As the minimum feature size of CMOS devices enters into the sub 50 nanometer (nm) regime, power dissipation becomes much worse due to intrinsic physical limits. Many approaches have been studied to reduce power dissipation of deeply scaled CMOS ICs. One possible candidate is the electrostatic electromechanical switch, which could be fabricated with conventional CMOS processing techniques. They have critical advantages compared to CMOS devices such as almost zero standby leakage in the off-state due to the absence of a pn junction and a gate oxide, as well as excellent drive current in the on-state due to a metallic channel. Despite their excellent standby power dissipation, the electrostatic MEMS/NEMS switches have not been considered as a viable replacement for CMOS devices due to their large mechanical delay. Moreover, previous literature reveals that their pull-in voltage and switching speed are strongly proportional to each other. This reduces their potential advantage. However, in this work, we theoretically and experimentally demonstrated that the use of single-walled carbon nanotube (SWNT) with very low mass density and strong mechanical properties could provide a route to move off of the conventional trend with respect to the pull-in voltage / switching speed tradeoff observed in the literature. We fabricated 2-terminal fixed- beam switches with aligned composite SWNT thin films. In this work, layer-by-layer (LbL) self-assembly and dielectrophoresis were selected for aligned-composite SWNT thin film deposition. The dense membranes were successfully patterned to form submicron beams by e-beam lithography and oxygen plasma etching. Fixed-fixed beam switches using these membranes successfully operated with approximately 600

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

CMOS MEMS capacitive absolute pressure sensor

International Nuclear Information System (INIS)

Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

2013-01-01

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

Recent developments with CMOS SSPM photodetectors

Energy Technology Data Exchange (ETDEWEB)

Stapels, Christopher J. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)], E-mail: CStapels@RMDInc.com; Barton, Paul [University of Michigan, Ann Arbor, MI (United States); Johnson, Erik B. [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Wehe, David K. [University of Michigan, Ann Arbor, MI (United States); Dokhale, Purushottam; Shah, Kanai [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Augustine, Frank L. [Augustine Engineering, Encinitas, CA (United States); Christian, James F. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)

2009-10-21

Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k{omega} and 150-{omega} preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 {mu}m.

CMOS SPDT switch for WLAN applications

International Nuclear Information System (INIS)

Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

2015-01-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

Cmos spdt switch for wlan applications

Science.gov (United States)

Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

2015-04-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation

International Nuclear Information System (INIS)

Moreau, Y.; Gasiot, J.; Duzellier, S.

1995-01-01

Upsets caused by incident heavy ion on CMOS static RAM are studied here. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

Science.gov (United States)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

Science.gov (United States)

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-11-01

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

Gun muzzle flash detection using a single photon avalanche diode array in 0.18µm CMOS technology

Science.gov (United States)

Savuskan, Vitali; Jakobson, Claudio; Merhav, Tomer; Shoham, Avi; Brouk, Igor; Nemirovsky, Yael

2015-05-01

In this study, a CMOS Single Photon Avalanche Diode (SPAD) 2D array is used to record and sample muzzle flash events in the visible spectrum, from representative weapons. SPADs detect the emission peaks of alkali salts, potassium or sodium, with spectral emission lines around 769nm and 589nm, respectively. The alkali salts are included in the gunpowder to suppress secondary flashes ignited during the muzzle flash event. The SPADs possess two crucial properties for muzzle flash imaging: (i) very high photon detection sensitivity, (ii) a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. The sole noise sources are the ones prior to the readout circuitry (optical signal distribution, avalanche initiation distribution and nonphotonic generation). This enables high sampling frequencies in the kilohertz range without significant SNR degradation, in contrast to regular CMOS image sensors. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength, in the presence of sunlight. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics and signal processing, which will be reported. The frame rate of ~16 KHz was chosen as an optimum between SNR degradation and temporal profile recognition accuracy. In contrast to a single SPAD, the 2D array allows for multiple events to be processed simultaneously. Moreover, a significant field of view is covered, enabling comprehensive surveillance and imaging.

A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

International Nuclear Information System (INIS)

Feng Peng; Zhang Qi; Wu Nanjian

2011-01-01

This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma—delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm 2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is −10.7 dBm/−8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is −0.6 °C/0.5 °C (−1.0 °C/1.2 °C) in the operating range from 5 to 15 °C in high resolution mode (−30 to 50 °C in low resolution mode). The resolution of the sensor achieves 0.02 °C (0.18 °C) in high (low) resolution mode. (semiconductor integrated circuits)

Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

KAUST Repository

Nayak, Pradipta K.

2014-04-14

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

Photon imaging using post-processed CMOS chips

NARCIS (Netherlands)

Melai, J.

2010-01-01

This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic

CMOS Imaging Sensor Technology for Aerial Mapping Cameras

Science.gov (United States)

Neumann, Klaus; Welzenbach, Martin; Timm, Martin

2016-06-01

In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

International Nuclear Information System (INIS)

Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

2011-01-01

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

Spatiotemporal norepinephrine mapping using a high-density CMOS microelectrode array.

Science.gov (United States)

Wydallis, John B; Feeny, Rachel M; Wilson, William; Kern, Tucker; Chen, Tom; Tobet, Stuart; Reynolds, Melissa M; Henry, Charles S

2015-10-21

A high-density amperometric electrode array containing 8192 individually addressable platinum working electrodes with an integrated potentiostat fabricated using Complementary Metal Oxide Semiconductor (CMOS) processes is reported. The array was designed to enable electrochemical imaging of chemical gradients with high spatiotemporal resolution. Electrodes are arranged over a 2 mm × 2 mm surface area into 64 subarrays consisting of 128 individual Pt working electrodes as well as Pt pseudo-reference and auxiliary electrodes. Amperometric measurements of norepinephrine in tissue culture media were used to demonstrate the ability of the array to measure concentration gradients in complex media. Poly(dimethylsiloxane) microfluidics were incorporated to control the chemical concentrations in time and space, and the electrochemical response at each electrode was monitored to generate electrochemical heat maps, demonstrating the array's imaging capabilities. A temporal resolution of 10 ms can be achieved by simultaneously monitoring a single subarray of 128 electrodes. The entire 2 mm × 2 mm area can be electrochemically imaged in 64 seconds by cycling through all subarrays at a rate of 1 Hz per subarray. Monitoring diffusional transport of norepinephrine is used to demonstrate the spatiotemporal resolution capabilities of the system.

Theoretical and experimental study of single particle tracking in extreme conditions: single photon imaging

International Nuclear Information System (INIS)

Cajgfinger, T.

2012-10-01

This manuscript presents my thesis on the high frame rate (500 frames / second) single-photon detector electron-bombarded CMOS (ebCMOS). The first section compares three ultra-sensitive detectors and their methods for improving photon sensitivity: the CMOS low noise (sCMOS), the electron-multiplying CCD (emCCD) with signal multiplication by pixel and the ebCMOS with amplification by applied electric field. The method developed to detect single photon impacts with intra-pixel resolution on the ebCMOS sensor is presented. The second section compares the localization accuracy of these detectors in extreme conditions of very low photon flux (<10 photons/frame). First the theoretical limit is calculated using the Cramer-Rao lower bound for significant parameter sets. An experimental comparison of the detectors is then described. The setup provides one or more point sources controlled in position, signal and background noise. The results allow a comparison of the experimental effectiveness, purity and localization accuracy. The last section describes two experiments with the ebCMOS camera. The first aims at tracking hundreds of quantum dots simultaneously at the Nanoptec center. The second focuses on the swimming of bacteria at the surface at the Joliot Curie Institute. The point sources tracking algorithm using single photons and the Kalman filter implementation developed for these experiments is also described. (author)

BioCMOS Interfaces and Co-Design

CERN Document Server

Carrara, Sandro

2013-01-01

The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

Science.gov (United States)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

SEU-hardened design for shift register in CMOS APS

International Nuclear Information System (INIS)

Meng Liya; Liu Zedong; Hu Dajiang; Wang Qingxiang

2012-01-01

The inverter-based quasi-static shift register in CMOS APS, which is used in ionizing radiation environment, is susceptible to single event upset (SEU), thus affecting the CMOS active pixel sensor (APS) working. The analysis of the SEU for inverter-based quasi-static shift register concludes that the most sensitive node to single event transient (SET) exists in the input of inverter, and the threshold voltage and capacitance of input node of inverter determine the capability of anti-SEU. A new method was proposed, which replaced the inverter with Schmitt trigger in shift register. Because there is a hysteresis on voltage transfer characteristic of Schmitt trigger, there is high flip threshold, thus better capability of anti-SEU can be achieved. Simulation results show that the anti-SEU capability of Schmitt trigger is 10 times more than that of inverter. (authors)

Nanocantilever based mass sensor integrated with cmos circuitry

DEFF Research Database (Denmark)

Davis, Zachary James; Abadal, G.; Campabadal, F.

2003-01-01

We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

Single InAs/GaSb nanowire low-power CMOS inverter.

Science.gov (United States)

Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

2012-11-14

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Hybrid CMOS/Molecular Integrated Circuits

Science.gov (United States)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Low-voltage CMOS operational amplifiers theory, design and implementation

CERN Document Server

Sakurai, Satoshi

1995-01-01

Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

Science.gov (United States)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

CERN Document Server

Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

2014-01-01

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

A CMOS 128-APS linear array integrated with a LVOF for highsensitivity and high-resolution micro-spectrophotometry

NARCIS (Netherlands)

Liu, C.; Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

2010-01-01

A linear array of 128 Active Pixel Sensors has been developed in standard CMOS technology and a Linear Variable Optical Filter (LVOF) is added using CMOS-compatible post-process, resulting in a single chip highly-integrated highresolution microspectrometer. The optical requirements imposed by the

CMOS MEMS Fabrication Technologies and Devices

Directory of Open Access Journals (Sweden)

Hongwei Qu

2016-01-01

Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

Science.gov (United States)

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

KAUST Repository

Saffih, Faycal; Elshurafa, Amro M.; Mohammad, Mohammad Ali; Nelson-Fitzpatrick, Nathan E.; Evoy, S.

2012-01-01

. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly

Scattering Study of Conductive-Dielectric Nano/Micro-Grained Single Crystals Based on Poly(ethylene glycol, Poly(3-hexyl thiophene and Polyaniline

Directory of Open Access Journals (Sweden)

Samira Agbolaghi

2017-12-01

Full Text Available Two types of rod-coil block copolymers including poly(3-hexylthiophene-block-poly(ethylene glycol (P3HT-b-PEG and PEG-block-polyaniline (PANI were synthesized using Grignard metathesis polymerization, Suzuki coupling, and interfacial polymerization. Afterward, two types of single crystals were grown by self-seeding methodology to investigate the coily and rod blocks in grafted brushes and ordered crystalline configurations. The conductive P3HT fibrillar single crystals covered by the dielectric coily PEG oligomers were grown from toluene, xylene, and anisole, and characterized by atomic force microscopy (AFM and grazing wide angle X-ray scattering (GIWAXS. Longer P3HT backbones resulted in folding, whereas shorter ones had a high tendency towards backbone lamination. The effective factors on folding of long P3HT backbones in the single crystal structures were the solvent quality and crystallization temperature. Better solvents due to decelerating the growth condition led to a higher number of foldings. Via increasing the crystallization temperature, the system decreased the folding number to maintain its stability. Poorer solvents also reflected a higher stacking in hexyl side chain and π-π stacking directions. The dielectric lamellar PEG single crystals sandwiched between the PANI nanorods were grown from amyl acetate, and analyzed using the interface distribution function (IDF of SAXS and AFM. The molecular weights of PANI and PEG blocks and crystallization temperature were focused while studying the grown single crystals.

Negative charge induced degradation of PMOSFETs with BF2-implanted p+-poly gate

International Nuclear Information System (INIS)

Lu, C.Y.; Sung, J.M.

1989-01-01

A new degradation phenomenon on thin gate oxide PMOS-FETs with BF 2 implanted p + -poly gate has been demonstrated and investigated. The cause of this type of degradation is a combination of the boron penetration through the gate oxide and charge trap generation due to the presence of fluorine in the gate oxide and some other processing-induced effects. The negative charge-induced degradation other than enhanced boron diffusion has been studied in detail here. The impact of this process-sensitive p + -poly gate structure on deep submicron CMOS process integration has been discussed. (author)

A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS

International Nuclear Information System (INIS)

Lu Yuxiao; Sun Lu; Li Zhe; Zhou Jianjun

2014-01-01

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 × 200 μm 2 is occupied. (semiconductor integrated circuits)

Comparison of analytical models and experimental results for single-event upset in CMOS SRAMs

International Nuclear Information System (INIS)

Mnich, T.M.; Diehl, S.E.; Shafer, B.D.

1983-01-01

In an effort to design fully radiation-hardened memories for satellite and deep-space applications, a 16K and a 2K CMOS static RAM were modeled for single-particle upset during the design stage. The modeling resulted in the addition of a hardening feedback resistor in the 16K remained tentatively unaltered. Subsequent experiments, using the Lawrence Berkeley Laboratories' 88-inch cyclotron to accelerate krypton and oxygen ions, established an upset threshold for the 2K and the 16K without resistance added, as well as a hardening threshold for the 16K with feedback resistance added. Results for the 16K showed it to be hardenable to the higher level than previously published data for other unhardened 16K RAMs. The data agreed fairly well with the modeling results; however, a close look suggests that modification of the simulation methodology is required to accurately predict the resistance necessary to harden the RAM cell

A Biologically Inspired CMOS Image Sensor

CERN Document Server

Sarkar, Mukul

2013-01-01

Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

Surface-modified CMOS IC electrochemical sensor array targeting single chromaffin cells for highly parallel amperometry measurements.

Science.gov (United States)

Huang, Meng; Delacruz, Joannalyn B; Ruelas, John C; Rathore, Shailendra S; Lindau, Manfred

2018-01-01

Amperometry is a powerful method to record quantal release events from chromaffin cells and is widely used to assess how specific drugs modify quantal size, kinetics of release, and early fusion pore properties. Surface-modified CMOS-based electrochemical sensor arrays allow simultaneous recordings from multiple cells. A reliable, low-cost technique is presented here for efficient targeting of single cells specifically to the electrode sites. An SU-8 microwell structure is patterned on the chip surface to provide insulation for the circuitry as well as cell trapping at the electrode sites. A shifted electrode design is also incorporated to increase the flexibility of the dimension and shape of the microwells. The sensitivity of the electrodes is validated by a dopamine injection experiment. Microwells with dimensions slightly larger than the cells to be trapped ensure excellent single-cell targeting efficiency, increasing the reliability and efficiency for on-chip single-cell amperometry measurements. The surface-modified device was validated with parallel recordings of live chromaffin cells trapped in the microwells. Rapid amperometric spikes with no diffusional broadening were observed, indicating that the trapped and recorded cells were in very close contact with the electrodes. The live cell recording confirms in a single experiment that spike parameters vary significantly from cell to cell but the large number of cells recorded simultaneously provides the statistical significance.

Design of millimeter-wave MEMS-based reconfigurable front-end circuits using the standard CMOS technology

International Nuclear Information System (INIS)

Chang, Chia-Chan; Hsieh, Sheng-Chi; Chen, Chien-Hsun; Huang, Chin-Yen; Yao, Chun-Han; Lin, Chun-Chi

2011-01-01

This paper describes the designs of three reconfigurable CMOS-MEMS front-end components for V-/W-band applications. The suspended MEMS structure is released through post-CMOS micromachining. To achieve circuit reconfigurability, dual-state and multi-state fishbone-beam-drive actuators are proposed herein. The reconfigurable bandstop is fabricated in a 0.35 µm CMOS process with the chip size of 0.765 × 0.98 mm 2 , showing that the stop-band frequency can be switched from 60 to 50 GHz with 40 V actuation voltage. The measured isolation is better than 38 dB at 60 GHz and 34 dB at 50 GHz, respectively. The bandpass filter-integrated single-pole single-throw switch, using the 0.18 µm CMOS process, demonstrates that insertion loss and return loss are better than 6.2 and 15 dB from 88 to 100 GHz in the on-state, and isolation is better than 21 dB in the off-state with an actuation voltage of 51 V. The chip size is 0.7 × 1.04 mm 2 . The third component is a reconfigurable slot antenna fabricated in a 0.18 µm CMOS process with the chip size of 1.2 × 1.2 mm 2 . By utilizing the multi-state actuators, the frequencies of this antenna can be switched to 43, 47, 50.5, 54, 57.5 GHz with return loss better than 20 dB. Those circuits demonstrate good RF performance and are relatively compact by employing several size miniaturizing techniques, thereby enabling a great potential for the future single-chip transceiver.

''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus

International Nuclear Information System (INIS)

Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

1989-01-01

The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

Science.gov (United States)

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Microelectronic test structures for CMOS technology

CERN Document Server

Ketchen, Mark B

2011-01-01

Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

CERN Document Server

Wang, T.

2017-01-01

The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Science.gov (United States)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated CMOS Image Sensor Technologies.

Science.gov (United States)

Horie, Yu; Han, Seunghoon; Lee, Jeong-Yub; Kim, Jaekwan; Kim, Yongsung; Arbabi, Amir; Shin, Changgyun; Shi, Lilong; Arbabi, Ehsan; Kamali, Seyedeh Mahsa; Lee, Hong-Seok; Hwang, Sungwoo; Faraon, Andrei

2017-05-10

We report transmissive color filters based on subwavelength dielectric gratings that can replace conventional dye-based color filters used in backside-illuminated CMOS image sensor (BSI CIS) technologies. The filters are patterned in an 80 nm-thick poly silicon film on a 115 nm-thick SiO 2 spacer layer. They are optimized for operating at the primary RGB colors, exhibit peak transmittance of 60-80%, and have an almost insensitive response over a ± 20° angular range. This technology enables shrinking of the pixel sizes down to near a micrometer.

X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

International Nuclear Information System (INIS)

Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

2016-01-01

This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd_2O_2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

Energy Technology Data Exchange (ETDEWEB)

Cha, Bo Kyung, E-mail: goldrain99@kaist.ac.kr [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Jeon, Seongchae [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Seo, Chang-Woo [Department of Radiological Science, Yonsei University, Gangwon-do 220-710 (Korea, Republic of)

2016-09-21

This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd{sub 2}O{sub 2}S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

Optoelectronic circuits in nanometer CMOS technology

CERN Document Server

Atef, Mohamed

2016-01-01

This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

Electrical Interconnections Through CMOS Wafers

DEFF Research Database (Denmark)

Rasmussen, Frank Engel

2003-01-01

Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

International Nuclear Information System (INIS)

Han Ye; Li Quanliang; Shi Cong; Wu Nanjian

2013-01-01

This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm 2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors. (semiconductor integrated circuits)

Absorbed dose by a CMOS in radiotherapy

International Nuclear Information System (INIS)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

2011-10-01

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Neutron absorbed dose in a pacemaker CMOS

International Nuclear Information System (INIS)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

2012-01-01

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2012-06-15

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

Two transistor cluster DICE Cells with the minimum area for a hardened 28-nm CMOS and 65-nm SRAM layout design

International Nuclear Information System (INIS)

Stenin, V.Ya.; Stepanov, P.V.

2015-01-01

A hardened DICE cell layout design is based on the two spaced transistor clusters of the DICE cell each consisting of four transistors. The larger the distance between these two CMOS transistor clusters, the more robust the hardened DICE SRAM to Single Event Upsets. Some versions of the 28-nm and 65-nm DICE CMOS SRAM block composition have been suggested with minimum cluster distances of 2.27-2.32 mkm. The area of hardened 28-nm DICE CMOS cells is larger than the area of 28-nm 6T CMOS cells by a factor of 2.1 [ru

Analysis of 3D stacked fully functional CMOS Active Pixel Sensor detectors

International Nuclear Information System (INIS)

Passeri, D; Servoli, L; Meroli, S

2009-01-01

The IC technology trend is to move from 3D flexible configurations (package on package, stacked dies) to real 3D ICs. This is mainly due to i) the increased electrical performances and ii) the cost of 3D integration which may be cheaper than to keep shrinking 2D circuits. Perspective advantages for particle tracking and vertex detectors applications in High Energy Physics can be envisaged: in this work, we will focus on the capabilities of the state-of-the-art vertical scale integration technologies, allowing for the fabrication of very compact, fully functional, multiple layers CMOS Active Pixel Sensor (APS) detectors. The main idea is to exploit the features of the 3D technologies for the fabrication of a ''stack'' of very thin and precisely aligned CMOS APS layers, leading to a single, integrated, multi-layers pixel sensor. The adoption of multiple-layers single detectors can dramatically reduce the mass of conventional, separated detectors (thus reducing multiple scattering issues), at the same time allowing for very precise measurements of particle trajectory and momentum. As a proof of concept, an extensive device and circuit simulation activity has been carried out, aiming at evaluate the suitability of such a kind of CMOS active pixel layers for particle tracking purposes.

Single event upset test structures for digital CMOS application specific integrated circuits

International Nuclear Information System (INIS)

Baze, M.P.; Bartholet, W.G.; Braatz, J.C.; Dao, T.A.

1993-01-01

An approach has been developed for the design and utilization of SEU test structures for digital CMOS ASICs. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU response and designing a structure to characterize each response for each category. Critical SEU response parameters extracted from these structures are used to evaluate the SEU hardness of ASIC libraries and predict the hardness of ASIC chips

Absorbed dose by a CMOS in radiotherapy

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-10-15

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Investigation of a new low cost and low consumption single poly-silicon memory

Directory of Open Access Journals (Sweden)

Patrick Calenzo

2010-10-01

Full Text Available In this paper is presented an investigation on a new low cost and voltage consumption single poly-silicon memory cell for passive RFID (Radio Frequency IDentificationapplications. This structure is low cost due to its single poly-silicon design. This memory cell has two particularities : the first one is that no deported capacitor is necessary to program this cell which allows to reduce the structure size to 1.1μm². The second one is the way the cell is erased. A Zener diode is used to generate carriers in order to be injected into the floating gate. This Zener diode is one of the key points for the functionality that has to be validated with some electrical trials. These trials permit to integrate and use the Zener diodes measured in simulations of the complete memory cell. This is done to validate the best candidate between the Zener diodes used for the cell and highlight the efficiency in consumption and rapidity to erase the cell. Besides, the writing and the reading cases are simulated in order to show the low consumption required by the cell during these phases.

The CMOS Integration of a Power Inverter

OpenAIRE

Mannarino, Eric Francis

2016-01-01

Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this proce...

A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

Science.gov (United States)

Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

2011-01-01

A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

CERN Document Server

El-Khatib, Ziad; Mahmoud, Samy A

2012-01-01

This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

CMOS image sensors: State-of-the-art

Science.gov (United States)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

All-CMOS night vision viewer with integrated microdisplay

Science.gov (United States)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

International Nuclear Information System (INIS)

Contopanagos, Harry

2005-01-01

We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

Energy Technology Data Exchange (ETDEWEB)

Contopanagos, Harry [Institute for Microelectronics, NCSR ' Demokritos' , PO Box 60228, GR-153 10 Aghia Paraskevi, Athens (Greece)

2005-01-01

We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 {mu}m. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

Beyond CMOS nanodevices 1

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

Beyond CMOS nanodevices 2

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

A Novel Offset Cancellation Based on Parasitic-Insensitive Switched-Capacitor Sensing Circuit for the Out-of-Plane Single-Gimbaled Decoupled CMOS-MEMS Gyroscope

Science.gov (United States)

Chang, Ming-Hui; Huang, Han-Pang

2013-01-01

This paper presents a novel parasitic-insensitive switched-capacitor (PISC) sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG). According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement. PMID:23493122

Variation-aware advanced CMOS devices and SRAM

CERN Document Server

Shin, Changhwan

2016-01-01

This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

CMOS dot matrix microdisplay

Science.gov (United States)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

Directory of Open Access Journals (Sweden)

Hongyi Mi

2017-03-01

Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

Science.gov (United States)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

An acquisition system for CMOS imagers with a genuine 10 Gbit/s bandwidth

International Nuclear Information System (INIS)

Guérin, C.; Mahroug, J.; Tromeur, W.; Houles, J.; Calabria, P.; Barbier, R.

2012-01-01

This paper presents a high data throughput acquisition system for pixel detector readout such as CMOS imagers. This CMOS acquisition board offers a genuine 10 Gbit/s bandwidth to the workstation and can provide an on-line and continuous high frame rate imaging capability. On-line processing can be implemented either on the Data Acquisition Board or on the multi-cores workstation depending on the complexity of the algorithms. The different parts composing the acquisition board have been designed to be used first with a single-photon detector called LUSIPHER (800×800 pixels), developed in our laboratory for scientific applications ranging from nano-photonics to adaptive optics. The architecture of the acquisition board is presented and the performances achieved by the produced boards are described. The future developments (hardware and software) concerning the on-line implementation of algorithms dedicated to single-photon imaging are tackled.

Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

CERN Document Server

Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

2012-01-01

CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes

Energy Technology Data Exchange (ETDEWEB)

Huang, Wen-Hsien; Shen, Chang-Hong; Wang, Hsing-Hsiang; Yang, Chih-Chao; Hsieh, Tung-Ying; Hsieh, Jin-Long; Yeh, Wen-Kuan [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Shieh, Jia-Min, E-mail: jmshieh@narlabs.org.tw, E-mail: jmshieh@faculty.nctu.edu.tw [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China); Huang, Tzu-En [Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China)

2016-06-13

A doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 × 10{sup 18 }cm{sup −3} and high crystallinity (Raman FWHM ∼ 4.54 cm{sup −1}). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an I{sub on}/I{sub off} ratio over 10{sup 5} and drain-induced barrier lowering of 168 mV/V. Moreover, the fast programming speed of 100 μs–1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics.

Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

KAUST Repository

Saffih, Faycal

2012-06-01

In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

A Standard CMOS Humidity Sensor without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023?10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

1.5V fully programmable CMOS Membership Function Generator Circuit with proportional DC-voltage control

Directory of Open Access Journals (Sweden)

C. Muñiz-Montero

2013-06-01

Full Text Available A Membership Function Generator Circuit (MFGC with bias supply of 1.5 Volts and independent DC-voltage programmable functionalities is presented. The realization is based on a programmable differential current mirror and three compact voltage-to-current converters, allowing continuous and quasi-linear adjustment of the center position, height, width and slopes of the triangular/trapezoidal output waveforms. HSPICE simulation results of the proposed circuit using the parameters of a double-poly, three metal layers, 0.5 μm CMOS technology validate the functionality of the proposed architecture, which exhibits a maximum deviation of the linearity in the programmability of 7 %.

Integrated X-band FMCW front-end in SiGe BiCMOS

NARCIS (Netherlands)

Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

2010-01-01

An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

Directory of Open Access Journals (Sweden)

Mohammad Reza Shokrani

2014-01-01

Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

Science.gov (United States)

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-11-15

The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

A 900 MHz RF energy harvesting system in 40 nm CMOS technology with efficiency peaking at 47% and higher than 30% over a 22dB wide input power range

NARCIS (Netherlands)

Wang, J.; Jiang, Y.; Dijkhuis, J.; Dolmans, G.; Gao, H.; Baltus, P.G.M.

2017-01-01

A 900 MHz RF energy harvesting system is proposed for a far-field wireless power transfer application. The topology of a single-stage CMOS rectifier loaded with an integrated boost DC-DC converter is implemented in a 40 nm CMOS technology. The co-design of a cross-coupled CMOS rectifier and an

Nanometer CMOS ICs from basics to ASICs

CERN Document Server

J M Veendrick, Harry

2017-01-01

This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

An improved standard total dose test for CMOS space electronics

International Nuclear Information System (INIS)

Fleetwood, D.M.; Winokur, P.S.; Riewe, L.C.; Pease, R.L.

1989-01-01

The postirradiation response of hardened and commercial CMOS devices is investigated as a function of total dose, dose rate, and annealing time and temperature. Cobalt-60 irradiation at ≅ 200 rad(SiO 2 )/s followed by a 1-week 100 degrees C biased anneal and testing is shown to be an effective screen of hardened devices for space use. However, a similar screen and single-point test performed after Co-60 irradiation and elevated temperature anneal cannot be generally defined for commercial devices. In the absence of detailed knowledge about device and circuit radiation response, a two-point standard test is proposed to ensure space surviability of CMOS circuits: a Co-60 irradiation and test to screen against oxide-trapped charge related failures, and an additional rebound test to screen against interface-trap related failures. Testing implications for bipolar technologies are also discussed

Mass transfer ranking of polylysine, poly-ornithine and poly-methylene-co-guanidine microcapsule membranes using a single low molecular mass marker

Directory of Open Access Journals (Sweden)

Rosinski Stefan

2003-01-01

Full Text Available On the long way to clinical transplantable hybrid systems, comprising of cells, acting as immuno-protected bioreactors microencapsulated in a polymeric matrix and delivering desired factors (proteins, hormones, enzymes etc to the patient's body, an important step is the optimization of the microcapsule. This topic includes the selection of a proper coating membrane which could fulfil, first of all, the mass transfer as well as biocompatibility, stability and durability requirements. Three different membranes from polymerised aminoacids, formed around exactly identical alginate gel cores, were considered, concerning their mass transport properties, as potential candidates in this task. The results of the evaluation of the mass ingress and mass transfer coefficient h for the selected low molecular mass marker, vitamin B12, in poly-L-lysine (HPLL poly-L-ornithine (HPLO and poly-methylene-co-guanidine hydrochloride (HPMCG membrane alginate microcapsules demonstrate the advantage of using the mass transfer approach to a preliminary screening of various microcapsule formulations. Applying a single marker and evaluating mass transfer coefficients can help to quickly rank the investigated membranes and microcapsules according to their permeability. It has been demonstrated that HPLL, HPLO and HPMCG microcapsules differ from each other by a factor of two concerning the rate of low molecular mass marker transport. Interesting differences in mass transfer through the membrane in both directions in-out was also found, which could possibly be related to the membrane asymmetry.

High-speed nonvolatile CMOS/MNOS RAM

International Nuclear Information System (INIS)

Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

1979-01-01

A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

Monolithic CMOS imaging x-ray spectrometers

Science.gov (United States)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

Science.gov (United States)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

NV-CMOS HD camera for day/night imaging

Science.gov (United States)

Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

2014-06-01

SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

JPL CMOS Active Pixel Sensor Technology

Science.gov (United States)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

Science.gov (United States)

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

Science.gov (United States)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2014-01-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa

2017-11-23

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography

International Nuclear Information System (INIS)

Esposito, M.; Waltham, C.; Allinson, N.M.; Anaxagoras, T.; Evans, P.M.; Poludniowski, G.; Green, S.; Parker, D.J.; Price, T.; Manolopoulos, S.; Nieto-Camero, J.

2015-01-01

Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs

CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography.

Science.gov (United States)

Esposito, M; Anaxagoras, T; Evans, P M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Poludniowski, G; Price, T; Waltham, C; Allinson, N M

2015-06-03

Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs.

Batch Processing of CMOS Compatible Feedthroughs

DEFF Research Database (Denmark)

Rasmussen, F.E.; Heschel, M.; Hansen, Ole

2003-01-01

. The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...... of 2.5 pF. (C) 2003 Elsevier Science B.V. All rights reserved....

Fast Hopping Frequency Generation in Digital CMOS

CERN Document Server

Farazian, Mohammad; Gudem, Prasad S

2013-01-01

Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

Resistor Extends Life Of Battery In Clocked CMOS Circuit

Science.gov (United States)

Wells, George H., Jr.

1991-01-01

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Carbon Nanotube Integration with a CMOS Process

Science.gov (United States)

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Depleted CMOS pixels for LHC proton–proton experiments

International Nuclear Information System (INIS)

Wermes, N.

2016-01-01

While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

Interaction of Zn2+ Ions with Single-Stranded PolyU and PolyC in Neutral Solutions

Czech Academy of Sciences Publication Activity Database

Sorokin, V. A.; Usenko, E. L.; Valeev, V. A.; Berezniak, E. G.; Andrushchenko, Valery

2015-01-01

Roč. 119, č. 12 (2015), s. 4409-4416 ISSN 1520-6106 R&D Projects: GA ČR GAP208/11/0105; GA ČR GA15-09072S Institutional support: RVO:61388963 Keywords : metal ions * polyU * polyC * metallized DNA * differential UV spectroscopy * thermal denaturation * phase diagram Subject RIV: CF - Physical ; Theoretical Chemistry Impact factor: 3.187, year: 2015

Broadband image sensor array based on graphene-CMOS integration

Science.gov (United States)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

CMOS Cell Sensors for Point-of-Care Diagnostics

Science.gov (United States)

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

CERN Document Server

Ghafar-Zadeh, Ebrahim

2010-01-01

The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

CMOS optimization for radiation hardness

International Nuclear Information System (INIS)

Derbenwick, G.F.; Fossum, J.G.

1975-01-01

Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

International Nuclear Information System (INIS)

Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

2005-01-01

This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

Upset due to a single particle caused propagated transients in a bulk CMOS microprocessor

International Nuclear Information System (INIS)

Leavy, J.F.; Hoffmann, L.F.; Shoran, R.W.; Johnson, M.T.

1991-01-01

This paper reports on data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, that were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one of the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N 2 gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET's, a 24-26 MeV-cm 2 /mg LET threshold was deduced. Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm 2 /mg (283 MeV Cu at 0 degrees) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

Science.gov (United States)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

CMOS sensors for atmospheric imaging

Science.gov (United States)

Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

2017-09-01

Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

Self-calibrated humidity sensor in CMOS without post-processing.

Science.gov (United States)

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Self-Calibrated Humidity Sensor in CMOS without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

AIE-doped poly(ionic liquid) photonic spheres: a single sphere-based customizable sensing platform for the discrimination of multi-analytes.

Science.gov (United States)

Zhang, Wanlin; Gao, Ning; Cui, Jiecheng; Wang, Chen; Wang, Shiqiang; Zhang, Guanxin; Dong, Xiaobiao; Zhang, Deqing; Li, Guangtao

2017-09-01

By simultaneously exploiting the unique properties of ionic liquids and aggregation-induced emission (AIE) luminogens, as well as photonic structures, a novel customizable sensing system for multi-analytes was developed based on a single AIE-doped poly(ionic liquid) photonic sphere. It was found that due to the extraordinary multiple intermolecular interactions involved in the ionic liquid units, one single sphere could differentially interact with broader classes of analytes, thus generating response patterns with remarkable diversity. Moreover, the optical properties of both the AIE luminogen and photonic structure integrated in the poly(ionic liquid) sphere provide multidimensional signal channels for transducing the involved recognition process in a complementary manner and the acquisition of abundant and sufficient sensing information could be easily achieved on only one sphere sensor element. More importantly, the sensing performance of our poly(ionic liquid) photonic sphere is designable and customizable through a simple ion-exchange reaction and target-oriented multi-analyte sensing can be conveniently realized using a selective receptor species, such as counterions, showing great flexibility and extendibility. The power of our single sphere-based customizable sensing system was exemplified by the successful on-demand detection and discrimination of four multi-analyte challenge systems: all 20 natural amino acids, nine important phosphate derivatives, ten metal ions and three pairs of enantiomers. To further demonstrate the potential of our spheres for real-life application, 20 amino acids in human urine and their 26 unprecedented complex mixtures were also discriminated between by the single sphere-based array.

Single-ion triblock copolymer electrolytes based on poly(ethylene oxide) and methacrylic sulfonamide blocks for lithium metal batteries

Science.gov (United States)

Porcarelli, Luca; Aboudzadeh, M. Ali; Rubatat, Laurent; Nair, Jijeesh R.; Shaplov, Alexander S.; Gerbaldi, Claudio; Mecerreyes, David

2017-10-01

Single-ion conducting polymer electrolytes represent the ideal solution to reduce concentration polarization in lithium metal batteries (LMBs). This paper reports on the synthesis and characterization of single-ion ABA triblock copolymer electrolytes comprising PEO and poly(lithium 1-[3-(methacryloyloxy)propylsulfonyl]-1-(trifluoromethylsulfonyl)imide) blocks, poly(LiMTFSI). Block copolymers are prepared by reversible addition-fragmentation chain transfer polymerization, showing low glass transition temperature (-55 to 7 °C) and degree of crystallinity (51-0%). Comparatively high values of ionic conductivity are obtained (up to ≈ 10-4 S cm-1 at 70 °C), combined with a lithium-ion transference number close to unity (tLi+ ≈ 0.91) and a 4 V electrochemical stability window. In addition to these promising features, solid polymer electrolytes are successfully tested in lithium metal cells at 70 °C providing long lifetime up to 300 cycles, and stable charge/discharge cycling at C/2 (≈100 mAh g-1).

Radiation-hardened bulk CMOS technology

International Nuclear Information System (INIS)

Dawes, W.R. Jr.; Habing, D.H.

1979-01-01

The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

CMOS/SOS processing

Science.gov (United States)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

Directory of Open Access Journals (Sweden)

Jose Luis Muñoz-Gamarra

2016-02-01

Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

Simulations of depleted CMOS sensors for high-radiation environments

CERN Document Server

Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

2017-01-01

After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

3D monolithically stacked CMOS active pixel sensor detectors for particle tracking applications

International Nuclear Information System (INIS)

Passeri, D; Placidi, P; Servoli, L; Meroli, S; Magalotti, D; Marras, A

2012-01-01

In this work we propose an innovative approach to particle tracking based on CMOS Active Pixel Sensors layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle impact point and direction) within a single detector. This will results in a very low material detector, thus dramatically reducing multiple scattering issues. To this purpose, we rely on the capabilities of the CMOS vertical scale integration (3D IC) technology. A first chip prototype has been fabricated within a multi-project run using a 130 nm CMOS Chartered/Tezzaron technology, featuring two layers bonded face-to-face. Tests have been carried out on full 3D structures, providing the functionalities of both tiers. To this purpose, laser scans have been carried out using highly focussed spot size obtaining coincidence responses of the two layers. Tests have been made as well with X-ray sources in order to calibrate the response of the sensor. Encouraging results have been found, fostering the suitability of both the adopted 3D-IC vertical scale fabrication technology and the proposed approach for particle tracking applications.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

2018-01-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.

2018-02-27

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

Science.gov (United States)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

Prevention of CMOS latch-up by gold doping

International Nuclear Information System (INIS)

Dawes, W.R.; Derbenwick, G.F.

1976-01-01

CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.

2014-06-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

Directory of Open Access Journals (Sweden)

Hang Song

2017-01-01

Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

High-voltage CMOS detectors

International Nuclear Information System (INIS)

Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

2016-01-01

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

High-voltage CMOS detectors

Energy Technology Data Exchange (ETDEWEB)

Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

2016-07-11

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

High molecular weight poly(L-lactide) and poly(ethylene oxide) blends : Thermal characterization and physical properties

NARCIS (Netherlands)

Nijenhuis, AJ; Colstee, E; Grijpma, DW; Pennings, AJ

1996-01-01

The miscibility of high molecular weight poly(L-lactide) (PLLA) with high molecular weight poly(ethylene oxide) (PEG) was studied by differential scanning calorimetry. Ail blends containing up to 50 weight% PEO showed single glass transition temperatures. The PLLA and PEO melting temperatures were

Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50 micron pitch

CERN Document Server

Bellazzini, R; Minuti, M; Baldini, L; Brez, A; Cavalca, F; Latronico, L; Omodei, N; Massai, M M; Sgro, C; Costa, E; Krummenacher, P S F; De Oliveira, R

2006-01-01

We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50 micron pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and two poly-silicon layers of a 0.18 micron VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The ve...

Large Format CMOS-based Detectors for Diffraction Studies

Science.gov (United States)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Large Format CMOS-based Detectors for Diffraction Studies

International Nuclear Information System (INIS)

Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

2013-01-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

NARCIS (Netherlands)

Dutta, Satadal

2017-01-01

Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

Design of CMOS imaging system based on FPGA

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

Directory of Open Access Journals (Sweden)

Haitao Li

2016-12-01

Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

E-Beam Effects on CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

2011-01-01

Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

International Nuclear Information System (INIS)

Yu Xiaomei; Tang Yaquan; Zhang Haitao

2008-01-01

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

CMOS-compatible spintronic devices: a review

Science.gov (United States)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

Directory of Open Access Journals (Sweden)

M. Jamal Deen

2013-08-01

Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

Small Pixel Hybrid CMOS X-ray Detectors

Science.gov (United States)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

Modeling methodology for a CMOS-MEMS electrostatic comb

Science.gov (United States)

Iyer, Sitaraman V.; Lakdawala, Hasnain; Mukherjee, Tamal; Fedder, Gary K.

2002-04-01

A methodology for combined modeling of capacitance and force 9in a multi-layer electrostatic comb is demonstrated in this paper. Conformal mapping-based analytical methods are limited to 2D symmetric cross-sections and cannot account for charge concentration effects at corners. Vertex capacitance can be more than 30% of the total capacitance in a single-layer 2 micrometers thick comb with 10 micrometers overlap. Furthermore, analytical equations are strictly valid only for perfectly symmetrical finger positions. Fringing and corner effects are likely to be more significant in a multi- layered CMOS-MEMS comb because of the presence of more edges and vertices. Vertical curling of CMOS-MEMS comb fingers may also lead to reduced capacitance and vertical forces. Gyroscopes are particularly sensitive to such undesirable forces, which therefore, need to be well-quantified. In order to address the above issues, a hybrid approach of superposing linear regression models over a set of core analytical models is implemented. Design of experiments is used to obtain data for capacitance and force using a commercial 3D boundary-element solver. Since accurate force values require significantly higher mesh refinement than accurate capacitance, we use numerical derivatives of capacitance values to compute the forces. The model is formulated such that the capacitance and force models use the same regression coefficients. The comb model thus obtained, fits the numerical capacitance data to within +/- 3% and force to within +/- 10%. The model is experimentally verified by measuring capacitance change in a specially designed test structure. The capacitance model matches measurements to within 10%. The comb model is implemented in an Analog Hardware Description Language (ADHL) for use in behavioral simulation of manufacturing variations in a CMOS-MEMS gyroscope.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

Science.gov (United States)

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

2017-01-01

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

Data.gov (United States)

Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

CMOS Compressed Imaging by Random Convolution

OpenAIRE

Jacques, Laurent; Vandergheynst, Pierre; Bibet, Alexandre; Majidzadeh, Vahid; Schmid, Alexandre; Leblebici, Yusuf

2009-01-01

We present a CMOS imager with built-in capability to perform Compressed Sensing. The adopted sensing strategy is the random Convolution due to J. Romberg. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to comp...

The challenge of sCMOS image sensor technology to EMCCD

Science.gov (United States)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

Science.gov (United States)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Variationen und ihre Kompensation in CMOS Digitalschaltungen

OpenAIRE

Baumann, Thomas

2010-01-01

Variationen bei der Herstellung und während des Betriebs von CMOS Schaltungen beeinflussen deren Geschwindigkeit und erschweren die Verifikation der in der Spezifikation zugesicherten Eigenschaften. In dieser Arbeit wird eine abstraktionsebenenübergreifende Vorgehensweise zur Abschätzung des Einflusses von Prozess- und betriebsbedingten Umgebungsvariationen auf die Geschwindigkeit einer Schaltung vorgestellt. Neben Untersuchungen der Laufzeitsensitivität in low-power CMOS Technologien von...

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

Science.gov (United States)

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

Fully depleted CMOS pixel sensor development and potential applications

Energy Technology Data Exchange (ETDEWEB)

Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

2015-07-01

CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Directory of Open Access Journals (Sweden)

Mauro Olivieri

2013-01-01

Full Text Available Synchronous early-completion-prediction adders (ECPAs are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

Characterization of active CMOS sensors for capacitively coupled pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

2015-07-01

Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Long term ionization response of several BiCMOS VLSIC technologies

International Nuclear Information System (INIS)

Pease, R.L.; Combs, W.; Clark, S.

1992-01-01

BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies

First principle leakage current reduction technique for CMOS devices

CSIR Research Space (South Africa)

Tsague, HD

2015-12-01

Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

Science.gov (United States)

Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

2018-06-01

Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

Directory of Open Access Journals (Sweden)

Sangyong Park

2018-01-01

Full Text Available This paper presents two single-pole, double-throw (SPDT mm-wave switches for Ka-band phased-array transceivers, fabricated with a 65-nm complementary metal oxide semiconductor (CMOS process. One switch employs cross-biasing (CB control with a single supply, while the other uses dual-supply biasing (DSB control with positive and negative voltages. Negative voltages were generated internally, using a ring oscillator and a charge pump. Identical gate and body floated N-type metal oxide semiconductor field effect transistors (N-MOSFETs in a triple well were used as the switch core transistors. Inductors were used to improve the isolation between the transmitter (TX and receiver (RX, as well as insertion loss, by canceling the parasitic capacitance of the switch core transistors at resonance. The size of the proposed radio frequency (RF switch is 260 μm × 230 μm, excluding all pads. The minimum insertion losses of the CB and DSB switches were 2.1 dB at 28 GHz and 1.93 dB at 24 GHz, respectively. Between 25 GHz and 34 GHz, the insertion losses were less than 2.3 dB and 2.5 dB, the return losses were less than 16.7 dB and 17.3 dB, and the isolation was over 18.4 dB and 15.3 dB, respectively. The third order input intercept points (IIP3 of the CB and DSB switches were 38.4 dBm and 39 dBm at 28 GHz, respectively.

Ion traps fabricated in a CMOS foundry

Energy Technology Data Exchange (ETDEWEB)

Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

CMOS front ends for millimeter wave wireless communication systems

CERN Document Server

Deferm, Noël

2015-01-01

This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

Merits of CMOS/SIMOX technology for low-voltage SRAM macros

CERN Document Server

Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

1999-01-01

A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

International Nuclear Information System (INIS)

Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

2006-01-01

Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

NARCIS (Netherlands)

Patra, B; Incandela, R.M.; van Dijk, J.P.G.; Homulle, H.A.R.; Song, Lin; Shahmohammadi, M.; Staszewski, R.B.; Vladimirescu, A.; Babaie, M.; Sebastiano, F.; Charbon, E.E.E.

2018-01-01

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising

From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

DEFF Research Database (Denmark)

Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

2008-01-01

This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

Comparative studies on the pest reactions of single- and poly- crystalline MoSi2

International Nuclear Information System (INIS)

Chou, T.C.; Nieh, T.G.

1992-01-01

Molybdenum disilicide (MoSi 2 ) has many attractive properties, e.g., high melting point (2020 degrees C), relatively low density (6.28 g/cm 3 ), good thermal stability and thermal shock resistance, and excellent oxidation resistance, for potential high temperature applications. Specifically, it is oxidation resistant at temperatures up to about 1900 degrees C, resulting from the formation of a self-healing, glassy silica (SiO 2 ) surface layer. Because of its suitability for use as a high temperature coating and as heating elements, the oxidation properties of MoSi 2 have been extensively studied in the past 30 years, but mainly in the high temperature regimes. In this paper, the authors investigate the evolution and morphological characteristics of the oxidation products of both MoSi 2 single crystals and cast polycrystals. Special attention is given to addressing the nucleation of pest in single crystalline material. The results from both the single- and poly-crystalline samples are correlated with an effort to resolve the origin of MoSi 2 pest. Their implications to the early-stage formation (nucleation) of pest are discussed

CMOS-compatible high-voltage integrated circuits

Energy Technology Data Exchange (ETDEWEB)

Parpia, Z

1988-01-01

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

CMOS Image Sensors: Electronic Camera On A Chip

Science.gov (United States)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

CMOS image sensor-based immunodetection by refractive-index change.

Science.gov (United States)

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

Fabrication and characterization of novel multilayered structures by stereocomplexion of poly(D-lactic acid)/poly(L-lactic acid) and self-assembly of polyelectrolytes

OpenAIRE

Elena Dellacasa; Li Zhao; Gesheng Yang; Laura Pastorino; Gleb B. Sukhorukov

2016-01-01

The enantiomers poly(D-lactic acid) (PDLA) and poly(L-lactic acid) (PLLA) were alternately adsorbed directly on calcium carbonate (CaCO3) templates and on poly(styrene sulfonate) (PSS) and poly(allylamine hydrochloride) (PAH) multilayer precursors in order to fabricate a novel layer-by-layer (LBL) assembly. A single layer of poly(L-lysine) (PLL) was used as a linker between the (PDLA/PLLA)n stereocomplex and the cores with and without the polymeric (PSS/PAH)n/PLL multilayer precursor (PEM). N...

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

Poly(A)-tag deep sequencing data processing to extract poly(A) sites.

Science.gov (United States)

Wu, Xiaohui; Ji, Guoli; Li, Qingshun Quinn

2015-01-01

Polyadenylation [poly(A)] is an essential posttranscriptional processing step in the maturation of eukaryotic mRNA. The advent of next-generation sequencing (NGS) technology has offered feasible means to generate large-scale data and new opportunities for intensive study of polyadenylation, particularly deep sequencing of the transcriptome targeting the junction of 3'-UTR and the poly(A) tail of the transcript. To take advantage of this unprecedented amount of data, we present an automated workflow to identify polyadenylation sites by integrating NGS data cleaning, processing, mapping, normalizing, and clustering. In this pipeline, a series of Perl scripts are seamlessly integrated to iteratively map the single- or paired-end sequences to the reference genome. After mapping, the poly(A) tags (PATs) at the same genome coordinate are grouped into one cleavage site, and the internal priming artifacts removed. Then the ambiguous region is introduced to parse the genome annotation for cleavage site clustering. Finally, cleavage sites within a close range of 24 nucleotides and from different samples can be clustered into poly(A) clusters. This procedure could be used to identify thousands of reliable poly(A) clusters from millions of NGS sequences in different tissues or treatments.

Contact CMOS imaging of gaseous oxygen sensor array.

Science.gov (United States)

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

CMOS sigma-delta converters practical design guide

CERN Document Server

De la Rosa, Jose M

2013-01-01

A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

High-Voltage-Input Level Translator Using Standard CMOS

Science.gov (United States)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

Design, Characterization and Analysis of a 0.35 μm CMOS SPAD

Directory of Open Access Journals (Sweden)

Khalil Jradi

2014-12-01

Full Text Available Most of the works about single-photon detectors rely on Single Photon Avalanche Diodes (SPADs designed with dedicated technological processes in order to achieve single-photon sensitivity and excellent timing resolution. Instead, this paper focuses on the implementation of high-performance SPADs detectors manufactured in a standard 0.35-micron opto-CMOS technology provided by AMS. We propose a series of low-noise SPADs designed with a variable pitch from 20 µm down to 5 µm. This opens the further way to the integration of large arrays of optimized SPAD pixels with pitch of a few micrometers in order to provide high-resolution single-photon imagers. We experimentally demonstrate that a 20-micron SPAD appears as the most relevant detector in terms of Signal-to-Noise ratio, enabling emergence of large arrays of SPAD.

Multifunctional Poly(2,5-benzimidazole)/Carbon Nanotube Composite Films

Science.gov (United States)

2010-01-01

Multifunctional Poly(2,5- benzimidazole )/Carbon Nanotube Composite Films JI-YE KANG,1 SOO-MI EO,1 IN-YUP JEON,1 YEONG SUK CHOI,2 LOON-SENG TAN,3 JONG...molecular-weight poly(2,5- benzimidazole ) (ABPBI). ABPBI/carbon nanotube (CNT) compo- sites were prepared via in situ polymerization of the AB-monomer in the...polymerization; multiwalled carbon nanotube (MWCNT); nano- composites; poly(2,5- benzimidazole ); (ABPBI); polycondensa- tion; poly(phosphoric acid); single-walled

Advancement of CMOS Doping Technology in an External Development Framework

Science.gov (United States)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

Science.gov (United States)

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Transient-induced latchup in CMOS integrated circuits

CERN Document Server

Ker, Ming-Dou

2009-01-01

"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

Single-Chain Conformation for Interacting Poly(N-isopropylacrylamide in Aqueous Solution

Directory of Open Access Journals (Sweden)

Boualem Hammouda

2015-04-01

Full Text Available The demixing phase behavior of Poly(N-isopropylacrylamide (PNIPAM aqueous solution is investigated using small-angle neutron scattering. This polymer phase separates upon heating and demixes around 32 °C. The pre-transition temperature range is characterized by two scattering modes; a low-Q (large-scale signal and a high-Q dissolved chains signal. In order to get insight into this pre-transition region, especially the origin of the low-Q (large-scale structure, the zero average contrast method is used in order to isolate single-chain conformations even in the demixing polymers transition region. This method consists of measuring deuterated and non-deuterated polymers dissolved in mixtures of deuterated and non-deuterated water for which the polymer scattering length density matches the solvent scattering length density. A fixed 4% polymer mass fraction is used in a contrast variation series where the d-water/h-water fraction is varied in order to determine the match point. The zero average contrast (match point sample displays pure single-chain scattering with no interchain contributions. Our measurements prove that the large scale structure in this polymer solution is due to a transient polymer network formed through hydrophobic segment-segment interactions. Scattering intensity increases when the temperature gets close to the phase boundary. While the apparent radius of gyration increases substantially at the Lower Critical Solution Temperature (LCST transition due to strong interchain correlation, the single-chain true radius of gyration has been found to decrease slightly with temperature when approaching the transition.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

Science.gov (United States)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Development of a CMOS process using high energy ion implantation

International Nuclear Information System (INIS)

Stolmeijer, A.

1986-01-01

The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

Energy Technology Data Exchange (ETDEWEB)

Aunet, Snorre

2002-06-01

This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

National Research Council Canada - National Science Library

An, S

2001-01-01

.... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

KAUST Repository

Hussain, Aftab M.

2016-12-01

With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

Investigation of single event latchup

International Nuclear Information System (INIS)

Xue Yuxiong; Yang Shengsheng; Cao Zhou; Ba Dedong; An Heng; Chen Luojing; Guo Gang

2012-01-01

Radiation effects on avionics microelectronics are important reliability issues for many space applications. In particular, single-event latchup (SEL) phenomenon is a major threat to CMOS integrated circuits in space systems. To effectively circumvent the failure, it is important to know the behavior of such devices during latchup. In this paper, the mechanisms for SEL in CMOS devices are investigated. Several microelectronic devices used in avionics are tested using heavy ion beams, pulsed laser and 252 Cf source. Based on the SEL test results, SEL-hardening and monitoring methods for preventing SEL from the systems design level are proposed. (authors)

A CMOS transconductance-C filter technique for very high frequencies

NARCIS (Netherlands)

Nauta, Bram

1992-01-01

CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters

A Multipurpose CMOS Platform for Nanosensing

Directory of Open Access Journals (Sweden)

Alberto Bonanno

2016-11-01

Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

A Multipurpose CMOS Platform for Nanosensing.

Science.gov (United States)

Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

2016-11-30

This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW-229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

10-bit segmented current steering DAC in 90nm CMOS technology

International Nuclear Information System (INIS)

Bringas, R Jr; Dy, F; Gerasta, O J

2015-01-01

This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm 2 .The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources. (paper)

Nano-electromechanical switch-CMOS hybrid technology and its applications.

Science.gov (United States)

Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

2011-01-01

Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

Development of radiation hard CMOS active pixel sensors for HL-LHC

International Nuclear Information System (INIS)

Pernegger, Heinz

2016-01-01

New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

Science.gov (United States)

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

Integrated 60GHz RF beamforming in CMOS

CERN Document Server

Yu, Yikun; van Roermund, Arthur H M

2011-01-01

""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

Challenges & Roadmap for Beyond CMOS Computing Simulation.

Energy Technology Data Exchange (ETDEWEB)

Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2017-12-01

Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

Fully Integrated Linear Single Photon Avalanche Diode (SPAD) Array with Parallel Readout Circuit in a Standard 180 nm CMOS Process

Science.gov (United States)

Isaak, S.; Bull, S.; Pitter, M. C.; Harrison, Ian.

2011-05-01

This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system, and was fabricated in a UMC 0.18 μm CMOS process. A low-doped p- guard ring (t-well layer) encircling the active area to prevent the premature reverse breakdown. The array is a 16×1 parallel output SPAD array, which comprises of an active quenched SPAD circuit in each pixel with the current value being set by an external resistor RRef = 300 kΩ. The SPAD I-V response, ID was found to slowly increase until VBD was reached at excess bias voltage, Ve = 11.03 V, and then rapidly increase due to avalanche multiplication. Digital circuitry to control the SPAD array and perform the necessary data processing was designed in VHDL and implemented on a FPGA chip. At room temperature, the dark count was found to be approximately 13 KHz for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns.

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Characterization of active CMOS pixel sensors on high resistive substrate

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

2016-07-01

Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Raman study of magnesium induced conversion of polyU·polyA duplexes to polyU·polyA·polyU triplexes

OpenAIRE

Herrera, S. J. Espinoza; Štepánek, J.

2010-01-01

Raman titration experiment with magnesium salt added gradually to aqueous solution of duplexes formed by RNA homopolynucleotides polyU and polyA was performed to reveal its effect on homopolynucleotide complexes. Statistical analysis of obtained spectral set has confirmed the effect already found by less structurally sensitive methods [Nucleic Acids Res. 31(17) (2003), 5101–5107] that at sufficiently high concentrations magnesium causes transformation of polyU·polyA duplexes to polyU·polyA·po...

Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

CERN Document Server

Nguyen, Cam

2017-01-01

This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Risti{c}, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

CERN Document Server

Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

2003-01-01

Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Gaudiello, Andrea; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

Science.gov (United States)

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

Energy Technology Data Exchange (ETDEWEB)

Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

Science.gov (United States)

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

International Nuclear Information System (INIS)

Li Shu; Zhang Tong

2008-01-01

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance

Electromagnetic Investigation of a CMOS MEMS Inductive Microphone

Directory of Open Access Journals (Sweden)

Farès TOUNSI

2009-09-01

Full Text Available This paper presents a detailed electromagnetic modeling for a new structure of a monolithic CMOS micromachined inductive microphone. We have shown, that the use of an alternative current (AC in the primary fixed inductor results in a substantially higher induced voltage in the secondary inductor comparing to the case when a direct current (DC is used. The expected increase of the induced voltage can be expressed by a voltage ratio of AC and DC solutions that is in the range of 3 to 6. A prototype fabrication of this microphone has been realized using a combination of standard CMOS 0.6 µm process with a CMOS-compatible post-process consisting in a bulk micromachining technology. The output voltage of the electrodynamic microphone that achieves the µV range can be increased by the use of the symmetric dual-layer spiral inductor structure.

CMOS Silicon-on-Sapphire RF Tunable Matching Networks

Directory of Open Access Journals (Sweden)

Chamseddine Ahmad

2006-01-01

Full Text Available This paper describes the design and optimization of an RF tunable network capable of matching highly mismatched loads to 50 at 1.9 GHz. Tuning was achieved using switched capacitors with low-loss, single-transistor switches. Simulations show that the performance of the matching network depends strongly on the switch performances and on the inductor losses. A 0.5 m silicon-on-sapphire (SOS CMOS technology was chosen for network implementation because of the relatively high-quality monolithic inductors achievable in the process. The matching network provides very good matching for inductive loads, and acceptable matching for highly capacitive loads. A 1 dB compression point greater than dBm was obtained for a wide range of load impedances.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

International Nuclear Information System (INIS)

Wang Riyan; Li Zhengping; Zhang Weifeng; Zeng Longyue; Huang Jiwei

2012-01-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, −7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply. (semiconductor integrated circuits)

CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

Directory of Open Access Journals (Sweden)

Pei-Zen Chang

2012-12-01

Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

Electrochemical characterization of mixed self-assembled films of water-soluble single-walled carbon nanotube-poly(m-aminobenzene sulfonic acid) and Iron(II) tetrasulfophthalocyanine

CSIR Research Space (South Africa)

Agboola, BO

2010-09-01

Full Text Available The redox activities of water-soluble iron(II) tetrasulfophthalocyanine (FeTSPc) and single-walled carbon nanotube-poly(m-aminobenzene sulfonic acid) (SWCNT-PABS) adsorbed on a gold surface precoated with a self-assembled monolayer (SAM) of 2...

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

Science.gov (United States)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

CMOS-based avalanche photodiodes for direct particle detection

International Nuclear Information System (INIS)

Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

2007-01-01

Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

The total dose effects on the 1/f noise of deep submicron CMOS transistors

International Nuclear Information System (INIS)

Hu Rongbin; Wang Yuxin; Lu Wu

2014-01-01

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

CERN Document Server

Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

2010-01-01

We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

OpenAIRE

Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

2011-01-01

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

KAUST Repository

Ghoneim, Mohamed T.; Alfaraj, Nasir; Torres-Sevilla, Galo A.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

2016-01-01

. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied

Application of CMOS Technology to Silicon Photomultiplier Sensors

Science.gov (United States)

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

Directory of Open Access Journals (Sweden)

Chang-Hung Lee

2014-05-01

Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

Science.gov (United States)

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

Science.gov (United States)

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process

International Nuclear Information System (INIS)

Ji Xu; Li Zhihong; Li Juan; Wang Yangyuan; Xi Jianzhong

2008-01-01

This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra process required. A partially split cantilever configuration is developed for the lateral force detection. The piezoresistors are self-aligned to the split cantilever, and therefore the width of the beam is only limited by lithography. Consequently, this kind of cantilever potentially has a high resolution. The preliminary experimental results show expected performances of the fabricated piezoresistors and electronic circuits

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

Science.gov (United States)

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Ristic, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

CMOS voltage references an analytical and practical perspective

CERN Document Server

Kok, Chi-Wah

2013-01-01

A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

International Nuclear Information System (INIS)

Estreich, D.B.

1978-11-01

A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

Energy Technology Data Exchange (ETDEWEB)

Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin' an, E-mail: wangxa@szpku.edu.c [Key Laboratory of Integrated Microsystems, Shenzhen Graduate School of Peking University, Shenzhen 518055 (China)

2009-06-01

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 x 200 mum{sup 2} without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

International Nuclear Information System (INIS)

Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin'an

2009-01-01

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 x 200 μm 2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

Science.gov (United States)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

The review of radiation effects of γ total dose in CMOS circuits

International Nuclear Information System (INIS)

Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

1992-01-01

Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

Science.gov (United States)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

Energy loss function for biological material: poly(CSP)

International Nuclear Information System (INIS)

Fung, A.Y.C.; Zaider, M.

1994-01-01

In this paper calculated cross sections are presented for the interaction of electrons with poly(CSP), a single-stranded chain that contains one cytosine sugar phosphate unit in the elementary cell. To model a single strand of helical DNA (e.g. the base stacking), the Watson-Crick model for the geometry of poly(CSP) has been used. The use, for computational simplicity, of a single, rather than a double stranded polynucleotide may be justified on the basis of previous calculations indicating that -to a good approximation - the electronic structure (other than excitation states) of complementary base pairs may be described as a superposition of the corresponding structures of the individual components. (Author)

Latch-up control in CMOS integrated circuits

International Nuclear Information System (INIS)

Ochoa, A. Jr.; Estreich, D.B.; Dawes, W.R. Jr.

1979-01-01

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

A novel CMOS SRAM feedback element for SEU environments

International Nuclear Information System (INIS)

Verghese, S.; Wortman, J.J.; Kerns, S.E.

1987-01-01

A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells

Materials Characterization of CIGS solar cells on Top of CMOS chips

NARCIS (Netherlands)

Lu, J.; Liu, W.; Kovalgin, A.Y.; Sun, Y.; Schmitz, J.; Venkatasubramanian, R.; Radousky, H.; Liang, H.

2011-01-01

In the current work, we present a detailed study on the material properties of the CIGS layers, fabricated on top of the CMOS chips, and compare the results with the fabrication on standard glass substrates. Almost identical elemental composition on both glass and CMOS chips (within measurement

Radiation imaging detectors made by wafer post-processing of CMOS chips

NARCIS (Netherlands)

Blanco Carballo, V.M.

2009-01-01

In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

Science.gov (United States)

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

Two CMOS BGR using CM and DTMOST techniques

International Nuclear Information System (INIS)

Mohd-Yasin, F.; Teh, Y.K.; Choong, F.; Reaz, M.B.I.

2009-06-01

Two CMOS BGR using current mode (0.044mm 2 ) and Dynamic Threshold MOST (0.017mm 2 ) techniques are designed on CMOS 0.18μm process. On-wafer measurement shows both circuits have minimum operating V DD 1.28V at 25 o C; taking 2.1μA and 0.5μA (maximum current 3.1μA and 1.1μA) and output voltage of 514mV and 457mV. Both circuits could support V DD range up to 4V required by passive UHF RFID. (author)

A CMOS silicon spin qubit

Science.gov (United States)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Analog filters in nanometer CMOS

CERN Document Server

Uhrmann, Heimo; Zimmermann, Horst

2014-01-01

Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

International Nuclear Information System (INIS)

Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

2011-01-01

The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

Simple BiCMOS CCCTA design and resistorless analog function realization.

Science.gov (United States)

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

Directory of Open Access Journals (Sweden)

Worapong Tangsrirat

2014-01-01

Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Latch-up in CMOS integrated circuits

International Nuclear Information System (INIS)

Estreich, D.B.; Dutton, R.W.

1978-04-01

An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

Energy Technology Data Exchange (ETDEWEB)

Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

2000-08-10

In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition

Directory of Open Access Journals (Sweden)

Golnaz Karbasian

2017-03-01

Full Text Available Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics.

Fabrication of single walled carbon nanotubes/poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) layers under enhanced gravity drying

International Nuclear Information System (INIS)

Rincón, M.E.; Alvarado-Tenorio, G.; Vargas, M.G.; Ramos, E.; Sánchez-Tizapa, M.

2015-01-01

In this contribution, we explore the use of enhanced gravity in order to achieve composite films of single walled carbon nanotubes (SWCNTs)/poly(3,4-ethylenedioxythiophene):polystyrenesulfonate (PEDOT:PSS) with improved properties. The samples were characterized by atomic force microscopy, scanning electron microscopy, and electrochemical impedance spectroscopy, in order to determine the differences caused by the enhanced gravity. Impedance spectroscopy results show that there is an improvement of the electrical properties of the SWCNT/PEDOT:PSS junction, manifested as lower contact resistance, modified chemical capacitance, and induced p-type doping. A force-induced interpenetration of the polymer into the SWCNT network and the efficient removal of water and PSS are proposed to explain the results. The transparency and electrical properties of these films forecast their application as a buffer layer in organic solar cell heterojunctions, or as hole transporting materials in perovskite-based solar cells. - Highlights: • A technique to fabricate conductive films of SWCNT/PEDOT:PSS is presented. • The technique is based on enhanced gravity drying. • Improved interpenetration of the bilayer SWCNT/PEDOT:PSS system • Enhanced gravity increases the p-type conductivity of the film. • Impedance spectroscopy confirms the improvement on the electrical properties.

Total dose and dose rate radiation characterization of EPI-CMOS radiation hardened memory and microprocessor devices

International Nuclear Information System (INIS)

Gingerich, B.L.; Hermsen, J.M.; Lee, J.C.; Schroeder, J.E.

1984-01-01

The process, circuit discription, and total dose radiation characteristics are presented for two second generation hardened 4K EPI-CMOS RAMs and a first generation 80C85 microprocessor. Total dose radiation performance is presented to 10M rad-Si and effects of biasing and operating conditions are discussed. The dose rate sensitivity of the 4K RAMs is also presented along with single event upset (SEU) test data

A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

DEFF Research Database (Denmark)

Olesen, Ole

circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

A CMOS Humidity Sensor for Passive RFID Sensing Applications

Directory of Open Access Journals (Sweden)

Fangming Deng

2014-05-01

Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

A CMOS Humidity Sensor for Passive RFID Sensing Applications

Science.gov (United States)

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

Science.gov (United States)

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

The CMOS integration of a power inverter

Science.gov (United States)

Mannarino, Eric Francis

Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this process using two topologies. The first is a cell-based switched-capacitor topology first presented by Ke Zou. The second is a novel topology that explores the advantage of using a bused input-output system, as in digital electronics. Simulations run on both topologies confirm the high-efficiency demonstrated in Zou’s process as well as the advantage the bus-based system has in output voltage levels.

Design and fabrication of a CMOS-compatible MHP gas sensor

Directory of Open Access Journals (Sweden)

Ying Li

2014-03-01

Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

CMOS cassette for digital upgrade of film-based mammography systems

Science.gov (United States)

Baysal, Mehmet A.; Toker, Emre

2006-03-01

While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

Desenvolvimento de uma matriz de portas CMOS

OpenAIRE

Jose Geraldo Mendes Taveira

1991-01-01

Resumo: É apresentado o projeto de uma matriz deportas CMOS. O capítulo 11 descreve as etapas de projeto, incluindo desde a escolha da topologia das células internas e de interface, o projeto e a simulação elétrica, até a geração do lay-out. Ocaprtulo III apresenta o projeto dos circuitos de aplicação, incluídos para permitir a validação da matriz. Os circuitos de apl icação são : Oscilador em anel e comparador de códigos. A matriz foi difundida no Primeiro Projeto Multi-Usuário CMOS Brasile...

Ultralow-loss CMOS copper plasmonic waveguides

DEFF Research Database (Denmark)

Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

2016-01-01

with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

Science.gov (United States)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

International Nuclear Information System (INIS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-01-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

Science.gov (United States)

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

The impact transconductance parameter and threshold voltage of MOSFET’s in static characteristics of CMOS inverter

Directory of Open Access Journals (Sweden)

Milaim Zabeli

2017-11-01

Full Text Available The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements.

Improved Space Object Orbit Determination Using CMOS Detectors

Science.gov (United States)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Guo-Neng Lu

2009-01-01

Full Text Available We present a single-transistor pixel for CMOS image sensors (CIS. It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

Science.gov (United States)

Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

2009-01-01

We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

Multi-target electrochemical biosensing enabled by integrated CMOS electronics

International Nuclear Information System (INIS)

Rothe, J; Lewandowska, M K; Heer, F; Frey, O; Hierlemann, A

2011-01-01

An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 µM choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

International Nuclear Information System (INIS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.

2016-01-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

Science.gov (United States)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

Energy Technology Data Exchange (ETDEWEB)

Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

2016-09-21

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

A scalable neural chip with synaptic electronics using CMOS integrated memristors

International Nuclear Information System (INIS)

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-01-01

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

Science.gov (United States)

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Science.gov (United States)

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Above-CMOS a-Si and CIGS Solar Cells for Powering Autonomous Microsystems

NARCIS (Netherlands)

Lu, J.; Liu, W.; van der Werf, C.H.M.; Kovalgin, A.Y.; Sun, Y.; Schropp, R.E.I.; Schmitz, J.

2010-01-01

Two types of solar cells are successfully grown on chips from two CMOS generations. The efficiency of amorphous-silicon (a-Si) solar cells reaches 5.2%, copperindium-gallium-selenide (CIGS) cells 7.1%. CMOS functionality is unaffected. The main integration issues: adhesion, surface topography, metal

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

Directory of Open Access Journals (Sweden)

Nan Guo

2014-10-01

Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

Science.gov (United States)

Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

2017-05-01

In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

Association of poly-purine/poly-pyrimidine sequences with meiotic recombination hot spots

Directory of Open Access Journals (Sweden)

Pitt Joel PW

2006-07-01

Full Text Available Abstract Background Meiotic recombination events have been found to concentrate in 1–2.5 kilo base regions, but these recombination hot spots do not share a consensus sequence and why they occur at specific sites is not fully understood. Some previous evidence suggests that poly-purine/poly-pyrimidine (poly-pu/py tracts (PPTs, a class of sequence with distinctive biochemical properties, could be involved in recombination, but no general association of PPTs with meiotic recombination hot spots has previously been reported. Results We used computational methods to investigate in detail the relationship between PPTs and hot spots. We show statistical associations of PPT frequency with hot spots of meiotic recombination initiating lesions, double-strand breaks, in the genome of the yeast S. cerevisiae and with experimentally well characterized human meiotic recombination hot spots. Supporting a possible role of poly-pu/py-rich sequences in hot spot recombination, we also found that all three single nucleotide polymorphisms previously shown to be associated with human hot spot activity changes occur within sequence contexts of 14 bp or longer that are 85% or more poly-pu/py and at least 70% G/C. These polymorphisms are all close to the hot spot mid points. Comparing the sequences of experimentally characterized human hot spots with the orthologous regions of the chimpanzee genome previously shown not to contain hot spots, we found that in all five cases in which comparisons for the hot spot central regions are possible with publicly available sequence data, there are differences near the human hot spot mid points within sequences 14 bp or longer consisting of more than 80% poly-pu/py and at least 50% G/C. Conclusion Our results, along with previous evidence for the unique biochemical properties and recombination-stimulating potential of poly-pu/py-rich sequences, suggest that the possible functional involvement of this type of sequence in meiotic

A 205GHz Amplifier in 90nm CMOS Technology

Science.gov (United States)

2017-03-01

10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

An introduction to deep submicron CMOS for vertex applications

CERN Document Server

Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

2001-01-01

Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

Linear CMOS RF power amplifiers a complete design workflow

CERN Document Server

Ruiz, Hector Solar

2013-01-01

The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

CMOS circuits for piezoelectric energy harvesters efficient power extraction, interface modeling and loss analysis

CERN Document Server

Hehn, Thorsten

2014-01-01

This book deals with the challenge of exploiting ambient vibrational energy which can be used to power small and low-power electronic devices, e.g. wireless sensor nodes. Generally, particularly for low voltage amplitudes, low-loss rectification is required to achieve high conversion efficiency. In the special case of piezoelectric energy harvesting, pulsed charge extraction has the potential to extract more power compared to a single rectifier. For this purpose, a fully autonomous CMOS integrated interface circuit for piezoelectric generators which fulfills these requirements is presented.Due

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

Science.gov (United States)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

International Nuclear Information System (INIS)

Kim, Y; Pham, C; Chang, J P

2015-01-01

This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

Applications of Si/SiGe heterostructures to CMOS devices

International Nuclear Information System (INIS)

Sidek, R.M.

1999-03-01

For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

Research-grade CMOS image sensors for demanding space applications

Science.gov (United States)

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2017-11-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Development of CMOS Imager Block for Capsule Endoscope

International Nuclear Information System (INIS)

Shafie, S; Fodzi, F A M; Tung, L Q; Lioe, D X; Halin, I A; Hasan, W Z W; Jaafar, H

2014-01-01

This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5 V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5 V to 3.3 V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5 V to 3.3 V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

Multifunctional poly(alkyl methacrylate) films for dental care

International Nuclear Information System (INIS)

Nielsen, Birthe V; Nevell, Thomas G; Barbu, Eugen; Smith, James R; Tsibouklis, John; Rees, Gareth D

2011-01-01

Towards the evaluation of non-permanent dental coatings for their capacity to impart dental-care benefits, thin films of a homologous series of comb-like poly(alkyl methacrylate)s (ethyl to octadecyl) have been deposited, from aqueous latex formulations, onto dentally relevant substrates. AFM studies have shown that the thickness (40-300 nm) and surface roughness (8-12 nm) of coherent polymer films are influenced by the degree of polymerization and by the length of the pendant chain. Of the polymers under consideration, poly(butyl methacrylate) formed a close-packed film that conferred to dental substrates a high degree of inhibition to acid-mediated erosion (about 27%), as evaluated by released-phosphate determinations. The potential utility of the coatings to act as anti-sensitivity barriers has been evaluated by determining the hydraulic conductance of coated bovine-dentine substrates; single treatments of dentine discs with poly(butyl methacrylate) or with poly(ethyl methacrylate) effected mean respective reductions in fluid flow of about 23% with respect to water-treated controls; repeated applications of the poly(butyl methacrylate) latex led to mean reductions in fluid flow of about 80%. Chromometric measurements have shown that pellicle-coated hydroxyapatite discs treated with poly(butyl methacrylate), poly(hexyl methacrylate) or poly(lauryl methacrylate) exhibit significant resistance to staining by food chromogens.

Multifunctional poly(alkyl methacrylate) films for dental care

Energy Technology Data Exchange (ETDEWEB)

Nielsen, Birthe V; Nevell, Thomas G; Barbu, Eugen; Smith, James R; Tsibouklis, John [School of Pharmacy and Biomedical Sciences, University of Portsmouth, Portsmouth, Hampshire, PO1 2DT (United Kingdom); Rees, Gareth D [GlaxoSmithKline R and D, St George' s Avenue, Weybridge, Surrey, KT13 0DE (United Kingdom)

2011-02-15

Towards the evaluation of non-permanent dental coatings for their capacity to impart dental-care benefits, thin films of a homologous series of comb-like poly(alkyl methacrylate)s (ethyl to octadecyl) have been deposited, from aqueous latex formulations, onto dentally relevant substrates. AFM studies have shown that the thickness (40-300 nm) and surface roughness (8-12 nm) of coherent polymer films are influenced by the degree of polymerization and by the length of the pendant chain. Of the polymers under consideration, poly(butyl methacrylate) formed a close-packed film that conferred to dental substrates a high degree of inhibition to acid-mediated erosion (about 27%), as evaluated by released-phosphate determinations. The potential utility of the coatings to act as anti-sensitivity barriers has been evaluated by determining the hydraulic conductance of coated bovine-dentine substrates; single treatments of dentine discs with poly(butyl methacrylate) or with poly(ethyl methacrylate) effected mean respective reductions in fluid flow of about 23% with respect to water-treated controls; repeated applications of the poly(butyl methacrylate) latex led to mean reductions in fluid flow of about 80%. Chromometric measurements have shown that pellicle-coated hydroxyapatite discs treated with poly(butyl methacrylate), poly(hexyl methacrylate) or poly(lauryl methacrylate) exhibit significant resistance to staining by food chromogens.

Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

OpenAIRE

Hassan Jassim Motlak

2015-01-01

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to...

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

Science.gov (United States)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

CMOS technology: a critical enabler for free-form electronics-based killer applications

Science.gov (United States)

Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

2016-05-01

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

Science.gov (United States)

Rimoldi, M.

2017-12-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

The study of poly-Si n+pp+ solar cells

International Nuclear Information System (INIS)

Aboud, S.R.

1990-01-01

The electrical and optical properties such as (activation energy, optical energy gap, and gap state density) of the polycrystalline silicon (poly-Si) have been studied. A comparative study between the chemical and mechanical polishing to clean and polish the poly-Si surface were done through the measurement of the reflectivity of these surfaces. A group of solar cells of type n + pp + were prepared, using p-type poly-Si wafers (SISLO). Solar cells were also prepared using single silicon (Sing-Si) with and, without (BSF) to study the effect of (BSF) on Sing-Si cell and a comparative study between poly-Si cell and Sing-Si cell under the same conditions. 2 tabs.; 45 figs.; 49 refs

Analysis of the resistive network in a bio-inspired CMOS vision chip

Science.gov (United States)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

CMOS VHF transconductance-C lowpass filter

NARCIS (Netherlands)

Nauta, Bram

1990-01-01

Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

International Nuclear Information System (INIS)

Cheng, Chao-Lin; Fang, Weileun; Tsai, Ming-Han

2015-01-01

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

Science.gov (United States)

2012-12-14

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations, Modifications and Rulings AGENCY: U.S... United States after importation of certain CMOS image sensors and products containing the same based on...

Performance simulation and analysis of a CMOS/nano hybrid nanoprocessor system

International Nuclear Information System (INIS)

Cabe, Adam C; Das, Shamik

2009-01-01

This paper provides detailed simulation results and analysis of the prospective performance of hybrid CMOS/nanoelectronic processor systems based upon the field-programmable nanowire interconnect (FPNI) architecture. To evaluate this architecture, a complete design was developed for an FPNI implementation using 90 nm CMOS with 15 nm wide nanowire interconnects. Detailed simulations of this design illustrate that critical design choices and tradeoffs exist beyond those specified by the architecture. This includes the selection of the types of junction nanodevices, as well as the implementation of low-level circuits. In particular, the simulation results presented here show that only nanodevices with an 'on/off' current ratio of 200 or more are suitable to produce correct system-level behaviour. Furthermore, the design of the CMOS logic gates in the FPNI system must be customized to accommodate the resistances of both 'on'-state and 'off'-state nanodevices. Using these customized designs together with models of suitable nanodevices, additional simulations demonstrate that, relative to conventional 90 nm CMOS FPGA systems, performance gains can be obtained of up to 70% greater speed or up to a ninefold reduction in energy consumption.

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

Science.gov (United States)

Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

2013-03-06

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

Energy Technology Data Exchange (ETDEWEB)

Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng, E-mail: xxd@tju.edu.c [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China)

2009-12-15

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 {mu}m EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10{sup -9}. The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

International Nuclear Information System (INIS)

Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng

2009-01-01

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10 -9 . The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

Voltammetric sensing of bisphenol A based on a single-walled carbon nanotubes/poly{3-butyl-1-[3-(N-pyrrolyl)propyl] imidazolium ionic liquid} composite film modified electrode

International Nuclear Information System (INIS)

Chen, Xuemin; Ren, Tongqing; Ma, Ming; Wang, Zhengguo; Zhan, Guoqing; Li, Chunya

2013-01-01

Highlights: • Single-walled carbon nanotubes (SWCNTs)-ionic liquid (IL) nanocomposite fabrication. • SWCNTs-Poly-IL film modified electrode was prepared and characterized. • Voltammetric behaviors of bisphenol A were investigated thoroughly. • Sensitive voltammetric method for bisphenol A determination was developed. -- Abstract: Using carboxylic acid-functionalized single walled carbon nanotubes (SWCNTs-COO − ) as an anion and 3-butyl-1-[3-(N-pyrrolyl)propyl]imidazolium as a cation, a novel SWCNTs-COO-ionic liquid (SWCNTs-COO-IL) nanocomposite was fabricated successfully. The as-prepared SWCNTs-COO-IL nanocomposite was confirmed with transmission electron microscopy, X-ray photoelectron spectroscopy, UV–vis, FTIR and Raman spectroscopy. The SWCNTs-COO-IL nanocomposite was coated onto a glassy carbon electrode surface followed by cyclic voltammetric scanning to fabricate a SWCNTs/poly{3-butyl-1-[3-(N-pyrrolyl)propyl] imidazolium ionic liquid} composite film modified electrode (SWCNTs/Poly-IL/GCE). Scanning electron microscope and electrochemical impedance spectroscopy were used to characterize SWCNTs/Poly-IL/GCE. Electrochemical behaviors of bisphenol A (BPA) at the SWCNTs/Poly-IL/GCE were investigated thoroughly. It was found that an obvious oxidation peak appeared without reduction peak in the reverse scanning, indicating an irreversible electrochemical process. The oxidation peak currents of BPA were linearly related to scan rate in the range of 20–300 mV s −1 , suggesting an adsorption controlled process rather than a diffusion controlled process. Differential pulse voltammetry was employed for the voltammetric sensing of BPA. Experimental conditions such as film thickness, pH value, accumulation potential and time that influence the analytical performance of the SWCNTs/Poly-IL/GCE were optimized. Under optimal conditions, the oxidation peak current was linearly related to BPA concentration in the range of 5.0 × 10 −9 to 3.0 × 10 −5 mol L

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Science.gov (United States)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

A back-illuminated megapixel CMOS image sensor

Science.gov (United States)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

RF Circuit Design in Nanometer CMOS

NARCIS (Netherlands)

Nauta, Bram

2007-01-01

With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

Science.gov (United States)

Davidson, Bradley Darren

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

CMOS technology: a critical enabler for free-form electronics-based killer applications

KAUST Repository

Hussain, Muhammad Mustafa

2016-05-17

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

NARCIS (Netherlands)

Acar, M.

2011-01-01

In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers in the mainstream CMOS technology is essential. In general, CMOS Power Amplifiers (PAs) require high voltage to decrease the matching network losses and for high

Optimization Design Method for the CMOS-type Capacitive Micro-Machined Ultrasonic Transducer

Directory of Open Access Journals (Sweden)

D. Y. Chiou

2011-12-01

Full Text Available In this study, an integrated modeling technique for characterization and optimization design of the complementary metal-oxide-semiconductor (CMOS capacitive micro-arrayed ultrasonic transducer (pCMOS-CMUT is presented. Electromechanical finite element simulations are performed to investigate its operational characteristics, such as the collapse voltage and the resonant frequency. Both the numerical and experimental results are in good agreement. In order to simultaneously customize the resonant frequency and minimize the collapse voltage, the genetic algorithm (GA is applied to optimize dimensional parameters of the transducer. From the present results, it is concluded that the FE/GA coupling approach provides another efficient numerical tool for multi-objective design of the pCMOS-CMUT.

Investigations of radiation-induced strand breaks of poly(U) in aqueous solutions

International Nuclear Information System (INIS)

Lemaire, D.G.E.

1984-01-01

DNA strand breaks induced by γ irradiation were studied in polyuridylic acid (Poly(U)), a single-strand model substance with a single base. Poly(U) in diluted, aqueous solution was irradiated in a Co-γ source, and the 100 eV yields of strand breaks (Cr values) were determined on the basis of the loss of molecular weight. The molecular weight was determined by small-angle laser light scattering. (orig./PW) [de

Radiation hardness of CMOS monolithic active pixel sensors manufactured in a 0.18 μm CMOS process

Energy Technology Data Exchange (ETDEWEB)

Linnik, Benjamin [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

2015-07-01

CMOS Monolithic Active Pixels Sensors (MAPS) are considered as the technology of choice for various vertex detectors in particle and heavy-ion physics including the STAR HFT, the upgrade of the ALICE ITS, the future ILC detectors and the CBM experiment at FAIR. To match the requirements of those detectors, their hardness to radiation is being improved, among others in a joined research activity of the Goethe University Frankfurt and the IPHC Strasbourg. It was assumed that combining an improved high resistivity (1-8 kΩcm) sensitive medium with the features of a 0.18 μm CMOS process, is suited to reach substantial improvements in terms of radiation hardness as compared to earlier sensor designs. This strategy was tested with a novel generation of sensor prototypes named MIMOSA-32 and MIMOSA-34. We show results on the radiation hardness of those sensors and discuss its impact on the design of future vertex detectors.

Interfacial electrostatics of poly(vinylamine hydrochloride), poly(diallyldimethylammonium chloride), poly-l-lysine, and poly-l-arginine interacting with lipid bilayers.

Science.gov (United States)

McGeachy, A C; Dalchand, N; Caudill, E R; Li, T; Doğangün, M; Olenick, L L; Chang, H; Pedersen, J A; Geiger, F M

2018-04-25

Charge densities of cationic polymers adsorbed to lipid bilayers are estimated from second harmonic generation (SHG) spectroscopy and quartz crystal microbalance with dissipation monitoring (QCM-D) measurements. The systems surveyed included poly(vinylamine hydrochloride) (PVAm), poly(diallyldimethylammonium chloride) (PDADMAC), poly-l-lysine (PLL), and poly-l-arginine (PLR), as well as polyalcohol controls. Upon accounting for the number of positive charges associated with each polyelectrolyte, the binding constants and apparent free energies of adsorption as estimated from SHG data are comparable despite differences in molecular masses and molecular structure, with ΔGads values of -61 ± 2, -58 ± 2, -57 ± 1, -52 ± 2, -52 ± 1 kJ mol-1 for PDADMAC400, PDADMAC100, PVAm, PLL, and PLR, respectively. Moreover, we find charge densities for polymer adlayers of approximately 0.3 C m-2 for poly(diallyldimethylammonium chloride) while those of poly(vinylamine) hydrochloride, poly-l-lysine, and poly-l-arginine are approximately 0.2 C m-2. Time-dependent studies indicate that polycation adsorption to supported lipid bilayers is only partially reversible for most of the polymers explored. Poly(diallyldimethylammonium chloride) does not demonstrate reversible binding even over long timescales (>8 hours).

A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

Science.gov (United States)

Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

2012-08-01

An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

Nanosecond-laser induced crosstalk of CMOS image sensor

Science.gov (United States)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

CERN Document Server

Aznar, Francisco; Calvo Lopez, Belén

2013-01-01

This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

From vertex detectors to inner trackers with CMOS pixel sensors

CERN Document Server

Besson, A.

2017-01-01

The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

Designing a robust high-speed CMOS-MEMS capacitive humidity sensor

International Nuclear Information System (INIS)

Lazarus, N; Fedder, G K

2012-01-01

In our previous work (Lazarus and Fedder 2011 J. Micromech. Microeng. 21 0650281), we demonstrated a CMOS-MEMS capacitive humidity sensor with a 72% improvement in sensitivity over the highest previously integrated on a CMOS die. This paper explores a series of methods for creating a faster and more manufacturable high-sensitivity capacitive humidity sensor. These techniques include adding oxide pillars to hold the plates apart, spin coating polymer to allow sensors to be fabricated more cheaply, adding a polysilicon heater and etching away excess polymer in the release holes. In most cases a tradeoff was found between sensitivity and other factors such as response time or robustness. A robust high-speed sensor was designed with a sensitivity of 0.21% change in capacitance per per cent relative humidity, while dropping the response time constant from 70 to 4s. Although less sensitive than our design, the sensor remains 17% more sensitive than the most sensitive interdigitated designs successfully integrated with CMOS. (paper)

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

Science.gov (United States)

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

Development of a lens-coupled CMOS detector for an X-ray inspection system

International Nuclear Information System (INIS)

Kim, Ho Kyung; Ahn, Jung Keun; Cho, Gyuseong

2005-01-01

A digital X-ray imaging detector based on a complementary metal-oxide-semiconductor (CMOS) image sensor has been developed for X-ray non-destructive inspection applications. This is a cost-effective solution because of the availability of cheap commercial standard CMOS image sensors. The detector configuration adopts an indirect X-ray detection method by using scintillation material and lens assembly. As a feasibility test of the developed lens-coupled CMOS detector as an X-ray inspection system, we have acquired X-ray projection images under a variety of imaging conditions. The results show that the projected image is reasonably acceptable in typical non-destructive testing (NDT). However, the developed detector may not be appropriate for laminography due to a low light-collection efficiency of lens assembly. In this paper, construction of the lens-coupled CMOS detector and its specifications are described, and the experimental results are presented. Using the analysis of quantum accounting diagram, inefficiency of the lens-coupling method is discussed

Regio-Regular Oligo and Poly(3-hexyl thiophene): Precise Structural Markers from the Vibrational Spectra of Oligomer Single Crystals.

KAUST Repository

Brambilla, Luigi

2014-10-14

© 2014 American Chemical Society. In this work, we report a comparative analysis of the infrared and Raman spectra of octa(3-hexylthiophene) (3HT)8, trideca(3-hexylthiophene) (3HT)13, and poly(3-hexylthiophene) P3HT recorded in various phases, namely, amorphous, semicrystalline, polycrystalline and single crystal. We have based our analysis on the spectra of the (3HT)8 single crystal (whose structure has been determined by selected area electron diffraction) taken as reference and on the results of DFT calculations and molecular vibrational dynamics. New and precise spectroscopic markers of the molecular structures show the existence of three phases, namely: hairy (phase 1), ordered (phase 2), and disordered/amorphous (phase 3). Conceptually, the identified markers can be used for the molecular structure analysis of other similar systems.

Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

NARCIS (Netherlands)

Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

Characterizing Subpixel Spatial Resolution of a Hybrid CMOS Detector

Science.gov (United States)

Bray, Evan; Burrows, Dave; Chattopadhyay, Tanmoy; Falcone, Abraham; Hull, Samuel; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

The detection of X-rays is a unique process relative to other wavelengths, and allows for some novel features that increase the scientific yield of a single observation. Unlike lower photon energies, X-rays liberate a large number of electrons from the silicon absorber array of the detector. This number is usually on the order of several hundred to a thousand for moderate-energy X-rays. These electrons tend to diffuse outward into what is referred to as the charge cloud. This cloud can then be picked up by several pixels, forming a specific pattern based on the exact incident location. By conducting the first ever “mesh experiment" on a hybrid CMOS detector (HCD), we have experimentally determined the charge cloud shape and used it to characterize responsivity of the detector with subpixel spatial resolution.

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures.

Science.gov (United States)

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2009-07-01

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n(+)/p-sub, n-well/p-sub and p(+)/n-well/p-sub. All structures were fabricated in a 0.5 mum 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated-the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 x and 1.6 x over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 x and 1.2 x improvement over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) while the p(+)/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

Science.gov (United States)

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Scaling Rule for Very Shallow Trench IGBT toward CMOS Process Compatibility

OpenAIRE

Tanaka, Masahiro; Omura, Ichiro

2012-01-01

Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables t...

Radiation effects of protons and 60Co γ rays on CMOS operational amplifier

International Nuclear Information System (INIS)

Lu Wu; Ren Diyuan; Guo Qi; Yu Xuefeng; Yan Rongliang

1997-01-01

Radiation effects of 60 Co γ ray and 4,7 and 30 MeV protons on LF 7650 CMOS operational amplifier were investigated. The damage mechanism of LF7650 was discussed. It is indicated that the mobility reduction of major carrier caused by ionizing and displacement damage is the chief mechanism causing the failure of CMOS operational amplifier irradiated by protons, and that is why the degradation of LF 7650 caused by protons is much more serious than that caused by 60 Co γ ray. In addition, a comparison of proton radiation effects on CMOS operational amplifier and MOSFET showed a significant difference in mechanism

Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

Science.gov (United States)

Zargham, Meysam; Gulak, P Glenn

2015-04-01

Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Micromachined high-performance RF passives in CMOS substrate

International Nuclear Information System (INIS)

Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

2016-01-01

This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

CMOS switched current phase-locked loop

NARCIS (Netherlands)

Leenaerts, D.M.W.; Persoon, G.G.; Putter, B.M.

1997-01-01

The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

International Nuclear Information System (INIS)

He Wenwei; Meng Qiao; Zhang Yi; Tang Kai

2014-01-01

A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm 2 with the pad. It consumes 210 mW from a 1.2 V single supply. (semiconductor integrated circuits)

First result on biased CMOS MAPs-on-diamond devices

Energy Technology Data Exchange (ETDEWEB)

Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

2015-10-01

Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

Science.gov (United States)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

Geant4-based simulations of charge collection in CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Esposito, M.; Allinson, N.M.; Price, T.; Anaxagoras, T.

2017-01-01

Geant4 is an object-oriented toolkit for the simulation of the interaction of particles and radiation with matter. It provides a snapshot of the state of a simulated particle in time, as it travels through a specified geometry. One important area of application is the modelling of radiation detector systems. Here, we extend the abilities of such modelling to include charge transport and sharing in pixelated CMOS Active Pixel Sensors (APSs); though similar effects occur in other pixel detectors. The CMOS APSs discussed were developed in the framework of the PRaVDA consortium to assist the design of custom sensors to be used in an energy-range detector for proton Computed Tomography (pCT). The development of ad-hoc classes, providing a charge transport model for a CMOS APS and its integration into the standard Geant4 toolkit, is described. The proposed charge transport model includes, charge generation, diffusion, collection, and sharing across adjacent pixels, as well as the full electronic chain for a CMOS APS. The proposed model is validated against experimental data acquired with protons in an energy range relevant for pCT.

CMOS capacitive biosensors for highly sensitive biosensing applications.

Science.gov (United States)

Chang, An-Yu; Lu, Michael S-C

2013-01-01

Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

Custom high-reliability radiation-hard CMOS-LSI circuit design

International Nuclear Information System (INIS)

Barnard, W.J.

1981-01-01

Sandia has developed a custom CMOS-LSI design capability to provide high reliability radiation-hardened circuits. This capability relies on (1) proven design practices to enhance reliability, (2) use of well characterized cells and logic modules, (3) computer-aided design tools to reduce design time and errors and to standardize design definition, and (4) close working relationships with the system designer and technology fabrication personnel. Trade-offs are made during the design between circuit complexity/performance and technology/producibility for high reliability and radiation-hardened designs to result. Sandia has developed and is maintaining a radiation-hardened bulk CMOS technology fabrication line for production of prototype and small production volume parts

Backside illuminated CMOS-TDI line scan sensor for space applications

Science.gov (United States)

Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

2018-05-01

A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

International Nuclear Information System (INIS)

Duzer, Theodore van; Feng Yijun; Meng Xiaofan; Whiteley, Stephen R; Yoshikawa, Nobuyuki

2002-01-01

The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented

Effect of CMOS Technology Scaling on Fully-Integrated Power Supply Efficiency

OpenAIRE

Pillonnet , Gaël; Jeanniot , Nicolas

2016-01-01

International audience; Integrating a power supply in the same die as the powered circuits is an appropriate solution for granular, fine and fast power management. To allow same-die co-integration, fully integrated DC-DC converters designed in the latest CMOS technologies have been greatly studied by academics and industrialists in the last decade. However, there is little study concerning the effects of the CMOS scaling on these particular circuits. To show the trends, this paper compares th...

A new method of preventing bulk-Si CMOS devices from latchup

International Nuclear Information System (INIS)

Xu Xianguo; Xu Xi

2004-01-01

A new method, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After we study the design of pseudo-latchup path method in detail, a practice and the corresponding simulation result by computer are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but it cannot be used to eliminate the dose rate upset of bulk-Si CMOS devices. (authors)

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

International Nuclear Information System (INIS)

Wang, Zujun; Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

2014-01-01

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10 8 n/cm 2 s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10 11 , 5 × 10 11 , and 1 × 10 12 n/cm 2 , respectively. The mean dark signal (K D ), dark signal spike, dark signal non-uniformity (DSNU), noise (V N ), saturation output signal voltage (V S ), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2006-01-01

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits

CMOS Pixel Sensors for High Precision Beam Telescopes and Vertex Detectors

International Nuclear Information System (INIS)

Masi, R. de; Baudot, J.; Fontaine, J.-Ch.

2009-01-01

CMOS sensors of the MIMOSA (standing for Minimum Ionising particle MOS Active pixel sensor) series are developed at IPHC since a decade and have ended up with full scale devices used in beam telescopes and in demonstrators of future vertex detectors. The sensors deliver analogue, unfiltered, signals and are therefore limited to read-out frequencies of ∼ 1 kframe/s. Since a few years, a fast architecture is being developed in collaboration with IRFU, which aims to speed up the read-out by 1-2 orders of magnitude. The first full scale sensor based on this architecture was fabricated recently and is being tested. Made of 660,000 pixels (18 μm pitch) covering an active area of ∼ 2 cm 2 , it delivers zero-suppressed binary signals, which allow running at ∼ 10 kframes/s. It will equip the beam telescope of the E.U. project EUDET and serve as a forerunner of the sensor equipping the 2 layers of the PIXEL detector of the STAR experiment at RHIC. The contribution to the conference will overview the main features and test results of this pioneering sensor. It will next describe its evolution towards read-out frequencies approaching 100 kframes/s, as required for the vertex detectors of the CBM experiment at FAIR and at the ILC. Finally, the issue of radiation tolerance will be addressed, in the context of a newly available CMOS process using a depleted substrate. A prototype sensor was fabricated in a such CMOS process. The talk will summarise beam test results showing, for the first time, that fluences of 10 14 n eq /cm 2 may be tolerable for CMOS sensors. Overall, the talk provides an overview of the status and plans of CMOS pixel sensors at the frontier of their achievements and outreach. (author)

Electrical and optical properties of poly(3,4-ethylenedioxythiophene) oxidized with poly(4-styrenesulfonate) and AuCl3-doped reduced graphene oxide/single-walled carbon nanotube films for ultraviolet light-emitting diodes.

Science.gov (United States)

Lee, Byeong Ryong; Lee, Jae Hoon; Kim, Kyeong Heon; Kim, Hee-Dong; Kim, Tae Geun

2014-12-01

We report the effects of poly(3,4-ethylenedioxythiophene) oxidized with poly(4-styrenesulfonate) ( PSS) and gold chloride (AuCl) co-doping on the electrical and optical properties of reduced graphene oxide (RGO)/single-walled carbon nanotube (SWNT) films fabricated by dipcoating methods. The RGO/SWNT films were doped with both AuCl3 dissolved in nitromethane and PSS hole injection layers by spin coating to improve their electrical properties by increasing the work function of the RGO/SWNT films, thereby reducing the Schottky barrier height between the RGO/SWNT and p-GaN films. As a result, we obtained a reduced sheet resistance of 851.9 Ω/Ω and a contact resistance of 1.97 x 10(-1) Ω x cm2, together with a high transmittance of 84.1% at 380 nm. The contact resistance of these films should be further reduced to fully utilize the feature of the electrode scheme proposed in this work, but the current result suggests its potential use as a transparent conductive electrode for ultraviolet light-emitting diodes.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

Science.gov (United States)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

Science.gov (United States)

Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

2015-05-07

In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...... of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses...

Higher cytoplasmic and nuclear poly(ADP-ribose) polymerase expression in familial than in sporadic breast cancer

NARCIS (Netherlands)

Klauke, M.L.; Hoogerbrugge-van der Linden, N.; Budczies, J.; Bult, P.; Prinzler, J.; Radke, C.; van Krieken, J.H.; Dietel, M.; Denkert, C.; Muller, B.M.

2012-01-01

Poly(ADP-ribose) polymerase 1 (PARP) is a key element of the single-base excision pathway for repair of DNA single-strand breaks. To compare the cytoplasmic and nuclear poly(ADP-ribose) expression between familial (BRCA1, BRCA2, or non BRCA1/2) and sporadic breast cancer, we investigated 39 sporadic

A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

International Nuclear Information System (INIS)

Chen Pufeng; Li Zhiqiang; Wang Xiaosong; Zhang Haiying; Ye Tianchun

2010-01-01

An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time. It incorporates two phase-locked loops and one single-sideband (SSB) mixer. A 2-to-1 multiplexer with high linearity is proposed. A modified wideband SSB mixer, quadrature VCO, and layout techniques are also employed. The synthesizer is fabricated in a 0.18 μm CMOS process and operates at 1.5-1.8 V while consuming 40 mA current. The measured phase noise is -128 dBc/Hz at 10 MHz offset, and the sideband rejection is -22 dBc at 7.656 GHz.

A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

Energy Technology Data Exchange (ETDEWEB)

Chen Pufeng; Li Zhiqiang; Wang Xiaosong; Zhang Haiying; Ye Tianchun, E-mail: chenpufeng@ime.ac.c [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

2010-07-15

An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time. It incorporates two phase-locked loops and one single-sideband (SSB) mixer. A 2-to-1 multiplexer with high linearity is proposed. A modified wideband SSB mixer, quadrature VCO, and layout techniques are also employed. The synthesizer is fabricated in a 0.18 {mu}m CMOS process and operates at 1.5-1.8 V while consuming 40 mA current. The measured phase noise is -128 dBc/Hz at 10 MHz offset, and the sideband rejection is -22 dBc at 7.656 GHz.

An Analytical Model for Spectral Peak Frequency Prediction of Substrate Noise in CMOS Substrates

DEFF Research Database (Denmark)

Shen, Ming; Mikkelsen, Jan H.

2013-01-01

This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform us...

CMOS direct time interval measurement of long-lived luminescence lifetimes.

Science.gov (United States)

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

Science.gov (United States)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Implementation of large area CMOS image sensor module using the precision align inspection

International Nuclear Information System (INIS)

Kim, Byoung Wook; Kim, Toung Ju; Ryu, Cheol Woo; Lee, Kyung Yong; Kim, Jin Soo; Kim, Myung Soo; Cho, Gyu Seong

2014-01-01

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a 2×1 butted CMOS image sensor module which except for the size of PCB is 170 mm×170 mm. And the pixel size is 55 μm×55 μm and the number of pixels is 3,072×3,072. The gap between the two CMOS image sensor module was arranged in less than one pixel size

Implementation of large area CMOS image sensor module using the precision align inspection

Energy Technology Data Exchange (ETDEWEB)

Kim, Byoung Wook; Kim, Toung Ju; Ryu, Cheol Woo [Radiation Imaging Technology Center, JBTP, Iksan (Korea, Republic of); Lee, Kyung Yong; Kim, Jin Soo [Nano Sol-Tech INC., Iksan (Korea, Republic of); Kim, Myung Soo; Cho, Gyu Seong [Dept. of Nuclear and Quantum Engineering, KAIST, Daejeon (Korea, Republic of)

2014-12-15

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a 2×1 butted CMOS image sensor module which except for the size of PCB is 170 mm×170 mm. And the pixel size is 55 μm×55 μm and the number of pixels is 3,072×3,072. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

Science.gov (United States)

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

CMOS technology and current-feedback op-amps

DEFF Research Database (Denmark)

Bruun, Erik

1993-01-01

Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

International Nuclear Information System (INIS)

Zhang, L.; Wang, M.; Fu, M.; Zhang, Y.; Yan, W.

2017-01-01

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm 2 .

Structured Analog CMOS Design

CERN Document Server

Stefanovic, Danica

2008-01-01

Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

An ultra-low-power CMOS temperature sensor for RFID applications

Energy Technology Data Exchange (ETDEWEB)

Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao, E-mail: yanna@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2009-04-15

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-mum CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 muA and 1.8 V for continuous operation and achieves an accuracy of +-0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

An ultra-low-power CMOS temperature sensor for RFID applications

International Nuclear Information System (INIS)

Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao

2009-01-01

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 μA and 1.8 V for continuous operation and achieves an accuracy of ±0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

CMOS Voltage-Controlled Oscillator Resilient Design for Wireless Communication Applications

Directory of Open Access Journals (Sweden)

Ekavut Kritchanchai

2015-08-01

Full Text Available Semiconductor process variation and reliability aging effect on CMOS VCO performance has been studied. A technique to mitigate the effect of process variations on the performances of nano-scale CMOS LC-VCO is presented. The LC-VCO compensation uses a process invariant current source. VCO parameters such as phase noise and core power before and after compensation over a wide range of variability are examined. Analytical equations are derived for physical insight. ADS and Monte-Carlo simulation results show that the use of invariant current source improves the robustness of the VCO performance against process variations and device aging.

Pixel front-end development in 65 nm CMOS technology

International Nuclear Information System (INIS)

Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

2014-01-01

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

Poly(ethylene glycol) and poly(dimethyl siloxane): Combining their advantages into efficient CO2 gas separation membranes

NARCIS (Netherlands)

Reijerkerk, Sander; Knoef, Michel H.; Nijmeijer, Dorothea C.; Wessling, Matthias

2010-01-01

Polymer blending is a versatile tool to combine the beneficial properties of two or more components in one single material. Here, we present the preparation, thermal- and mass transport properties of a series of blend membranes made from the commercially available PEBAX® MH 1657 and a poly(ethylene

A New CMOS Posicast Pre-shaper for Vibration Reduction of CMOS Op-Amps

Science.gov (United States)

Rasoulzadeh, M.; Ghaznavi-Ghoushchi, M. B.

2010-06-01

Posicast-based control is a widely used method in vibration reduction of lightly damped oscillatory systems especially in mechanical fields. The target systems to apply Posicast method are the systems which are excited by pulse inputs. Using the Posicast idea, the input pulse is reshaped into a new pulse, which is called Posicast pulse. Applying the generated Posicast pulse reduces the undesired oscillatory manner of under-test systems. In this paper, a fully CMOS Pulse pre-shaper circuit for realization of Posicast command is proposed. Our design is based on delay-and-add approach for the incoming pulses. The delay is done via a modified Schmitt Trigger-like circuit. The adder circuit is implemented by a simple non-binary analog adder terminated by a passive element. Our proposed design has a reasonable flexibility in configuration of time delay and amplitude of the desired pulse-like shapes. The delay is controlled via the delay unit and the pre-shaped pulse's amplitudes are controlled by an analog adder unit. The overall system has 18 MOS transistors, one small capacitor, and one resistor. To verify the effectiveness of the recommended method, it is experienced on a real CMOS Op-Amp. HSPICE simulation results, on 0.25u technology, show a significant reduction on overshoot and settling time of the under-test Op-Amp. The mentioned reduction is more than 95% in overshoot and more than 60% in settling time of the system.

A 24GHz Radar Receiver in CMOS

NARCIS (Netherlands)

Kwok, K.C.

2015-01-01

This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

Advancing the technology of monolithic CMOS detectors for use as x-ray imaging spectrometers

Science.gov (United States)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Amato, Stephen

2017-08-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff has been engaged in a multi year effort to advance the technology of monolithic back-thinned CMOS detectors for use as X-ray imaging spectrometers. The long term goal of this campaign is to produce X-ray Active Pixel Sensor (APS) detectors with Fano limited performance over the 0.1-10keV band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Such devices would be ideal for candidate post 2020 decadal missions such as LYNX and for smaller more immediate applications such as CubeX. Devices from a recent fabrication have been back-thinned, packaged and tested for soft X-ray response. These devices have 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels with ˜135μV/electron sensitivity and a highly parallel signal chain. These new detectors are fabricated on 10μm epitaxial silicon and have a 1k by 1k format. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting X-ray astronomy. These features include read noise, X-ray spectral response and quantum efficiency.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

Science.gov (United States)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

NARCIS (Netherlands)

Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

Directory of Open Access Journals (Sweden)

Chris R. Bowen

2011-05-01

Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

CMOS COLOUR SENSOR BASED pH MEASUREMENT FOR WATER QUALITY ANALYSIS

OpenAIRE

Sanjay Kumar; Arvind Singh

2016-01-01

A Real-Time pH measurement system using a novel design Programmable CMOS optical Colour light to frequency converter TCS230 is presented. The system uses Bogen’s universal indicator solution combined with a white light source and the Programmable CMOS colour sensor TCS230 to measure pH as a function of colour change in a sample. Bogen’s universal indicator solution causes a colour change in a sample according to the pH of the sample. The output frequency from the colour-sensitive CM...

Recent progress in the development of 3D deep n-well CMOS MAPS

International Nuclear Information System (INIS)

Traversi, G; Manghisoni, M; Re, V; Gaioni, L; Manazza, A; Ratti, L; Zucca, S

2012-01-01

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel.

Science.gov (United States)

Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

2014-11-01

A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments.

Deformation of confined poly(ethylene oxide) in multilayer films.

Science.gov (United States)

Lai, Chuan-Yar; Hiltner, Anne; Baer, Eric; Korley, LaShanda T J

2012-04-01

The effect of confinement on the deformation behavior of poly(ethylene oxide) (PEO) was studied using melt processed coextruded poly(ethylene-co-acrylic acid) (EAA) and PEO multilayer films with varying PEO layer thicknesses from 3600 to 25 nm. The deformation mechanism was found to shift as layer thickness was decreased between 510 and 125 nm, from typical axial alignment of the crystalline fraction, as seen in bulk materials, to nonuniform micronecking mechanisms found in solution-grown single crystals. This change was evaluated via tensile testing, wide-angle X-ray diffraction (WAXD), atomic force microscopy (AFM), and differential scanning calorimetry (DSC). With the commercially relevant method of melt coextrusion, we were able to overcome the limitations to the testing of solution-grown single crystals, and the artifacts that occur from their handling, and bridged the gap in knowledge between thick bulk materials and thin single crystals.

High-temperature complementary metal oxide semiconductors (CMOS)

International Nuclear Information System (INIS)

McBrayer, J.D.

1979-10-01

Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

A CMOS four-quadrant analog current multiplier

NARCIS (Netherlands)

Wiegerink, Remco J.

1991-01-01

A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

Science.gov (United States)

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

International Nuclear Information System (INIS)

Li Chen; Liao Huailin; Huang Ru; Wang Yangyuan

2008-01-01

In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications. (cross-disciplinary physics and related areas of science and technology)

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

Science.gov (United States)

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

Gamma and Proton-Induced Dark Current Degradation of 5T CMOS Pinned Photodiode 0.18 mu{m} CMOS Image Sensors

Science.gov (United States)

Martin, E.; Nuns, T.; David, J.-P.; Gilard, O.; Vaillant, J.; Fereyre, P.; Prevost, V.; Boutillier, M.

2014-02-01

The radiation tolerance of a 0.18 μm technology CMOS commercial image sensor has been evaluated with Co60 and proton irradiations. The effects of protons on the hot pixels and dynamic bias and duty cycle conditions during gamma irradiations are studied.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

Science.gov (United States)

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Prediction of Poly(A Sites by Poly(A Read Mapping.

Directory of Open Access Journals (Sweden)

Thomas Bonfert

Full Text Available RNA-seq reads containing part of the poly(A tail of transcripts (denoted as poly(A reads provide the most direct evidence for the position of poly(A sites in the genome. However, due to reduced coverage of poly(A tails by reads, poly(A reads are not routinely identified during RNA-seq mapping. Nevertheless, recent studies for several herpesviruses successfully employed mapping of poly(A reads to identify herpesvirus poly(A sites using different strategies and customized programs. To more easily allow such analyses without requiring additional programs, we integrated poly(A read mapping and prediction of poly(A sites into our RNA-seq mapping program ContextMap 2. The implemented approach essentially generalizes previously used poly(A read mapping approaches and combines them with the context-based approach of ContextMap 2 to take into account information provided by other reads aligned to the same location. Poly(A read mapping using ContextMap 2 was evaluated on real-life data from the ENCODE project and compared against a competing approach based on transcriptome assembly (KLEAT. This showed high positive predictive value for our approach, evidenced also by the presence of poly(A signals, and considerably lower runtime than KLEAT. Although sensitivity is low for both methods, we show that this is in part due to a high extent of spurious results in the gold standard set derived from RNA-PET data. Sensitivity improves for poly(A sites of known transcripts or determined with a more specific poly(A sequencing protocol and increases with read coverage on transcript ends. Finally, we illustrate the usefulness of the approach in a high read coverage scenario by a re-analysis of published data for herpes simplex virus 1. Thus, with current trends towards increasing sequencing depth and read length, poly(A read mapping will prove to be increasingly useful and can now be performed automatically during RNA-seq mapping with ContextMap 2.

SiGe BiCMOS manufacturing platform for mmWave applications

Science.gov (United States)

Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

2010-10-01

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Chen Qu

2017-09-01

Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

CMOS digital integrated circuits a first course

CERN Document Server

Hawkins, Charles; Zarkesh-Ha, Payman

2016-01-01

This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process.

Science.gov (United States)

Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

2018-01-12

To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke - . Readout noise under the highest pixel gain condition is 1 e - with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7", 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach.

Overview of CMOS process and design options for image sensor dedicated to space applications

Science.gov (United States)

Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

2005-10-01

With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

Science.gov (United States)

Kenter, Almus

The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

International Nuclear Information System (INIS)

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-01-01

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12μm to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

TCAD simulations of High-Voltage-CMOS Pixel structures for the CLIC vertex detector

CERN Document Server

Buckland, Matthew Daniel

2016-01-01

The requirements for precision physics and the experimental conditions at CLIC result in stringent constraints for the vertex detector. Capacitively coupled active pixel sensors with 25 μm pitch implemented in a commercial 180 nm High-Voltage CMOS (HV-CMOS) process are currently under study as a candidate technology for the CLIC vertex detector. Laboratory calibration measurements and beam tests with prototypes are complemented by detailed TCAD and electronic circuit simulations, aiming for a comprehensive understanding of the signal formation in the HV-CMOS sensors and subsequent readout stages. In this note 2D and 3D TCAD simulation results of the prototype sensor, the Capacitively Coupled Pixel Detector version three (CCPDv3), will be presented. These include the electric field distribution, leakage current, well capacitance, transient response to minimum ionising particles and charge-collection.

Silicon CMOS architecture for a spin-based quantum computer.

Science.gov (United States)

Veldhorst, M; Eenink, H G J; Yang, C H; Dzurak, A S

2017-12-15

Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

Multiple-Event, Single-Photon Counting Imaging Sensor

Science.gov (United States)

Zheng, Xinyu; Cunningham, Thomas J.; Sun, Chao; Wang, Kang L.

2011-01-01

The single-photon counting imaging sensor is typically an array of silicon Geiger-mode avalanche photodiodes that are monolithically integrated with CMOS (complementary metal oxide semiconductor) readout, signal processing, and addressing circuits located in each pixel and the peripheral area of the chip. The major problem is its single-event method for photon count number registration. A single-event single-photon counting imaging array only allows registration of up to one photon count in each of its pixels during a frame time, i.e., the interval between two successive pixel reset operations. Since the frame time can t be too short, this will lead to very low dynamic range and make the sensor merely useful for very low flux environments. The second problem of the prior technique is a limited fill factor resulting from consumption of chip area by the monolithically integrated CMOS readout in pixels. The resulting low photon collection efficiency will substantially ruin any benefit gained from the very sensitive single-photon counting detection. The single-photon counting imaging sensor developed in this work has a novel multiple-event architecture, which allows each of its pixels to register as more than one million (or more) photon-counting events during a frame time. Because of a consequently boosted dynamic range, the imaging array of the invention is capable of performing single-photon counting under ultra-low light through high-flux environments. On the other hand, since the multiple-event architecture is implemented in a hybrid structure, back-illumination and close-to-unity fill factor can be realized, and maximized quantum efficiency can also be achieved in the detector array.

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

Science.gov (United States)

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY

Directory of Open Access Journals (Sweden)

N. B. ROMLI

2015-03-01

Full Text Available Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques.

Tacticities study of high poly-α-olefins, from poly-1-hexene to poly-1-octadecene, obtained with metallocenes catalysts

International Nuclear Information System (INIS)

Silva, Luciano F. da; Galland, Griselda B.

2003-01-01

High poly-α-olefins such as poly-1-hexene, poly-1-octene, poly-1-decene, poly-1-dodecene, poly-1-tetradecene, poly-1-hexadecene and poly-1-octadecene were obtained with the homogeneous iso specific catalyst rac-Et[Ind]ZrCl 2 /MAO and with the homogeneous syndiospecific catalyst Me 2 C[Cp(9-Flu)]ZrCl 2 /MAO at the polymerization temperatures of 0 deg C, 30 deg C and 60 deg C. The polymers were analyzed by 13 C NMR to study the influence of the α - olefins sizes, the catalysts type and the polymerization temperatures in their tacticities. The stereospecific control of both catalytic systems decreased with the increase of the reaction temperature and with the α-olefin size. (author)

CMOS Analog IC Design: Fundamentals

OpenAIRE

Bruun, Erik

2018-01-01

This book is intended for use as the main textbook for an introductory course in CMOS analog integrated circuit design. It is aimed at electronics engineering students who have followed basic courses in mathematics, physics, circuit theory, electronics and signal processing. It takes the students directly from a basic level to a level where they can start working on simple analog IC design projects or continue their studies using more advanced textbooks in the field. A distinct feature of thi...

Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

Directory of Open Access Journals (Sweden)

Yasuhisa Omura

2014-01-01

Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

Single molecule studies of solvent-dependent diffusion and entrapment in poly(dimethylsiloxane) thin films.

Science.gov (United States)

Lange, Jeffrey J; Culbertson, Christopher T; Higgins, Daniel A

2008-12-15

Single molecule microscopic and spectroscopic methods are employed to probe the mobility and physical entrapment of dye molecules in dry and solvent-loaded poly(dimethylsiloxane) (PDMS) films. PDMS films of approximately 220 nm thickness are prepared by spin casting dilute solutions of Sylgard 184 onto glass coverslips, followed by low temperature curing. A perylene diimide dye (BPPDI) is used to probe diffusion and molecule-matrix interactions. Two classes of dye-loaded samples are investigated: (i) those incorporating dye dispersed throughout the films ("in film" samples) and (ii) those in which the dye is restricted primarily to the PDMS surface ("on film" samples). Experiments are performed under dry nitrogen and at various levels of isopropyl alcohol (IPA) loading from the vapor phase. A PDMS-coated quartz-crystal microbalance is employed to monitor solvent loading and drying of the PDMS and to ensure equilibrium conditions are achieved. Single molecules are shown to be predominantly immobile under dry conditions and mostly mobile under IPA-saturated conditions. Quantitative methods for counting the fluorescent spots produced by immobile single molecules in optical images of the samples demonstrate that the population of mobile molecules increases nonlinearly with IPA loading. Even under IPA saturated conditions, the population of fixed molecules is found to be greater than zero and is greatest for "in film" samples. Fluorescence correlation spectroscopy is used to measure the apparent diffusion coefficient for the mobile molecules, yielding a mean value of D = 1.4(+/-0.4) x 10(-8) cm(2)/s that is virtually independent of IPA loading and sample class. It is concluded that a nonzero population of dye molecules is physically entrapped within the PDMS matrix under all conditions. The increase in the population of mobile molecules under high IPA conditions is attributed to the filling of film micropores with solvent, rather than by incorporation of molecularly

A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector

NARCIS (Netherlands)

Chen, Y.; Wang, X.; Mierop, A.J.; Theuwissen, A.J.P.

2009-01-01

This paper presents a CMOS imager sensor with pinned-photodiode 4T active pixels which use in-pixel buried-channel source followers (SFs) and optimized row selectors. The test sensor has been fabricated in a 0.18-mum CMOS process. The sensor characterization was carried out successfully, and the

A CMOS ASIC Design for SiPM Arrays.

Science.gov (United States)

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2011-12-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

Detection of mutations using microarrays of poly(C)10-poly(T)10 modified DNA probes immobilized on agarose films

DEFF Research Database (Denmark)

Dufva, Hans Martin; Petersen, Jesper; Stoltenborg, M.

2006-01-01

Allele-specific hybridization to a DNA microarray call be a useful method for genotyping patient DNA. In this article, we demonstrate that 13- to 17-base oligonucleotides tagged with a poly(T)10-poly(C)10 tail (TC tag), but otherwise unmodified, can be crosslinked by UV light irradiation to an ag......Allele-specific hybridization to a DNA microarray call be a useful method for genotyping patient DNA. In this article, we demonstrate that 13- to 17-base oligonucleotides tagged with a poly(T)10-poly(C)10 tail (TC tag), but otherwise unmodified, can be crosslinked by UV light irradiation...... to an agarose film grafted onto unmodified glass. Microarrays of TC-tagged probes immobilized on the agarose film can be used to diagnose Mutations in the human P-globin gene, which encodes the beta-chains in hemoglobin. Although the probes differed widely regarding inciting point temperature (similar to 20...... degrees C), a single stringency wash still gave sufficiently high discrimination signals between perfect match and mismatch probes to allow robust mutation detection. In all, 270 genotypings were performed on patient materials, and no genotype was incorrectly classified. Quality control experiments...

Simulation of SEU transients in CMOS ICs

International Nuclear Information System (INIS)

Kaul, N.; Bhuva, B.L.; Kerns, S.E.

1991-01-01

This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE

5-Gb/s 0.18-{mu}m CMOS 2:1 multiplexer with integrated clock extraction

Energy Technology Data Exchange (ETDEWEB)

Zhang Changchun; Wang Zhigong; Shi Si; Miao Peng [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China); Tian Ling, E-mail: zgwang@seu.edu.c [School of Science and Engineering, Southeast University, Nanjing 210096 (China)

2009-09-15

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 {mu}m CMOS technology. The chip area is 670 x 780 {mu}m{sup 2}. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

International Nuclear Information System (INIS)

Zhang Changchun; Wang Zhigong; Shi Si; Miao Peng; Tian Ling

2009-01-01

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 x 780 μm 2 . At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

Science.gov (United States)

Changchun, Zhang; Zhigong, Wang; Si, Shi; Peng, Miao; Ling, Tian

2009-09-01

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

Latch-up control in CMOS integrated circuits

International Nuclear Information System (INIS)

Ochoa, A.; Dawes, W.; Estreich, D.; Packard, H.

1979-01-01

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs

A new CMOS Hall angular position sensor

Energy Technology Data Exchange (ETDEWEB)

Popovic, R.S.; Drljaca, P. [Swiss Federal Inst. of Tech., Lausanne (Switzerland); Schott, C.; Racz, R. [SENTRON AG, Zug (Switzerland)

2001-06-01

The new angular position sensor consists of a combination of a permanent magnet attached to a shaft and of a two-axis magnetic sensor. The permanent magnet produces a magnetic field parallel with the magnetic sensor plane. As the shaft rotates, the magnetic field also rotates. The magnetic sensor is an integrated combination of a CMOS Hall integrated circuit and a thin ferromagnetic disk. The CMOS part of the system contains two or more conventional Hall devices positioned under the periphery of the disk. The ferromagnetic disk converts locally a magnetic field parallel with the chip surface into a field perpendicular to the chip surface. Therefore, a conventional Hall element can detect an external magnetic field parallel with the chip surface. As the direction of the external magnetic field rotates in the chip plane, the output voltage of the Hall element varies as the cosine of the rotation angle. By placing the Hall elements at the appropriate places under the disk periphery, we may obtain the cosine signals shifted by 90 , 120 , or by any other angle. (orig.)

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

Science.gov (United States)

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

Science.gov (United States)

Roever, Stefan

2012-01-01

A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

Poly-ADP-ribosylation of proteins responds to cellular perturbations

International Nuclear Information System (INIS)

Schneeweiss, F.H.A.; Sharan, R.N.

1999-01-01

From the results presented above it is quite obvious that poly-ADP-ribosylation reaction is a sensitive parameter to monitor cellular responses to a wide variety of perturbations. Having developed a monolayer assay system using 32 P-NAD + as a marker, it has become possible to measure levels of cellular ADP-ribosylation more precisely. It has been demonstrated that the trigger of poly-ADP-ribosylation reaction may involve different cellular components for different perturbations. In this, membrane has been found to be important. The study has been particularly informative in the realm of DNA damage and repair following qualitatively different radiation assaults. As poly-ADP-ribosylation in eukaryotic cells primarily affects chromosomal proteins, notably histones, the reaction is strongly triggered in response to single and double strand breaks in DNA. Therefore, level of cellular poly-ADP-ribosylation can potentially be used as a biosensor of radiation induced strand breaks and can be specially useful in clinical monitoring of progress of radiotherapy. The assay of poly-ADP-ribosylation, however, requires use of radiolabelled tracer, e.g. 32 P-NAD + . Due to this, study of poly-ADP-ribosylation can not be extended to monitor effects of incorporated radionuclides. In order to overcome this shortcoming and to make the assay more sensitive and quick, a Western blot immunoassay has been developed. The preliminary indications are that the immunoassay of poly-ADP-ribosylation will fulfil the requirements to use poly-ADP-ribosylation as a sensitive, convenient and clinically applicable biosensor of cell response not only to radiations but also to different perturbations. (orig.)

Optimization of CMOS active pixels for high resolution digital radiography

International Nuclear Information System (INIS)

Kim, Young Soo

2007-02-01

CMOS image sensors have poorer performance compared to conventional charge coupled devices (CCDs). Since CMOS Active Pixel Sensors (APSs) in general have higher temporal noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range and superior signal-to-noise ratio as CCDs. In view of electronic noise, the main source for the CMOS APS is the pixel, along with other signal processing blocks such as row and column decoder, analog signal processor (ASP), analog-to-digital converter (ADC), and timing and control logic circuitry. Therefore, it is important and necessary to characterize noise of the active pixels in CMOS APSs. We developed our theoretical noise model to account for the temporal noise in active pixels, and then found out the optimum design parameters such as fill actor, each size of the three transistors (source follower, row selection transistor, bias transistor) comprising active pixels, bias current, and load capacitance that can have the maximum signal-to-noise ratio. To develop the theoretical noise model in active pixels, we considered the integration noise of the photodiode and the readout noise of the transistors related to readout. During integration, the shot noise due to the dark current and photocurrent, during readout, the thermal and flicker noise were considered. The developed model can take the input variables such as photocurrent, capacitance of the photodiode, integration time, transconductance of the transistors, channel resistance of the transistors, gate-to-source capacitance of the follower, and load capacitance etc. To validate our noise model, two types of test structures have been realized. Firstly, four types of photodiodes (n_d_i_f_f_u_s_i_o_n/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_s_u_b_s_t_r_a_t_e, n_d_i_f_f_u_s_i_o_n/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e) used in CMOS active pixels were fabricated

A CMOS integrated pulse mode alpha-particle counter for application in radon monitoring

International Nuclear Information System (INIS)

Ahmed, A.; Walkey, D.J.; Tarr, N.G.

1997-01-01

A custom integrated circuit for detecting alpha particles for application in the monitoring of radon has been designed and tested. The design uses the reverse-biased well to a substrate capacitance of a p-n junction in a conventional CMOS process as a sense capacitor for incident alpha particles. A simple CMOS inverter is used as an analog amplifier to detect the small potential change induced by an alpha-particle strike on the sense capacitor. The design was implemented in a 1.2-microm conventional CMOS process with a sense capacitor area of 110 microm 2 . Tests carried out under vacuum conditions using a calibrated 241 Am alpha-particle source showed an output voltage swing of ≥2.0 V for an alpha event. The detector is also shown to have good immunity to noise and high-quantum efficiency for alpha particles

Thermal-Diffusivity-Based Frequency References in Standard CMOS

NARCIS (Netherlands)

Kashmiri, S.M.

2012-01-01

In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

Probing the Kinetic Anabolism of Poly-Beta-Hydroxybutyrate in Cupriavidus necator H16 Using Single-Cell Raman Spectroscopy

Directory of Open Access Journals (Sweden)

Zhanhua Tao

2016-08-01

Full Text Available Poly-beta-hydroxybutyrate (PHB can be formed in large amounts in Cupriavidus necator and is important for the industrial production of biodegradable plastics. In this investigation, laser tweezers Raman spectroscopy (LTRS was used to characterize dynamic changes in PHB content—as well as in the contents of other common biomolecule—in C. necator during batch growth at both the population and single-cell levels. PHB accumulation began in the early stages of bacterial growth, and the maximum PHB production rate occurred in the early and middle exponential phases. The active biosynthesis of DNA, RNA, and proteins occurred in the lag and early exponential phases, whereas the levels of these molecules decreased continuously during the remaining fermentation process until the minimum values were reached. The PHB content inside single cells was relatively homogenous in the middle stage of fermentation; during the late growth stage, the variation in PHB levels between cells increased. In addition, bacterial cells in various growth phases could be clearly discriminated when principle component analysis was performed on the spectral data. These results suggest that LTRS is a valuable single-cell analysis tool that can provide more comprehensive information about the physiological state of a growing microbial population.

Preparation, Characterization and Permeation Behavior of Poly(methyl acrylate-Poly(dimethyl siloxane-Poly(methyl acrylate Block Copolymer/Poly(vinyl acetate Blend Membranes

Directory of Open Access Journals (Sweden)

Mohammad Ali Semsarzadeh

2015-03-01

Full Text Available Structure of polymeric materials is of the most important factors in determination of the characteristics and properties of the membranes. Various research and developments on polymeric membranes confirm the direct correlation between structure-properties of polymeric membranes. In this research, the structural outcome of poly(methyl acrylate-poly(dimethyl siloxane-poly(methyl acrylate/poly(vinyl acetate blend membranes and its relationship with gas permeation behavior of the blends were investigated. The flexible block copolymer of poly(methyl acrylate-poly(dimethyl siloxane-poly(methyl acrylate (PMA-PDMS-PMA was synthesized via atom transfer radical polymerization. Morphology and chemical structure of the synthesized block copolymer was investigated by Fourier transform infrared spectroscopy, proton nuclear magnetic resonance, gel permeation chromatography, X-ray diffraction analysis, differential scanning calorimetry and scanning electron microscopy. Blend membranes of PMA-PDMS-PMA and poly(vinyl acetate (PVAc were prepared by solution casting method in different compositions. By adding poly(vinyl acetate to PMA-PDMS-PMA block copolymer, the selectivity of the membranes for carbon dioxide/methane pair gases were increased by 55%. Fractional free volume (an indication of chain packing efficiency in blend membranes and dielectric constant (an indication of the molar volume and molar polarization of the blend membranes were obtained as the factors reflected the microstructural effect of PMA-PDMS-PMA and PVAc blend membranes. The efforts were directed toward expressing more precise structure-properties relationship of PMA-PDMS-PMA/PVAc blend membranes. The experimental permeability values of the blend membranes reported in this research were compared with the modified logarithmic model. The modified logarithmic model was evaluated for other blend membranes.

Integrated X-ray and charged particle active pixel CMOS sensor arrays using an epitaxial silicon sensitive region

International Nuclear Information System (INIS)

Kleinfelder, Stuart; Bichsel, Hans; Bieser, Fred; Matis, Howard S.; Rai, Gulshan; Retiere, Fabrice; Weiman, Howard; Yamamoto, Eugene

2002-01-01

Integrated CMOS Active Pixel Sensor (APS) arrays have been fabricated and tested using X-ray and electron sources. The 128 by 128 pixel arrays, designed in a standard 0.25 micron process, use a ∼10 micron epitaxial silicon layer as a deep detection region. The epitaxial layer has a much greater thickness than the surface features used by standard CMOS APS, leading to stronger signals and potentially better signal-to-noise ratio (SNR). On the other hand, minority carriers confined within the epitaxial region may diffuse to neighboring pixels, blur images and reduce peak signal intensity. But for low-rate, sparse-event images, centroid analysis of this diffusion may be used to increase position resolution. Careful trade-offs involving pixel size and sense-node area verses capacitance must be made to optimize overall performance. The prototype sensor arrays, therefore, include a range of different pixel designs, including different APS circuits and a range of different epitaxial layer contact structures. The fabricated arrays were tested with 1.5 GeV electrons and Fe-55 X-ray sources, yielding a measured noise of 13 electrons RMS and an SNR for single Fe-55 X-rays of greater than 38

Application of CMOS charge-sensitive preamplifier in triple-GEM detector

International Nuclear Information System (INIS)

Lai Yongfang; Li Jin; Chinese Academy of Sciences, Beijing; Deng Zhi; Li Yulan; Liu Yinong; Li Yuanjing

2006-01-01

Among the various micro-pattern gas detectors (MPGD) that are available, the gas electron multiplier (GEM) detector is an attractive gas detector that has been used in particle physics experiments. However the GEM detector usually needs thousands of preamplifier units for its large number of micro-pattern readout strips or pads, which leads to considerable difficulties and complexities for front end electronics (FEE). Nowadays, by making use of complementary metal-oxide semiconductor (CMOS)-based application specific integrated circuit (ASIC), it is feasible to integrate hundreds of preamplifier units and other signal process circuits in a small-sized chip, which can be bound to the readout strips or pads of a micro-pattern particle detector (MPPD). Therefore, CMOS ASIC may provide an ideal solution to the readout problem of MPPD. In this article, a triple GEM detector is constructed and one of its readout strips is connected to a CMOS charge-sensitive preamplifier chip. The chip was exposed to an 55 Fe source of 5.9 kev X-ray, and the amplitude spectrum of the chip was tested, and it was found that the energy resolution was approximately 27%, which indicates that the chip can be used in triple GEM detectors. (authors)

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

Science.gov (United States)

2015-12-24

manufacturing today (namely, the 14nm FinFET silicon CMOS technology). The JPEG algorithm is selected as a motivational example since it is widely...TIFF images of a U.S. Air Force F-16 aircraft provided by the University of Southern California Signal and Image Processing Institute (SIPI) image...silicon CMOS technology currently in high volume manufac- turing today (the 14 nm FinFET silicon CMOS technology). The main contribution of this

Temperature Sensors Integrated into a CMOS Image Sensor