Transistors using crystalline silicon devices on glass

Science.gov (United States)

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Crystalline Silicon Interconnected Strips (XIS). Introduction to a New, Integrated Device and Module Concept

Energy Technology Data Exchange (ETDEWEB)

Van Roosmalen, J.; Bronsveld, P.; Mewe, A.; Janssen, G.; Stodolny, M.; Cobussen-Pool, E.; Bennett, I.; Weeber, A.; Geerligs, B. [ECN Solar Energy, P.O. Box 1, NL-1755 ZG, Petten (Netherlands)

2012-06-15

A new device concept for high efficiency, low cost, wafer based silicon solar cells is introduced. To significantly lower the costs of Si photovoltaics, high efficiencies and large reductions of metals and silicon costs are required. To enable this, the device architecture was adapted into low current devices by applying thin silicon strips, to which a special high efficiency back-contact heterojunction cell design was applied. Standard industrial production processes can be used for our fully integrated cell and module design, with a cost reduction potential below 0.5 euro/Wp. First devices have been realized demonstrating the principle of a series connected back contact hybrid silicon heterojunction module concept.

Simulation of atomistic processes during silicon oxidation

OpenAIRE

Bongiorno, Angelo

2003-01-01

Silicon dioxide (SiO2) films grown on silicon monocrystal (Si) substrates form the gate oxides in current Si-based microelectronics devices. The understanding at the atomic scale of both the silicon oxidation process and the properties of the Si(100)-SiO2 interface is of significant importance in state-of-the-art silicon microelectronics manufacturing. These two topics are intimately coupled and are both addressed in this theoretical investigation mainly through first-principles calculations....

Al transmon qubits on silicon-on-insulator for quantum device integration

Science.gov (United States)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Silicon integrated circuits advances in materials and device research

CERN Document Server

Kahng, Dawon

1981-01-01

Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

From silicon to organic nanoparticle memory devices.

Science.gov (United States)

Tsoukalas, D

2009-10-28

After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

Strain-Induced Spin-Resonance Shifts in Silicon Devices

Science.gov (United States)

Pla, J. J.; Bienfait, A.; Pica, G.; Mansir, J.; Mohiyaddin, F. A.; Zeng, Z.; Niquet, Y. M.; Morello, A.; Schenkel, T.; Morton, J. J. L.; Bertet, P.

2018-04-01

In spin-based quantum-information-processing devices, the presence of control and detection circuitry can change the local environment of a spin by introducing strain and electric fields, altering its resonant frequencies. These resonance shifts can be large compared to intrinsic spin linewidths, and it is therefore important to study, understand, and model such effects in order to better predict device performance. We investigate a sample of bismuth donor spins implanted in a silicon chip, on top of which a superconducting aluminum microresonator is fabricated. The on-chip resonator provides two functions: it produces local strain in the silicon due to the larger thermal contraction of the aluminum, and it enables sensitive electron spin-resonance spectroscopy of donors close to the surface that experience this strain. Through finite-element strain simulations, we are able to reconstruct key features of our experiments, including the electron spin-resonance spectra. Our results are consistent with a recently observed mechanism for producing shifts of the hyperfine interaction for donors in silicon, which is linear with the hydrostatic component of an applied strain.

Single-Event Effects in Silicon Carbide Power Devices

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2015-01-01

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

Magneto-optical non-reciprocal devices in silicon photonics

Directory of Open Access Journals (Sweden)

Yuya Shoji

2014-01-01

Full Text Available Silicon waveguide optical non-reciprocal devices based on the magneto-optical effect are reviewed. The non-reciprocal phase shift caused by the first-order magneto-optical effect is effective in realizing optical non-reciprocal devices in silicon waveguide platforms. In a silicon-on-insulator waveguide, the low refractive index of the buried oxide layer enhances the magneto-optical phase shift, which reduces the device footprints. A surface activated direct bonding technique was developed to integrate a magneto-optical garnet crystal on the silicon waveguides. A silicon waveguide optical isolator based on the magneto-optical phase shift was demonstrated with an optical isolation of 30 dB and insertion loss of 13 dB at a wavelength of 1548 nm. Furthermore, a four port optical circulator was demonstrated with maximum isolations of 15.3 and 9.3 dB in cross and bar ports, respectively, at a wavelength of 1531 nm.

Surface wave photonic device based on porous silicon multilayers

International Nuclear Information System (INIS)

Guillermain, E.; Lysenko, V.; Benyattou, T.

2006-01-01

Porous silicon is widely studied in the field of photonics due to its interesting optical properties. In this work, we present theoretical and first experimental studies of a new kind of porous silicon photonic device based on optical surface wave. A theoretical analysis of the device is presented using plane-wave approximation. The porous silicon multilayered structures are realized using electrochemical etching of p + -type silicon. Morphological and optical characterizations of the realized structures are reported

Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

International Nuclear Information System (INIS)

Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

2013-01-01

Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

Solid state MEMS devices on flexible and semi-transparent silicon (100) platform

KAUST Repository

Ahmed, Sally; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2014-01-01

We report fabrication of MEMS thermal actuators on flexible and semi-transparent silicon fabric released from bulk silicon (100). We fabricated the devices first and then released the top portion of the silicon (≈ 19 μm) which is flexible and semi-transparent. We also performed chemical mechanical polishing to reuse the remaining wafer. A tested thermal actuator with 3 μm wide 240 μm hot arm and 10 μm wide 185 μm long cold arm deflected by 1.7 μm at 1 V. The fabricated thermal actuators exhibit similar performance before and after bending. We believe the demonstrated process will expand the horizon of flexible electronics into MEMS world devices. © 2014 IEEE.

Silicon spintronics with ferromagnetic tunnel devices

International Nuclear Information System (INIS)

Jansen, R; Sharma, S; Dash, S P; Min, B C

2012-01-01

In silicon spintronics, the unique qualities of ferromagnetic materials are combined with those of silicon, aiming at creating an alternative, energy-efficient information technology in which digital data are represented by the orientation of the electron spin. Here we review the cornerstones of silicon spintronics, namely the creation, detection and manipulation of spin polarization in silicon. Ferromagnetic tunnel contacts are the key elements and provide a robust and viable approach to induce and probe spins in silicon, at room temperature. We describe the basic physics of spin tunneling into silicon, the spin-transport devices, the materials aspects and engineering of the magnetic tunnel contacts, and discuss important quantities such as the magnitude of the spin accumulation and the spin lifetime in the silicon. We highlight key experimental achievements and recent progress in the development of a spin-based information technology. (topical review)

Fifth workshop on the role of impurities and defects in silicon device processing. Extended abstracts

Energy Technology Data Exchange (ETDEWEB)

Sopori, B.L.; Luque, A.; Sopori, B.; Swanson, D.; Gee, J.; Kalejs, J.; Jastrzebski, L.; Tan, T.

1995-08-01

This workshop dealt with engineering aspects and material properties of silicon electronic devices. Crystalline silicon growth, modeling, and properties are discussed in general and as applied to solar cells. Topics considered in discussions of silicon growth include: casting, string ribbons, Al backside contacts, ion implantation, gettering, passivation, and ultrasound treatments. Properties studies include: Electronic properties of defects and impurities, dopant and carrier concentrations, structure and bonding, nitrogen effects, degradation of bulk diffusion length, and recombination parameters. Individual papers from the workshop are indexed separately on the Energy Data Bases.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

Science.gov (United States)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

2016-01-01

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Oxygen defect processes in silicon and silicon germanium

KAUST Repository

Chroneos, A.

2015-06-18

Silicon and silicon germanium are the archetypical elemental and alloy semiconductor materials for nanoelectronic, sensor, and photovoltaic applications. The investigation of radiation induced defects involving oxygen, carbon, and intrinsic defects is important for the improvement of devices as these defects can have a deleterious impact on the properties of silicon and silicon germanium. In the present review, we mainly focus on oxygen-related defects and the impact of isovalent doping on their properties in silicon and silicon germanium. The efficacy of the isovalent doping strategies to constrain the oxygen-related defects is discussed in view of recent infrared spectroscopy and density functional theory studies.

Oxygen defect processes in silicon and silicon germanium

KAUST Repository

Chroneos, A.; Sgourou, E. N.; Londos, C. A.; Schwingenschlö gl, Udo

2015-01-01

Silicon and silicon germanium are the archetypical elemental and alloy semiconductor materials for nanoelectronic, sensor, and photovoltaic applications. The investigation of radiation induced defects involving oxygen, carbon, and intrinsic defects is important for the improvement of devices as these defects can have a deleterious impact on the properties of silicon and silicon germanium. In the present review, we mainly focus on oxygen-related defects and the impact of isovalent doping on their properties in silicon and silicon germanium. The efficacy of the isovalent doping strategies to constrain the oxygen-related defects is discussed in view of recent infrared spectroscopy and density functional theory studies.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

Science.gov (United States)

Bisadi, Zahra; Acerbi, Fabio; Fontana, Giorgio; Zorzi, Nicola; Piemonte, Claudio; Pucker, Georg; Pavesi, Lorenzo

2018-02-01

A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED) coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST) suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Linear all-optical signal processing using silicon micro-ring resonators

DEFF Research Database (Denmark)

Ding, Yunhong; Ou, Haiyan; Xu, Jing

2016-01-01

Silicon micro-ring resonators (MRRs) are compact and versatile devices whose periodic frequency response can be exploited for a wide range of applications. In this paper, we review our recent work on linear all-optical signal processing applications using silicon MRRs as passive filters. We focus...

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

Directory of Open Access Journals (Sweden)

Zahra Bisadi

2018-02-01

Full Text Available A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Simple processing of high efficiency silicon solar cells

International Nuclear Information System (INIS)

Hamammu, I.M.; Ibrahim, K.

2006-01-01

Cost effective photovoltaic devices have been an area research since the development of the first solar cells, as cost is the major factor in their usage. Silicon solar cells have the biggest share in the photovoltaic market, though silicon os not the optimal material for solar cells. This work introduces a simplified approach for high efficiency silicon solar cell processing, by minimizing the processing steps and thereby reducing cost. The suggested procedure might also allow for the usage of lower quality materials compared to the one used today. The main features of the present work fall into: simplifying the diffusion process, edge shunt isolation and using acidic texturing instead of the standard alkaline processing. Solar cells of 17% efficiency have been produced using this procedure. Investigations on the possibility of improving the efficiency and using less quality material are still underway

A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

2007-07-25

A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

KAUST Repository

Rojas, Jhonathan Prieto

2013-01-07

Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

International Nuclear Information System (INIS)

Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

2002-01-01

Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

Electrical effects of transient neutron irradiation of silicon devices

International Nuclear Information System (INIS)

Hjalmarson, H.P.; Pease, R.L.; Van Ginhoven, R.M.; Schultz, P.A.; Modine, N.A.

2007-01-01

The key effects of combined transient neutron and ionizing radiation on silicon diodes and bipolar junctions transistors are described. The results show that interstitial defect reactions dominate the annealing effects in the first stage of annealing for certain devices. Furthermore, the results show that oxide trapped charge can influence the effects of bulk silicon displacement damage for particular devices

Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

International Nuclear Information System (INIS)

Holland, S.

1991-11-01

A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

Light Absorption Enhancement of Silicon-Based Photovoltaic Devices with Multiple Bandgap Structures of Porous Silicon

Directory of Open Access Journals (Sweden)

Kuen-Hsien Wu

2015-09-01

Full Text Available Porous-silicon (PS multi-layered structures with three stacked PS layers of different porosity were prepared on silicon (Si substrates by successively tuning the electrochemical-etching parameters in an anodization process. The three PS layers have different optical bandgap energy and construct a triple-layered PS (TLPS structure with multiple bandgap energy. Photovoltaic devices were fabricated by depositing aluminum electrodes of Schottky contacts on the surfaces of the developed TLPS structures. The TLPS-based devices exhibit broadband photoresponses within the spectrum of the solar irradiation and get high photocurrent for the incident light of a tungsten lamp. The improved spectral responses of devices are owing to the multi-bandgap structures of TLPS, which are designed with a layered configuration analog to a tandem cell for absorbing a wider energy range of the incidental sun light. The large photocurrent is mainly ascribed to an enhanced light-absorption ability as a result of applying nanoporous-Si thin films as the surface layers to absorb the short-wavelength light and to improve the Schottky contacts of devices. Experimental results reveal that the multi-bandgap PS structures produced from electrochemical-etching of Si wafers are potentially promising for development of highly efficient Si-based solar cells.

Neuron-inspired flexible memristive device on silicon (100)

KAUST Repository

Ghoneim, Mohamed T.

2017-06-18

Comprehensive understanding of the world\\'s most energy efficient powerful computer, the human brain, is an elusive scientific issue. Still, already gained knowledge indicates memristors can be used as a building block to model the brain. At the same time, brain cortex is folded allowing trillions of neurons to be integrated in a compact volume. Therefore, we report flexible aluminium oxide based memristive devices fabricated and then derived from widely used bulk mono-crystalline silicon (100). We use complementary metal oxide semiconductor based processes to layout the foundation for ultra large scale integration (ULSI) of such memory devices to advance the task of comprehending a physical model of human brain.

Silicon Carbide Power Devices and Integrated Circuits

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan; Samsel, Isaak; LaBel, Ken; Chen, Yuan; Ikpe, Stanley; Wilcox, Ted; Phan, Anthony; Kim, Hak; Topper, Alyson

2017-01-01

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

Silicon Nanowires for All-Optical Signal Processing in Optical Communication

DEFF Research Database (Denmark)

Pu, Minhao; Hu, Hao; Ji, Hua

2012-01-01

Silicon (Si), the second most abundant element on earth, has dominated in microelectronics for many decades. It can also be used for photonic devices due to its transparency in the range of optical telecom wavelengths which will enable a platform for a monolithic integration of optics...... and microelectronics. Silicon photonic nanowire waveguides fabricated on silicon-on-insulator (SOI) substrates are crucial elements in nano-photonic integrated circuits. The strong light confinement in nanowires induced by high index contrast SOI material enhances the nonlinear effects in the silicon nanowire core...... such as four-wave mixing (FWM) which is an imperative process for optical signal processing. Since the current mature silicon fabrication technology enables a precise dimension control on nanowires, dispersion engineering can be performed by tailoring nanowire dimensions to realize an efficient nonlinear...

Device physics underlying silicon heterojunction and passivating-contact solar cells: A topical review

KAUST Repository

Chavali, Raghu V. K.

2018-01-15

The device physics of commercially dominant diffused-junction silicon solar cells is well understood, allowing sophisticated optimization of this class of devices. Recently, so-called passivating-contact solar cell technologies have become prominent, with Kaneka setting the world\\'s silicon solar cell efficiency record of 26.63% using silicon heterojunction contacts in an interdigitated configuration. Although passivating-contact solar cells are remarkably efficient, their underlying device physics is not yet completely understood, not in the least because they are constructed from diverse materials that may introduce electronic barriers in the current flow. To bridge this gap in understanding, we explore the device physics of passivating contact silicon heterojunction (SHJ) solar cells. Here, we identify the key properties of heterojunctions that affect cell efficiency, analyze the dependence of key heterojunction properties on carrier transport under light and dark conditions, provide a self-consistent multiprobe approach to extract heterojunction parameters using several characterization techniques (including dark J-V, light J-V, C-V, admittance spectroscopy, and Suns-Voc), propose design guidelines to address bottlenecks in energy production in SHJ cells, and develop a process-to-module modeling framework to establish the module\\'s performance limits. We expect that our proposed guidelines resulting from this multiscale and self-consistent framework will improve the performance of future SHJ cells as well as other passivating contact-based solar cells.

The design and investigation of hybrid ferromagnetic/silicon spin electronic devices

International Nuclear Information System (INIS)

Pugh, D.I.

2001-01-01

The focus of this study concerns the design and investigation of ferromagnetic/silicon hybrid spin electronic devices as part of a wider project to design a novel spin valve transistor. The key issue to obtain a room temperature spin electronic device is the electrical injection of a spin polarised current from a ferromagnetic contact into a semiconductor. Despite many attempts concentrating on GaAs and InAs only small (< 1%) effects have been observed, making it difficult to confirm spin injection. Lateral devices were designed and fabricated using standard device fabrication procedures to produce arrays of Co/Si/So junctions. Subsequent designs aimed to reduce the number of junctions and improve device isolation. Evidence for spin dependent MR of up to 0.56% was observed in Co/p-Si/Co junctions with silicon gaps up to 16 μm in length. The maximum MR was observed when the first Co/Si Schottky barrier was reverse biased forming a high resistance interface. Vertical devices were designed in an attempt to eliminate any alternative current paths by using a well defined, 1 μm thick silicon membrane. Despite attempts to include oxide barriers, no spin dependent MR was observed in these devices. However, a novel vertical silicon based design has been made which should facilitate further advanced studies of spin injection and transport. The spin diffusion length in n-type silicon has been calculated as a function of doping concentration and temperature by considering the spin relaxation mechanisms in the semiconductor. Discussion has been made concerning p-type silicon and comparisons made with GaAs, indicating that n-Si should show longer spin diffusion lengths. The key design criteria for designing room temperature spin electronic devices have been highlighted. These include the use of a high leakage Schottky barrier or tunnel barrier between the ferromagnet and p-Si and a contact to the silicon to enable appropriate biasing to each FM/Si interface. (author)

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids

International Nuclear Information System (INIS)

Strobel, Sebastian; Hernandez, Rocio Murcia; Hansen, Allan G; Tornow, Marc

2008-01-01

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10 -18 farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian; Hernandez, Rocio Murcia [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall 3, 85748 Garching (Germany); Hansen, Allan G; Tornow, Marc [Institut fuer Halbleitertechnik, Technische Universitaet Braunschweig, Hans-Sommer-Strasse 66, 38106 Braunschweig (Germany)], E-mail: m.tornow@tu-bs.de

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10{sup -18} farad and asymmetric resistances of 30 and 300 M{omega}, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids.

Science.gov (United States)

Strobel, Sebastian; Hernández, Rocío Murcia; Hansen, Allan G; Tornow, Marc

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10(-18) farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

Porous siliconformation and etching process for use in silicon micromachining

Science.gov (United States)

Guilinger, Terry R.; Kelly, Michael J.; Martin, Jr., Samuel B.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

A reproducible process for uniformly etching silicon from a series of micromechanical structures used in electrical devices and the like includes providing a micromechanical structure having a silicon layer with defined areas for removal thereon and an electrochemical cell containing an aqueous hydrofluoric acid electrolyte. The micromechanical structure is submerged in the electrochemical cell and the defined areas of the silicon layer thereon are anodically biased by passing a current through the electrochemical cell for a time period sufficient to cause the defined areas of the silicon layer to become porous. The formation of the depth of the porous silicon is regulated by controlling the amount of current passing through the electrochemical cell. The micromechanical structure is then removed from the electrochemical cell and submerged in a hydroxide solution to remove the porous silicon. The process is subsequently repeated for each of the series of micromechanical structures to achieve a reproducibility better than 0.3%.

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

International Nuclear Information System (INIS)

Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

2005-01-01

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto

2014-02-25

In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

Silicon nano crystal-based non-volatile memory devices

International Nuclear Information System (INIS)

Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

2006-01-01

In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

Science.gov (United States)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Digital signal processor for silicon audio playback devices; Silicon audio saisei kikiyo digital signal processor

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)

Eighth Workshop on Crystalline Silicon Solar Cell Materials and Processes; Summary Discussion Sessions

International Nuclear Information System (INIS)

Sopori, B.; Swanson, D.; Sinton, R.; Stavola, M.; Tan, T.

1998-01-01

This report is a summary of the panel discussions included with the Eighth Workshop on Crystalline Silicon Solar Cell Materials and Processes. The theme of the workshop was ''Supporting the Transition to World Class Manufacturing.'' This workshop provided a forum for an informal exchange of information between researchers in the photovoltaic and nonphotovoltaic fields on various aspects of impurities and defects in silicon, their dynamics during device processing, and their application in defect engineering. This interaction helped establish a knowledge base that can be used for improving device-fabrication processes to enhance solar-cell performance and reduce cell costs. It also provided an excellent opportunity for researchers from industry and universities to recognize mutual needs for future joint research

Self-consistent modeling of amorphous silicon devices

International Nuclear Information System (INIS)

Hack, M.

1987-01-01

The authors developed a computer model to describe the steady-state behaviour of a range of amorphous silicon devices. It is based on the complete set of transport equations and takes into account the important role played by the continuous distribution of localized states in the mobility gap of amorphous silicon. Using one set of parameters they have been able to self-consistently simulate the current-voltage characteristics of p-i-n (or n-i-p) solar cells under illumination, the dark behaviour of field-effect transistors, p-i-n diodes and n-i-n diodes in both the ohmic and space charge limited regimes. This model also describes the steady-state photoconductivity of amorphous silicon, in particular, its dependence on temperature, doping and illumination intensity

Silicon web process development

Science.gov (United States)

Duncan, C. S.; Seidensticker, R. G.; Mchugh, J. P.; Skutch, M. E.; Driggers, J. M.; Hopkins, R. H.

1981-01-01

The silicon web process takes advantage of natural crystallographic stabilizing forces to grow long, thin single crystal ribbons directly from liquid silicon. The ribbon, or web, is formed by the solidification of a liquid film supported by surface tension between two silicon filaments, called dendrites, which border the edges of the growing strip. The ribbon can be propagated indefinitely by replenishing the liquid silicon as it is transformed to crystal. The dendritic web process has several advantages for achieving low cost, high efficiency solar cells. These advantages are discussed.

Commercial power silicon devices as possible routine dosimeters for radiation processing

International Nuclear Information System (INIS)

Fuochi, P.G.; Lavalle, M.; Gombia, E.; Mosca, R.; Kovacs, A.V.; Hargittai, P.; Vitanza, A.; Patti, A.

2001-01-01

The use of silicon devices as possible radiation dosimeters has been investigated in this study. A bipolar power transistor in TO126 plastic packaging has been selected. Irradiations, with doses in the range from 50 Gy up to 5 kGy, have been performed at room temperature using different radiation sources ( 60 Co g source, 2.5, 4 and 12 MeV electron accelerators). Few irradiations with g rays were also done at different temperatures. A physical parameter, T, related to the charge carrier lifetime, has been found to change as a function of irradiation dose. This change is radiation energy dependent. Long term stability of the electron irradiated transistors has been checked by means of a reliability test ('high temperature reverse bias', HTRB) at 150 deg. C for 1000 h. Deep level transient spectroscopy (DLTS) measurements have been performed on the irradiated devices to identify the recombination centres introduced by the radiation treatment. The results obtained confirm that these transistors could be used as routine radiation dosimeters in a certain dose range. More work needs to be done particularly with g rays in the low dose region (50-200 Gy) and with low energy electrons. (author)

Effects of radiation on MOS structures and silicon devices

International Nuclear Information System (INIS)

Braeunig, D.; Fahrner, W.

1983-02-01

A comprehensive view of radiation effects on MOS structures and silicon devices is given. In the introduction, the interaction of radiation with semiconductor material is presented. In the next section, the electrical degradation of semiconductor devices due to this interaction is discussed. The commonly used hardening techniques are shown. The last section deals with testing of radiation hardness of devices. (orig.) [de

Noise and degradation of amorphous silicon devices

NARCIS (Netherlands)

Bakker, J.P.R.

2003-01-01

Electrical noise measurements are reported on two devices of the disordered semiconductor hydrogenated amorphous silicon (a-Si:H). The material is applied in sandwich structures and in thin-film transistors (TFTs). In a sandwich configuration of an intrinsic layer and two thin doped layers, the

Comparison of Six Different Silicones In Vitro for Application as Glaucoma Drainage Device

Directory of Open Access Journals (Sweden)

Claudia Windhövel

2018-02-01

Full Text Available Silicones are widely used in medical applications. In ophthalmology, glaucoma drainage devices are utilized if conservative therapies are not applicable or have failed. Long-term success of these devices is limited by failure to control intraocular pressure due to fibrous encapsulation. Therefore, different medical approved silicones were tested in vitro for cell adhesion, cell proliferation and viability of human Sclera (hSF and human Tenon fibroblasts (hTF. The silicones were analysed also depending on the sample preparation according to the manufacturer’s instructions. The surface quality was characterized with environmental scanning electron microscope (ESEM and water contact angle measurements. All silicones showed homogeneous smooth and hydrophobic surfaces. Cell adhesion was significantly reduced on all silicones compared to the negative control. Proliferation index and cell viability were not influenced much. For development of a new glaucoma drainage device, the silicones Silbione LSR 4330 and Silbione LSR 4350, in this study, with low cell counts for hTF and low proliferation indices for hSF, and silicone Silastic MDX4-4210, with low cell counts for hSF and low proliferation indices for hTF, have shown the best results in vitro. Due to the high cell adhesion shown on Silicone LSR 40, 40,026, this material is unsuitable.

Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances

International Nuclear Information System (INIS)

Suat, J.P.; Borel, J.

1976-01-01

The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr

Surface morphology evolution in silicon during ion beam processing; TOPICAL

International Nuclear Information System (INIS)

Bedrossian P; Caturla, M; Diaz de la Rubia, T; Johnson, M

1999-01-01

The Semiconductor Industry Association (SIA) projects that the semiconductor chips used in personal computers and scientific workstations will reach five times the speed and ten times the memory capacity of the current pentium-class processor by the year 2007. However, 1 GHz on-chip clock speeds and 64 Gbits/Chip DRAM technology will not come easy and without a price. Such technologies will require scaling the minimum feature size of CMOS devices (the transistors in the silicon chip) down to below 100nm from the current 180 to 250 nm. This requirement has profound implications for device manufacturing. Existing processing techniques must increasingly be understood quantitatively and modeled with unprecedented precision. Indeed, revolutionary advances in the development of physics-based process simulation tools will be required to achieve the goals for cost efficient manufacturing, and to satisfy the needs of the defense industrial base. These advances will necessitate a fundamental improvement in our basic understanding of microstructure evolution during processing. In order to cut development time and costs, the semiconductor industry makes extensive use of simple models of dopant implantation, and of phenomenological models of defect annealing and diffusion. However, the production of a single device often requires more than 200 processing steps, and the cumulative effects of the various steps are far too complex to be treated with these models. The lack of accurate process modeling simulators is proving to be a serious impediment to the development of next generation devices. New atomic-level models are required to describe the point defect distributions produced by the implantation process, and the defect and dopant diffusion resulting from rapid thermal annealing steps. In this LDRD project, we investigated the migration kinetics of defects and dopants in silicon both experimentally and theoretically to provide a fundamental database for use in the development

HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

Science.gov (United States)

Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

2000-08-01

Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

Spike-Timing Dependent Plasticity in Unipolar Silicon Oxide RRAM Devices.

Science.gov (United States)

Zarudnyi, Konstantin; Mehonic, Adnan; Montesi, Luca; Buckwell, Mark; Hudziak, Stephen; Kenyon, Anthony J

2018-01-01

Resistance switching, or Resistive RAM (RRAM) devices show considerable potential for application in hardware spiking neural networks (neuro-inspired computing) by mimicking some of the behavior of biological synapses, and hence enabling non-von Neumann computer architectures. Spike-timing dependent plasticity (STDP) is one such behavior, and one example of several classes of plasticity that are being examined with the aim of finding suitable algorithms for application in many computing tasks such as coincidence detection, classification and image recognition. In previous work we have demonstrated that the neuromorphic capabilities of silicon-rich silicon oxide (SiO x ) resistance switching devices extend beyond plasticity to include thresholding, spiking, and integration. We previously demonstrated such behaviors in devices operated in the unipolar mode, opening up the question of whether we could add plasticity to the list of features exhibited by our devices. Here we demonstrate clear STDP in unipolar devices. Significantly, we show that the response of our devices is broadly similar to that of biological synapses. This work further reinforces the potential of simple two-terminal RRAM devices to mimic neuronal functionality in hardware spiking neural networks.

Silicon etch process

International Nuclear Information System (INIS)

Day, D.J.; White, J.C.

1984-01-01

A silicon etch process wherein an area of silicon crystal surface is passivated by radiation damage and non-planar structure produced by subsequent anisotropic etching. The surface may be passivated by exposure to an energetic particle flux - for example an ion beam from an arsenic, boron, phosphorus, silicon or hydrogen source, or an electron beam. Radiation damage may be used for pattern definition and/or as an etch stop. Ethylenediamine pyrocatechol or aqueous potassium hydroxide anisotropic etchants may be used. The radiation damage may be removed after etching by thermal annealing. (author)

Proton irradiation effects in silicon devices

Energy Technology Data Exchange (ETDEWEB)

Simoen, E; Vanhellemont, J; Alaerts, A [IMEC, Leuven (Belgium); and others

1997-03-01

Proton irradiation effects in silicon devices are studied for components fabricated in various substrates in order to reveal possible hardening effects. The degradation of p-n junction diodes increases in first order proportionally with the fluence, when submitted to 10 MeV proton irradiations in the range 5x10{sup 9} cm{sup -2} to 5x10{sup 11} cm{sup -2}. The damage coefficients for both p- and n-type Czochralski, Float-Zone and epitaxial wafers are reported. Charge-Coupled Devices fabricated in a 1.2 {mu}m CCD-CMOS technology are shown to be quite resistant to 59 MeV H{sup +} irradiations, irrespective of the substrate type. (author)

Silicon processing for photovoltaics II

CERN Document Server

Khattak, CP

2012-01-01

The processing of semiconductor silicon for manufacturing low cost photovoltaic products has been a field of increasing activity over the past decade and a number of papers have been published in the technical literature. This volume presents comprehensive, in-depth reviews on some of the key technologies developed for processing silicon for photovoltaic applications. It is complementary to Volume 5 in this series and together they provide the only collection of reviews in silicon photovoltaics available.The volume contains papers on: the effect of introducing grain boundaries in silicon; the

SILICON CARBIDE MICRO-DEVICES FOR COMBUSTION GAS SENSING UNDER HARSH CONDITIONS

Energy Technology Data Exchange (ETDEWEB)

Ruby N. Ghosh; Peter Tobias; Roger G. Tobin

2004-04-01

A sensor based on the wide bandgap semiconductor, silicon carbide (SiC), has been developed for the detection of combustion products in power plant environments. The sensor is a catalytic gate field effect device that can detect hydrogen containing species in chemically reactive, high temperature environments. Robust metallization and electrical contacting techniques have been developed for device operation at elevated temperatures. To characterize the time response of the sensor responses in the millisecond range, a conceptually new apparatus has been built. Software has been developed to cope with the requirements of fast sensor control and data recording. In addition user friendly software has been developed to facilitate use of the SiC sensors for industrial process control applications.

Athermal Photonic Devices and Circuits on a Silicon Platform

Science.gov (United States)

Raghunathan, Vivek

In recent years, silicon based optical interconnects has been pursued as an effective solution that can offer cost, energy, distance and bandwidth density improvements over copper. Monolithic integration of optics and electronics has been enabled by silicon photonic devices that can be fabricated using CMOS technology. However, high levels of device integration result in significant local and global temperature fluctuations that prove problematic for silicon based photonic devices. In particular, high temperature dependence of Si refractive index (thermo-optic (TO) coefficient) shifts the filter response of resonant devices that limit wavelength resolution in various applications. Active thermal compensation using heaters and thermo-electric coolers are the legacy solution for low density integration. However, the required electrical power, device foot print and number of input/output (I/O) lines limit the integration density. We present a passive approach to an athermal design that involves compensation of positive TO effects from a silicon core by negative TO effects of the polymer cladding. In addition, the design rule involves engineering the waveguide core geometry depending on the resonance wavelength under consideration to ensure desired amount of light in the polymer. We develop exact design requirements for a TO peak stability of 0 pm/K and present prototype performance of 0.5 pm/K. We explore the material design space through initiated chemical vapor deposition (iCVD) of 2 polymer cladding choices. We study the effect of cross-linking on the optical properties of a polymer and establish the superior performance of the co-polymer cladding compared to the homo-polymer. Integration of polymer clad devices in an electronic-photonic architecture requires the possibility of multi-layer stacking capability. We use a low temperature, high density plasma chemical vapor deposition of SiO2/SiN x to hermetically seal the athermal. Further, we employ visible light for

The first results of siliconization on SWIP-RFP device

International Nuclear Information System (INIS)

Zhang Peng; Li Qiang; Luo Cuiwen; Li Jieping; Qian Shangjie; Fang Shuiquan; Yi Ping; Xue Jun; Li Kehua; Luo Junlin; Hong Wenyu; Cao Zeng; Zhang Nianman; Wang Quanming; Li Jie; Huang Ming; Zhong Yunze; Zhang Qingchun; Luo Cuixian

1997-01-01

The first results of reversed field pinch (RFP) and ultra low safety factor (ULQ) plasma experiments with siliconization on SWIP-RFP device are presented in this paper. The siliconization decreases the impurity concentrations in the plasma and increases the configuration sustainment time. Ion temperature has been estimated with the CV line of the visible light spectra and the broadening of CIII lines in vacuum ultraviolet (VUV) region. The anomalous ion heating as well as the anomalous resistance were observed. (orig.)

Simple processing of back-contacted silicon heterojunction solar cells using selective-area crystalline growth

KAUST Repository

Tomasi, Andrea; Paviet-Salomon, Bertrand; Jeangros, Quentin; Haschke, Jan; Christmann, Gabriel; Barraud, Loris; Descoeudres, Antoine; Seif, Johannes Peter; Nicolay, Sylvain; Despeisse, Matthieu; De Wolf, Stefaan; Ballif, Christophe

2017-01-01

For crystalline-silicon solar cells, voltages close to the theoretical limit are nowadays readily achievable when using passivating contacts. Conversely, maximal current generation requires the integration of the electron and hole contacts at the back of the solar cell to liberate its front from any shadowing loss. Recently, the world-record efficiency for crystalline-silicon single-junction solar cells was achieved by merging these two approaches in a single device; however, the complexity of fabricating this class of devices raises concerns about their commercial potential. Here we show a contacting method that substantially simplifies the architecture and fabrication of back-contacted silicon solar cells. We exploit the surface-dependent growth of silicon thin films, deposited by plasma processes, to eliminate the patterning of one of the doped carrier-collecting layers. Then, using only one alignment step for electrode definition, we fabricate a proof-of-concept 9-cm2 tunnel-interdigitated back-contact solar cell with a certified conversion efficiency >22.5%.

Simple processing of back-contacted silicon heterojunction solar cells using selective-area crystalline growth

KAUST Repository

Tomasi, Andrea

2017-04-24

For crystalline-silicon solar cells, voltages close to the theoretical limit are nowadays readily achievable when using passivating contacts. Conversely, maximal current generation requires the integration of the electron and hole contacts at the back of the solar cell to liberate its front from any shadowing loss. Recently, the world-record efficiency for crystalline-silicon single-junction solar cells was achieved by merging these two approaches in a single device; however, the complexity of fabricating this class of devices raises concerns about their commercial potential. Here we show a contacting method that substantially simplifies the architecture and fabrication of back-contacted silicon solar cells. We exploit the surface-dependent growth of silicon thin films, deposited by plasma processes, to eliminate the patterning of one of the doped carrier-collecting layers. Then, using only one alignment step for electrode definition, we fabricate a proof-of-concept 9-cm2 tunnel-interdigitated back-contact solar cell with a certified conversion efficiency >22.5%.

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.

2014-12-01

Today\\'s mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

CMOS compatible generic batch process towards flexible memory on bulk monocrystalline silicon (100)

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Kutbee, Arwa T.; Hanna, Amir; Hussain, Muhammad Mustafa

2014-01-01

Today's mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

Key Processes of Silicon-On-Glass MEMS Fabrication Technology for Gyroscope Application.

Science.gov (United States)

Ma, Zhibo; Wang, Yinan; Shen, Qiang; Zhang, Han; Guo, Xuetao

2018-04-17

MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.

Achievement Report for fiscal 1997 on developing a silicon manufacturing process with reduced energy consumption. Development of silicon mass-production manufacturing technology for solar cells; 1997 nendo energy shiyo gorika silicon seizo process kaihatsu. Taiyo denchiyo silicon ryosanka seizo gijutsu no kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

1998-03-01

In order to manufacture silicon for solar cells, development is intended on a technology to manufacture silicon (SOG-Si) for solar cells by means of metallurgical methods using metallic silicon with purity generally available as an interim starting material. The silicon is required of p-type electric conductivity characteristics with specific resistance of 0.5 to 1.5 ohm per cm, to be sufficient even with 6-7N as compared to silicon for semiconductors (11-N), and to be low in cost. While the NEDO fluid bed process and the metallurgical NEDO direct reduction process have been developed based on the technology to manufacture silicon for semiconductors, the basic policy was established to develop a new manufacturing method using commercially available high-purity metallic silicon as an interim starting material, with an objective to achieve cost as low as capable of responding to small-quantity phase production for proliferation purpose. Removal of boron and phosphor has been the main issue in the development, whereas SOG-Si was manufactured in a laboratory scale by combining with the conventional component technologies in fiscal 1991 and 1992. The scale was expanded to 20 kg since fiscal 1993, and a five year plan starting fiscal 1996 was decided to develop the technology for industrial scale. Fiscal 1997 has promoted the development by using the 20-kg scale device, and introduced facilities to develop technology for mass-production scale. (NEDO)

A manufacturable process integration approach for graphene devices

Science.gov (United States)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Synthesis of silicon nanocomposite for printable photovoltaic devices on flexible substrate

Science.gov (United States)

Odo, E. A.; Faremi, A. A.

2017-06-01

Renewed interest has been established in the preparation of silicon nanoparticles for electronic device applications. In this work, we report on the production of silicon powders using a simple ball mill and of silicon nanocomposite ink for screen-printable photovoltaic device on a flexible substrate. Bulk single crystalline silicon was milled for 25 h in the ball mill. The structural properties of the produced silicon nanoparticles were investigated using X-ray diffraction (XRD) and transmission electron microscopy. The results show that the particles remained highly crystalline, though transformed from their original single crystalline state to polycrystalline. The elemental composition using energy dispersive X-ray florescence spectroscopy (EDXRF) revealed that contamination from iron (Fe) and chromium (Cr) of the milling media and oxygen from the atmosphere were insignificant. The size distribution of the nanoparticles follows a lognormal pattern that ranges from 60 nm to about 1.2 μm and a mean particle size of about 103 nm. Electrical characterization of screen-printed PN structures of the nanocomposite formed by embedding the powder into a suitable water-soluble polymer on Kapton sheet reveals an enhanced photocurrent transport resulting from photo-induced carrier generation in the depletion region with energy greater that the Schottky barrier height at the metal-composite interface.

Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

Energy Technology Data Exchange (ETDEWEB)

Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

2009-06-10

We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

International Nuclear Information System (INIS)

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

2014-01-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

Analysis of heating effect on the process of high deposition rate microcrystalline silicon

International Nuclear Information System (INIS)

Xiao-Dan, Zhang; He, Zhang; Chang-Chun, Wei; Jian, Sun; Guo-Fu, Hou; Shao-Zhen, Xiong; Xin-Hua, Geng; Ying, Zhao

2010-01-01

A possible heating effect on the process of high deposition rate microcrystalline silicon has been studied. It includes the discharge time-accumulating heating effect, discharge power, inter-electrode distance, and total gas flow rate induced heating effect. It is found that the heating effects mentioned above are in some ways quite similar to and in other ways very different from each other. However, all of them will directly or indirectly cause the increase of the substrate surface temperature during the process of depositing microcrystalline silicon thin films, which will affect the properties of the materials with increasing time. This phenomenon is very serious for the high deposition rate of microcrystalline silicon thin films because of the high input power and the relatively small inter-electrode distance needed. Through analysis of the heating effects occurring in the process of depositing microcrystalline silicon, it is proposed that the discharge power and the heating temperature should be as low as possible, and the total gas flow rate and the inter-electrode distance should be suitable so that device-grade high quality deposition rate microcrystalline silicon thin films can be fabricated

Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs

DEFF Research Database (Denmark)

Li, Helong; Munk-Nielsen, Stig; Wang, Xiongfei

2016-01-01

This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influ......This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then......, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance...... of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed...

Mechanical engineering and design of silicon-based particle tracking devices

International Nuclear Information System (INIS)

Miller, W.O.; Thompson, T.C.; Gamble, M.T.; Reid, R.S.; Woloshun, K.A.; Dransfield, G.D.; Ziock, H.J.

1990-01-01

The Mechanical Engineering and Electronics Division of the Los Alamos National Laboratory has been investigating silicon-based particle tracking device technology as part of the Superconducting Super Collider-sponsored silicon subsystem collaboration. Structural, thermal, and materials issues have been addressed. This paper discussed detector structural integrity and stability, including detailed finite element models of the silicon chip support and predictive methods used in designing with advanced composite materials. Electronic thermal loading and efficient dissipation of such energy using heat pipe technology has been investigated. The use of materials whose coefficients of thermal expansion are engineered to match silicon or to be near zero, as appropriate, have been explored. Material analysis and test results from radiation, chemical, and static loading are compared with analytical predictions and discussed. 1 ref., 2 figs., 1 tab

Nanocrystalline Silicon Carrier Collectors for Silicon Heterojunction Solar Cells and Impact on Low-Temperature Device Characteristics

KAUST Repository

Nogay, Gizem

2016-09-26

Silicon heterojunction solar cells typically use stacks of hydrogenated intrinsic/doped amorphous silicon layers as carrier selective contacts. However, the use of these layers may cause parasitic optical absorption losses and moderate fill factor (FF) values due to a high contact resistivity. In this study, we show that the replacement of doped amorphous silicon with nanocrystalline silicon is beneficial for device performance. Optically, we observe an improved short-circuit current density when these layers are applied to the front side of the device. Electrically, we observe a lower contact resistivity, as well as higher FF. Importantly, our cell parameter analysis, performed in a temperature range from -100 to +80 °C, reveals that the use of hole-collecting p-type nanocrystalline layer suppresses the carrier transport barrier, maintaining FF s in the range of 70% at -100 °C, whereas it drops to 40% for standard amorphous doped layers. The same analysis also reveals a saturation onset of the open-circuit voltage at -100 °C using doped nanocrystalline layers, compared with saturation onset at -60 °C for doped amorphous layers. These findings hint at a reduced importance of the parasitic Schottky barrier at the interface between the transparent electrodes and the selective contact in the case of nanocrystalline layer implementation. © 2011-2012 IEEE.

Nanocrystalline Silicon Carrier Collectors for Silicon Heterojunction Solar Cells and Impact on Low-Temperature Device Characteristics

KAUST Repository

Nogay, Gizem; Seif, Johannes Peter; Riesen, Yannick; Tomasi, Andrea; Jeangros, Quentin; Wyrsch, Nicolas; Haug, Franz-Josef; De Wolf, Stefaan; Ballif, Christophe

2016-01-01

Silicon heterojunction solar cells typically use stacks of hydrogenated intrinsic/doped amorphous silicon layers as carrier selective contacts. However, the use of these layers may cause parasitic optical absorption losses and moderate fill factor (FF) values due to a high contact resistivity. In this study, we show that the replacement of doped amorphous silicon with nanocrystalline silicon is beneficial for device performance. Optically, we observe an improved short-circuit current density when these layers are applied to the front side of the device. Electrically, we observe a lower contact resistivity, as well as higher FF. Importantly, our cell parameter analysis, performed in a temperature range from -100 to +80 °C, reveals that the use of hole-collecting p-type nanocrystalline layer suppresses the carrier transport barrier, maintaining FF s in the range of 70% at -100 °C, whereas it drops to 40% for standard amorphous doped layers. The same analysis also reveals a saturation onset of the open-circuit voltage at -100 °C using doped nanocrystalline layers, compared with saturation onset at -60 °C for doped amorphous layers. These findings hint at a reduced importance of the parasitic Schottky barrier at the interface between the transparent electrodes and the selective contact in the case of nanocrystalline layer implementation. © 2011-2012 IEEE.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Optimization of process parameter variations on leakage current in in silicon-oninsulator vertical double gate mosfet device

Directory of Open Access Journals (Sweden)

K.E. Kaharudin

2015-12-01

Full Text Available This paper presents a study of optimizing input process parameters on leakage current (IOFF in silicon-on-insulator (SOI Vertical Double-Gate,Metal Oxide Field-Effect-Transistor (MOSFET by using L36 Taguchi method. The performance of SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF value. An orthogonal array, main effects, signal-to-noise ratio (SNR and analysis of variance (ANOVA are utilized in order to analyze the effect of input process parameter variation on leakage current (IOFF. Based on the results, the minimum leakage current ((IOFF of SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION value at 434 µA/µm. Both the drive current (ION and leakage current (IOFF values yield a higher ION/IOFF ratio (48.22 x 106 for low power consumption application. Meanwhile, polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors with each of the contributing factor effects percentage of 59% and 25%.

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

Energy Technology Data Exchange (ETDEWEB)

Seif, Johannes Peter, E-mail: johannes.seif@alumni.epfl.ch; Ballif, Christophe; De Wolf, Stefaan [Photovoltaics and Thin-Film Electronics Laboratory, Institute of Microengineering (IMT), Ecole Polytechnique Fédérale de Lausanne (EPFL), Rue de la Maladière 71b, CH-2002 Neuchâtel (Switzerland); Menda, Deneb; Özdemir, Orhan [Department of Physics, Yıldız Technical University, Davutpasa Campus, TR-34210 Esenler, Istanbul (Turkey); Descoeudres, Antoine; Barraud, Loris [CSEM, PV-Center, Jaquet-Droz 1, CH-2002 Neuchâtel (Switzerland)

2016-08-07

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation of such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.

Optimized optical devices for edge-coupling-enabled silicon photonics platform

Science.gov (United States)

Png, Ching Eng; Ang, Thomas Y. L.; Ong, Jun Rong; Lim, Soon Thor; Sahin, Ezgi; Chen, G. F. R.; Tan, D. T. H.; Guo, Tina X.; Wang, Hong

2018-02-01

We present a library of high-performance passive and active silicon photonic devices at the C-band that is specifically designed and optimized for edge-coupling-enabled silicon photonics platform. These devices meet the broadband (100 nm), low-loss (= 25 Gb/s), and polarization diversity requirements (TE and TM polarization extinction ratio beam splitters (PBSs), and high-speed modulators are some of the devices within our library. In particular, we have designed and fabricated inverse taper fiber-to-waveguide edge couplers of tip widths ranging from 120 nm to 200 nm, and we obtained a low coupling loss of 1.80+/-0.28 dB for 160 nm tip width. To achieve polarization diversity operation for inverse tapers, we have experimentally realized different designs of polarization beam splitters (PBS). Our optimized PBS has a measured extinction ratio of <= 25 dB for both the quasiTE modes, and quasi-TM modes. Additionally, a broadband (100 nm) directional coupler with a 50/50 power splitting ratio was experimentally realized on a small footprint of 20×3 μm2 . Last but not least, high-speed silicon modulators with a range of carrier doping concentrations and offset of the PN junction can be used to optimise the modulation efficiency, and insertion losses for operation at 25 GHz.

Molecular monolayers for electrical passivation and functionalization of silicon-based solar energy devices

NARCIS (Netherlands)

Veerbeek, Janneke; Firet, Nienke J.; Vijselaar, Wouter; Elbersen, R.; Gardeniers, Han; Huskens, Jurriaan

2017-01-01

Silicon-based solar fuel devices require passivation for optimal performance yet at the same time need functionalization with (photo)catalysts for efficient solar fuel production. Here, we use molecular monolayers to enable electrical passivation and simultaneous functionalization of silicon-based

Rapid Prototyping of Nanofluidic Slits in a Silicone Bilayer

Science.gov (United States)

Kole, Thomas P.; Liao, Kuo-Tang; Schiffels, Daniel; Ilic, B. Robert; Strychalski, Elizabeth A.; Kralj, Jason G.; Liddle, J. Alexander; Dritschilo, Anatoly; Stavis, Samuel M.

2015-01-01

This article reports a process for rapidly prototyping nanofluidic devices, particularly those comprising slits with microscale widths and nanoscale depths, in silicone. This process consists of designing a nanofluidic device, fabricating a photomask, fabricating a device mold in epoxy photoresist, molding a device in silicone, cutting and punching a molded silicone device, bonding a silicone device to a glass substrate, and filling the device with aqueous solution. By using a bilayer of hard and soft silicone, we have formed and filled nanofluidic slits with depths of less than 400 nm and aspect ratios of width to depth exceeding 250 without collapse of the slits. An important attribute of this article is that the description of this rapid prototyping process is very comprehensive, presenting context and details which are highly relevant to the rational implementation and reliable repetition of the process. Moreover, this process makes use of equipment commonly found in nanofabrication facilities and research laboratories, facilitating the broad adaptation and application of the process. Therefore, while this article specifically informs users of the Center for Nanoscale Science and Technology (CNST) at the National Institute of Standards and Technology (NIST), we anticipate that this information will be generally useful for the nanofabrication and nanofluidics research communities at large, and particularly useful for neophyte nanofabricators and nanofluidicists. PMID:26958449

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

Science.gov (United States)

Tokel, Onur; Turnalı, Ahmet; Makey, Ghaith; Elahi, Parviz; ćolakoǧlu, Tahir; Ergeçen, Emre; Yavuz, Ã.-zgün; Hübner, René; Zolfaghari Borra, Mona; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ã.-mer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3, with untapped potential for mid-infrared optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow the fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realized with techniques like reactive ion etching. Embedded optical elements7, electronic devices and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1-µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has an optical index different to that in unmodified parts, enabling the creation of numerous photonic devices. Optionally, these parts can be chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface—that is, `in-chip'—microstructures for microfluidic cooling of chips, vias, micro-electro-mechanical systems, photovoltaic applications and photonic devices that match or surpass corresponding state-of-the-art device performances.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon.

Science.gov (United States)

Tokel, Onur; Turnali, Ahmet; Makey, Ghaith; Elahi, Parviz; Çolakoğlu, Tahir; Ergeçen, Emre; Yavuz, Özgün; Hübner, René; Borra, Mona Zolfaghari; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F Ömer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3 with untapped potential for mid-IR optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realised with techniques like reactive ion etching. Embedded optical elements, like in glass7, electronic devices, and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1 µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has a different optical index than unmodified parts, which enables numerous photonic devices. Optionally, these parts are chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface, i.e. , " in-chip" microstructures for microfluidic cooling of chips, vias, MEMS, photovoltaic applications and photonic devices that match or surpass the corresponding state-of-the-art device performances.

Friction and dynamically dissipated energy dependence on temperature in polycrystalline silicon MEMS devices

NARCIS (Netherlands)

Gkouzou, A.; Kokorian, J.; Janssen, G.C.A.M.; van Spengen, W.M.

2017-01-01

In this paper, we report on the influence of capillary condensation on the sliding friction of sidewall surfaces in polycrystalline silicon micro-electromechanical
systems (MEMS). We developed a polycrystalline silicon MEMS tribometer, which is a microscale test device with two components

Impurity doping processes in silicon

CERN Document Server

Wang, FFY

1981-01-01

This book introduces to non-experts several important processes of impurity doping in silicon and goes on to discuss the methods of determination of the concentration of dopants in silicon. The conventional method used is the discussion process, but, since it has been sufficiently covered in many texts, this work describes the double-diffusion method.

Practical silicon Light emitting devices fabricated by standard IC technology

International Nuclear Information System (INIS)

Aharoni, H.; Monuko du Plessis; Snyman, L.W.

2004-01-01

Full Text:Research activities are described with regard to the development of a comprehensive approach for the practical realization of single crystal Silicon Light Emitting Devices (Si-LEDs). Several interesting suggestions for the fabrication of such devices were made in the literature but they were not adopted by the semiconductor industry because they involve non-standard fabrication schemes, requiring special production lines. Our work presents an alternative approach, proposed and realized in practice by us, permitting the fabrication of Si-LEDs using the standard conventional fully industrialized IC technology ''as is'' without any adaptation. It enables their fabrication in the same production lines of the presently existing IC industry. This means that Si-LEDs can now be fabricated simultaneously with other components, such as transistors, on the same silicon chip, using the same masks and processing procedures. The result is that the yield, reliability, and price of the above Si-LEDs are the same as the other Si devices integrated on the same chip. In this work some structural details of several practical Si-LED's designed by us, as well as experimental results describing their performance are presented. These Si-LED's were fabricated to our specifications utilizing standard CMOS/BiCMOS technology, a fact which comprises an achievement by itself. The structure of the Si-LED's, is designed according to specifications such as the required operating voltage, overall light output intensity, its dependence(linear, or non-linear) on the input signal (voltage or current), light generations location (bulk, or near-surface), the emission pattern and uniformity. Such structural design present a problem since the designer can not use any structural parameters (such as doping levels and junction depths for example) but only those which already exist in the production lines. Since the fabrication procedures in these lines are originally designed for processing of

Thin film silicon solar cells: advanced processing and characterization - Final report

Energy Technology Data Exchange (ETDEWEB)

Ballif, Ch.

2008-04-15

This final report elaborated for the Swiss Federal Office of Energy (SFOE) takes a look at the results of a project carried out at the photovoltaics laboratory at the University of Neuchatel in Switzerland. The project aimed to demonstrate the production of high-efficiency thin-film silicon devices on flexible substrates using low cost processes. New ways of improving processing and characterisation are examined. The process and manufacturing know-how necessary to provide support for industrial partners within the framework of further projects is discussed. The authors state that the efficiency of most devices was significantly improved, both on glass substrates and on flexible plastic foils. The process reproducibility was also improved and the interactions between the different layers in the device are now said to be better understood. The report presents the results obtained and discusses substrate materials, transparent conductors, defect analyses and new characterisation tools. Finally, the laboratory infrastructure is described.

Device physics underlying silicon heterojunction and passivating-contact solar cells: A topical review

KAUST Repository

Chavali, Raghu V. K.; De Wolf, Stefaan; Alam, Muhammad A.

2018-01-01

The device physics of commercially dominant diffused-junction silicon solar cells is well understood, allowing sophisticated optimization of this class of devices. Recently, so-called passivating-contact solar cell technologies have become prominent

Large-scale membrane transfer process: its application to single-crystal-silicon continuous membrane deformable mirror

International Nuclear Information System (INIS)

Wu, Tong; Sasaki, Takashi; Hane, Kazuhiro; Akiyama, Masayuki

2013-01-01

This paper describes a large-scale membrane transfer process developed for the construction of large-scale membrane devices via the transfer of continuous single-crystal-silicon membranes from one substrate to another. This technique is applied for fabricating a large stroke deformable mirror. A bimorph spring array is used to generate a large air gap between the mirror membrane and the electrode. A 1.9 mm × 1.9 mm × 2 µm single-crystal-silicon membrane is successfully transferred to the electrode substrate by Au–Si eutectic bonding and the subsequent all-dry release process. This process provides an effective approach for transferring a free-standing large continuous single-crystal-silicon to a flexible suspension spring array with a large air gap. (paper)

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

Science.gov (United States)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

Science.gov (United States)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Silicide/Silicon Heterointerfaces, Reaction Kinetics and Ultra-short Channel Devices

Science.gov (United States)

Tang, Wei

Nickel silicide is one of the electrical contact materials widely used on very large scale integration (VLSI) of Si devices in microelectronic industry. This is because the silicide/silicon interface can be formed in a highly controlled manner to ensure reproducibility of optimal structural and electrical properties of the metal-Si contacts. These advantages can be inherited to Si nanowire (NW) field-effect transistors (FET) device. Due to the technological importance of nickel silicides, fundamental materials science of nickel silicides formation (Ni-Si reaction), especially in nanoscale, has raised wide interest and stimulate new insights and understandings. In this dissertation, in-situ transmission electron microscopy (TEM) in combination with FET device characterization will be demonstrated as useful tools in nano-device fabrication as well as in gaining insights into the process of nickel silicide formation. The shortest transistor channel length (17 nm) fabricated on a vapor-liquid-solid (VLS) grown silicon nanowire (NW) has been demonstrated by controlled reaction with Ni leads on an in-situ transmission electron microscope (TEM) heating stage at a moderate temperature of 400 ºC. NiSi2 is the leading phase, and the silicide-silicon interface is an atomically sharp type-A interface. At such channel lengths, high maximum on-currents of 890 (microA/microm) and a maximum transconductance of 430 (microS/microm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in a large number of SB-FETs with channel lengths in the range of (17 nm -- 3.6 microm). Our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, which is different from that in conventional MOSFETs

Process optimization of a deep trench isolation structure for high voltage SOI devices

International Nuclear Information System (INIS)

Zhu Kuiying; Qian Qinsong; Zhu Jing; Sun Weifeng

2010-01-01

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology. (semiconductor devices)

Micro-fabricated silicon devices for advanced thermal management and integration of particle tracking detectors

CERN Document Server

Romagnoli, Giulia; Gambaro, Carla

Since their first studies targeting the cooling of high-power computing chips, micro-channel devices are proven to provide a very efficient cooling system. In the last years micro-channel cooling has been successfully applied to the cooling of particle detectors at CERN. Thanks to their high thermal efficiency, they can guarantee a good heat sink for the cooling of silicon trackers, fundamental for the reduction of the radiation damage caused by the beam interactions. The radiation damage on the silicon detector is increasing with temperature and furthermore the detectors are producing heat that should be dissipated in the supporting structure. Micro-channels guarantee a distributed and uniform thermal exchange, thanks to the high flexibility of the micro-fabrication process that allows a large variety of channel designs. The thin nature of the micro-channels etched inside silicon wafers, is fulfilling the physics requirement of minimization of the material crossed by the particle beam. Furthermore micro-chan...

White-light emission from porous-silicon-aluminium Schottky junctions

International Nuclear Information System (INIS)

Masini, G.; La Monica, S.; Maiello, G.

1996-01-01

Porous-silicon-based white-light-emitting devices are presented. The fabrication process on different substrates is described. The peculiarities of technological steps for device fabrication (porous-silicon formation and aluminium treatment) are underlined. Doping profile of the porous layer, current-voltage characteristics, time response, lifetime tests and electroluminescence emission spectrum of the device are presented. A model for electrical behaviour of Al/porous silicon Schottky junction is presented. Electroluminescence spectrum of the presented devices showed strong similarities with white emission from crystalline silicon junctions in the breakdown region

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

Science.gov (United States)

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

Process of preparing tritiated porous silicon

Science.gov (United States)

Tam, Shiu-Wing

1997-01-01

A process of preparing tritiated porous silicon in which porous silicon is equilibrated with a gaseous vapor containing HT/T.sub.2 gas in a diluent for a time sufficient for tritium in the gas phase to replace hydrogen present in the pore surfaces of the porous silicon.

Off-axis electron holography for the measurement of active dopants in silicon semiconductor devices

International Nuclear Information System (INIS)

Cooper, David

2016-01-01

There is a need in the semiconductor industry for a dopant profiling technique with nm-scale resolution. Here we demonstrate that off-axis electron holography can be used to provide maps of the electrostatic potential in semiconductor devices with nm-scale resolution. In this paper we will discuss issues regarding the spatial resolution and precision of the technique. Then we will discuss problems with specimen preparation and how this affects the accuracy of the measurements of the potentials. Finally we show results from experimental off-axis electron holography applied to nMOS and pMOS CMOS devices grown on bulk silicon and silicon- on-insulator type devices and present solutions to common problems that are encountered when examining these types of devices. (paper)

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

Energy Technology Data Exchange (ETDEWEB)

Shiota, Koki, E-mail: a14510@sr.kagawa-nct.ac.jp; Kai, Kazuho; Nagaoka, Shiro, E-mail: nagaoka@es.kagawa-nct.ac.jp [National Institute of Technology, Kagawa College, Kagawa, Mitoyo, Takuma, Koda 551 (Japan); Tsuji, Takuto [National Institute of Technology, Suzuka College, Mie, Suzuka, Shiroko (Japan); Wakahara, Akihiro [Toyohashi University of Technology, Aichi, Toyohashi, Tenpaku, Hibarigaoka 1-1 (Japan); Rusop, Mohamad [University Technology Mara, Selangor, Shah Alam, 40450 (Malaysia)

2016-07-06

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As the result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.

Comparison of silicon pin diode detector fabrication processes using ion implantation and thermal doping

International Nuclear Information System (INIS)

Zhou, C.Z.; Warburton, W.K.

1996-01-01

Two processes for the fabrication of silicon p-i-n diode radiation detectors are described and compared. Both processes are compatible with conventional integrated-circuit fabrication techniques and yield very low leakage currents. Devices made from the process using boron thermal doping have about a factor of 2 lower leakage current than those using boron ion implantation. However, the boron thermal doping process requires additional process steps to remove boron skins. (orig.)

MOS structures containing silicon nanoparticles for memory device applications

International Nuclear Information System (INIS)

Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S

2008-01-01

Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability

Silicon based nanogap device for investigating electronic transport through 12 nm long oligomers

DEFF Research Database (Denmark)

Strobel, S.; Albert, E.; Csaba, G.

2009-01-01

We have fabricated vertical nanogap electrode devices based on Silicon-on-Insulator (SOI) substrates for investigating the electronic transport properties of long, conjugated molecular wires. Our nanogap electrode devices comprise smooth metallic contact pairs situated at the sidewall of an SOI s...

All-silica nanofluidic devices for DNA-analysis fabricated by imprint of sol-gel silica with silicon stamp

DEFF Research Database (Denmark)

Mikkelsen, Morten Bo Lindholm; Letailleur, Alban A; Søndergård, Elin

2011-01-01

We present a simple and cheap method for fabrication of silica nanofluidic devices for single-molecule studies. By imprinting sol-gel materials with a multi-level stamp comprising micro- and nanofeatures, channels of different depth are produced in a single process step. Calcination of the imprin......We present a simple and cheap method for fabrication of silica nanofluidic devices for single-molecule studies. By imprinting sol-gel materials with a multi-level stamp comprising micro- and nanofeatures, channels of different depth are produced in a single process step. Calcination...... of the imprinted hybrid sol-gel material produces purely inorganic silica, which has very low autofluorescence and can be fusion bonded to a glass lid. Compared to top-down processing of fused silica or silicon substrates, imprint of sol-gel silica enables fabrication of high-quality nanofluidic devices without...

David Adler Lectureship Award Talk: III-V Semiconductor Nanowires on Silicon for Future Devices

Science.gov (United States)

Riel, Heike

Bottom-up grown nanowires are very attractive materials for direct integration of III-V semiconductors on silicon thus opening up new possibilities for the design and fabrication of nanoscale devices for electronic, optoelectronic as well as quantum information applications. Template-Assisted Selective Epitaxy (TASE) allows the well-defined and monolithic integration of complex III-V nanostructures and devices on silicon. Achieving atomically abrupt heterointerfaces, high crystal quality and control of dimension down to 1D nanowires enabled the demonstration of FETs and tunnel devices based on In(Ga)As and GaSb. Furthermore, the strong influence of strain on nanowires as well as results on quantum transport studies of InAs nanowires with well-defined geometry will be presented.

On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

Science.gov (United States)

Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

2018-04-01

The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process.

Science.gov (United States)

Mehta, Karan K; Orcutt, Jason S; Shainline, Jeffrey M; Tehar-Zahav, Ofer; Sternberg, Zvi; Meade, Roy; Popović, Miloš A; Ram, Rajeev J

2014-02-15

We present measurements on resonant photodetectors utilizing sub-bandgap absorption in polycrystalline silicon ring resonators, in which light is localized in the intrinsic region of a p+/p/i/n/n+ diode. The devices, operating both at λ=1280 and λ=1550  nm and fabricated in a complementary metal-oxide-semiconductor (CMOS) dynamic random-access memory emulation process, exhibit detection quantum efficiencies around 20% and few-gigahertz response bandwidths. We observe this performance at low reverse biases in the range of a few volts and in devices with dark currents below 50 pA at 10 V. These results demonstrate that such photodetector behavior, previously reported by Preston et al. [Opt. Lett. 36, 52 (2011)], is achievable in bulk CMOS processes, with significant improvements with respect to the previous work in quantum efficiency, dark current, linearity, bandwidth, and operating bias due to additional midlevel doping implants and different material deposition. The present work thus offers a robust realization of a fully CMOS-fabricated all-silicon photodetector functional across a wide wavelength range.

Silicon-based sleeve devices for chemical reactions

Science.gov (United States)

Northrup, M. Allen; Mariella, Jr., Raymond P.; Carrano, Anthony V.; Balch, Joseph W.

1996-01-01

A silicon-based sleeve type chemical reaction chamber that combines heaters, such as doped polysilicon for heating, and bulk silicon for convection cooling. The reaction chamber combines a critical ratio of silicon and silicon nitride to the volume of material to be heated (e.g., a liquid) in order to provide uniform heating, yet low power requirements. The reaction chamber will also allow the introduction of a secondary tube (e.g., plastic) into the reaction sleeve that contains the reaction mixture thereby alleviating any potential materials incompatibility issues. The reaction chamber may be utilized in any chemical reaction system for synthesis or processing of organic, inorganic, or biochemical reactions, such as the polymerase chain reaction (PCR) and/or other DNA reactions, such as the ligase chain reaction, which are examples of a synthetic, thermal-cycling-based reaction. The reaction chamber may also be used in synthesis instruments, particularly those for DNA amplification and synthesis.

Silicon integrated circuits part A : supplement 2

CERN Document Server

Kahng, Dawon

1981-01-01

Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

Science.gov (United States)

Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro

2013-04-01

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.; Rojas, Jhonathan Prieto; Ahmed, Sally; Hussain, Aftab M.; Inayat, Salman Bin; Hussain, Muhammad Mustafa

2013-01-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.

2013-06-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

13th Workshop on Crystalline Silicon Solar Cell Materials and Processes: Extended Abstracts and Papers

Energy Technology Data Exchange (ETDEWEB)

Sopori, B. L.; Rand, J.; Saitoh, T.; Sinton, R.; Stavola, M.; Swanson, D.; Tan, T.; Weber, E.; Werner, J.; Al-Jassim, M.

2003-08-01

The 13th Workshop will provide a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and relevant non-photovoltaic fields. It will offer an excellent opportunity for researchers in private industry and at universities to prioritize mutual needs for future collaborative research. The workshop is intended to address the fundamental aspects of impurities and defects in silicon: their properties, the dynamics during device processing, and their application for developing low-cost processes for manufacturing high-efficiency silicon solar cells. A combination of oral, poster, and discussion sessions will review recent advances in crystal growth, new cell structures, new processes and process characterization techniques, and cell fabrication approaches suitable for future manufacturing demands.

Seventh workshop on the role of impurities and defects in silicon device processing

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-08-01

This workshop is the latest in a series which has looked at technological issues related to the commercial development and success of silicon based photovoltaic (PV) modules. PV modules based on silicon are the most common at present, but face pressure from other technologies in terms of cell performance and cell cost. This workshop addresses a problem which is a factor in the production costs of silicon based PV modules.

Dopant atoms as quantum components in silicon nanoscale devices

Science.gov (United States)

Zhao, Xiaosong; Han, Weihua; Wang, Hao; Ma, Liuhong; Li, Xiaoming; Zhang, Wang; Yan, Wei; Yang, Fuhua

2018-06-01

Recent progress in nanoscale fabrication allows many fundamental studies of the few dopant atoms in various semiconductor nanostructures. Since the size of nanoscale devices has touched the limit of the nature, a single dopant atom may dominate the performance of the device. Besides, the quantum computing considered as a future choice beyond Moore's law also utilizes dopant atoms as functional units. Therefore, the dopant atoms will play a significant role in the future novel nanoscale devices. This review focuses on the study of few dopant atoms as quantum components in silicon nanoscale device. The control of the number of dopant atoms and unique quantum transport characteristics induced by dopant atoms are presented. It can be predicted that the development of nanoelectronics based on dopant atoms will pave the way for new possibilities in quantum electronics. Project supported by National Key R&D Program of China (No. 2016YFA0200503).

MEMS monocrystalline-silicon based thermal devices for chemical and microfluidic applications

NARCIS (Netherlands)

Mihailovic, M.

2011-01-01

This thesis explores the employment of monocrystalline silicon in microsystems as an active material for different thermal functions, such as heat generation and heat transfer by conduction. In chapter 1 applications that need thermal micro devices, micro heaters and micro heat exchangers, are

Nitride-based Quantum-Confined Structures for Ultraviolet-Visible Optical Devices on Silicon Substrates

KAUST Repository

Janjua, Bilal

2017-04-01

III–V nitride quantum-confined structures embedded in nanowires (NWs), also known as quantum-disks-in-nanowires (Qdisks-in-NWs), have recently emerged as a new class of nanoscale materials exhibiting outstanding properties for optoelectronic devices and systems. It is promising for circumventing the technology limitation of existing planar epitaxy devices, which are bounded by the lattice-, crystal-structure-, and thermal- matching conditions. This work presents significant advances in the growth of good quality GaN, InGaN and AlGaN Qdisks-in-NWs based on careful optimization of the growth parameters, coupled with a meticulous layer structure and active region design. The NWs were grown, catalyst-free, using plasma assisted molecular beam epitaxy (PAMBE) on silicon (Si) substrates. A 2-step growth scheme was developed to achieve high areal density, dislocation free and vertically aligned NWs on Ti/Si substrates. Numerical modeling of the NWs structures, using the nextnano3 software, showed reduced polarization fields, and, in the presence of Qdisks, exhibited improved quantum-confinement; thus contributing to high carrier radiative-recombination rates. As a result, based on the growth and device structure optimization, the technologically challenging orange and yellow NWs light emitting devices (LEDs) targeting the ‘green-yellow’ gap were demonstrated on scalable, foundry compatible, and low-cost Ti coated Si substrates. The NWs work was also extended to LEDs emitting in the ultraviolet (UV) range with niche applications in environmental cleaning, UV-curing, medicine, and lighting. In this work, we used a Ti (100 nm) interlayer and Qdisks to achieve good quality AlGaN based UV-A (320 - 400 nm) device. To address the issue of UV-absorbing polymer, used in the planarization process, we developed a pendeo-epitaxy technique, for achieving an ultra-thin coalescence of the top p-GaN contact layer, for a self-planarized Qdisks-in-NWs UV-B (280 – 320 nm) LED grown

Silicon Nano-Photonic Devices

DEFF Research Database (Denmark)

Pu, Minhao

with the couplers, a silicon ridge waveguide is utilized in nonlinear all-optical signal processing for optical time division multiplexing (OTDM) systems. Record ultra-highspeed error-free optical demultiplexing and waveform sampling are realized and demonstrated for the rst time. Microwave phase shifters and notch...... lters based on tunable microring resonators are proposed and analyzed. Based on a single microring resonator, a maximum radio frequency (RF) phase shift of 336degrees is obtained, but with large power variation. By utilizing a dual-microring resonator, a RF phase shifting range larger than 2pi...

Electronic spectrum of a deterministic single-donor device in silicon

International Nuclear Information System (INIS)

Fuechsle, Martin; Miwa, Jill A.; Mahapatra, Suddhasatta; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.

2013-01-01

We report the fabrication of a single-electron transistor (SET) based on an individual phosphorus dopant that is deterministically positioned between the dopant-based electrodes of a transport device in silicon. Electronic characterization at mK-temperatures reveals a charging energy that is very similar to the value expected for isolated P donors in a bulk Si environment. Furthermore, we find indications for bulk-like one-electron excited states in the co-tunneling spectrum of the device, in sharp contrast to previous reports on transport through single dopants

Current-voltage characteristics of porous-silicon structures

International Nuclear Information System (INIS)

Diligenti, A.; Nannini, A.; Pennelli, G.; Pieri, F.; Fuso, F.; Allegrini, M.

1996-01-01

I-V DC characteristics have been measured on metal/porous-silicon structures. In particular, the measurements on metal/free-standing porous-silicon film/metal devices confirmed the result, already obtained, that the metal/porous-silicon interface plays a crucial role in the transport of any device. Four-contacts measurements on free-standing layers showed that the current linearly depends on the voltage and that the conduction process is thermally activated, the activation energy depending on the porous silicon film production parameters. Finally, annealing experiments performed in order to improve the conduction of rectifying contacts, are described

Environmentally benign silicon solar cell manufacturing

Energy Technology Data Exchange (ETDEWEB)

Tsuo, Y.S. [National Renewable Energy Lab., Golden, CO (United States); Gee, J.M. [Sandia National Labs., Albuquerque, NM (United States); Menna, P. [National Agency for New Technologies Energy and Environment, Portici (Italy); Strebkov, D.S.; Pinov, A.; Zadde, V. [Intersolarcenter, Moscow (Russian Federation)

1998-09-01

The manufacturing of silicon devices--from polysilicon production, crystal growth, ingot slicing, wafer cleaning, device processing, to encapsulation--requires many steps that are energy intensive and use large amounts of water and toxic chemicals. In the past two years, the silicon integrated-circuit (IC) industry has initiated several programs to promote environmentally benign manufacturing, i.e., manufacturing practices that recover, recycle, and reuse materials resources with a minimal consumption of energy. Crystalline-silicon solar photovoltaic (PV) modules, which accounted for 87% of the worldwide module shipments in 1997, are large-area devices with many manufacturing steps similar to those used in the IC industry. Obviously, there are significant opportunities for the PV industry to implement more environmentally benign manufacturing approaches. Such approaches often have the potential for significant cost reduction by reducing energy use and/or the purchase volume of new chemicals and by cutting the amount of used chemicals that must be discarded. This paper will review recent accomplishments of the IC industry initiatives and discuss new processes for environmentally benign silicon solar-cell manufacturing.

Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2013-01-01

(100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

Effect of layer thickness on device response of silicon heavily supersaturated with sulfur

Energy Technology Data Exchange (ETDEWEB)

Hutchinson, David [Department of Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy NY 12180 (United States); Department of Physics and Nuclear Engineering, United States Military Academy, West Point NY 10996 (United States); Mathews, Jay [US Army ARDEC – Benét Laboratories, Watervliet NY 12189 (United States); Department of Physics, University of Dayton, Dayton, OH 45469 (United States); Sullivan, Joseph T.; Buonassisi, Tonio [School of Engineering, Massachusetts Institute of Technology, Cambridge MA 02139 (United States); Akey, Austin [School of Engineering, Massachusetts Institute of Technology, Cambridge MA 02139 (United States); Harvard John A. Paulson School of Engineering and Applied Sciences, Cambridge MA 02138 (United States); Aziz, Michael J. [Harvard John A. Paulson School of Engineering and Applied Sciences, Cambridge MA 02138 (United States); Persans, Peter [Department of Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy NY 12180 (United States); Warrender, Jeffrey M., E-mail: jwarrend@post.harvard.edu [US Army ARDEC – Benét Laboratories, Watervliet NY 12189 (United States)

2016-05-15

We report on a simple experiment in which the thickness of a hyperdoped silicon layer, supersaturated with sulfur by ion implantation followed by pulsed laser melting and rapid solidification, is systematically varied at constant average sulfur concentration, by varying the implantation energy, dose, and laser fluence. Contacts are deposited and the external quantum efficiency (EQE) is measured for visible wavelengths. We posit that the sulfur layer primarily absorbs light but contributes negligible photocurrent, and we seek to support this by analyzing the EQE data for the different layer thicknesses in two interlocking ways. In the first, we use the measured concentration depth profiles to obtain the approximate layer thicknesses, and, for each wavelength, fit the EQE vs. layer thickness curve to obtain the absorption coefficient of hyperdoped silicon for that wavelength. Comparison to literature values for the hyperdoped silicon absorption coefficients [S.H. Pan et al. Applied Physics Letters 98, 121913 (2011)] shows good agreement. Next, we essentially run this process in reverse; we fit with Beer’s law the curves of EQE vs. hyperdoped silicon absorption coefficient for those wavelengths that are primarily absorbed in the hyperdoped silicon layer, and find that the layer thicknesses obtained from the fit are in good agreement with the original values obtained from the depth profiles. We conclude that the data support our interpretation of the hyperdoped silicon layer as providing negligible photocurrent at high S concentrations. This work validates the absorption data of Pan et al. [Applied Physics Letters 98, 121913 (2011)], and is consistent with reports of short mobility-lifetime products in hyperdoped layers. It suggests that for optoelectronic devices containing hyperdoped layers, the most important contribution to the above band gap photoresponse may be due to photons absorbed below the hyperdoped layer.

Effect of layer thickness on device response of silicon heavily supersaturated with sulfur

Directory of Open Access Journals (Sweden)

David Hutchinson

2016-05-01

Full Text Available We report on a simple experiment in which the thickness of a hyperdoped silicon layer, supersaturated with sulfur by ion implantation followed by pulsed laser melting and rapid solidification, is systematically varied at constant average sulfur concentration, by varying the implantation energy, dose, and laser fluence. Contacts are deposited and the external quantum efficiency (EQE is measured for visible wavelengths. We posit that the sulfur layer primarily absorbs light but contributes negligible photocurrent, and we seek to support this by analyzing the EQE data for the different layer thicknesses in two interlocking ways. In the first, we use the measured concentration depth profiles to obtain the approximate layer thicknesses, and, for each wavelength, fit the EQE vs. layer thickness curve to obtain the absorption coefficient of hyperdoped silicon for that wavelength. Comparison to literature values for the hyperdoped silicon absorption coefficients [S.H. Pan et al. Applied Physics Letters 98, 121913 (2011] shows good agreement. Next, we essentially run this process in reverse; we fit with Beer’s law the curves of EQE vs. hyperdoped silicon absorption coefficient for those wavelengths that are primarily absorbed in the hyperdoped silicon layer, and find that the layer thicknesses obtained from the fit are in good agreement with the original values obtained from the depth profiles. We conclude that the data support our interpretation of the hyperdoped silicon layer as providing negligible photocurrent at high S concentrations. This work validates the absorption data of Pan et al. [Applied Physics Letters 98, 121913 (2011], and is consistent with reports of short mobility-lifetime products in hyperdoped layers. It suggests that for optoelectronic devices containing hyperdoped layers, the most important contribution to the above band gap photoresponse may be due to photons absorbed below the hyperdoped layer.

Laser process for extended silicon thin film solar cells

International Nuclear Information System (INIS)

Hessmann, M.T.; Kunz, T.; Burkert, I.; Gawehns, N.; Schaefer, L.; Frick, T.; Schmidt, M.; Meidel, B.; Auer, R.; Brabec, C.J.

2011-01-01

We present a large area thin film base substrate for the epitaxy of crystalline silicon. The concept of epitaxial growth of silicon on large area thin film substrates overcomes the area restrictions of an ingot based monocrystalline silicon process. Further it opens the possibility for a roll to roll process for crystalline silicon production. This concept suggests a technical pathway to overcome the limitations of silicon ingot production in terms of costs, throughput and completely prevents any sawing losses. The core idea behind these thin film substrates is a laser welding process of individual, thin silicon wafers. In this manuscript we investigate the properties of laser welded monocrystalline silicon foils (100) by micro-Raman mapping and spectroscopy. It is shown that the laser beam changes the crystalline structure of float zone grown silicon along the welding seam. This is illustrated by Raman mapping which visualizes compressive stress as well as tensile stress in a range of - 147.5 to 32.5 MPa along the welding area.

Development of processes for the production of low cost silicon dendritic web for solar cells

Science.gov (United States)

Duncan, C. S.; Seidensticker, R. G.; Mchugh, J. P.; Hopkins, R. H.; Skutch, M. E.; Driggers, J. M.; Hill, F. E.

1980-01-01

High area output rates and continuous, automated growth are two key technical requirements for the growth of low-cost silicon ribbons for solar cells. By means of computer-aided furnace design, silicon dendritic web output rates as high as 27 sq cm/min have been achieved, a value in excess of that projected to meet a $0.50 per peak watt solar array manufacturing cost. The feasibility of simultaneous web growth while the melt is replenished with pelletized silicon has also been demonstrated. This step is an important precursor to the development of an automated growth system. Solar cells made on the replenished material were just as efficient as devices fabricated on typical webs grown without replenishment. Moreover, web cells made on a less-refined, pelletized polycrystalline silicon synthesized by the Battelle process yielded efficiencies up to 13% (AM1).

Silicon Photonics: All-Optical Devices for Linear and Nonlinear Applications

Science.gov (United States)

Driscoll, Jeffrey B.

Silicon photonics has grown rapidly since the first Si electro-optic switch was demonstrated in 1987, and the field has never grown more quickly than it has over the past decade, fueled by milestone achievements in semiconductor processing technologies for low loss waveguides, high-speed Si modulators, Si lasers, Si detectors, and an enormous toolbox of passive and active integrated devices. Silicon photonics is now on the verge of major commercialization breakthroughs, and optical communication links remain the force driving integrated and Si photonics towards the first commercial telecom and datacom transceivers; however other potential and future applications are becoming uncovered and refined as researchers reveal the benefits of manipulating photons on the nanoscale. This thesis documents an exploration into the unique guided-wave and nonlinear properties of deeply-scaled high-index-contrast sub-wavelength Si waveguides. It is found that the tight confinement inherent to single-mode channel waveguides on the silicon-on-insulator platform lead to a rich physics, which can be leveraged for new devices extending well beyond simple passive interconnects and electro-optic devices. The following chapters will concentrate, in detail, on a number of unique physical features of Si waveguides and extend these attributes towards new and interesting devices. Linear optical properties and nonlinear optical properties are investigated, both of which are strongly affected by tight optical confinement of the guided waveguide modes. As will be shown, tight optical confinement directly results in strongly vectoral modal components, where the electric and magnetic fields of the guided modes extend into all spatial dimensions, even along the axis of propagation. In fact, the longitudinal electric and magnetic field components can be just as strong as the transverse fields, directly affecting the modal group velocity and energy transport properties since the longitudinal fields

The use of silicon devices (diodes, RAMs, etc.) for alpha particle detection

International Nuclear Information System (INIS)

Agosteo, S.; Foglio Para, A.

1993-01-01

Silicon electronic devices (diodes, random access memories (RAMs), etc.) can be employed in alpha particle detection and spectroscopy with a good energy resolution. The detection mechanisms are first discussed; the performances of these devices operating in the pulse and in the current mode are then described starting from the pioneering works of the last decade. Some peculiar applications of RAMs are finally reported. (author). 7 refs, 5 figs, 1 tab

Using a novel spectroscopic reflectometer to optimize a radiation-hardened submicron silicon-on-sapphire CMOS process

International Nuclear Information System (INIS)

Do, N.T.; Zawaideh, E.; Vu, T.Q.; Warren, G.; Mead, D.; Do, N.T.; Li, G.P.; Tsai, C.S.

1999-01-01

A radiation-hardened sub-micron silicon-on-sapphire CMOS process is monitored and optimized using a novel optical technique based on spectroscopic reflectometry. Quantitative measurements of the crystal quality, surface roughness, and device radiation hardness show excellent correlation between this technique and the Atomic Force Microscopy. (authors)

Interaction between rare-earth ions and amorphous silicon nanoclusters produced at low processing temperatures

Energy Technology Data Exchange (ETDEWEB)

Meldrum, A. [Department of Physics, University of Alberta, Edmonton, T6G2J1 (Canada)]. E-mail: ameldrum@ualberta.ca; Hryciw, A. [Department of Physics, University of Alberta, Edmonton, T6G2J1 (Canada); MacDonald, A.N. [Department of Physics, University of Alberta, Edmonton, T6G2J1 (Canada); Blois, C. [Department of Physics, University of Alberta, Edmonton, T6G2J1 (Canada); Clement, T. [Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G2V4 (Canada); De Corby, R. [Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G2V4 (Canada); Wang, J. [Department of Physics, Chinese University of Hong Kong, Shatin, Hong Kong (China); Li Quan [Department of Physics, Chinese University of Hong Kong, Shatin, Hong Kong (China)

2006-12-15

Temperatures of 1000 deg. C and higher are a significant problem for the incorporation of erbium-doped silicon nanocrystal devices into standard silicon technology, and make the fabrication of contacts and reflectors in light emitting devices difficult. In the present work, we use energy-filtered TEM imaging techniques to show the formation of size-controlled amorphous silicon nanoclusters in SiO films annealed between 400 and 500 deg. C. The PL properties of such films are characteristic of amorphous silicon, and the spectrum can be controlled via a statistical size effect-as opposed to quantum confinement-that has previously been proposed for porous amorphous silicon. Finally, we show that amorphous nanoclusters sensitize the luminescence from the rare-earth ions Er, Nd, Yb, and Tm with excitation cross-sections similar in magnitude to erbium-doped silicon nanocrystal composites, and with a similar nonresonant energy transfer mechanism.

Thin film silicon by a microwave plasma deposition technique: Growth and devices, and, interface effects in amorphous silicon/crystalline silicon solar cells

Science.gov (United States)

Jagannathan, Basanth

Thin film silicon (Si) was deposited by a microwave plasma CVD technique, employing double dilution of silane, for the growth of low hydrogen content Si films with a controllable microstructure on amorphous substrates at low temperatures (prepared by this technique. Such films showed a dark conductivity ˜10sp{-6} S/cm, with a conduction activation energy of 0.49 eV. Film growth and properties have been compared for deposition in Ar and He carrier systems and growth models have been proposed. Low temperature junction formation by undoped thin film silicon was examined through a thin film silicon/p-type crystalline silicon heterojunctions. The thin film silicon layers were deposited by rf glow discharge, dc magnetron sputtering and microwave plasma CVD. The hetero-interface was identified by current transport analysis and high frequency capacitance methods as the key parameter controlling the photovoltaic (PV) response. The effect of the interface on the device properties (PV, junction, and carrier transport) was examined with respect to modifications created by chemical treatment, type of plasma species, their energy and film microstructure interacting with the substrate. Thermally stimulated capacitance was used to determine the interfacial trap parameters. Plasma deposition of thin film silicon on chemically clean c-Si created electron trapping sites while hole traps were seen when a thin oxide was present at the interface. Under optimized conditions, a 10.6% efficient cell (11.5% with SiOsb2 A/R) with an open circuit voltage of 0.55 volts and a short circuit current density of 30 mA/cmsp2 was fabricated.

Molecular Monolayers for Electrical Passivation and Functionalization of Silicon-Based Solar Energy Devices.

Science.gov (United States)

Veerbeek, Janneke; Firet, Nienke J; Vijselaar, Wouter; Elbersen, Rick; Gardeniers, Han; Huskens, Jurriaan

2017-01-11

Silicon-based solar fuel devices require passivation for optimal performance yet at the same time need functionalization with (photo)catalysts for efficient solar fuel production. Here, we use molecular monolayers to enable electrical passivation and simultaneous functionalization of silicon-based solar cells. Organic monolayers were coupled to silicon surfaces by hydrosilylation in order to avoid an insulating silicon oxide layer at the surface. Monolayers of 1-tetradecyne were shown to passivate silicon micropillar-based solar cells with radial junctions, by which the efficiency increased from 8.7% to 9.9% for n + /p junctions and from 7.8% to 8.8% for p + /n junctions. This electrical passivation of the surface, most likely by removal of dangling bonds, is reflected in a higher shunt resistance in the J-V measurements. Monolayers of 1,8-nonadiyne were still reactive for click chemistry with a model catalyst, thus enabling simultaneous passivation and future catalyst coupling.

Heterogenous integration of a thin-film GaAs photodetector and a microfluidic device on a silicon substrate

International Nuclear Information System (INIS)

Song, Fuchuan; Xiao, Jing; Udawala, Fidaali; Seo, Sang-Woo

2011-01-01

In this paper, heterogeneous integration of a III–V semiconductor thin-film photodetector (PD) with a microfluidic device is demonstrated on a SiO 2 –Si substrate. Thin-film format of optical devices provides an intimate integration of optical functions with microfluidic devices. As a demonstration of a multi-material and functional system, the biphasic flow structure in the polymeric microfluidic channels was co-integrated with a III–V semiconductor thin-film PD. The fluorescent drops formed in the microfluidic device are successfully detected with an integrated thin-film PD on a silicon substrate. The proposed three-dimensional integration structure is an alternative approach to combine optical functions with microfluidic functions on silicon-based electronic functions.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

Science.gov (United States)

Tour, James M; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2013-11-26

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the the gap region between the first electical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

Device for fracturing silicon-carbide coatings on nuclear-fuel particles

Science.gov (United States)

Turner, L.J.; Willey, M.G.; Tiegs, S.M.; Van Cleve, J.E. Jr.

This invention is a device for fracturing particles. It is designed especially for use in hot cells designed for the handling of radioactive materials. In a typical application, the device is used to fracture a hard silicon-carbide coating present on carbon-matrix microspheres containing nuclear-fuel materials, such as uranium or thorium compounds. To promote remote control and facilitate maintenance, the particle breaker is pneumatically operated and contains no moving parts. It includes means for serially entraining the entrained particles on an anvil housed in a leak-tight chamber. The flow rate of the gas is at a value effecting fracture of the particles; preferably, it is at a value fracturing them into product particulates of fluidizable size. The chamber is provided with an outlet passage whose cross-sectional area decreases in the direction away from the chamber. The outlet is connected tangentially to a vertically oriented vortex-flow separator for recovering the product particulates entrained in the gas outflow from the chamber. The invention can be used on a batch or continuous basis to fracture the silicon-carbide coatings on virtually all of the particles fed thereto.

Process Simulation and Characterization of Substrate Engineered Silicon Thin Film Transistor for Display Sensors and Large Area Electronics

International Nuclear Information System (INIS)

Hashmi, S M; Ahmed, S

2013-01-01

Design, simulation, fabrication and post-process qualification of substrate-engineered Thin Film Transistors (TFTs) are carried out to suggest an alternate manufacturing process step focused on display sensors and large area electronics applications. Damage created by ion implantation of Helium and Silicon ions into single-crystalline n-type silicon substrate provides an alternate route to create an amorphized region responsible for the fabrication of TFT structures with controllable and application-specific output parameters. The post-process qualification of starting material and full-cycle devices using Rutherford Backscattering Spectrometry (RBS) and Proton or Particle induced X-ray Emission (PIXE) techniques also provide an insight to optimize the process protocols as well as their applicability in the manufacturing cycle

High Input Voltage, Silicon Carbide Power Processing Unit Performance Demonstration

Science.gov (United States)

Bozak, Karin E.; Pinero, Luis R.; Scheidegger, Robert J.; Aulisio, Michael V.; Gonzalez, Marcelo C.; Birchenough, Arthur G.

2015-01-01

A silicon carbide brassboard power processing unit has been developed by the NASA Glenn Research Center in Cleveland, Ohio. The power processing unit operates from two sources: a nominal 300 Volt high voltage input bus and a nominal 28 Volt low voltage input bus. The design of the power processing unit includes four low voltage, low power auxiliary supplies, and two parallel 7.5 kilowatt (kW) discharge power supplies that are capable of providing up to 15 kilowatts of total power at 300 to 500 Volts (V) to the thruster. Additionally, the unit contains a housekeeping supply, high voltage input filter, low voltage input filter, and master control board, such that the complete brassboard unit is capable of operating a 12.5 kilowatt Hall effect thruster. The performance of the unit was characterized under both ambient and thermal vacuum test conditions, and the results demonstrate exceptional performance with full power efficiencies exceeding 97%. The unit was also tested with a 12.5kW Hall effect thruster to verify compatibility and output filter specifications. With space-qualified silicon carbide or similar high voltage, high efficiency power devices, this would provide a design solution to address the need for high power electric propulsion systems.

Silicon photonics design from devices to systems

CERN Document Server

Chrostowski, Lukas

2015-01-01

From design and simulation through to testing and fabrication, this hands-on introduction to silicon photonics engineering equips students with everything they need to begin creating foundry-ready designs. In-depth discussion of real-world issues and fabrication challenges ensures that students are fully equipped for careers in industry. Step-by-step tutorials, straightforward examples, and illustrative source code fragments guide students through every aspect of the design process, providing a practical framework for developing and refining key skills. Offering industry-ready expertise, the text supports existing PDKs for CMOS UV-lithography foundry services (OpSIS, ePIXfab, imec, LETI, IME and CMC) and the development of new kits for proprietary processes and clean-room based research. Accompanied by additional online resources to support students, this is the perfect learning package for senior undergraduate and graduate students studying silicon photonics design, and academic and industrial researchers in...

Structural modification of silicon during the formation process of porous silicon

International Nuclear Information System (INIS)

Martin-Palma, R.J.; Pascual, L.; Landa-Canovas, A.R.; Herrero, P.; Martinez-Duart, J.M.

2005-01-01

Direct examination of porous silicon (PS) by the use of high resolution transmission electron microscopy (HRTEM) allowed us to perform a deep insight into the formation mechanisms of this material. In particular, the structure of the PS/Si interface and that of the silicon nanocrystals that compose porous silicon were analyzed in detail. Furthermore, image processing was used to study in detail the structure of PS. The mechanism of PS formation and lattice matching between the PS layer and the Si substrate is analyzed and discussed. Finally, a formation mechanism for PS based on the experimental observations is proposed

Towards neuromorphic electronics: Memristors on foldable silicon fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-11-01

The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex\\'s folded pattern for ultra-compact design.

3D active edge silicon sensors: Device processing, yield and QA for the ATLAS-IBL production

Energy Technology Data Exchange (ETDEWEB)

Da Vià, Cinzia; Boscardil, Maurizio; Dalla Betta, GianFranco; Darbo, Giovanni; Fleta, Celeste; Gemme, Claudia; Giacomini, Gabriele; Grenier, Philippe; Grinstein, Sebastian; Hansen, Thor-Erik; Hasi, Jasmine; Kenney, Christopher; Kok, Angela; La Rosa, Alessandro; Micelli, Andrea; Parker, Sherwood; Pellegrini, Giulio; Pohl, David-Leon; Povoli, Marco; Vianello, Elisa; Zorzi, Nicola; Watts, S. J.

2013-01-01

3D silicon sensors, where plasma micromachining is used to etch deep narrow apertures in the silicon substrate to form electrodes of PIN junctions, were successfully manufactured in facilities in Europe and USA. In 2011 the technology underwent a qualification process to establish its maturity for a medium scale production for the construction of a pixel layer for vertex detection, the Insertable B-Layer (IBL) at the CERN-LHC ATLAS experiment. The IBL collaboration, following that recommendation from the review panel, decided to complete the production of planar and 3D sensors and endorsed the proposal to build enough modules for a mixed IBL sensor scenario where 25% of 3D modules populate the forward and backward part of each stave. The production of planar sensors will also allow coverage of 100% of the IBL, in case that option was required. This paper will describe the processing strategy which allowed successful 3D sensor production, some of the Quality Assurance (QA) tests performed during the pre-production phase and the production yield to date.

3D active edge silicon sensors: Device processing, yield and QA for the ATLAS-IBL production

Energy Technology Data Exchange (ETDEWEB)

Da Vià, Cinzia, E-mail: cinzia.da.via@cern.ch [School of Physics and Astronomy, The University of Manchester, Oxford Road, M13 9PL Manchester (United Kingdom); Boscardil, Maurizio [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Dalla Betta, GianFranco [DISI, Università degli Studi di Trento and INFN, Via Sommarive 14, I-38123 Trento (Italy); Darbo, Giovanni [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Fleta, Celeste [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Gemme, Claudia [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Giacomini, Gabriele [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Grenier, Philippe [SLAC National Accelerator Laboratory, 2575 Sand Hill Rd, Menlo Park, CA 94025 (United States); Grinstein, Sebastian [Institut de Fisica d' Altes Energies (IFAE) and ICREA, Universitat Autonoma de Barcelona (UAB) E-08193, Bellaterra, Barcelona (Spain); Hansen, Thor-Erik [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); Hasi, Jasmine; Kenney, Christopher [SLAC National Accelerator Laboratory, 2575 Sand Hill Rd, Menlo Park, CA 94025 (United States); Kok, Angela [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); La Rosa, Alessandro [CERN CH 1211, Geneva 23 (Switzerland); Micelli, Andrea [Tne University of Udine and INFN, via del Cotonificio 108, 33100 Udine (Italy); Parker, Sherwood [University of Hawaii, c/o Lawrence Berkeley Laboratory, Berkeley, CA 94720 (United States); Pellegrini, Giulio [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Pohl, David-Leon [Physikalisches Institut der Universität Bonn, Nußallee 12 D-53115, Bonn, Federal Republic of Germany (Germany); Povoli, Marco [DISI, Università degli Studi di Trento and INFN, Via Sommarive 14, I-38123 Trento (Italy); and others

2013-01-21

3D silicon sensors, where plasma micromachining is used to etch deep narrow apertures in the silicon substrate to form electrodes of PIN junctions, were successfully manufactured in facilities in Europe and USA. In 2011 the technology underwent a qualification process to establish its maturity for a medium scale production for the construction of a pixel layer for vertex detection, the Insertable B-Layer (IBL) at the CERN-LHC ATLAS experiment. The IBL collaboration, following that recommendation from the review panel, decided to complete the production of planar and 3D sensors and endorsed the proposal to build enough modules for a mixed IBL sensor scenario where 25% of 3D modules populate the forward and backward part of each stave. The production of planar sensors will also allow coverage of 100% of the IBL, in case that option was required. This paper will describe the processing strategy which allowed successful 3D sensor production, some of the Quality Assurance (QA) tests performed during the pre-production phase and the production yield to date.

Integrated porous-silicon light-emitting diodes: A fabrication process using graded doping profiles

International Nuclear Information System (INIS)

Barillaro, G.; Diligenti, A.; Pieri, F.; Fuso, F.; Allegrini, M.

2001-01-01

A fabrication process, compatible with an industrial bipolar+complementary metal - oxide - semiconductor (MOS)+diffusion MOS technology, has been developed for the fabrication of efficient porous-silicon-based light-emitting diodes. The electrical contact is fabricated with a double n + /p doping, achieving a high current injection efficiency and thus lower biasing voltages. The anodization is performed as the last step of the process, thus reducing potential incompatibilities with industrial processes. The fabricated devices show yellow-orange electroluminescence, visible with the naked eye in room lighting. A spectral characterization of light emission is presented and briefly discussed. [copyright] 2001 American Institute of Physics

Process development for high-efficiency silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Gee, J.M.; Basore, P.A.; Buck, M.E.; Ruby, D.S.; Schubert, W.K.; Silva, B.L.; Tingley, J.W.

1991-12-31

Fabrication of high-efficiency silicon solar cells in an industrial environment requires a different optimization than in a laboratory environment. Strategies are presented for process development of high-efficiency silicon solar cells, with a goal of simplifying technology transfer into an industrial setting. The strategies emphasize the use of statistical experimental design for process optimization, and the use of baseline processes and cells for process monitoring and quality control. 8 refs.

Crystal growth for high-efficiency silicon solar cells workshop: Summary

Science.gov (United States)

Dumas, K. A.

1985-01-01

The state of the art in the growth of silicon crystals for high-efficiency solar cells are reviewed, sheet requirements are defined, and furture areas of research are identified. Silicon sheet material characteristics that limit cell efficiencies and yields were described as well as the criteria for the ideal sheet-growth method. The device engineers wish list to the material engineer included: silicon sheet with long minority carrier lifetime that is uniform throughout the sheet, and which doesn't change during processing; and sheet material that stays flat throughout device processing, has uniform good mechanical strength, and is low cost. Impurities in silicon solar cells depreciate cell performance by reducing diffusion length and degrading junctions. The impurity behavior, degradation mechanisms, and variations in degradation threshold with diffusion length for silicon solar cells were described.

Electrical characterization of MIS devices using PECVD SiN{sub x}:H films for application of silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Yoo, Jin-Su; Cho, Jun-Sik; Park, Joo-Hyung; Ahn, Seung-Kyu; Shin, Kee-Shik; Yoon, Kyung-Hoon [Korea Institute of Energy Research, Daejeon (Korea, Republic of); Yi, Jun-Sin [Sungkyunkwan University, Suwon (Korea, Republic of)

2012-07-15

The surface passivation of crystalline silicon solar cells using plasma enhanced chemical vapor deposition (PECVD), hydrogenated, silicon-nitride (SiN{sub x}:H) thin films has become significant due to a low-temperature, low-cost and very effective defect passivation process. Also, a good quality antireflection coating can be formed. In this work, SiN{sub x}:H thin films were deposited by varying the gas ratio R (=NH{sub 3}/SiH{sub 4}+NH{sub 3}) and were annealed by rapid thermal processing (RTP). Metal-insulator- semiconductor (MIS) devices were fabricated using SiN{sub x}:H thin films as insulator layers and they were analyzed in the temperature range of 100 - 400 K by using capacitance-voltage (C-V) and current-voltage (I-V) measurements. The annealed SiN{sub x}:H thin films were evaluated by using the electrical properties at different temperature to determine the effect of surface passivation. We achieved an energy conversion efficiency of 18.1% under one-sun standard testing conditions for large-area (156 mm x 156 mm) crystalline-silicon solar cells.

Assessing the potential roles of silicon and germanium phthalocyanines in planar heterojunction organic photovoltaic devices and how pentafluoro phenoxylation can enhance π-π interactions and device performance.

Science.gov (United States)

Lessard, Benoît H; White, Robin T; Al-Amar, Mohammad; Plint, Trevor; Castrucci, Jeffrey S; Josey, David S; Lu, Zheng-Hong; Bender, Timothy P

2015-03-11

In this study, we have assessed the potential application of dichloro silicon phthalocyanine (Cl2-SiPc) and dichloro germanium phthalocyanine (Cl2-GePc) in modern planar heterojunction organic photovoltaic (PHJ OPV) devices. We have determined that Cl2-SiPc can act as an electron donating material when paired with C60 and that Cl2-SiPc or Cl2-GePc can also act as an electron acceptor material when paired with pentacene. These two materials enabled the harvesting of triplet energy resulting from the singlet fission process in pentacene. However, contributions to the generation of photocurrent were observed for Cl2-SiPc with no evidence of photocurrent contribution from Cl2-GePc. The result of our initial assessment established the potential for the application of SiPc and GePc in PHJ OPV devices. Thereafter, bis(pentafluoro phenoxy) silicon phthalocyanine (F10-SiPc) and bis(pentafluoro phenoxy) germanium phthalocyanine (F10-GePc) were synthesized and characterized. During thermal processing, it was discovered that F10-SiPc and F10-GePc underwent a reaction forming small amounts of difluoro SiPc (F2-SiPc) and difluoro GePc (F2-GePc). This undesirable reaction could be circumvented for F10-SiPc but not for F10-GePc. Using single crystal X-ray diffraction, it was determined that F10-SiPc has significantly enhanced π-π interactions compared with that of Cl2-SiPc, which had little to none. Unoptimized PHJ OPV devices based on F10-SiPc were fabricated and directly compared to those constructed from Cl2-SiPc, and in all cases, PHJ OPV devices based on F10-SiPc had significantly improved device characteristics compared to Cl2-SiPc.

Broadband Nonlinear Signal Processing in Silicon Nanowires

DEFF Research Database (Denmark)

Yvind, Kresten; Pu, Minhao; Hvam, Jørn Märcher

The fast non-linearity of silicon allows Tbit/s optical signal processing. By choosing suitable dimensions of silicon nanowires their dispersion can be tailored to ensure a high nonlinearity at power levels low enough to avoid significant two-photon abso We have fabricated low insertion...

Application of hydrogen-plasma technology for property modification of silicon and producing the silicon-based structures

International Nuclear Information System (INIS)

Fedotov, A.K.; Mazanik, A.V.; Ul'yashin, A.G.; Dzhob, R; Farner, V.R.

2000-01-01

Effects of atomic hydrogen on the properties of Czochralski-grown single crystal silicon as well as polycrystalline shaped silicon have been investigated. It was established that the buried defect layers created by high-energy hydrogen or helium ion implantation act as a good getter centers for hydrogen atoms introduced in silicon in the process of hydrogen plasma hydrogenation. Atomic hydrogen was shown to be active as a catalyzer significantly enhancing the rate of thermal donors formation in p-type single crystal silicon. This effect can be used for n-p- and p-n-p-silicon based device structures producing [ru

Semiconductors and semimetals oxygen in silicon

CERN Document Server

Willardson, Robert K; Beer, Albert C; Shimura, Fumio

1994-01-01

This volume reviews the latest understanding of the behavior and roles of oxygen in silicon, which will carry the field into the ULSI era from the experimental and theoretical points of view. The fourteen chapters, written by recognized authorities representing industrial and academic institutions, cover thoroughly the oxygen related phenomena from the crystal growth to device fabrication processes, as well as indispensable diagnostic techniques for oxygen.Key Features* Comprehensive study of the behavior of oxygen in silicon* Discusses silicon crystals for VLSI and ULSI applications* Thorough coverage from crystal growth to device fabrication* Edited by technical experts in the field* Written by recognized authorities from industrial and academic institutions* Useful to graduate students, scientists in other disciplines, and active participants in the arena of silicon-based microelectronics research* 297 original line drawings

Fabrication of a novel silicon single electron transistor for Si:P quantum computer devices

International Nuclear Information System (INIS)

Angus, S.J.; Smith, C.E.A.; Gauja, E.; Dzurak, A.S.; Clark, R.G.; Snider, G.L.

2004-01-01

Full text: Quantum computation relies on the successful measurement of quantum states. Single electron transistors (SETs) are known to be able to perform fast and sensitive charge measurements of solid state qubits. However, due to their sensitivity, SETs are also very susceptible to random charge fluctuations in a solid-state materials environment. In previous dc transport measurements, silicon-based SETs have demonstrated greater charge stability than A1/A1 2 O 3 SETs. We have designed and fabricated a novel silicon SET architecture for a comparison of the noise characteristics of silicon and aluminium based devices. The silicon SET described here is designed for controllable and reproducible low temperature operation. It is fabricated using a novel dual gate structure on a silicon-on-insulator substrate. A silicon quantum wire is formed in a 100nm thick high-resistivity superficial silicon layer using reactive ion etching. Carriers are induced in the silicon wire by a back gate in the silicon substrate. The tunnel barriers are created electrostatically, using lithographically defined metallic electrodes (∼40nm width). These tunnel barriers surround the surface of the quantum wire, thus producing excellent electrostatic confinement. This architecture provides independent control of tunnel barrier height and island occupancy, thus promising better control of Coulomb blockade oscillations than in previously investigated silicon SETs. The use of a near intrinsic silicon substrate offers compatibility with Si:P qubits in the longer term

All-(111) surface silicon nanowire field effect transistor devices: Effects of surface preparations

NARCIS (Netherlands)

Masood, M.N.; Carlen, Edwin; van den Berg, Albert

2014-01-01

Etching/hydrogen termination of All-(111) surface silicon nanowire field effect (SiNW-FET) devices developed by conventional photolithography and plane dependent wet etchings is studied with X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM) and

Enhanced Electroluminescence from Silicon Quantum Dots Embedded in Silicon Nitride Thin Films Coupled with Gold Nanoparticles in Light Emitting Devices

Directory of Open Access Journals (Sweden)

Ana Luz Muñoz-Rosas

2018-03-01

Full Text Available Nowadays, the use of plasmonic metal layers to improve the photonic emission characteristics of several semiconductor quantum dots is a booming tool. In this work, we report the use of silicon quantum dots (SiQDs embedded in a silicon nitride thin film coupled with an ultra-thin gold film (AuNPs to fabricate light emitting devices. We used the remote plasma enhanced chemical vapor deposition technique (RPECVD in order to grow two types of silicon nitride thin films. One with an almost stoichiometric composition, acting as non-radiative spacer; the other one, with a silicon excess in its chemical composition, which causes the formation of silicon quantum dots imbibed in the silicon nitride thin film. The ultra-thin gold film was deposited by the direct current (DC-sputtering technique, and an aluminum doped zinc oxide thin film (AZO which was deposited by means of ultrasonic spray pyrolysis, plays the role of the ohmic metal-like electrode. We found that there is a maximum electroluminescence (EL enhancement when the appropriate AuNPs-spacer-SiQDs configuration is used. This EL is achieved at a moderate turn-on voltage of 11 V, and the EL enhancement is around four times bigger than the photoluminescence (PL enhancement of the same AuNPs-spacer-SiQDs configuration. From our experimental results, we surmise that EL enhancement may indeed be due to a plasmonic coupling. This kind of silicon-based LEDs has the potential for technology transfer.

Thin Single Crystal Silicon Solar Cells on Ceramic Substrates: November 2009 - November 2010

Energy Technology Data Exchange (ETDEWEB)

Kumar, A.; Ravi, K. V.

2011-06-01

In this program we have been developing a technology for fabricating thin (< 50 micrometres) single crystal silicon wafers on foreign substrates. We reverse the conventional approach of depositing or forming silicon on foreign substrates by depositing or forming thick (200 to 400 micrometres) ceramic materials on high quality single crystal silicon films ~ 50 micrometres thick. Our key innovation is the fabrication of thin, refractory, and self-adhering 'handling layers or substrates' on thin epitaxial silicon films in-situ, from powder precursors obtained from low cost raw materials. This 'handling layer' has sufficient strength for device and module processing and fabrication. Successful production of full sized (125 mm X 125 mm) silicon on ceramic wafers with 50 micrometre thick single crystal silicon has been achieved and device process flow developed for solar cell fabrication. Impurity transfer from the ceramic to the silicon during the elevated temperature consolidation process has resulted in very low minority carrier lifetimes and resulting low cell efficiencies. Detailed analysis of minority carrier lifetime, metals analysis and device characterization have been done. A full sized solar cell efficiency of 8% has been demonstrated.

Analysis of quantum ballistic electron transport in ultrasmall silicon devices including space-charge and geometric effects

Science.gov (United States)

Laux, S. E.; Kumar, A.; Fischetti, M. V.

2004-05-01

A two-dimensional device simulation program which self consistently solves the Schrödinger and Poisson equations with current flow is described in detail. Significant approximations adopted in this work are the absence of scattering and a simple six-valley, parabolic band structure for silicon. A modified version of the quantum transmitting boundary method is used to describe open boundary conditions permitting current flow in device solutions far from equilibrium. The continuous energy spectrum of the system is discretized by temporarily imposing two different forms of closed boundary conditions, resulting in energies which sample the density-of-states and establish the wave function normalization conditions. These standing wave solutions ("normal modes") are decomposed into their traveling wave constituents, each of which represents injection from only one of the open boundary contacts ("traveling eigencomponents"). These current-carrying states are occupied by a drifted Fermi distribution associated with their injecting contact and summed to form the electron density in the device. Holes are neglected in this calculation. The Poisson equation is solved on the same finite element computational mesh as the Schrödinger equation; devices of arbitrary geometry can be modeled. Computational performance of the program including characterization of a "Broyden+Newton" algorithm employed in the iteration for self consistency is described. Device results are presented for a narrow silicon resonant tunneling diode (RTD) and many variants of idealized silicon double-gate field effect transistors (DGFETs). The RTD results show two resonant conduction peaks, each of which demonstrates hysteresis. Three 7.5 nm channel length DGFET structures with identical intrinsic device configurations but differing access geometries (straight, taper and "dog bone") are studied and found to have differing current flows owing to quantum-mechanical reflection in their access regions

Process control device

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Kobayashi, Hiroshi.

1994-01-01

A process control device comprises a memory device for memorizing a plant operation target, a plant state or a state of equipments related with each other as control data, a read-only memory device for storing programs, a plant instrumentation control device or other process control devices, an input/output device for performing input/output with an operator, and a processing device which conducts processing in accordance with the program and sends a control demand or a display demand to the input/output device. The program reads out control data relative to a predetermined operation target, compares and verify them with actual values to read out control data to be a practice premise condition which is further to be a practice premise condition if necessary, thereby automatically controlling the plant or requiring or displaying input. Practice presuming conditions for the operation target can be examined succesively in accordance with the program without constituting complicated logical figures and AND/OR graphs. (N.H.)

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

International Nuclear Information System (INIS)

Holland, S.E.

2000-01-01

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels

Superacid Passivation of Crystalline Silicon Surfaces.

Science.gov (United States)

Bullock, James; Kiriya, Daisuke; Grant, Nicholas; Azcatl, Angelica; Hettick, Mark; Kho, Teng; Phang, Pheng; Sio, Hang C; Yan, Di; Macdonald, Daniel; Quevedo-Lopez, Manuel A; Wallace, Robert M; Cuevas, Andres; Javey, Ali

2016-09-14

The reduction of parasitic recombination processes commonly occurring within the silicon crystal and at its surfaces is of primary importance in crystalline silicon devices, particularly in photovoltaics. Here we explore a simple, room temperature treatment, involving a nonaqueous solution of the superacid bis(trifluoromethane)sulfonimide, to temporarily deactivate recombination centers at the surface. We show that this treatment leads to a significant enhancement in optoelectronic properties of the silicon wafer, attaining a level of surface passivation in line with state-of-the-art dielectric passivation films. Finally, we demonstrate its advantage as a bulk lifetime and process cleanliness monitor, establishing its compatibility with large area photoluminescence imaging in the process.

Hybrid Integrated Platforms for Silicon Photonics

Science.gov (United States)

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Strained silicon/silicon germanium heterojunction n-channel metal oxide semiconductor field effect transistors

International Nuclear Information System (INIS)

Olsen, Sarah H.

2002-01-01

Investigations into the performance of strained silicon/silicon-germanium (Si/SiGe) n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) have been carried out. Theoretical predictions suggest that use of a strained Si/SiGe material system with advanced material properties compared with conventional silicon allows enhanced MOSFET device performance. This study has therefore investigated the practical feasibility of obtaining superior electrical performance using a Si/SiGe material system. The MOSFET devices consisted of a strained Si surface channel and were fabricated on relaxed SiGe material using a reduced thermal budget process in order to preserve the strain. Two batches of strained Si/SiGe devices fabricated on material grown by differing methods have been analysed and both showed good transistor action. A correlation of electrical and physical device data established that the electrical device behaviour was closely related to the SiGe material quality, which differed depending on growth technique. The cross-wafer variation in the electrical performance of the strained Si/SiGe devices was found to be a function of material quality, thus the viability of Si/SiGe MOSFET technology for commercial applications has been addressed. Of particular importance was the finding that large-scale 'cross-hatching' roughness associated with relaxed SiGe alloys led to degradation in the small-scale roughness at the gate oxide interface, which affects electrical device performance. The fabrication of strained Si MOSFET devices on high quality SiGe material thus enabled significant performance gains to be realised compared with conventional Si control devices. In contrast, the performance of devices fabricated on material with severe cross-hatching roughness was found to be diminished by the nanoscale oxide interface roughness. The effect of device processing on SiGe material with differing as-grown roughness has been carried out and compared with the reactions

Making Porous Luminescent Regions In Silicon Wafers

Science.gov (United States)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Silicone metalization

Energy Technology Data Exchange (ETDEWEB)

Maghribi, Mariam N. (Livermore, CA); Krulevitch, Peter (Pleasanton, CA); Hamilton, Julie (Tracy, CA)

2008-12-09

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Growth of a delta-doped silicon layer by molecular beam epitaxy on a charge-coupled device for reflection-limited ultraviolet quantum efficiency

Science.gov (United States)

Hoenk, Michael E.; Grunthaner, Paula J.; Grunthaner, Frank J.; Terhune, R. W.; Fattahi, Masoud; Tseng, Hsin-Fu

1992-01-01

Low-temperature silicon molecular beam epitaxy is used to grow a delta-doped silicon layer on a fully processed charge-coupled device (CCD). The measured quantum efficiency of the delta-doped backside-thinned CCD is in agreement with the reflection limit for light incident on the back surface in the spectral range of 260-600 nm. The 2.5 nm silicon layer, grown at 450 C, contained a boron delta-layer with surface density of about 2 x 10 exp 14/sq cm. Passivation of the surface was done by steam oxidation of a nominally undoped 1.5 nm Si cap layer. The UV quantum efficiency was found to be uniform and stable with respect to thermal cycling and illumination conditions.

Ultrafast Nonlinear Signal Processing in Silicon Waveguides

DEFF Research Database (Denmark)

Oxenløwe, Leif Katsuo; Mulvad, Hans Christian Hansen; Hu, Hao

2012-01-01

We describe recent demonstrations of exploiting highly nonlinear silicon waveguides for ultrafast optical signal processing. We describe wavelength conversion and serial-to-parallel conversion of 640 Gbit/s data signals and 1.28 Tbit/s demultiplexing and all-optical sampling.......We describe recent demonstrations of exploiting highly nonlinear silicon waveguides for ultrafast optical signal processing. We describe wavelength conversion and serial-to-parallel conversion of 640 Gbit/s data signals and 1.28 Tbit/s demultiplexing and all-optical sampling....

Linear signal processing using silicon micro-ring resonators

DEFF Research Database (Denmark)

Peucheret, Christophe; Ding, Yunhong; Ou, Haiyan

2012-01-01

We review our recent achievements on the use of silicon micro-ring resonators for linear optical signal processing applications, including modulation format conversion, phase-to-intensity modulation conversion and waveform shaping.......We review our recent achievements on the use of silicon micro-ring resonators for linear optical signal processing applications, including modulation format conversion, phase-to-intensity modulation conversion and waveform shaping....

Space and military radiation effects in silicon-on-insulator devices

International Nuclear Information System (INIS)

Schwank, J.R.

1996-09-01

Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

Processing of poly-Si electrodes for charge-coupled devices

Energy Technology Data Exchange (ETDEWEB)

Sherohman, J.W.; Cook, F.D.

1978-12-06

A technique has been developed to fabricate poly-Si electrodes for charge-coupled devices. By controlling the microstructure of a poly-Si film, an anisotropic etchant was selected to provide essentially uniform electrode width dimensions. The electrode widths have only a 6% variation for the majority of the devices over the area of a 2 inch silicon wafer.

Tin (Sn) - An Unlikely Ally to Extend Moore's Law for Silicon CMOS?

KAUST Repository

Hussain, Aftab M.

2012-12-01

There has been an exponential increase in the performance of silicon based semiconductor devices in the past few decades. This improvement has mainly been due to dimensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel material for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by diffusion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material.

Hybrid Integrated Platforms for Silicon Photonics

Directory of Open Access Journals (Sweden)

John E. Bowers

2010-03-01

Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

STM-excited luminescence of porous and spark-processed silicon

International Nuclear Information System (INIS)

Andrienko, I.; Kuznetsov, V.; Yuan, J.; Haneman, D.

1998-01-01

Full text: Scanning tunneling microscopy (STM) permits highly local electronic excitation of light emission (LE) from the surface of silicon. Measuring STM LE, one can study simultaneously both the topography and the luminescence properties of areas down to nm dimensions and thus make conclusions about the luminescence mechanism of the material. We have built an STM spectroscopy system which allows measurement of spectra of visible light emitted from areas as small as 13 x 13 nm 2 (porous silicon) and 10 x 10 nm 2 (spark-processed silicon). Porous silicon shows a broad emission band centered at 630 nm, and spark-processed silicon, one at 690 nm. The STM LE spectra of spark-processed silicon obtained for the first time. We have found that visible light is emitted only from areas containing nanometer-scale structures down to around 2 nm in diameter. STM LE occurs under negative bias voltage applied to the tip, i.e. when electrons are injected into the sample. Other workers used p-type silicon for the sample preparations, but it has been found that STM LE can be induced also from n-type silicon. Furthermore, we have shown that STM LE spectra can be resolved using much lover voltages and tunneling currents: -(7-9) V and 25 - 50 nA vs -(25-50) V and 100 nA. To consider different excitation mechanisms, the STM LE measurements are compared with photoluminescence and electroluminescence spectra of similar samples. We suggest that excitation of individual quantum confinement structures has been observed

Improved luminescence properties of nanocrystalline silicon based electroluminescent device by annealing

International Nuclear Information System (INIS)

Sato, Keisuke; Hirakuri, Kenji

2006-01-01

We report an annealing effect on electrical and luminescence properties of a red electroluminescent device consisting of nanocrystalline silicon (nc-Si). The red luminescence was generated by flowing the forward current into the device at a low threshold direct current (DC) forward voltage with a rise of annealing temperature up to 500 deg. C. Moreover, the luminescence of the device annealed at 500 deg. C was more intense than that of the device annealed at 200 deg. C or less under the same forward current density, because of the injection of a large quantity of carriers to the radiative recombination centers at the nc-Si surface vicinity. These were attained by a low resistivity of indium tin oxide (ITO) electrode and good contact at the ITO electrode/luminous layer interface region by the annealing treatment. The above results indicated that the annealing treatment of the device is effective for the realization of high luminance due to the improvement in the injection efficiency of carriers to the radiative recombination centers

Porous silicon structures with high surface area/specific pore size

Science.gov (United States)

Northrup, M.A.; Yu, C.M.; Raley, N.F.

1999-03-16

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gases in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters. 9 figs.

Fabrication of detectors and transistors on high-resistivity silicon

International Nuclear Information System (INIS)

Holland, S.

1988-06-01

A new process for the fabrication of silicon p-i-n diode radiation detectors is described. The utilization of backside gettering in the fabrication process results in the actual physical removal of detrimental impurities from critical device regions. This reduces the sensitivity of detector properties to processing variables while yielding low diode reverse-leakage currents. In addition, gettering permits the use of processing temperatures compatible with integrated-circuit fabrication. P-channel MOSFETs and silicon p-i-n diodes have been fabricated simultaneously on 10 kΩ/centerreverse arrowdot/cm silicon using conventional integrated-circuit processing techniques. 25 refs., 5 figs

Thermoelectric characteristics of Pt-silicide/silicon multi-layer structured p-type silicon

International Nuclear Information System (INIS)

Choi, Wonchul; Jun, Dongseok; Kim, Soojung; Shin, Mincheol; Jang, Moongyu

2015-01-01

Electric and thermoelectric properties of silicide/silicon multi-layer structured devices were investigated with the variation of silicide/silicon heterojunction numbers from 3 to 12 layers. For the fabrication of silicide/silicon multi-layered structure, platinum and silicon layers are repeatedly sputtered on the (100) silicon bulk substrate and rapid thermal annealing is carried out for the silicidation. The manufactured devices show ohmic current–voltage (I–V) characteristics. The Seebeck coefficient of bulk Si is evaluated as 195.8 ± 15.3 μV/K at 300 K, whereas the 12 layered silicide/silicon multi-layer structured device is evaluated as 201.8 ± 9.1 μV/K. As the temperature increases to 400 K, the Seebeck coefficient increases to 237.2 ± 4.7 μV/K and 277.0 ± 1.1 μV/K for bulk and 12 layered devices, respectively. The increase of Seebeck coefficient in multi-layered structure is mainly attributed to the electron filtering effect due to the Schottky barrier at Pt-silicide/silicon interface. At 400 K, the thermal conductivity is reduced by about half of magnitude compared to bulk in multi-layered device which shows the efficient suppression of phonon propagation by using Pt-silicide/silicon hetero-junctions. - Highlights: • Silicide/silicon multi-layer structured is proposed for thermoelectric devices. • Electric and thermoelectric properties with the number of layer are investigated. • An increase of Seebeck coefficient is mainly attributed the Schottky barrier. • Phonon propagation is suppressed with the existence of Schottky barrier. • Thermal conductivity is reduced due to the suppression of phonon propagation

Second-harmonic generation in substoichiometric silicon nitride layers

Science.gov (United States)

Pecora, Emanuele; Capretti, Antonio; Miano, Giovanni; Dal Negro, Luca

2013-03-01

Harmonic generation in optical circuits offers the possibility to integrate wavelength converters, light amplifiers, lasers, and multiple optical signal processing devices with electronic components. Bulk silicon has a negligible second-order nonlinear optical susceptibility owing to its crystal centrosymmetry. Silicon nitride has its place in the microelectronic industry as an insulator and chemical barrier. In this work, we propose to take advantage of silicon excess in silicon nitride to increase the Second Harmonic Generation (SHG) efficiency. Thin films have been grown by reactive magnetron sputtering and their nonlinear optical properties have been studied by femtosecond pumping over a wide range of excitation wavelengths, silicon nitride stoichiometry and thermal processes. We demonstrate SHG in the visible range (375 - 450 nm) using a tunable 150 fs Ti:sapphire laser, and we optimize the SH emission at a silicon excess of 46 at.% demonstrating a maximum SHG efficiency of 4x10-6 in optimized films. Polarization properties, generation efficiency, and the second order nonlinear optical susceptibility are measured for all the investigated samples and discussed in terms of an effective theoretical model. Our findings show that the large nonlinear optical response demonstrated in optimized Si-rich silicon nitride materials can be utilized for the engineering of nonlinear optical functions and devices on a Si chip.

Process Development in the Preparation and Characterization of Silicon Alkoxide From Rice Husk

International Nuclear Information System (INIS)

Khin San Win; Toe Shein; Nyunt Wynn

2011-12-01

The preparation and characterization of silicon alkoxide (silicon isopropoxide) from rice husk char has been studied. In the investigation, four kinds of Myanmar paddies were chemically assayed. Analyses showed the silicon contend varies from 73-92% . Based on the silicon content, the process development in the production of silicon isopropoxide was carried out. In the process development, silicon isopropoxide with a yield of 44.21% was achieved by the direct reaction of isopropanol in situ by silicon tetrachloride, which was directly produced by the chlorination of rice husk char at the high temperature range of 900-1100 C. The novelity of the process was that, silicon isopropoxide was achieved in situ and not by using the old process, where generally isopropanol was reacted with silicon tetrachloride. The physiochemical properties of silicon isopropoxide was confirmed by conventional and modern techniques. In the investigation, the starting materials, silica in the reaction products were characterized, identified and confirmed by modren techniques. Silicon isopropoxide can be a sources of pore silica whereby silicon of 97-99% of purity can be achieved.

Damage-free laser patterning of silicon nitride on textured crystalline silicon using an amorphous silicon etch mask for Ni/Cu plated silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Bailly, Mark S., E-mail: mbailly@asu.edu; Karas, Joseph; Jain, Harsh; Dauksher, William J.; Bowden, Stuart

2016-08-01

We investigate the optimization of laser ablation with a femtosecond laser for direct and indirect removal of SiN{sub x} on alkaline textured c-Si. Our proposed resist-free indirect removal process uses an a-Si:H etch mask and is demonstrated to have a drastically improved surface quality of the laser processed areas when compared to our direct removal process. Scanning electron microscope images of ablated sites show the existence of substantial surface defects for the standard direct removal process, and the reduction of those defects with our proposed process. Opening of SiN{sub x} and SiO{sub x} passivating layers with laser ablation is a promising alternative to the standard screen print and fire process for making contact to Si solar cells. The potential for small contacts from laser openings of dielectrics coupled with the selective deposition of metal from light induced plating allows for high-aspect-ratio metal contacts for front grid metallization. The minimization of defects generated in this process would serve to enhance the performance of the device and provides the motivation for our work. - Highlights: • Direct laser removal of silicon nitride (SiN{sub x}) damages textured silicon. • Direct laser removal of amorphous silicon (a-Si) does not damage textured silicon. • a-Si can be used as a laser patterned etch mask for SiN{sub x}. • Chemically patterned SiN{sub x} sites allow for Ni/Cu plating.

Amorphous silicon crystalline silicon heterojunction solar cells

CERN Document Server

Fahrner, Wolfgang Rainer

2013-01-01

Amorphous Silicon/Crystalline Silicon Solar Cells deals with some typical properties of heterojunction solar cells, such as their history, the properties and the challenges of the cells, some important measurement tools, some simulation programs and a brief survey of the state of the art, aiming to provide an initial framework in this field and serve as a ready reference for all those interested in the subject. This book helps to "fill in the blanks" on heterojunction solar cells. Readers will receive a comprehensive overview of the principles, structures, processing techniques and the current developmental states of the devices. Prof. Dr. Wolfgang R. Fahrner is a professor at the University of Hagen, Germany and Nanchang University, China.

Transfer-less flexible and transparent high-κ/metal gate germanium devices on bulk silicon (100)

KAUST Repository

Nassar, Joanna M.; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2014-01-01

Flexible wearable electronics have been of great interest lately for the development of innovative future technology for various interactive applications in the field of consumer electronics and advanced healthcare, offering the promise of low-cost, lightweight, and multifunctionality. In the pursuit of this trend, high mobility channel materials need to be investigated on a flexible platform, for the development of flexible high performance devices. Germanium (Ge) is one of the most attractive alternatives for silicon (Si) for high-speed computational applications, due its higher hole and electron mobility. Thus, in this work we show a cost effective CMOS compatible process for transforming conventional rigid Ge metal oxide semiconductor capacitors (MOSCAPS) into a mechanically flexible and semi-transparent platform. Devices exhibit outstanding bendability with a bending radius of 0.24 cm, and semi-transparency up to 30 %, varying with respect to the diameter size of the release holes array.

Transfer-less flexible and transparent high-κ/metal gate germanium devices on bulk silicon (100)

KAUST Repository

Nassar, Joanna M.

2014-08-01

Flexible wearable electronics have been of great interest lately for the development of innovative future technology for various interactive applications in the field of consumer electronics and advanced healthcare, offering the promise of low-cost, lightweight, and multifunctionality. In the pursuit of this trend, high mobility channel materials need to be investigated on a flexible platform, for the development of flexible high performance devices. Germanium (Ge) is one of the most attractive alternatives for silicon (Si) for high-speed computational applications, due its higher hole and electron mobility. Thus, in this work we show a cost effective CMOS compatible process for transforming conventional rigid Ge metal oxide semiconductor capacitors (MOSCAPS) into a mechanically flexible and semi-transparent platform. Devices exhibit outstanding bendability with a bending radius of 0.24 cm, and semi-transparency up to 30 %, varying with respect to the diameter size of the release holes array.

Production of Solar Grade (SoG) Silicon by Refining Liquid Metallurgical Grade (MG) Silicon: Final Report, 19 April 2001; FINAL

International Nuclear Information System (INIS)

Khattack, C. P.; Joyce, D. B.; Schmid, F.

2001-01-01

efficiency of 1-cm2 devices made from Cz crystals grown using the new feedstock were 95% as high as those from Cz crystals grown using EG feedstock and were comparable to those we obtained using commercial and lt;111 and gt; Cz wafers. Devices with an efficiency of 7.3% were also made directly on wafers cut from the feedstock that had not gone through a controlled directional solidification. Only a few cells have been processed. Device parameters for this material have not yet been optimized, and additional diagnostic device fabrication, analysis, and verification is under way. The successful B treatment process developed during the program can be used with high-B-doped silicon scrap from the electronics industry thereby making available, for the short term, a new silicon feedstock for an additional 200 MW/year annual production of PV modules. For the future, this approach, when used in an MG silicon production plant, will produce SoG silicon for$7.62/kg, which is less than the goal of$20/kg

Gamma non-ionizing energy loss: Comparison with the damage factor in silicon devices

Science.gov (United States)

El Allam, E.; Inguimbert, C.; Meulenberg, A.; Jorio, A.; Zorkani, I.

2018-03-01

The concept of non-ionizing energy loss (NIEL) has been demonstrated to be a successful approach to describe the displacement damage effects in silicon materials and devices. However, some discrepancies exist in the literature between experimental damage factors and theoretical NIELs. 60Co gamma rays having a low NIEL are an interesting particle source that can be used to validate the NIEL scaling approach. This paper presents different 60Co gamma ray NIEL values for silicon targets. They are compared with the radiation-induced increase in the thermal generation rate of carriers per unit fluence. The differences between the different models, including one using molecular dynamics, are discussed.

Chemical modification of silicon surfaces for the application in soft lithography

Energy Technology Data Exchange (ETDEWEB)

Gilles, S.

2007-05-15

The objective of this work was to chemically modify silicon surfaces by anchoring functional molecules. A major part was devoted to the investigation and improvement of the self-assembly process of organosilanes on oxidized silicon surfaces. The formation of a release agent layer with perfluorinated alkylsilanes was performed by vapor phase deposition. An advanced vapor phase deposition device, called CASINO device, was built to enhance the qualities of the thin films. It is possible to carry out cleaning and silanization in a closed chamber without exposing the samples to air in between. Thereby surface contamination is avoided. Experiments with the new device were performed following examples given in literature. To optimize the silanization process in the CASINO device, it was also planned to apply heat treatment of the sample during or after the deposition process. Surface layers of thiolterminated and of aminoterminated molecules were investigated as adhesive layer for the linkage of metal structures to silicon surfaces, e.g. Shuttle-Transfer Printing with gold crossbar electrodes. First, thiol- and aminoterminated organosilane SAMs were tested as adhesive layers for gold. The surface modified with thiolterminated silane molecules was further examined. Adhesion was promoted only after heat treatment of a thiolmodified silicon substrate with a gold layer on top. (orig.)

Eighth workshop on crystalline silicon solar cell materials and processes: Extended abstracts and papers

Energy Technology Data Exchange (ETDEWEB)

NONE

1998-08-01

The theme of this workshop is Supporting the Transition to World Class Manufacturing. This workshop provides a forum for an informal exchange of information between researchers in the photovoltaic and non-photovoltaic fields on various aspects of impurities and defects in silicon, their dynamics during device processing, and their application in defect engineering. This interaction helps establish a knowledge base that can be used for improving device fabrication processes to enhance solar-cell performance and reduce cell costs. It also provides an excellent opportunity for researchers from industry and universities to recognize mutual needs for future joint research. The workshop format features invited review presentations, panel discussions, and two poster sessions. The poster sessions create an opportunity for both university and industrial researchers to present their latest results and provide a natural forum for extended discussions and technical exchanges.

Method of fabricating porous silicon carbide (SiC)

Science.gov (United States)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

The processing and potential applications of porous silicon

Energy Technology Data Exchange (ETDEWEB)

Syyuan Shieh.

1992-07-01

Stability of a cylindrical pore under the influence of surface energy is important for porous silicon (PS) processing in the integrated circuit industry. Once the zig-zag cylindrical pores of porous silicon or oxidized porous silicon (OPS) are unstable and breakup into rows of isolated spherical pores, oxidation of PS and densification/nitridation of OPS become difficult. Swing to difficulty transport of reactant gas (O{sub 2}, NH{sub 3}) or the trapped gas (for densification of OPS). A first order analysis of the stability of a cylindrical pore or cylinder is considered first. Growth of small sinusoidal perturbations by viscous flow or evaporation/condensation result in dependence of perturbation growth rate on perturbation wavelength. Rapid thermal oxidation (RTO) of porous silicon is proposed as an alternative for the tedious two-step 300 and 800C oxidation process. Transmission electron microscopy, energy dispersive spectroscopy ESCA are used for quality control. Also, rapid thermal nitridation of oxidized porous silicon in ammonia is proposed to enhance OPS resistance to HF solution. Pores breakup of OPS results in a trapped gas problem during densification. Wet helium is proposed as OPS densification ambient gas to shorten densification time. Finally, PS is proposed to be an extrinsic gettering center in silicon wafers. The suppression of oxidation-induced stacking faults is used to demonstrate the gettering ability. Possible mechanism is discussed.

The processing and potential applications of porous silicon

Energy Technology Data Exchange (ETDEWEB)

Shieh, Syyuan [Univ. of California, Berkeley, CA (United States)

1992-07-01

Stability of a cylindrical pore under the influence of surface energy is important for porous silicon (PS) processing in the integrated circuit industry. Once the zig-zag cylindrical pores of porous silicon or oxidized porous silicon (OPS) are unstable and breakup into rows of isolated spherical pores, oxidation of PS and densification/nitridation of OPS become difficult. Swing to difficulty transport of reactant gas (O₂, NH₃) or the trapped gas (for densification of OPS). A first order analysis of the stability of a cylindrical pore or cylinder is considered first. Growth of small sinusoidal perturbations by viscous flow or evaporation/condensation result in dependence of perturbation growth rate on perturbation wavelength. Rapid thermal oxidation (RTO) of porous silicon is proposed as an alternative for the tedious two-step 300 and 800C oxidation process. Transmission electron microscopy, energy dispersive spectroscopy ESCA are used for quality control. Also, rapid thermal nitridation of oxidized porous silicon in ammonia is proposed to enhance OPS resistance to HF solution. Pores breakup of OPS results in a trapped gas problem during densification. Wet helium is proposed as OPS densification ambient gas to shorten densification time. Finally, PS is proposed to be an extrinsic gettering center in silicon wafers. The suppression of oxidation-induced stacking faults is used to demonstrate the gettering ability. Possible mechanism is discussed.

Radio frequency siliconization: An approach to the coating for the future large superconducting fusion devices

International Nuclear Information System (INIS)

Li, J.; Zhao, Y.P.; Wan, B.N.; Gong, X.Z.; Zhen, M.; Gu, X.M.; Zhang, X.D.; Luo, J.R.; Wan, Y.X.; Xie, J.K.; Li, C.F.; Chen, J.L.; Toi, K.; Noda, N.; Watari, T.

2001-01-01

Radio frequency (rf) siliconization has been carried out on the HT-7 superconducting tokamak in the presence of a high magnetic field, which is a try on superconducting tokamaks. Three different procedures of rf siliconization have been tested and a very promising method to produce high quality silicon films was found after comparing the film properties and plasma performance produced by these three different procedures. The Si/C films are amorphous, semitransparent, and homogeneous throughout the layer and adhere firmly to all the substrates. The advantages of silicon atoms as a powerful radiator and a good oxygen getter have been proved. An outstanding merit of rf siliconization to superconducting devices is its fast recovery after a serious degradation of the condition due to the leakage of air to good wall conditions. A wider stable operation region has been obtained and plasma performance is improved immediately after each siliconization due to significant reduction of impurities. Energy confinement time increases more than 50% and particle confinement time increases by a factor of 2. The lifetime of the silicon film is more than 400 standard ohmic heated plasma discharges. Simulation shows that the confinement improvement is due to the reduction of the electron thermal diffusivity in the outer region of the plasma

Nanowire-integrated microporous silicon membrane for continuous fluid transport in micro cooling device

International Nuclear Information System (INIS)

So, Hongyun; Pisano, Albert P.; Cheng, Jim C.

2013-01-01

We report an efficient passive micro pump system combining the physical properties of nanowires and micropores. This nanowire-integrated microporous silicon membrane was created to feed coolant continuously onto the surface of the wick in a micro cooling device to ensure it remains hydrated and in case of dryout, allow for regeneration of the system. The membrane was fabricated by photoelectrochemical etching to form micropores followed by hydrothermal growth of nanowires. This study shows a promising approach to address thermal management challenges for next generation electronic devices with absence of external power

Nonlinear silicon photonics

Science.gov (United States)

Borghi, M.; Castellan, C.; Signorini, S.; Trenti, A.; Pavesi, L.

2017-09-01

Silicon photonics is a technology based on fabricating integrated optical circuits by using the same paradigms as the dominant electronics industry. After twenty years of fervid development, silicon photonics is entering the market with low cost, high performance and mass-manufacturable optical devices. Until now, most silicon photonic devices have been based on linear optical effects, despite the many phenomenologies associated with nonlinear optics in both bulk materials and integrated waveguides. Silicon and silicon-based materials have strong optical nonlinearities which are enhanced in integrated devices by the small cross-section of the high-index contrast silicon waveguides or photonic crystals. Here the photons are made to strongly interact with the medium where they propagate. This is the central argument of nonlinear silicon photonics. It is the aim of this review to describe the state-of-the-art in the field. Starting from the basic nonlinearities in a silicon waveguide or in optical resonator geometries, many phenomena and applications are described—including frequency generation, frequency conversion, frequency-comb generation, supercontinuum generation, soliton formation, temporal imaging and time lensing, Raman lasing, and comb spectroscopy. Emerging quantum photonics applications, such as entangled photon sources, heralded single-photon sources and integrated quantum photonic circuits are also addressed at the end of this review.

Silicon nanowires for ultra-fast and ultrabroadband optical signal processing

DEFF Research Database (Denmark)

Ji, Hua; Hu, Hao; Pu, Minhao

2015-01-01

In this paper, we present recent research on silicon nanowires for ultra-fast and ultra-broadband optical signal processing at DTU Fotonik. The advantages and limitations of using silicon nanowires for optical signal processing are revealed through experimental demonstrations of various optical...

Porous silicon technology for integrated microsystems

Science.gov (United States)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially

Silicon light-emitting diodes and lasers photon breeding devices using dressed photons

CERN Document Server

Ohtsu, Motoichi

2016-01-01

This book focuses on a novel phenomenon named photon breeding. It is applied to realizing light-emitting diodes and lasers made of indirect-transition-type silicon bulk crystals in which the light-emission principle is based on dressed photons. After presenting physical pictures of dressed photons and dressed-photon phonons, the principle of light emission by using dressed-photon phonons is reviewed. A novel phenomenon named photon breeding is also reviewed. Next, the fabrication and operation of light emitting diodes and lasers are described The role of coherent phonons in these devices is discussed. Finally, light-emitting diodes using other relevant crystals are described and other relevant devices are also reviewed.

Promising silicones modified with cationic biocides for the development of antimicrobial medical devices.

Science.gov (United States)

Ghamrawi, Sarah; Bouchara, Jean-Philippe; Tarasyuk, Oksana; Rogalsky, Sergiy; Lyoshina, Lyudmila; Bulko, Olga; Bardeau, Jean-François

2017-06-01

We have tested silicones containing 2% or 5% of the cationic biocides polyhexamethylene guanidine dodecylbenzenesulfonate (PHMG-DBS), 1-octyl-3-methylimidazolium tetrafluoroborate (OMIM-BF 4 ) or 1-dodecyl-3-methylimidazolium tetrafluoroborate (DMIM-BF 4 ) against the major relevant bacterial and yeast species in health care-associated infections (HCAI). Study conducted according to the international standard ISO 22196 revealed that silicones containing 2% or 5% DMIM-BF 4 or 5% PHMG-DBS presented the highest antimicrobial activity, leading to a logarithmic growth reduction of 3.03 to 6.46 and 3.65 to 4.85 depending on the bacterial or fungal species. Heat-pretreated silicones containing 2% DMIM-BF 4 kept a high activity, with at least a 3-log reduction in bacterial growth, except against P. aeruginosa where there was only a 1.1-log reduction. After 33days, the release ratio of cationic biocide from silicone films containing 5% of DMIM-BF 4 was found to be 5.6% in pure water and 1.9% in physiological saline solution, respectively. No leaching of PHMG-DBS polymeric biocide was detected under the same conditions. These results demonstrate unambiguously that silicones containing 2% DMIM-BF 4 or 5% PHMG-DBS present high antimicrobial activity, as well as high leaching resistance and therefore may be good candidates for the development of safer medical devices. Copyright © 2017 Elsevier B.V. All rights reserved.

Silicon radiation detectors: materials and applications

International Nuclear Information System (INIS)

Walton, J.T.; Haller, E.E.

1982-10-01

Silicon nuclear radiation detectors are available today in a large variety of sizes and types. This profusion has been made possible by the ever increasing quality and diameter silicon single crystals, new processing technologies and techniques, and innovative detector design. The salient characteristics of the four basic detector groups, diffused junction, ion implanted, surface barrier, and lithium drift are reviewed along with the silicon crystal requirements. Results of crystal imperfections detected by lithium ion compensation are presented. Processing technologies and techniques are described. Two recent novel position-sensitive detector designs are discussed - one in high-energy particle track reconstruction and the other in x-ray angiography. The unique experimental results obtained with these devices are presented

Design Procedure and Fabrication of Reproducible Silicon Vernier Devices for High-Performance Refractive Index Sensing.

Science.gov (United States)

Troia, Benedetto; Khokhar, Ali Z; Nedeljkovic, Milos; Reynolds, Scott A; Hu, Youfang; Mashanovich, Goran Z; Passaro, Vittorio M N

2015-06-10

In this paper, we propose a generalized procedure for the design of integrated Vernier devices for high performance chemical and biochemical sensing. In particular, we demonstrate the accurate control of the most critical design and fabrication parameters of silicon-on-insulator cascade-coupled racetrack resonators operating in the second regime of the Vernier effect, around 1.55 μm. The experimental implementation of our design strategies has allowed a rigorous and reliable investigation of the influence of racetrack resonator and directional coupler dimensions as well as of waveguide process variability on the operation of Vernier devices. Figures of merit of our Vernier architectures have been measured experimentally, evidencing a high reproducibility and a very good agreement with the theoretical predictions, as also confirmed by relative errors even lower than 1%. Finally, a Vernier gain as high as 30.3, average insertion loss of 2.1 dB and extinction ratio up to 30 dB have been achieved.

Silicon Solar Cell Process Development, Fabrication and Analysis, Phase 1

Science.gov (United States)

Yoo, H. I.; Iles, P. A.; Tanner, D. P.

1979-01-01

Solar cells from RTR ribbons, EFG (RF and RH) ribbons, dendritic webs, Silso wafers, cast silicon by HEM, silicon on ceramic, and continuous Czochralski ingots were fabricated using a standard process typical of those used currently in the silicon solar cell industry. Back surface field (BSF) processing and other process modifications were included to give preliminary indications of possible improved performance. The parameters measured included open circuit voltage, short circuit current, curve fill factor, and conversion efficiency (all taken under AM0 illumination). Also measured for typical cells were spectral response, dark I-V characteristics, minority carrier diffusion length, and photoresponse by fine light spot scanning. the results were compared to the properties of cells made from conventional single crystalline Czochralski silicon with an emphasis on statistical evaluation. Limited efforts were made to identify growth defects which will influence solar cell performance.

Device and material characterization and analytic modeling of amorphous silicon thin film transistors

Science.gov (United States)

Slade, Holly Claudia

Hydrogenated amorphous silicon thin film transistors (TFTs) are now well-established as switching elements for a variety of applications in the lucrative electronics market, such as active matrix liquid crystal displays, two-dimensional imagers, and position-sensitive radiation detectors. These applications necessitate the development of accurate characterization and simulation tools. The main goal of this work is the development of a semi- empirical, analytical model for the DC and AC operation of an amorphous silicon TFT for use in a manufacturing facility to improve yield and maintain process control. The model is physically-based, in order that the parameters scale with gate length and can be easily related back to the material and device properties. To accomplish this, extensive experimental data and 2D simulations are used to observe and quantify non- crystalline effects in the TFTs. In particular, due to the disorder in the amorphous network, localized energy states exist throughout the band gap and affect all regimes of TFT operation. These localized states trap most of the free charge, causing a gate-bias-dependent field effect mobility above threshold, a power-law dependence of the current on gate bias below threshold, very low leakage currents, and severe frequency dispersion of the TFT gate capacitance. Additional investigations of TFT instabilities reveal the importance of changes in the density of states and/or back channel conduction due to bias and thermal stress. In the above threshold regime, the model is similar to the crystalline MOSFET model, considering the drift component of free charge. This approach uses the field effect mobility to take into account the trap states and must utilize the correct definition of threshold voltage. In the below threshold regime, the density of deep states is taken into account. The leakage current is modeled empirically, and the parameters are temperature dependent to 150oC. The capacitance of the TFT can be

Integrated silicon optoelectronics

CERN Document Server

Zimmermann, Horst

2000-01-01

'Integrated Silicon Optoelectronics'assembles optoelectronics and microelectronics The book concentrates on silicon as the major basis of modern semiconductor devices and circuits Starting from the basics of optical emission and absorption and from the device physics of photodetectors, the aspects of the integration of photodetectors in modern bipolar, CMOS, and BiCMOS technologies are discussed Detailed descriptions of fabrication technologies and applications of optoelectronic integrated circuits are included The book, furthermore, contains a review of the state of research on eagerly expected silicon light emitters In order to cover the topic of the book comprehensively, integrated waveguides, gratings, and optoelectronic power devices are included in addition Numerous elaborate illustrations promote an easy comprehension 'Integrated Silicon Optoelectronics'will be of value to engineers, physicists, and scientists in industry and at universities The book is also recommendable for graduate students speciali...

Characterization of 10 μm thick porous silicon dioxide obtained by complex oxidation process for RF application

International Nuclear Information System (INIS)

Park, Jeong-Yong; Lee, Jong-Hyun

2003-01-01

This paper proposes a 10 μm thick oxide layer structure, which can be used as a substrate for RF circuits. The structure has been fabricated by anodic reaction and complex oxidation, which is a combined process of low temperature thermal oxidation (500 deg. C, for 1 h at H 2 O/O 2 ) and a rapid thermal oxidation (RTO) process (1050 deg. C, for 1 min). The electrical characteristics of oxidized porous silicon layer (OPSL) were almost the same as those of standard thermal silicon dioxide. The leakage current through the OPSL of 10 μm was about 100-500 pA in the range of 0-50 V. The average value of breakdown field was about 3.9 MV cm -1 . From the X-ray photo-electron spectroscopy (XPS) analysis, surface and internal oxide films of OPSL, prepared by complex process were confirmed to be completely oxidized and also the role of RTO process was important for the densification of porous silicon layer (PSL) oxidized at a lower temperature. For the RF-test of Si substrate with thick silicon dioxide layer, we have fabricated high performance passive devices such as coplanar waveguide (CPW) on OPSL substrate. The insertion loss of CPW on OPSL prepared by complex oxidation process was -0.39 dB at 4 GHz and similar to that of CPW on OPSL prepared by a temperature of 1050 deg. C (1 h at H 2 O/O 2 ). Also the return loss of CPW on OPSL prepared by complex oxidation process was -23 dB at 10 GHz, which is similar to that of CPW on OPSL prepared by high temperature

10th Workshop on Crystalline Silicon Solar Cell Materials and Processes: Extended Abstracts and Papers from the Workshop, Copper Mountain Resort; August 14-16, 2000

Energy Technology Data Exchange (ETDEWEB)

Sopori, B.L.; Gee, J.; Kalejs, J.; Saitoh, R.; Stavola, M.; Swanson, D.; Tan, T.; Weber, E.; Werner, J.

2000-08-11

The 10th Workshop provided a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and non-photovoltaic fields. Discussions included the various aspects of impurities and defects in silicon-their properties, the dynamics during device processing, and their application for developing low-cost processes for manufacturing high-efficiency silicon solar cells. Sessions and panel discussions also reviewed thin-film crystalline-silicon PV, advanced cell structures, new processes and process characterization techniques, and future manufacturing requirements to meet the ambitious expansion goals described in the recently released US PV Industry Roadmap. The Workshop also provided an excellent opportunity for researchers in private industry and at universities to recognize a mutual need for future collaborative research. The three-day workshop consisted of presentations by invited speakers, followed by discussion sessions. In addition, there was two poster sessions presenting the latest research and development results. The subjects discussed included: solar cell processing, light-induced degradation, gettering and passivation, crystalline silicon growth, thin-film silicon solar cells, and impurities and defects. Two special sessions featured at this workshop: advanced metallization and interconnections, and characterization methods.

Silicon germanium mask for deep silicon etching

KAUST Repository

Serry, Mohamed

2014-07-29

Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF.sub.6/O.sub.2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from -80 degrees Celsius to -140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.

Silicon germanium mask for deep silicon etching

KAUST Repository

Serry, Mohamed; Rubin, Andrew; Refaat, Mohamed; Sedky, Sherif; Abdo, Mohammad

2014-01-01

Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF.sub.6/O.sub.2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from -80 degrees Celsius to -140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.

Doping of silicon carbide by ion implantation

International Nuclear Information System (INIS)

Gimbert, J.

1999-01-01

It appeared that in some fields, as the hostile environments (high temperature or irradiation), the silicon compounds showed limitations resulting from the electrical and mechanical properties. Doping of 4H and 6H silicon carbide by ion implantation is studied from a physicochemical and electrical point of view. It is necessary to obtain n-type and p-type material to realize high power and/or high frequency devices, such as MESFETs and Schottky diodes. First, physical and electrical properties of silicon carbide are presented and the interest of developing a process technology on this material is emphasised. Then, physical characteristics of ion implantation and particularly classical dopant implantation, such as nitrogen, for n-type doping, and aluminium and boron, for p-type doping are described. Results with these dopants are presented and analysed. Optimal conditions are extracted from these experiences so as to obtain a good crystal quality and a surface state allowing device fabrication. Electrical conduction is then described in the 4H and 6H-SiC polytypes. Freezing of free carriers and scattering processes are described. Electrical measurements are carried out using Hall effect on Van der Panw test patterns, and 4 point probe method are used to draw the type of the material, free carrier concentrations, resistivity and mobility of the implanted doped layers. These results are commented and compared to the theoretical analysis. The influence of the technological process on electrical conduction is studied in view of fabricating implanted silicon carbide devices. (author)

Assessment on thermoelectric power factor in silicon nanowire networks

Energy Technology Data Exchange (ETDEWEB)

Lohn, Andrew J.; Kobayashi, Nobuhiko P. [Baskin School of Engineering, University of California Santa Cruz, CA (United States); Nanostructured Energy Conversion Technology and Research (NECTAR), Advanced Studies Laboratories, University of California Santa Cruz, NASA Ames Research Center, Moffett Field, CA (United States); Coleman, Elane; Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)

2012-01-15

Thermoelectric devices based on three-dimensional networks of highly interconnected silicon nanowires were fabricated and the parameters that contribute to the power factor, namely the Seebeck coefficient and electrical conductivity were assessed. The large area (2 cm x 2 cm) devices were fabricated at low cost utilizing a highly scalable process involving silicon nanowires grown on steel substrates. Temperature dependence of the Seebeck coefficient was found to be weak over the range of 20-80 C at approximately -400 {mu}V/K for unintentionally doped devices and {+-}50 {mu}V/K for p-type and n-type devices, respectively. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

An investigation into the use of large area silicon semiconductors in microwave systems

International Nuclear Information System (INIS)

Holliday, H.R.

1999-09-01

Semiconductor microwave devices are usually manufactured using micron or sub-micron geometries. The equipment needed for these techniques has a high capital cost and demands high overheads. The material traditionally processed for microwave applications is gallium arsenide but during the period of this investigation a move towards the use of silicon and silicon germanium has emerged. This study, which is essentially practical, covers a range of new ideas for components using large area silicon devices. In the course of the study considerable progress has also been made in the understanding of the behaviour of silicon at microwave frequencies, and some of the initial Concepts were shown to be invalid. An accurate determination of the dielectric constant of silicon has been made using quasi optical techniques at microwave frequencies. The fabrication techniques described originate from methods used at Q-par Angus to manufacture large area silicon nuclear radiation detectors. Developed at the University of Birmingham, these are 'wet chemistry' methods that preclude the need for diffusion or other conventional semiconductor processing techniques. Novel microwave components have been developed using these techniques. These include an optically controlled attenuator with multioctave bandwidth and good dynamic range; window devices to reduce the radar cross section of microwave antennas; and microwave cavity devices including a variable-Q cavity. Concepts for millimeter wave filters are discussed, as are areas for further research. During the attenuator study Wheeler's equations have been extended to cover truncated microstrip. It was observed at an early stage in the work that optical excitation was very effective as a method of controlling the devices. This fits well with current trends in electro-optical devices. The piezo resistance effect in silicon has been briefly investigated and a mechanical attenuator exploiting this effect has been developed. (author)

Predicting the valley physics of silicon quantum dots directly from a device layout

Science.gov (United States)

Gamble, John King; Harvey-Collard, Patrick; Jacobson, N. Tobias; Bacewski, Andrew D.; Nielsen, Erik; Montaño, Inès; Rudolph, Martin; Carroll, Malcolm S.; Muller, Richard P.

Qubits made from electrostatically-defined quantum dots in Si-based systems are excellent candidates for quantum information processing applications. However, the multi-valley structure of silicon's band structure provides additional challenges for the few-electron physics critical to qubit manipulation. Here, we present a theory for valley physics that is predictive, in that we take as input the real physical device geometry and experimental voltage operation schedule, and with minimal approximation compute the resulting valley physics. We present both effective mass theory and atomistic tight-binding calculations for two distinct metal-oxide-semiconductor (MOS) quantum dot systems, directly comparing them to experimental measurements of the valley splitting. We conclude by assessing these detailed simulations' utility for engineering desired valley physics in future devices. Sandia is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the US Department of Energy's National Nuclear Security Administration under Contract No. DE-AC04-94AL85000. The authors gratefully acknowledge support from the Sandia National Laboratories Truman Fellowship Program, which is funded by the Laboratory Directed Research and Development (LDRD) Program.

Optoelectronic properties of Black-Silicon generated through inductively coupled plasma (ICP) processing for crystalline silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Hirsch, Jens, E-mail: J.Hirsch@emw.hs-anhalt.de [Anhalt University of Applied Sciences, Faculty EMW, Bernburger Str. 55, DE-06366 Köthen (Germany); Fraunhofer Center for Silicon Photovoltaics CSP, Otto-Eißfeldt-Str. 12, DE-06120 Halle (Saale) (Germany); Gaudig, Maria; Bernhard, Norbert [Anhalt University of Applied Sciences, Faculty EMW, Bernburger Str. 55, DE-06366 Köthen (Germany); Lausch, Dominik [Fraunhofer Center for Silicon Photovoltaics CSP, Otto-Eißfeldt-Str. 12, DE-06120 Halle (Saale) (Germany)

2016-06-30

Highlights: • Fabrication of black silicon through inductively coupled plasma (ICP) processing. • Suppressed formation a self-bias and therefore a reduced ion bombardment of the silicon sample. • Reduction of the average hemispherical reflection between 300 and 1120 nm up to 8% within 5 min ICP process time. • Reflection is almost independent of the angle of incidence up to 60°. • 2.5 ms effective lifetime at 10{sup 15} cm{sup −3} MCD after ALD Al{sub 2}O{sub 3} surface passivation. - Abstract: The optoelectronic properties of maskless inductively coupled plasma (ICP) generated black silicon through SF{sub 6} and O{sub 2} are analyzed by using reflection measurements, scanning electron microscopy (SEM) and quasi steady state photoconductivity (QSSPC). The results are discussed and compared to capacitively coupled plasma (CCP) and industrial standard wet chemical textures. The ICP process forms parabolic like surface structures in a scale of 500 nm. This surface structure reduces the average hemispherical reflection between 300 and 1120 nm up to 8%. Additionally, the ICP texture shows a weak increase of the hemispherical reflection under tilted angles of incidence up to 60°. Furthermore, we report that the ICP process is independent of the crystal orientation and the surface roughness. This allows the texturing of monocrystalline, multicrystalline and kerf-less wafers using the same parameter set. The ICP generation of black silicon does not apply a self-bias on the silicon sample. Therefore, the silicon sample is exposed to a reduced ion bombardment, which reduces the plasma induced surface damage. This leads to an enhancement of the effective charge carrier lifetime up to 2.5 ms at 10{sup 15} cm{sup −3} minority carrier density (MCD) after an atomic layer deposition (ALD) with Al{sub 2}O{sub 3}. Since excellent etch results were obtained already after 4 min process time, we conclude that the ICP generation of black silicon is a promising technique

Process for making silicon

Science.gov (United States)

Levin, Harry (Inventor)

1987-01-01

A reactor apparatus (10) adapted for continuously producing molten, solar grade purity elemental silicon by thermal reaction of a suitable precursor gas, such as silane (SiH.sub.4), is disclosed. The reactor apparatus (10) includes an elongated reactor body (32) having graphite or carbon walls which are heated to a temperature exceeding the melting temperature of silicon. The precursor gas enters the reactor body (32) through an efficiently cooled inlet tube assembly (22) and a relatively thin carbon or graphite septum (44). The septum (44), being in contact on one side with the cooled inlet (22) and the heated interior of the reactor (32) on the other side, provides a sharp temperature gradient for the precursor gas entering the reactor (32) and renders the operation of the inlet tube assembly (22) substantially free of clogging. The precursor gas flows in the reactor (32) in a substantially smooth, substantially axial manner. Liquid silicon formed in the initial stages of the thermal reaction reacts with the graphite or carbon walls to provide a silicon carbide coating on the walls. The silicon carbide coated reactor is highly adapted for prolonged use for production of highly pure solar grade silicon. Liquid silicon (20) produced in the reactor apparatus (10) may be used directly in a Czochralski or other crystal shaping equipment.

Strained Silicon Photonics

Directory of Open Access Journals (Sweden)

Ralf B. Wehrspohn

2012-05-01

Full Text Available A review of recent progress in the field of strained silicon photonics is presented. The application of strain to waveguide and photonic crystal structures can be used to alter the linear and nonlinear optical properties of these devices. Here, methods for the fabrication of strained devices are summarized and recent examples of linear and nonlinear optical devices are discussed. Furthermore, the relation between strain and the enhancement of the second order nonlinear susceptibility is investigated, which may enable the construction of optically active photonic devices made of silicon.

Development of the external cooling device of increase the productivity of neutron-transmutation-doped silicon semiconductor (NTD-Si) (Joint research)

International Nuclear Information System (INIS)

Hirose, Akira; Wada, Shigeru; Sasajima, Fumio; Kusunoki, Tsuyoshi; Kameyama, Iwao; Aizawa, Ryouji; Kikuchi, Naoyuki

2007-01-01

Neutron-Transmutation-Doped Silicon Semiconductor (hereinafter referred as 'NTD-Si') is the best semiconductor for the power device. The needs of NTD-Si increase recently in proportion to the popularization of hybrid-cars. A fission research reactor, which is a steady state neutron source, is being expected as the best device to meet the needs. So far, we have reconsidered the existing approach which is employed for NTD-Si production works at the research reactors JRR-3, JRR-4 and JMTR of JAEA so as to meet the needs. As one of the effective measures, we found out that the productivity can be increased by incorporating a new device to cool down radioactivity of irradiated silicon ingots at the place outside the main stream from the loading of silicon ingots to the withdrawal of irradiated ingots to the existing JRR-3 Uniformity Irradiation System. Consequently, we developed and installed the device (hereinafter referred as 'external cooling device'). After an ingot was irradiated once, it is turned over manually and irradiated again in order to irradiate the ingot uniformly. With the conventional system, it was necessary to wait the radioactivity of ingot decrease less than the permissible level with holding the ingot in the irradiation equipment. It was effective to shorten the waiting period by using an external cooling device for production increase of NTD-Si. It is expected that the productivity of NTD-Si will be increased by using the external cooling device. This report mentions the design of the external cooling device and verification between its design specifications and the performance of the device completed. (author)

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

Science.gov (United States)

Gowda, Srivardhan Shivappa

Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was

Back-contacted back-junction silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Mangersnes, Krister

2010-10-15

Conventional silicon solar cells have a front-side contacted emitter. Back-contacted back-junction (BC-BJ) silicon solar cells, on the other hand, have both the complete metallization and the active diffused regions of both polarities on the backside. World-record efficiencies have already been demonstrated for this type of cell design in production, both on cell and module level. However, the production of these cells is both complex and costly, and a further cost reduction in fabrication is needed to make electricity from BC-BJ silicon solar cells cost-competitive with electricity on the grid ('grid-parity'). During the work with this thesis, we have investigated several important issues regarding BC-BJ silicon solar cells. The aim has been to reduce production cost and complexity while at the same time maintaining, or increasing, the already high conversion efficiencies demonstrated elsewhere. This has been pursued through experimental work as well as through numerical simulations and modeling. Six papers are appended to this thesis, two of which are still under review in scientific journals. In addition, two patents have been filed based on the work presented herein. Experimentally, we have focused on investigating and optimizing single, central processing steps. A laser has been the key processing tool during most of the work. We have used the same laser both to structure the backside of the cell and to make holes in a double-layer of passivating amorphous silicon and silicon oxide, where the holes were opened with the aim of making local contact to the underlying silicon. The processes developed have the possibility of using a relatively cheap and industrially proven laser and obtain results better than most state-of-the-art laser technologies. During the work with the laser, we also developed a thermodynamic model that was able to predict the outcome from laser interaction with amorphous and crystalline silicon. Alongside the experimental work, we

Materials issues in silicon integrated circuit processing

International Nuclear Information System (INIS)

Wittmer, M.; Stimmell, J.; Strathman, M.

1986-01-01

The symposium on ''Materials Issues in Integrated Circuit Processing'' sought to bring together all of the materials issued pertinent to modern integrated circuit processing. The inherent properties of the materials are becoming an important concern in integrated circuit manufacturing and accordingly research in materials science is vital for the successful implementation of modern integrated circuit technology. The session on Silicon Materials Science revealed the advanced stage of knowledge which topics such as point defects, intrinsic and extrinsic gettering and diffusion kinetics have achieved. Adaption of this knowledge to specific integrated circuit processing technologies is beginning to be addressed. The session on Epitaxy included invited papers on epitaxial insulators and IR detectors. Heteroepitaxy on silicon is receiving great attention and the results presented in this session suggest that 3-d integrated structures are an increasingly realistic possibility. Progress in low temperature silicon epitaxy and epitaxy of thin films with abrupt interfaces was also reported. Diffusion and Ion Implantation were well presented. Regrowth of implant-damaged layers and the nature of the defects which remain after regrowth were discussed in no less than seven papers. Substantial progress was also reported in the understanding of amorphising boron implants and the use of gallium implants for the formation of shallow p/sup +/ -layers

Synthesis of silicon nanocrystals in silane plasmas for nanoelectronics and large area electronic devices

International Nuclear Information System (INIS)

Roca i Cabarrocas, P; Nguyen-Tran, Th; Djeridane, Y; Abramov, A; Johnson, E; Patriarche, G

2007-01-01

The synthesis of silicon nanocrystals in standard radio-frequency glow discharge systems is studied with respect to two main objectives: (i) the production of devices based on quantum size effects associated with the small dimensions of silicon nanocrystals and (ii) the synthesis of polymorphous and polycrystalline silicon films in which silicon nanocrystals are the elementary building blocks. In particular we discuss results on the mechanisms of nanocrystal formation and their transport towards the substrate. We found that silicon nanocrystals can contribute to a significant fraction of deposition (50-70%) and that they can be positively charged. This has a strong influence on their deposition because positively charged nanocrystals will be accelerated towards the substrate with energy of the order of the plasma potential. However, the important parameter with respect to the deposition of charged nanocrystals is not the accelerating voltage but the energy per atom and thus a doubling of the diameter will result in a decrease in the energy per atom by a factor of 8. To leverage this geometrical advantage we propose the use of more electronegative gases, which may have a strong effect on the size and charge distribution of the nanocrystals. This is illustrated in the case of deposition from silicon tetrafluoride plasmas in which we observe low-frequency plasma fluctuations, associated with successive generations of nanocrystals. The contribution of larger nanocrystals to deposition results in a lower energy per deposited atom and thus polycrystalline films

Selective growth of carbon nanotube on silicon substrates

Institute of Scientific and Technical Information of China (English)

ZOU Xiao-ping; H. ABE; T. SHIMIZU; A. ANDO; H. TOKUMOT; ZHU Shen-ming; ZHOU Hao-shen

2006-01-01

The carbon nanotube (CNT) growth of iron oxide-deposited trench-patterns and the locally-ordered CNT arrays on silicon substrate were achieved by simple thermal chemical vapor deposition(STCVD) of ethanol vapor. The CNTs were uniformly synthesized with good selectivity on trench-patterned silicon substrates. This fabrication process is compatible with currently used semiconductor-processing technologies,and the carbon-nanotube fabrication process can be widely applied for the development of electronic devices using carbon-nanotube field emitters as cold cathodes and can revolutionize the area of field-emitting electronic devices. The site-selective growth of CNT from an iron oxide nanoparticle catalyst patterned were also achieved by drying-mediated self-assembly technique. The present method offers a simple and cost-effective method to grow carbon nanotubes with self-assembled patterns.

Periodically poled silicon

Science.gov (United States)

Hon, Nick K.; Tsia, Kevin K.; Solli, Daniel R.; Khurgin, Jacob B.; Jalali, Bahram

2010-02-01

Bulk centrosymmetric silicon lacks second-order optical nonlinearity χ(2) - a foundational component of nonlinear optics. Here, we propose a new class of photonic device which enables χ(2) as well as quasi-phase matching based on periodic stress fields in silicon - periodically-poled silicon (PePSi). This concept adds the periodic poling capability to silicon photonics, and allows the excellent crystal quality and advanced manufacturing capabilities of silicon to be harnessed for devices based on χ(2)) effects. The concept can also be simply achieved by having periodic arrangement of stressed thin films along a silicon waveguide. As an example of the utility, we present simulations showing that mid-wave infrared radiation can be efficiently generated through difference frequency generation from near-infrared with a conversion efficiency of 50% based on χ(2) values measurements for strained silicon reported in the literature [Jacobson et al. Nature 441, 199 (2006)]. The use of PePSi for frequency conversion can also be extended to terahertz generation. With integrated piezoelectric material, dynamically control of χ(2)nonlinearity in PePSi waveguide may also be achieved. The successful realization of PePSi based devices depends on the strength of the stress induced χ(2) in silicon. Presently, there exists a significant discrepancy in the literature between the theoretical and experimentally measured values. We present a simple theoretical model that produces result consistent with prior theoretical works and use this model to identify possible reasons for this discrepancy.

Process research of non-CZ silicon material

Science.gov (United States)

Campbell, R. B.

1984-01-01

Advanced processing techniques for non-CZ silicon sheet material that might improve the cost effectiveness of photovoltaic module production were investigated. Specifically, the simultaneous diffusion of liquid boron and liquid phosphorus organometallic precursors into n-type dendritic silicon web was examined. The simultaneous junction formation method for solar cells was compared with the sequential junction formation method. The electrical resistivity of the n-n and p-n junctions was discussed. Further research activities for this program along with a program documentation schedule are given.

Ultra-Fast Optical Signal Processing in Nonlinear Silicon Waveguides

DEFF Research Database (Denmark)

Oxenløwe, Leif Katsuo; Galili, Michael; Pu, Minhao

2011-01-01

We describe recent demonstrations of exploiting highly nonlinear silicon nanowires for processing Tbit/s optical data signals. We perform demultiplexing and optical waveform sampling of 1.28 Tbit/s and wavelength conversion of 640 Gbit/s data signals.......We describe recent demonstrations of exploiting highly nonlinear silicon nanowires for processing Tbit/s optical data signals. We perform demultiplexing and optical waveform sampling of 1.28 Tbit/s and wavelength conversion of 640 Gbit/s data signals....

Silicon Photonics for Signal Processing of Tbit/s Serial Data Signals

DEFF Research Database (Denmark)

Oxenløwe, Leif Katsuo; Ji, Hua; Galili, Michael

2012-01-01

In this paper, we describe our recent work on signal processing of terabit per second optical serial data signals using pure silicon waveguides. We employ nonlinear optical signal processing in nanoengineered silicon waveguides to perform demultiplexing and optical waveform sampling of 1.28-Tbit/...

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

Science.gov (United States)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Energy and exergy analysis of the silicon production process

International Nuclear Information System (INIS)

Takla, M.; Kamfjord, N.E.; Tveit, Halvard; Kjelstrup, S.

2013-01-01

We used energy and exergy analysis to evaluate two industrial and one ideal (theoretical) production process for silicon. The industrial processes were considered in the absence and presence of power production from waste heat in the off-gas. The theoretical process, with pure reactants and no side-reactions, was used to provide a more realistic upper limit of performance for the others. The energy analysis documented the large thermal energy source in the off-gas system, while the exergy analysis documented the potential for efficiency improvement. We found an exergetic efficiency equal to 0.33 ± 0.02 for the process without power production. The value increased to 0.41 ± 0.03 when waste heat was utilized. For the ideal process, we found an exergetic efficiency of 0.51. Utilization of thermal exergy in an off-gas of 800 °C increased this exergetic efficiency to 0.71. Exergy destructed due to combustion of by-product gases and exergy lost with the furnace off-gas were the largest contributors to the thermodynamic inefficiency of all processes. - Highlights: • The exergetic efficiency for an industrial silicon production process when silicon is the only product was estimated to 0.33. • With additional power production from thermal energy in the off-gas we estimated the exergetic efficiency to 0.41. • The theoretical silicon production process is established as the reference case. • Exergy lost with the off-gas and exergy destructed due to combustion account for roughly 75% of the total losses. • With utilization of the thermal exergy in the off-gas at a temperature of 800 °C the exergetic efficiency was 0.71

Core-shell heterojunction of silicon nanowire arrays and carbon quantum dots for photovoltaic devices and self-driven photodetectors.

Science.gov (United States)

Xie, Chao; Nie, Biao; Zeng, Longhui; Liang, Feng-Xia; Wang, Ming-Zheng; Luo, Linbao; Feng, Mei; Yu, Yongqiang; Wu, Chun-Yan; Wu, Yucheng; Yu, Shu-Hong

2014-04-22

Silicon nanostructure-based solar cells have lately intrigued intensive interest because of their promising potential in next-generation solar energy conversion devices. Herein, we report a silicon nanowire (SiNW) array/carbon quantum dot (CQD) core-shell heterojunction photovoltaic device by directly coating Ag-assisted chemical-etched SiNW arrays with CQDs. The heterojunction with a barrier height of 0.75 eV exhibited excellent rectifying behavior with a rectification ratio of 10(3) at ±0.8 V in the dark and power conversion efficiency (PCE) as high as 9.10% under AM 1.5G irradiation. It is believed that such a high PCE comes from the improved optical absorption as well as the optimized carrier transfer and collection capability. Furthermore, the heterojunction could function as a high-performance self-driven visible light photodetector operating in a wide switching wavelength with good stability, high sensitivity, and fast response speed. It is expected that the present SiNW array/CQD core-shell heterojunction device could find potential applications in future high-performance optoelectronic devices.

Development of an oxidized porous silicon vacuum microtriode

Energy Technology Data Exchange (ETDEWEB)

Smith, II, Don Deewayne [Texas A & M Univ., College Station, TX (United States)

1994-05-01

In order to realize a high-power microwave amplifier design known as a gigatron, a gated field emission array must be developed that can deliver a high-intensity electron beam at gigahertz frequencies. No existing field emission device meets the requirements for a gigatron cathode. In the present work, a porous silicon-based approach is evaluated. The use of porous silicon reduces the size of a single emitter to the nanometer scale, and a true two-dimensional array geometry can be approached. A wide number of applications for such a device exist in various disciplines. Oxidized porous silicon vacuum diodes were first developed in 1990. No systematic study had been done to characterize the performance of these devices as a function of the process parameters. The author has done the first such study, fabricating diodes from p<100>, p<111>, and n<100> silicon substrates. Anodization current densities from 11 mA/cm² to 151 mA/cm² were used, and Fowler-Nordheim behavior was observed in over 80% of the samples. In order to effectively adapt this technology to mainstream vacuum microelectronic applications, a means of creating a gated triodic structure must be found. No previous attempts had successfully yielded such a device. The author has succeeded in utilizing a novel metallization method to fabricate the first operational oxidized porous silicon vacuum microtriodes, and results are encouraging.

An all-silicon passive optical diode.

Science.gov (United States)

Fan, Li; Wang, Jian; Varghese, Leo T; Shen, Hao; Niu, Ben; Xuan, Yi; Weiner, Andrew M; Qi, Minghao

2012-01-27

A passive optical diode effect would be useful for on-chip optical information processing but has been difficult to achieve. Using a method based on optical nonlinearity, we demonstrate a forward-backward transmission ratio of up to 28 decibels within telecommunication wavelengths. Our device, which uses two silicon rings 5 micrometers in radius, is passive yet maintains optical nonreciprocity for a broad range of input power levels, and it performs equally well even if the backward input power is higher than the forward input. The silicon optical diode is ultracompact and is compatible with current complementary metal-oxide semiconductor processing.

Porous silicon: silicon quantum dots for photonic applications

International Nuclear Information System (INIS)

Pavesi, L.; Guardini, R.

1996-01-01

Porous silicon formation and structure characterization are briefly illustrated. Its luminescence properties rae presented and interpreted on the basis of exciton recombination in quantum dot structures: the trap-controlled hopping mechanism is used to describe the recombination dynamics. Porous silicon application to photonic devices is considered: porous silicon multilayer in general, and micro cavities in particular are described. The present situation in the realization of porous silicon LEDs is considered, and future developments in this field of research are suggested. (author). 30 refs., 30 figs., 13 tabs

Evaluation of selected chemical processes for production of low-cost silicon

Science.gov (United States)

Blocher, J. M., Jr.; Browning, M. F.; Wilson, W. J.; Carmichael, D. C.

1976-01-01

Plant construction costs and manufacturing costs were estimated for the production of solar-grade silicon by the reduction of silicon tetrachloride in a fluidized bed of seed particles, and several modifications of the iodide process using either thermal decomposition on heated filaments (rods) or hydrogen reduction in a fluidized bed of seed particles. Energy consumption data for the zinc reduction process and each of the iodide process options are given and all appear to be acceptable from the standpoint of energy pay back. Information is presented on the experimental zinc reduction of SiCl4 and electrolytic recovery of zinc from ZnCl2. All of the experimental work performed thus far has supported the initial assumption as to technical feasibility of producing semiconductor silicon by the zinc reduction or iodide processes proposed. The results of a more thorough thermodynamic evaluation of the iodination of silicon oxide/carbon mixtures are presented which explain apparent inconsistencies in an earlier cursory examination of the system.

Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

International Nuclear Information System (INIS)

Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

2015-01-01

Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

Recent progress on fabrication of memristor and transistor-based neuromorphic devices for high signal processing speed with low power consumption

Science.gov (United States)

Hadiyawarman; Budiman, Faisal; Goldianto Octensi Hernowo, Detiza; Pandey, Reetu Raj; Tanaka, Hirofumi

2018-03-01

The advanced progress of electronic-based devices for artificial neural networks and recent trends in neuromorphic engineering are discussed in this review. Recent studies indicate that the memristor and transistor are two types of devices that can be implemented as neuromorphic devices. The electrical switching characteristics and physical mechanism of neuromorphic devices based on metal oxide, metal sulfide, silicon, and carbon materials are broadly covered in this review. Moreover, the switching performance comparison of several materials mentioned above are well highlighted, which would be useful for the further development of memristive devices. Recent progress in synaptic devices and the application of a switching device in the learning process is also discussed in this paper.

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

Science.gov (United States)

Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

2018-04-01

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

Fabrication and optical characterization of light trapping silicon nanopore and nanoscrew devices

International Nuclear Information System (INIS)

Jin, Hyunjong; Logan Liu, G

2012-01-01

We have fabricated nanotextured Si substrates that exhibit controllable optical reflection intensities and colors. Si nanopore has a photon trapping nanostructure but has abrupt changes in the index of refraction displaying a darkened specular reflection. Nanoscrew Si shows graded refractive-index photon trapping structures that enable diffuse reflection to be as low as 2.2% over the visible wavelengths. By tuning the 3D nanoscale silicon structure, the optical reflection peak wavelength and intensity are changed in the wavelength range of 300–800 nm, making the surface have different reflectivity and apparent colors. The relation between the surface optical properties with the spatial features of the photon trapping nanostructures is examined. Integration of photon trapping structures with planar Si structure on the same substrate is also demonstrated. The tunable photon trapping silicon structures have potential applications in enhancing the performance of semiconductor photoelectric devices. (paper)

ATLAS Silicon Microstrip Tracker

CERN Document Server

Haefner, Petra; The ATLAS collaboration

2010-01-01

The SemiConductor Tracker (SCT), made up from silicon micro-strip detectors is the key precision tracking device in ATLAS, one of the experiments at CERN LHC. The completed SCT is in very good shape: 99.3% of the SCT strips are operational, noise occupancy and hit efficiency exceed the design specifications. In the talk the current status of the SCT will be reviewed. We will report on the operation of the detector and observed problems, with stress on the sensor and electronics performance. TWEPP Summary In December 2009 the ATLAS experiment at the CERN Large Hadron Collider (LHC) recorded the first proton- proton collisions at a centre-of-mass energy of 900 GeV and this was followed by the unprecedented energy of 7 TeV in March 2010. The SemiConductor Tracker (SCT) is the key precision tracking device in ATLAS, made up from silicon micro-strip detectors processed in the planar p-in-n technology. The signal from the strips is processed in the front-end ASICS ABCD3TA, working in the binary readout mode. Data i...

Small area silicon diffused junction x-ray detectors

International Nuclear Information System (INIS)

Walton, J.T.; Pehl, R.H.; Larsh, A.E.

1981-10-01

The low temperature performance of silicon diffused junction detectors in the measurement of low energy x-rays is reported. The detectors have an area of 0.04 cm 2 and a thickness of 100 μm. The spectral resolutions of these detectors were found to be in close agreement with expected values indicating that the defects introduced by the high temperature processing required in the device fabrication were not deleteriously affecting the detection of low energy x-rays. Device performance over a temperature range of 77 to 150 0 K is given. These detectors were designed to detect low energy x-rays in the presence of minimum ionizing electrons. The successful application of silicon diffused junction technology to x-ray detector fabrication may facilitate the development of other novel silicon x-ray detector designs

Small area silicon diffused junction X-ray detectors

Science.gov (United States)

Walton, J. T.; Pehl, R. H.; Larsh, A. E.

1982-01-01

The low-temperature performance of silicon diffused junction detectors in the measurement of low energy X-rays is reported. The detectors have an area of 0.04 sq cm and a thickness of 100 microns. The spectral resolutions of these detectors were found to be in close agreement with expected values, indicating that the defects introduced by the high-temperature processing required in the device fabrication were not deleteriously affecting the detection of low-energy X-rays. Device performance over a temperature range of 77 K to 150 K is given. These detectors were designed to detect low-energy X-rays in the presence of minimum ionizing electrons. The successful application of silicon-diffused junction technology to X-ray detector fabrication may facilitate the development of other novel silicon X-ray detector designs.

Gate protective device for SOS array

Science.gov (United States)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

A CMOS silicon spin qubit

Science.gov (United States)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

From physics to devices light emissions in silicon from physics to devices

CERN Document Server

Lockwood, David J; Weber, Eicke R; Lockwood, David J

1997-01-01

Since its inception in 1966, the series of numbered volumes known as Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors.The"Willardson and Beer"Series, as it is widely known, has succeeded in publishing numerous landmark volumes and chapters. Not only did many of these volumes make an impact at the time of their publication, but they continue to be well-cited years after their original release. Recently, Professor Eicke R. Weber of the University of California at Berkeley joined as a co-editor of the series. Professor Weber, a well-known expert in the field of semiconductor materials, will further contribute to continuing the series' tradition of publishing timely, highly relevant, and long-impacting volumes. Some of the recent volumes, such as Hydrogen in Semiconductors, Imperfections in III/V Materials, Epitaxial Microstructures, High-Speed Heterostructure Devices,Oxygen in Silicon, and others promise indeed that this traditi...

THz generation from a nanocrystalline silicon-based photoconductive device

International Nuclear Information System (INIS)

Daghestani, N S; Persheyev, S; Cataluna, M A; Rose, M J; Ross, G

2011-01-01

Terahertz generation has been achieved from a photoconductive switch based on hydrogenated nanocrystalline silicon (nc-Si:H), gated by a femtosecond laser. The nc-Si:H samples were produced by a hot wire chemical vapour deposition process, a process with low production costs owing to its higher growth rate and manufacturing simplicity. Although promising ultrafast carrier dynamics of nc-Si have been previously demonstrated, this is the first report on THz generation from a nc-Si:H material

Study of hydrogenated amorphous silicon devices under intense electric field: application to nuclear detection

International Nuclear Information System (INIS)

Ilie, A.

1996-01-01

The goal of this work was the study, development and optimization of hydrogenated amorphous silicon (a-Si:H) devices for use in detection of ionizing radiation in applications connected to the nuclear industry. Thick p-i-n devices, capable of withstanding large electric fields (up to 10 6 V/cm) with small currents (nA/cm 2 ), were proposed and developed. In order to decrease fabrication time, films were made using the 'He diluted' PECVD process and compared to standard a-Si:H films. Aspects connected to specific detector applications as well as to the fundamental physics of a-Si:H were considered: the internal electric field technique, in which the depletion charge was measured as a function of the applied bias voltage; study of the leakage current of p-i-n devices permitted us to demonstrate different regimes: depletion, field-enhanced thermal generation and electronic injection across the p layer. The effect of the electric field on the thermal generation of the carriers was studied considering the Poole-Frenkel and tunneling mechanisms. A model was developed taking under consideration the statistics of the correlated states and electron-phonon coupling. The results suggest that mechanisms not included in the 'standard model' of a Si:h need to be considered, such as defect relaxation, a filed-dependent mobility edge etc...; a new metastable phenomenon, called 'forming', induced by prolonged exposure to a strong electric field, was observed and studied. It is characterized by marked decrease of the leakage current and the detector noise, and increase in the breakdown voltage, as well as an improvement of carrier collection efficiency. This forming process appears to be principally due to an activation of the dopants in the p layer; finally, the capacity of thick p-i-n a Si:H devices to detect ionizing radiation has been evaluated. We show that it is possible, with 20-50 micron thick p-i-n devices, to detect the full spectrum of alpha and beta particles. With an

Micro-Raman spectroscopy as a tool for the characterization of silicon carbide in power semiconductor material processing

Science.gov (United States)

De Biasio, M.; Kraft, M.; Schultz, M.; Goller, B.; Sternig, D.; Esteve, R.; Roesner, M.

2017-05-01

Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

Silicon solar cell - from R and D to production

International Nuclear Information System (INIS)

Akhter, P.

1995-01-01

During last 30 years tremendous research and development efforts have concluded that tech-economically silicon is the most suitable material for the manufacturing of solar cells and a number of achievements have been made in the processing of both the materials nd devices. A number of novel structure have been designed and fabricated. The crystalline silicon technology has now become mature enough and is ready to take off from R/D laboratories to large scale fabrication. At laboratory scale the performance of monocrystalline silicon cells have already reached very close to the theoretical value. However the processing cost and efficiency being complimentary, the commercial cells, as a trade off, have to compromise at rather lower efficiencies. Further efforts of lowering the processing cost of both the material and devices are in progress. At the same time attempts are being made to understand the physics of all those factors that limit the efficiency; develop the technologies to eliminate or optimize such effects to reach limiting efficiency with lowest possible cost. All such factors, along with the development will be discussed. (author)

Integration of mask and silicon metrology in DFM

Science.gov (United States)

Matsuoka, Ryoichi; Mito, Hiroaki; Sugiyama, Akiyuki; Toyoda, Yasutaka

2009-03-01

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based

Towards Ordered Silicon Nanostructures through Self-Assembling Mechanisms and Processes

Directory of Open Access Journals (Sweden)

R. A. Puglisi

2015-01-01

Full Text Available The design and development of innovative architectures for memory storage and energy conversion devices are at the forefront of current research efforts driving us towards a sustainable future. However, issues related to the cost, efficiency, and reliability of current technologies are still severely limiting their overtake of the standard designs. The use of ordered nanostructured silicon is expected to overcome these limitations and push the advancement of the alternative technologies. Specifically, self-assembling of block copolymers has been recognized as a promising and cost-effective approach to organize silicon nanostructures. This work reviews some of the most important findings on block copolymer self-assembling and complements those with the results of new experimental studies. First of all, a quantitative analysis is presented on the ordering and fluctuations expected in the synthesis of silicon nanostructures by using standard synthesis methods like chemical vapour deposition. Then the effects of the several parameters guiding the ordering mechanisms in the block copolymer systems, such as film thickness, molecular weight, annealing conditions, solvent, and substrate topography are discussed. Finally, as a proof of concept, an in-house developed example application to solar cells is presented, based on silicon nanostructures resulting from self-assembling of block copolymers.

Effect of Silicon Nanowire on Crystalline Silicon Solar Cell Characteristics

OpenAIRE

Zahra Ostadmahmoodi Do; Tahereh Fanaei Sheikholeslami; Hassan Azarkish

2016-01-01

Nanowires (NWs) are recently used in several sensor or actuator devices to improve their ordered characteristics. Silicon nanowire (Si NW) is one of the most attractive one-dimensional nanostructures semiconductors because of its unique electrical and optical properties. In this paper, silicon nanowire (Si NW), is synthesized and characterized for application in photovoltaic device. Si NWs are prepared using wet chemical etching method which is commonly used as a simple and low cost method fo...

Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

Science.gov (United States)

Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

2015-02-01

We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

Photonic integration and photonics-electronics convergence on silicon platform

CERN Document Server

Liu, Jifeng; Baba, Toshihiko; Vivien, Laurent; Xu, Dan-Xia

2015-01-01

Silicon photonics technology, which has the DNA of silicon electronics technology, promises to provide a compact photonic integration platform with high integration density, mass-producibility, and excellent cost performance. This technology has been used to develop and to integrate various photonic functions on silicon substrate. Moreover, photonics-electronics convergence based on silicon substrate is now being pursued. Thanks to these features, silicon photonics will have the potential to be a superior technology used in the construction of energy-efficient cost-effective apparatuses for various applications, such as communications, information processing, and sensing. Considering the material characteristics of silicon and difficulties in microfabrication technology, however, silicon by itself is not necessarily an ideal material. For example, silicon is not suitable for light emitting devices because it is an indirect transition material. The resolution and dynamic range of silicon-based interference de...

Behavior of ion-implanted cesium in silicon dioxide films

International Nuclear Information System (INIS)

Fishbein, B.J.

1988-01-01

Charged impurities in silicon dioxide can be used to controllably shift the flatband voltage of metal-oxide-semiconductor devices independently of the substrate doping, the gate oxide thickness and the gate-electrode work function. Cesium is particularly well suited for this purpose because it is immobile in SiO 2 at normal device operating temperatures, and because it can be controllably introduced into oxide films by ion implantation. Cesium is positively charged in silicon dioxide, resulting in a negative flatband voltage shift. Possible applications for cesium technology include solar cells, devices operated at liquid nitrogen temperature, and power devices. The goal of this work has been to characterize as many aspects of cesium behavior in silicon dioxide as are required for practical applications. Accordingly, cesium-ion implantation, cesium diffusion, and cesium electrical activation in SiO 2 were studied over a broad range of processing conditions. The electrical properties of cesium-containing oxides, including current-voltage characteristics, interface trap density, and inversion-layer carrier mobility were examined, and several potential applications for cesium technology have been experimentally demonstrated

Radioactive waste processing device

International Nuclear Information System (INIS)

Inaguma, Masahiko; Takahara, Nobuaki; Hara, Satomi.

1996-01-01

In a processing device for filtering laundry liquid wastes and shower drains incorporated with radioactive materials, a fiber filtration device is disposed and an activated carbon filtration device is also disposed subsequent to the fiber filtration device. In addition, a centrifugal dewatering device is disposed for dewatering spent granular activated carbon in the activated carbon filtration device, and a minute filtering device is disposed for filtering the separated dewatering liquid. Filtrates filtered by the minute filtration device are recovered in a collecting tank. Namely, at first, suspended solid materials in laundry liquid wastes and shower drains are captured, and then, ingredients concerning COD are adsorbed in the activated carbon filtration device. The radioactive liquid wastes of spent granular activated carbon in the activated carbon filtration device are reduced by dewatering them by the centrifugal dewatering device, and then the granular activated carbon is subjected to an additional processing. Further, it is separated by filtration using the minute filtration device and removed as cakes. Since the filtrates are recovered to the collecting tank and filtered again, the water quality of the drains is not degraded. (N.H.)

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

11th Workshop on Crystalline Silicon Solar Cell Materials and Processes, Extended Abstracts and Papers, 19-22 August 2001, Estes Park, Colorado

Energy Technology Data Exchange (ETDEWEB)

Sopori, B.

2001-08-16

The 11th Workshop will provide a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and non-photovoltaic fields. Discussions will include the various aspects of impurities and defects in silicon--their properties, the dynamics during device processing, and their application for developing low-cost processes for manufacturing high-efficiency silicon solar cells. Sessions and panel discussions will review impurities and defects in crystalline-silicon PV, advanced cell structures, new processes and process characterization techniques, and future manufacturing demands. The workshop will emphasize some of the promising new technologies in Si solar cell fabrication that can lower PV energy costs and meet the throughput demands of the future. The three-day workshop will consist of presentations by invited speakers, followed by discussion sessions. Topics to be discussed are: Si Mechanical properties and Wafer Handling, Advanced Topics in PV Fundamentals, Gettering and Passivation, Impurities and Defects, Advanced Emitters, Crystalline Silicon Growth, and Solar Cell Processing. The workshop will also include presentations by NREL subcontractors who will review the highlights of their research during the current subcontract period. In addition, there will be two poster sessions presenting the latest research and development results. Some presentations will address recent technologies in the microelectronics field that may have a direct bearing on PV.

Silicon photonics for multicore fiber communication

DEFF Research Database (Denmark)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

2016-01-01

We review our recent work on silicon photonics for multicore fiber communication, including multicore fiber fan-in/fan-out, multicore fiber switches towards reconfigurable optical add/drop multiplexers. We also present multicore fiber based quantum communication using silicon devices.......We review our recent work on silicon photonics for multicore fiber communication, including multicore fiber fan-in/fan-out, multicore fiber switches towards reconfigurable optical add/drop multiplexers. We also present multicore fiber based quantum communication using silicon devices....

Ion beam figuring of silicon aspheres

Science.gov (United States)

Demmler, Marcel; Zeuner, Michael; Luca, Alfonz; Dunger, Thoralf; Rost, Dirk; Kiontke, Sven; Krüger, Marcus

2011-03-01

Silicon lenses are widely used for infrared applications. Especially for portable devices the size and weight of the optical system are very important factors. The use of aspherical silicon lenses instead of spherical silicon lenses results in a significant reduction of weight and size. The manufacture of silicon lenses is more challenging than the manufacture of standard glass lenses. Typically conventional methods like diamond turning, grinding and polishing are used. However, due to the high hardness of silicon, diamond turning is very difficult and requires a lot of experience. To achieve surfaces of a high quality a polishing step is mandatory within the manufacturing process. Nevertheless, the required surface form accuracy cannot be achieved through the use of conventional polishing methods because of the unpredictable behavior of the polishing tools, which leads to an unstable removal rate. To overcome these disadvantages a method called Ion Beam Figuring can be used to manufacture silicon lenses with high surface form accuracies. The general advantage of the Ion Beam Figuring technology is a contactless polishing process without any aging effects of the tool. Due to this an excellent stability of the removal rate without any mechanical surface damage is achieved. The related physical process - called sputtering - can be applied to any material and is therefore also applicable to materials of high hardness like Silicon (SiC, WC). The process is realized through the commercially available ion beam figuring system IonScan 3D. During the process, the substrate is moved in front of a focused broad ion beam. The local milling rate is controlled via a modulated velocity profile, which is calculated specifically for each surface topology in order to mill the material at the associated positions to the target geometry. The authors will present aspherical silicon lenses with very high surface form accuracies compared to conventionally manufactured lenses.

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

Science.gov (United States)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

Ordered silicon nanostructures for silicon-based photonics devices

Czech Academy of Sciences Publication Activity Database

Fojtík, A.; Valenta, J.; Pelant, Ivan; Kálal, M.; Fiala, P.

2007-01-01

Roč. 5, Suppl. (2007), S250-S253 ISSN 1671-7694 R&D Projects: GA AV ČR IAA1010316 Grant - others:GA MŠk(CZ) ME 933 Institutional research plan: CEZ:AV0Z10100521 Keywords : nanocrystals * silicon * self-assembled monolayers Subject RIV: BM - Solid Matter Physics ; Magnetism

Amorphous silicon passivation for 23.3% laser processed back contact solar cells

Science.gov (United States)

Carstens, Kai; Dahlinger, Morris; Hoffmann, Erik; Zapf-Gottwick, Renate; Werner, Jürgen H.

2017-08-01

This paper presents amorphous silicon deposited at temperatures below 200 °C, leading to an excellent passivation layer for boron doped emitter and phosphorus doped back surface field areas in interdigitated back contact solar cells. A higher deposition temperature degrades the passivation of the boron emitter by an increased hydrogen effusion due to lower silicon hydrogen bond energy, proved by hydrogen effusion measurements. The high boron surface doping in crystalline silicon causes a band bending in the amorphous silicon. Under these conditions, at the interface, the intentionally undoped amorphous silicon becomes p-type conducting, with the consequence of an increased dangling bond defect density. For bulk amorphous silicon this effect is described by the defect pool model. We demonstrate, that the defect pool model is also applicable to the interface between amorphous and crystalline silicon. Our simulation shows the shift of the Fermi energy towards the valence band edge to be more pronounced for high temperature deposited amorphous silicon having a small bandgap. Application of optimized amorphous silicon as passivation layer for the boron doped emitter and phosphorus doped back surface field on the rear side of laser processed back contact solar cells, fabricated using four laser processing steps, yields an efficiency of 23.3%.

Fundamental understanding and development of low-cost, high-efficiency silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

ROHATGI,A.; NARASIMHA,S.; MOSCHER,J.; EBONG,A.; KAMRA,S.; KRYGOWSKI,T.; DOSHI,P.; RISTOW,A.; YELUNDUR,V.; RUBY,DOUGLAS S.

2000-05-01

The overall objectives of this program are (1) to develop rapid and low-cost processes for manufacturing that can improve yield, throughput, and performance of silicon photovoltaic devices, (2) to design and fabricate high-efficiency solar cells on promising low-cost materials, and (3) to improve the fundamental understanding of advanced photovoltaic devices. Several rapid and potentially low-cost technologies are described in this report that were developed and applied toward the fabrication of high-efficiency silicon solar cells.

Process research on non-CZ silicon material

Science.gov (United States)

1982-01-01

High risk, high payoff research areas associated with he process for producing photovoltaic modules using non-CZ sheet material are investigated. All investigations are being performed using dendritic web silicon, but all processes are directly applicable to other ribbon forms of sheet material. The technical feasibility of forming front and back junctions in non-CZ silicon using liquid dopant techniques was determined. Numerous commercially available liquid phosphorus and boron dopant solutions are investigated. Temperature-time profiles to achieve N(+) and P(+) sheet resistivities of 60 + or - 10 and 40 + or - s10 ohms per square centimeter respectively are established. A study of the optimal method of liquid dopant application is performed. The technical feasibility of forming a liquid applied diffusion mask to replace the more costly chemical vapor deposited SiO2 diffusion mask was also determined.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

Science.gov (United States)

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Characterization of Amorphous Silicon Advanced Materials and PV Devices: Final Technical Report, 15 December 2001--31 January 2005

Energy Technology Data Exchange (ETDEWEB)

Taylor, P. C.

2005-11-01

The major objectives of this subcontract have been: (1) understand the microscopic properties of the defects that contribute to the Staebler-Wronski effect to eliminate this effect, (2) perform correlated studies on films and devices made by novel techniques, especially those with promise to improve stability or deposition rates, (3) understand the structural, electronic, and optical properties of films of hydrogenated amorphous silicon (a-Si:H) made on the boundary between the amorphous and microcrystalline phases, (4) search for more stable intrinsic layers of a-Si:H, (5) characterize the important defects, impurities, and metastabilities in the bulk and at surfaces and interfaces in a-Si:H films and devices and in important alloy systems, and (6) make state-of-the-art plasma-enhanced chemical vapor deposition (PECVD) devices out of new, advanced materials, when appropriate. All of these goals are highly relevant to improving photovoltaic devices based on a-Si:H and related alloys. With regard to the first objective, we have identified a paired hydrogen site that may be the defect that stabilizes the silicon dangling bonds formed in the Staebler-Wronski effect.

Label-Free Virus Capture and Release by a Microfluidic Device Integrated with Porous Silicon Nanowire Forest.

Science.gov (United States)

Xia, Yiqiu; Tang, Yi; Yu, Xu; Wan, Yuan; Chen, Yizhu; Lu, Huaguang; Zheng, Si-Yang

2017-02-01

Viral diseases are perpetual threats to human and animal health. Detection and characterization of viral pathogens require accurate, sensitive, and rapid diagnostic assays. For field and clinical samples, the sample preparation procedures limit the ultimate performance and utility of the overall virus diagnostic protocols. This study presents the development of a microfluidic device embedded with porous silicon nanowire (pSiNW) forest for label-free size-based point-of-care virus capture in a continuous curved flow design. The pSiNW forests with specific interwire spacing are synthesized in situ on both bottom and sidewalls of the microchannels in a batch process. With the enhancement effect of Dean flow, this study demonstrates that about 50% H5N2 avian influenza viruses are physically trapped without device clogging. A unique feature of the device is that captured viruses can be released by inducing self-degradation of the pSiNWs in physiological aqueous environment. About 60% of captured viruses can be released within 24 h for virus culture, subsequent molecular diagnosis, and other virus characterization and analyses. This device performs viable, unbiased, and label-free virus isolation and release. It has great potentials for virus discovery, virus isolation and culture, functional studies of virus pathogenicity, transmission, drug screening, and vaccine development. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Dominant rate process of silicon surface etching by hydrogen chloride gas

International Nuclear Information System (INIS)

Habuka, Hitoshi; Suzuki, Takahiro; Yamamoto, Sunao; Nakamura, Akio; Takeuchi, Takashi; Aihara, Masahiko

2005-01-01

Silicon surface etching and its dominant rate process are studied using hydrogen chloride gas in a wide concentration range of 1-100% in ambient hydrogen at atmospheric pressure in a temperature range of 1023-1423 K, linked with the numerical calculation accounting for the transport phenomena and the surface chemical reaction in the entire reactor. The etch rate, the gaseous products and the surface morphology are experimentally evaluated. The dominant rate equation accounting for the first-order successive reactions at silicon surface by hydrogen chloride gas is shown to be valid. The activation energy of the dominant surface process is evaluated to be 1.5 x 10 5 J mol - 1 . The silicon deposition by the gaseous by-product, trichlorosilane, is shown to have a negligible influence on the silicon etch rate

Mechanically flexible optically transparent porous mono-crystalline silicon substrate

KAUST Repository

Rojas, Jhonathan Prieto; Syed, Ahad A.; Hussain, Muhammad Mustafa

2012-01-01

For the first time, we present a simple process to fabricate a thin (≥5μm), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon <100> wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates. © 2012 IEEE.

Enhanced UV photoresponse of KrF-laser-synthesized single-wall carbon nanotubes/n-silicon hybrid photovoltaic devices.

Science.gov (United States)

Le Borgne, V; Gautier, L A; Castrucci, P; Del Gobbo, S; De Crescenzi, M; El Khakani, M A

2012-06-01

We report on the KrF-laser ablation synthesis, purification and photocurrent generation properties of single-wall carbon nanotubes (SWCNTs). The thermally purified SWCNTs are integrated into hybrid photovoltaic (PV) devices by spin-coating them onto n-Si substrates. These novel SWCNTs/n-Si hybrid devices are shown to generate significant photocurrent (PC) over the entire 250-1050 nm light spectrum with external quantum efficiencies (EQE) reaching up to ~23%. Our SWCNTs/n-Si hybrid devices are not only photoactive in the traditional spectral range of Si solar cells, but generate also significant PC in the UV domain (below 400 nm). This wider spectral response is believed to be the result of PC generation from both the SWCNTs themselves and the tremendous number of local p-n junctions created at the nanotubes/Si interface. To assess the prevalence of these two contributions, the EQE spectra and J-V characteristics of these hybrid devices were investigated in both planar and top-down configurations, as a function of SWCNTs' film thickness. A sizable increase in EQE in the near UV with respect to the silicon is observed in both configurations, with a more pronounced UV photoresponse in the planar mode, confirming thereby the role of SWCNTs in the photogeneration process. The PC generation is found to reach its maximum for an optimal the SWCNT film thickness, which is shown to correspond to the best trade-off between lowest electrical resistance and highest optical transparency. Finally, by analyzing the J-V characteristics of our SWCNTs/n-Si devices with an equivalent circuit model, we were able to point out the contribution of the various electrical components involved in the photogeneration process. The SWCNTs-based devices demonstrated here open up the prospect for their use in highly effective photovoltaics and/or UV-light sensors.

Phase-sensitive optical processing in silicon waveguides

DEFF Research Database (Denmark)

Petermann, Klaus; Gajda, A.; Dziallas, Claudia

2015-01-01

Parametric optical signal processing is reviewed for silicon nano-rib-waveguides with a reverse-biased pin-junction. Phase-sensitive parametric amplification with a phase-sensitive extinction of more than 20 dB has been utilized for the regeneration of DPSK signals...

Role of the inversion layer on the charge injection in silicon nanocrystal multilayered light emitting devices

Energy Technology Data Exchange (ETDEWEB)

Tondini, S. [Nanoscience Laboratory, Department of Physics, University of Trento, Via Sommarive 14, 38123 Trento (Italy); Dipartimento di Fisica, Informatica e Matematica, Università di Modena e Reggio Emilia, Via Campi 213/a, 41125 Modena (Italy); Pucker, G. [Advanced Photonics and Photovoltaics Group, Bruno Kessler Foundation, Via Sommarive 18, 38123 Trento (Italy); Pavesi, L. [Nanoscience Laboratory, Department of Physics, University of Trento, Via Sommarive 14, 38123 Trento (Italy)

2016-09-07

The role of the inversion layer on injection and recombination phenomena in light emitting diodes (LEDs) is here studied on a multilayer (ML) structure of silicon nanocrystals (Si-NCs) embedded in SiO{sub 2}. Two Si-NC LEDs, which are similar for the active material but different in the fabrication process, elucidate the role of the non-radiative recombination rates at the ML/substrate interface. By studying current- and capacitance-voltage characteristics as well as electroluminescence spectra and time-resolved electroluminescence under pulsed and alternating bias pumping scheme in both the devices, we are able to ascribe the different experimental results to an efficient or inefficient minority carrier (electron) supply by the p-type substrate in the metal oxide semiconductor LEDs.

Silicon deposition in nanopores using a liquid precursor

Science.gov (United States)

Masuda, Takashi; Tatsuda, Narihito; Yano, Kazuhisa; Shimoda, Tatsuya

2016-11-01

Techniques for depositing silicon into nanosized spaces are vital for the further scaling down of next-generation devices in the semiconductor industry. In this study, we filled silicon into 3.5-nm-diameter nanopores with an aspect ratio of 70 by exploiting thermodynamic behaviour based on the van der Waals energy of vaporized cyclopentasilane (CPS). We originally synthesized CPS as a liquid precursor for semiconducting silicon. Here we used CPS as a gas source in thermal chemical vapour deposition under atmospheric pressure because vaporized CPS can fill nanopores spontaneously. Our estimation of the free energy of CPS based on Lifshitz van der Waals theory clarified the filling mechanism, where CPS vapour in the nanopores readily undergoes capillary condensation because of its large molar volume compared to those of other vapours such as water, toluene, silane, and disilane. Consequently, a liquid-specific feature was observed during the deposition process; specifically, condensed CPS penetrated into the nanopores spontaneously via capillary force. The CPS that filled the nanopores was then transformed into solid silicon by thermal decomposition at 400 °C. The developed method is expected to be used as a nanoscale silicon filling technology, which is critical for the fabrication of future quantum scale silicon devices.

Characterization of Czochralski Silicon Detectors

OpenAIRE

Luukka, Panja-Riina; Haerkoenen, Jaakko

2012-01-01

This thesis describes the characterization of irradiated and non-irradiated segmenteddetectors made of high-resistivity (>1 kΩcm) magnetic Czochralski (MCZ) silicon. It isshown that the radiation hardness (RH) of the protons of these detectors is higher thanthat of devices made of traditional materials such as Float Zone (FZ) silicon or DiffusionOxygenated Float Zone (DOFZ) silicon due to the presence of intrinsic oxygen (> 5 x1017 cm-3). The MCZ devices therefore present an interesting alter...

CuO-Functionalized Silicon Photoanodes for Photoelectrochemical Water Splitting Devices.

Science.gov (United States)

Shi, Yuanyuan; Gimbert-Suriñach, Carolina; Han, Tingting; Berardi, Serena; Lanza, Mario; Llobet, Antoni

2016-01-13

One main difficulty for the technological development of photoelectrochemical (PEC) water splitting (WS) devices is the fabrication of active, stable and cost-effective photoelectrodes that ensure high performance. Here, we report the development of a CuO/Silicon based photoanode, which shows an onset potential for the water oxidation of 0.53 V vs SCE at pH 9, that is, an overpotential of 75 mV, and high stability above 10 h. These values account for a photovoltage of 420 mV due to the absorbed photons by silicon, as proven by comparing with analogous CuO/FTO electrodes that are not photoactive. The photoanodes have been fabricated by sputtering a thin film of Cu(0) on commercially available n-type Si wafers, followed by a photoelectrochemical treatment in basic pH conditions. The resulting CuO/Cu layer acts as (1) protective layer to avoid the corrosion of nSi, (2) p-type hole conducting layer for efficient charge separation and transportation, and (3) electrocatalyst to reduce the overpotential of the water oxidation reaction. The low cost, low toxicity, and good performance of CuO-based coatings can be an attractive solution to functionalize unstable materials for solar energy conversion.

Effects of excitation intensity on the photocurrent response of thin film silicon solar modules

Science.gov (United States)

Kim, Q.; Shumka, A.; Trask, J.

1986-01-01

Photocurrent responses of amorphous thin film silicon solar modules at room temperature were studied at different excitation intensities using various monochromatic light sources. Photocurrent imaging techniques have been effectively used to locate rapidly, and non-destructively, failure and defect sites in the multilayer thin film device. Differences observed in the photocurrent response characteristics for two different cells in the same amorphous thin film silicon solar module suggest the possibility of the formation of dissimilarly active devices, even though the module is processed in the same fabrication process. Possible mechanisms are discussed.

Atomic and electronic structures of novel silicon surface structures

Energy Technology Data Exchange (ETDEWEB)

Terry, J.H. Jr.

1997-03-01

The modification of silicon surfaces is presently of great interest to the semiconductor device community. Three distinct areas are the subject of inquiry: first, modification of the silicon electronic structure; second, passivation of the silicon surface; and third, functionalization of the silicon surface. It is believed that surface modification of these types will lead to useful electronic devices by pairing these modified surfaces with traditional silicon device technology. Therefore, silicon wafers with modified electronic structure (light-emitting porous silicon), passivated surfaces (H-Si(111), Cl-Si(111), Alkyl-Si(111)), and functionalized surfaces (Alkyl-Si(111)) have been studied in order to determine the fundamental properties of surface geometry and electronic structure using synchrotron radiation-based techniques.

Ultra-high-speed Optical Signal Processing using Silicon Photonics

DEFF Research Database (Denmark)

Oxenløwe, Leif Katsuo; Ji, Hua; Jensen, Asger Sellerup

with a photonic layer on top to interconnect them. For such systems, silicon is an attractive candidate enabling both electronic and photonic control. For some network scenarios, it may be beneficial to use optical on-chip packet switching, and for high data-density environments one may take advantage...... of the ultra-fast nonlinear response of silicon photonic waveguides. These chips offer ultra-broadband wavelength operation, ultra-high timing resolution and ultra-fast response, and when used appropriately offer energy-efficient switching. In this presentation we review some all-optical functionalities based...... on silicon photonics. In particular we use nano-engineered silicon waveguides (nanowires) [1] enabling efficient phasematched four-wave mixing (FWM), cross-phase modulation (XPM) or self-phase modulation (SPM) for ultra-high-speed optical signal processing of ultra-high bit rate serial data signals. We show...

Silicon materials task of the Low Cost Solar Array Project: Effect of impurities and processing on silicon solar cells

Science.gov (United States)

Hopkins, R. H.; Davis, J. R.; Rohatgi, A.; Hanes, M. H.; Rai-Choudhury, P.; Mollenkopf, H. C.

1982-01-01

The effects of impurities and processing on the characteristics of silicon and terrestrial silicon solar cells were defined in order to develop cost benefit relationships for the use of cheaper, less pure solar grades of silicon. The amount of concentrations of commonly encountered impurities that can be tolerated in typical p or n base solar cells was established, then a preliminary analytical model from which the cell performance could be projected depending on the kinds and amounts of contaminants in the silicon base material was developed. The impurity data base was expanded to include construction materials, and the impurity performace model was refined to account for additional effects such as base resistivity, grain boundary interactions, thermal processing, synergic behavior, and nonuniform impurity distributions. A preliminary assessment of long term (aging) behavior of impurities was also undertaken.

Custom 3D Printable Silicones with Tunable Stiffness.

Science.gov (United States)

Durban, Matthew M; Lenhardt, Jeremy M; Wu, Amanda S; Small, Ward; Bryson, Taylor M; Perez-Perez, Lemuel; Nguyen, Du T; Gammon, Stuart; Smay, James E; Duoss, Eric B; Lewicki, James P; Wilson, Thomas S

2018-02-01

Silicone elastomers have broad versatility within a variety of potential advanced materials applications, such as soft robotics, biomedical devices, and metamaterials. A series of custom 3D printable silicone inks with tunable stiffness is developed, formulated, and characterized. The silicone inks exhibit excellent rheological behavior for 3D printing, as observed from the printing of porous structures with controlled architectures. Herein, the capability to tune the stiffness of printable silicone materials via careful control over the chemistry, network formation, and crosslink density of the ink formulations in order to overcome the challenging interplay between ink development, post-processing, material properties, and performance is demonstrated. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Heterogeneously integrated silicon photonics for the mid-infrared and spectroscopic sensing.

Science.gov (United States)

Chen, Yu; Lin, Hongtao; Hu, Juejun; Li, Mo

2014-07-22

Besides being the foundational material for microelectronics, crystalline silicon has long been used for the production of infrared lenses and mirrors. More recently, silicon has become the key material to achieve large-scale integration of photonic devices for on-chip optical interconnect and signal processing. For optics, silicon has significant advantages: it offers a very high refractive index and is highly transparent in the spectral range from 1.2 to 8 μm. To fully exploit silicon’s superior performance in a remarkably broad range and to enable new optoelectronic functionalities, here we describe a general method to integrate silicon photonic devices on arbitrary foreign substrates. In particular, we apply the technique to integrate silicon microring resonators on mid-infrared compatible substrates for operation in the mid-infrared. These high-performance mid-infrared optical resonators are utilized to demonstrate, for the first time, on-chip cavity-enhanced mid-infrared spectroscopic analysis of organic chemicals with a limit of detection of less than 0.1 ng.

Angular sensitivity of modeled scientific silicon charge-coupled devices to initial electron direction

Energy Technology Data Exchange (ETDEWEB)

Plimley, Brian, E-mail: brian.plimley@gmail.com [Nuclear Engineering Department, University of California, Berkeley, CA (United States); Coffer, Amy; Zhang, Yigong [Nuclear Engineering Department, University of California, Berkeley, CA (United States); Vetter, Kai [Nuclear Engineering Department, University of California, Berkeley, CA (United States); Nuclear Science Division, Lawrence Berkeley National Laboratory, Berkeley, CA (United States)

2016-08-11

Previously, scientific silicon charge-coupled devices (CCDs) with 10.5-μm pixel pitch and a thick (650 μm), fully depleted bulk have been used to measure gamma-ray-induced fast electrons and demonstrate electron track Compton imaging. A model of the response of this CCD was also developed and benchmarked to experiment using Monte Carlo electron tracks. We now examine the trade-off in pixel pitch and electronic noise. We extend our CCD response model to different pixel pitch and readout noise per pixel, including pixel pitch of 2.5 μm, 5 μm, 10.5 μm, 20 μm, and 40 μm, and readout noise from 0 eV/pixel to 2 keV/pixel for 10.5 μm pixel pitch. The CCD images generated by this model using simulated electron tracks are processed by our trajectory reconstruction algorithm. The performance of the reconstruction algorithm defines the expected angular sensitivity as a function of electron energy, CCD pixel pitch, and readout noise per pixel. Results show that our existing pixel pitch of 10.5 μm is near optimal for our approach, because smaller pixels add little new information but are subject to greater statistical noise. In addition, we measured the readout noise per pixel for two different device temperatures in order to estimate the effect of temperature on the reconstruction algorithm performance, although the readout is not optimized for higher temperatures. The noise in our device at 240 K increases the FWHM of angular measurement error by no more than a factor of 2, from 26° to 49° FWHM for electrons between 425 keV and 480 keV. Therefore, a CCD could be used for electron-track-based imaging in a Peltier-cooled device.

Characteristics of thin-film transistors based on silicon nitride passivation by excimer laser direct patterning

International Nuclear Information System (INIS)

Chen, Chao-Nan; Huang, Jung-Jie

2013-01-01

This study explored the removal of silicon nitride using KrF laser ablation technology with a high threshold fluence of 990 mJ/cm 2 . This technology was used for contact hole patterning to fabricate SiN x -passivation-based amorphous-silicon thin films in a transistor device. Compared to the photolithography process, laser direct patterning using KrF laser ablation technology can reduce the number of process steps by at least three. Experimental results showed that the mobility and threshold voltages of thin film transistors patterned using the laser process were 0.16 cm 2 /V-sec and 0.2 V, respectively. The device performance and the test results of gate voltage stress reliability demonstrated that laser direct patterning is a promising alternative to photolithography in the panel manufacturing of thin-film transistors for liquid crystal displays. - Highlights: ► KrF laser ablation technology is used to remove silicon nitride. ► A simple method for direct patterning contact-hole in thin-film-transistor device. ► Laser technology reduced processing by at least three steps

Cobalt micro-magnet integration on silicon MOS quantum dots

Science.gov (United States)

Camirand Lemyre, Julien; Rochette, Sophie; Anderson, John; Manginell, Ronald P.; Pluym, Tammy; Ward, Dan; Carroll, Malcom S.; Pioro-Ladrière, Michel

Integration of cobalt micro-magnets on silicon metal-oxide-semiconductor (MOS) quantum dot devices has been investigated. The micro-magnets are fabricated in a lift-off process with e-beam lithography and deposited directly on top of an etched poly-silicon gate stack. Among the five resist stacks tested, one is found to be compatible with our MOS specific materials (Si and SiO2) . Moreover, devices with and without additional Al2O3 insulating layer show no additional gate leakage after processing. Preliminary transport data indicates electrostatic stability of our devices with integrated magnets. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

Towards nanometer-spaced silicon contacts to proteins

Science.gov (United States)

Schukfeh, Muhammed I.; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Towards nanometer-spaced silicon contacts to proteins

International Nuclear Information System (INIS)

Schukfeh, Muhammed I; Behr, Pascal; Tornow, Marc; Sepunaru, Lior; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David

2016-01-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO_2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p"+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current–voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si–protein–Si configuration. (paper)

Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's

International Nuclear Information System (INIS)

Neamen, D.; Shedd, W.; Buchanan, B.

1975-01-01

The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed

Effect of Processing Parameters on Thickness of Columnar Structured Silicon Wafers Directly Grown from Silicon Melts

Directory of Open Access Journals (Sweden)

Jin-Seok Lee

2012-01-01

Full Text Available In order to obtain optimum growth conditions for desired thickness and more effective silicon feedstock usage, effects of processing parameters such as preheated substrate temperatures, time intervals, moving velocity of substrates, and Ar gas blowing rates on silicon ribbon thickness were investigated in the horizontal growth process. Most of the parameters strongly affected in the control of ribbon thickness with columnar grain structure depended on the solidification rate. The thickness of the silicon ribbon decreased with an increasing substrate temperature, decreasing time interval, and increasing moving velocity of the substrate. However, the blowing of Ar gas onto a liquid layer existing on the surface of solidified ribbon contributed to achieving smooth surface roughness but did not closely affect the change of ribbon thickness in the case of a blowing rate of ≥0.65 Nm3/h because the thickness of the solidified layer was already determined by the exit height of the reservoir.

Epitaxial growth of silicon for layer transfer

Science.gov (United States)

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

N-Type delta Doping of High-Purity Silicon Imaging Arrays

Science.gov (United States)

Blacksberg, Jordana; Hoenk, Michael; Nikzad, Shouleh

2005-01-01

A process for n-type (electron-donor) delta doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays. Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac delta function (impulse function): the dopant is highly concentrated in a very thin layer. Preferably, the dopant is concentrated in one or at most two atomic layers in a crystal plane and, therefore, delta doping is also known as atomic-plane doping. The use of doping to enable detection of high-energy photons and low-energy particles was reported in several prior NASA Tech Briefs articles. As described in more detail in those articles, the main benefit afforded by delta doping of a back-illuminated silicon detector is to eliminate a "dead" layer at the back surface of the silicon wherein high-energy photons and low-energy particles are absorbed without detection. An additional benefit is that the delta-doped layer can serve as a back-side electrical contact. Delta doping of p-type silicon detectors is well established. The development of the present process addresses concerns specific to the delta doping of high-purity silicon detectors, which are typically n-type. The present process involves relatively low temperatures, is fully compatible with other processes used to fabricate the detectors, and does not entail interruption of those processes. Indeed, this process can be the last stage in the fabrication of an imaging detector that has, in all other respects, already been fully processed, including metallized. This process includes molecular-beam epitaxy (MBE) for deposition of three layers, including

SOI silicon on glass for optical MEMS

DEFF Research Database (Denmark)

Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

2003-01-01

and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

Charge transfer processes in hybrid solar cells composed of amorphous silicon and organic materials

Energy Technology Data Exchange (ETDEWEB)

Schaefer, Sebastian; Neher, Dieter [Universitaet Potsdam, Inst. Physik u. Astronomie, Karl-Liebknecht-Strasse 24/25, 14467 Potsdam-Golm (Germany); Schulze, Tim; Korte, Lars [Helmholtz Zentrum Berlin, Inst. fuer Silizium Photovoltaik, Kekulestrasse 5, 12489 Berlin (Germany)

2011-07-01

The efficiency of hybrid solar cells composed of organic materials and amorphous hydrogenated silicon (a-Si:H) strongly depends upon the efficiency of charge transfer processes at the inorganic-organic interface. We investigated the performance of devices comprising an ITO/a-Si:H(n-type)/a-Si:H(intrinsic)/organic/metal multilayer structure and using two different organic components: zinc phthalocyanine (ZnPc) and poly(3-hexylthiophene) (P3HT). The results show higher power conversion- and quantum efficiencies for the P3HT based cells, compared to ZnPc. This can be explained by larger energy-level offset at the interface between the organic layer and a-Si:H, which facilitates hole transfer from occupied states in the valence band tail to the HOMO of the organic material and additionally promotes exciton splitting. The performance of the a-Si:H/P3HT cells can be further improved by treatment of the amorphous silicon surface with hydrofluoric acid (HF) and p-type doping of P3HT with F4TCNQ. The improved cells reached maximum power conversion efficiencies of 1%.

CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

KAUST Repository

Ghoneim, Mohamed T.; Hanna, Amir; Hussain, Muhammad Mustafa

2014-01-01

Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-08-01

Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

Characterization of Czochralski silicon detectors

OpenAIRE

Luukka, Panja-Riina

2006-01-01

This thesis describes the characterization of irradiated and non-irradiated segmented detectors made of high-resistivity (>1 kΩcm) magnetic Czochralski (MCZ) silicon. It is shown that the radiation hardness (RH) of the protons of these detectors is higher than that of devices made of traditional materials such as Float Zone (FZ) silicon or Diffusion Oxygenated Float Zone (DOFZ) silicon due to the presence of intrinsic oxygen (> 5 × 1017 cm−3). The MCZ devices therefore present an interesting ...

Silicon Nano fabrication by Atomic Force Microscopy-Based Mechanical Processing

International Nuclear Information System (INIS)

Miyake, Sh.; Wang, M.; Kim, J.

2014-01-01

This paper reviews silicon nano fabrication processes using atomic force microscopy (AFM). In particular, it summarizes recent results obtained in our research group regarding AFM-based silicon nano fabrication through mechanochemical local oxidation by diamond tip sliding, as well as mechanical, electrical, and electromechanical processing using an electrically conductive diamond tip. Microscopic three-dimensional manufacturing mainly relies on etching, deposition, and lithography. Therefore, a special emphasis was placed on nano mechanical processes, mechanochemical reaction by potassium hydroxide solution etching, and mechanical and electrical approaches. Several important surface characterization techniques consisting of scanning tunneling microscopy and related techniques, such as scanning probe microscopy and AFM, were also discussed.

The evolution of FDA policy on silicone breast implants: a case study of politics, bureaucracy, and business in the process of decision-making.

Science.gov (United States)

Palley, H A

1995-01-01

The central issue facing federal regulation of breast implants is that while such devices are not functionally necessary or needed for survival, the side effects may be harmful and have not been proven unharmful. The Medical Device Amendments of 1976 appear to require such evidence prior to the FDA permitting the unrestricted marketing of these devices. However, only recently have such requirements been imposed by the FDA. The author examines the FDA's decision-making process, particularly as applied to silicone breast implants, and the factors that appears to have affected such decisions. In pursuing this study, the activities of a number of interest-group actors, as well as congressional responses and the role of federal bureaucratic actors, were examined. In 1992, the FDA established a regulatory protocol that effectively withdrew most silicone breast implants from the market for the purpose of breast augmentation and allows for the monitoring of the impact of new implants on women's health. This increase concern for determining the safety of breast implants is due to a number of factors, which are examined in this article.

Treatment of transparent conductive oxides by laser processes for the development of Silicon photovoltaic cells

International Nuclear Information System (INIS)

Canteli Perez-Caballero, D.

2015-01-01

Transparent conductive oxides (TCOs) are heavily doped oxides with high transparency in the visible range of the spectrum and a very low sheet resistance, making them very attractive for applications in optoelectronic devices. TCOs are widely found in many different areas such as low emissivity windows, electric contacts in computers, televisions or portable devices, and, specially, in the photovoltaic (PV) industry. PV industry is mainly based on mono- and multicrystalline silicon, where TCOs are used as anti-reflective coatings, but the search for cheaper, alternative technologies has led to the development of thin film PV technologies, where TCOs are used as transparent contacts. With the maturation of the thin film PV industry, laser sources have become an essential tool, allowing the improvement of some industrial processes and the development of new ones. Because of the interest on a deeper understanding of the interaction processes between laser light and TCOs, the laser ablation of three of the most important TCOs has been studied in depth in the present work. (Author)

High-performance RF coil inductors on silicon

Energy Technology Data Exchange (ETDEWEB)

Malba, V.; Young, D.; Ou, J.J.; Bernhardt, A.F.; Boser, B.E.

1998-03-01

Strong demand for wireless communication devices has motivated research directed toward monolithic integration of transceivers. The fundamental electronic component least compatible with silicon integrated circuits is the inductor, although a number of inductors are required to implement oscillators, filters and matching networks in cellular devices. Spiral inductors have been integrated into the silicon IC metallization sequence but have not performed adequately due to coupling to the silicon which results in parasitic capacitance and loss. We have, for the first time, fabricated three dimensional coil inductors on silicon which have significantly lower capacitive coupling and loss and which now exceed the requirements of potential applications. Quality factors of 30 at 1 GHz have been measured in single turn devices and Q > 16 in 2 and 4 turn devices. The reduced Q for multiturn devices appears to be related to eddy currents in outer turns generated by magnetic fields from current in neighboring turns. Higher Q values significantly in excess of 30 are anticipated using modified coil designs.

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

Science.gov (United States)

Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Chattopadhyay, Goutam (Inventor); Perez, Jose Vicente Siles (Inventor); Lin, Robert H. (Inventor); Mehdi, Imran (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Substrate-bias effect on the breakdown characteristic in a new silicon high-voltage device structure

International Nuclear Information System (INIS)

Li Qi; Wang Weidong; Zhao Qiuming; Wei Xueming

2012-01-01

A novel silicon double-RESURF LDMOS structure with an improved breakdown characteristic by substrate bias technology (SB) is reported. The P-type epitaxial layer is embedded between an N-type drift region and an N-type substrate to block the conduction path in the off-state and change the distributions of the bulk electric field. The substrate bias strengthens the charge share effect of the drift region near the source, and the vertical electric field peak under the drain is decreased, which is especially helpful in improving the vertical breakdown voltage in a lateral power device with a thin drift region. The numerical results by MEDICI indicate that the breakdown voltage of the proposed device is increased by 97% compared with a conventional LDMOS, while maintaining a lowon-resistance. (semiconductor devices)

Optoelectronic Device Integration in Silicon (OpSIS)

Science.gov (United States)

2015-10-26

silicon-on-insulator," Opt. Express 22, 17872-17879 (2014) Y. Yang, C. Galland, Y. Liu, K. Tan , R. Ding, Q. Li, K. Bergman, T. Baehr-Jones, M...Jaeger, Nicolas AF; Chrostowski, Lukas; “Electrically tunable resonant filters in phase-shifted contra- directional couplers” IEEE Group IV Photonics... Nicolas AF; Chrostowski, Lukas; “Silicon photonic grating-assisted, contra-directional couplers” Optics express Vol. 21, No. 3; 3633-3650 (2013

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology.

Science.gov (United States)

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-12-03

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm(2), and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p(+-)n homojunction through the formation of re-grown crystalline silicon layer (~5-10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method.

Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

Directory of Open Access Journals (Sweden)

Shisheng Cai

2017-03-01

Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

Firewood processing devices in Finland 2002

International Nuclear Information System (INIS)

Mutikainen, A.; Kaerhae, K.

2002-01-01

This Forestry Bulletin presents a review of the market situation for firewood processing devices in Finland during March 2002. The review is based on a questionnaire sent to device manufacturers. The firewood processing devices have traditionally been divided into three groups according to their functions: cross-cutting devices, splitting devices and cross-cutting and splitting devices. With a cross-cutting device the tree can be cross-cut only. Because it is easily possible to build the splitting function into a cross-cutting device, merely manufacturing a cross-cutting devices is rare. In all the splitting machines on the market, the splitting is carried out on a horizontally operated hydraulic cylinder pushing against a splitting blade. The types of cross-cutting blade mostly used in cross-cutting and splitting devices are circular i.e. circular saw blade, and chain saw. These devices are called firewood sawing machines. In firewood chopping machines that have a chopping blade, the wood is cross-cut using a spiral or guillotine blade. The splitting is done by a wedge blade or an axe blade. The firewood chopping machines can cross-cut and split stems up to a maximum of 20-22 cm in diameter. Circular blade firewood machines use either a cone screw or hydraulic cylinder and counter blade for splitting. They can handle wood of 20-30 cm thick in diameter. Machines using a chain saw can process stems of a maximum 30-45 cm thick in diameter. All firewood machines that work with a chain saw use a hydraulic cylinder and counter blade for splitting. According to the questionnaire responses, there were 14 (12 Finnish, one Norwegian and one Italian) manufacturers of firewood processing devices in the market. There were over 80 device models. There were only three cross-cutting devices, thirty splitting devices and forty cross-cutting splitting devices. The price range of the devices was 500-66,000 euros (including 22% VAT). According to the MTT Agrifood Research Finland

Nanostructured silicon for photonics from materials to devices

CERN Document Server

Gaburro, Z; Daldosso, N

2006-01-01

The use of light to channel signals around electronic chips could solve several current problems in microelectronic evolution including: power dissipation, interconnect bottlenecks, input/output from/to optical communication channels, poor signal bandwidth, etc. It is unfortunate that silicon is not a good photonic material: it has a poor light-emission efficiency and exhibits a negligible electro-optical effect. Silicon photonics is a field having the objective of improving the physical properties of silicon; thus turning it into a photonic material and permitting the full convergence of elec

Mathematical model of silicon smelting process basing on pelletized charge from technogenic raw materials

Science.gov (United States)

Nemchinova, N. V.; Tyutrin, A. A.; Salov, V. M.

2018-03-01

The silicon production process in the electric arc reduction furnaces (EAF) is studied using pelletized charge as an additive to the standard on the basis of the generated mathematical model. The results obtained due to the model will contribute to the analysis of the charge components behavior during melting with the achievement of optimum final parameters of the silicon production process. The authors proposed using technogenic waste as a raw material for the silicon production in a pelletized form using liquid glass and aluminum production dust from the electrostatic precipitators as a binder. The method of mathematical modeling with the help of the ‘Selector’ software package was used as a basis for the theoretical study. A model was simulated with the imitation of four furnace temperature zones and a crystalline silicon phase (25 °C). The main advantage of the created model is the ability to analyze the behavior of all burden materials (including pelletized charge) in the carbothermic process. The behavior analysis is based on the thermodynamic probability data of the burden materials interactions in the carbothermic process. The model accounts for 17 elements entering the furnace with raw materials, electrodes and air. The silicon melt, obtained by the modeling, contained 91.73 % wt. of the target product. The simulation results showed that in the use of the proposed combined charge, the recovery of silicon reached 69.248 %, which is in good agreement with practical data. The results of the crystalline silicon chemical composition modeling are compared with the real silicon samples of chemical analysis data, which showed the results of convergence. The efficiency of the mathematical modeling methods in the studying of the carbothermal silicon obtaining process with complex interphase transformations and the formation of numerous intermediate compounds using a pelletized charge as an additive to the traditional one is shown.

Comparative analysis for evaluating the traceability of interventional devices using blood vessel phantom models made of PVA-H or silicone.

Science.gov (United States)

Yu, Chang-Ho; Kwon, Tae-Kyu; Park, Chan Hee; Ohta, Makoto; Kim, Sung Hoon

2015-01-01

In this paper, we investigated the parameters with effective traceability to assess the mechanical properties of interventional devices. In our evaluation system, a box-shaped poly (vinyl alcohol) hydrogel (PVA-H) and silicone were prepared with realistic geometry, and the measurement and evaluation of traceability were carried out on devices using load hand force. The phantom models had a total of five curve pathways to reach the aneurysm sac. Traceability depends on the performance of the interventional devices in order to pass through the curved part of the model simulation track. The traceability of the guide wire was found to be much better than that of the balloon and stent loading catheter, as it reached the aneurysm sac in both phantom models. Observation using the video record is another advantage of our system, because the high transparency of the materials with silicone and PVA-H can allow visualization of the inside of an artery.

Silicon nanophotonics for scalable quantum coherent feedback networks

International Nuclear Information System (INIS)

Sarovar, Mohan; Brif, Constantin; Soh, Daniel B.S.; Cox, Jonathan; DeRose, Christopher T.; Camacho, Ryan; Davids, Paul

2016-01-01

The emergence of coherent quantum feedback control (CQFC) as a new paradigm for precise manipulation of dynamics of complex quantum systems has led to the development of efficient theoretical modeling and simulation tools and opened avenues for new practical implementations. This work explores the applicability of the integrated silicon photonics platform for implementing scalable CQFC networks. If proven successful, on-chip implementations of these networks would provide scalable and efficient nanophotonic components for autonomous quantum information processing devices and ultra-low-power optical processing systems at telecommunications wavelengths. We analyze the strengths of the silicon photonics platform for CQFC applications and identify the key challenges to both the theoretical formalism and experimental implementations. In particular, we determine specific extensions to the theoretical CQFC framework (which was originally developed with bulk-optics implementations in mind), required to make it fully applicable to modeling of linear and nonlinear integrated optics networks. We also report the results of a preliminary experiment that studied the performance of an in situ controllable silicon nanophotonic network of two coupled cavities and analyze the properties of this device using the CQFC formalism. (orig.)

Silicon nanophotonics for scalable quantum coherent feedback networks

Energy Technology Data Exchange (ETDEWEB)

Sarovar, Mohan; Brif, Constantin [Sandia National Laboratories, Livermore, CA (United States); Soh, Daniel B.S. [Sandia National Laboratories, Livermore, CA (United States); Stanford University, Edward L. Ginzton Laboratory, Stanford, CA (United States); Cox, Jonathan; DeRose, Christopher T.; Camacho, Ryan; Davids, Paul [Sandia National Laboratories, Albuquerque, NM (United States)

2016-12-15

The emergence of coherent quantum feedback control (CQFC) as a new paradigm for precise manipulation of dynamics of complex quantum systems has led to the development of efficient theoretical modeling and simulation tools and opened avenues for new practical implementations. This work explores the applicability of the integrated silicon photonics platform for implementing scalable CQFC networks. If proven successful, on-chip implementations of these networks would provide scalable and efficient nanophotonic components for autonomous quantum information processing devices and ultra-low-power optical processing systems at telecommunications wavelengths. We analyze the strengths of the silicon photonics platform for CQFC applications and identify the key challenges to both the theoretical formalism and experimental implementations. In particular, we determine specific extensions to the theoretical CQFC framework (which was originally developed with bulk-optics implementations in mind), required to make it fully applicable to modeling of linear and nonlinear integrated optics networks. We also report the results of a preliminary experiment that studied the performance of an in situ controllable silicon nanophotonic network of two coupled cavities and analyze the properties of this device using the CQFC formalism. (orig.)

Silicon-based metallic micro grid for electron field emission

International Nuclear Information System (INIS)

Kim, Jaehong; Jeon, Seok-Gy; Kim, Jung-Il; Kim, Geun-Ju; Heo, Duchang; Shin, Dong Hoon; Sun, Yuning; Lee, Cheol Jin

2012-01-01

A micro-scale metal grid based on a silicon frame for application to electron field emission devices is introduced and experimentally demonstrated. A silicon lattice containing aperture holes with an area of 80 × 80 µm 2 and a thickness of 10 µm is precisely manufactured by dry etching the silicon on one side of a double-polished silicon wafer and by wet etching the opposite side. Because a silicon lattice is more rigid than a pure metal lattice, a thin layer of Au/Ti deposited on the silicon lattice for voltage application can be more resistant to the geometric stress caused by the applied electric field. The micro-fabrication process, the images of the fabricated grid with 88% geometric transparency and the surface profile measurement after thermal feasibility testing up to 700 °C are presented. (paper)

Si-semiconductor device failure mechanisms

International Nuclear Information System (INIS)

Clauss, H.

1976-12-01

This report presents investigations on failure mechanisms that may cause defects during production and operation of silicon semiconductor devices. The failure analysis of aluminium metallization defects covers topics such as step coverage, dissolution pits and electromigration. Furthermore, the generation of process induced lattice defects was investigated. Improved processes avoiding those defects were developed. (orig.) [de

THz-wave generation via difference frequency mixing in strained silicon based waveguide utilizing its second order susceptibility χ((2)).

Science.gov (United States)

Saito, Kyosuke; Tanabe, Tadao; Oyama, Yutaka

2014-07-14

Terahertz (THz) wave generation via difference frequency mixing (DFM) process in strain silicon membrane waveguides by introducing the straining layer is theoretically investigated. The Si(3)N(4) straining layer induces anisotropic compressive strain in the silicon core and results in the appearance of the bulk second order nonlinear susceptibility χ((2)) by breaking the crystal symmetry. We have proposed waveguide structures for THz wave generation under the DFM process by .using the modal birefringence in the waveguide core. Our simulations show that an output power of up to 0.95 mW can be achieved at 9.09 THz. The strained silicon optical device may open a widow in the field of the silicon-based active THz photonic device applications.

The development of the market for neutron transmutation doped silicon

International Nuclear Information System (INIS)

Herzer, H.; Vieweg-Gutberlet, G.

1984-01-01

Neutron transmutation doped silicon was introduced to the electronic device market in the 1975-1976 time period. Today, neutron transmutation doping is definitely a mature technology applied mainly to semiconductor power devices. There is no doubt that the power device sector will remain the major consumer of NTD silicon in the near future. This paper examines the possible application of NTD silicon to other areas of the semiconductor market, and concludes that the need for NTD silicon will continue to grow and will expand into other applications. Consequently, unless new reactor capacities become available by the end of the decade, NTD silicon applications will probably be limited mainly to power and sensor devices

Neuron Stimulation Device Integrated with Silicon Nanowire-Based Photodetection Circuit on a Flexible Substrate

Directory of Open Access Journals (Sweden)

Suk Won Jung

2016-12-01

Full Text Available This paper proposes a neural stimulation device integrated with a silicon nanowire (SiNW-based photodetection circuit for the activation of neurons with light. The proposed device is comprised of a voltage divider and a current driver in which SiNWs are used as photodetector and field-effect transistors; it has the functions of detecting light, generating a stimulation signal in proportion to the light intensity, and transmitting the signal to a micro electrode. To show the applicability of the proposed neural stimulation device as a high-resolution retinal prosthesis system, a high-density neural stimulation device with a unit cell size of 110 × 110 μ m and a resolution of 32 × 32 was fabricated on a flexible film with a thickness of approximately 50 μm. Its effectiveness as a retinal stimulation device was then evaluated using a unit cell in an in vitro animal experiment involving the retinal tissue of retinal Degeneration 1 (rd1 mice. Experiments wherein stimulation pulses were applied to the retinal tissues successfully demonstrate that the number of spikes in neural response signals increases in proportion to light intensity.

Integration of lateral porous silicon membranes into planar microfluidics.

Science.gov (United States)

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

Atomic-Layer-Deposited Transparent Electrodes for Silicon Heterojunction Solar Cells

International Nuclear Information System (INIS)

Demaurex, Benedicte; Seif, Johannes P.; Smit, Sjoerd; Macco, Bart; Kessels, W. M.; Geissbuhler, Jonas; De Wolf, Stefaan; Ballif, Christophe

2014-01-01

We examine damage-free transparent-electrode deposition to fabricate high-efficiency amorphous silicon/crystalline silicon heterojunction solar cells. Such solar cells usually feature sputtered transparent electrodes, the deposition of which may damage the layers underneath. Using atomic layer deposition, we insert thin protective films between the amorphous silicon layers and sputtered contacts and investigate their effect on device operation. We find that a 20-nm-thick protective layer suffices to preserve, unchanged, the amorphous silicon layers beneath. Insertion of such protective atomic-layer-deposited layers yields slightly higher internal voltages at low carrier injection levels. However, we identify the presence of a silicon oxide layer, formed during processing, between the amorphous silicon and the atomic-layer-deposited transparent electrode that acts as a barrier, impeding hole and electron collection

A miniaturized silicon based device for nucleic acids electrochemical detection

Directory of Open Access Journals (Sweden)

Salvatore Petralia

2015-12-01

Full Text Available In this paper we describe a novel portable system for nucleic acids electrochemical detection. The core of the system is a miniaturized silicon chip composed by planar microelectrodes. The chip is embedded on PCB board for the electrical driving and reading. The counter, reference and work microelectrodes are manufactured using the VLSI technology, the material is gold for reference and counter electrodes and platinum for working electrode. The device contains also a resistor to control and measuring the temperature for PCR thermal cycling. The reaction chamber has a total volume of 20 μL. It is made in hybrid silicon–plastic technology. Each device contains four independent electrochemical cells.Results show HBV Hepatitis-B virus detection using an unspecific DNA intercalating redox probe based on metal–organic compounds. The recognition event is sensitively detected by square wave voltammetry monitoring the redox signals of the intercalator that strongly binds to the double-stranded DNA. Two approaches were here evaluated: (a intercalation of electrochemical unspecific probe on ds-DNA on homogeneous solution (homogeneous phase; (b grafting of DNA probes on electrode surface (solid phase.The system and the method here reported offer better advantages in term of analytical performances compared to the standard commercial optical-based real-time PCR systems, with the additional incomes of being potentially cheaper and easier to integrate in a miniaturized device. Keywords: Electrochemical detection, Real time PCR, Unspecific DNA intercalator

All-solid-state supercapacitors on silicon using graphene from silicon carbide

Energy Technology Data Exchange (ETDEWEB)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca, E-mail: f.iacopi@griffith.edu.au [Environmental Futures Research Institute, Griffith University, Nathan 4111 (Australia); Wood, Barry [Centre for Microscopy and Microanalysis, The University of Queensland, St. Lucia 4072 (Australia)

2016-05-02

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm{sup −2} with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

All-solid-state supercapacitors on silicon using graphene from silicon carbide

International Nuclear Information System (INIS)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca; Wood, Barry

2016-01-01

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm"−"2 with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

Graphene field-effect devices

Science.gov (United States)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Hybrid integration of carbon nanotubes in silicon photonic structures

Science.gov (United States)

Durán-Valdeiglesias, E.; Zhang, W.; Alonso-Ramos, C.; Le Roux, X.; Serna, S.; Hoang, H. C.; Marris-Morini, D.; Cassan, E.; Intonti, F.; Sarti, F.; Caselli, N.; La China, F.; Gurioli, M.; Balestrieri, M.; Vivien, L.; Filoramo, A.

2017-02-01

Silicon photonics, due to its compatibility with the CMOS platform and unprecedented integration capability, has become the preferred solution for the implementation of next generation optical interconnects to accomplish high efficiency, low energy consumption, low cost and device miniaturization in one single chip. However, it is restricted by silicon itself. Silicon does not have efficient light emission or detection in the telecommunication wavelength range (1.3 μm-1.5 μm) or any electro-optic effect (i.e. Pockels effect). Hence, silicon photonic needs to be complemented with other materials for the realization of optically-active devices, including III-V for lasing and Ge for detection. The very different requirement of these materials results in complex fabrication processes that offset the cost-effectiveness of the Si photonics approach. For this purpose, carbon nanotubes (CNTs) have recently been proposed as an attractive one-dimensional light emitting material. Interestingly, semiconducting single walled CNTs (SWNTs) exhibit room-temperature photo- and electro-luminescence in the near-IR that could be exploited for the implementation of integrated nano-sources. They can also be considered for the realization of photo-detectors and optical modulators, since they rely on intrinsically fast non-linear effects, such as Stark and Kerr effect. All these properties make SWNTs ideal candidates in order to fabricate a large variety of optoelectronic devices, including near-IR sources, modulators and photodetectors on Si photonic platforms. In addition, solution processed SWNTs can be integrated on Si using spin-coating or drop-casting techniques, obviating the need of complex epitaxial growth or chip bonding approaches. Here, we report on our recent progress in the coupling of SWNTs light emission into optical resonators implemented on the silicon-on-insulator (SOI) platform. .

Transformation optics on a silicon platform

International Nuclear Information System (INIS)

Gabrielli, Lucas H; Lipson, Michal

2011-01-01

Transformation optics allows the creation of innovative devices; however, its implementation in the optical domain remains challenging. We describe here our process to design and fabricate such devices using silicon as a platform for broad band operation in the optical domain. We discuss the approximations and methods employed to overcome the challenges of using dielectric materials as a platform for transformation optics, such as the anisotropy and gradient refractive index implementation. These encompass conformal and quasi-conformal mappings, and a dithering process to discretize and quantize the continuously inhomogeneous index function. We show examples of devices that we fabricated and tested, including the carpet invisibility cloak, a broad bandwidth light concentrator, and a perfect imaging device, known as Maxwell's fish eye lens. Finally, we touch on future directions under investigation to further develop transformation optics based on dielectric materials

Compact integrated optical devices for optical sensor and switching applications

NARCIS (Netherlands)

Kauppinen, L.J.

2010-01-01

This thesis describes the design, fabrication, and characterization of compact optical devices for sensing and switching applications. Our focus has been to realize the devices using CMOS-compatible fabrication processes. Particularly the silicon photonics fabrication platform, ePIXfab, has been

All silicon waveguide spherical microcavity coupler device.

Science.gov (United States)

Xifré-Pérez, E; Domenech, J D; Fenollosa, R; Muñoz, P; Capmany, J; Meseguer, F

2011-02-14

A coupler based on silicon spherical microcavities coupled to silicon waveguides for telecom wavelengths is presented. The light scattered by the microcavity is detected and analyzed as a function of the wavelength. The transmittance signal through the waveguide is strongly attenuated (up to 25 dB) at wavelengths corresponding to the Mie resonances of the microcavity. The coupling between the microcavity and the waveguide is experimentally demonstrated and theoretically modeled with the help of FDTD calculations.

Industrial science and technology research and development project of university cooperative type in fiscal 2000. Report on achievements in semiconductor device manufacturing processes using Cat-CVD method (Development of technology to rationalize energy usage); 2000 nendo daigaku renkeigata sangyo kagaku gijutsu kenkyu kaihatsu project. Cat-CVD ho ni yoru handotai device seizo process seika hokokusho (energy shiyo gorika gijutsu kaihatsu)

Energy Technology Data Exchange (ETDEWEB)

NONE

2001-03-01

The catalytic chemical vapor deposition (Cat-CVD) method is a low-temperature thin film depositing technology that can achieve improvement in quality of semiconductor thin films and can perform inexpensive film deposition in a large area. This paper summarizes the achievements in fiscal 2000 in the demonstrative research and development theme of the present project, centering on the following five areas: 1) discussions on application of the Cat-CVD method to the mass production process for gallium arsenide integrated circuits, 2) studies on the possibility to apply the Cat-CVD method to the process to fabricate nitrided silicon protective film for ferroelectric memory devices, 3) formation of nitrided silicon films for silicon integrated circuits by means of the Cat-CVD method, and development of a chamber cleaning technology, 4) fabrication of high-mobility poly-crystalline silicon thin film transistors formed by using the Cat-CVD method and large particle size poly-crystalline silicon films by using the catalytic chemical sputtering process, and 5) discussions on properties of amorphous silicon thin film transistors formed by using the Cat-CVD method and formation of large area films by using a catalyst integrated shower head. (NEDO)

Recent results from the development of silicon detectors with integrated electronics

Energy Technology Data Exchange (ETDEWEB)

Dalla Betta, G.-F. E-mail: dallabe@dit.unitn.it; Boscardin, M.; Batignani, G.; Bettarini, S.; Bisogni, M.G.; Bosisio, L.; Carpinelli, M.; Ciacchi, M.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Novelli, M.; Piemonte, C.; Rachevskaia, I.; Rama, M.; Ratti, L.; Re, V.; Ronchin, S.; Sandrelli, F.; Simi, G.; Speziali, V.; Rosso, V.; Traversi, G.; Zorzi, N

2004-02-01

In the past few years we have developed a technological process allowing for the fabrication of radiation detectors with integrated electronics on high-resistivity silicon substrates. We report on some recent results relevant to the process optimisation and to device/circuit characterization.

Recent results from the development of silicon detectors with integrated electronics

International Nuclear Information System (INIS)

Dalla Betta, G.-F.; Boscardin, M.; Batignani, G.; Bettarini, S.; Bisogni, M.G.; Bosisio, L.; Carpinelli, M.; Ciacchi, M.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Novelli, M.; Piemonte, C.; Rachevskaia, I.; Rama, M.; Ratti, L.; Re, V.; Ronchin, S.; Sandrelli, F.; Simi, G.; Speziali, V.; Rosso, V.; Traversi, G.; Zorzi, N.

2004-01-01

In the past few years we have developed a technological process allowing for the fabrication of radiation detectors with integrated electronics on high-resistivity silicon substrates. We report on some recent results relevant to the process optimisation and to device/circuit characterization

Process research of non-Czochralski silicon material

Science.gov (United States)

Campbell, R. B.

1986-01-01

Simultaneous diffusion of liquid precursors containing phosphorus and boron into dendritic web silicon to form solar cell structures was investigated. A simultaneous junction formation techniques was developed. It was determined that to produce high quality cells, an annealing cycle (nominal 800 C for 30 min) should follow the diffusion process to anneal quenched-in defects. Two ohm-cm n-base cells were fabricated with efficiencies greater than 15%. A cost analysis indicated that the simultansous diffusion process costs can be as low as 65% of the costs of the sequential diffusion process.

Biofilm formation and design features of indwelling silicone rubber tracheoesophageal voice prostheses - An electron microscopical study

NARCIS (Netherlands)

Leunisse, C; van Weissenbruch, R; Busscher, HJ; van der Mei, HC; Dijk, F; Albers, FWJ

2001-01-01

After total laryngectomy, voice can be restored with a silicone rubber tracheoesophageal voice prosthesis. However, biofilm formation and subsequent deterioration of the silicone material of the prosthesis will limit device life by impairing valve function. To simulate the natural process of biofilm

Control of back surface reflectance from aluminum alloyed contacts on silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Cudzinovic, M.; Sopori, B. [National Renewable Energy Lab., Golden, CO (United States)

1996-05-01

A process for forming highly reflective aluminum back contacts with low contact resistance to silicon solar cells is described. By controlling the process conditions, it is possible to vary the silicon/aluminum interface from a specular to a diffuse reflector while maintaining a high interface reflectance. The specular interface is found to be a uniform silicon/aluminum alloy layer a few angstroms thick that has epitaxially regrown on the silicon. The diffuse interface consists of randomly distributed (111) pyramids produced by crystallographic out-diffusion of the bulk silicon. The light trapping ability of the diffuse contact is found to be close to the theoretical limit. Both types of contacts are found to have specific contact resistivities of 10{sup {minus}5} {Omega}-cm{sup 2}. The process for forming the contacts involves illuminating the devices with tungsten halogen lamps. The process is rapid (under 100 s) and low temperature (peak temperature < 580{degrees}C), making it favorable for commercial solar cell fabrication.

Stress testing on silicon carbide electronic devices for prognostics and health management.

Energy Technology Data Exchange (ETDEWEB)

Kaplar, Robert James; Brock, Reinhard C.; Marinella, Matthew; King, Michael Patrick; Smith, Mark A.; Atcitty, Stanley

2011-01-01

Power conversion systems for energy storage and other distributed energy resource applications are among the drivers of the important role that power electronics plays in providing reliable electricity. Wide band gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) will help increase the performance and efficiency of power electronic equipment while condition monitoring (CM) and prognostics and health management (PHM) will increase the operational availability of the equipment and thereby make it more cost effective. Voltage and/or temperature stress testing were performed on a number of SiC devices in order to accelerate failure modes and to identify measureable shifts in electrical characteristics which may provide early indication of those failures. Those shifts can be interpreted and modeled to provide prognostic signatures for use in CM and/or PHM. Such experiments will also lead to a deeper understanding of basic device physics and the degradation mechanisms behind failure.

Gas processing device

International Nuclear Information System (INIS)

Kobayashi, Yoshihiro; Seki, Eiji.

1991-01-01

State of electric discharge is detected based on a gas pressure in a sealed container and a discharging current flowing between both of electrodes. When electric arc discharges occur, introduction of gases to be processed is stopped and a voltage applied to both of the electrodes is interrupted. Then, when the gas pressure in the sealed container is lowered to a predetermined value, a power source voltage is applied again to both of the electrodes to recover glow discharges, and the introduction of the gas to be processed is started. With such steps, even if electric arc discharges occur, they are eliminated automatically and, accordingly, normal glow discharges can be recovered, to prevent failures of the device due to electric arc discharges. The glow discharges are recovered automatically without stopping the operation of the gas processing device, and gas injection and solidification processing can be conducted continuously and stably. (T.M.)

Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

International Nuclear Information System (INIS)

Son, Dang Ngoc; Van Duy, Nguyen; Jung, Sungwook; Yi, Junsin

2010-01-01

Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiN x films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application

Microcrystalline silicon deposition: Process stability and process control

International Nuclear Information System (INIS)

Donker, M.N. van den; Kilper, T.; Grunsky, D.; Rech, B.; Houben, L.; Kessels, W.M.M.; Sanden, M.C.M. van de

2007-01-01

Applying in situ process diagnostics, we identified several process drifts occurring in the parallel plate plasma deposition of microcrystalline silicon (μc-Si:H). These process drifts are powder formation (visible from diminishing dc-bias and changing spatial emission profile on a time scale of 10 0 s), transient SiH 4 depletion (visible from a decreasing SiH emission intensity on a time scale of 10 2 s), plasma heating (visible from an increasing substrate temperature on a time scale of 10 3 s) and a still puzzling long-term drift (visible from a decreasing SiH emission intensity on a time scale of 10 4 s). The effect of these drifts on the crystalline volume fraction in the deposited films is investigated by selected area electron diffraction and depth-profiled Raman spectroscopy. An example shows how the transient depletion and long-term drift can be prevented by suitable process control. Solar cells deposited using this process control show enhanced performance. Options for process control of plasma heating and powder formation are discussed

Structural and optical properties of silicon rich oxide films in graded-stoichiometric multilayers for optoelectronic devices

Energy Technology Data Exchange (ETDEWEB)

Palacios-Huerta, L.; Aceves-Mijares, M. [Electronics Department, INAOE, Apdo. 51, Puebla, Pue. 72000, México (Mexico); Cabañas-Tay, S. A.; Cardona-Castro, M. A.; Morales-Sánchez, A., E-mail: alfredo.morales@cimav.edu.mx [Centro de Investigación en Materiales Avanzados S.C., Unidad Monterrey-PIIT, Apodaca, NL 66628, México (Mexico); Domínguez-Horna, C. [Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC), Bellaterra 08193, Barcelona (Spain)

2016-07-18

Silicon nanocrystals (Si-ncs) are excellent candidates for the development of optoelectronic devices. Nevertheless, different strategies are still necessary to enhance their photo and electroluminescent properties by controlling their structural and compositional properties. In this work, the effect of the stoichiometry and structure on the optical properties of silicon rich oxide (SRO) films in a multilayered (ML) structure is studied. SRO MLs with silicon excess gradually increased towards the top and bottom and towards the center of the ML produced through the variation of the stoichiometry in each SRO layer were fabricated and confirmed by X-ray photoelectron spectroscopy. Si-ncs with three main sizes were observed by a transmission electron microscope, in agreement with the stoichiometric profile of each SRO layer. The presence of the three sized Si-ncs and some oxygen related defects enhances intense violet/blue and red photoluminescence (PL) bands. The SRO MLs were super-enriched with additional excess silicon by Si{sup +} implantation, which enhanced the PL intensity. Oxygen-related defects and small Si-ncs (<2 nm) are mostly generated during ion implantation enhancing the violet/blue band to become comparable to the red band. The structural, compositional, and luminescent characteristics of the multilayers are the result of the contribution of the individual characteristics of each layer.

P3HT:PCBM Incorporated with Silicon Nanoparticles as Photoactive Layer in Efficient Organic Photovoltaic Devices

Directory of Open Access Journals (Sweden)

Shang-Chou Chang

2013-01-01

Full Text Available Silicon nanoparticles doped poly(3-hexylthiophene and [6,6]-phenyl C61-butyric acid methyl ester blends (P3HT:PCBM: Si NP have been produced as the photoactive layer of organic photovoltaic devices (OPVs. The silicon nanoparticles’ size is between 80 and 100 nm checked by transmission electron microscope (TEM. The 0.35 wt% Si NP doping OPVs exhibit higher power conversion efficiency (PCE than other OPVs. The PCE of the OPVs increases from 3.01% to 3.38% mainly due to increasing short-circuit current density from 8.38 to 9.48 mA/cm2, while the open-circuit voltage remains the same. The Si NP can provide extra exciton separation and electron pathways in hybrid solar cells.

MicroElectroMechanical devices and fabrication technologies for radio-frequency analog signal processing

Science.gov (United States)

Young, Darrin Jun

The proliferation of wireless services creates a pressing need for compact and low cost RF transceivers. Modern sub-micron technologies provide the active components needed for miniaturization but fail to deliver high quality passives needed in oscillators and filters. This dissertation demonstrates procedures for adding high quality inductors and tunable capacitors to a standard silicon integrated circuits. Several voltage-controlled oscillators operating in the low Giga-Hertz range demonstrate the suitability of these components for high performance RF building blocks. Two low-temperature processes are described to add inductors and capacitors to silicon ICs. A 3-D coil geometry is used for the inductors rather than the conventional planar spiral to substantially reduce substrate loss and hence improve the quality factor and self-resonant frequency. Measured Q-factors at 1 GHz are 30 for a 4.8 nH device, 16 for 8.2 nH and 13.8 nH inductors. Several enhancements are proposed that are expected to result in a further improvement of the achievable Q-factor. This research investigates the design and fabrication of silicon-based IC-compatible high-Q tunable capacitors and inductors. The goal of this investigation is to develop a monolithic low phase noise radio-frequency voltage-controlled oscillator using these high-performance passive components for wireless communication applications. Monolithic VCOs will help the miniaturization of current radio transceivers, which offers a potential solution to achieve a single hand-held wireless phone with multistandard capabilities. IC-compatible micromachining fabrication technologies have been developed to realize on-chip high-Q RF tunable capacitors and 3-D coil inductors. The capacitors achieve a nominal capacitance value of 2 pF and can be tuned over 15% with 3 V. A quality factor over 60 has been measured at 1 GHz. 3-D coil inductors obtain values of 4.8 nH, 8.2 nH and 13.8 nH. At 1 GHz a Q factor of 30 has been achieved

Heterogeneous silicon mesostructures for lipid-supported bioelectric interfaces

Energy Technology Data Exchange (ETDEWEB)

Jiang, Yuanwen; Carvalho-de-Souza, João L.; Wong, Raymond C. S.; Luo, Zhiqiang; Isheim, Dieter; Zuo, Xiaobing; Nicholls, Alan W.; Jung, Il Woong; Yue, Jiping; Liu, Di-Jia; Wang, Yucai; De Andrade, Vincent; Xiao, Xianghui; Navrazhnykh, Luizetta; Weiss, Dara E.; Wu, Xiaoyang; Seidman, David N.; Bezanilla, Francisco; Tian, Bozhi

2016-06-27

Silicon-based materials have widespread application as biophysical tools and biomedical devices. Here we introduce a biocompatible and degradable mesostructured form of silicon with multi-scale structural and chemical heterogeneities. The material was synthesized using mesoporous silica as a template through a chemical vapour deposition process. It has an amorphous atomic structure, an ordered nanowire-based framework and random submicrometre voids, and shows an average Young’s modulus that is 2–3 orders of magnitude smaller than that of single-crystalline silicon. In addition, we used the heterogeneous silicon mesostructures to design a lipid-bilayer-supported bioelectric interface that is remotely controlled and temporally transient, and that permits non-genetic and subcellular optical modulation of the electrophysiology dynamics in single dorsal root ganglia neurons. Our findings suggest that the biomimetic expansion of silicon into heterogeneous and deformable forms can open up opportunities in extracellular biomaterial or bioelectric systems.

Effect of ultraviolet illumination and ambient gases on the photoluminescence and electrical properties of nanoporous silicon layer for organic vapor sensor.

Science.gov (United States)

Atiwongsangthong, Narin

2012-08-01

The purpose of this research, the nanoporous silicon layer were fabricated and investigated the physical properties such as photoluminescence and the electrical properties in order to develop organic vapor sensor by using nanoporous silicon. The Changes in the photoluminescence intensity of nanoporous silicon samples are studied during ultraviolet illumination in various ambient gases such as nitrogen, oxigen and vacuum. In this paper, the nanoporous silicon layer was used as organic vapor adsorption and sensing element. The advantage of this device are simple process compatible in silicon technology and usable in room temperature. The structure of this device consists of nanoporous silicon layer which is formed by anodization of silicon wafer in hydrofluoric acid solution and aluminum electrode which deposited on the top of nanoporous silicon layer by evaporator. The nanoporous silicon sensors were placed in a gas chamber with various organic vapor such as ethanol, methanol and isopropyl alcohol. From studying on electrical characteristics of this device, it is found that the nanoporous silicon layer can detect the different organic vapor. Therefore, the nanoporous silicon is important material for organic vapor sensor and it can develop to other applications about gas sensors in the future.

Gaseous waste processing device in nuclear power plant

International Nuclear Information System (INIS)

Takechi, Eisuke; Matsutoshi, Makoto.

1978-01-01

Purpose: To arrange the units of waste processing devices in a number one more than the number thereof required for a plurality of reactors, and to make it usable commonly as a preliminary waste processing device thereby to effectively use all the gaseous waste processing devices. Constitution: A gaseous waste processing device is constituted by an exhaust gas extractor, a first processing device, a second processing device and the like, which are all connected in series. Upon this occasion, devices from the exhaust gas extractor to the first processing device and valves, which are provided in each of reactors, are arranged in series, on one hand, but valves at the downstream side join one another by one pipeline, and are connected to a stack through a total gaseous waste processing device, on another. (Yoshihara, H.)

Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

KAUST Repository

Hussain, Aftab M.

2016-12-01

With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

Compound FDTD method for silicon photonics

Directory of Open Access Journals (Sweden)

Abbas Olyaee

2011-09-01

Full Text Available Attempt to manufacture photonics devices on silicon requires theoretical and numerical prediction. This essay presents Compound FDTD (C-FDTD method for comprehensive simulation of silicon photonics devices. Although this method is comprehensive, it maintains conventional Yee algorithm. The method involves variation of refractive index due to nonlinear effects. With the help of this simulator, refractive index change due to free-carriers created through two photon absorption and Kerr effect in silicon waveguide is considered. Results indicate how to choose pump pulse shape to optimum operation of active photonics devices. Also conductivity variation of Si waveguide due to change in free-carrier density is studied. By considering variations in conductivity profile, we are able to design better schemes for sweep free carriers away with reverse bias or nonlinear photovoltaic effect for fast devices and Raman amplifiers.

Tin - an unlikely ally for silicon field effect transistors?

KAUST Repository

Hussain, Aftab M.

2014-01-13

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high-κ/metal gate based multi-gate-field-effect-transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Study of the processes of carbonization and oxidation of porous silicon by Raman and IR spectroscopy

International Nuclear Information System (INIS)

Vasin, A. V.; Okholin, P. N.; Verovsky, I. N.; Nazarov, A. N.; Lysenko, V. S.; Kholostov, K. I.; Bondarenko, V. P.; Ishikawa, Y.

2011-01-01

Porous silicon layers were produced by electrochemical etching of single-crystal silicon wafers with the resistivity 10 Ω cm in the aqueous-alcohol solution of hydrofluoric acid. Raman spectroscopy and infrared absorption spectroscopy are used to study the processes of interaction of porous silicon with undiluted acetylene at low temperatures and the processes of oxidation of carbonized porous silicon by water vapors. It is established that, even at the temperature 550°C, the silicon-carbon bonds are formed at the pore surface and the graphite-like carbon condensate emerges. It is shown that the carbon condensate inhibits oxidation of porous silicon by water vapors and contributes to quenching of white photoluminescence in the oxidized carbonized porous silicon nanocomposite layer.

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

Science.gov (United States)

Chung, Jae-Moon; Zhang, Xiaokun; Shang, Fei; Kim, Ji-Hoon; Wang, Xiao-Lin; Liu, Shuai; Yang, Baoguo; Xiang, Yong

2018-05-01

To overcome the technological and economic obstacles of amorphous indium-gallium-zinc-oxide (a-IGZO)-based display backplane for industrial production, a clean etch-stopper (CL-ES) process is developed to fabricate a-IGZO-based thin film transistor (TFT) with improved uniformity and reproducibility on 8.5th generation glass substrates (2200 mm × 2500 mm). Compared with a-IGZO-based TFT with back-channel-etched (BCE) structure, a newly formed ES nano-layer ( 100 nm) and a simultaneous etching of a-IGZO nano-layer (30 nm) and source-drain electrode layer are firstly introduced to a-IGZO-based TFT device with CL-ES structure to improve the uniformity and stability of device for large-area display. The saturation electron mobility of 8.05 cm2/V s and the V th uniformity of 0.72 V are realized on the a-IGZO-based TFT device with CL-ES structure. In the negative bias temperature illumination stress and positive bias thermal stress reliability testing under a ± 30 V bias for 3600 s, the measured V th shift of CL-ES-structured device significantly decreased to - 0.51 and + 1.94 V, which are much lower than that of BCE-structured device (- 3.88 V, + 5.58 V). The electrical performance of the a-IGZO-based TFT device with CL-ES structure implies that the economic transfer from a silicon-based TFT process to the metal oxide semiconductor-based process for LCD fabrication is highly feasible.

Effects of impurities on silicon solar-cell performance

Science.gov (United States)

Hopkins, R. H.

1986-01-01

Model analyses indicate that sophisticated solar cell designs (back surface fields, optical reflectors, surface passivation, and double layer antireflective coatings) can produce devices with conversion efficiencies above 20%. To realize this potential, the quality of the silicon from which the cells are made must be improved; and these excellent electrical properties must be maintained during device processing. As the cell efficiency rises, the sensitivity to trace contaminants also increases. For example, the threshold Ti impurity concentraion at which cell performance degrades is more than an order of magnitude lower for an 18% cell than for a 16% cell. Similar behavior occurs for numerous other metal species which introduce deep level traps that stimulate the recombination of photogenerated carriers in silicon. Purification via crystal growth in conjunction with gettering steps to preserve the large diffusion length of the as grown material can lead to the production of devices with efficiencies above 18%, as verified experimentally.

Laser desorption ionization and peptide sequencing on laser induced silicon microcolumn arrays

Science.gov (United States)

Vertes, Akos [Reston, VA; Chen, Yong [San Diego, CA

2011-12-27

The present invention provides a method of producing a laser-patterned silicon surface, especially silicon wafers for use in laser desorption ionization (LDI-MS) (including MALDI-MS and SELDI-MS), devices containing the same, and methods of testing samples employing the same. The surface is prepared by subjecting a silicon substrate to multiple laser shots from a high-power picosecond or femtosecond laser while in a processing environment, e.g., underwater, and generates a remarkable homogenous microcolumn array capable of providing an improved substrate for LDI-MS.

Silicon micro-fluidic cooling for NA62 GTK pixel detectors

CERN Document Server

Romagnoli, G; Brunel, B; Catinaccio, A; Degrange, J; Mapelli, A; Morel, M; Noel, J; Petagna, P

2015-01-01

Silicon micro-channel cooling is being studied for efficient thermal management in application fields such as high power computing and 3D electronic integration. This concept has been introduced in 2010 for the thermal management of silicon pixel detectors in high energy physics experiments. Combining the versatility of standard micro-fabrication processes with the high thermal efficiency typical of micro-fluidics, it is possible to produce effective thermal management devices that are well adapted to different detector configurations. The production of very thin cooling devices in silicon enables a minimization of material of the tracking sensors and eliminates mechanical stresses due to the mismatch of the coefficient of thermal expansion between detectors and cooling systems. The NA62 experiment at CERN will be the first high particle physics experiment that will install a micro-cooling system to perform the thermal management of the three detection planes of its Gigatracker pixel detector.

Report on achievements in fiscal 1999. Development of energy usage rationalizing silicon manufacturing process (Development of manufacturing technology for mass production of silicon for solar cells); 1999 nendo energy shiyo gorika silicon seizo process kaihatsu seika hokokusho. Taiyo denchiyo silicon ryosanka seizo gijutsu no kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

Discussions were given on manufacture of raw material silicon for solar cells with regard to boron removal, solidification, finishing and refining of metallic impurities, refining of unutilized silicon scraps, and making them into wafers and solar cells after refining. This paper summarizes the achievements in fiscal 1999. With regard to purity deterioration due to contamination by boron containing silica powder generated during the boron removal in the manufacturing process, the facilities were modified resulting in the reduction thereof to 0.04 ppmw or less. Regarding the repetitive use of boron removing crucibles, the experiment identified the possibility of using them for more than three times. In trial fabrication of samples by using the solidification refining and cast integrated process, ingots of 550 mm square and about 300 mm high were obtained, which were sliced into 10-cm square materials for use as wafers. Measurement of the conversion efficiency has resulted in 13% or more which is almost equivalent in the center and edges of the ingot. It was revealed that solar cell wafers may be fabricated by using this process, which can use either the p-type low-resistance silicon scraps or the metallic silicon as the starting material. (NEDO)

Low temperature surface passivation of crystalline silicon and its application to interdigitated back contact silicon heterojunction (ibc-shj) solar cell

Science.gov (United States)

Shu, Zhan

With the absence of shading loss together with improved quality of surface passivation introduced by low temperature processed amorphous silicon crystalline silicon (a-Si:H/c-Si) heterojunction, the interdigitated back contact silicon heterojunction (IBC-SHJ) solar cell exhibits a potential for higher conversion efficiency and lower cost than a traditional front contact diffused junction solar cell. In such solar cells, the front surface passivation is of great importance to achieve both high open-circuit voltage (Voc) and short-circuit current (Jsc). Therefore, the motivation of this work is to develop a low temperature processed structure for the front surface passivation of IBC-SHJ solar cells, which must have an excellent and stable passivation quality as well as a good anti-reflection property. Four different thin film materials/structures were studied and evaluated for this purpose, namely: amorphous silicon nitride (a-SiNx:H), thick amorphous silicon film (a-Si:H), amorphous silicon/silicon nitride/silicon carbide (a-Si:H/a-SiN x:H/a-SiC:H) stack structure with an ultra-thin a-Si:H layer, and zinc sulfide (ZnS). It was demonstrated that the a-Si:H/a-SiNx:H/a-SiC:H stack surpasses other candidates due to both of its excellent surface passivation quality (SRVSi surface is found to be resulted from (i) field effect passivation due to the positive fixed charge (Q fix~1x1011 cm-2 with 5 nm a-Si:H layer) in a-SiNx:H as measured from capacitance-voltage technique, and (ii) reduced defect state density (mid-gap Dit~4x1010 cm-2eV-1) at a-Si:H/c-Si interface provided by a 5 nm thick a-Si:H layer, as characterized by conductance-frequency measurements. Paralleled with the experimental studies, a computer program was developed in this work based on the extended Shockley-Read-Hall (SRH) model of surface recombination. With the help of this program, the experimental injection level dependent SRV curves of the stack passivated c-Si samples were successfully reproduced and

Silicon fiber with p-n junction

International Nuclear Information System (INIS)

Homa, D.; Cito, A.; Pickrell, G.; Hill, C.; Scott, B.

2014-01-01

In this study, we fabricated a p-n junction in a fiber with a phosphorous doped silicon core and fused silica cladding. The fibers were fabricated via a hybrid process of the core-suction and melt-draw techniques and maintained overall diameters ranging from 200 to 900 μm and core diameters of 20–800 μm. The p-n junction was formed by doping the fiber with boron and confirmed via the current-voltage characteristic. The demonstration of a p-n junction in a melt-drawn silicon core fiber paves the way for the seamless integration of optical and electronic devices in fibers.

PECVD silicon carbide surface micromachining technology and selected MEMS applications

NARCIS (Netherlands)

Rajaraman, V.; Pakula, L.S.; Yang, H.; French, P.J.; Sarro, P.M.

2011-01-01

Attractive material properties of plasma enhanced chemical vapour deposited (PECVD) silicon carbide (SiC) when combined with CMOS-compatible low thermal budget processing provides an ideal technology platform for developing various microelectromechanical systems (MEMS) devices and merging them with

Kinetic Modeling of a Silicon Refining Process in a Moist Hydrogen Atmosphere

Science.gov (United States)

Chen, Zhiyuan; Morita, Kazuki

2018-06-01

We developed a kinetic model that considers both silicon loss and boron removal in a metallurgical grade silicon refining process. This model was based on the hypotheses of reversible reactions. The reaction rate coefficient kept the same form but error of terminal boron concentration could be introduced when relating irreversible reactions. Experimental data from published studies were used to develop a model that fit the existing data. At 1500 °C, our kinetic analysis suggested that refining silicon in a moist hydrogen atmosphere generates several primary volatile species, including SiO, SiH, HBO, and HBO2. Using the experimental data and the kinetic analysis of volatile species, we developed a model that predicts a linear relationship between the reaction rate coefficient k and both the quadratic function of p(H2O) and the square root of p(H2). Moreover, the model predicted the partial pressure values for the predominant volatile species and the prediction was confirmed by the thermodynamic calculations, indicating the reliability of the model. We believe this model provides a foundation for designing a silicon refining process with a fast boron removal rate and low silicon loss.

Electrically active defects in solar grade multicrystalline silicon

DEFF Research Database (Denmark)

Dahl, Espen

2013-01-01

Shortage in high purity silicon feedstock, as a result of the formidable increased demand for solar cell devices during the last two decades, can be mitigated by the introduction of cheaper feedstock of solar grade (So-G) quality. Silicon produced through the metallurgical process route has shown...... the potential to be such a feedstock. However, this feedstock has only few years of active commercial history and the detailed understanding of the nature of structural defects in this material still has fundamental shortcomings. In this thesis the electrical activity of structural defects, commonly associated...

Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

Science.gov (United States)

Chang, You-Tai; Peng, Kang-Ping; Li, Pei-Wen; Lin, Horng-Chih

2018-04-01

In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

Battery, especially for portable devices, has an anode containing silicon

NARCIS (Netherlands)

Kan, S.Y.

2002-01-01

The anode (2) contains silicon. A battery with a silicon-containing anode is claimed. An Independent claim is also included for a method used to make the battery, comprising the doping of a silicon substrate (1) with charge capacity-increasing material (preferably boron, phosphorous or arsenic),

Illuminating the future of silicon photonics: optical coupling of carbon nanotubes to microrings

International Nuclear Information System (INIS)

Kato, Y K

2015-01-01

Advances in carbon nanotube material quality and processing techniques have led to an increased interest in nanotube photonics. In particular, emission in the telecommunication wavelengths makes nanotubes compatible with silicon photonics. Noury et al (2014 Nanotechnology 25 215201) have reported on carbon nanotube photoluminescence coupled to silicon microring resonators, underscoring the advantage of combining carbon nanotube emitters with silicon photonics. Their results open up the possibility of using nanotubes in other waveguide-based devices, taking advantage of well-established technologies. (viewpoint)

Silicon Nanocrystal Synthesis in Microplasma Reactor

Science.gov (United States)

Nozaki, Tomohiro; Sasaki, Kenji; Ogino, Tomohisa; Asahi, Daisuke; Okazaki, Ken

Nanocrystalline silicon particles with grains smaller than 5 nm are widely recognized as a key material in optoelectronic devices, lithium battery electrodes, and bio-medical labels. Another important characteristic is that silicon is an environmentally safe material that is used in numerous silicon technologies. To date, several synthesis methods such as sputtering, laser ablation, and plasma-enhanced chemical vapor deposition (PECVD) based on low-pressure silane chemistry (SiH4) have been developed for precise control of size and density distributions of silicon nanocrystals. In this study, we explore the possibility of microplasma technologies for efficient production of mono-dispersed nanocrystalline silicon particles on a micrometer-scale, continuous-flow plasma reactor operated at atmospheric pressure. Mixtures of argon, hydrogen, and silicon tetrachloride were activated using a very-high-frequency (144 MHz) power source in a capillary glass tube with volume of less than 1 μl. Fundamental plasma parameters of the microplasma were characterized using optical emission spectroscopy, which respectively indicated electron density of 1015 cm-3, argon excitation temperature of 5000 K, and rotational temperature of 1500 K. Such high-density non-thermal reactive plasma can decompose silicon tetrachloride into atomic silicon to produce supersaturated silicon vapor, followed by gas-phase nucleation via three-body collision: particle synthesis in high-density plasma media is beneficial for promoting nucleation processes. In addition, further growth of silicon nuclei can be terminated in a short-residence-time reactor. Micro-Raman scattering spectra showed that as-deposited particles are mostly amorphous silicon with a small fraction of silicon nanocrystals. Transmission electron micrography confirmed individual 3-15 nm silicon nanocrystals. Although particles were not mono-dispersed, they were well separated and not coagulated.

The role of point defects and defect complexes in silicon device processing. Summary report and papers

Energy Technology Data Exchange (ETDEWEB)

Sopori, B.; Tan, T.Y.

1994-08-01

This report is a summary of a workshop hold on August 24--26, 1992. Session 1 of the conference discussed characteristics of various commercial photovoltaic silicon substrates, the nature of impurities and defects in them, and how they are related to the material growth. Session 2 on point defects reviewed the capabilities of theoretical approaches to determine equilibrium structure of defects in the silicon lattice arising from transitional metal impurities and hydrogen. Session 3 was devoted to a discussion of the surface photovoltaic method for characterizing bulk wafer lifetimes, and to detailed studies on the effectiveness of various gettering operations on reducing the deleterious effects of transition metals. Papers presented at the conference are also included in this summary report.

Effect of Silicon Nanowire on Crystalline Silicon Solar Cell Characteristics

Directory of Open Access Journals (Sweden)

Zahra Ostadmahmoodi Do

2016-06-01

Full Text Available Nanowires (NWs are recently used in several sensor or actuator devices to improve their ordered characteristics. Silicon nanowire (Si NW is one of the most attractive one-dimensional nanostructures semiconductors because of its unique electrical and optical properties. In this paper, silicon nanowire (Si NW, is synthesized and characterized for application in photovoltaic device. Si NWs are prepared using wet chemical etching method which is commonly used as a simple and low cost method for producing nanowires of the same substrate material. The process conditions are adjusted to find the best quality of Si NWs. Morphology of Si NWs is studied using a field emission scanning electron microscopic technique. An energy dispersive X-Ray analyzer is also used to provide elemental identification and quantitative compositional information. Subsequently, Schottky type solar cell samples are fabricated on Si and Si NWs using ITO and Ag contacts. The junction properties are calculated using I-V curves in dark condition and the solar cell I-V characteristics are obtained under incident of the standardized light of AM1.5. The results for the two mentioned Schottky solar cell samples are compared and discussed. An improvement in short circuit current and efficiency of Schottky solar cell is found when Si nanowires are employed.

Plasma deposition of amorphous silicon-based materials

CERN Document Server

Bruno, Giovanni; Madan, Arun

1995-01-01

Semiconductors made from amorphous silicon have recently become important for their commercial applications in optical and electronic devices including FAX machines, solar cells, and liquid crystal displays. Plasma Deposition of Amorphous Silicon-Based Materials is a timely, comprehensive reference book written by leading authorities in the field. This volume links the fundamental growth kinetics involving complex plasma chemistry with the resulting semiconductor film properties and the subsequent effect on the performance of the electronic devices produced. Key Features * Focuses on the plasma chemistry of amorphous silicon-based materials * Links fundamental growth kinetics with the resulting semiconductor film properties and performance of electronic devices produced * Features an international group of contributors * Provides the first comprehensive coverage of the subject, from deposition technology to materials characterization to applications and implementation in state-of-the-art devices.

Multivariate data analysis of process control data from neutron transmutation doping of silicon

DEFF Research Database (Denmark)

Heydorn, K.; Hegaard, N.

1994-01-01

Final resistivities obtained by neutron transmutation doping (NTD) of silicon can be measured only after an annealing process has been carried out at the manufacturer's plant. The reactor centre carrying out the neutron doping process by irradiation under selected conditions must control the proc......Final resistivities obtained by neutron transmutation doping (NTD) of silicon can be measured only after an annealing process has been carried out at the manufacturer's plant. The reactor centre carrying out the neutron doping process by irradiation under selected conditions must control...

Low energy production processes in manufacturing of silicon solar cells

Science.gov (United States)

Kirkpatrick, A. R.

1976-01-01

Ion implantation and pulsed energy techniques are being combined for fabrication of silicon solar cells totally under vacuum and at room temperature. Simplified sequences allow very short processing times with small process energy consumption. Economic projections for fully automated production are excellent.

Amorphous silicon radiation detectors

Science.gov (United States)

Street, Robert A.; Perez-Mendez, Victor; Kaplan, Selig N.

1992-01-01

Hydrogenated amorphous silicon radiation detector devices having enhanced signal are disclosed. Specifically provided are transversely oriented electrode layers and layered detector configurations of amorphous silicon, the structure of which allow high electric fields upon application of a bias thereby beneficially resulting in a reduction in noise from contact injection and an increase in signal including avalanche multiplication and gain of the signal produced by incoming high energy radiation. These enhanced radiation sensitive devices can be used as measuring and detection means for visible light, low energy photons and high energy ionizing particles such as electrons, x-rays, alpha particles, beta particles and gamma radiation. Particular utility of the device is disclosed for precision powder crystallography and biological identification.

Origin of the visible emission of black silicon microstructures

International Nuclear Information System (INIS)

Fabbri, Filippo; Lin, Yu-Ting; Bertoni, Giovanni; Rossi, Francesca; Salviati, Giancarlo; Smith, Matthew J.; Gradečak, Silvija; Mazur, Eric

2015-01-01

Silicon, the mainstay semiconductor in microelectronics, is considered unsuitable for optoelectronic applications due to its indirect electronic band gap that limits its efficiency as light emitter. Here, we univocally determine at the nanoscale the origin of visible emission in microstructured black silicon by cathodoluminescence spectroscopy and imaging. We demonstrate the formation of amorphous silicon oxide microstructures with a white emission. The white emission is composed by four features peaking at 1.98 eV, 2.24 eV, 2.77 eV, and 3.05 eV. The origin of such emissions is related to SiO x intrinsic point defects and to the sulfur doping due to the laser processing. Similar results go in the direction of developing optoelectronic devices suitable for silicon-based circuitry

Silicon wafers for integrated circuit process

OpenAIRE

Leroy , B.

1986-01-01

Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

Cross two photon absorption in a silicon photonic crystal waveguide fiber taper coupler with a physical junction

Energy Technology Data Exchange (ETDEWEB)

Sarkissian, Raymond, E-mail: RaymondSark@gmail.com; O' Brien, John [Electrophysics department, University of Southern California, Los Angeles, California 90089 (United States)

2015-01-21

Cross two photon absorption in silicon is characterized using a tapered fiber photonic crystal silicon waveguide coupler. There is a physical junction between the tapered fiber and the waveguide constituting a stand-alone device. This device is used to obtain the spectrum for cross two photon absorption coefficient per unit volume of interaction between photons of nondegenerate energy. The corresponding Kerr coefficient per unit volume of interaction is also experimentally extracted. The thermal resistance of the device is also experimentally determined and the response time of the device is estimated for on-chip all-optical signal processing and data transfer between optical signals of different photon energies.

High Growth Rate Deposition of Hydrogenated Amorphous Silicon-Germanium Films and Devices Using ECR-PECVD

Energy Technology Data Exchange (ETDEWEB)

Liu, Yong [Iowa State Univ., Ames, IA (United States)

2002-01-01

Hydrogenated amorphous silicon germanium films (a-SiGe:H) and devices have been extensively studied because of the tunable band gap for matching the solar spectrum and mature the fabrication techniques. a-SiGe:H thin film solar cells have great potential for commercial manufacture because of very low cost and adaptability to large-scale manufacturing. Although it has been demonstrated that a-SiGe:H thin films and devices with good quality can be produced successfully, some issues regarding growth chemistry have remained yet unexplored, such as the hydrogen and inert-gas dilution, bombardment effect, and chemical annealing, to name a few. The alloying of the SiGe introduces above an order-of-magnitude higher defect density, which degrades the performance of the a-SiGe:H thin film solar cells. This degradation becomes worse when high growth-rate deposition is required. Preferential attachment of hydrogen to silicon, clustering of Ge and Si, and columnar structure and buried dihydride radicals make the film intolerably bad. The work presented here uses the Electron-Cyclotron-Resonance Plasma-Enhanced Chemical Vapor Deposition (ECR-PECVD) technique to fabricate a-SiGe:H films and devices with high growth rates. Helium gas, together with a small amount of H₂, was used as the plasma species. Thickness, optical band gap, conductivity, Urbach energy, mobility-lifetime product, I-V curve, and quantum efficiency were characterized during the process of pursuing good materials. The microstructure of the a-(Si,Ge):H material was probed by Fourier-Transform Infrared spectroscopy. They found that the advantages of using helium as the main plasma species are: (1) high growth rate--the energetic helium ions break the reactive gas more efficiently than hydrogen ions; (2) homogeneous growth--heavy helium ions impinging on the surface promote the surface mobility of the reactive radicals, so that heteroepitaxy growth as clustering of Ge and Si, columnar structure are

Confocal imaging of protein distributions in porous silicon optical structures

International Nuclear Information System (INIS)

De Stefano, Luca; D'Auria, Sabato

2007-01-01

The performances of porous silicon optical biosensors depend strongly on the arrangement of the biological probes into their sponge-like structures: it is well known that in this case the sensing species do not fill the pores but instead cover their internal surface. In this paper, the direct imaging of labelled proteins into different porous silicon structures by using a confocal laser microscope is reported. The distribution of the biological matter in the nanostructured material follows a Gaussian behaviour which is typical of the diffusion process in the porous media but with substantial differences between a porous silicon monolayer and a multilayer such as a Bragg mirror. Even if semi-quantitative, the results can be very useful in the design of the porous silicon based biosensing devices

High performance SONOS flash memory with in-situ silicon nanocrystals embedded in silicon nitride charge trapping layer

Science.gov (United States)

Lim, Jae-Gab; Yang, Seung-Dong; Yun, Ho-Jin; Jung, Jun-Kyo; Park, Jung-Hyun; Lim, Chan; Cho, Gyu-seok; Park, Seong-gye; Huh, Chul; Lee, Hi-Deok; Lee, Ga-Won

2018-02-01

In this paper, SONOS-type flash memory device with highly improved charge-trapping efficiency is suggested by using silicon nanocrystals (Si-NCs) embedded in silicon nitride (SiNX) charge trapping layer. The Si-NCs were in-situ grown by PECVD without additional post annealing process. The fabricated device shows high program/erase speed and retention property which is suitable for multi-level cell (MLC) application. Excellent performance and reliability for MLC are demonstrated with large memory window of ∼8.5 V and superior retention characteristics of 7% charge loss for 10 years. High resolution transmission electron microscopy image confirms the Si-NC formation and the size is around 1-2 nm which can be verified again in X-ray photoelectron spectroscopy (XPS) where pure Si bonds increase. Besides, XPS analysis implies that more nitrogen atoms make stable bonds at the regular lattice point. Photoluminescence spectra results also illustrate that Si-NCs formation in SiNx is an effective method to form deep trap states.

Non-fossil reduction materials in the silicon process - properties and behaviour

Energy Technology Data Exchange (ETDEWEB)

Myrhaug, Edin Henrik

2003-07-01

The purpose of this work has been to clarify the effect of using biocarbon as a reduction material in the silicon process. It was decided to compare the biocarbon with fossil carbon and find possible differences both on process performance and eventually on product quality. The elements in the raw materials added to the silicon process goes into three different products: silicon metal, silica dust and into open air. Based on analysis of raw materials and of produced silicon metal and microsilica extensive material balances have been established. One important result from these are the distribution factors that indicate how much of the trace elements that goes into each medium. Another result is that the boiling point of an element or a compound gives a good indication of were it ends. A high boiling point indicates that the element ends up in the silicon metal, while a low boiling point indicates that the element goes with off-gas into air. With an intermediate boiling point, the element goes into the silica dust. The SiO-reactivity of the reduction materials are commonly acknowledged to affect strongly the productivity and consumption figures of the silicon process. Based on data from thermogravimetric experiments with chemical reaction between carbonaceous spheres and SiO-gas, kinetic parameters have been estimated from the shrinking core model for some selected reduction materials of various sizes and spanning a wide range of SiO-reactivity figures. This model describes the degree of conversion versus time for a single sphere where the chemical reaction progresses in a topochemical manner from the outer surface of the solid towards the centre forming a porous product layer around an unreacted shrinking core. This behaviour is for the selected reduction materials to a large extent supported by an investigation of cross section pictures of fully and 50% converted spheres obtained with a microprobe. The estimated kinetic parameters obtained from the

Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process

Science.gov (United States)

McKee, Rodney A.; Walker, Frederick J.

1993-01-01

A process and structure involving a silicon substrate utilizes an ultra high vacuum and molecular beam epitaxy (MBE) methods to grow an epitaxial oxide film upon a surface of the substrate. As the film is grown, the lattice of the compound formed at the silicon interface becomes stabilized, and a base layer comprised of an oxide having a sodium chloride-type lattice structure grows epitaxially upon the compound so as to cover the substrate surface. A perovskite may then be grown epitaxially upon the base layer to render a product which incorporates silicon, with its electronic capabilities, with a perovskite having technologically-significant properties of its own.

77 FR 51571 - Certain Wireless Communication Devices, Portable Music and Data Processing Devices, Computers...

Science.gov (United States)

2012-08-24

... Music and Data Processing Devices, Computers, and Components Thereof; Notice of Receipt of Complaint... complaint entitled Wireless Communication Devices, Portable Music and Data Processing Devices, Computers..., portable music and data processing devices, computers, and components thereof. The complaint names as...

Back contact to film silicon on metal for photovoltaic cells

Science.gov (United States)

Branz, Howard M.; Teplin, Charles; Stradins, Pauls

2013-06-18

A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.

Composite silicon nanostructure arrays fabricated on optical fibre by chemical etching of multicrystal silicon film

International Nuclear Information System (INIS)

Zuo, Zewen; Zhu, Kai; Ning, Lixin; Cui, Guanglei; Qu, Jun; Huang, Wanxia; Shi, Yi; Liu, Hong

2015-01-01

Integrating nanostructures onto optical fibers presents a promising strategy for developing new-fashioned devices and extending the scope of nanodevices’ applications. Here we report the first fabrication of a composite silicon nanostructure on an optical fiber. Through direct chemical etching using an H 2 O 2 /HF solution, multicrystal silicon films with columnar microstructures are etched into a vertically aligned, inverted-cone-like nanorod array embedded in a nanocone array. A faster dissolution rate of the silicon at the void-rich boundary regions between the columns is found to be responsible for the separation of the columns, and thus the formation of the nanostructure array. The morphology of the nanorods primarily depends on the microstructure of the columns in the film. Through controlling the microstructure of the as-grown film and the etching parameters, the structural control of the nanostructure is promising. This fabrication method can be extended to a larger length scale, and it even allows roll-to-roll processing. (paper)

Composite silicon nanostructure arrays fabricated on optical fibre by chemical etching of multicrystal silicon film.

Science.gov (United States)

Zuo, Zewen; Zhu, Kai; Ning, Lixin; Cui, Guanglei; Qu, Jun; Huang, Wanxia; Shi, Yi; Liu, Hong

2015-04-17

Integrating nanostructures onto optical fibers presents a promising strategy for developing new-fashioned devices and extending the scope of nanodevices' applications. Here we report the first fabrication of a composite silicon nanostructure on an optical fiber. Through direct chemical etching using an H2O2/HF solution, multicrystal silicon films with columnar microstructures are etched into a vertically aligned, inverted-cone-like nanorod array embedded in a nanocone array. A faster dissolution rate of the silicon at the void-rich boundary regions between the columns is found to be responsible for the separation of the columns, and thus the formation of the nanostructure array. The morphology of the nanorods primarily depends on the microstructure of the columns in the film. Through controlling the microstructure of the as-grown film and the etching parameters, the structural control of the nanostructure is promising. This fabrication method can be extended to a larger length scale, and it even allows roll-to-roll processing.

Non-logic devices in logic processes

CERN Document Server

Ma, Yanjun

2017-01-01

This book shows readers how to design semiconductor devices using the most common and lowest cost logic CMOS processes.  Readers will benefit from the author’s extensive, industrial experience and the practical approach he describes for designing efficiently semiconductor devices that typically have to be implemented using specialized processes that are expensive, time-consuming, and low-yield. The author presents an integrated picture of semiconductor device physics and manufacturing techniques, as well as numerous practical examples of device designs that are tried and true.

Near-infrared free carrier absorption in heavily doped silicon

International Nuclear Information System (INIS)

Baker-Finch, Simeon C.; McIntosh, Keith R.; Yan, Di; Fong, Kean Chern; Kho, Teng C.

2014-01-01

Free carrier absorption in heavily doped silicon can have a significant impact on devices operating in the infrared. In the near infrared, the free carrier absorption process can compete with band to band absorption processes, thereby reducing the number of available photons to optoelectronic devices such as solar cells. In this work, we fabricate 18 heavily doped regions by phosphorus and boron diffusion into planar polished silicon wafers; the simple sample structure facilitates accurate and precise measurement of the free carrier absorptance. We measure and model reflectance and transmittance dispersion to arrive at a parameterisation for the free carrier absorption coefficient that applies in the wavelength range between 1000 and 1500 nm, and the range of dopant densities between ∼10 18 and 3 × 10 20  cm −3 . Our measurements indicate that previously published parameterisations underestimate the free carrier absorptance in phosphorus diffusions. On the other hand, published parameterisations are generally consistent with our measurements and model for boron diffusions. Our new model is the first to be assigned uncertainty and is well-suited to routine device analysis

Impurity effects in silicon for high efficiency solar cells

Science.gov (United States)

Hopkins, R. H.; Rohatgi, A.

1986-01-01

Model analyses indicate that sophisticated solar cell designs including, e.g., back surface fields, optical reflectors, surface passivation, and double layer antireflective coatings can produce devices with conversion efficiencies above 20 percent (AM1). To realize this potential, the quality of the silicon from which the cells are made must be improved; and these excellent electrical properties must be maintained during device processing. As the cell efficiency rises, the sensitivity to trace contaminants also increases. For example, the threshold Ti impurity concentration at which cell performance degrades is more than an order of magnitude lower for an 18-percent cell. Similar behavior occurs for numerous other metal species which introduce deep level traps that stimulate the recombination of photogenerated carriers in silicon. Purification via crystal growth in conjunction with gettering steps to preserve the large diffusion length of the as-grown material can lead to the production of devices with efficiencies aboved 18 percent, as has been verified experimentally.

The Effects of Thermal Cycling on Gallium Nitride and Silicon Carbide Semiconductor Devices for Aerospace Use

Science.gov (United States)

Patterson, Richard L.; Hammoud, Ahmad

2012-01-01

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These Include radiation, extreme temperatures, thermal cycling, to name a few. Preliminary data obtained on new Gallium Nitride and Silicon Carbide power devices under exposure to radiation followed by long term thermal cycling are presented. This work was done in collaboration with GSFC and JPL in support of the NASA Electronic Parts and Packaging (NEPP) Program

Direct current microhollow cathode discharges on silicon devices operating in argon and helium

Science.gov (United States)

Michaud, R.; Felix, V.; Stolz, A.; Aubry, O.; Lefaucheux, P.; Dzikowski, S.; Schulz-von der Gathen, V.; Overzet, L. J.; Dussart, R.

2018-02-01

Microhollow cathode discharges have been produced on silicon platforms using processes usually used for MEMS fabrication. Microreactors consist of 100 or 150 μm-diameter cavities made from Ni and SiO2 film layers deposited on a silicon substrate. They were studied in the direct current operating mode in two different geometries: planar and cavity configuration. Currents in the order of 1 mA could be injected in microdischarges operating in different gases such as argon and helium at a working pressure between 130 and 1000 mbar. When silicon was used as a cathode, the microdischarge operation was very unstable in both geometry configurations. Strong current spikes were produced and the microreactor lifetime was quite short. We evidenced the fast formation of blisters at the silicon surface which are responsible for the production of these high current pulses. EDX analysis showed that these blisters are filled with argon and indicate that an implantation mechanism is at the origin of this surface modification. Reversing the polarity of the microdischarge makes the discharge operate stably without current spikes, but the discharge appearance is quite different from the one obtained in direct polarity with the silicon cathode. By coating the silicon cathode with a 500 nm-thick nickel layer, the microdischarge becomes very stable with a much longer lifetime. No current spikes are observed and the cathode surface remains quite smooth compared to the one obtained without coating. Finally, arrays of 76 and 576 microdischarges were successfully ignited and studied in argon. At a working pressure of 130 mbar, all microdischarges are simultaneously ignited whereas they ignite one by one at higher pressure.

Key Success Factors and Future Perspective of Silicon-Based Solar Cells

Directory of Open Access Journals (Sweden)

S. Binetti

2013-01-01

Full Text Available Today, after more than 70 years of continued progress on silicon technology, about 85% of cumulative installed photovolatic (PV modules are based on crystalline silicon (c-Si. PV devices based on silicon are the most common solar cells currently being produced, and it is mainly due to silicon technology that the PV has grown by 40% per year over the last decade. An additional step in the silicon solar cell development is ongoing, and it is related to a further efficiency improvement through defect control, device optimization, surface modification, and nanotechnology approaches. This paper attempts to briefly review the most important advances and current technologies used to produce crystalline silicon solar devices and in the meantime the most challenging and promising strategies acting to increase the efficiency to cost/ratio of silicon solar cells. Eventually, the impact and the potentiality of using a nanotechnology approach in a silicon-based solar cell are also described.

Bis(tri-n-hexylsilyl oxide) silicon phthalocyanine: a unique additive in ternary bulk heterojunction organic photovoltaic devices.

Science.gov (United States)

Lessard, Benoît H; Dang, Jeremy D; Grant, Trevor M; Gao, Dong; Seferos, Dwight S; Bender, Timothy P

2014-09-10

Previous studies have shown that the use of bis(tri-n-hexylsilyl oxide) silicon phthalocyanine ((3HS)2-SiPc) as an additive in a P3HT:PC61BM cascade ternary bulk heterojunction organic photovoltaic (BHJ OPV) device results in an increase in the short circuit current (J(SC)) and efficiency (η(eff)) of up to 25% and 20%, respectively. The previous studies have attributed the increase in performance to the presence of (3HS)2-SiPc at the BHJ interface. In this study, we explored the molecular characteristics of (3HS)2-SiPc which makes it so effective in increasing the OPV device J(SC) and η(eff. Initially, we synthesized phthalocyanine-based additives using different core elements such as germanium and boron instead of silicon, each having similar frontier orbital energies compared to (3HS)2-SiPc and tested their effect on BHJ OPV device performance. We observed that addition of bis(tri-n-hexylsilyl oxide) germanium phthalocyanine ((3HS)2-GePc) or tri-n-hexylsilyl oxide boron subphthalocyanine (3HS-BsubPc) resulted in a nonstatistically significant increase in JSC and η(eff). Secondly, we kept the silicon phthalocyanine core and substituted the tri-n-hexylsilyl solubilizing groups with pentadecyl phenoxy groups and tested the resulting dye in a BHJ OPV. While an increase in JSC and η(eff) was observed at low (PDP)2-SiPc loadings, the increase was not as significant as (3HS)2-SiPc; therefore, (3HS)2-SiPc is a unique additive. During our study, we observed that (3HS)2-SiPc had an extraordinary tendency to crystallize compared to the other compounds in this study and our general experience. On the basis of this observation, we have offered a hypothesis that when (3HS)2-SiPc migrates to the P3HT:PC61BM interface the reason for its unique performance is not solely due to its frontier orbital energies but also might be due to a high driving force for crystallization.

Breakdown study of dc silicon micro-discharge devices

International Nuclear Information System (INIS)

Schwaederlé, L; Kulsreshath, M K; Lefaucheux, P; Tillocher, T; Dussart, R; Overzet, L J

2012-01-01

The influence of geometrical and operating parameters on the electrical characteristics of dc microcavity discharges provides insight into their controlling physics. We present here results of such a study on silicon-based microcavity discharge devices carried out in helium at pressure ranging from 100 to 1000 Torr. Different micro-reactor configurations were measured. The differences include isolated single cavities versus arrays of closely spaced cavities, various cavity geometries (un-etched as well as isotropically and anisotropically etched), various dimensions (100 or 150 µm cavity diameter and 0-150 µm depth). The electrode gap was kept constant in all cases at approximately 6 µm. The applied electric field reaches 5 × 10 7 V m -1 which results in current and power densities up to 2 A cm -2 and 200 kW cm -3 , respectively. The number of microcavities and the microcavity depth are shown to be the most important geometrical parameters for predicting breakdown and operation of microcavity devices. The probability of initiatory electron generation which is volume dependent and the electric field strength which is depth dependent are, respectively, considered to be responsible. The cavity shape (isotropic/anisotropic) and diameter had no significant influence. The number of micro-discharges that could be ignited depends on the rate of voltage rise and pressure. Larger numbers ignite at lower frequency and pressure. In addition, the voltage polarity has the largest influence on the electrical characteristics of the micro-discharge of all parameters, which is due to both the asymmetric role of electrodes as electron emitter and the non-uniformity of the electric field resulting in different ionization efficiencies. The qualitative shape of all breakdown voltage versus pressure curves can be explained in terms of the distance over which the discharge breakdown effectively occurs as long as one understand that this distance can depend on pressure. (paper)

High-efficiency power transfer for silicon-based photonic devices

Science.gov (United States)

Son, Gyeongho; Yu, Kyoungsik

2018-02-01

We demonstrate an efficient coupling of guided light of 1550 nm from a standard single-mode optical fiber to a silicon waveguide using the finite-difference time-domain method and propose a fabrication method of tapered optical fibers for efficient power transfer to silicon-based photonic integrated circuits. Adiabatically-varying fiber core diameters with a small tapering angle can be obtained using the tube etching method with hydrofluoric acid and standard single-mode fibers covered by plastic jackets. The optical power transmission of the fundamental HE11 and TE-like modes between the fiber tapers and the inversely-tapered silicon waveguides was calculated with the finite-difference time-domain method to be more than 99% at a wavelength of 1550 nm. The proposed method for adiabatic fiber tapering can be applied in quantum optics, silicon-based photonic integrated circuits, and nanophotonics. Furthermore, efficient coupling within the telecommunication C-band is a promising approach for quantum networks in the future.

Development of thin pixel detectors on epitaxial silicon for HEP experiments

International Nuclear Information System (INIS)

Boscardin, Maurizio; Calvo, Daniela; Giacomini, Gabriele; Wheadon, Richard; Ronchin, Sabina; Zorzi, Nicola

2013-01-01

The foreseen luminosity of the new experiments in High Energy Physics will require that the innermost layer of vertex detectors will be able to sustain fluencies up to 10 16 n eq /cm 2 . Moreover, in many experiments there is a demand for the minimization of the material budget of the detectors. Therefore, thin pixel devices fabricated on n-type silicon are a natural choice to fulfill these requirements due to their rad-hard performances and low active volume. We present an R and D activity aimed at developing a new thin hybrid pixel device in the framework of PANDA experiments. The detector of this new device is a p-on-n pixel sensor realized starting from epitaxial silicon wafers and back thinned up to 50–100 μm after process completion. We present the main technological steps and some electrical characterization on the fabricated devices before and after back thinning and after bump bonding to the front-end electronics

Development of thin pixel detectors on epitaxial silicon for HEP experiments

Energy Technology Data Exchange (ETDEWEB)

Boscardin, Maurizio, E-mail: boscardi@fbk.eu [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy); Calvo, Daniela [INFN and Dipartimento di Fisica, Università di Torino, Via Pietro Giuria, I-10125 Torino (Italy); Giacomini, Gabriele [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy); Wheadon, Richard [INFN and Dipartimento di Fisica, Università di Torino, Via Pietro Giuria, I-10125 Torino (Italy); Ronchin, Sabina; Zorzi, Nicola [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy)

2013-08-01

The foreseen luminosity of the new experiments in High Energy Physics will require that the innermost layer of vertex detectors will be able to sustain fluencies up to 10{sup 16} n{sub eq}/cm{sup 2}. Moreover, in many experiments there is a demand for the minimization of the material budget of the detectors. Therefore, thin pixel devices fabricated on n-type silicon are a natural choice to fulfill these requirements due to their rad-hard performances and low active volume. We present an R and D activity aimed at developing a new thin hybrid pixel device in the framework of PANDA experiments. The detector of this new device is a p-on-n pixel sensor realized starting from epitaxial silicon wafers and back thinned up to 50–100 μm after process completion. We present the main technological steps and some electrical characterization on the fabricated devices before and after back thinning and after bump bonding to the front-end electronics.

Nonlinear electrical properties of Si three-terminal junction devices

DEFF Research Database (Denmark)

Fantao, Meng; Jie, Sun; Graczyk, Mariusz

2010-01-01

This letter reports on the realization and characterization of silicon three-terminal junction devices made in a silicon-on-insulator wafer. Room temperature electrical measurements show that the fabricated devices exhibit pronounced nonlinear electrical properties inherent to ballistic electron...... transport in a three-terminal ballistic junction (TBJ) device. The results show that room temperature functional TBJ devices can be realized in a semiconductor material other than high-mobility III-V semiconductor heterostructures and provide a simple design principle for compact silicon devices...

Fiscal 1983 Sunshine Program achievement report. Development for practical application of photovoltaic system (Verification of experimental low cost silicon refining - Development of technology for chlorosilane hydrogen-reduction process); 1983 nendo taiyoko hatsuden system jitsuyoka gijutsu kaihatsu seika hokokusho. Tei cost silicon jikken seisei kensho (Chlorosilane no suiso kangen kotei no gijutsu kaihatsu)

Energy Technology Data Exchange (ETDEWEB)

NONE

1984-03-01

The effort aims to develop a reactor and its peripheral devices and process management technology therefor and to develop chlorosilane hydrogen-reduction process technology as part of the endeavors to develop a low cost production process for silicon for photovoltaic cells for the purpose of building a model plant capable of approximately 10 tons/year in terms of SOG (spin on glass) silicon. A study is made of ten operations (total reaction time of 2,264 hours), and it turns out that the electric power consumption efficiency is near the initially planned value. The yield of Si is, however, but 16.5% which is lower than the initially planned value of 20%. The value is elevated to 18% by raising the reactor temperature. To prevent overcleaning, a reactor with its internal walls experimentally coated with SiC is tested. The problems with devices other than the reactor tube are extraction rendered difficult by anomalously grown granules and processing devices choked by Si powder contained in waste gas after reaction. The first problem is settled by modifying the extraction tube but the other still needs a remedy. The produced granules are found to be high in quality. The seed producing roll crusher is operated for a total of 92 hours yielding 857kg in total. (NEDO)

Subsurface damage mechanism of high speed grinding process in single crystal silicon revealed by atomistic simulations