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Sample records for programmable delay circuit

  1. Programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    Linstadt, E.

    1985-04-01

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  2. A programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    Linstadt, E.

    1985-01-01

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  3. Picosecond resolution programmable delay line

    International Nuclear Information System (INIS)

    Suchenek, Mariusz

    2009-01-01

    The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market. (technical design note)

  4. TECHNICAL DESIGN NOTE: Picosecond resolution programmable delay line

    Science.gov (United States)

    Suchenek, Mariusz

    2009-11-01

    The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market.

  5. Design and implementation of high-precision and low-jitter programmable delay circuitry

    International Nuclear Information System (INIS)

    Gao Yuan; Cui Ke; Zhang Hongfei; Luo Chunli; Yang Dongxu; Liang Hao; Wang Jian

    2011-01-01

    A programmable delay circuit design which has characteristics of high-precision, low-jitter, wide-programmable-range and low power is introduced. The delay circuitry uses the scheme which has two parts: the coarse delay and the fine delay that could be controlled separately. Using different coarse delay chip can reach different maximum programmable range. And the fine delay programmable chip has the minimum step which is down to 10 ps. The whole circuitry jitter will be less than 100 ps. The design has been successfully applied in Quantum Key Distribution experiment. (authors)

  6. The Limitations to Delay-Insensitivity in Asynchronous Circuits

    National Research Council Canada - National Science Library

    Martin, Alain J

    1990-01-01

    ... produced are delay-insensitive (DI). A digital circuit is DI when its correct operation is independent of the delays in operators and in the wires connecting the operators, except that the delays are finite and positive...

  7. Statistical delay estimation in digital circuits using VHDL

    Directory of Open Access Journals (Sweden)

    Milić Miljana Lj.

    2014-01-01

    Full Text Available The most important feature of modern integrated circuit is the speed. It depends on circuit's delay. For the design of high-speed digital circuits, it is necessary to evaluate delays in the earliest stages of design, thus making it easy to modify and redesign a circuit if it's too slow. This paper gives an approach for efficient delay estimation in the describing phase of the circuit design. The method can statistically estimate the minimum and maximum delay of all possible paths and signal transitions in the circuit, considering the practical implementation of circuits, and information about the parameters' tolerances. The method uses a VHDL description and is verified on ISCAS85 benchmark circuits. Matlab was used for data processing.

  8. Programmable delay circuit for sparker signal analysis

    Digital Repository Service at National Institute of Oceanography (India)

    Pathak, D.

    The sparker echo signal had been recorded along with the EPC recorder trigger on audio cassettes in a dual channel analog recorder. The sparker signal in the analog form had to be digitised for further signal processing techniques to be performed...

  9. Heavy ions testing experimental results on programmable integrated circuits

    International Nuclear Information System (INIS)

    Velazco, R.; Provost-Grellier, A.

    1988-01-01

    The natural radiation environment in space has been shown to produce anomalies in satellite-borne microelectronics. It becomes then mandatory to define qualification strategies allowing to choose the less vulnerable circuits. In this paper, is presented a strategy devoted to one of the most critical effects, the soft errors (so called upset). The method addresses programmable integrated circuits i.e. circuits able to execute an instruction or command set. Experimental results on representative circuits will illustrate the approach. 11 refs [fr

  10. Design of delay insensitive circuits using multi-ring structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

    1992-01-01

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...

  11. Universal programmable quantum circuit schemes to emulate an operator

    Energy Technology Data Exchange (ETDEWEB)

    Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)

    2012-12-21

    Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

  12. Universal programmable quantum circuit schemes to emulate an operator

    International Nuclear Information System (INIS)

    Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre

    2012-01-01

    Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

  13. LHCb: Radiation hard programmable delay line for LHCb Calorimeter Upgrade

    CERN Multimedia

    Mauricio Ferre, J; Vilasís Cardona, X; Picatoste Olloqui, E; Machefert, F; Lefrançois, J; Duarte, O

    2013-01-01

    This poster describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with a 4ps jitter and 18ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35um technology.

  14. A programmable CCD driver circuit for multiphase CCD operation

    International Nuclear Information System (INIS)

    Ewin, A.J.; Reed, K.V.

    1989-01-01

    A programmable CCD driver circuit was designed to drive CCD's in multiphased modes. The purpose of the drive electronics was to operate developmental CCD imaging arrays for NASA's Moderate Resolution Imaging Spectrometer - Tiltable (MODIS-T). Five prototype arrays were designed. Valid's Graphics Editor (GED) was used to design the driver. With this driver design, any of the five arrays can be readout. Designing the driver with GED allowed functional simulation, timing verification, and certain packaging analyses to be done on the design before fabrication. The driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400 Kpixels/sec. Timing and packaging parameters were verified. the design uses 54 TTL component chips

  15. Hopf bifurcation analysis of Chen circuit with direct time delay feedback

    International Nuclear Information System (INIS)

    Hai-Peng, Ren; Wen-Chao, Li; Ding, Liu

    2010-01-01

    Direct time delay feedback can make non-chaotic Chen circuit chaotic. The chaotic Chen circuit with direct time delay feedback possesses rich and complex dynamical behaviours. To reach a deep and clear understanding of the dynamics of such circuits described by delay differential equations, Hopf bifurcation in the circuit is analysed using the Hopf bifurcation theory and the central manifold theorem in this paper. Bifurcation points and bifurcation directions are derived in detail, which prove to be consistent with the previous bifurcation diagram. Numerical simulations and experimental results are given to verify the theoretical analysis. Hopf bifurcation analysis can explain and predict the periodical orbit (oscillation) in Chen circuit with direct time delay feedback. Bifurcation boundaries are derived using the Hopf bifurcation analysis, which will be helpful for determining the parameters in the stabilisation of the originally chaotic circuit

  16. The ATPG Attack for Reverse Engineering of Combinational Hybrid Custom-Programmable Circuits

    Science.gov (United States)

    2017-03-23

    Introduction The widely practiced horizontal integrated circuit supply chain exposes a design to various types of attacks including the reverse engineering ...STT_CMOS designs for reverse- engineering prevention, DAC 2016. [5] M. E. Massad and et. al. Integrated circuit (IC) decamouflaging: reverse...The ATPG Attack for Reverse Engineering of Combinational Hybrid Custom-Programmable Circuits Raza Shafiq Hamid Mahmoodi Houman Homayoun Hassan

  17. Delay-area trade-off for MPRM circuits based on hybrid discrete particle swarm optimization

    International Nuclear Information System (INIS)

    Jiang Zhidi; Wang Zhenhai; Wang Pengjun

    2013-01-01

    Polarity optimization for mixed polarity Reed—Muller (MPRM) circuits is a combinatorial issue. Based on the study on discrete particle swarm optimization (DPSO) and mixed polarity, the corresponding relation between particle and mixed polarity is established, and the delay-area trade-off of large-scale MPRM circuits is proposed. Firstly, mutation operation and elitist strategy in genetic algorithm are incorporated into DPSO to further develop a hybrid DPSO (HDPSO). Then the best polarity for delay and area trade-off is searched for large-scale MPRM circuits by combining the HDPSO and a delay estimation model. Finally, the proposed algorithm is testified by MCNC Benchmarks. Experimental results show that HDPSO achieves a better convergence than DPSO in terms of search capability for large-scale MPRM circuits. (semiconductor integrated circuits)

  18. An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

    Directory of Open Access Journals (Sweden)

    Chao Chen

    2014-01-01

    Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

  19. Comparative Effects of Circuit Training Programme on Speed and ...

    African Journals Online (AJOL)

    Stratified random sampling technique was used to select 40 pre-menarceal and 40 postmenarcheal girls who were later randomly assigned to experimental and control groups. At the end of the training programme, 40 subjects completed the post training measurements, so there were 10 subjects in each of the four study ...

  20. Comparative Effects of Circuit Training Programme on Speed and ...

    African Journals Online (AJOL)

    cce

    the end of the training programme, 40 subjects completed the post training ... Speed is the rate of motion or velocity of the body or any of his part (Wilmore, 1977). ... Bulugbe (1991) reported improvement in running speed as a result of interval training. ..... The pre-menarcheal girls showed higher power performance than the ...

  1. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    International Nuclear Information System (INIS)

    Lashin, A. V.; Kozyrev, A. V.

    2015-01-01

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits

  2. A new time-digital convert circuit based on digital delay line

    International Nuclear Information System (INIS)

    Liu Haifeng; Guo Ying; Zhang Zhi

    2004-01-01

    An introduction of a new method of time-digital convert circuit based on digital delay line is given. High precision and good reliability can be realized when it is combined with traditional counting convert method in the measurement of large scale pulse width and low frequency self-excitation oscillator. (authors)

  3. Chaos in the fractional order logistic delay system: Circuit realization and synchronization

    International Nuclear Information System (INIS)

    Baskonus, Haci Mehmet; Hammouch, Zakia; Mekkaoui, Toufik; Bulut, Hasan

    2016-01-01

    In this paper, we present a numerical study and a circuit design to prove existence of chaos in the fractional order Logistic delay system. In addition, we investigate an active control synchronization scheme in this system. Numerical and cicruit simulations show the effectiveness and feasibility of this method.

  4. Practical programmable circuits a guide to PLDs, state machines, and microcontrollers

    CERN Document Server

    Broesch, James D

    1991-01-01

    This is a practical guide to programmable logic devices. It covers all devices related to PLD: PALs, PGAs, state machines, and microcontrollers. Usefulness is evaluated; support needed in order to effectively use the devices is discussed. All examples are based on real-world circuits.

  5. Universal file processing program for field programmable integrated circuits

    International Nuclear Information System (INIS)

    Freytag, D.R.; Nelson, D.J.

    1985-01-01

    A computer program is presented that translates logic equations into promburner files (or the reverse) for programmable logic devices of various kinds, namely PROMs FPLAs, FPLSs and PALs. The program achieves flexibility through the use of a database containing detailed information about the devices to be programmed. New devices can thus be accommodated through simple extensions of the database. When writing logic equations, the user can define logic combinations of signals as new logic variables for use in subsequent equations. This procedure yields compact and transparent expressions for logic operations, thus reducing the chances for error. A logic simulation program is also provided so that an independent check of the design can be performed at the software level

  6. Automatic test pattern generation for stuck-at and delay faults in combinational circuits

    International Nuclear Information System (INIS)

    Kim, Dae Sik

    1998-02-01

    The present studies are developed to propose the automatic test pattern generation (ATG) algorithms for combinational circuits. These ATG algorithms are realized in two ATG programs: One is the ATG program for stuck-at fault and the other one for delay faults. In order to accelerate the ATG process, these two ATG programs have a common feature (the search method based on the concept of the degree of freedom), whereas only ATG program for the delay fault utilizes the 19-valued logic, a type of composite valued logic. This difference between two ATG programs results from the difference of the target fault. Accelerating the ATG process is indispensable for improving the ATG algorithms. This acceleration is mainly achieved by reducing the number of the unnecessary backtrackings, making the earlier detection of the conflicts, and shortening the computation time between the implication. Because of this purpose, the developed ATG programs include the new search method based on the concept of the degree of freedom (DF). The DF concept, computed directly and easily from the system descriptions such as types of gates and their interconnections, is the criterion to decide which, among several alternate lines' logic values required along each path, promises to be the most effective in order to accelerate and improve the ATG process. This DF concept is utilized to develop and improve both of ATG programs for stuck-at and delay faults in combinational circuits. In addition to improving the ATG process, reducing number of test pattern is indispensable for testing the delay faults because the size of the delay faults grows rapidly as increasing the size of the circuit. In order to improve the compactness of the test set, 19-valued logic are derived. Unlike other TG logic systems, 19-valued logic is utilized to generate the robustly hazard-free test pattern. This is achieved by using the basic 5-valued logic, proposed in this work, where the transition with no hazard is

  7. On mill flow rate and fineness control in cement grinding circuits: instability and delayed measurements

    International Nuclear Information System (INIS)

    Lepore, R.; Boulvin, M.; Renotte, C.; Remy, M.

    1999-01-01

    A control structure for the mill flow rate and the product fineness is designed, with the feed flow rate and the classifier characteristic as the manipulated variables. Experimental results from a plant highlight the instability of the grinding circuit. A model previously developed by the authors stresses the major influence of the classifier nonlinearities onto this instability. A cascade control structure has been designed and implemented on site. The measurements of the product fineness, sensitive to material grindability fluctuations, are randomly time-delayed. The control structure uses a fineness estimator based on an adaptive scheme and a time delay compensator. (author)

  8. Estimation of leakage power and delay in CMOS circuits using parametric variation

    Directory of Open Access Journals (Sweden)

    Preeti Verma

    2016-09-01

    Full Text Available With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz at 400 mHz.

  9. A Novel Programmable CMOS Fuzzifiers Using Voltage-to-Current Converter Circuit

    Directory of Open Access Journals (Sweden)

    K. P. Abdulla

    2012-01-01

    Full Text Available This paper presents a new voltage-input, current-output programmable membership function generator circuit (MFC using CMOS technology. It employs a voltage-to-current converter to provide the required current bias for the membership function circuit. The proposed MFC has several advantageous features. This MFC can be reconfigured to perform triangular, trapezoidal, S-shape, Z-Shape, and Gaussian membership forms. This membership function can be programmed in terms of its width, slope, and its center locations in its universe of discourses. The easily adjustable characteristics of the proposed circuit and its accuracy make it suitable for embedded system and industrial control applications. The proposed MFC is designed using the spice software, and simulation results are obtained.

  10. SENARIET, A Programme To Solve Transient Flows Of Liquids In Complex Circuits

    Science.gov (United States)

    Vargas-Munoz, M.; Rodriguez-Fernandez, M.; Perena-Tapiador, A.

    2011-05-01

    SENARIET is a programme to study fluid transients in pipeline systems in order to obtain pressure and velocity distributions along a circuit. When a transient process occurs in periods of the same order of the pressure waves’ travelling time along a circuit (the order of the circuit length divided by the effective propagation speed), the compressibility effects in liquids have to be considered. Taking this effect into account, the appropriate equations of continuity and momentum are solved by the method of characteristics, to obtain pressure and velocity along pipes as a function of time. The simulated results have been compared to theoretical and experimental ones to validate and evaluate the precision of the software. The results help to perform efficient and accurate predictions in order to define the propulsion sub-system. This type of analysis is very important in order to evaluate the water hammer effects in propulsion systems used on spacecrafts and launchers.

  11. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    Science.gov (United States)

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  12. A high-resolution programmable Vernier delay generator based on carry chains in FPGA.

    Science.gov (United States)

    Cui, Ke; Li, Xiangyu; Zhu, Rihong

    2017-06-01

    This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 20  ° C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

  13. A high-resolution programmable Vernier delay generator based on carry chains in FPGA

    Science.gov (United States)

    Cui, Ke; Li, Xiangyu; Zhu, Rihong

    2017-06-01

    This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 2 0°C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

  14. 1.5V fully programmable CMOS Membership Function Generator Circuit with proportional DC-voltage control

    Directory of Open Access Journals (Sweden)

    C. Muñiz-Montero

    2013-06-01

    Full Text Available A Membership Function Generator Circuit (MFGC with bias supply of 1.5 Volts and independent DC-voltage programmable functionalities is presented. The realization is based on a programmable differential current mirror and three compact voltage-to-current converters, allowing continuous and quasi-linear adjustment of the center position, height, width and slopes of the triangular/trapezoidal output waveforms. HSPICE simulation results of the proposed circuit using the parameters of a double-poly, three metal layers, 0.5 μm CMOS technology validate the functionality of the proposed architecture, which exhibits a maximum deviation of the linearity in the programmability of 7 %.

  15. Programmable dispersion on a photonic integrated circuit for classical and quantum applications.

    Science.gov (United States)

    Notaros, Jelena; Mower, Jacob; Heuck, Mikkel; Lupo, Cosmo; Harris, Nicholas C; Steinbrecher, Gregory R; Bunandar, Darius; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

    2017-09-04

    We demonstrate a large-scale tunable-coupling ring resonator array, suitable for high-dimensional classical and quantum transforms, in a CMOS-compatible silicon photonics platform. The device consists of a waveguide coupled to 15 ring-based dispersive elements with programmable linewidths and resonance frequencies. The ability to control both quality factor and frequency of each ring provides an unprecedented 30 degrees of freedom in dispersion control on a single spatial channel. This programmable dispersion control system has a range of applications, including mode-locked lasers, quantum key distribution, and photon-pair generation. We also propose a novel application enabled by this circuit - high-speed quantum communications using temporal-mode-based quantum data locking - and discuss the utility of the system for performing the high-dimensional unitary optical transformations necessary for a quantum data locking demonstration.

  16. Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS and LHC Transverse Dampers

    CERN Document Server

    Rossi, V

    2002-01-01

    In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC-type beams circulating in t...

  17. A SHORT-TERM CIRCUIT RESISTANCE PROGRAMME REDUCED EPICARDIAL FAT IN OBESE AGED WOMEN.

    Science.gov (United States)

    Rosety, Miguel Angel; Pery, Maria Teresa; Rodriguez-Pareja, Maria Antonia; Diaz, Antonio; Rosety, Jesus; Garcia, Natalia; Brenes-Martin, Francisco; Rosety-Rodríguez, Manuel; Toro, Rocío; Ordoñez, Francisco Javier; Rosety, Ignacio

    2015-11-01

    this study was conducted to ascertain the effects of resistance circuit training on epicardial adipose tissue (EAT) in obese aged women. A secondary objective was to assess muscle damage induced by supervised resistance training to confirm the intervention program was effective and safe. in the present interventional study, a total of 48 obese aged women were recruited from the community. Twenty-four of them were randomly assigned to perform a 12-week resistance circuit training programme, 3-days per week. This training was circularly performed in 6 stations: arm curl, leg extension, seated row, leg curl, triceps extension and leg press. The Jamar handgrip electronic dynamometer was used to assess maximal handgrip strength of the dominant hand. Two experienced observers assessed EAT by transthoracic two-dimensional echocardiography. Lastly, serum samples were analysed using one-step sandwich assays for creatine kinase activity (CK) and myoglobin (MB) concentration. as was hypothesized, resistance training significantly reduced EAT thickness (8.4 ± 1.0 vs. 7.3 ± 1.3 mm; p = 0.014; d = 0.76) in the experimental group. Resistance training induced no significant changes in markers of muscle damage such as CK (181.6 ± 36.9 vs. 194.2 ± 37.8 U/l; p = 0.31) and MB (62.4 ± 7.1 vs. 67.3 ± 7.7 ng/ml; p = 0.26). No significant changes in any of the tested outcomes were found in the control group. resistance training reduced EAT in aged obese women. A secondary finding was that the training program was effective and safe. While current results are promising, future studies are still required to consolidate this approach in clinical application. Copyright AULA MEDICA EDICIONES 2014. Published by AULA MEDICA. All rights reserved.

  18. A fortran programme for determining frequency responses for linear systems with time delays

    International Nuclear Information System (INIS)

    Milsom, P.R.

    1966-11-01

    In this report a digital computer programme for evaluating frequency responses is described. In its standard form the programme is capable of determining the gain and phase of up to 35 variables over a range of up to 30 frequencies for a system described by up to 65 equations. The equations must be either first order differential or algebraic and either type may include time delayed terms. Up to 50 such terms are permissible throughout the equation set. Provision is made for up to 10 inputs and up to 50 differentiated input terms are permitted throughout the equation set. However, it is possible for the user to increase a maximum dimension, albeit at the expense of another array dimension. In punching the data from the equations the user has no sorting or arranging of coefficients to do, and the equations may be in any order. The specifying of other input information, such as frequency range, the inputs to be perturbed and the variables for which frequency responses are required, is also very straightforward. (author)

  19. Small Delay and High Performance AD/DA Converters of Lease Circuit System for AM&FM Broadcast

    Science.gov (United States)

    Takato, Kenji; Suzuki, Dai; Ishii, Takashi; Kobayashi, Masato; Yamada, Hirokazu; Amano, Shigeru

    Many AM&FM broadcasting stations in Japan are connected by the leased circuit system of NTT. Small delay and high performance AD/DA converter was developed for the system. The system was designed based on ITU-T J.41 Recommendation (384kbps), the transmission signal is 11bit-32 kHz where the Gain-frequency characteristics between 40Hz to 15kHz have to be quite flat. The ΔΣAD/DA converter LSIs for audio application in the market today realize very high performance. However the performance is not enough for the leased circuit system. We found that it is not possible to meet the delay and Gain-frequency requirements only by using ΔΣAD/DA converter LSI in normal operation, because 15kHz the highest frequency and 16kHz Nyquist frequency are too close, therefore there are aliasing around Nyquist frequency. In this paper, we designed AD/DA architecture having small delay (1msec) and sharp cut off LPF (100dB attenuation at 16kHz, and 1500dB/Oct from 15kHz to 16kHz) by operating ΔΣAD/DA converter LSIs over-sampling rate such as 128kHz and by adding custom LPF designed Infinite Impulse Response (IIR) filter. The IIR filter is a 16th order elliptic type and it is consist of eight biquad filters in series. We described how to evaluate the stability of IIR filter theoretically by calculating frequency response, Pole and Zero Layout and impulse response of each biquad filter, and experimentally by adding overflow detection circuit on each filters and input overlord signal.

  20. Structural and composition investigations at delayered locations of low k integrated circuit device by gas-assisted focused ion beam

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Dandan, E-mail: dandan.wang@globalfoundries.com; Kee Tan, Pik; Yamin Huang, Maggie; Lam, Jeffrey; Mai, Zhihong [Technology Development Department, GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406 (Singapore)

    2014-05-15

    The authors report a new delayering technique – gas-assisted focused ion beam (FIB) method and its effects on the top layer materials of integrated circuit (IC) device. It demonstrates a highly efficient failure analysis with investigations on the precise location. After removing the dielectric layers under the bombardment of an ion beam, the chemical composition of the top layer was altered with the reduced oxygen content. Further energy-dispersive x-ray spectroscopy and Fourier transform infrared analysis revealed that the oxygen reduction lead to appreciable silicon suboxide formation. Our findings with structural and composition alteration of dielectric layer after FIB delayering open up a new insight avenue for the failure analysis in IC devices.

  1. A self-adjusting delay circuit for pixel read-out chips

    International Nuclear Information System (INIS)

    Raith, B.

    1997-01-01

    A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

  2. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  3. Loss-to-follow-up and delay to treatment initiation in Pakistan's national tuberculosis control programme.

    Science.gov (United States)

    Ali, Syed Mustafa; Naureen, Farah; Noor, Arif; Fatima, Irum; Viney, Kerri; Ishaq, Muhammad; Anjum, Naveed; Rashid, Aamna; Haider, Ghulam Rasool; Khan, Muhammad Aamir; Aamir, Javariya

    2018-03-09

    Researchers and policy-makers have identified loss to follow-up as a major programmatic problem. Therefore, the objective of this study is to quantify TB related pre-treatment loss to follow up and treatment delay in private sector health care facilities in Pakistan. This was a retrospective, descriptive cohort study using routinely collected programmatic data from TB referral, diagnosis and treatment registers. Data from 48 private healthcare facilities were collected using an online questionnaire prepared in ODK Collect, for the period October 2015 to March 2016. Data were analysed using SPSS. We calculated the: (1) number and proportion of patients who were lost to follow-up during the diagnostic period, (2) number and proportion of patients with pre-treatment loss to follow-up, and (3) the number of days between diagnosis and initiation of treatment. One thousand five hundred ninety-six persons with presumptive TB were referred to the laboratory. Of these, 96% (n = 1538) submitted an on-the-spot sputum sample. Of the 1538 people, 1462 (95%) people subsequently visited the laboratory to submit the early morning (i.e. the second) sample. Hence, loss to follow-up during the diagnostic process was 8% overall (n = 134). Of the 1462 people who submitted both sputum samples, 243 (17%) were diagnosed with sputum smear-positive pulmonary TB and 231 were registered for anti-TB treatment, hence, loss in the pre-treatment phase was 4.9% (n = 12). 152 persons with TB (66%) initiated TB treatment either on the day of TB diagnosis or the next day. A further 79 persons with TB (34%) commenced TB treatment within a mean time of 7 days (range 2 to 64 days). Concentrated efforts should be made by the National TB Control Programme to retain TB patients and innovative methods such as text reminders and behavior change communication may need to be used and tested.

  4. Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

    Science.gov (United States)

    Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

    2017-11-20

    A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

    Directory of Open Access Journals (Sweden)

    Mohammed Darmi

    2017-10-01

    Full Text Available As we increasingly use advanced technology nodes to design integrated circuits (ICs, physical designers and electronic design automation (EDA providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR. An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS and total negative slack (TNS improved up to 13% and 56%, respectively, compared to the baseline flow.

  6. Development of hybrid micro circuit based multi-channel programmable HV supply for BARC-pelletron experimental facility

    International Nuclear Information System (INIS)

    Manna, A.; Thombare, S.; Moitra, S.; Kuswarkar, M.; Punna, M.; Nair, P.M.; Diwakar, M.P.; Pithawa, C.K.

    2013-01-01

    Electronics Division, BARC has developed a Multi channel programmable HV bias supply system for charge particle detector array for use in BARC-TIFR Pelletron-LINAC facility. The HV supplies are compact in size due to use of hybrid micro-circuits developed indigenously and are modular in construction to achieve versatility, scalability and serviceability. All programming operations and monitoring are performed remotely through PC over Ethernet. Each supply has a built-in over voltage, over current and thermal overload protections for safe operation and employs a Zero Voltage Switching (ZVS) technique to reduce thermal stress on the inverter switches. This article describes salient design aspects and performance of the HV supply system. (author)

  7. A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

    Science.gov (United States)

    Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

    2010-01-01

    A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

  8. Electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and graphical user interface platform for aviation industries training purposes

    Science.gov (United States)

    Burhan, I.; Azman, A. A.; Othman, R.

    2016-10-01

    An electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and Visual Basic (VB) platform is fabricated as a supporting tool to existing teaching and learning process, and to achieve the objectives and learning outcomes towards enhancing the student's knowledge and hands-on skill, especially in electro pneumatic devices. The existing learning process for electro pneumatic courses conducted in the classroom does not emphasize on simulation and complex practical aspects. VB is used as the platform for graphical user interface (GUI) while PIC as the interface circuit between the GUI and hardware of electro pneumatic apparatus. Fabrication of electro pneumatic trainer interfacing between PIC and VB has been designed and improved by involving multiple types of electro pneumatic apparatus such as linear drive, air motor, semi rotary motor, double acting cylinder and single acting cylinder. Newly fabricated electro pneumatic trainer microcontroller interface can be programmed and re-programmed for numerous combination of tasks. Based on the survey to 175 student participants, 97% of the respondents agreed that the newly fabricated trainer is user friendly, safe and attractive, and 96.8% of the respondents strongly agreed that there is improvement in knowledge development and also hands-on skill in their learning process. Furthermore, the Lab Practical Evaluation record has indicated that the respondents have improved their academic performance (hands-on skills) by an average of 23.5%.

  9. Programme

    OpenAIRE

    Hobday, E, fl. 1905, artist

    2003-01-01

    A photograph of an illustrated programme listing dances. The illustration shows a snake charmer playing to a snake while another man watches. Buildings and trees can be seen behind a wall in the distance. In the lower right-hand corner of the programme is the signature 'E. Hobday'. The programme is almost certainly related to the Punjab Ball, Lahore. It is placed next to the Punjab Ball Menu in the album and the Menu is also illustrated by 'E. Hobday'.

  10. Analysis of the effects of time delay in clock recovery circuits based on Phase-locked loops

    DEFF Research Database (Denmark)

    Zibar, Darko; Oxenløwe, Leif Katsuo; Clausen, Anders

    2004-01-01

    Influence of time delay in a balanced optical phase-locked loops (OPLL) with a proportional integrator (Pl) filter is investigated using a delayed differential equation (DDE) is investigated. The limitations, which a time delay imposes on the Pl filter bandwidth, at increasing values of loop gain...

  11. Mitigating the Effects of Poverty and Crime: The Long-Term Effects of an Early Intervention Programme for Children Who Were Developmentally Delayed and Prenatally Exposed to Cocaine

    Science.gov (United States)

    Ullery, Mary Anne; Gonzalez, Antonio; Katz, Lynne

    2016-01-01

    This study explores the long-term impact on participation in the Linda Ray Intervention Program (LRIP) for children (n = 54) who were developmentally delayed and prenatally exposed to cocaine. By identifying a group of programme graduates from a high crime/high poverty neighbourhood in Miami-Dade County using ArcGIS 10.2 software, a…

  12. Pulse advancement and delay in an integrated optical two-port ring-resonator circuit: direct experimental observations

    NARCIS (Netherlands)

    Uranus, H.P.; Zhuang, L.; Roeloffzen, C.G.H.; Hoekstra, Hugo

    We report experimental observations of the negative-group-velocity (v_g) phenomenon in an integrated-optical two-port ring-resonator circuit. We demonstrate that when the v_g is negative, the (main) peak of output pulse appears earlier than the peak of a reference pulse, while for a positive v_g,

  13. A chaotic jerk system with non-hyperbolic equilibrium: Dynamics, effect of time delay and circuit realisation

    Science.gov (United States)

    Rajagopal, Karthikeyan; Pham, Viet-Thanh; Tahir, Fadhil Rahma; Akgul, Akif; Abdolmohammadi, Hamid Reza; Jafari, Sajad

    2018-04-01

    The literature on chaos has highlighted several chaotic systems with special features. In this work, a novel chaotic jerk system with non-hyperbolic equilibrium is proposed. The dynamics of this new system is revealed through equilibrium analysis, phase portrait, bifurcation diagram and Lyapunov exponents. In addition, we investigate the time-delay effects on the proposed system. Realisation of such a system is presented to verify its feasibility.

  14. arXiv A Programmable Delay Design for the sTGC Detector at the Upgraded New Small Wheel of the ATLAS Muon Spectrometer

    CERN Document Server

    INSPIRE-00225390; Guan, Liang; Chapman, John W; Zhou, Bing; Zhu, Junjie

    2017-11-01

    We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ∼ 3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. The approach is adaptable to other applications with similar phase shifting requirements. In addition, the design is resource efficient and is suitable for cost-effective digital implementation with a large number of channels.

  15. Multiuser remote access to distributed heterogeneous system of programmable logic based laboratory equipment for remote digital circuits design labs

    Directory of Open Access Journals (Sweden)

    Mikhail N. Yokhin

    2017-12-01

    Full Text Available The paper contains an analysis of perspective structures of software and hardware equipment of universal digital design laboratories with the purpose of enabling laboratory classes of digital circuit design to be taken remotely. Implementation characteristics and usage experience of some of those structures applied to labs on several hardware related courses of « Computer science and computer engineering» program in NRNU MEPhI are presented. The paper also considers different aspects of usage of remote access enabled laboratory which should be taken into account to substantiate laboratory configuration from technical and economical standpoints. To increase equipment usage efficiency an approach to group several distinct projects to place them on a single FPGA chip is proposed. The paper shows advisability and gives an example of parametrizable virtual stand for remote debugging of FPGA projects.

  16. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

    Science.gov (United States)

    Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-06-24

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  17. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

    Directory of Open Access Journals (Sweden)

    Chen Yang

    2017-06-01

    Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  18. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    International Nuclear Information System (INIS)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun

    2016-01-01

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD

  19. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun [KHNP CRI, Daejeon (Korea, Republic of)

    2016-10-15

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD.

  20. Cost-effectiveness of a structured progressive task-oriented circuit class training programme to enhance walking competency after stroke: The protocol of the FIT-Stroke trial

    Directory of Open Access Journals (Sweden)

    Roelse Hanneke

    2009-08-01

    Full Text Available Abstract Background Most patients who suffer a stroke experience reduced walking competency and health-related quality of life (HRQoL. A key factor in effective stroke rehabilitation is intensive, task-specific training. Recent studies suggest that intensive, patient-tailored training can be organized as a circuit with a series of task-oriented workstations. Primary aim of the FIT-Stroke trial is to evaluate the effects and cost-effectiveness of a structured, progressive task-oriented circuit class training (CCT programme, compared to usual physiotherapeutic care during outpatient rehabilitation in a rehabilitation centre. The task-oriented CCT will be applied in groups of 4 to 6 patients. Outcome will be defined in terms of gait and gait-related ADLs after stroke. The trial will also investigate the generalizability of treatment effects of task-oriented CCT in terms of perceived fatigue, anxiety, depression and perceived HRQoL. Methods/design The multicentre single-blinded randomized trial will include 220 stroke patients discharged to the community from inpatient rehabilitation, who are able to communicate and walk at least 10 m without physical, hands-on assistance. After discharge from inpatient rehabilitation, patients in the experimental group will receive task-oriented CCT two times a week for 12 weeks at the physiotherapy department of the rehabilitation centre. Control group patients will receive usual individual, face-to-face, physiotherapy. Costs will be evaluated by having each patient keep a cost diary for the first 24 weeks after randomisation. Primary outcomes are the mobility part of the Stroke Impact Scale (SIS-3.0 and the EuroQol. Secondary outcomes are the other domains of SIS-3.0, lower limb muscle strength, walking endurance, gait speed, balance, confidence not to fall, instrumental ADL, fatigue, anxiety, depression and HRQoL. Discussion Based on assumptions about the effect of intensity of practice and specificity of

  1. Delayed diagnosis of childhood deafness: the value of false negatives in the Programme for Early Detection of Neonatal Hearing Loss.

    Science.gov (United States)

    Martínez-Pacheco, María C; Ferrán de la Cierva, Luis; García-Purriños, Francisco J

    Despite its importance, the existence of false negatives (patients who are told they hear well, but they have some degree of hipacusia) is rarely evaluated in programs for early detection of hearing loss. The aim of this study is to determine the variables that can lead to a delayed diagnosis, especially the existence of false negatives and the lack of registration of risk factors. A retrospective study of prevalence has been carried out, in which the medical records of children diagnosed with sensorineural hearing loss born within 2005 and 2012 in the health centers of study have been analyzed. Of the 32 children with sensorineural hearing loss, 16 passed the OAE, 12 did not passed the OAE, and in four they were not carried out. Of the children who passed the OAE, 57% have severe hearing loss. 66% of children with hearing loss presented a risk factor for hearing loss at birth, being the most frecuent family history of hearing loss, but only 7% of those with family history of hearing loss were included in the risk group. The results of the study indicate that the late diagnosis of hearing loss is related to the presence of false negatives to the OAE and the non-registration of risk factors. Copyright © 2016 Elsevier España, S.L.U. and Sociedad Española de Otorrinolaringología y Cirugía de Cabeza y Cuello. All rights reserved.

  2. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    Science.gov (United States)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  3. Peak reading detector circuit

    International Nuclear Information System (INIS)

    Courtin, E.; Grund, K.; Traub, S.; Zeeb, H.

    1975-01-01

    The peak reading detector circuit serves for picking up the instants during which peaks of a given polarity occur in sequences of signals in which the extreme values, their time intervals, and the curve shape of the signals vary. The signal sequences appear in measuring the foetal heart beat frequence from amplitude-modulated ultrasonic, electrocardiagram, and blood pressure signals. In order to prevent undesired emission of output signals from, e. g., disturbing intermediate extreme values, the circuit consists of the series connections of a circuit to simulate an ideal diode, a strong unit, a discriminator for the direction of charging current, a time-delay circuit, and an electronic switch lying in the decharging circuit of the storage unit. The time-delay circuit thereby causes storing of a preliminary maximum value being used only after a certain time delay for the emission of the output signal. If a larger extreme value occurs during the delay time the preliminary maximum value is cleared and the delay time starts running anew. (DG/PB) [de

  4. Oscillator circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

  5. Measuring circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

  6. Computer programmes of the Power Research Institute for the analysis of processes in the primary coolant circuit and in the containment of a WWER plant in a loss-of-coolant accident

    International Nuclear Information System (INIS)

    Misak, J.

    1976-01-01

    A brief description is given of computer programmes for the analysis of loss-of-coolant accidents (LOCA) in WWER type reactors. The LENKA programme is intended for the thermal and hydraulic analysis of the consequences of such accidents in the primary coolant circuit. The SICHTA programme is intended for the detailed calculation of the time dependence of the axial and radial distribution of heat in fuel rods from steady-state to the flooding of the core. CHEMLOC is intended for the analysis of the heat history of the core and the extent of chemical reactions in LOCA when the emergency core cooling system is not operating. The TRACO I is intended for the analysis of the initial stage of the transient process in a full-pressure containment after LOCA (the computation of the time and spatial dependences of pressures and temperatures). TRACO III is intended for the computation of the long-term time dependence of pressure and temperature in the full-pressure containment after LOCA. (B.S.)

  7. WHO Parents Skills Training (PST) programme for children with developmental disorders and delays delivered by Family Volunteers in rural Pakistan: study protocol for effectiveness implementation hybrid cluster randomized controlled trial.

    Science.gov (United States)

    Hamdani, S U; Akhtar, P; Zill-E-Huma; Nazir, H; Minhas, F A; Sikander, S; Wang, D; Servilli, C; Rahman, A

    2017-01-01

    Development disorders and delays are recognised as a public health priority and included in the WHO mental health gap action programme (mhGAP). Parents Skills Training (PST) is recommended as a key intervention for such conditions under the WHO mhGAP intervention guide. However, sustainable and scalable delivery of such evidence based interventions remains a challenge. This study aims to evaluate the effectiveness and scaled-up implementation of locally adapted WHO PST programme delivered by family volunteers in rural Pakistan. The study is a two arm single-blind effectiveness implementation-hybrid cluster randomised controlled trial. WHO PST programme will be delivered by 'family volunteers' to the caregivers of children with developmental disorders and delays in community-based settings. The intervention consists of the WHO PST along with the WHO mhGAP intervention for developmental disorders adapted for delivery using the android application on a tablet device. A total of 540 parent-child dyads will be recruited from 30 clusters. The primary outcome is child's functioning, measured by WHO Disability Assessment Schedule - child version (WHODAS-Child) at 6 months post intervention. Secondary outcomes include children's social communication and joint engagement with their caregiver, social emotional well-being, parental health related quality of life, family empowerment and stigmatizing experiences. Mixed method will be used to collect data on implementation outcomes. Trial has been retrospectively registered at ClinicalTrials.gov (NCT02792894). This study addresses implementation challenges in the real world by incorporating evidence-based intervention strategies with social, technological and business innovations. If proven effective, the study will contribute to scaled-up implementation of evidence-based packages for public mental health in low resource settings. Registered with ClinicalTrials.gov as Family Networks (FaNs) for Children with Developmental

  8. Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

    CERN Document Server

    Bonacini, Sandro; Kloukinas, Kostas

    2007-01-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

  9. Precise delay measurement through combinatorial logic

    Science.gov (United States)

    Burke, Gary R. (Inventor); Chen, Yuan (Inventor); Sheldon, Douglas J. (Inventor)

    2010-01-01

    A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

  10. Multiple channel programmable coincidence counter

    Science.gov (United States)

    Arnone, Gaetano J.

    1990-01-01

    A programmable digital coincidence counter having multiple channels and featuring minimal dead time. Neutron detectors supply electrical pulses to a synchronizing circuit which in turn inputs derandomized pulses to an adding circuit. A random access memory circuit connected as a programmable length shift register receives and shifts the sum of the pulses, and outputs to a serializer. A counter is input by the adding circuit and downcounted by the seralizer, one pulse at a time. The decoded contents of the counter after each decrement is output to scalers.

  11. Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

    Science.gov (United States)

    Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

    2011-07-01

    This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

  12. Economic testing of large integrated switching circuits - a challenge to the test engineer

    International Nuclear Information System (INIS)

    Kreinberg, W.

    1978-01-01

    With reference to large integrated switching circuits, one can use an incoming standard programme test or the customer's switching circuits. The author describes the development of suitable, extensive and economical test programmes. (orig.) [de

  13. Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

    Science.gov (United States)

    Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

    2013-01-01

    This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

  14. Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

    Directory of Open Access Journals (Sweden)

    Santiago T. Pérez Suárez

    2013-12-01

    Full Text Available This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

  15. Hybdrid integral circuit for proportional chambers

    International Nuclear Information System (INIS)

    Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

    1978-01-01

    Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

  16. Estimating Delays In ASIC's

    Science.gov (United States)

    Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

    1994-01-01

    Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

  17. Optically controllable molecular logic circuits

    International Nuclear Information System (INIS)

    Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-01-01

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

  18. Vernier Delay Unit

    International Nuclear Information System (INIS)

    Pierce, W.B.

    1984-10-01

    This module will accept differential ECL pulses from the auxiliary rear panel or NIM level pulses from the front panel. The pulses are produced at the output with a fixed delay that is software programmable in steps of 0.1 ns over the range of 0.1 to 10.5 ns. Multiple outputs are available at the front panel. Minimum delay through the module is 9 ns

  19. Resonance circuits for adiabatic circuits

    Directory of Open Access Journals (Sweden)

    C. Schlachta

    2003-01-01

    Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

  20. Development of True Time Delay Circuits

    Science.gov (United States)

    2014-06-13

    public release Distribution is unlimited DATA SHEET SKY65014-70LF: 0.1-7.0 GHz InGaP Cascadable Amplifier Applications • Wireless infrastructure: WLAN ...decoupling network out of band. For low frequency applications , R1 may be used to conveniently limit supply current on the Evaluation Board. The Evaluation...additional information, refer to the Skyworks Application Note, Solder Reflow Information, document number 200164. Care must be taken when attaching this

  1. Electronic circuit encyclopedia 2

    International Nuclear Information System (INIS)

    Park, Sun Ho

    1992-10-01

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  2. Electronic circuit encyclopedia 2

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sun Ho

    1992-10-15

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  3. A new fast and programmable trigger logic

    International Nuclear Information System (INIS)

    Fucci, A.; Amendolia, S.R.; Bertolucci, E.; Bottigli, U.; Bradaschia, C.; Foa, L.; Giazotto, A.; Giorgi, M.; Givoletti, M.; Lucardesi, P.; Menzione, A.; Passuello, D.; Quaglia, M.; Ristori, L.; Rolandi, L.; Salvadori, P.; Scribano, A.; Stanga, R.; Stefanini, A.; Vincelli, M.L.

    1977-01-01

    The NA1 (FRAMM) experiment, under construction for the CERN-SPS North Area, deals with more than 1000 counter signals which have to be combined together in order to build sophisticated and highly selective triggers. These requirements have led to the development of a low cost, combinatorial, fast electronics which can replace, in an advantageous way the standard NIM electronics at the trigger level. The essential performances of the basic circuit are: 1) programmability of any desired logical expression; 2) trigger time independent of the chosen expression; 3) reduced cost and compactness due to the use of commercial RAMs, PROMs, and PLAs; 4) short delay, less than 20 ns, between input and output pulses. (Auth.)

  4. Analog circuit design and field programmable gat

    Indian Academy of Sciences (India)

    HAMID REZA ABDOLMOHAMMADI

    2018-04-30

    Apr 30, 2018 ... 1Department of Electrical Engineering, Golpayegan University of ... 4Department of Electrical and Communication Engineering, The Papua New Guinea University of ... because of its effective and easy implementation as it.

  5. Flexible programmable logic module

    Science.gov (United States)

    Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

    2001-01-01

    The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

  6. Programmable dc motor controller

    Science.gov (United States)

    Hopwood, J. E.

    1982-11-01

    A portable programmable dc motor controller, with features not available on commercial instruments was developed for controlling fixtures during welding processes. The controller can be used to drive any dc motor having tachometer feedback and motor requirements not exceeding 30 volts, 3 amperes. Among the controller's features are delayed start time, upslope time, speed, and downslope time.

  7. Controllable circuit

    DEFF Research Database (Denmark)

    2010-01-01

    A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...

  8. Circuit Training.

    Science.gov (United States)

    Nelson, Jane B.

    1998-01-01

    Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)

  9. A programmable artificial retina

    International Nuclear Information System (INIS)

    Bernard, T.M.; Zavidovique, B.Y.; Devos, F.J.

    1993-01-01

    An artificial retina is a device that intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environments and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare Boolean processors with halftoning facilities might be used, providing versatility from programmability. By setting the pixel memory size to 3 b, the authors have demonstrated both the technological practicality and the computational efficiency of this programmable Boolean retina concept. Using semi-static shifting structures together with some interaction circuitry, a minimal retina Boolean processor can be built with less than 30 transistors and controlled by as few as 6 global clock signals. The successful design, integration, and test of such a 65x76 Boolean retina on a 50-mm 2 CMOS 2-μm circuit are presented

  10. Low cost design of microprocessor EDAC circuit

    International Nuclear Information System (INIS)

    Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

    2015-01-01

    An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

  11. Temperature Dependent Wire Delay Estimation in Floorplanning

    DEFF Research Database (Denmark)

    Winther, Andreas Thor; Liu, Wei; Nannarelli, Alberto

    2011-01-01

    Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this w......Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability....... In this work, we show that using wirelength as the evaluation metric does not always produce a floorplan with the shortest delay. We propose a temperature dependent wire delay estimation method for thermal aware floorplanning algorithms, which takes into account the thermal effect on wire delay. The experiment...

  12. Microcontroller based Integrated Circuit Tester

    OpenAIRE

    Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

    2015-01-01

    The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

  13. Delayed fission

    Energy Technology Data Exchange (ETDEWEB)

    Hatsukawa, Yuichi [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan). Tokai Research Establishment

    1997-07-01

    Delayed fission is a nuclear decay process that couples {beta} decay and fission. In the delayed fission process, a parent nucleus undergoes {beta} decay and thereby populates excited states in the daughter. If these states are of energies comparable to or greater than the fission barrier of the daughter, then fission may compete with other decay modes of the excited states in the daughter. In this paper, mechanism and some experiments of the delayed fission will be discussed. (author)

  14. Scan cell design for enhanced delay fault testability

    NARCIS (Netherlands)

    van Brakel, Gerrit; van Brakel, G.; Xing, Yizi; Xing, Y.; Kerkhoff, Hans G.

    1992-01-01

    Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan

  15. Modeling delay in genetic networks: from delay birth-death processes to delay stochastic differential equations.

    Science.gov (United States)

    Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Bennett, Matthew R; Josić, Krešimir; Ott, William

    2014-05-28

    Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

  16. Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

    Energy Technology Data Exchange (ETDEWEB)

    Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Bennett, Matthew R. [Department of Biochemistry and Cell Biology, Rice University, Houston, Texas 77204, USA and Institute of Biosciences and Bioengineering, Rice University, Houston, Texas 77005 (United States); Josić, Krešimir [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Department of Biology and Biochemistry, University of Houston, Houston, Texas 77204 (United States)

    2014-05-28

    Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

  17. Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

    International Nuclear Information System (INIS)

    Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William; Bennett, Matthew R.; Josić, Krešimir

    2014-01-01

    Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay

  18. UWB delay and multiply receiver

    Energy Technology Data Exchange (ETDEWEB)

    Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

    2013-09-10

    An ultra-wideband (UWB) delay and multiply receiver is formed of a receive antenna; a variable gain attenuator connected to the receive antenna; a signal splitter connected to the variable gain attenuator; a multiplier having one input connected to an undelayed signal from the signal splitter and another input connected to a delayed signal from the signal splitter, the delay between the splitter signals being equal to the spacing between pulses from a transmitter whose pulses are being received by the receive antenna; a peak detection circuit connected to the output of the multiplier and connected to the variable gain attenuator to control the variable gain attenuator to maintain a constant amplitude output from the multiplier; and a digital output circuit connected to the output of the multiplier.

  19. LOGIC CIRCUIT

    Science.gov (United States)

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  20. Short- circuit tests of circuit breakers

    OpenAIRE

    Chorovský, P.

    2015-01-01

    This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.

  1. Integrated circuit implementation of fuzzy controllers

    OpenAIRE

    Huertas Díaz, José Luis; Sánchez Solano, Santiago; Baturone Castillo, María Iluminada; Barriga Barros, Ángel

    1996-01-01

    This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno’s method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these...

  2. Dynamics of Nonlinear Time-Delay Systems

    CERN Document Server

    Lakshmanan, Muthusamy

    2010-01-01

    Synchronization of chaotic systems, a patently nonlinear phenomenon, has emerged as a highly active interdisciplinary research topic at the interface of physics, biology, applied mathematics and engineering sciences. In this connection, time-delay systems described by delay differential equations have developed as particularly suitable tools for modeling specific dynamical systems. Indeed, time-delay is ubiquitous in many physical systems, for example due to finite switching speeds of amplifiers in electronic circuits, finite lengths of vehicles in traffic flows, finite signal propagation times in biological networks and circuits, and quite generally whenever memory effects are relevant. This monograph presents the basics of chaotic time-delay systems and their synchronization with an emphasis on the effects of time-delay feedback which give rise to new collective dynamics. Special attention is devoted to scalar chaotic/hyperchaotic time-delay systems, and some higher order models, occurring in different bran...

  3. Collective of mechatronics circuit

    International Nuclear Information System (INIS)

    1987-02-01

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  4. Collective of mechatronics circuit

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1987-02-15

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  5. Topological Acoustic Delay Line

    Science.gov (United States)

    Zhang, Zhiwang; Tian, Ye; Cheng, Ying; Wei, Qi; Liu, Xiaojun; Christensen, Johan

    2018-03-01

    Topological protected wave engineering in artificially structured media is at the frontier of ongoing metamaterials research that is inspired by quantum mechanics. Acoustic analogues of electronic topological insulators have recently led to a wealth of new opportunities in manipulating sound propagation with strikingly unconventional acoustic edge modes immune to backscattering. Earlier fabrications of topological insulators are characterized by an unreconfigurable geometry and a very narrow frequency response, which severely hinders the exploration and design of useful devices. Here we establish topologically protected sound in reconfigurable phononic crystals that can be switched on and off simply by rotating its three-legged "atoms" without altering the lattice structure. In particular, we engineer robust phase delay defects that take advantage of the ultrabroadband reflection-free sound propagation. Such topological delay lines serve as a paradigm in compact acoustic devices, interconnects, and electroacoustic integrated circuits.

  6. Circuit parties.

    Science.gov (United States)

    Guzman, R

    2000-03-01

    Circuit parties are extended celebrations, lasting from a day to a week, primarily attended by gay and bisexual men in their thirties and forties. These large-scale dance parties move from city to city and draw thousands of participants. The risks for contracting HIV during these parties include recreational drug use and unsafe sex. Limited data exists on the level of risk at these parties, and participants are skeptical of outside help because of past criticism of these events. Health care and HIV advocates can promote risk-reduction strategies with the cooperation of party planners and can counsel individuals to personally reduce their own risk. To convey the message, HIV prevention workers should emphasize positive and community-centered aspects of the parties, such as taking care of friends and avoiding overdose.

  7. Inductive circuit arrangements

    International Nuclear Information System (INIS)

    Mansfield, Peter; Coxon, R.J.

    1987-01-01

    A switched coil arrangement is connected in a bridge configuration of four switches S 1 , S 2 , S 3 and S 4 which are each shunted by diodes D 1 , D 2 , D 3 and D 4 so that current can flow in either direction through a coil L depending on the setting of the switches. A capacitor C is connected across the bridge through a switch S 5 to receive the inductive energy stored in coil L on breaking the current flow path through the coil. The electrostatic energy stored in capacitor C can then be used to supply current through the coil in the reverse direction either immediately or after a time delay. Coil L may be a superconductive coil. Losses in the circuit can be made up by a trickle charge of capacitor C from a separate supply V 2 . The device may be used in nuclear magnetic resonance imaging. (author)

  8. Analysis of electronic circuits using digital computers

    International Nuclear Information System (INIS)

    Tapu, C.

    1968-01-01

    Various programmes have been proposed for studying electronic circuits with the help of computers. It is shown here how it possible to use the programme ECAP, developed by I.B.M., for studying the behaviour of an operational amplifier from different point of view: direct current, alternating current and transient state analysis, optimisation of the gain in open loop, study of the reliability. (author) [fr

  9. Commutation circuit for an HVDC circuit breaker

    Science.gov (United States)

    Premerlani, William J.

    1981-01-01

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

  10. Installations having pressurised fluid circuits

    International Nuclear Information System (INIS)

    Rigg, S.; Grant, J.

    1977-01-01

    Reference is made to nuclear installations having pressurised coolant flow circuits. Breaches in such circuits may quickly result in much damage to the plant. Devices such as non-return valves, orifice plates, and automatically operated shut-off valves have been provided to prevent or reduce fluid flow through a breached pipe line, but such devices have several disadvantages; they may present large restrictions to normal flow of coolant, and may depend on the operation of ancillary equipment, with consequent delay in bringing them into operation in an emergency. Other expedients that have been adopted to prevent or reduce reverse flow through an upstream breach comprise various forms of hydraulic counter flow brakes. The arrangement described has at least one variable fluid brake comprising a fluidic device connected into a duct in the pressurised circuit, the device having an inlet, an outlet, a vortex chamber between the inlet and outlet, a control jet for introducing fluid into the vortex chamber, connections communicating the inlet and the outlet into one part of the circuit and the control jet into another region at a complementary pressure so that, in the event of a breach in the circuit in one region, fluid passes from the other region to enter the vortex chamber to stimulate pressure to create a flow restricting vortex in the chamber that reduces flow through the breach. The system finds particular application to stream generating pressure tube reactors, such as the steam generating heavy water reactor at UKAEA, Winfrith. (U.K.)

  11. Delayed Ejaculation

    Science.gov (United States)

    ... cases, it is due to a combination of physical and psychological concerns. Psychological causes of delayed ejaculation include: Depression, anxiety or other mental health conditions Relationship problems due to stress, poor communication ...

  12. Delayed growth

    Science.gov (United States)

    ... Slow rate of growth; Retarded growth and development; Growth delay Images Toddler development References Cooke DW, Divall SA, Radovick S. Normal and aberrant growth in children. In: Melmed S, Polonsky KS, Larsen PR, ...

  13. Analog circuit design designing dynamic circuit response

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

  14. Trigger circuit

    International Nuclear Information System (INIS)

    Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.

    1984-01-01

    A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)

  15. The impact of software and CAE tools on SEU in field programmable gate arrays

    International Nuclear Information System (INIS)

    Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

    1999-01-01

    Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements

  16. Optical programmable Boolean logic unit.

    Science.gov (United States)

    Chattopadhyay, Tanay

    2011-11-10

    Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.

  17. Set of CAMAC modules on the base of large integrated circuits for an accelerator synchronization system

    International Nuclear Information System (INIS)

    Glejbman, Eh.M.; Pilyar, N.V.

    1986-01-01

    Parameters of functional moduli in the CAMAC standard developed for accelerator synchronization system are presented. They comprise BZN-8K and BZ-8K digital delay circuits, timing circuit and pulse selection circuit. In every module 3 large integral circuits of KR 580 VI53 type programmed timer, circuits of the given system bus bar interface with bus bars of crate, circuits of data recording control, 2 peripheric storage devices, circuits of initial regime setting, input and output shapers, circuits of installation and removal of blocking in channels are used

  18. Synchronization circuit for shaping electron beam picosecond pulses

    International Nuclear Information System (INIS)

    Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.

    1985-01-01

    A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes

  19. Control circuits for the 1.3 GeV electron synchrotron

    International Nuclear Information System (INIS)

    Asaoka, S.; Shiino, K.; Yoshioka, M.; Norimura, K.

    1980-01-01

    Following control circuits for the 1.3 GeV electron synchrotron, Institute for Nuclear Study, University of Tokyo, have been designed and constructed. 1. Variable delay circuits for the timing pulse of the synchrotron. 2. An alarm circuit for sputter ion pumps. 3. A sample and hold circuit for digital display and computer control of the beam intensity. This report describes detailes of the circuits and their specificatons. (author)

  20. Timing Analysis of Genetic Logic Circuits using D-VASim

    DEFF Research Database (Denmark)

    Baig, Hasan; Madsen, Jan

    and propagation delay analysis of single as well as cascaded geneticlogic circuits can be performed. D-VASim allows user to change the circuit parameters during runtime simulation to observe its effectson circuit’s timing behavior. The results obtained from D-VASim can be used not only to characterize the timing...... delay analysis may play a very significant role in the designing of genetic logic circuits. In thisdemonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagationdelay analysis of genetic logic circuits. Using D-VASim, the timing...... behavior of geneticlogic circuits but also to analyze the timing constraints of cascaded genetic logic circuits....

  1. Developmental delay

    Science.gov (United States)

    Nutrition support is essential for the care of the child with developmental delay. After a thorough evaluation, an individualized intervention plan that accounts for the child’s nutrition status, feeding ability, and medical condition may be determined. Nutrition assessments may be performed at leas...

  2. An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

    International Nuclear Information System (INIS)

    Duan Shukai; Liao Xiaofeng

    2007-01-01

    A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments

  3. Solid-state circuits

    CERN Document Server

    Pridham, G J

    2013-01-01

    Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

  4. Circuit analysis for dummies

    CERN Document Server

    Santiago, John

    2013-01-01

    Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

  5. Current limiter circuit system

    Science.gov (United States)

    Witcher, Joseph Brandon; Bredemann, Michael V.

    2017-09-05

    An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

  6. Superconducting flux flow digital circuits

    International Nuclear Information System (INIS)

    Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.

    1993-01-01

    The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic

  7. Electron commutator on integrated circuits

    International Nuclear Information System (INIS)

    Demidenko, V.V.

    1975-01-01

    The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru

  8. A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

    International Nuclear Information System (INIS)

    Tang Lu; Wang Zhigong; Xue Hong; He Xiaohu; Xu Yong; Sun Ling

    2010-01-01

    A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed. Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL. An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit. Through integrating the D-latch with 'OR' logic for dual-modulus operation, the delays associated with both the 'OR' and D-flip-flop (DFF) operations are reduced, and the complexity of the circuit is also decreased. The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model. The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system. The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz. The circuit exhibits a low RMS jitter of 3.3 ps. The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply. (semiconductor integrated circuits)

  9. Managing contamination delay to improve Timing Speculation architectures

    Directory of Open Access Journals (Sweden)

    Naga Durga Prasad Avirneni

    2016-08-01

    Full Text Available Timing Speculation (TS is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.

  10. Coplanar strips for Josephson voltage standard circuits

    International Nuclear Information System (INIS)

    Schubert, M.; May, T.; Wende, G.; Fritzsch, L.; Meyer, H.-G.

    2001-01-01

    We present a microwave circuit for Josephson voltage standards. Here, the Josephson junctions are integrated in a microwave transmission line designed as coplanar strips (CPS). The new layout offers the possibility of achieving a higher scale of integration and to considerably simplify the fabrication technology. The characteristic impedance of the CPS is about 50 Ω, and this should be of interest for programmable Josephson voltage standard circuits with SNS or SINIS junctions. To demonstrate the function of the microwave circuit design, conventional 10 V Josephson voltage standard circuits with 17000 Nb/AlO x /Nb junctions were prepared and tested. Stable Shapiro steps at the 10 V level were generated. Furthermore, arrays of 1400 SINIS junctions in this microwave layout exhibited first-order Shapiro steps. Copyright 2001 American Institute of Physics

  11. Miniaturization of Josephson logic circuits

    International Nuclear Information System (INIS)

    Ko, H.; Van Duzer, T.

    1985-01-01

    The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements

  12. Multiwire proportional counter (lecture by an electromagnetic delay line)

    International Nuclear Information System (INIS)

    Bruere-Dawson, R.

    1989-01-01

    For track localisation of ionizing particles with multiwire proportional chamber, an electronic chain including amplifying, shaping and memorizing circuits is required for each wire. In order to lower the cost of this type of detector, an electromagnetic delay line is proposed among various possibilities. In this paper, different coupling modes between chamber and delay line are studied with their respective advantages. The realization of one meter long delay line with a unit delay time of 15 ns per cm is also presented [fr

  13. Delay 25 an ASIC for timing adjustment in LHC

    NARCIS (Netherlands)

    Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.

    A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from

  14. Crispv programme

    International Nuclear Information System (INIS)

    Marinkovicj, N.

    CRISPV (Criticality and Spectrum code) is a multigroup neutron spectrum code for homogeneous reactor cores and is actually a somewhat modified version of the original CRISP programme. It is a combination of DATAPREP-II and BIGG-II programmes. It is assumed that the reactor cell is a cylindrical fuel rod in the light or heavy water moderator. DATEPREP-II CODE forms the multigroup data for homogeneous reactor and prepares the input parameters for the BIGG-II code. It has its own nuclear data library on a separate tape in binary mode. BIGG-II code is a multigroup neutron spectrum and criticality code for a homogenized medium. It has as well its own separate data library. In the CRISPV programme the overlay structure enables automatic handling of data calculated in the DATAPREP-II programme and needed in the BIGG-II core. Both programmes are written in FORTRAN for CDC 3600. Using the programme is very efficient and simple

  15. Circuit, especially for digital nuclear gyroscope systems

    International Nuclear Information System (INIS)

    Lowdenslager, J.R.

    1974-01-01

    The circuit with at least one or two spin generator shows a digital phase synchronizing loop in solid-state construction without movable mechanical parts. It is stable, may be turned in one direction any number of times without saturation, and also remains phase-synchronized when input signals are turned off. For this purpose, crystal oscillators with certain resonance frequencies are used. The spin generators are coupled at the outled side with filtering, squaring, and differential connections generating control impulses synchronous to the spin generators. Step divider circuits are connected to the oscillators, which act upon flip-flop registers. This is controlled by the filtering, squaring, and differential connections. Furthermore, field proportional control circuits with registers, advancing and delay circuits are provided, the registers being connected at the outlet side with digital adders and subtractors. The digital adder serves inertial-related purposes. (DG) [de

  16. Intuitive analog circuit design

    CERN Document Server

    Thompson, Marc

    2013-01-01

    Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

  17. The circuit designer's companion

    CERN Document Server

    Williams, Tim

    1991-01-01

    The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

  18. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1972-01-01

    Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

  19. A protocol for a cluster-randomized controlled trial of a self-help psycho-education programme to reduce diagnosis delay in women with breast cancer symptoms in Indonesia

    NARCIS (Netherlands)

    Setyowibowo, H. (Hari); M. Sijbrandij (Marit); A. Iskandarsyah (Aulia); J.A.M. Hunfeld (Joke); S.S. Sadarjoen (Sawitri); Badudu, D.F. (Dharmayanti F.); D.R. Suardi (Dradjat); J. Passchier (Jan)

    2017-01-01

    textabstractBackground: Breast cancer (BC) is the most frequent cancer occurring in women across the world. Its mortality rate in low-middle income countries (LMICs) is higher than in high-income countries (HICs), and in Indonesia BC is the leading cause of cancer deaths among women. Delay in breast

  20. A protocol for a cluster-randomized controlled trial of a self-help psycho-education programme to reduce diagnosis delay in women with breast cancer symptoms in Indonesia

    NARCIS (Netherlands)

    H. Setyowibowo (Hari); M. Sijbrandij (Marit); A. Iskandarsyah (Aulia); J.A.M. Hunfeld (Joke); S.S. Sadarjoen (Sawitri); D.F. Badudu (Dharmayanti F.); D.R. Suardi (Dradjat); J. Passchier (Jan)

    2017-01-01

    markdownabstractBackground: Breast cancer (BC) is the most frequent cancer occurring in women across the world. Its mortality rate in low-middle income countries (LMICs) is higher than in high-income countries (HICs), and in Indonesia BC is the leading cause of cancer deaths among women. Delay in

  1. Delayed Puberty

    DEFF Research Database (Denmark)

    Kolby, Nanna; Busch, Alexander Siegfried; Juul, Anders

    2017-01-01

    . The underlying reasons for the large variation in the age at pubertal onset are not fully established; however, nutritional status and socioeconomic and environmental factors are known to be influencing, and a significant amount of influencing genetic factors have also been identified. The challenges...... optimal in discriminating especially CDGP from HH. Management of the delayed puberty depends on the etiology. For boys with CDGP an observational period will often reveal imminent puberty. If puberty is not progressing spontaneously, sex steroid replacement is effective in stimulating the development...

  2. Electrical Circuits and Water Analogies

    Science.gov (United States)

    Smith, Frederick A.; Wilson, Jerry D.

    1974-01-01

    Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

  3. Global synchronization criteria with channel time-delay for chaotic time-delay system

    International Nuclear Information System (INIS)

    Sun Jitao

    2004-01-01

    Based on the Lyapunov stabilization theory, matrix measure, and linear matrix inequality (LMIs), this paper studies the chaos synchronization of time-delay system using the unidirectional linear error feedback coupling with time-delay. Some generic conditions of chaos synchronization with time-delay in the transmission channel is established. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criteria under which the global chaos synchronization of the time-delay coupled systems is achieved

  4. Electric circuits essentials

    CERN Document Server

    REA, Editors of

    2012-01-01

    REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

  5. Non-noise instabilities in oscilloscope trigger circuits

    International Nuclear Information System (INIS)

    Burd, Aleksander

    2011-01-01

    The paper discusses two phenomena called tremor, which result in incorrect operation of the oscilloscope trigger circuits. Both of them change delays introduced by the trigger circuit, resulting in horizontal shifts of traces on the screen, but the origins of the two phenomena are different. Both kinds of tremors in the oscilloscope trigger circuits produce images on the screen, which often are similar to those resulting from the noise jitter. Hence, limited knowledge of tremor may be a source of improper interpretation of the oscilloscope measurements. On the other hand tremor can be considered as a different approach to the problem of flip-flop circuit's metastability

  6. Piezoelectric drive circuit

    Science.gov (United States)

    Treu, C.A. Jr.

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

  7. Load testing circuit

    DEFF Research Database (Denmark)

    2009-01-01

    A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...

  8. Short-circuit logic

    NARCIS (Netherlands)

    Bergstra, J.A.; Ponse, A.

    2010-01-01

    Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of

  9. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2011-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  10. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2010-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  11. Refractory silicides for integrated circuits

    International Nuclear Information System (INIS)

    Murarka, S.P.

    1980-01-01

    Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

  12. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  13. Monitoring programme

    International Nuclear Information System (INIS)

    1994-06-01

    Her Majesty's Inspectorate of Pollution's 1992 report on its programme of monitoring radioactive substances is presented. Site operators' returns are verified and the report provides independent data on the environmental impact of authorized disposal of radioactive wastes. Radiation doses which may have been received by members of the public, fall well below the International Commission for Radiological Protection's (ICRP) recommended annual doses. (UK)

  14. Feedback in analog circuits

    CERN Document Server

    Ochoa, Agustin

    2016-01-01

    This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

  15. Development of a non-delay-line constant-fraction discriminator

    International Nuclear Information System (INIS)

    Yang Tao; Zhao Bo; Zhang Chi

    2002-01-01

    A Non-Delay-Line Constant-Fraction Discriminator (CFD) timing circuit is introduced. The delay line in the CFD is replaced with a low pass filter in this simplified circuit. The timing resolution of the CFD is better than 150 ps

  16. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

    Science.gov (United States)

    Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

    2016-01-01

    A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

  17. Multiplier less high-speed squaring circuit for binary numbers

    Science.gov (United States)

    Sethi, Kabiraj; Panda, Rutuparna

    2015-03-01

    The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

  18. Programmable Baseband Filter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Jensen, Rasmus Glarborg; Christensen, Kåre Tais; Bruun, Erik

    2003-01-01

    of the input transconductor. The entire filter consumes between 2.5 mW and 7.5 mW, depending on the desired noise performance. It is implemented in a standard 0.25 mum CMOS process. A test circuit has been developed and fabricated and measurements show that both the required programmability and the required...

  19. Programmable electronic safety systems

    International Nuclear Information System (INIS)

    Parry, R.R.

    1993-01-01

    Traditionally safety systems intended for protecting personnel from electrical and radiation hazards at particle accelerator laboratories have made extensive use of electromechanical relays. These systems have the advantage of high reliability and allow the designer to easily implement fail-safe circuits. Relay based systems are also typically simple to design, implement, and test. As systems, such as those presently under development at the Superconducting Super Collider Laboratory (SSCL), increase in size, and the number of monitored points escalates, relay based systems become cumbersome and inadequate. The move toward Programmable Electronic Safety Systems is becoming more widespread and accepted. In developing these systems there are numerous precautions the designer must be concerned with. Designing fail-safe electronic systems with predictable failure states is difficult at best. Redundancy and self-testing are prime examples of features that should be implemented to circumvent and/or detect failures. Programmable systems also require software which is yet another point of failure and a matter of great concern. Therefore the designer must be concerned with both hardware and software failures and build in the means to assure safe operation or shutdown during failures. This paper describes features that should be considered in developing safety systems and describes a system recently installed at the Accelerator Systems String Test (ASST) facility of the SSCL

  20. Programmable Electronic Safety Systems

    International Nuclear Information System (INIS)

    Parry, R.

    1993-05-01

    Traditionally safety systems intended for protecting personnel from electrical and radiation hazards at particle accelerator laboratories have made extensive use of electromechanical relays. These systems have the advantage of high reliability and allow the designer to easily implement failsafe circuits. Relay based systems are also typically simple to design, implement, and test. As systems, such as those presently under development at the Superconducting Super Collider Laboratory (SSCL), increase in size, and the number of monitored points escalates, relay based systems become cumbersome and inadequate. The move toward Programmable Electronic Safety Systems is becoming more widespread and accepted. In developing these systems there are numerous precautions the designer must be concerned with. Designing fail-safe electronic systems with predictable failure states is difficult at best. Redundancy and self-testing are prime examples of features that should be implemented to circumvent and/or detect failures. Programmable systems also require software which is yet another point of failure and a matter of great concern. Therefore the designer must be concerned with both hardware and software failures and build in the means to assure safe operation or shutdown during failures. This paper describes features that should be considered in developing safety systems and describes a system recently installed at the Accelerator Systems String Test (ASST) facility of the SSCL

  1. A survival programme

    International Nuclear Information System (INIS)

    Vester, F.

    1978-01-01

    The book is a non-speculative information source on ecological problems and their possible solutions. It is a 'programme' from a twofold point of view: it determines political and scientific-technological objectives and it transfers knowledge by mental steps with techniques of programmed instruction. Thus emphasis is laid on detailed problems, especially by conscionsly challenged redundancies, and, on the other hand, a greater context is presented. Selected facts are examined under their different aspects, interactions and control circuits are described. Each chapter will speak for itself after the introduction has been read but is related to other chapters by cross references, illustrative material, a glossary and a comprehensive list of references. The 'Survival Programme' is a realistic and challenging discussion with the problem of 'Ecology in the Industrial Age'. It adresses scientists from various disciplines but also offers itself as a compendium to laymen in search of information, members of citizens initiatives and responsible representants of the political and industrial world. (orig./HP) [de

  2. Technology Programme

    Energy Technology Data Exchange (ETDEWEB)

    Batistoni, Paola; De Marco, Francesco; Pieroni, Leonardo [ed.

    2005-07-01

    The technology activities carried out by the Euratom-ENEA Association in the framework of the European Fusion Development Agreement concern the Next Step (International Thermonuclear Experimental Reactor - ITER), the Long-Term Programme (breeder blanket, materials, International Fusion Materials Irradiation Facility - IFMIF), Power Plant Conceptual Studies and Socio-Economic Studies. The Underlying Technology Programme was set up to complement the fusion activities as well to develop technologies with a wider range of interest. The Technology Programme mainly involves staff from the Frascati laboratories of the Fusion Technical and Scientific Unit and from the Brasimone laboratories of the Advanced Physics Technologies Unit. Other ENEA units also provide valuable contributions to the programme. ENEA is heavily engaged in component development/testing and in design and safety activities for the European Fusion Technology Programme. Although the work documented in the following covers a large range of topics that differ considerably because they concern the development of extremely complex systems, the high level of integration and coordination ensures the capability to cover the fusion system as a whole. In 2004 the most significant testing activities concerned the ITER primary beryllium-coated first wall. In the field of high-heat-flux components, an important achievement was the qualification of the process for depositing a copper liner on carbon fibre composite (CFC) hollow tiles. This new process, pre-brazed casting (PBC), allows the hot radial pressing (HRP) joining procedure to be used also for CFC-based armour monoblock divertor components. The PBC and HRP processes are candidates for the construction of the ITER divertor. In the materials field an important milestone was the commissioning of a new facility for chemical vapour infiltration/deposition, used for optimising silicon carbide composite (SiCf/SiC) components. Eight patents were deposited during 2004

  3. Technology Programme

    International Nuclear Information System (INIS)

    Batistoni, Paola; De Marco, Francesco; Pieroni, Leonardo

    2005-01-01

    The technology activities carried out by the Euratom-ENEA Association in the framework of the European Fusion Development Agreement concern the Next Step (International Thermonuclear Experimental Reactor - ITER), the Long-Term Programme (breeder blanket, materials, International Fusion Materials Irradiation Facility - IFMIF), Power Plant Conceptual Studies and Socio-Economic Studies. The Underlying Technology Programme was set up to complement the fusion activities as well to develop technologies with a wider range of interest. The Technology Programme mainly involves staff from the Frascati laboratories of the Fusion Technical and Scientific Unit and from the Brasimone laboratories of the Advanced Physics Technologies Unit. Other ENEA units also provide valuable contributions to the programme. ENEA is heavily engaged in component development/testing and in design and safety activities for the European Fusion Technology Programme. Although the work documented in the following covers a large range of topics that differ considerably because they concern the development of extremely complex systems, the high level of integration and coordination ensures the capability to cover the fusion system as a whole. In 2004 the most significant testing activities concerned the ITER primary beryllium-coated first wall. In the field of high-heat-flux components, an important achievement was the qualification of the process for depositing a copper liner on carbon fibre composite (CFC) hollow tiles. This new process, pre-brazed casting (PBC), allows the hot radial pressing (HRP) joining procedure to be used also for CFC-based armour monoblock divertor components. The PBC and HRP processes are candidates for the construction of the ITER divertor. In the materials field an important milestone was the commissioning of a new facility for chemical vapour infiltration/deposition, used for optimising silicon carbide composite (SiCf/SiC) components. Eight patents were deposited during 2004

  4. Electric circuits and signals

    CERN Document Server

    Sabah, Nassir H

    2007-01-01

    Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...

  5. [Shunt and short circuit].

    Science.gov (United States)

    Rangel-Abundis, Alberto

    2006-01-01

    Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

  6. All optical programmable logic array (PLA)

    Science.gov (United States)

    Hiluf, Dawit

    2018-03-01

    A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

  7. Analog circuits cookbook

    CERN Document Server

    Hickman, Ian

    2013-01-01

    Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.

  8. Analog circuit design

    CERN Document Server

    Dobkin, Bob

    2012-01-01

    Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

  9. Regenerative feedback resonant circuit

    Science.gov (United States)

    Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

    2014-09-02

    A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

  10. Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

    Directory of Open Access Journals (Sweden)

    Ruiping Cao

    2014-01-01

    Full Text Available In high-speed applications, MOS current mode logic (MCML is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP. However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

  11. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  12. Timergenerator circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

  13. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1968-01-01

    Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

  14. Maximum Acceleration Recording Circuit

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1995-01-01

    Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

  15. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  16. Circuits and filters handbook

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

  17. Security electronics circuits manual

    CERN Document Server

    MARSTON, R M

    1998-01-01

    Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

  18. Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

    Science.gov (United States)

    Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

    2018-06-01

    A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

  19. Gravitational Lens Time Delays Using Polarization Monitoring

    Directory of Open Access Journals (Sweden)

    Andrew Biggs

    2017-11-01

    Full Text Available Gravitational lens time delays provide a means of measuring the expansion of the Universe at high redshift (and therefore in the ‘Hubble flow’ that is independent of local calibrations. It was hoped that many of the radio lenses found in the JVAS/CLASS survey would yield time delays as these were selected to have flat spectra and are dominated by multiple compact components. However, despite extensive monitoring with the Very Large Array (VLA, time delays have only been measured for three of these systems (out of 22. We have begun a programme to reanalyse the existing VLA monitoring data with the goal of producing light curves in polarized flux and polarization position angle, either to improve delay measurements or to find delays for new sources. Here, we present preliminary results on the lens system B1600+434 which demonstrate the presence of correlated and substantial polarization variability in each image.

  20. Scaling of graphene integrated circuits.

    Science.gov (United States)

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

    2015-05-07

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

  1. Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

    Directory of Open Access Journals (Sweden)

    Michael S. Hsiao

    2002-01-01

    Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

  2. Analysis of electronic circuits using digital computers; L'analyse des circuits electroniques par les calculateurs numeriques

    Energy Technology Data Exchange (ETDEWEB)

    Tapu, C [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1968-07-01

    Various programmes have been proposed for studying electronic circuits with the help of computers. It is shown here how it possible to use the programme ECAP, developed by I.B.M., for studying the behaviour of an operational amplifier from different point of view: direct current, alternating current and transient state analysis, optimisation of the gain in open loop, study of the reliability. (author) [French] Differents programmes ont ete proposes pour l'etude des circuits electroniques a l'aide des calculateurs. On montre comment on peut utiliser le programme ECAP, mis au point par I. B. M., pour etudier le comportement d'un amplificateur operationnel, a differents points de vue: analyse en courant continu, courant alternatif et regime transitoire, optimalisation du gain en boucle ouverte, etude de la fiabilite. (auteur)

  3. Circuits on Cylinders

    DEFF Research Database (Denmark)

    Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V

    2006-01-01

    We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching pro...

  4. Delayed puberty in girls

    Science.gov (United States)

    ... sexual development - girls; Pubertal delay - girls; Constitutional delayed puberty ... In most cases of delayed puberty, growth changes just begin later than usual, sometimes called a late bloomer. Once puberty begins, it progresses normally. This pattern runs ...

  5. Delayed Puberty (For Teens)

    Science.gov (United States)

    ... Safe Videos for Educators Search English Español Delayed Puberty KidsHealth / For Teens / Delayed Puberty What's in this ... wonder if there's anything wrong. What Is Delayed Puberty? Puberty is the time when your body grows ...

  6. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  7. A cluster-randomized controlled trial evaluating the effects of delaying onset of adolescent substance abuse on cognitive development and addiction following a selective, personality-targeted intervention programme: the Co-Venture trial.

    Science.gov (United States)

    O'Leary-Barrett, Maeve; Mâsse, Benoit; Pihl, Robert O; Stewart, Sherry H; Séguin, Jean R; Conrod, Patricia J

    2017-10-01

    Substance use and binge drinking during early adolescence are associated with neurocognitive abnormalities, mental health problems and an increased risk for future addiction. The trial aims to evaluate the protective effects of an evidence-based substance use prevention programme on the onset of alcohol and drug use in adolescence, as well as on cognitive, mental health and addiction outcomes over 5 years. Thirty-eight high schools will be recruited, with a final sample of 31 schools assigned to intervention or control conditions (3826 youth). Brief personality-targeted interventions will be delivered to high-risk youth attending intervention schools during the first year of the trial. Control school participants will receive no intervention above what is offered to them in the regular curriculum by their respective schools. Public/private French and English high schools in Montreal (Canada). All grade 7 students (12-13 years old) will be invited to participate. High-risk youth will be identified as those scoring one standard deviation or more above the school mean on one of the four personality subscales of the Substance Use Risk Profile Scale (40-45% youth). Self-reported substance use and mental health symptoms and cognitive functioning measured annually throughout 5 years. Primary outcomes are the onset of substance use disorders at 4 years post-intervention (year 5). Secondary intermediate outcomes are the onset of alcohol and substance use 2 years post-intervention and neuropsychological functions; namely, the protective effects of substance use prevention on cognitive functions generally, and executive functions and reward sensitivity specifically. This longitudinal, cluster-randomized controlled trial will investigate the impact of a brief personality-targeted intervention program on reducing the onset of addiction 4 years-post intervention. Results will tease apart the developmental sequences of uptake and growth in substance use and cognitive

  8. Break-before-make CMOS inverter for power-efficient delay implementation.

    Science.gov (United States)

    Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

    2014-01-01

    A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

  9. ISOLDE PROGRAMME

    CERN Multimedia

    Fedosseev, V; Herfurth, F; Scheidenberger, C; Geppert, C; Gorges, C; Ratajczyk, T; Wiederhold, J C; Vogel, S; Munch, M K; Nieminen, P; Pakarinen, J J A; Lecesne, N; Bouzomita, H; Grinyer, J; Marques moreno, F M; Parlog, M; Blank, B A; Pedroza, J; Ghetta, V; Lozeva, R; Zacarias, S M; Guillemaud mueller, D S; Cottereau, E; Cheikh mhamed, M; Tusseau nenez, S; Tungate, G; Walker, P M; Smith, A G; Fitzpatrick, C; Dominik, W M; Karny, M; Ciemny, A A; Nyman, G H; Thies, R M A; Lindberg, S K G; Langouche, G F; Velten, P; Araujo escalona, V I; Boudreau, M; Domnanich, K A; Richter, D; Lutter, R J; Javaji, A; Engel, R Y; Wiehr, S; Nacher gonzalez, E; Jungclaus, A; Ribeiro jimenez, G; Marroquin alonso, I; Cal gonzalez, J; Paziy, V; Salsac, M; Murphy, C; Podolyak, Z F; Bajoga, A D; Butler, P; Pritchard, A; Colosimo, S J; Steer, A N; Fox, S P; Wadsworth, B A; Truesdale, V L; Al monthery, M; Bracco, A; Guttormsen, M S; Badea, M N; Calinescu, S; Ujeniuc, S; Cederkall, J A; Zemlyanoy, S; Donets, E D; Golovkov, M; Schweitzer, D K; Vranicar, A; Harrichunder, S; Ncube, M; Nannini, A; Strisovska, J; Wolf, E; Gerten, R F; Lehnert, J; Rainovski, G I; Pospisil, S; Datta pramanik, U; Benzoni, G; Fedorov, D; Maier, F M; Bonanni, A; Pfeiffer, B; Griesel, T; Wehner, L W; Mikkelsen, M; Recchia, F; Lenzi, S M; Smith, J F; Kelly, C M; Acosta sanchez, L A; Chavez lomeli, E R; De melo bandeira tavares, P M; Vieira, J M; Martins da silva, M A; Lima lopes, A M; Lopes leal, T J; Mader, J; Kessler, P; Laurent, B G; Schweikhard, L C; Marx, G H; Kulczycka, E; Komorowska, M; Da silva, M F; Goncalves marques, C P; Baptista peres, M A; Welander, J E; Reiter, P; Miller, C; Martin sanchez-cano, D; Wiens, A; Blazhev, A A; Braun, N; Cappellazzo, M V; Birkenbach, B; Gerst, R; Dannhoff, M F; Sithole, M J; Bilgier, B; Nardelli, S; Araujo mendes, C M; Agramunt ros, J; Valencia marin, E; Pantea, E; Hessberger, F P; Leduc, A J; Mitsuoka, S; Carbonari, A W; Buchegger, F J; Garzon camacho, A; Dapo, H; Papka, P; Stachura, M K; Stora, T; Marsh, B A; Thiboud, J A; Heylen, H; Antalic, S; Stahl, C; Bauer, C; Thurauf, M; Maass, B; Sturm, S; Boehm, C; Wolf, N R; Ways, M; Steinsberger, T P; Riisager, K; Ruotsalainen, P A; Bastin, B; Duval, F T; Penessot, G; Flechard, X D; Desrues, P; Giovinazzo, J; Kurtukian nieto, T; Ascher, P E L; Roccia, S; Matea, I; Croizet, H A G; Bonnin, C M; Morfouace, P; Smith, A J; Guin, R; Banerjee, D; Gunnlaugsson, H P; Ohtsubo, T; Zhukov, M V; Tengborn, E A; Welker, A; Giannopoulos, E; Dessagne, P; Juscamaita vivanco, Y; Da costa pereira, L M; Hustings, J; Yu, H; Kruecken, R; Nowak, A K; Jankowski, M; Cano ott, D; Galve lahoz, P; Murphy, A S J; Shand, C M; Jones, G D; Herzberg, R; Ikin, P; Revill, J P; Everett, C; Napoli, D R; Scarel, G; Larsen, A; Tornyi, T G; Pascu, S G; Stroe, L; Toma, S; Jansson, K; Dronjak fahlander, M; Krupko, S; Hurst, A M; Veskovic, M; Nikolov, J; Masenda, H; Sibanda, W N; Rocchini, M; Klimo, J; Deicher, M; Wichert, T; Kronenberg, J; Helmke, A; Meliani, Z; Ivanov, V S; Green, B L; Keatings, J M; Kuti, I; Halasz, Z; Henry, M O; Bras de sequeira amaral, V; Espirito santo, F; Da silva, D J; Rosendahl, S; Vianden, R J; Speidel, K; Agarwal, I; Faul, T; Kownacki, J M; Martins correia, J G; Lorenz, K; Costa miranda, S M; Granadeiro costa, A R; Zyabkin, D; Kotthaus, T; Pfeiffer, M; Gironi, L; Jensen, A; Romstedt, F; Constantino silva furtado, I; Heredia cardona, J A; Jordan martin, M D; Montaner piza, A; Zacate, M O; Plewinski, F; Mesli, A; Akakpo, E H; Pichard, A; Hergemoller, F; Neu, W; Fallis starhunter, J P; Voulot, D; Mrazek, J; Ugryumov, V; Savreux, R P; Kojouharov, I M; Kern, R O; Papst, O; Fitting, J; Lauer, M; Kirsebom, O S; Jensen, K L; Jokinen, A; Rahkila, P J; Hager, U D K; Konki, J P; Dubois, M; Orr, N A; Fabian, X; Huikari, J E; Goigoux, T; Magron, C; Zakari, A A; Maietta, M; Bachelet, C E M; Roussiere, B; Li, R; Canavan, R L; Lorfing, C; Foster, R M; Gislason, H P; Shayestehaminzadeh, S; Qi, B; Mukai, M; Watanabe, Y; Willmann, L; Kurcewicz, W; Wimmer, K; Meisel, Z P; Dorvaux, O; Nowacki, F; Koudriavtsev, I; Lievens, P; Delaure, B J P; Neyens, G; Ceruti, S; Bunka, M; Vermeulen, C; Umbricht, C A; De boer, J; Podadera aliseda, I; Alcorta moreno, M; Pesudo fortes, V; Zielinska, M; Korten, W; Wang, C H; Lotay, G J; Mason, P; Rice, S J; Regan, P H; Willenegger, L M; Andreev, A; Yavuzkanat, N; Hass, M; Kumar, V; Valiente dobon, J J; Crespo campo, L; Zamfir, N - V; Deleanu, D; Clisu, C; Jeppesen, H B; Wu, C; Pain, S D; Stracener, D W; Wuosmaa, A H; Szilner, S; Colovic, P; Matousek, V; Venhart, M; Birova, M; Li, X; Stuchbery, A E; Lellep, G M; Chakraborty, S; Leoni, S; Chupp, T; Yilmaz, C; Severin, G; Garcia ramos, J E; Newton, M E; Hadinia, B; Mc glynn, E; Monteiro de sena silvares de carvalho, I; Friedag, P; Figuera, P; Koos, V; Meot, V H; Pauwels, D B; Jancso, A; Srebrny, J; Alves, E J; David bosne, E; Bengtsson, L; Kalkuehler, M; Albers, M; Bharuth-ram, K; Akkus, B; Hemmingsen, L B S; Pedersen, J T; Dos santos redondo, L M; Rubio barroso, B; Algora, A; Kozlov, V; Mavela, D L; Mokhles gerami, A; Keeley, N; Bernardo da silva, E; Unzueta solozabal, I; Schell, J; Szybowicz, M; Yang, X; Plavec, J; Lassen, J; Johnston, K; Coquard, L; Bloch, T P; Bonig, E S; Stegmann, R; Ignatov, A; Paschalis, S; Fernandez martinez, G; Schilling, M; Habermann, T; Von hahn, R; Minaya ramirez, E E; Moore, I D; Wang, Y; Saastamoinen, A J; Grahn, T; Herzan, A; Stolze, S M; Clement, E; Dijon, A; Shornikov, A; Lienard, E; Gibelin, J D; Pain, C; Canchel, G; Simpson, G S; Latrasse, L P; Huang, W; Forest, D H; Billowes, J; Flanagan, K; Strashnov, I; Binnersley, C L; Sanchez poncela, M; Simpson, J; Morrall, P S; Grant, A F; Charisopoulos, S; Lagogiannis, A; Bhattacharya, C; Olafsson, S; Stepaniuk, M; Tornqvist, H T; Heinz, A M; White iv, E R; Courtin, S; Marechal, F; Da silva fenta, A E; De lemos lima, T A; Stryjczyk, M; Dockx, K; Haller, S; Rizzi, M; Reichert, S B; Bonn, J; Thirolf, P G; Garcia rios, A R; Gugliermina, V M; Cubero campos, M A; Sanchez tembleque, V; Benito garcia, J; Senoville, M; Mountford, D J; Gelletly, W; Alharbi, T S T; Wilson, E; Rigby, S V; Andreoiu, C; Paul, E S; Harkness, L J; Judson, D S; Wraith, C; Van esbroeck, K; Wadsworth, R; Cubiss, J G; Harding, R D; Vaintraub, S; Mandal, S K; Scarpa, D; Hoff, P; Syed naeemul, H; Borcea, R; Balabanski, D L; Marginean, R; Rotaru, F; Rudolph, D; Fahlander, C H; Chudoba, V; Kay, B P; Soic, N; Naidoo, D; Veselsky, M; Kliman, J; Raisanen, J A; Dietrich, M; Maung maung than, M M T; Reed, M W; Danchev, M T; Ray, J; Roy, M; Hammen, M; Capponi, L; Veghne csatlos, M M; Fryar, J; Mirzadeh vaghefi, S P; Trindade pereira, A M; De pinho oliveira, G N; Bakenecker, A; Tramm, C; Germic, V; Morel, P A; Kowalczyk, M; Matejska-minda, M; Wolinska-cichocka, M; Ringvall moberg, A; Mantovan, R; Fransen, C H; Radeck, F; Schneiders, D W; Steinbach, T; Vibenholt, J E; Magnussen, M J; Stevnhoved, H M; Comas lijachev, V; Dasenbrock-gammon, N M; Perkowski, J; O'neill, G G; Matveev, Y; Wegner, M; Liu, Z; Perez alvarez, T; Cerato, L; Radchenko, V; Molholt, T E; Tabares giraldo, J A; Srnka, D; Dlouhy, Z; Beck, D; Werner, V R; Homm, I; Eliseev, S; Blaum, K; Probst, M B; Kaiser, C J; Martin, J A; Refsgaard, J; Peura, P J; Greenlees, P T; Auranen, K; Delahaye, P; Traykov, E K; Perez loureiro, D; Mery, A A; Couratin, C; Tsekhanovich, I; Lunney, D; Gaulard, C V; Mottram, A D; Cullen, D M; Das, S K; Van de walle, J; Mazzocchi, C; Jonson, B N G; Woehr, A; Lesher, S R; Zuber, K T; Filippin, L; De witte, H J; Van den bergh, P A M; Raabe, R; Dirkx, D; Parnefjord gustafsson, F O A; Dunlop, R A; Tarasava, K; Gernhaeuser, R A; Weinzierl, W; Berger, C; Wendt, K; Achtzehn, T; Gottwald, T; Schug, M; Rossel, R E; Dominguez reyes, R R; Fraile prieto, L M; Briz monago, J A; Koester, U H; Bunce, M R; Bowry, M D; Nakhostin, M; Shearman, R; Cresswell, J R; Joss, D T; Gredley, A; Groombridge, D; Laird, A M; Aslanoglou, X; Siem, S; Weterings, J A; Renstrom, T; Szpak, B T; Luczkowski, M J; Ghita, D; Bezbakh, A; Soltz, R A; Bollmann, J; Bhattacharya, P; Roy, S; Rahaman, M A; Wlodarski, T; Carvalho soares, J; Barzakh, A; Schertz, F; Froemmgen, N E; Liberati, V; Foy, B E; Baptista barbosa, M; Weinheimer, C P; Zboril, M; Simon, R E; Popescu, L A; Czosnyka, T; Miranda jana, P A; Leimbach, D; Naskrecki, R; Plociennik, W A; Ruchowska, E E; Chiara, C J; Walters, W; Eberth, J H; Thomas, T; Thole, P; Queiser, M T; Lo bianco, G; D'amico, F; Muller, S; Sanchez alarcon, R M; Tain enriquez, J L; Orrigo, S E A; Orlandi, R; Masango, S; Plazaola muguruza, F C; Lepareur, N G; Fiebig, J M; Ceylan, N; Wildner, E; Kowalska, M; Malbrunot, S; Garcia ruiz, R F; Pallada, S; Slezak, M; Roeckl, E; Schrieder, G H; Ilieva, S K; Koenig, K L; Amoretti, M A; Lommen, J M; Fynbo, H O U; Weyer, G O P; Koldste, G T; Madsboll, K; Jensen, J H; Nieminen, A M; Reponen, M; Villari, A; Thomas, J; Saint-laurent, M; Sorlin, O H; Carniol, B; Pereira lopez, J; Grevy, S; Plaisir, C; Marie-jeanne, M J; Georgiev, G P; Etile, A M; Le blanc, F M; Verney, D; Stefan, G I; Assie, M; Suzuki, D; Guillot, J; Vazquez rodriguez, L; Campbell, P; Deacon, A N; Ware, T; Flueras, A; Xie, L; Banerjee, K; Piersa, M; Galaviz redondo, D; Johansson, H T; Schwarz, S; Toysa, A S; Aumont, J; Van duppen, P L E; Atanasov, D; Zadvornaya, A; Renaud, M A; Xu, Z; Garrett, P E; Rapisarda, E; Reber, J A; Mattolat, C F; Raeder, S; Habs, D; Vidal, M; Perez liva, M; Calvo portela, P; Ulla pedrera, F J; Wood, R T; Lalkovski, S; Page, R; Petri, M; Barton, C J; Nichols, A J; Vermeulen, M J; Bloor, D M; Henderson, J; Wilson, G L; De angelis, G; Buerger, A; Modamio hoybjor, V; Klintefjord, M L; Ingeberg, V W; Fornal, B A; Marginean, R; Sava, T; Kusoglu, A; Suvaila, R; Lica, R; Costache, C; Mihai, R; Ionescu, A; Baeck, T M; Hoffman, C R; Sedlak, M; Koskelo, O K; Kyaw myat, K M; Gladnishki, K A; Ganguly, B; Goncalves marques, J; Cardoso, S; Seliverstov, M; Niessen, B D; Gutt, L E; Chapman, R; Spagnoletti, P N; Lopes, C; De oliveira amorim, C; Batista lopes, C M; Araujo, J; Schielke, S J; Daugas, J R; Gaudefroy, L; Chevrier, R; Szunyogh, D M; Napiorkowski, P J; Wrzosek-lipska, K; Wahl, U; Catarino, N; Pereira carvalho alves de sequeira, M; Hess, H E; Holler, A; Bettermann, L; Geibel, K; Taprogge, J; Lewandowski, L T N; Manchado de sola, F; Cakirli mutlu, R B; Das gupta, S; Thulstrup, P W; Heinz, U; Nogwanya, T; Neidherr, D M; Morales lopez, A I; Gumenyuk, O; Peaker, A R; Wakabayashi, Y; Abrahams, K J; Martin montes, E J; Mach, H A; Souza ribeiro junior, I; He, J; Chalil, A; Xing, R; Dos santos augusto, R M; Giles, T J; Dorsival, A; Trujillo hernandez, J S; Kalaninova, Z; Andel, B; Venos, D; Kraemer, J; Saha, S; Neugart, R; Eronen, T O; Kreim, K D; Heck, M K; Goncharov, M; Karthein, J; Julin, R J; Eleon, C; Achouri, N L; Grinyer, G F; Fontbonne, C M; Alfaurt, P; Lynch, K M; Wilkins, S G; Brown, A R; Imai, N; Pomorski, M J; Janiak, L; Nilsson, T; Stroke, H H; Stanja, J; Dangelser, E; Heenen, P; Godefroid, M; Mallion, S N; Gins, W A M; Stegemann, S T; Koszorus, A; Mcnulty, J F; Lin, P; Ohlert, C M; Schwerdtfeger, W; Tengblad, O; Becerril reyes, A D; Perea martinez, A; Martinez perez, M C; Margerin, V; Rudigier, M; Alexander, T D; Patel, Z V; Hammond, N; Wearing, F; Patel, A; Jenkins, D G; Corradi, L; Galtarossa, F; Debernardi, A; Giacoppo, F; Tveten, G M; Malatji, K L; Krolas, W A; Stanoiu, M A; Rickert, E U; Ter-akopian, G; Cline, D; Riihimaeki, I A; Simon, K D; Wagner, F E; Turker, M; Neef, M H; Coombes, B J; Jakubek, J; Vagena, E; Bottoni, S; Nishimura, K; Correia, J; Rodrigues valdrez, C J; Molkanov, P; Adhikari, R; Ostrowski, A N; Hallmann, O; Scheck, M; Wady, P T; Lane, J; Krasznahorkay, A J; Kunne sohler, D; Meaney, A J; Hochschulz, F; Roig, O; Behan, C C; Kargoll, S; Kemnitz, S; Carvalho teixeira, R C; Redondo cubero, A; Tallarida, G; Kaczarowski, R; Finke, F; Linnemann, A; Altenkirch, R; Saed-samii, N; Ansari, S H; Dlamini, W B; Adoons, V N; Ronning, C R; Wiedeking, M; Herlert, A J; Mehl, C V; Judge, S M; Gaertner, D; Divinskyi, S; Karabasov, M O; Zagoraios, G; Boztosun, I; Van zyl, J J; Catherall, R; Lettry, J; Wenander, F J C; Zakoucky, D; Catchen, G L; Noertershaeuser, W; Kroell, T; Leske, J; Shubina, D; Murray, I M; Pancin, J; Delaunay, F; Poincheval, J J L; Audirac, L L; Gerbaux, M T; Aouadi, M; Sole, P G P; Fallot, M P; Onillon, A; Duchemin, C; Formento cavaier, R; Audi, G; Boukhari, A; Lau, C; Martin, J A; Barre, N H; Berry, T A; Procter, T J; Bladen, L K; Axiotis, M; Muto, S; Jeong, S C; Hirayama, Y; Korgul, A B; Minamisono, K; Bingham, C R; Aprahamian, A; Bucher, B M; Severijns, N; Huyse, M L; Ferrer garcia, R; Verlinde, M N S; Romano, N; Maugeri, E A; Klupp, S C; Dehn, M H; Heinke, R M; Naubereit, P; Maira vidal, A; Vedia fernandez, M V; Ibanez garcia, P B; Bruyneel, B J E; Materna, T; Hadynska-klek, K; Al-dahan, N; Alazemi, N; Carroll, R J; Babcock, C; Patronis, N; Eleme, Z; Dhal, A; Sahin, E; Goergen, A; Maj, A; Bednarczyk, P A; Borcea, C; Negoita, F; Suliman, G; Marginean, N M; Sotty, C O; Negret, A L; Nae, S A; Nita, C; Golubev, P I; Knyazev, A; Jost, C U; Petrik, K; Vaeyrynen, S A; Dracoulis, G D; Uher, J; Fernandez dominguez, B; Chakraborty, P; Avigo, R; Falahat, S; Lekovic, F; Dorrer, H J; Mengoni, D; Derkx, X; Angus, L J; Sandhu, K S; Gregor, E; Kelly, N A; Byrne, D J; Haas, H; Lourenco, A A; Sousa pereira, S M; Sousa, J B; De melo mendonca, T M; Tavares de sousa, C; Guerreiro dos santos oliveira custodio, L M; Da rocha rodrigues, P M; Yamaguchi, T; Thompson, P C; Rosenbusch, M; Wienholtz, F; Fischer, P; Iwanicki, J S; Rusek, K M; Hanstorp, D; Vetter, U; Wolak, J M; Park, S H; Warr, N V; Doornenbal, P C; Imig, A; Seidlitz, M; Moschner, K; Vogt, A; Kaya, L; Martel bravo, I; Orduz, A K; Serot, O; Majola, S N; Litvinov, Y; Bommert, M; Hensel, S; Markevich, V; Nishio, K; Ota, S; Matos, I; Zenkevich, A; Picado sandi, E; Forstner, O; Hu, B; Ntshangase, S S; Sanchez-segovia, J

    2002-01-01

    The experiments aim at a broad exploration of the properties of atomic nuclei far away from the region of beta stability. Furthermore, the unique radioactive beams of over 60~elements produced at the on-line isotope separators ISOLDE-2 and ISOLDE-3 are used in a wide programme of atomic, solid state and surface physics. Around 300 scientists are involved in the project, coming from about 70 laboratories. \\\\ \\\\ The electromagnetic isotope separators are connected on-line with their production targets in the extracted 600 MeV proton or 910~MeV Helium-3 beam of the Synchro-Cyclotron. Secondary beams of radioactive isotopes are available at the facility in intensities of 10$^1

  10. A Quantized Analog Delay for an ir-UWB Quadrature Downconversion Autocorrelation Receiver

    NARCIS (Netherlands)

    Bagga, S.; Zhang, L.; Serdijn, W.A.; Long, J.R.; Busking, E.B.

    2005-01-01

    A quantized analog delay is designed as a requirement for the autocorrelation function in the quadrature downconversion autocorrelation receiver (QDAR). The quantized analog delay is comprised of a quantizer, multiple binary delay lines and an adder circuit. Being the foremost element, the quantizer

  11. Approximate circuits for increased reliability

    Science.gov (United States)

    Hamlet, Jason R.; Mayo, Jackson R.

    2015-08-18

    Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

  12. Troubleshooting analog circuits

    CERN Document Server

    Pease, Robert A

    1991-01-01

    Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other

  13. Modern TTL circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

  14. Circuit analysis with Multisim

    CERN Document Server

    Baez-Lopez, David

    2011-01-01

    This book is concerned with circuit simulation using National Instruments Multisim. It focuses on the use and comprehension of the working techniques for electrical and electronic circuit simulation. The first chapters are devoted to basic circuit analysis.It starts by describing in detail how to perform a DC analysis using only resistors and independent and controlled sources. Then, it introduces capacitors and inductors to make a transient analysis. In the case of transient analysis, it is possible to have an initial condition either in the capacitor voltage or in the inductor current, or bo

  15. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.

  16. 'Speedy' superconducting circuits

    International Nuclear Information System (INIS)

    Holst, T.

    1994-01-01

    The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

  17. 4-channel time delayed pulse generator

    International Nuclear Information System (INIS)

    Wetzel, L.F.S.; Rossi, J.O.; Del Bosco, E.

    1987-02-01

    It is described the project of a 4-channel delayed pulse generator employed to trigger the plasma centrifuge experiment of the Laboratorio Associado de Plasmas. The circuit delivers pulses with amplitude of 15V, full width at half maximum of 50μs and rise time of 0.7μs. The maximum time delay is 100ms. There are two channels with a fine adjustment of 0-1ms. The system can be manually or automatically driven. (author) [pt

  18. High voltage generator circuit with low power and high efficiency applied in EEPROM

    International Nuclear Information System (INIS)

    Liu Yan; Zhang Shilin; Zhao Yiqiang

    2012-01-01

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

  19. Analysis and Implementation of Cryptographic Hash Functions in Programmable Logic Devices

    Directory of Open Access Journals (Sweden)

    Tautvydas Brukštus

    2016-06-01

    Full Text Available In this day’s world, more and more focused on data pro-tection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryp-tographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryp-tographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less effi-ciency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be inves-tigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integ-rated circuit made using different dimension technology. Choo-sing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Re-search show the calculation speed and stability of different prog-rammable logic circuits.

  20. Speech and Language Delay

    Science.gov (United States)

    ... OTC Relief for Diarrhea Home Diseases and Conditions Speech and Language Delay Condition Speech and Language Delay Share Print Table of Contents1. ... Treatment6. Everyday Life7. Questions8. Resources What is a speech and language delay? A speech and language delay ...

  1. Analogue circuits simulation

    Energy Technology Data Exchange (ETDEWEB)

    Mendo, C

    1988-09-01

    Most analogue simulators have evolved from SPICE. The history and description of SPICE-like simulators are given. From a mathematical formulation of the electronic circuit the following analysis are possible: DC, AC, transient, noise, distortion, Worst Case and Statistical.

  2. Printed circuit for ATLAS

    CERN Multimedia

    Laurent Guiraud

    1999-01-01

    A printed circuit board made by scientists in the ATLAS collaboration for the transition radiaton tracker (TRT). This will read data produced when a high energy particle crosses the boundary between two materials with different electrical properties.

  3. Magnonic logic circuits

    International Nuclear Information System (INIS)

    Khitun, Alexander; Bao Mingqiang; Wang, Kang L

    2010-01-01

    We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

  4. Technology programme

    International Nuclear Information System (INIS)

    2007-01-01

    The technology activities carried out by the EURATOM-ENEA Association concern the continuation of the European Fusion Development Agreement (EFDA) as well as the ITER activities coordinated by the ITER International Office and Fusion for Energy. Also included in the activities are design and RD under the Broader Approach Agreement between the EU and Japan. In order to better contribute to the programme a number of consortium agreements among the Associations are being signed. Collaboration with industries in view of their participation in the construction of ITER was further strengthened, mainly in the field of magnet and divertor components. The new European Test Blanket Facility at ENEA Brasimone was completed; the design of the ITER radial neutron camera was optimised and the performance achievable with the in-vessel viewing system was further assessed by experimental trials. Design activities for the JT-60SA magnet and power supply system as well as the design and experimental activities related to the target of the International Fusion Materials Irradiation Facility were continued. Significant work was done to define quality assurance for neutronics analyses. Mockups of the ITER pre-compression ring made in glass fibre epoxy were tested. The activities and results documented in the following illustrate ENEA's efforts to support fusion development

  5. Thermal Aware Floorplanning Incorporating Temperature Dependent Wire Delay Estimation

    DEFF Research Database (Denmark)

    Winther, AndreasThor; Liu, Wei; Nannarelli, Alberto

    2015-01-01

    Temperature has a negative impact on metal resistance and thus wire delay. In state-of-the-art VLSI circuits, large thermal gradients usually exist due to the uneven distribution of heat sources. The difference in wire temperature can lead to performance mismatch because wires of the same length...... can have different delay. Traditional floorplanning algorithms use wirelength to estimate wire performance. In this work, we show that this does not always produce a design with the shortest delay and we propose a floorplanning algorithm taking into account temperature dependent wire delay as one...

  6. Comparative Effects of Circuit Training Programme on Speed and ...

    African Journals Online (AJOL)

    cce

    sprints are universally accepted by football coaches. ... by taking their relevant medical history and examining their physical health status. .... American College of Sports Medicine (1986) that recommended an exercise intensity of between.

  7. Variable Delay Element For Jitter Control In High Speed Data Links

    Science.gov (United States)

    Livolsi, Robert R.

    2002-06-11

    A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.

  8. Is the use of albumin in colloid prime solution of cardiopulmonary bypass circuit justified?

    NARCIS (Netherlands)

    Boks, RH; van Herwerden, LA; Takkenberg, JJM; van Oeveren, W; Gu, YJ; Wijers, MJ; Bogers, AJJC

    Background. Albumin in the priming solution precoats the surface of the cardiopulmonary bypass circuit, supposedly causing delayed adsorption of fibrinogen and reduced activation and adhesion of platelets. This action may result in lower transoxygenator resistance. Because our institution uses a

  9. Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

    Science.gov (United States)

    Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

    2015-01-01

    Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

  10. Project Circuits in a Basic Electric Circuits Course

    Science.gov (United States)

    Becker, James P.; Plumb, Carolyn; Revia, Richard A.

    2014-01-01

    The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

  11. Safety of steel vessel Magnox pressure circuits

    International Nuclear Information System (INIS)

    Stokoe, T.Y.; Bolton, C.J.; Heffer, P.J.H.

    1991-01-01

    The maintenance of pressure circuit integrity is fundamental to nuclear safety at the steel vessel Magnox stations. To confirm continued pressure circuit integrity the CEGB, as part of the Long Term Safety Review, has carried out extensive assessment and inspection in recent years. The assessment methods and inspection techniques employed are based on the most modern available. Reactor pressure vessel integrity is confirmed by a combination of arguments including safety factors inferred from the successful pre-service overpressure test, leak-before-break analysis and probabilistic assessment. In the case of other parts of the pressure circuits that are more accessible, comprising the boiler shells and interconnecting gas duct work, in-service inspection is a major element of the safety substantiation. The assessment and inspection techniques and the materials property data have been underpinned for many years by extensive research and development programmes and in-reactor monitoring of representative samples has also been undertaken. The paper summarises the work carried out to demonstrate the long term integrity of the Magnox pressure circuits and provides examples of the results obtained. (author)

  12. Nanoeletromechanical switch and logic circuits formed therefrom

    Science.gov (United States)

    Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

    2010-05-18

    A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

  13. Engineering embedded systems physics, programs, circuits

    CERN Document Server

    Hintenaus, Peter

    2015-01-01

    This is a textbook for graduate and final-year-undergraduate computer-science and electrical-engineering students interested in the hardware and software aspects of embedded and cyberphysical systems design. It is comprehensive and self-contained, covering everything from the basics to case-study implementation. Emphasis is placed on the physical nature of the problem domain and of the devices used. The reader is assumed to be familiar on a theoretical level with mathematical tools like ordinary differential equation and Fourier transforms. In this book these tools will be put to practical use. Engineering Embedded Systems begins by addressing basic material on signals and systems, before introducing to electronics. Treatment of digital electronics accentuating synchronous circuits and including high-speed effects proceeds to micro-controllers, digital signal processors and programmable logic. Peripheral units and decentralized networks are given due weight. The properties of analog circuits and devices like ...

  14. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  15. Nonlinear dynamics based digital logic and circuits.

    Science.gov (United States)

    Kia, Behnam; Lindner, John F; Ditto, William L

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

  16. Low latency asynchronous interface circuits

    Science.gov (United States)

    Sadowski, Greg

    2017-06-20

    In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

  17. Deep learning with coherent nanophotonic circuits

    Science.gov (United States)

    Shen, Yichen; Harris, Nicholas C.; Skirlo, Scott; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Sun, Xin; Zhao, Shijie; Larochelle, Hugo; Englund, Dirk; Soljačić, Marin

    2017-07-01

    Artificial neural networks are computational network models inspired by signal processing in the brain. These models have dramatically improved performance for many machine-learning tasks, including speech and image recognition. However, today's computing hardware is inefficient at implementing neural networks, in large part because much of it was designed for von Neumann computing schemes. Significant effort has been made towards developing electronic architectures tuned to implement artificial neural networks that exhibit improved computational speed and accuracy. Here, we propose a new architecture for a fully optical neural network that, in principle, could offer an enhancement in computational speed and power efficiency over state-of-the-art electronics for conventional inference tasks. We experimentally demonstrate the essential part of the concept using a programmable nanophotonic processor featuring a cascaded array of 56 programmable Mach-Zehnder interferometers in a silicon photonic integrated circuit and show its utility for vowel recognition.

  18. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  19. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  20. Synthesis for robust synchronization of chaotic systems under output feedback control with multiple random delays

    International Nuclear Information System (INIS)

    Wen Guilin; Wang Qingguo; Lin Chong; Han Xu; Li Guangyao

    2006-01-01

    Synchronization under output feedback control with multiple random time delays is studied, using the paradigm in nonlinear physics-Chua's circuit. Compared with other synchronization control methods, output feedback control with multiple random delay is superior for a realistic synchronization application to secure communications. Sufficient condition for global stability of delay-dependent synchronization is established based on the LMI technique. Numerical simulations fully support the analytical approach, in spite of the random delays

  1. A high-precision synchronization circuit for clock distribution

    International Nuclear Information System (INIS)

    Lu Chong; Tan Hongzhou; Duan Zhikui; Ding Yi

    2015-01-01

    In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm 2 , and the power consumption is 1.64 mW at 500 MHz. (paper)

  2. Junction and circuit fabrication

    International Nuclear Information System (INIS)

    Jackel, L.D.

    1980-01-01

    Great strides have been made in Josephson junction fabrication in the four years since the first IC SQUID meeting. Advances in lithography have allowed the production of devices with planar dimensions as small as a few hundred angstroms. Improved technology has provided ultra-high sensitivity SQUIDS, high-efficiency low-noise mixers, and complex integrated circuits. This review highlights some of the new fabrication procedures. The review consists of three parts. Part 1 is a short summary of the requirements on junctions for various applications. Part 2 reviews intergrated circuit fabrication, including tunnel junction logic circuits made at IBM and Bell Labs, and microbridge radiation sources made at SUNY at Stony Brook. Part 3 describes new junction fabrication techniques, the major emphasis of this review. This part includes a discussion of small oxide-barrier tunnel junctions, semiconductor barrier junctions, and microbridge junctions. Part 3 concludes by considering very fine lithography and limitations to miniaturization. (orig.)

  3. UAVs and Control Delays

    National Research Council Canada - National Science Library

    de Vries, S. C

    2005-01-01

    .... Delays of about 250-300 ms often lead to unacceptable airplane handling qualities. Techniques such as filtering and predictive displays may extend the range of acceptable delays up to about 400 ms...

  4. Delayed puberty in boys

    Science.gov (United States)

    ... page: //medlineplus.gov/ency/article/007695.htm Delayed puberty in boys To use the sharing features on this page, please enable JavaScript. Delayed puberty in boys is when puberty does not begin ...

  5. National programme: Finland

    International Nuclear Information System (INIS)

    Forsten, J.

    1986-01-01

    Finland's programmes in the field of reactor pressure components are presented in this paper. The following information on each of these programmes is given: the brief description of the programme; the programme's schedule and duration; the name of the project manager

  6. A deadtime reduction circuit for thermal neutron coincidence counters with Amptek preamplifiers

    International Nuclear Information System (INIS)

    Bourret, S.C.; Krick, M.S.

    1994-01-01

    We have developed a deadtime reduction circuit for thermal neutron coincidence counters using Amptek preamplifier/amplifier/discriminator circuits. The principle is to remove the overlap between the output pulses from the Amptek circuits by adding a derandomizer between the Amptek circuits and the shift-register coincidence electronics. We implemented the derandomizer as an Actel programmable logic array; the derandomizer board is small and can be mounted in the high-voltage junction box with the Amptek circuits, if desired. Up to 32 Amptek circuits can be used with one derandomizer. The derandomizer has seven outputs: four groups of eight inputs, two groups of 16 inputs, and one group of 32 inputs. We selected these groupings to facilitate detector ring-ratio measurements. The circuit was tested with the five-ring research multiplicity counter, which has five output signals-one for each ring. The counter's deadtime was reduced from 70 to 30 ns

  7. Small circuits for cryptography.

    Energy Technology Data Exchange (ETDEWEB)

    Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

    2005-10-01

    This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

  8. Silicon integrated circuit process

    International Nuclear Information System (INIS)

    Lee, Jong Duck

    1985-12-01

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  9. Primer printed circuit boards

    CERN Document Server

    Argyle, Andrew

    2009-01-01

    Step-by-step instructions for making your own PCBs at home. Making your own printed circuit board (PCB) might seem a daunting task, but once you master the steps, it's easy to attain professional-looking results. Printed circuit boards, which connect chips and other components, are what make almost all modern electronic devices possible. PCBs are made from sheets of fiberglass clad with copper, usually in multiplelayers. Cut a computer motherboard in two, for instance, and you'll often see five or more differently patterned layers. Making boards at home is relatively easy

  10. Silicon integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Jong Duck

    1985-12-15

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  11. Circuit design for reliability

    CERN Document Server

    Cao, Yu; Wirth, Gilson

    2015-01-01

    This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

  12. Electronic circuits fundamentals & applications

    CERN Document Server

    Tooley, Mike

    2015-01-01

    Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The

  13. Delayed Orgasm and Anorgasmia

    OpenAIRE

    Jenkins, Lawrence C.; Mulhall, John P.

    2015-01-01

    Delayed orgasm/anorgasmia defined as the persistent or recurrent difficulty, delay in, or absence of attaining orgasm after sufficient sexual stimulation, which causes personal distress. Delayed orgasm and anorgasmia are associated with significant sexual dissatisfaction. A focused medical history can shed light on the potential etiologies; which include: medications, penile sensation loss, endocrinopathies, penile hyperstimulation and psychological etiologies, amongst others. Unfortunately, ...

  14. The practical engineer-fine-tuning memory macros using variable internal delays

    CERN Document Server

    Gray, K

    1999-01-01

    Embedded memory blocks are extremely common in application-specific IC (ASIC) chips. In this era of design reuse, it is critical that these memory macros, as they are also called, should be as versatile as possible. Their $9 performance should be optimal, with adequate sense amplifier signal over the full manufacturing process range of the chip. Fortunately, several simple techniques exist for adapting memory macros to different applications running at $9 different speeds. The key is to design in delays that are variable and/or programmable. The approach is also helpful in debugging initial hardware where a memory macro is refusing to function because its timing is too fast and there $9 is insufficient internal delay for proper circuit operation. The techniques can also eliminate the process of redesigning and refabricating the initial hardware just to characterize it. A memory macro is made to function by internal $9 pulses, generated in the correct number, sequence and relationship by the internal timing ch...

  15. Study of the phase delay in the amplitude-modulated harmonic oscillator

    International Nuclear Information System (INIS)

    Krupska, Aldona; Krupski, Marcin

    2003-01-01

    The delayed response of a damped harmonic oscillator (RLC circuit) to a slow periodic disturbance is presented. This communication is supplementary to the paper published recently (Krupska et al 2001 Eur. J. Phys. 22 133-8)

  16. New reactor safety circuit for low-power-level operation

    International Nuclear Information System (INIS)

    McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

    1978-01-01

    In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

  17. Predicting the behavior of microfluidic circuits made from discrete elements

    Science.gov (United States)

    Bhargava, Krisna C.; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah

    2015-10-01

    Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand.

  18. Predicting the behavior of microfluidic circuits made from discrete elements.

    Science.gov (United States)

    Bhargava, Krisna C; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah

    2015-10-30

    Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand.

  19. ESD analog circuits and design

    CERN Document Server

    Voldman, Steven H

    2014-01-01

    A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

  20. Unstable oscillators based hyperchaotic circuit

    DEFF Research Database (Denmark)

    Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.

    1999-01-01

    A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...

  1. The test of VLSI circuits

    Science.gov (United States)

    Baviere, Ph.

    Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

  2. Electronic Circuit Analysis Language (ECAL)

    Science.gov (United States)

    Chenghang, C.

    1983-03-01

    The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

  3. An integrated circuit switch

    Science.gov (United States)

    Bonin, E. L.

    1969-01-01

    Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

  4. Automatic sweep circuit

    International Nuclear Information System (INIS)

    Keefe, D.J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input is described. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found

  5. Automatic sweep circuit

    Science.gov (United States)

    Keefe, Donald J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

  6. "Printed-circuit" rectenna

    Science.gov (United States)

    Dickinson, R. M.

    1977-01-01

    Rectifying antenna is less bulky structure for absorbing transmitted microwave power and converting it into electrical current. Printed-circuit approach, using microstrip technology and circularly polarized antenna, makes polarization orientation unimportant and allows much smaller arrays for given performance. Innovation is particularly useful with proposed electric vehicles powered by beam microwaves.

  7. Het onzichtbare circuit

    NARCIS (Netherlands)

    Nauta, Bram

    2013-01-01

    De chip, of geïntegreerde schakeling, heeft in een razend tempo ons leven ingrijpend veranderd. Het lijkt zo vanzelfsprekend dat er weer een nieuwe generatie smartphones, tablets of computers is. Maar dat is het niet. Prof.dr.ir. Bram Nauta, hoogleraar Integrated Circuit Design, laat in zijn rede

  8. Voltage regulating circuit

    NARCIS (Netherlands)

    2005-01-01

    A voltage regulating circuit comprising a rectifier (2) for receiving an AC voltage (Vmains) and for generating a rectified AC voltage (vrec), and a capacitor (3) connected in parallel with said rectified AC voltage for providing a DC voltage (VDC) over a load (5), characterized by a unidirectional

  9. Streaming Reduction Circuit

    NARCIS (Netherlands)

    Gerards, Marco Egbertus Theodorus; Kuper, Jan; Kokkeler, Andre B.J.; Molenkamp, Egbert

    2009-01-01

    Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths

  10. A Magnetic Circuit Demonstration.

    Science.gov (United States)

    Vanderkooy, John; Lowe, June

    1995-01-01

    Presents a demonstration designed to illustrate Faraday's, Ampere's, and Lenz's laws and to reinforce the concepts through the analysis of a two-loop magnetic circuit. Can be made dramatic and challenging for sophisticated students but is suitable for an introductory course in electricity and magnetism. (JRH)

  11. Programme for test generation for combinatorial and sequential systems

    International Nuclear Information System (INIS)

    Tran Huy Hoan

    1973-01-01

    This research thesis reports the computer-assisted search for tests aimed at failure detection in combinatorial and sequential logic circuits. As he wants to deal with complex circuits with many modules such as those met in large scale integrated circuits (LSI), the author used propagation paths. He reports the development of a method which is valid for combinatorial systems and for several sequential circuits comprising elementary logic modules and JK and RS flip-flops. This method is developed on an IBM 360/91 computer in PL/1 language. The used memory space is limited and adjustable with respect to circuit dimension. Computing time is short when compared to that needed by other programmes. The solution is practical and efficient for failure test and localisation

  12. Management of delayed nuclear power plant projects

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1999-09-01

    According to the available information at the IAEA PRIS (Power Reactor Information System) at the end of 1998 there were more than 40 nuclear power plant projects with delays of five or more years with respect to the originally scheduled commercial operation. The degree of conformance with original construction schedules showed large variations due to several issues, including financial, economic and public opinion factors. Taking into account the number of projects with several years delay in their original schedules, it was considered useful to identify the subject areas where exchange of experience among Member States would be mutually beneficial in identification of problems and development of guidance for successful management of the completion of these delayed projects. A joint programme of the IAEA Departments of Nuclear Energy (Nuclear Power Engineering Section) and Technical Co-operation (Europe Section, with additional support from the Latin America and West Asia Sections) was set up during the period 1997-1998. The specific aim of the programme was to provide assistance in the management of delayed nuclear power plants regarding measures to maintain readiness for resuming the project implementation schedule when the conditions permit. The integration of IAEA interdepartmental resources enabled the participation of 53 experts from 14 Member States resulting in a wider exchange of experience and dissemination of guidance. Under the framework of the joint programme, senior managers directly responsible for delayed nuclear power plant projects identified several issues or problem areas that needed to be addressed and guidance on management be provided. A work plan for the development of several working documents, addressing the different issues, was established. Subsequently these documents were merged into a single one to produce the present publication. This publication provides information and practical examples on necessary management actions to preserve

  13. Management of delayed nuclear power plant projects

    International Nuclear Information System (INIS)

    1999-09-01

    According to the available information at the IAEA PRIS (Power Reactor Information System) at the end of 1998 there were more than 40 nuclear power plant projects with delays of five or more years with respect to the originally scheduled commercial operation. The degree of conformance with original construction schedules showed large variations due to several issues, including financial, economic and public opinion factors. Taking into account the number of projects with several years delay in their original schedules, it was considered useful to identify the subject areas where exchange of experience among Member States would be mutually beneficial in identification of problems and development of guidance for successful management of the completion of these delayed projects. A joint programme of the IAEA Departments of Nuclear Energy (Nuclear Power Engineering Section) and Technical Co-operation (Europe Section, with additional support from the Latin America and West Asia Sections) was set up during the period 1997-1998. The specific aim of the programme was to provide assistance in the management of delayed nuclear power plants regarding measures to maintain readiness for resuming the project implementation schedule when the conditions permit. The integration of IAEA interdepartmental resources enabled the participation of 53 experts from 14 Member States resulting in a wider exchange of experience and dissemination of guidance. Under the framework of the joint programme, senior managers directly responsible for delayed nuclear power plant projects identified several issues or problem areas that needed to be addressed and guidance on management be provided. A work plan for the development of several working documents, addressing the different issues, was established. Subsequently these documents were merged into a single one to produce the present publication. This publication provides information and practical examples on necessary management actions to preserve

  14. Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

    Science.gov (United States)

    Abedini-Nassab, Roozbeh

    Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into

  15. The primary circuit of the dragon high temperature reactor experiment

    International Nuclear Information System (INIS)

    Simon, R.

    2005-01-01

    The 20 MWth Dragon Reactor Experiment was the first HTGR (High Temperature Gas-cooled Reactor) with coated particle fuel. Its purpose was to test fuel and materials for the High Temperature Reactor programmes pursued in Europe 40 years ago. This paper describes the design and construction of the primary (helium) circuit. It summarizes the main design objectives, lists the performance data and explains the flow paths of the heat removal and helium purification systems. The principal circuit accidents postulated are discussed and the choice of the main construction materials is given. (author)

  16. The LMT circuit and SPICE

    DEFF Research Database (Denmark)

    Lindberg, Erik; Murali, K.; Tamacevicius, Arunas

    2006-01-01

    The state equations of the LMT circuit are modeled as a dedicated analogue computer circuit and solved by means of PSpice. The nonlinear part of the system is studied. Problems with the PSpice program are presented....

  17. Resistor Combinations for Parallel Circuits.

    Science.gov (United States)

    McTernan, James P.

    1978-01-01

    To help simplify both teaching and learning of parallel circuits, a high school electricity/electronics teacher presents and illustrates the use of tables of values for parallel resistive circuits in which total resistances are whole numbers. (MF)

  18. Detecting short circuits during assembly

    Science.gov (United States)

    Deboo, G. J.

    1980-01-01

    Detector circuit identifies shorts between bus bars of electronic equipment being wired. Detector sounds alarm and indicates which planes are shorted. Power and ground bus bars are scanned continuously until short circuit occurs.

  19. BR-5 primary circuit decontamination

    International Nuclear Information System (INIS)

    Efimov, I.A.; Nikulin, M.P.; Smirnov-Averin, A.P.; Tymosh, B.S.; Shereshkov, V.S.

    1976-01-01

    Results and methodology of steam-water and acid decontamination of the primary coolant circuit SBR-5 reactor in 1971 are discussed. Regeneration process in a cold trap of the primary coolant circuit is discussed

  20. Basic Guidelines for Application of Performance Standards to Commissioning of DCS Digital Circuits

    Science.gov (United States)

    1992-06-01

    V6Z2J7 Canada Gustavo A. Cubas E. 1 Engineered Systems, Inc 2 Seccion De Transmission ATTN: Mr. David Gilfillan Direccion De Ingenieria Y Proyectos 14775...buffering, and and filter delay (for a voice circuit). Propagation delay is independent of data rate, while buffering delay is inversely proportional to...Complexe Des Jardins, 15th Fl. 171 N. Covington Drive 75 Rene Levesque West Bloomingdale, IL 60108 Montreal, PG H2Z Canada DISTRIBUTION LIST Department

  1. MOS voltage automatic tuning circuit

    OpenAIRE

    李, 田茂; 中田, 辰則; 松本, 寛樹

    2004-01-01

    Abstract ###Automatic tuning circuit adjusts frequency performance to compensate for the process variation. Phase locked ###loop (PLL) is a suitable oscillator for the integrated circuit. It is a feedback system that compares the input ###phase with the output phase. It can make the output frequency equal to the input frequency. In this paper, PLL ###fomed of MOSFET's is presented.The presented circuit consists of XOR circuit, Low-pass filter and Relaxation ###Oscillator. On PSPICE simulation...

  2. Behavioral synthesis of asynchronous circuits

    DEFF Research Database (Denmark)

    Nielsen, Sune Fallgaard

    2005-01-01

    This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...

  3. Selected collection of circuit drawings

    International Nuclear Information System (INIS)

    1977-01-01

    The many electronics circuits have been constracted in the Electronics Shop for use in nuclear experiments or other purposes of this Institute. The types of these circuits amount to about 500 items in total since 1968. This report describes the electronics circuit diagrams selected from this collection. The circuit details are not presented in this report, because these are already been published in the other technical reports. (auth.)

  4. Diode, transistor & fet circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

  5. Global chaos synchronization with channel time-delay

    International Nuclear Information System (INIS)

    Jiang Guoping; Zheng Weixing; Chen Guanrong

    2004-01-01

    This paper addresses a practical issue in chaos synchronization where there is a time-delay in the receiver as compared with the transmitter. A new synchronization scheme and a general criterion for global chaos synchronization are proposed and developed from the approach of unidirectional linear error feedback coupling with time-delay. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criterion under which the global chaos synchronization of the time-delay coupled systems is achieved

  6. The review of radiation effects of γ total dose in CMOS circuits

    International Nuclear Information System (INIS)

    Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

    1992-01-01

    Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

  7. Analysis of Bernstein's factorization circuit

    NARCIS (Netherlands)

    Lenstra, A.K.; Shamir, A.; Tomlinson, J.; Tromer, E.; Zheng, Y.

    2002-01-01

    In [1], Bernstein proposed a circuit-based implementation of the matrix step of the number field sieve factorization algorithm. These circuits offer an asymptotic cost reduction under the measure "construction cost x run time". We evaluate the cost of these circuits, in agreement with [1], but argue

  8. High voltage MOSFET switching circuit

    Science.gov (United States)

    McEwan, Thomas E.

    1994-01-01

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  9. Neuromorphic Silicon Neuron Circuits

    Science.gov (United States)

    Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

    2011-01-01

    Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

  10. Neuromorphic silicon neuron circuits

    Directory of Open Access Journals (Sweden)

    Giacomo eIndiveri

    2011-05-01

    Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

  11. High-explosive-driven delay line pulse generator

    International Nuclear Information System (INIS)

    Shearer, J.W.

    1982-01-01

    The inclusion of a delay line circuit into the design of a high-explosive-driven generator shortens the time constant of the output pulse. After a brief review of generator concepts and previously described pulse-shortening methods, a geometry is presented which incorporates delay line circuit techcniques into a coil generator. The circuit constants are adjusted to match the velocity of the generated electromagnetic wave to the detonation velocity of the high explosive. The proposed generator can be modeled by adding a variable inductance term to the telegrapher's equation. A particular solution of this equation is useful for exploring the operational parameters of the generator. The duration of the electromagnetic pulse equals the radial expansion time of the high-explosive-driven armature until it strikes the coil. Because the impedance of the generator is a constant, the current multiplication factor is limited only by nonlinear effects such as voltage breakdown, diffusion, and compression at high energies

  12. Integrated circuit structure

    International Nuclear Information System (INIS)

    1981-01-01

    The invention describes the fabrication of integrated circuit structures, such as read-only memory components of field-effect transistors, which may be fabricated and then maintained in inventory, and later selectively modified in accordance with a desired pattern. It is claimed that MOS depletion-mode devices in accordance with the invention can be fabricated at lower cost and at higher yields. (U.K.)

  13. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  14. Integrated coincidence circuits

    International Nuclear Information System (INIS)

    Borejko, V.F.; Grebenyuk, V.M.; Zinov, V.G.

    1976-01-01

    The description is given of two coincidence units employing integral circuits in the VISHNYA standard. The units are distinguished for the coincidence selection element which is essentially a combination of a tunnel diode and microcircuits. The output fast response of the units is at least 90 MHz in the mode of the output signal unshaped in duration and 50 MHz minimum in the mode of the output signal shaping. The resolution time of the units is dependent upon the duration of input signals

  15. Semiconductor integrated circuits

    International Nuclear Information System (INIS)

    Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

    1979-01-01

    An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

  16. Ghana's nuclear programme

    International Nuclear Information System (INIS)

    Ahafia, Albert K.

    1988-01-01

    The Paper gives the purpose of Ghana's Nuclear Programme and describes some specific research activities and peaceful applications of atomic energy in agriculture, medicine and industry. A discussion of some of the problem facing the programme concludes the Paper. (author)

  17. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    Science.gov (United States)

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

  18. Delayed orgasm and anorgasmia.

    Science.gov (United States)

    Jenkins, Lawrence C; Mulhall, John P

    2015-11-01

    Delayed orgasm/anorgasmia defined as the persistent or recurrent difficulty, delay in, or absence of attaining orgasm after sufficient sexual stimulation, which causes personal distress. Delayed orgasm and anorgasmia are associated with significant sexual dissatisfaction. A focused medical history can shed light on the potential etiologies, which include medications, penile sensation loss, endocrinopathies, penile hyperstimulation, and psychological etiologies. Unfortunately, there are no excellent pharmacotherapies for delayed orgasm/anorgasmia, and treatment revolves largely around addressing potential causative factors and psychotherapy. Copyright © 2015 American Society for Reproductive Medicine. Published by Elsevier Inc. All rights reserved.

  19. Interface Circuit For Printer Port

    Science.gov (United States)

    Tucker, Jerry H.; Yadlowsky, Ann B.

    1991-01-01

    Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

  20. Changes to the shuttle circuits

    CERN Multimedia

    GS Department

    2011-01-01

    To fit with passengers expectation, there will be some changes to the shuttle circuits as from Monday 10 October. See details on http://cern.ch/ShuttleService (on line on 7 October). Circuit No. 5 is cancelled as circuit No. 1 also stops at Bldg. 33. In order to guarantee shorter travel times, circuit No. 1 will circulate on Meyrin site only and circuit No. 2, with departures from Bldg. 33 and 500, on Prévessin site only. Site Services Section

  1. CHEETAH: circuit-switched high-speed end-to-end transport architecture

    Science.gov (United States)

    Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

    2003-10-01

    Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

  2. The Winfrith DSN programme

    International Nuclear Information System (INIS)

    Francescon, S.

    1963-05-01

    The programme, which is written in the Fortran language, solves the Carlson discrete S n approximation to the Boltzmann transport equation in cylindrical geometry. This report describes the input and output facilities of the WINFRITH DSN programme and the associated editing programme WED. (author)

  3. The Winfrith DSN programme

    Energy Technology Data Exchange (ETDEWEB)

    Francescon, S [General Reactor Physics Division, Atomic Energy Establishment, Winfrith, Dorchester, Dorset (United Kingdom)

    1963-05-15

    The programme, which is written in the Fortran language, solves the Carlson discrete S{sub n} approximation to the Boltzmann transport equation in cylindrical geometry. This report describes the input and output facilities of the WINFRITH DSN programme and the associated editing programme WED. (author)

  4. UNESCO's Ethics Education Programme.

    NARCIS (Netherlands)

    Have, H.A.M.J. ten

    2008-01-01

    Unesco initiated the Ethics Education Programme in 2004 at the request of member states to reinforce and increase the capacities in the area of ethics teaching. The programme is focused on providing detailed information about existing teaching programmes. It also develops and promotes teaching

  5. Thermionic integrated circuits: electronics for hostile environments

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

    1985-01-01

    Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

  6. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  7. An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

    Energy Technology Data Exchange (ETDEWEB)

    Duan Shukai [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China); School of Electronic and Information Engineering, Southwest University, Chongqing 400715 (China)], E-mail: duansk@swu.edu.cn; Liao Xiaofeng [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China)], E-mail: xfliao@cqu.edu.cn

    2007-09-10

    A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments.

  8. Integrated coherent matter wave circuits

    International Nuclear Information System (INIS)

    Ryu, C.; Boshier, M. G.

    2015-01-01

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

  9. Delay line clipping in a scintillation camera system

    International Nuclear Information System (INIS)

    Hatch, K.F.

    1979-01-01

    The present invention provides a novel base line restoring circuit and a novel delay line clipping circuit in a scintillation camera system. Single and double delay line clipped signal waveforms are generated for increasing the operational frequency and fidelity of data detection of the camera system by base line distortion such as undershooting, overshooting, and capacitive build-up. The camera system includes a set of photomultiplier tubes and associated amplifiers which generate sequences of pulses. These pulses are pulse-height analyzed for detecting a scintillation having an energy level which falls within a predetermined energy range. Data pulses are combined to provide coordinates and energy of photopeak events. The amplifiers are biassed out of saturation over all ranges of pulse energy level and count rate. Single delay line clipping circuitry is provided for narrowing the pulse width of the decaying electrical data pulses which increase operating speed without the occurrence of data loss. (JTA)

  10. A current-mode multi-valued adder circuit for multi-operand addition

    Science.gov (United States)

    Cini, Ugur; Morgül, Avni

    2011-06-01

    Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

  11. Swiss breeder research programme

    International Nuclear Information System (INIS)

    1992-01-01

    to find a sound base for the financial support. For the reactor physics research two almost parallel activities were considered. During the first period mainly existing know-how will be applied and a step by step familiarisation with the significance of fast breeder reactor physics is foreseen. New pointwise and group-wise cross section libraries based on ENDFIB-VI and JEF 1.1 have been prepared. A large (1250 MWe) sodium-cooled fast breeder reactor benchmark problem was calculated and the eigenvalues, isothermal core fuel Doppler-reactivities, effective delayed neutron fraction and reactivity worths were compared with a great number of solutions obtained in the past. During the following period new methods and models to calculate burnup-cycles of large breeder reactors should be developed and tested. Data libraries for shielding problems to be used in the ECCO code will be prepared and shielding problems calculated. The thermal hydraulics research is conducted to investigate the flow structures produced by two parallel layers of liquid at different velocities and temperatures. This problem arises particularly on occasions where natural circulation is prevailing and hot and cold streams of liquid come together. At present, tests are carried out with water in an horizontal glass channel (WAMIX). Two flow visualization techniques are being used: laser-sheet induced luminescence and image-analysis of video pictures taken with ink injection marking. Based on the image analysis a determination of the frequency of appearance of vortices (time-dependence) could be made. In the analytical area the computational thermal hydraulics code ASTEC was further validated by participation in an international benchmark calculation exercise. This code is also used to calculate the velocity profiles in the boundary layer of the inlet segment of the WAMIX test section. It is intended to directly participate in the European and the French R and D programmes for sodium-cooled fast breeder

  12. American Dream Delayed

    DEFF Research Database (Denmark)

    Khorunzhina, Natalia; Miller, Robert A.

    This paper investigates the delay in homeownership and a subsequent reduction in homeownership rate observed over the past decades. We focus on the delay in giving birth to children and increased labor market participation as contributing factors to homeownership dynamics for prime-age female hou...

  13. Synthesis of energy-efficient FSMs implemented in PLD circuits

    Science.gov (United States)

    Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

    2017-11-01

    The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

  14. Engineering genetic circuit interactions within and between synthetic minimal cells

    Science.gov (United States)

    Adamala, Katarzyna P.; Martin-Alarcon, Daniel A.; Guthrie-Honea, Katriona R.; Boyden, Edward S.

    2017-05-01

    Genetic circuits and reaction cascades are of great importance for synthetic biology, biochemistry and bioengineering. An open question is how to maximize the modularity of their design to enable the integration of different reaction networks and to optimize their scalability and flexibility. One option is encapsulation within liposomes, which enables chemical reactions to proceed in well-isolated environments. Here we adapt liposome encapsulation to enable the modular, controlled compartmentalization of genetic circuits and cascades. We demonstrate that it is possible to engineer genetic circuit-containing synthetic minimal cells (synells) to contain multiple-part genetic cascades, and that these cascades can be controlled by external signals as well as inter-liposomal communication without crosstalk. We also show that liposomes that contain different cascades can be fused in a controlled way so that the products of incompatible reactions can be brought together. Synells thus enable a more modular creation of synthetic biology cascades, an essential step towards their ultimate programmability.

  15. Dynamic pulse difference circuit

    International Nuclear Information System (INIS)

    Erickson, G.L.

    1978-01-01

    A digital electronic circuit of especial use for subtracting background activity pulses in gamma spectrometry is disclosed which comprises an up-down counter connected to count up with signal-channel pulses and to count down with background-channel pulses. A detector responsive to the count position of the up-down counter provides a signal when the up-down counter has completed one scaling sequence cycle of counts in the up direction. In an alternate embodiment, a detector responsive to the count position of the up-down counter provides a signal upon overflow of the counter

  16. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2007-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Each chapter ends with a set

  17. Electric circuits problem solver

    CERN Document Server

    REA, Editors of

    2012-01-01

    Each Problem Solver is an insightful and essential study and solution guide chock-full of clear, concise problem-solving gems. All your questions can be found in one convenient source from one of the most trusted names in reference solution guides. More useful, more practical, and more informative, these study aids are the best review books and textbook companions available. Nothing remotely as comprehensive or as helpful exists in their subject anywhere. Perfect for undergraduate and graduate studies.Here in this highly useful reference is the finest overview of electric circuits currently av

  18. Digital logic circuit test

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Gil Jung; Yang, Hong Young

    2011-03-15

    This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

  19. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  20. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  1. Nano integrated circuit process

    International Nuclear Information System (INIS)

    Yoon, Yung Sup

    2004-02-01

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  2. Electronic logic circuits

    CERN Document Server

    Gibson, J

    2013-01-01

    Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate

  3. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  4. Nano integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Yung Sup

    2004-02-15

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  5. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2011-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Ea

  6. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    1999-01-01

    This manual is a useful single-volume guide specifically aimed at the practical design engineer, technician, and experimenter, as well as the electronics student and amateur. It deals with the subject in an easy to read, down to earth, and non-mathematical yet comprehensive manner, explaining the basic principles and characteristics of the best known devices, and presenting the reader with many practical applications and over 200 circuits. Most of the ICs and other devices used are inexpensive and readily available types, with universally recognised type numbers.The second edition

  7. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  8. Calculation programme for transient thermo-pneumatic flows; Programme de calcul pour les ecoulements transitoires thermopneumatiques

    Energy Technology Data Exchange (ETDEWEB)

    Coste, D. [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1964-07-01

    With a view to determining the changes occurring in gas reactors after cooling accidents, a calculation programme is established for unidimensional gas flows with pressure drops, heat exchanges and in certain cases blowing, in a reticulated lattice. Any schematization can be taken into account by the use of a set of indices. This programme, of which the FORTRAN list is given, is applied to particular cases of sudden pressure drops in the circuits. The results obtained are in good agreement with those obtained both from the graphical method using the characteristics and from experimental recorded data. (author) [French] En vue de determiner les evolutions des reacteurs a gaz apres accident de refroidissement, on etablit un programme de calcul pour les ecoulements gazeux unidimensionnels avec pertes de charge, echanges thermiques et eventuellement soufflage, en reseau maille. Toute schematisation peut etre prise en compte grace a un jeu d'indices. Ce programme, dont la liste FORTRAN est presentee, est applique a des cas particuliers de degonflage brutal de circuits. Ses resultats sont en bon accord, d'une part avec ceux de la methode graphique des caracteristiques, d'autre part avec des enregistrements experimentaux. (auteur)

  9. Calculation programme for transient thermo-pneumatic flows; Programme de calcul pour les ecoulements transitoires thermopneumatiques

    Energy Technology Data Exchange (ETDEWEB)

    Coste, D [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1964-07-01

    With a view to determining the changes occurring in gas reactors after cooling accidents, a calculation programme is established for unidimensional gas flows with pressure drops, heat exchanges and in certain cases blowing, in a reticulated lattice. Any schematization can be taken into account by the use of a set of indices. This programme, of which the FORTRAN list is given, is applied to particular cases of sudden pressure drops in the circuits. The results obtained are in good agreement with those obtained both from the graphical method using the characteristics and from experimental recorded data. (author) [French] En vue de determiner les evolutions des reacteurs a gaz apres accident de refroidissement, on etablit un programme de calcul pour les ecoulements gazeux unidimensionnels avec pertes de charge, echanges thermiques et eventuellement soufflage, en reseau maille. Toute schematisation peut etre prise en compte grace a un jeu d'indices. Ce programme, dont la liste FORTRAN est presentee, est applique a des cas particuliers de degonflage brutal de circuits. Ses resultats sont en bon accord, d'une part avec ceux de la methode graphique des caracteristiques, d'autre part avec des enregistrements experimentaux. (auteur)

  10. Simple Cell Balance Circuit

    Science.gov (United States)

    Johnson, Steven D.; Byers, Jerry W.; Martin, James A.

    2012-01-01

    A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.

  11. Quantum-Circuit Refrigerator

    Science.gov (United States)

    MöTtöNen, Mikko; Tan, Kuan Y.; Masuda, Shumpei; Partanen, Matti; Lake, Russell E.; Govenius, Joonas; Silveri, Matti; Grabert, Hermann

    Quantum technology holds great potential in providing revolutionizing practical applications. However, fast and precise cooling of the functional quantum degrees of freedom on demand remains a major challenge in many solid-state implementations, such as superconducting circuits. We demonstrate direct cooling of a superconducting resonator mode using voltage-controllable quantum tunneling of electrons in a nanoscale refrigerator. In our first experiments on this type of a quantum-circuit refrigerator, we measure the drop in the mode temperature by electron thermometry at a resistor which is coupled to the resonator mode through ohmic losses. To eliminate unwanted dissipation, we remove the probe resistor and directly observe the power spectrum of the resonator output in agreement with the so-called P(E) theory. We also demonstrate in microwave reflection experiments that the internal quality factor of the resonator can be tuned by orders of magnitude. In the future, our refrigerator can be integrated with different quantum electric devices, potentially enhancing their performance. For example, it may prove useful in the initialization of superconducting quantum bits and in dissipation-assisted quantum annealing. We acknowledge European Research Council Grant SINGLEOUT (278117) and QUESS (681311) for funding.

  12. Quasi-Linear Circuit

    Science.gov (United States)

    Bradley, William; Bird, Ross; Eldred, Dennis; Zook, Jon; Knowles, Gareth

    2013-01-01

    This work involved developing spacequalifiable switch mode DC/DC power supplies that improve performance with fewer components, and result in elimination of digital components and reduction in magnetics. This design is for missions where systems may be operating under extreme conditions, especially at elevated temperature levels from 200 to 300 degC. Prior art for radiation-tolerant DC/DC converters has been accomplished utilizing classical magnetic-based switch mode converter topologies; however, this requires specific shielding and component de-rating to meet the high-reliability specifications. It requires complex measurement and feedback components, and will not enable automatic re-optimization for larger changes in voltage supply or electrical loading condition. The innovation is a switch mode DC/DC power supply that eliminates the need for processors and most magnetics. It can provide a well-regulated voltage supply with a gain of 1:100 step-up to 8:1 step down, tolerating an up to 30% fluctuation of the voltage supply parameters. The circuit incorporates a ceramic core transformer in a manner that enables it to provide a well-regulated voltage output without use of any processor components or magnetic transformers. The circuit adjusts its internal parameters to re-optimize its performance for changes in supply voltage, environmental conditions, or electrical loading at the output

  13. Delayed power analysis

    International Nuclear Information System (INIS)

    Adamovich, L.A.; Azarov, V.V.

    1999-01-01

    Time dependent core power behavior in a nuclear reactor is described with well-known neutron kinetics equations. At the same time, two portions are distinguished in energy released from uranium nuclei fission; one released directly at fission and another delayed (residual) portion produced during radioactive decay of fission products. While prompt power is definitely described with kinetics equations, the delayed power presentation still remains outstanding. Since in operation the delayed power part is relatively small (about 6%) operation, it can be neglected for small reactivity disturbances assuming that entire power obeys neutron kinetics equations. In case of a high negative reactivity rapidly inserted in core (e.g. reactor scram initiation) the prompt and delayed components can be calculated separately with practically no impact on each other, employing kinetics equations for prompt power and known approximation formulas for delayed portion, named residual in this specific case. Under substantial disturbances the prompt component in the dynamic process becomes commensurable with delayed portion, thus making necessary to take into account their cross impact. A system of differential equations to describe time-dependent behavior of delayed power is presented. Specific NPP analysis shows a way to significantly simplify the task formulation. (author)

  14. Arithmetic circuits for DSP applications

    CERN Document Server

    Stouraitis, Thanos

    2017-01-01

    Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

  15. Integrated circuit cooled turbine blade

    Science.gov (United States)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  16. Control circuit for transformer relay

    International Nuclear Information System (INIS)

    Wyatt, G.A.

    1984-01-01

    A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

  17. Hybrid CMOS/Molecular Integrated Circuits

    Science.gov (United States)

    Stan, M. R.; Rose, G. S.; Ziegler, M. M.

    CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

  18. Source-circuit design overview

    Science.gov (United States)

    Ross, R. G., Jr.

    1983-01-01

    The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

  19. REASONS FOR PATIENT DELAYS & HEALTH SYSTEM DELAYS FOR TUBERCULOSIS IN SOUTH INDIA

    Directory of Open Access Journals (Sweden)

    Kapil Goel

    2011-12-01

    Full Text Available Background: Globally, the burden of Tuberculosis is escalating. Early diagnosis and prompt initiation of tuberculosis treatment is essential for an effective tuberculosis control programme. Objectives: To study the self reported reasons for patient and health system (diagnosis & treatment delays in Tuberculosis patients. Methods: A community based cross sectional study was conducted among 98 new sputum positive TB cases aged > 15 years registered under RNTCP from Oct 2006 to June 2007 & receiving treatment under DOTS in Udupi taluk by interviewing them. Results: Total 98 patients were recruited and 68% were males. Out of 17 patients with patient delays, 82% felt that their symptoms were not severe, 71% felt that patient delay was due to lack of awareness and 71% did not take it seriously. Out of 86 patients with health system delays, 82.6% of patients mentioned that doctor has not advised for sputum examination, 76.7% of patients told that they first consulted a private doctor, 21% of them mentioned that doctor was unaware to diagnose TB. Conclusion: Symptoms not severe is the main reason for the patient delay and doctor didn’t advise for sputum examination is the main reason for health system delays.

  20. Delays in switching patients onto second-line antiretroviral treatment ...

    African Journals Online (AJOL)

    Background: South Africa has one of the largest antiretroviral treatment (ART) programmes globally. In addition to increasing access to ART, it is important that the health system also focuses on the appropriate management of patients who fail first-line ART. Delays in switching patients onto second-line ART can adversely ...

  1. Radiation-sensitive switching circuits

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J.H.; Cockshott, C.P.

    1976-03-16

    A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

  2. Four-junction superconducting circuit

    Science.gov (United States)

    Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

    2016-01-01

    We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

  3. Multi parametric card to personal computers interface based in ispLSI1016 circuits

    International Nuclear Information System (INIS)

    Osorio Deliz, J.F.; Toledo Acosta, R.B.; Arista Romeu, E.

    1997-01-01

    It is described the design and principal characteristic of the interface circuit for a 16 bit multi parametric add on card for IBM or compatible microcomputer which content two communication channels of direct memory access and bidirectional between the card and the computer, an interrupt controller, a programmable address register, a default add res register of the card, a four channels multiplexer, as well as the decoder logic of the 80C186 and computer. The circuit was designed with two programmable logic devices ispL1016, which allowed drastically to diminish the quantity of utilized components and get a more flexible design in less time better characteristics

  4. Neutron delayed choice experiments

    International Nuclear Information System (INIS)

    Bernstein, H.J.

    1986-01-01

    Delayed choice experiments for neutrons can help extend the interpretation of quantum mechanical phenomena. They may also rule out alternative explanations which static interference experiments allow. A simple example of a feasible neutron test is presented and discussed. (orig.)

  5. Quad nanosecond delay module

    International Nuclear Information System (INIS)

    McDonald, R.J.; Hunter, J.B.; Wozniak, G.J.

    1986-04-01

    Four nanosecond (ns) delay units have been designed to fit in a single-width NIM module. This module is particularly suited for use in conjunction with quad constant fraction timing discriminators (CFTDs) since it has four delay units that can be placed adjacent to the four units of the CFTD. A series of different length cables connected via DIP toggle switches provide delays of 0.60 ns in 4 ns increments. Thus, the CFTD delay can be optimized for pulses of different rise times from approx.10-100 ns. Design work for the PC board and silkscreening of the front panel were done with the MacDraw program on the Apple Mackintosh computer and printed with the Lasewriter printer. 6 refs

  6. Delayed rule following

    OpenAIRE

    Schmitt, David R.

    2001-01-01

    Although the elements of a fully stated rule (discriminative stimulus [SD], some behavior, and a consequence) can occur nearly contemporaneously with the statement of the rule, there is often a delay between the rule statement and the SD. The effects of this delay on rule following have not been studied in behavior analysis, but they have been investigated in rule-like settings in the areas of prospective memory (remembering to do something in the future) and goal pursuit. Discriminative even...

  7. Quad precision delay generator

    International Nuclear Information System (INIS)

    Krishnan, Shanti; Gopalakrishnan, K.R.; Marballi, K.R.

    1997-01-01

    A Quad Precision Delay Generator delays a digital edge by a programmed amount of time, varying from nanoseconds to microseconds. The output of this generator has an amplitude of the order of tens of volts and rise time of the order of nanoseconds. This was specifically designed and developed to meet the stringent requirements of the plasma focus experiments. Plasma focus is a laboratory device for producing and studying nuclear fusion reactions in hot deuterium plasma. 3 figs

  8. Universal programmable logic gate and routing method

    Science.gov (United States)

    Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

    2009-01-01

    An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

  9. Finnish bioenergy research programme

    Energy Technology Data Exchange (ETDEWEB)

    Asplund, D. [VTT Energy, Jyvaeskylae (Finland)

    1996-12-31

    Finland is a leading country in the use of biofuels and has excellent opportunities to increase the use of biofuels by up to 25-30 %. The Finnish Government has set an objective for the promotion of bioenergy. The aim is to increase the use of bioenergy by about 25 % from the present level by 2005, and the increment corresponds to 1.5 million tonnes of oil equivalent (toe) per year. The R and D work has been considered as an important factor to achieve this ambitious goal. Energy research was organised into a series of research programmes in 1988 in accordance with the proposal of Finnish Energy Research Committee. The object of the research programmes is to enhance research activities and to bundle individual projects together into larger research packages. The common target of the Finnish energy research programmes is to proceed from basic and applied research to product development and pilot operation, and after that to the first commercial applications, e.g. demonstrations. As the organisation of energy research to programmes has led to good results, the Finnish Ministry of Trade and Industry decided to go on with this practice by launching new six-year programmes in 1993-1998. One of these programmes is the Bioenergy Research Programme and the co-ordination of this programme is carried out by VTT Energy. Besides VTT Energy the Finnish Forest Research Institute, Work Efficiency Institute, Metsaeteho and University of Joensuu are participating in the programme 7 refs.

  10. Finnish bioenergy research programme

    Energy Technology Data Exchange (ETDEWEB)

    Asplund, D [VTT Energy, Jyvaeskylae (Finland)

    1997-12-31

    Finland is a leading country in the use of biofuels and has excellent opportunities to increase the use of biofuels by up to 25-30 %. The Finnish Government has set an objective for the promotion of bioenergy. The aim is to increase the use of bioenergy by about 25 % from the present level by 2005, and the increment corresponds to 1.5 million tonnes of oil equivalent (toe) per year. The R and D work has been considered as an important factor to achieve this ambitious goal. Energy research was organised into a series of research programmes in 1988 in accordance with the proposal of Finnish Energy Research Committee. The object of the research programmes is to enhance research activities and to bundle individual projects together into larger research packages. The common target of the Finnish energy research programmes is to proceed from basic and applied research to product development and pilot operation, and after that to the first commercial applications, e.g. demonstrations. As the organisation of energy research to programmes has led to good results, the Finnish Ministry of Trade and Industry decided to go on with this practice by launching new six-year programmes in 1993-1998. One of these programmes is the Bioenergy Research Programme and the co-ordination of this programme is carried out by VTT Energy. Besides VTT Energy the Finnish Forest Research Institute, Work Efficiency Institute, Metsaeteho and University of Joensuu are participating in the programme 7 refs.

  11. Memristor Circuits and Systems

    KAUST Repository

    Zidan, Mohammed A.

    2015-05-01

    Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort. In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results. Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for

  12. Basic electronic circuits

    CERN Document Server

    Buckley, P M

    1980-01-01

    In the past, the teaching of electricity and electronics has more often than not been carried out from a theoretical and often highly academic standpoint. Fundamentals and basic concepts have often been presented with no indication of their practical appli­ cations, and all too frequently they have been illustrated by artificially contrived laboratory experiments bearing little relationship to the outside world. The course comes in the form of fourteen fairly open-ended constructional experiments or projects. Each experiment has associated with it a construction exercise and an explanation. The basic idea behind this dual presentation is that the student can embark on each circuit following only the briefest possible instructions and that an open-ended approach is thereby not prejudiced by an initial lengthy encounter with the theory behind the project; this being a sure way to dampen enthusiasm at the outset. As the investigation progresses, questions inevitably arise. Descriptions of the phenomena encounte...

  13. ECCS control circuit

    International Nuclear Information System (INIS)

    Sato, Takashi.

    1986-01-01

    Purpose: To afford a sufficient margin to pressure vibrations upon starting of an automatic depressurization system by dispersing pressure vibration in suppression water due to the opening action of an automatic releaf valve in the automatic depressurization system thereby reducing the dynamic load exerted to the surface of the suppression walls. Constitution: Upon occurrence of loss of coolant accidents, an automatic releaf valve for automatic depressurization is opened to deliver the steams in the pressure vessel into the suppression pool. Since a plurality of automatic releaf valves have usually been disposed, if they are opened simultaneously, excess dynamic loads are exerted due to the pressure vibrations to the wall surface of the suppression pool. In this invention, a control circuit is disposed such that the opening timing for each of the automatic releaf valves is deviated upon occurrence of a driving signal for the automatic depressurization system to thereby disperse the pressure vibrations in the suppression water. (Kamimura, M.)

  14. A dishwasher for circuits

    CERN Multimedia

    Rosaria Marraffino

    2014-01-01

    You have always been told that electronic devices fear water. However, at the Surface Mount Devices (SMD) Workshop here at CERN all the electronic assemblies are cleaned with a machine that looks like a… dishwasher.   The circuit dishwasher. Credit: Clara Nellist.  If you think the image above shows a dishwasher, you wouldn’t be completely wrong. Apart from the fact that the whole pumping system and the case itself are made entirely from stainless steel and chemical resistant materials, and the fact that it washes electrical boards instead of dishes… it works exactly like a dishwasher. It’s a professional machine (mainly used in the pharmaceutical industry) designed to clean everything that can be washed with a water-based chemical soap. This type of treatment increases the lifetime of the electronic boards and therefore the LHC's reliability by preventing corrosion problems in the severe radiation and ozone environment of the LHC tunn...

  15. Modeling cortical circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Rohrer, Brandon Robinson; Rothganger, Fredrick H.; Verzi, Stephen J.; Xavier, Patrick Gordon

    2010-09-01

    The neocortex is perhaps the highest region of the human brain, where audio and visual perception takes place along with many important cognitive functions. An important research goal is to describe the mechanisms implemented by the neocortex. There is an apparent regularity in the structure of the neocortex [Brodmann 1909, Mountcastle 1957] which may help simplify this task. The work reported here addresses the problem of how to describe the putative repeated units ('cortical circuits') in a manner that is easily understood and manipulated, with the long-term goal of developing a mathematical and algorithmic description of their function. The approach is to reduce each algorithm to an enhanced perceptron-like structure and describe its computation using difference equations. We organize this algorithmic processing into larger structures based on physiological observations, and implement key modeling concepts in software which runs on parallel computing hardware.

  16. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Shikha Panwar

    2014-01-01

    Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

  17. Modelling delays in pharmacokinetics

    International Nuclear Information System (INIS)

    Farooqi, Z.H.; Lambrecht, R.M.

    1990-01-01

    Linear system analysis has come to form the backbone of pharmacokinetics. Natural systems usually involve time delays, thus models incorporating them would be an order closer approximation to the real world compared to those that do not. Delays may be modelled in several ways. The approach considered in this study is to have a discrete-time delay dependent rate with the delay respresenting the duration between the entry of a drug into a compartment and its release in some form (may be as a metabolite) from the compartment. Such a delay may be because of one or more of several physiological reasons, like, formation of a reservoir, slow metabolism, or receptor binding. The mathematical structure this gives rise to is a system of delay-differential equations. Examples are given of simple one and two compartment systems with drugs like bumetanide, carbamazepine, and quinolone-caffeine interaction. In these examples generally a good fit is obtained and the suggested models form a good approximation. 21 refs., 6 figs

  18. Radiofrequency spark chambers and delay line resonators

    International Nuclear Information System (INIS)

    Sayag, Jacques

    1971-01-01

    According to a suggestion of A. Kastler, a spark chamber was excited by an undamped radiofrequency pulse and tracks about 1 mm wide obtained; the result was interpreted by computation of the coefficients of electronic amplification and partial ambipolar diffusion. This work led us to the construction of a new fast triggering undamped wave-train generator of very high tension (patent taken out by the C.E.A. under the no.: EN 7 134 650 the 27.9.1971). Since this apparatus uses a resonant storage line, its design implied a precise knowledge of high impedance delay lines. The experimental radiofrequency spectra of the input impedance of opened or short-circuited lines were plotted completely and analysed by the circuits theory, new measuring methods were established, dispersion relations accurately checked and the equivalence of the formulas, within the third order, with theses of Debye's Dipolar Absorption demonstrated. General properties of Hilbert's transform were also investigated. From the experimental point of view, the electromagnetic energy storage process was extended to the case of a liquid nitrogen-immersed resonant delay line. The good behavior of the cryogenic experiment, where the main difficulty of icing was overcame by the construction of special electrodes, offers great promise for extrapolation to superconductivity. (author) [fr

  19. Monolithic microwave integrated circuit water vapor radiometer

    Science.gov (United States)

    Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

    1991-01-01

    A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

  20. Optical reversible programmable Boolean logic unit.

    Science.gov (United States)

    Chattopadhyay, Tanay

    2012-07-20

    Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.

  1. Noise distribution of a peak track and hold circuit

    International Nuclear Information System (INIS)

    Seller, Paul; Hardie, Alec L.; Morrissey, Quentin

    2012-01-01

    Noise in linear electronic circuits is well characterised in terms of power spectral density in the frequency domain and the Normal probability density function in the time domain. For instance a charge preamplifier followed by a simple time independent pulse shaping circuit produces an output with a predictable, easily calculated Normal density function. By the Ergodic Principle this is true if the signal is sampled randomly in time or the experiment is run many times and measured at a fixed time after the circuit is released from reset. Apart from well defined cases, the time of the sample after release of reset does not affect the density function. If this signal is then passed through a peak track-and-hold circuit the situation is very different. The probability density function of the sampled signal is no longer Normal and the function changes with the time of the sample after release of reset. This density function can be classified by the Gumbel probability density function which characterises the Extreme Value Distribution of a defined number of Normally distributed values. The number of peaks in the signal is an important factor in the analysis. This issue is analysed theoretically and compared with a time domain noise simulation programme. This is then related to a real electronic circuit used for low-noise X-ray measurements and shows how the low-energy resolution of this system is significantly degraded when using a peak track-and-hold.

  2. Note concerning the Ecasac programme; Note sur le programme ecasac

    Energy Technology Data Exchange (ETDEWEB)

    Bras, D [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1969-07-01

    The analytical programme developed by the firm I.B.M. for ECAP electronic circuits, operated initially on the IBM 1620 computer with a certain limitation on the size of the network studied, but already equipped from the conversational angle (type-writer). The IBM 360 computers made it possible to increase the size of the network treated to 50 nodes and 200 branches, but the conversational aspect was suppressed in the ECAP 360 version. With a view to making use of the possibilities of hybrid computers, we have adapted this latter version to the EAI 8400 computer. Without diminishing it in any way, we have modified it so as to provide it with conversational characteristics by using the computers control panel; to give it still further flexibility we have made it possible to record curves during the calculation operation, and to obtain a division of the printed results. To obtain the curves, use was made of analog digital converters of the interface of the hybrid unit EAI 8900 of which the EAI 8400 computer represents the numerical section. The modifications made concern in particular the A.C. analysis and the transient analysis. They facilitate and complete the input of the data; they allow modifications to be made for the calculation of these analyses; they also improve the presentation of the results and facilitate their interpretation. They constitute finally the version ECASAC, i.e. the programme ECAP 360 made conversational by use of a type-writer, with automatic output of the curves. (author) [French] Le programme d'analyse de circuits electroniques ECAP, mis au point par la firme I.B.M., a d'abord fonctionne sur ordinateur IBM 1620 avec une certaine limitation pour la taille du reseau etudie, mais deja une optique conversationnelle (machine a ecrire). Les ordinateurs IBM 360 ont permis d'accroitre la taille du reseau permis a 50 noeuds et 200 branches, mais par contre l'optique conversationnelle fut supprimee dans la version ECAP 360. Dans le but d

  3. Compact Circuit Preprocesses Accelerometer Output

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1993-01-01

    Compact electronic circuit transfers dc power to, and preprocesses ac output of, accelerometer and associated preamplifier. Incorporated into accelerometer case during initial fabrication or retrofit onto commercial accelerometer. Made of commercial integrated circuits and other conventional components; made smaller by use of micrologic and surface-mount technology.

  4. Comminution circuits for compact itabirites

    Directory of Open Access Journals (Sweden)

    Pedro Ferreira Pinto

    Full Text Available Abstract In the beneficiation of compact Itabirites, crushing and grinding account for major operational and capital costs. As such, the study and development of comminution circuits have a fundamental importance for feasibility and optimization of compact Itabirite beneficiation. This work makes a comparison between comminution circuits for compact Itabirites from the Iron Quadrangle. The circuits developed are: a crushing and ball mill circuit (CB, a SAG mill and ball mill circuit (SAB and a single stage SAG mill circuit (SSSAG. For the SAB circuit, the use of pebble crushing is analyzed (SABC. An industrial circuit for 25 million tons of run of mine was developed for each route from tests on a pilot scale (grinding and industrial scale. The energy consumption obtained for grinding in the pilot tests was compared with that reported by Donda and Bond. The SSSAG route had the lowest energy consumption, 11.8kWh/t and the SAB route had the highest energy consumption, 15.8kWh/t. The CB and SABC routes had a similar energy consumption of 14.4 kWh/t and 14.5 kWh/t respectively.

  5. Current-mode minimax circuit

    NARCIS (Netherlands)

    Wassenaar, R.F.

    1992-01-01

    The minimum-maximum (minimax) circuit selects the minimum and maximum of two input currents. Four transistors in matched pairs are operated in the saturation region. Because the behavior of the circuit is based on matched devices and is independent of the relationship between the drain current and

  6. Short-circuit impedance measurement

    DEFF Research Database (Denmark)

    Pedersen, Knud Ole Helgesen; Nielsen, Arne Hejde; Poulsen, Niels Kjølstad

    2003-01-01

    Methods for estimating the short-circuit impedance in the power grid are investigated for various voltage levels and situations. The short-circuit impedance is measured, preferably from naturally occurring load changes in the grid, and it is shown that such a measurement system faces different...

  7. Cell short circuit, preshort signature

    Science.gov (United States)

    Lurie, C.

    1980-01-01

    Short-circuit events observed in ground test simulations of DSCS-3 battery in-orbit operations are analyzed. Voltage signatures appearing in the data preceding the short-circuit event are evaluated. The ground test simulation is briefly described along with performance during reconditioning discharges. Results suggest that a characteristic signature develops prior to a shorting event.

  8. Enhancement of Linear Circuit Program

    DEFF Research Database (Denmark)

    Gaunholt, Hans; Dabu, Mihaela; Beldiman, Octavian

    1996-01-01

    In this report a preliminary user friendly interface has been added to the LCP2 program making it possible to describe an electronic circuit by actually drawing the circuit on the screen. Component values and other options and parameters can easily be set by the aid of the interface. The interface...

  9. Non-Destructive Investigation on Short Circuit Capability of Wind-Turbine-Scale IGBT Power Modules

    DEFF Research Database (Denmark)

    Wu, Rui; Iannuzzo, Francesco; Wang, Huai

    2014-01-01

    This paper presents a comprehensive investigation on the short circuit capability of wind-turbine-scale IGBT power modules by means of a 6 kA/1.1 kV non-destructive testing system. A Field Programmable Gate Array (FPGA) supervising unit is adpoted to achieve an accurate time control for short...... circuit test, which enables to define the driving signals with an accuracy of 10 ns. Thanks to the capability and the effectiveness of the constructed setup, oscillations appearing during short circuits of the new-generation 1.7 kV/1 kA IGBT power modules have been evidenced and characterized under...

  10. MOS Current Mode Logic Near Threshold Circuits

    Directory of Open Access Journals (Sweden)

    Alexander Shapiro

    2014-06-01

    Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

  11. Wavy Channel TFT-Based Digital Circuits

    KAUST Repository

    Hanna, Amir; Hussain, Aftab M.; Hussain, Aftab M.; Hussain, Aftab M.; Omran, Hesham; Alsharif, Sarah M.; Salama, Khaled N.; Hussain, Muhammad Mustafa

    2016-01-01

    We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

  12. Wavy Channel TFT-Based Digital Circuits

    KAUST Repository

    Hanna, Amir

    2016-02-23

    We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

  13. Fractional Delayer Utilizing Hermite Interpolation with Caratheodory Representation

    Directory of Open Access Journals (Sweden)

    Qiang DU

    2018-04-01

    Full Text Available Fractional delay is indispensable for many sorts of circuits and signal processing applications. Fractional delay filter (FDF utilizing Hermite interpolation with an analog differentiator is a straightforward way to delay discrete signals. This method has a low time-domain error, but a complicated sampling module than the Shannon sampling scheme. A simplified scheme, which is based on Shannon sampling and utilizing Hermite interpolation with a digital differentiator, will lead a much higher time-domain error when the signal frequency approaches the Nyquist rate. In this letter, we propose a novel fractional delayer utilizing Hermite interpolation with Caratheodory representation. The samples of differential signal are obtained by Caratheodory representation from the samples of the original signal only. So, only one sampler is needed and the sampling module is simple. Simulation results for four types of signals demonstrate that the proposed method has significantly higher interpolation accuracy than Hermite interpolation with digital differentiator.

  14. Automatic circuit analysis based on mask information

    International Nuclear Information System (INIS)

    Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.

    1976-01-01

    The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program

  15. Novel concept of TDI readout circuit for LWIR detector

    Science.gov (United States)

    Kim, Byunghyuck; Yoon, Nanyoung; Lee, Hee Chul; Kim, Choong-Ki

    2000-07-01

    Noise property is the prime consideration in readout circuit design. The output noise caused by the photon noise, which dominates total noise in BLIP detectors, is limited by the integration time that an element looks at a specific point in the scene. Large integration time leads to a low noise performance. Time-delay integration (TDI) is used to effectively increase the integration time and reduce the photon noise. However, it increases the number of dead pixels and requires large integration capacitors and low noise output stage of the readout circuit. In this paper, to solve these problems, we propose a new concept of readout circuit, which performs background suppression, cell-to-cell background current non-uniformity compensation, and dead pixel correction using memory, ADC, DAC, and current copier cell. In simulation results, comparing with the conventional TDI readout circuit, the integration capacitor size can be reduced to 1/5 and trans-impedance gain can be increased by five times. Therefore, the new TDI readout circuit does not require large area and low noise output stage. And the error of skimming current is less than 2%, and the fixed pattern noise induced by cell-to-cell background current variation is reduced to less than 1%.

  16. High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

    CERN Document Server

    Palchaudhuri, Ayan

    2016-01-01

    This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

  17. Updating Procedures Can Reorganize the Neural Circuit Supporting a Fear Memory.

    Science.gov (United States)

    Kwapis, Janine L; Jarome, Timothy J; Ferrara, Nicole C; Helmstetter, Fred J

    2017-07-01

    Established memories undergo a period of vulnerability following retrieval, a process termed 'reconsolidation.' Recent work has shown that the hypothetical process of reconsolidation is only triggered when new information is presented during retrieval, suggesting that this process may allow existing memories to be modified. Reconsolidation has received increasing attention as a possible therapeutic target for treating disorders that stem from traumatic memories, yet little is known about how this process changes the original memory. In particular, it is unknown whether reconsolidation can reorganize the neural circuit supporting an existing memory after that memory is modified with new information. Here, we show that trace fear memory undergoes a protein synthesis-dependent reconsolidation process following exposure to a single updating trial of delay conditioning. Further, this reconsolidation-dependent updating process appears to reorganize the neural circuit supporting the trace-trained memory, so that it better reflects the circuit supporting delay fear. Specifically, after a trace-to-delay update session, the amygdala is now required for extinction of the updated memory but the retrosplenial cortex is no longer required for retrieval. These results suggest that updating procedures could be used to force a complex, poorly defined memory circuit to rely on a better-defined neural circuit that may be more amenable to behavioral or pharmacological manipulation. This is the first evidence that exposure to new information can fundamentally reorganize the neural circuit supporting an existing memory.

  18. Fusion technology programme

    International Nuclear Information System (INIS)

    Finken, D.

    1984-04-01

    KfK participates to the Fusion Technology Programme of the European Community. Most of the work in progress addresses the Next European Torus (NET) and the long term technology aspects as defined in the 82/86 programme. A minor part serves to preparation of future contributions and to design studies on fusion concepts in a wider perspective. The Fusion Technology Programme of Euratom covers mainly aspects of nuclear engineering. Plasma engineering, heating, refueling and vacuum technology are at present part of the Physics Programme. In view of NET, integration of the different areas of work will be mandatory. KfK is therefore prepared to address technical aspects beyond the actual scope of the physics experiments. The technology tasks are reported project wise under title and code of the Euratom programme. Most of the projects described here are shared with other European fusion laboratories as indicated in the table annexed to this report. (orig./GG)

  19. Note concerning the Ecasac programme

    International Nuclear Information System (INIS)

    Bras, D.

    1969-01-01

    The analytical programme developed by the firm I.B.M. for ECAP electronic circuits, operated initially on the IBM 1620 computer with a certain limitation on the size of the network studied, but already equipped from the conversational angle (type-writer). The IBM 360 computers made it possible to increase the size of the network treated to 50 nodes and 200 branches, but the conversational aspect was suppressed in the ECAP 360 version. With a view to making use of the possibilities of hybrid computers, we have adapted this latter version to the EAI 8400 computer. Without diminishing it in any way, we have modified it so as to provide it with conversational characteristics by using the computers control panel; to give it still further flexibility we have made it possible to record curves during the calculation operation, and to obtain a division of the printed results. To obtain the curves, use was made of analog digital converters of the interface of the hybrid unit EAI 8900 of which the EAI 8400 computer represents the numerical section. The modifications made concern in particular the A.C. analysis and the transient analysis. They facilitate and complete the input of the data; they allow modifications to be made for the calculation of these analyses; they also improve the presentation of the results and facilitate their interpretation. They constitute finally the version ECASAC, i.e. the programme ECAP 360 made conversational by use of a type-writer, with automatic output of the curves. (author) [fr

  20. Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

    Science.gov (United States)

    Yuan, S. C.

    2008-11-01

    We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

  1. Optimal Joint Expected Delay Forwarding in Delay Tolerant Networks

    OpenAIRE

    Jia Xu; Xin Feng; Wen Jun Yang; Ru Chuan Wang; Bing Qing Han

    2013-01-01

    Multicopy forwarding schemes have been employed in delay tolerant network (DTN) to improve the delivery delay and delivery rate. Much effort has been focused on reducing the routing cost while retaining high performance. This paper aims to provide an optimal joint expected delay forwarding (OJEDF) protocol which minimizes the expected delay while satisfying a certain constant on the number of forwardings per message. We propose a comprehensive forwarding metric called joint expected delay (JE...

  2. Nanofluidic Transistor Circuits

    Science.gov (United States)

    Chang, Hsueh-Chia; Cheng, Li-Jing; Yan, Yu; Slouka, Zdenek; Senapati, Satyajyoti

    2012-02-01

    Non-equilibrium ion/fluid transport physics across on-chip membranes/nanopores is used to construct rectifying, hysteretic, oscillatory, excitatory and inhibitory nanofluidic elements. Analogs to linear resistors, capacitors, inductors and constant-phase elements were reported earlier (Chang and Yossifon, BMF 2009). Nonlinear rectifier is designed by introducing intra-membrane conductivity gradient and by asymmetric external depletion with a reverse rectification (Yossifon and Chang, PRL, PRE, Europhys Lett 2009-2011). Gating phenomenon is introduced by functionalizing polyelectrolytes whose conformation is field/pH sensitive (Wang, Chang and Zhu, Macromolecules 2010). Surface ion depletion can drive Rubinstein's microvortex instability (Chang, Yossifon and Demekhin, Annual Rev of Fluid Mech, 2012) or Onsager-Wien's water dissociation phenomenon, leading to two distinct overlimiting I-V features. Bipolar membranes exhibit an S-hysteresis due to water dissociation (Cheng and Chang, BMF 2011). Coupling the hysteretic diode with some linear elements result in autonomous ion current oscillations, which undergo classical transitions to chaos. Our integrated nanofluidic circuits are used for molecular sensing, protein separation/concentration, electrospray etc.

  3. Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

    OpenAIRE

    石橋, 孝昭

    2012-01-01

    This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

  4. Variational integrators for electric circuits

    International Nuclear Information System (INIS)

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

    2013-01-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

  5. Proposal for a fast, zero suppressing circuit for the digitization of analog pulses over long memory times

    International Nuclear Information System (INIS)

    Bourgeois, F.

    1984-01-01

    This report describes the design principles of a fast (100 MHz) time and pulse height digitizer that can record up to 15 analog pulses over 10-80 μs memory times. Unlike other triggered circuits prepulse samples are recorded without the help of an analog delay line. The low power requirements of the circuit as well as its fast read-out characteristics make it very attractive for detectors with many digitizing channels. Conventional circuits are described as a reference for the evaluation of this new design. An ECL 10 K implementation of the circuit is presented in the third section. (orig.)

  6. Test and Diagnosis for Small-Delay Defects

    CERN Document Server

    Tehranipoor, Mohammad; Chakrabarty, Krishnendu

    2012-01-01

    This book introduces new techniques for detecting and diagnosing small-delay defects (SDD) in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise. This book presents new techniques and methodologies to improve overall SDD detection with very small pattern sets. These methods can result in pattern counts as low as a traditional 1-detect pattern set and long path sensitization and SDD detection similar to or even better than n-detect or timing-aware pattern sets. The important design parameters and pattern-induced noises such as process variations,power supply noise (PSN) and crosstalk are taken into account in the methodologies presented. A diagnostic flow is also presented to identify whether the failure is ...

  7. Integrated circuits, and design and manufacture thereof

    Science.gov (United States)

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  8. Radiation-sensitive switching circuits

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J.H.; Cockshott, C.P.

    1976-03-16

    A radiation-sensitive switching circuit includes a light emitting diode which from time to time illuminates a photo-transistor, the photo-transistor serving when its output reaches a predetermined value to operate a trigger circuit. In order to allow for aging of the components, the current flow through the diode is increased when the output from the transistor falls below a known level. Conveniently, this is achieved by having a transistor in parallel with the diode, and turning the transistor off when the output from the phototransistor becomes too low. The circuit is designed to control the ignition system in an automobile engine.

  9. The Maplin electronic circuits handbook

    CERN Document Server

    Tooley, Michael

    1990-01-01

    The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

  10. Secure integrated circuits and systems

    CERN Document Server

    Verbauwhede, Ingrid MR

    2010-01-01

    On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

  11. INTEGRATED SENSOR EVALUATION CIRCUIT AND METHOD FOR OPERATING SAID CIRCUIT

    OpenAIRE

    Krüger, Jens; Gausa, Dominik

    2015-01-01

    WO15090426A1 Sensor evaluation device and method for operating said device Integrated sensor evaluation circuit for evaluating a sensor signal (14) received from a sensor (12), having a first connection (28a) for connection to the sensor and a second connection (28b) for connection to the sensor. The integrated sensor evaluation circuit comprises a configuration data memory (16) for storing configuration data which describe signal properties of a plurality of sensor control signals (26a-c). T...

  12. A note on exponential convergence of neural networks with unbounded distributed delays

    Energy Technology Data Exchange (ETDEWEB)

    Chu Tianguang [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)]. E-mail: chutg@pku.edu.cn; Yang Haifeng [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)

    2007-12-15

    This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network.

  13. A note on exponential convergence of neural networks with unbounded distributed delays

    International Nuclear Information System (INIS)

    Chu Tianguang; Yang Haifeng

    2007-01-01

    This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network

  14. Optical programmable metamaterials

    Science.gov (United States)

    Gong, Cheng; Zhang, Nan; Dai, Zijie; Liu, Weiwei

    2018-02-01

    We suggest and demonstrate the concept of optical programmable metamaterials which can configure the device's electromagnetic parameters by the programmable optical stimuli. In such metamaterials, the optical stimuli produced by a FPGA controlled light emitting diode array can switch or combine the resonance modes which are coupled in. As an example, an optical programmable metamaterial terahertz absorber is proposed. Each cell of the absorber integrates four meta-rings (asymmetric 1/4 rings) with photo-resistors connecting the critical gaps. The principle and design of the metamaterials are illustrated and the simulation results demonstrate the functionalities for programming the metamaterial absorber to change its bandwidth and resonance frequency.

  15. NNP Life Management Programmes

    International Nuclear Information System (INIS)

    Hervia Ruperez, F.

    1996-01-01

    Around the world, power station owners are increasingly concerned to optimise Plant Life Management. In response, they are setting up Life Management programmes, of more or less ambitious scope and depth. Strategic, economic and security concerns and the close link between life extension work and the improved maintenance practices that are so important today, will increase and global these programmes for monitoring and conservation or mitigation of ageing. These programmes are all based on knowledge of the precise condition of all components and population with the greatest effect on the economics and safety of the plant, and trends in changes in their condition. (Author)

  16. The European Fusion Programme

    International Nuclear Information System (INIS)

    Palumbo, D.

    1983-01-01

    The European Fusion Programme is coordinated by Euratom and represents a long term cooperative project of Member States of the European Communities in the field of fusion, designed to lead to the joint construction of prototypes. The main lines of the programme proposed for 1982 to 1986 are: (1) the continuation of a strong effort on tokamaks with emphasis on JET construction, operation and upgrading, (2) conceptual design of NET and development of the related technology, and (3) further work on two alternative magnetic confinement systems. The current status and future plans for this programme are discussed in the paper. (author)

  17. Assessing delay discounting in mice

    OpenAIRE

    Mitchell, Suzanne H.

    2014-01-01

    Delay discounting (also intertemporal choice or impulsive choice) is the process by which delayed outcomes, such as delayed food delivery, are valued less than the same outcomes delivered immediately or with a shorter delay. This process is of interest because many psychopathologies, including substance dependence, pathological gambling, attention deficit hyperactivity disorder and conduct disorder, are characterized by heightened levels of delay discounting. Some of these disorders are herit...

  18. Quantum circuit behaviour

    International Nuclear Information System (INIS)

    Poulton, D.

    1989-09-01

    Single electron tunnelling in multiply connected weak link systems is considered. Using a second quantised approach the tunnel current, in both normal and superconducting systems, using perturbation theory, is derived. The tunnel currents are determined as a function of an Aharanov-Bohm phase (acquired by the electrons). Using these results, the multiply connected system is then discussed when coupled to a resonant LC circuit. The resulting dynamics of this composite system are then determined. In the superconducting case the results are compared and contrasted with flux mode behaviour seen in large superconducting weak link rings. Systems in which the predicted dynamics may be seen are also discussed. In analogy to the electron tunnelling analysis, the tunnelling of magnetic flux quanta through the weak link is also considered. Here, the voltage across the weak link, due to flux tunnelling, is determined as a function of an externally applied current. This is done for both singly and multiply connected flux systems. The results are compared and contrasted with charge mode behaviour seen in superconducting weak link systems. Finally, the behaviour of simple quantum fluids is considered when subject to an external rotation. Using a microscopic analysis it is found that the microscopic quantum behaviour of the particles is manifest on a macroscopic level. Results are derived for bosonic, fermionic and BCS pair-type systems. The connection between flux quantisation in electromagnetic systems is also made. Using these results, the dynamics of such a quantum fluid is considered when coupled to a rotating torsional oscillator. The results are compared with those found in SQUID devices. A model is also presented which discusses the possible excited state dynamics of such a fluid. (author)

  19. Permissible Delay in Payments

    Directory of Open Access Journals (Sweden)

    Yung-Fu Huang

    2007-01-01

    Full Text Available The main purpose of this paper wants to investigate the optimal retailer's lot-sizing policy with two warehouses under partially permissible delay in payments within the economic order quantity (EOQ framework. In this paper, we want to extend that fully permissible delay in payments to the supplier would offer the retailer partially permissible delay in payments. That is, the retailer must make a partial payment to the supplier when the order is received. Then the retailer must pay off the remaining balance at the end of the permissible delay period. In addition, we want to add the assumption that the retailer's storage space is limited. That is, the retailer will rent the warehouse to store these exceeding items when the order quantity is larger than retailer's storage space. Under these conditions, we model the retailer's inventory system as a cost minimization problem to determine the retailer's optimal cycle time and optimal order quantity. Three theorems are developed to efficiently determine the optimal replenishment policy for the retailer. Finally, numerical examples are given to illustrate these theorems and obtained a lot of managerial insights.

  20. Delayed neutrons in ANSTO

    International Nuclear Information System (INIS)

    Wall, T.

    1988-01-01

    Delayed neutron analysis carried out at the Australian Nuclear Scientific and Technology Organization facilities, provides a fast, high sensitivity, low cost, reliable method, particularly suitable for large batches of samples, and for non destructive analysis of a range of materials. While its main use has been in uranium exploration, other applications include archeological investigations, agriculture, oceanography and biology

  1. Programmable spark counter of tracks

    International Nuclear Information System (INIS)

    Denisov, A.E.; Nikolaev, V.A.; Vorobjev, I.B.

    2005-01-01

    For the purpose, a new set-the programmable all-automatic spark counter AIST-4-has been developed and manufactured. Compared to our previous automated spark counter ISTRA, which was operated by the integrated fixed program, the new set is operated completely by a personal computer. The mechanism for pressing and pulling the aluminized foil is put into action by a step motor operated by a microcontroller. The step motor turns an axle. The axle has two eccentrics. One of them moves a pressing plate up and down. The second eccentric moves the aluminized foil by steps of ∼15mm after the end of each pulse counting. One turnover of the axle corresponds to one pulse count cycle. The step motor, the high-voltage block and the pulse count block are operated by the microcontroller PIC 16C84 (Microstar). The set can be operated either manually by keys on the front panel or by a PC using dialogue windows for radon or neutron measurements (for counting of alpha or fission fragment tracks). A number of algorithms are developed: the general procedures, the automatic stopping of the pulse counting, the calibration curve, determination of the count characteristics and elimination of the short circuit in a track

  2. Multi-purpose logical device with integrated circuit for the automation of mine water disposal

    Energy Technology Data Exchange (ETDEWEB)

    Pop, E.; Pasculescu, M.

    1980-06-01

    After an analysis of the waste water disposal as an object of automation, the author presents a BASIC-language programme established to simulate the automated control system on a digital computer. Then a multi-purpose logical device with integrated circuits for the automation of the mine water disposal is presented. (In Romanian)

  3. Emergency reactor cooling circuit

    International Nuclear Information System (INIS)

    Araki, Hidefumi; Matsumoto, Tomoyuki; Kataoka, Yoshiyuki.

    1994-01-01

    Cooling water in a gravitationally dropping water reservoir is injected into a reactor pressure vessel passing through a pipeline upon occurrence of emergency. The pipeline is inclined downwardly having one end thereof being in communication with the pressure vessel. During normal operation, the cooling water in the upper portion of the inclined pipeline is heated by convection heat transfer from the communication portion with the pressure vessel. On the other hand, cooling water present at a position lower than the communication portion forms cooling water lumps. Accordingly, temperature stratification layers are formed in the inclined pipeline. Therefore, temperature rise of water in a vertical pipeline connected to the inclined pipeline is small. With such a constitution, the amount of heat lost from the pressure vessel by way of the water injection pipeline is reduced. Further, there is no worry that cooling water to be injected upon occurrence of emergency is boiled under reduced pressure in the injection pipeline to delay the depressurization of the pressure vessel. (I.N.)

  4. Transistor and integrated circuit manufacture

    International Nuclear Information System (INIS)

    Colman, D.

    1978-01-01

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

  5. Time domain analog circuit simulation

    NARCIS (Netherlands)

    Fijnvandraat, J.G.; Houben, S.H.M.J.; Maten, ter E.J.W.; Peters, J.M.F.

    2006-01-01

    Recent developments of new methods for simulating electric circuits are described. Emphasis is put on methods that fit existing datastructures for backward differentiation formulae methods. These methods can be modified to apply to hierarchically organized datastructures, which allows for efficient

  6. Circuit design on plastic foils

    CERN Document Server

    Raiteri, Daniele; Roermund, Arthur H M

    2015-01-01

    This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics.  The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.   • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels.

  7. Discharge quenching circuit for counters

    International Nuclear Information System (INIS)

    Karasik, A.S.

    1982-01-01

    A circuit for quenching discharges in gas-discharge detectors with working voltage of 3-5 kV based on transistors operating in the avalanche mode is described. The quenching circuit consists of a coordinating emitter follower, amplifier-shaper for avalanche key cascade control which changes potential on the counter electrodes and a shaper of discharge quenching duration. The emitter follower is assembled according to a widely used flowsheet with two transistors. The circuit permits to obtain a rectangular quenching pulse with front of 100 ns and an amplitude of up to 3.2 kV at duration of 500 μm-8 ms. Application of the quenching circuit described permits to obtain countering characteristics with the slope less than or equal to 0.02%/V and plateau extent greater than or equal to 300 V [ru

  8. Transistor and integrated circuit manufacture

    Energy Technology Data Exchange (ETDEWEB)

    Colman, D

    1978-09-27

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

  9. Ignition circuit for combustion engines

    Energy Technology Data Exchange (ETDEWEB)

    Becker, H W

    1977-05-26

    The invention refers to the ignition circuit for combustion engines, which are battery fed. The circuit contains a transistor and an oscillator to produce an output voltage on the secondary winding of an output transformer to supply an ignition current. The plant is controlled by an interrupter. The purpose of the invention is to form such a circuit that improved sparks for ignition are produced, on the one hand, and that on the other hand, the plant can continue to function after loss of the oscillator. The problem is solved by the battery and the secondary winding of the output transformers of the oscillator are connected via a rectifier circuit to produce a resultant total voltage with the ignition coil from the battery voltage and the rectified pulsating oscillator output.

  10. Fellows, Associates & Students Programmes

    CERN Document Server

    2005-01-01

    The present document reviews the CERN Fellows, Associates and Students Programmes emphasizing the developments since 2000, when the previous review was presented to the Scientific Policy Committee, Finance Committee and Council (CERN/2325), and makes proposals for the coming five years. In summary, it is proposed to â?¢ Simplify the payment scheme for the Paid Scientific Associates Programme, which will no longer depend on candidateâ??s home support and age; â?¢ Broaden the scope of the Fellowship Programme, in order to facilitate the recruitment of young graduates in computing and engineering. Age-related eligibility conditions and payment levels will be replaced with experience-based criteria; â?¢ Modify subsistence rates for the Doctoral and Technical Student Programme in order to harmonize CERNâ??s payment levels with those offered by other research establishments. This document is presented for discussion and recommendation by the Scientific Policy Committee and approval by the Council. Additiona...

  11. (ARV) treatment training programme

    African Journals Online (AJOL)

    Winnie

    Keywords:ARV, training, evaluation, HIV, health care provider. RÉSUMÉ .... workers, adequate laboratory facilities for measuring viral load and .... questionnaire guide, the head of unit of the ART ...... begins its scale-up programme. Some of ...

  12. The French nuclear programme

    International Nuclear Information System (INIS)

    Bacher, Pierre

    1987-01-01

    France has a civil nuclear power generation programme second only to the USA with 49 nuclear units in operation and 13 under construction. The units in service are described. These include 33 PWR 900 MW and 9 PWR 1300 MW units. The electricity consumption and generation in France is illustrated. The absence of a powerful anti-nuclear lobby and two main technical options have contributed to the success of the French nuclear programme. These are the PWR design and the plant standardization policy which allows the setting up of an effective industrial complex (eg for analysis of operating conditions and of safety and reliability information). The programme and the reasons for its success are reviewed. Research programmes and future plans are also discussed. (UK)

  13. Elukestva õppe programm : Erasmus+

    Index Scriptorium Estoniae

    2014-01-01

    Erasmus+ programm liidab senised koostööprogrammid „Euroopa elukestva õppe programm“, „Euroopa Noored“ ning Euroopa komisjoni rahvusvahelised kõrgharidusprogrammid. Elukestva õppe programmi 2013 kokkuvõte

  14. Greek Teachers Programme 2015

    CERN Multimedia

    Hoch, Michael

    2015-01-01

    The 3rd edition of this year's Greek Teachers Programme was co-organized by CERN Education Group and the Hellenic Physical Society and took place from 8 to 12 November 2015. The programme targets physics high-school teachers from all over Greece. It aims to help teachers inspire the next generation of scientists and engineers by motivating their students to understand and appreciate how science works at the world's largest physics laboratory, whereby increasing their interest in pursuing studies in STEM fields in secondary and post-secondary education. 33 teachers took part in this programme which comprised lectures by Greek members of the CERN scientific community, with visits to experimental facilities, hands-on activities and dedicated sessions on effective and creative ways through which participants may bring physics, particle physics and CERN closer to their school classroom. In 2015, more than 100 teachers took part in the three editions of the Greek Teachers Programme.

  15. The French energy programme

    International Nuclear Information System (INIS)

    Bohnen, U.

    1980-01-01

    The challenge of the oil crisis made French energy policy react chiefly by means of a programme for the rapid expansion of nuclear energy which has become unparalleled because of its systematic realization. The following article gives a survey of this programme and its political preconditions. The French energy programme deserves special attention as the utilization of nuclear energy in France including all related activities has reached a more advanced stage than in most other countries. The effects and requirements connected with such an extensive programme which can therefore be investigated with the help of the French example migth be of importance also for other countries in a similar way. (orig./UA) [de

  16. Reverse engineering of integrated circuits

    Science.gov (United States)

    Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  17. The Gold Standard Programme

    DEFF Research Database (Denmark)

    Neumann, Tim; Rasmussen, Mette; Ghith, Nermin

    2013-01-01

    To evaluate the real-life effect of an evidence-based Gold Standard Programme (GSP) for smoking cessation interventions in disadvantaged patients and to identify modifiable factors that consistently produce the highest abstinence rates.......To evaluate the real-life effect of an evidence-based Gold Standard Programme (GSP) for smoking cessation interventions in disadvantaged patients and to identify modifiable factors that consistently produce the highest abstinence rates....

  18. Motivation programmes of organizations

    OpenAIRE

    Pízová, Tereza

    2008-01-01

    The Bachelor Thesis "'Motivation Programmes of Organizations" focuses on an extremely important area within personnel management. Employee motivation is crucial to the effective operation of businesses. Motivation programmes assist in increasing and maintaining employee motivation and demonstrate an organization's interest in its employees. This piece is on one hand concerned with theoretical foundations of motivation, describing theories and concepts important to the area of human behaviour ...

  19. The Prince Henry Hospital dementia caregivers' training programme.

    Science.gov (United States)

    Brodaty, H; Gresham, M; Luscombe, G

    1997-02-01

    To describe the theory, elements and practice of a successful caregiver training programme; and report the 8-year outcome. Prospective, randomized control trial and longitudinal follow-up over approximately 8 years. Psychiatry unit, general teaching hospital, Sydney, Australia. 96 persons less than 80 years old with mild to moderate dementia and their cohabiting caregivers. All patients received a 10-day structured memory retraining and activity programme. Caregivers in the immediate and wait-list caregiver training groups received a structured, residential, intensive 10-day training programme, boosted by follow-ups and telephone conferences over 12 months. Those in the wait-list group entered the programme after waiting 6 months. The third group of caregivers received 10 days' respite (while patients underwent their memory retraining programme) and 12 months booster sessions as for the other groups. Nursing home admission; time until patient death. 64% of patients whose caregivers were in the immediate training group, 53% of wait-list group patients and 70% of memory retraining patients had died. Nursing home admission had occurred in 79% of the immediate training, 83% of the delayed and 90% of the memory retraining group. Eight-year survival analysis indicated that patients whose caregivers received training stayed at home significantly longer (p = 0.037) and tended to live longer (p = 0.08). Caregiver training programmes demonstrably can delay institutionalization of people with dementia.

  20. Carbon Nanotubes-Based Digitally Programmable Current Follower

    Directory of Open Access Journals (Sweden)

    S. K. Tripathi

    2018-01-01

    Full Text Available The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET’s parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.

  1. Design of acoustic logging signal source of imitation based on field programmable gate array

    International Nuclear Information System (INIS)

    Zhang, K; Ju, X D; Lu, J Q; Men, B Y

    2014-01-01

    An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes. (paper)

  2. Design of acoustic logging signal source of imitation based on field programmable gate array

    Science.gov (United States)

    Zhang, K.; Ju, X. D.; Lu, J. Q.; Men, B. Y.

    2014-08-01

    An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes.

  3. Receiver Gain Modulation Circuit

    Science.gov (United States)

    Jones, Hollis; Racette, Paul; Walker, David; Gu, Dazhen

    2011-01-01

    A receiver gain modulation circuit (RGMC) was developed that modulates the power gain of the output of a radiometer receiver with a test signal. As the radiometer receiver switches between calibration noise references, the test signal is mixed with the calibrated noise and thus produces an ensemble set of measurements from which ensemble statistical analysis can be used to extract statistical information about the test signal. The RGMC is an enabling technology of the ensemble detector. As a key component for achieving ensemble detection and analysis, the RGMC has broad aeronautical and space applications. The RGMC can be used to test and develop new calibration algorithms, for example, to detect gain anomalies, and/or correct for slow drifts that affect climate-quality measurements over an accelerated time scale. A generalized approach to analyzing radiometer system designs yields a mathematical treatment of noise reference measurements in calibration algorithms. By treating the measurements from the different noise references as ensemble samples of the receiver state, i.e. receiver gain, a quantitative description of the non-stationary properties of the underlying receiver fluctuations can be derived. Excellent agreement has been obtained between model calculations and radiometric measurements. The mathematical formulation is equivalent to modulating the gain of a stable receiver with an externally generated signal and is the basis for ensemble detection and analysis (EDA). The concept of generating ensemble data sets using an ensemble detector is similar to the ensemble data sets generated as part of ensemble empirical mode decomposition (EEMD) with exception of a key distinguishing factor. EEMD adds noise to the signal under study whereas EDA mixes the signal with calibrated noise. It is mixing with calibrated noise that permits the measurement of temporal-functional variability of uncertainty in the underlying process. The RGMC permits the evaluation of EDA by

  4. The British flue gas desulphurisation programme

    Energy Technology Data Exchange (ETDEWEB)

    Longhurst, J.W.S.

    1989-09-01

    Retrofitting UK power plants with flue gas desulfurization equipment should reduce SO{sub 2} emission by around 15%. Three systems appear suitable for UK installations: limestone/gypsum, regenerative Wellman Lord, and spray dry. The CEGB has used limestone/gypsum at Drax A B, West Burton, Fawley and Kingsnorth, and Wellman Lord at Fiddlers Ferry. Despite the environmental benefits, however, there is concern that the negative aspects of the programme (choice of technology, waste disposal, by-product disposal) may delay implementation and thus threaten Britain's aim of 30% reduction by 1999. 3 tabs.

  5. A TDC integrated circuit for drift chamber readout

    International Nuclear Information System (INIS)

    Passaseo, M.; Petrolo, E.; Veneziano, S.

    1995-01-01

    A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 μm CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.)

  6. A TDC integrated circuit for drift chamber readout

    Energy Technology Data Exchange (ETDEWEB)

    Passaseo, M. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Petrolo, E. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Veneziano, S. [Istituto Nazionale di Fisica Nucleare, Rome (Italy)

    1995-12-11

    A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 {mu}m CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.).

  7. Delayed traumatic intracranial hematoma

    International Nuclear Information System (INIS)

    Tomita, Hiroki

    1984-01-01

    CT was performed serially within 24 hours after head injury in 64 patients having Glasgow Coma Scale of 14 or less or cranial fracture shown on roentgenogram. Delayed traumatic extradural hematoma was observed within 7-12 hours after head injury in 6 cases (9.4%). This was prominent in the frontal and occipital regions (67%). Good recovery was seen in 83.3%. Delayed traumatic intracerebral hematoma was observed within 6-24 hours after head injury in 17 cases (26.6%). This higher incidence was related to contre coup injury. Conservative treatment was possible in 14 of the 17 patients (82.4%), showing good recovery in 70%. (Namekawa, K.)

  8. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  9. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    Science.gov (United States)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  10. Spectral Purity Enhancement via Polyphase Multipath Circuits

    NARCIS (Netherlands)

    Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

    2004-01-01

    The central question of this paper is: can we enhance the spectral purity of nonlinear circuits by using polyphase multipath circuits? The basic idea behind polyphase multipath circuits is to split the nonlinear circuits into two or more paths and exploit phase differences between these paths to

  11. Distortion Cancellation via Polyphase Multipath Circuits

    NARCIS (Netherlands)

    Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

    The central question of this paper is: can we enhance the spectral purity of nonlinear circuits with the help of polyphase multipath circuits. Polyphase multipath circuits are circuits with two or more paths that exploit phase differences between the paths to cancel unwanted signals. It turns out

  12. Dynamic theory for the mesoscopic electric circuit

    International Nuclear Information System (INIS)

    Chen Bin; Shen Xiaojuan; Li Youquan; Sun LiLy; Yin Zhujian

    2005-01-01

    The quantum theory for mesoscopic electric circuit with charge discreteness is briefly described. The minibands of quasienergy in LC design mesoscopic electric circuit have been found. In the mesoscopic 'pure' inductance design circuit, just like in the mesoscopic metallic rings, the quantum dynamic characteristics have been obtained explicitly. In the 'pure' capacity design circuit, the Coulomb blockade had also been addressed

  13. Multi-Layer E-Textile Circuits

    Science.gov (United States)

    Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

    2012-01-01

    Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

  14. The design of programme-controlled gain and linear pulse amplifier

    International Nuclear Information System (INIS)

    Guan Xuemei; Chen Chunkai; Northeast Normal Univ., Changchun; Qiao Shuang; Zhou Chuansheng

    2006-01-01

    The authors have designed a kind of new-style programme-controlled gain and linear pulse amplifier with accurate gausses of CR-RC-CR shaping circuit structure. The use of non-volatile digital electric potential device and accurate operational amplifier makes the circuit structure simple greatly, makes the ability stronger that resists assault. It can realize multistage gain in succession and make the drift of temperature low and make the linearity of pulse well. (authors)

  15. Time-Delay Interferometry

    Directory of Open Access Journals (Sweden)

    Massimo Tinto

    2014-08-01

    Full Text Available Equal-arm detectors of gravitational radiation allow phase measurements many orders of magnitude below the intrinsic phase stability of the laser injecting light into their arms. This is because the noise in the laser light is common to both arms, experiencing exactly the same delay, and thus cancels when it is differenced at the photo detector. In this situation, much lower level secondary noises then set the overall performance. If, however, the two arms have different lengths (as will necessarily be the case with space-borne interferometers, the laser noise experiences different delays in the two arms and will hence not directly cancel at the detector. In order to solve this problem, a technique involving heterodyne interferometry with unequal arm lengths and independent phase-difference readouts has been proposed. It relies on properly time-shifting and linearly combining independent Doppler measurements, and for this reason it has been called time-delay interferometry (TDI. This article provides an overview of the theory, mathematical foundations, and experimental aspects associated with the implementation of TDI. Although emphasis on the application of TDI to the Laser Interferometer Space Antenna (LISA mission appears throughout this article, TDI can be incorporated into the design of any future space-based mission aiming to search for gravitational waves via interferometric measurements. We have purposely left out all theoretical aspects that data analysts will need to account for when analyzing the TDI data combinations.

  16. Design and implementation of SFQ programmable clock generators

    International Nuclear Information System (INIS)

    Ito, M.; Nakajima, N.; Fujiwara, K.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

    2004-01-01

    We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the variable number of SFQ pulses according to its internal state. The PCG is composed of an SFQ ring oscillator, a control circuit which counts up the number of SFQ pulses and stops the operation of the ring oscillator, and a decoder which defines the initial state of the control circuit. The PCG can generate the variable number of SFQ pulses ranging from 2 to 2 N , where N is the number of T flip-flops in the control circuit. The oscillation frequency of the PCG is designed to be ranging from 6.2 to 18.8 GHz. In this study, we have implemented a PCG generating SFQ pulses ranging from 2 to 2 4 using a cell-based design methodology and confirmed its correct functionality

  17. The INTEGRAL Core Observing Programme

    DEFF Research Database (Denmark)

    Winkler, C.; Gehrels, N.; Lund, Niels

    1999-01-01

    The Core Programme of the INTEGRAL mission is defined as the portion of the scientific programme covering the guaranteed time observations for the INTEGRAL Science Working Team. This paper describes the current status of the Core Programme preparations and summarizes the key elements...... of the observing programme....

  18. G(sup 4)FET Implementations of Some Logic Circuits

    Science.gov (United States)

    Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

    2009-01-01

    Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

  19. Synthetic multicellular oscillatory systems: controlling protein dynamics with genetic circuits

    International Nuclear Information System (INIS)

    Koseska, Aneta; Volkov, Evgenii; Kurths, Juergen

    2011-01-01

    Synthetic biology is a relatively new research discipline that combines standard biology approaches with the constructive nature of engineering. Thus, recent efforts in the field of synthetic biology have given a perspective to consider cells as 'programmable matter'. Here, we address the possibility of using synthetic circuits to control protein dynamics. In particular, we show how intercellular communication and stochasticity can be used to manipulate the dynamical behavior of a population of coupled synthetic units and, in this manner, finely tune the expression of specific proteins of interest, e.g. in large bioreactors.

  20. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience

    International Nuclear Information System (INIS)

    Bugnet, H.

    1995-01-01

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs

  1. Investigation of SFQ integrated circuits using Nb fabrication technology

    International Nuclear Information System (INIS)

    Numata, H.; Tanaka, M.; Kitagawa, Y.; Tahara, S.

    1999-01-01

    In NEC's standard process, the minimum junction size is 2 μm and the critical current density (J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation (σ) of the critical current (I C ) was 0.9% for the 2 μm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits. (author)

  2. Programmable full-adder computations in communicating three-dimensional cell cultures.

    Science.gov (United States)

    Ausländer, David; Ausländer, Simon; Pierrat, Xavier; Hellmann, Leon; Rachid, Leila; Fussenegger, Martin

    2018-01-01

    Synthetic biologists have advanced the design of trigger-inducible gene switches and their assembly into input-programmable circuits that enable engineered human cells to perform arithmetic calculations reminiscent of electronic circuits. By designing a versatile plug-and-play molecular-computation platform, we have engineered nine different cell populations with genetic programs, each of which encodes a defined computational instruction. When assembled into 3D cultures, these engineered cell consortia execute programmable multicellular full-adder logics in response to three trigger compounds.

  3. Instrumentation and test gear circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Instrumentation and Test Gear Circuits Manual provides diagrams, graphs, tables, and discussions of several types of practical circuits. The practical circuits covered in this book include attenuators, bridges, scope trace doublers, timebases, and digital frequency meters. Chapter 1 discusses the basic instrumentation and test gear principles. Chapter 2 deals with the design of passive attenuators, and Chapter 3 with passive and active filter circuits. The subsequent chapters tackle 'bridge' circuits, analogue and digital metering techniques and circuitry, signal and waveform generation, and p

  4. Logic circuits from zero forcing.

    Science.gov (United States)

    Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

    We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

  5. Implementation of programmable logic controller for proposed new instrumentation and control system of RTP

    International Nuclear Information System (INIS)

    Mohd Khairulezwan Abdul Manan; Mohd Idris Taib; Mohd Dzul Aiman Aslan

    2010-01-01

    Reactor Monitoring System is one of very important part of Reactor Instrumentation and Control system. Current monitoring system is using analog system whereby all circuits are discrete circuit and all displays and indicators are not digitalized. The proposed new system will use using a Commercial Off-The-Shelf, state of the art, Supervisory Control and Data Acquisition system such as Programmable Logic Controller as well as Computer System. The implementations of Programmable Logic Controller are used for Data Acquisition System and as a sub-system for Computer System where all the activities involved are stored for operation record and report as well as use for research purposes. Programmable Logic Controller receives galvanised or optically isolated signal from Reactor Protection System. Programmable Logic Controller also receives signal from other parameters as a digital and analog input related to reactor system. (author)

  6. 30 CFR 75.601-1 - Short circuit protection; ratings and settings of circuit breakers.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit protection; ratings and settings... Trailing Cables § 75.601-1 Short circuit protection; ratings and settings of circuit breakers. Circuit breakers providing short circuit protection for trailing cables shall be set so as not to exceed the...

  7. 30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

    Science.gov (United States)

    2010-07-01

    ... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

  8. 30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

    Science.gov (United States)

    2010-07-01

    ... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

  9. Delayed Dopamine Signaling of Energy Level Builds Appetitive Long-Term Memory in Drosophila

    OpenAIRE

    Pierre-Yves Musso; Paul Tchenio; Thomas Preat

    2015-01-01

    Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level t...

  10. STICAP: A linear circuit analysis program with stiff systems capability. Volume 1: Theory manual. [network analysis

    Science.gov (United States)

    Cooke, C. H.

    1975-01-01

    STICAP (Stiff Circuit Analysis Program) is a FORTRAN 4 computer program written for the CDC-6400-6600 computer series and SCOPE 3.0 operating system. It provides the circuit analyst a tool for automatically computing the transient responses and frequency responses of large linear time invariant networks, both stiff and nonstiff (algorithms and numerical integration techniques are described). The circuit description and user's program input language is engineer-oriented, making simple the task of using the program. Engineering theories underlying STICAP are examined. A user's manual is included which explains user interaction with the program and gives results of typical circuit design applications. Also, the program structure from a systems programmer's viewpoint is depicted and flow charts and other software documentation are given.

  11. The French nuclear programme

    International Nuclear Information System (INIS)

    Feger, M.

    1990-01-01

    EDF has long been interested in the use of nuclear energy for thermal power generation. After a period of apprenticeship and experiments, EDF launched a major PWR plant programme so as to reduce France's energy dependence and master generation costs. This programme, based on standardization, has achieved the desired results. It must now be adapted to suit the needs of the 21st century. For this programme, all those involved (Governmental authorities, EDF, manufacturers) were mobilized to an unprecedented extent and rigorous working methods were imposed. Experience feedback has been used to make improvements both to the installations themselves and to procedures. Results have proved satisfactory as regards nuclear safety but vigilance must be maintained. Public opinion on nuclear power is reserved we are sentenced to achieving a 'fault-free' track record, all the while mastering costs, so as to ensure the continuing use of nuclear energy. (author)

  12. The French nuclear programme

    Energy Technology Data Exchange (ETDEWEB)

    Feger, M [Ecole Nationale Superieure d' Electrotechnique de Grenoble, Institute National des Sciences et Techniques Nucleaires (Saclay), Gif-sur-Yvette, Electricite de France (France)

    1990-06-01

    EDF has long been interested in the use of nuclear energy for thermal power generation. After a period of apprenticeship and experiments, EDF launched a major PWR plant programme so as to reduce France's energy dependence and master generation costs. This programme, based on standardization, has achieved the desired results. It must now be adapted to suit the needs of the 21st century. For this programme, all those involved (Governmental authorities, EDF, manufacturers) were mobilized to an unprecedented extent and rigorous working methods were imposed. Experience feedback has been used to make improvements both to the installations themselves and to procedures. Results have proved satisfactory as regards nuclear safety but vigilance must be maintained. Public opinion on nuclear power is reserved we are sentenced to achieving a 'fault-free' track record, all the while mastering costs, so as to ensure the continuing use of nuclear energy. (author)

  13. External Mobility Programme

    CERN Multimedia

    HR Department

    2007-01-01

    Every year, a significant number of highly-skilled staff members leave the Organization and offer their talents on the European job market. CERN is launching a programme aiming to help staff members to whom the Organization cannot offer an indefinite contract in the transition towards their next employment. The programme, which is based on the establishment of a number of partnerships with potential employers in the private sector, will run on a voluntary basis. Staff members who have received confirmation that they will not be offered an indefinite contract and who are interested in availing themselves of the opportunities offered by the programme, are invited to enrol by following the procedure described at: https://ert.cern.ch/browse_intranet/wd_pds?p_web_page_id=5841 Applications will be processed in the strictest confidence by the Human Resources Department and eligible profiles will then be made available to partner companies for recruitment purposes. Any subsequent ...

  14. Approaching the Processes in the Generator Circuit Breaker at Disconnection through Sustainability Concepts

    Directory of Open Access Journals (Sweden)

    Carmen A. Bulucea

    2013-03-01

    Full Text Available Nowadays, the electric connection circuits of power plants (based on fossil fuels as well as renewable sources entail generator circuit-breakers (GCBs at the generator terminals, since the presence of that electric equipment offers many advantages related to the sustainability of a power plant. In an alternating current (a.c. circuit the interruption of a short circuit is performed by the circuit-breaker at the natural passing through zero of the short-circuit current. During the current interruption, an electric arc is generated between the opened contacts of the circuit-breaker. This arc must be cooled and extinguished in a controlled way. Since the synchronous generator stator can flow via highly asymmetrical short-circuit currents, the phenomena which occur in the case of short-circuit currents interruption determine the main stresses of the generator circuit-breaker; the current interruption requirements of a GCB are significantly higher than for the distribution network circuit breakers. For shedding light on the proper moment when the generator circuit-breaker must operate, using the space phasor of the short-circuit currents, the time expression to the first zero passing of the short-circuit current is determined. Here, the manner is investigated in which various factors influence the delay of the zero passing of the short-circuit current. It is shown that the delay time is influenced by the synchronous machine parameters and by the load conditions which precede the short-circuit. Numerical simulations were conducted of the asymmetrical currents in the case of the sudden three-phase short circuit at the terminals of synchronous generators. Further in this study it is emphasized that although the phenomena produced in the electric arc at the terminals of the circuit-breaker are complicated and not completely explained, the concept of exergy is useful in understanding the physical phenomena. The article points out that just after the short-circuit

  15. Multiplication circuit for particle identification

    International Nuclear Information System (INIS)

    Gerlier, Jean

    1962-01-01

    After having commented some characteristics of the particles present in a cyclotron, and their interactions, this report addresses the development and the implementation of a method and a device for selecting and counting particles. The author presents the principle and existing techniques of selection. In comparison with an existing device, the proportional counter and the scintillator are replaced by junctions: a surface barrier type junction (a silicon N layer with a very thin oxygen layer playing the role of the P layer), and lithium-based junction (a silicon P type layer made intrinsic by migration of lithium). The author then describes the developed circuit and assembly (background of the choice of a multiplication circuit), and their operation. In the next part, he presents the performed tests and discuses the obtained results. He finally outlines the benefits of the herein presented circuit [fr

  16. Wiring of electronic evaluation circuits

    International Nuclear Information System (INIS)

    Bauer, R.; Svoboda, Z.

    1977-01-01

    The wiring is described of electronic evaluation circuits for the automatic viewing of photographic paper strip negatives on which line tracks with an angular scatter relative to the spectrograph longitudinal axis were recorded during the oblique flight of nuclear particles during exposure in the spectrograph. In coincidence evaluation, the size of the angular scatter eventually requires that evaluation dead time be increased. The equipment consists of minimally two fixed registers and a block of logic circuits whose output is designed such as will allow connection to equipment for recording signals corresponding to the number of tracks on the film. The connection may be implemented using integrated circuits guaranteeing high operating reliability and life. (J.B.)

  17. Counterpulse railgun energy recovery circuit

    International Nuclear Information System (INIS)

    Honig, E.M.

    1986-01-01

    This patent describes a counterpulse railgun energy recovery circuit for propelling a projectile along a railgun the counterpulse railgun energy recovery circuit consists of: a railgun having an effective inductance; a source inductor initially charged to an initial current; current means for initially charging the source inductor to the initial current; first current-zero type switching means; second current-zero type switching; third current-zero type switching; muzzle current-zero type switching means; transfer capacitor, the transfer capacitor is for cooperating with the first, second, third, and muzzle current-zero type switching means for providing a resonant circuit for transferring current from the source inductor to the effective inductance of the railgun during the propelling of a projectile along the railgun and for returning current from the effective inductance of the railgun to the source inductance after the projectile has exited the railgun

  18. Vertically Integrated Circuits at Fermilab

    International Nuclear Information System (INIS)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  19. Delayed child-bearing.

    Science.gov (United States)

    Johnson, Jo-Ann; Tough, Suzanne

    2012-01-01

    To provide an overview of delayed child-bearing and to describe the implications for women and health care providers. Delayed child-bearing, which has increased greatly in recent decades, is associated with an increased risk of infertility, pregnancy complications, and adverse pregnancy outcome. This guideline provides information that will optimize the counselling and care of Canadian women with respect to their reproductive choices. Maternal age is the most important determinant of fertility, and obstetric and perinatal risks increase with maternal age. Many women are unaware of the success rates or limitations of assisted reproductive technology and of the increased medical risks of delayed child-bearing, including multiple births, preterm delivery, stillbirth, and Caesarean section. This guideline provides a framework to address these issues. Studies published between 2000 and August 2010 were retrieved through searches of PubMed and the Cochrane Library using appropriate key words (delayed child-bearing, deferred pregnancy, maternal age, assisted reproductive technology, infertility, and multiple births) and MeSH terms (maternal age, reproductive behaviour, fertility). The Internet was also searched using similar key words, and national and international medical specialty societies were searched for clinical practice guidelines and position statements. Data were extracted based on the aims, sample, authors, year, and results. The quality of evidence was rated using the criteria described in the Report of the Canadian Task Force on Preventive Health Care (Table 1). The Society of Obstetricians and Gynaecologists of Canada. RECOMMENDATIONS 1. Women who delay child-bearing are at increased risk of infertility. Prospective parents, especially women, should know that their fecundity and fertility begin to decline significantly after 32 years of age. Prospective parents should know that assisted reproductive technologies cannot guarantee a live birth or completely

  20. Cycles of self-pulsations in a photonic integrated circuit.

    Science.gov (United States)

    Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

    2015-12-01

    We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

  1. Spiking neuron devices consisting of single-flux-quantum circuits

    International Nuclear Information System (INIS)

    Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito

    2006-01-01

    Single-flux-quantum (SFQ) circuits can be used for making spiking neuron devices, which are useful elements for constructing intelligent, brain-like computers. The device we propose is based on the leaky integrate-and-fire neuron (IFN) model and uses a SFQ pulse as an action signal or a spike of neurons. The operation of the neuron device is confirmed by computer simulator. It can operate with a short delay of 100 ps or less and is the highest-speed neuron device ever reported

  2. Monitoring Sodium Circuits and ACSR cables using Fiber Optic Sensors

    International Nuclear Information System (INIS)

    Kasinathan, M.; Sosamma, S.; Babu-Rao, C.; Kumar, Anish; Purna-Chandra-Rao, B.; Murali, N; Jayakumar, T.

    2013-06-01

    Raman Distributed Temperature Sensors (RDTS) are attractive for the monitoring of coolant loop systems in nuclear power plants and monitoring of overhead power transmission lines. This paper discusses deployment of RDTS on double walled pipelines of primary sodium circuits in Fast Breeder Reactors (FBR). It is demonstrated as a proof-of-concept on a test loop with water as the leaking medium. Path delay multiplexing is adopted to improve the spatial resolution from 1.02 m to 0.5 m. A second application focuses on the influence of environmental factors on the detectability of defects in the ACSR cables using RDTS. (authors)

  3. Probabilistic programmable quantum processors

    International Nuclear Information System (INIS)

    Buzek, V.; Ziman, M.; Hillery, M.

    2004-01-01

    We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

  4. A programme in transition

    International Nuclear Information System (INIS)

    Dean, S.O.

    1992-01-01

    Fusion is beginning its transition from a scientific research programme to that of an engineering development programme aimed at practical applications. This transition is likely to last a decade or more because many scientific questions remain and because of the magnitude and cost of the engineering issues. This article reviews briefly the encouraging results produced at the Joint European Torus (JET) where 1.7 MW of fusion power was generated for 2 seconds in experiments in November 1991, the remaining scientific issues, the role of near-term experimental reactors like the International Thermonuclear Experimental reactor (ITER) and other approaches to a demonstration power plant. (author)

  5. Computer mathematics for programmers

    CERN Document Server

    Abney, Darrell H; Sibrel, Donald W

    1985-01-01

    Computer Mathematics for Programmers presents the Mathematics that is essential to the computer programmer.The book is comprised of 10 chapters. The first chapter introduces several computer number systems. Chapter 2 shows how to perform arithmetic operations using the number systems introduced in Chapter 1. The third chapter covers the way numbers are stored in computers, how the computer performs arithmetic on real numbers and integers, and how round-off errors are generated in computer programs. Chapter 4 details the use of algorithms and flowcharting as problem-solving tools for computer p

  6. Delaying information search

    Directory of Open Access Journals (Sweden)

    Yaniv Shani

    2012-11-01

    Full Text Available In three studies, we examined factors that may temporarily attenuate information search. People are generally curious and dislike uncertainty, which typically encourages them to look for relevant information. Despite these strong forces that promote information search, people sometimes deliberately delay obtaining valuable information. We find they may do so when they are concerned that the information might interfere with future pleasurable activities. Interestingly, the decision to search or to postpone searching for information is influenced not only by the value and importance of the information itself but also by well-being maintenance goals related to possible detrimental effects that negative knowledge may have on unrelated future plans.

  7. Fermionic models with superconducting circuits

    Energy Technology Data Exchange (ETDEWEB)

    Las Heras, Urtzi; Garcia-Alvarez, Laura; Mezzacapo, Antonio; Lamata, Lucas [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); Solano, Enrique [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); IKERBASQUE, Basque Foundation for Science, Bilbao (Spain)

    2015-12-01

    We propose a method for the efficient quantum simulation of fermionic systems with superconducting circuits. It consists in the suitable use of Jordan-Wigner mapping, Trotter decomposition, and multiqubit gates, be with the use of a quantum bus or direct capacitive couplings. We apply our method to the paradigmatic cases of 1D and 2D Fermi-Hubbard models, involving couplings with nearest and next-nearest neighbours. Furthermore, we propose an optimal architecture for this model and discuss the benchmarking of the simulations in realistic circuit quantum electrodynamics setups. (orig.)

  8. Circuit modeling for electromagnetic compatibility

    CERN Document Server

    Darney, Ian B

    2013-01-01

    Very simply, electromagnetic interference (EMI) costs money, reduces profits, and generally wreaks havoc for circuit designers in all industries. This book shows how the analytic tools of circuit theory can be used to simulate the coupling of interference into, and out of, any signal link in the system being reviewed. The technique is simple, systematic and accurate. It enables the design of any equipment to be tailored to meet EMC requirements. Every electronic system consists of a number of functional modules interconnected by signal links and power supply lines. Electromagnetic interference

  9. Relative ultrasound energy measurement circuit

    OpenAIRE

    Gustafsson, E.Martin I.; Johansson, Jonny; Delsing, Jerker

    2005-01-01

    A relative ultrasound energy estimation circuit has been designed in a standard 0.35-μm CMOS process, to be a part of a thumb size internet connected wireless ultrasound measurement system. This circuit measures the relative energy between received ultrasound pulses, and presents an output signal that is linear to the received energy. Post-layout simulations indicate 7 bit linearity for 500 mV input signals, 5 μsec startup and stop times, 2.6 mW power consumption during active state. The acti...

  10. Simplified design of filter circuits

    CERN Document Server

    Lenk, John

    1999-01-01

    Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets

  11. Programming languages for circuit design.

    Science.gov (United States)

    Pedersen, Michael; Yordanov, Boyan

    2015-01-01

    This chapter provides an overview of a programming language for Genetic Engineering of Cells (GEC). A GEC program specifies a genetic circuit at a high level of abstraction through constraints on otherwise unspecified DNA parts. The GEC compiler then selects parts which satisfy the constraints from a given parts database. GEC further provides more conventional programming language constructs for abstraction, e.g., through modularity. The GEC language and compiler is available through a Web tool which also provides functionality, e.g., for simulation of designed circuits.

  12. Endogenous money, circuits and financialization

    OpenAIRE

    Malcolm Sawyer

    2013-01-01

    This paper locates the endogenous money approach in a circuitist framework. It argues for the significance of the credit creation process for the evolution of the economy and the absence of any notion of ‘neutrality of money’. Clearing banks are distinguished from other financial institutions as the providers of initial finance in a circuit whereas other financial institutions operate in a final finance circuit. Financialization is here viewed in terms of the growth of financial assets an...

  13. A review of the HDR research programme

    International Nuclear Information System (INIS)

    Talja, H.; Koski, K.; Rintamaa, R.; Keskinen, R.

    1995-10-01

    In the German HDR (Heissdampfreaktor, hot steam reactor) reactor safety programme, experiments and simulating numerical analyses have been undertaken since 1976 to study the integrity and safety of light water reactors under operational and faulted conditions. The last experiments of the programme were conducted in 1991. The post test analyses have been finished by March 1994 and the last final reports were obtained a few months later. The report aims to inform the utilities and the regulatory body of Finland about the contents of the lokset HDR research programme and to consider the applicability of the results to safety analyses of Finnish nuclear power plants. The report centers around the thermal shock and piping component experiments within the last or third phase of the HDR programme. Investigations into severe reactor accidents, fire safety and non-destructive testing, also conducted during the third phase, are not considered. The report presents a review of the following experiment groups: E21 (crack growth under corrosive conditions, loading due to thermal stratification), E22 (leak rate and leak detection experiments of through-cracked piping), E23 (thermal transient and stratification experiments for a pipe nozzle), E31 (vibration of cracked piping due to blow down and closure of isolation valve), E32 (seismically induced vibrations of cracked piping), E33 (condensation phenomena in horizontal piping during emergency cooling). A comprehensive list of reference reports, received by VTT and containing a VTT more detailed description, is given for each experiment group. The review is focused on the loading conditions and their theoretical modelling. A comparison of theoretical and experimental results is presented for each experiment group. The safety margins are finally assessed with special reference to leak-before-break, a well known principle for assuring the integrity of primary circuit piping of nuclear power plants. (orig.) (71 figs., 5 tabs.)

  14. Impact of Compensatory Intervention in 6- to 18-Month-Old Babies at Risk of Motor Development Delays

    Science.gov (United States)

    Müller, Alessandra Bombarda; Saccani, Raquel; Valentini, Nadia Cristina

    2017-01-01

    Purpose: Research indicates that delayed motor development observed in the first years of life can be prevented through compensatory intervention programmes that provide proper care during this critical period of child development. Method: This study analysed the impact of a 12-week compensatory motor intervention programme on 32 babies with…

  15. A review of the UK fast reactor programme, March 1981

    International Nuclear Information System (INIS)

    Smith, R.D.

    1981-01-01

    A reduction in electricity sales over the last year had led to some fossil-fuelled stations being prematurely retired and has postponed the start of some new stations. Nevertheless the main programme for the building of 1 5 G We of thermal reactors during the next ten years remains unaltered and as summarised in last year's review. A formal request to build the first PWR at Sizewell in Suffolk has been presented by the CEGB to the government. This is expected to lead to a Public Inquiry within the next 12-18 months. The major contracts for building the AGR stations at Torness and Heysham were placed recently. Reduced projections for electricity demand up to the end of the century have also contributed to a delay in the government's response to the recommendation by the industry that the Commercial Demonstration Fast Reactor (CDFR) should be built to ensure that the option for commercial LMFBR should be demonstrated and maintained. A government statement is now expected before the end of 1981. Fast breeder reactors are expected to be required in the UK electrical supply system by about the turn of the century. Series ordering will be preceded by construction and operation of the CDFR, of a design suitable in all basic features for replication in programme reactors. The National Nuclear Corporation (NNC) has continued the development of a CDFR design having the required operational safety and economic characteristics. The basic design concept is now nearing completion following investigation of a number of alternatives. Some of the more important features of this design, namely the core, primary circuit and reactor cooling systems. steam cycle and boilers, and overall plant and station layout are described in this review. As a result of increased understanding of sodium/water reaction behaviour, development of manufacturing and inspection techniques and experience in plugging and repair of tubes containing leaking welds, coupled with the preference for a once through

  16. A review of the UK fast reactor programme, March 1981

    Energy Technology Data Exchange (ETDEWEB)

    Smith, R D [Risley Nuclear Power Development Establishment, Risley, Warrington (United Kingdom)

    1981-05-01

    A reduction in electricity sales over the last year had led to some fossil-fuelled stations being prematurely retired and has postponed the start of some new stations. Nevertheless the main programme for the building of 1 5 G We of thermal reactors during the next ten years remains unaltered and as summarised in last year's review. A formal request to build the first PWR at Sizewell in Suffolk has been presented by the CEGB to the government. This is expected to lead to a Public Inquiry within the next 12-18 months. The major contracts for building the AGR stations at Torness and Heysham were placed recently. Reduced projections for electricity demand up to the end of the century have also contributed to a delay in the government's response to the recommendation by the industry that the Commercial Demonstration Fast Reactor (CDFR) should be built to ensure that the option for commercial LMFBR should be demonstrated and maintained. A government statement is now expected before the end of 1981. Fast breeder reactors are expected to be required in the UK electrical supply system by about the turn of the century. Series ordering will be preceded by construction and operation of the CDFR, of a design suitable in all basic features for replication in programme reactors. The National Nuclear Corporation (NNC) has continued the development of a CDFR design having the required operational safety and economic characteristics. The basic design concept is now nearing completion following investigation of a number of alternatives. Some of the more important features of this design, namely the core, primary circuit and reactor cooling systems. steam cycle and boilers, and overall plant and station layout are described in this review. As a result of increased understanding of sodium/water reaction behaviour, development of manufacturing and inspection techniques and experience in plugging and repair of tubes containing leaking welds, coupled with the preference for a once through

  17. Review of programmable systems associated with Fermilab experiments

    International Nuclear Information System (INIS)

    Nash, T.

    1981-05-01

    The design and application of programmable systems for Fermilab experiments are reviewed. The high luminosity fixed target environment at Fermilab has been a very fertile ground for the development of sophisticated, powerful triggering systems. A few of these are integrated systems designed to be flexible and to have broad application. Many are dedicated triggers taking advantage of large scale integrated circuits to focus on the specific needs of one experiment. In addition, the data acquisition requirements of large detectors, existing and planned, are being met with programmable systems to process the data. Offline reconstruction of data places a very heavy load on large general purpose computers. This offers a potentially very fruitful area for new developments involving programmable dedicated systems. Some of the present thinking at Fermilab regarding offline reconstruction processors will be described

  18. A review of programmable systems associated with Fermilab experiments

    International Nuclear Information System (INIS)

    Nash, T.

    1981-01-01

    In this paper we review the design and application of programmable systems for Fermilab experiments. The high luminosity fixed target environment at Fermilab has been a very fertile ground for the development of sophisticated, powerful triggering systems. A few of these are integrated systems designed to be flexible and to have broad application. Many are dedicated triggers taking advantage of large scale integrated circuits to focus on the specific needs of one experiment. In addition, the data acquisition requirements of large detectors, existing and planned, are being met with programmable systems to process the data. Offline reconstruction of data places a very heavy load on large general purpose computers. This offers a potentially very fruitful area for new developments involving programmable dedicated systems. Some of the present thinking at Fermilab regarding offline reconstruction processors will be described. (orig.)

  19. Vehicle barrier with access delay

    Science.gov (United States)

    Swahlan, David J; Wilke, Jason

    2013-09-03

    An access delay vehicle barrier for stopping unauthorized entry into secure areas by a vehicle ramming attack includes access delay features for preventing and/or delaying an adversary from defeating or compromising the barrier. A horizontally deployed barrier member can include an exterior steel casing, an interior steel reinforcing member and access delay members disposed within the casing and between the casing and the interior reinforcing member. Access delay members can include wooden structural lumber, concrete and/or polymeric members that in combination with the exterior casing and interior reinforcing member act cooperatively to impair an adversarial attach by thermal, mechanical and/or explosive tools.

  20. Photonic integrated circuits unveil crisis-induced intermittency.

    Science.gov (United States)

    Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

    2016-09-19

    We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

  1. Implementation of Chua's circuit using simulated inductance

    Science.gov (United States)

    Gopakumar, K.; Premlet, B.; Gopchandran, K. G.

    2011-05-01

    In this study we describe how to build an inductorless version of the classic Chua's circuit. A suitable inductor for Chua's circuit is often hard to procure. The required inductor for the circuit is designed using simple circuit elements such as resistors, capacitors and operational amplifiers. The complete circuit can be implemented by using off-the-shelf components, and it can readily be integrated on a single chip. This design of Chua's circuit allows the original dynamics to be slowed down to just a few hertz, enabling implementation of sophisticated control schemes without severe time restrictions. Another novel feature of the circuit is that losses associated with capacitors due to leakages can easily be compensated by providing negative resistance using the same setup. The chaotic behaviour of the circuit is verified by PSpice and Multisim simulation and also by experimental study on a circuit breadboard. The results give excellent agreement with each other and with the results of previous investigators.

  2. Delayed rule following.

    Science.gov (United States)

    Schmitt, D R

    2001-01-01

    Although the elements of a fully stated rule (discriminative stimulus [S(D)], some behavior, and a consequence) can occur nearly contemporaneously with the statement of the rule, there is often a delay between the rule statement and the S(D). The effects of this delay on rule following have not been studied in behavior analysis, but they have been investigated in rule-like settings in the areas of prospective memory (remembering to do something in the future) and goal pursuit. Discriminative events for some behavior can be event based (a specific setting stimulus) or time based. The latter are more demanding with respect to intention following and show age-related deficits. Studies suggest that the specificity with which the components of a rule (termed intention) are stated has a substantial effect on intention following, with more detailed specifications increasing following. Reminders of an intention, too, are most effective when they refer specifically to both the behavior and its occasion. Covert review and written notes are two effective strategies for remembering everyday intentions, but people who use notes appear not to be able to switch quickly to covert review. By focusing on aspects of the setting and rule structure, research on prospective memory and goal pursuit expands the agenda for a more complete explanation of rule effects.

  3. Pseudotumoral delayed cerebral radionecrosis

    International Nuclear Information System (INIS)

    Ciaudo-Lacroix, C.; Lapresle, J.

    1985-01-01

    A 60 year-old woman with a scalp epithelioma underwent radiotherapy, the dose being 57 Gray. A first epileptic seizure occurred twenty months later. Neurological examination revealed signs of left hemisphere involvement. γEG, angiography, CT scans, demonstrated a pseudotumoral avascular process. On account of the localisation, the patient being right-handed, no surgical procedure was performed. In spite of corticotherapy and anticonvulsive treatment, seizures recurred and neurological signs slowly progressed. The patient died, 22 months after the first seizure, of an associated disseminated carcinoma with cachexia. Neuropathological examination showed a massive lesion presenting all the features of delayed radionecrosis in the left hemisphere: situated mainly in the white matter; numerous vascular abnormalities; wide-spread demyelination; disappearance of oligoglial cells. The Authors recall the clinical and anatomical aspects of this condition for which the only successful treatment is surgical removal when location and size of the lesion permit. Finally, the mechanisms which have been proposed to explain this delayed cerebral radionecrosis are discussed [fr

  4. Pseudotumoral delayed cerebral radionecrosis

    Energy Technology Data Exchange (ETDEWEB)

    Ciaudo-Lacroix, C; Lapresle, J [Centre Hospitalier de Bicetre, 94 - Le Kremlin-Bicetre (France)

    1985-01-01

    A 60 year-old woman with a scalp epithelioma underwent radiotherapy, the dose being 57 Gray. A first epileptic seizure occurred twenty months later. Neurological examination revealed signs of left hemisphere involvement. ..gamma..EG, angiography, CT scans, demonstrated a pseudotumoral avascular process. On account of the localisation, the patient being right-handed, no surgical procedure was performed. In spite of corticotherapy and anticonvulsive treatment, seizures recurred and neurological signs slowly progressed. The patient died, 22 months after the first seizure, of an associated disseminated carcinoma with cachexia. Neuropathological examination showed a massive lesion presenting all the features of delayed radionecrosis in the left hemisphere: situated mainly in the white matter; numerous vascular abnormalities; wide-spread demyelination; disappearance of oligoglial cells. The Authors recall the clinical and anatomical aspects of this condition for which the only successful treatment is surgical removal when location and size of the lesion permit. Finally, the mechanisms which have been proposed to explain this delayed cerebral radionecrosis are discussed.

  5. Mexican medfly programme

    International Nuclear Information System (INIS)

    1980-01-01

    This film tells the story of the fight against and final extinction of the Mediterranean fruit-fly (Ceratitis capitata) in Mexico. By producing billions of high quality sterile flies in the Medfly reproduction and sterilization laboratory in the province of Chiapas and releasing them over infested areas, the Moscamed Programme succeeded in eradicating this pest from Mexico in 1982

  6. Nuclear safety. Improvement programme

    International Nuclear Information System (INIS)

    2000-01-01

    In this brochure the improvement programme of nuclear safety of the Mochovce NPP is presented in detail. In 1996, a 'Mochovce NPP Nuclear Safety Improvement Programme' was developed in the frame of unit 1 and 2 completion project. The programme has been compiled as a continuous one, with the aim to reach the highest possible safety level at the time of commissioning and to establish good preconditions for permanent safety improvement in future. Such an approach is in compliance with the world's trends of safety improvement, life-time extension, modernisation and nuclear station power increase. The basic document for development of the 'Programme' is the one titled 'Safety Issues and their Ranking for WWER 440/213 NPP' developed by a group of IAEA experts. The following organisations were selected for solution of the safety measures: EUCOM (Consortium of FRAMATOME, France, and SIEMENS, Germany); SKODA Prague, a.s.; ENERGOPROJEKT Prague, a.s. (EGP); Russian organisations associated in ATOMENERGOEXPORT; VUJE Trnava, a.s

  7. Progressive Retirement Programme

    CERN Document Server

    HR Department

    2009-01-01

    Following the Standing Concertation Committee meeting of 2 December 2008, please note that the Progressive Retirement Programme has been extended by one year, i.e. until 31 March 2010. Further information is available on : https://hr-services.web.cern.ch/hr-services/services-Ben/prp/prp.asp HR Department, tel. 73903

  8. Fusion technology programme

    International Nuclear Information System (INIS)

    Finken, D.

    1985-10-01

    KfK is involved in the European Fusion Programme predominantly in the NET and Fusion Technology part. The following fields of activity are covered: Studies for NET, alternative confinement concepts, and needs and issues of integral testing. Research on structural materials. Development of superconducting magnets. Gyrotron development (part of the Physics Programme). Nuclear technology (breeding materials, blanket design, tritium technology, safety and environmental aspects of fusion, remote maintenance). Reported here are status and results of work under contracts with the CEC within the NET and Technology Programme. The aim of the major part of this R and D work is the support of NET, some areas (e.g. materials, safety and environmental impact, blanket design) have a wider scope and address problems of a demonstration reactor. In the current working period, several new proposals have been elaborated to be implemented into the 85/89 Euratom Fusion Programme. New KfK contributions relate to materials research (dual beam and fast reactor irradiations, ferritic steels), to blanket engineering (MHD-effects) and to safety studies (e.g. magnet safety). (orig./GG)

  9. SET-Routes programme

    CERN Multimedia

    Marietta Schupp, EMBL Photolab

    2008-01-01

    Dr Sabine Hentze, specialist in human genetics, giving an Insight Lecture entitled "Human Genetics – Diagnostics, Indications and Ethical Issues" on 23 September 2008 at EMBL Heidelberg. Activities in a achool in Budapest during a visit of Angela Bekesi, Ambassadors for the SET-Routes programme.

  10. Exchange and fellowship programme

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1959-04-15

    By February 1959, the IAEA had received and considered nearly 300 nominations from 31 countries for nuclear science fellowships. More than 200 of the candidates - from 29 countries - had been selected for placement in centres of training in 21 countries. The programme covers three types of training: 1. General techniques training: to develop skills in the use of some fundamental techniques in the field of nuclear energy; 2. Specialist training: to prepare specialists in the theoretical and experimental aspects of the science and technology of nuclear energy; 3. Research training: to provide advanced training, including active participation in research work; this is for persons potentially qualified to develop and carry out research programmes in the basic sciences and engineering. The duration of training varies from some weeks to five or six years. The long-duration training is given at universities or educational establishments of university level, and is of special interest to Member States lacking personnel with the requisite university education. Under its 1959 exchange and fellowship programme, the Agency will be in a position to award over 400 fellowships. Some of these will be paid out of the Agency's operating fund, while 130 fellowships have been offered directly to IAEA by Member States for training at their universities or institutes. There are two new features in the Agency's 1959 programme. One provides for fellowships for scientific research work, the other is the exchange of specialists

  11. Air Quality Monitoring Programme

    DEFF Research Database (Denmark)

    Kemp, K.; Palmgren, F.

    The Danish Air Quality Monitoring Programme (LMP IV) has been revised in accordance with the Framework Directive and the first three daughter directives of SO2, NOx/NO2, PM10, lead, benzene, CO and ozone. PM10 samplers are under installation and the installation will be completed during 2002...

  12. Conceptualizing Programme Evaluation

    Science.gov (United States)

    Hassan, Salochana

    2013-01-01

    The main thrust of this paper deals with the conceptualization of theory-driven evaluation pertaining to a tutor training programme. Conceptualization of evaluation, in this case, is an integration between a conceptualization model as well as a theoretical framework in the form of activity theory. Existing examples of frameworks of programme…

  13. The European Programme Manager

    DEFF Research Database (Denmark)

    Larson, Anne; Bergman, E.; Ehlers, S.

    The publication is a result of a cooperation between organisations in six European countries with the aim to develop a common European education for programme managers. It contains of a description of the different elements of the education together with a number of case-studies from the counties...

  14. The Productive Programmer

    CERN Document Server

    Ford, Neal

    2009-01-01

    Anyone who develops software for a living needs a proven way to produce it better, faster, and cheaper. The Productive Programmer offers critical timesaving and productivity tools that you can adopt right away, no matter what platform you use. Master developer Neal Ford details ten valuable practices that will help you elude common traps, improve your code, and become more valuable to your team.

  15. Design and implementation of a programming circuit in radiation-hardened FPGA

    International Nuclear Information System (INIS)

    Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

    2011-01-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

  16. Design and implementation of a programming circuit in radiation-hardened FPGA

    Science.gov (United States)

    Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

    2011-08-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

  17. Introduction to Focus Issue: Time-delay dynamics

    Science.gov (United States)

    Erneux, Thomas; Javaloyes, Julien; Wolfrum, Matthias; Yanchuk, Serhiy

    2017-11-01

    The field of dynamical systems with time delay is an active research area that connects practically all scientific disciplines including mathematics, physics, engineering, biology, neuroscience, physiology, economics, and many others. This Focus Issue brings together contributions from both experimental and theoretical groups and emphasizes a large variety of applications. In particular, lasers and optoelectronic oscillators subject to time-delayed feedbacks have been explored by several authors for their specific dynamical output, but also because they are ideal test-beds for experimental studies of delay induced phenomena. Topics include the control of cavity solitons, as light spots in spatially extended systems, new devices for chaos communication or random number generation, higher order locking phenomena between delay and laser oscillation period, and systematic bifurcation studies of mode-locked laser systems. Moreover, two original theoretical approaches are explored for the so-called Low Frequency Fluctuations, a particular chaotical regime in laser output which has attracted a lot of interest for more than 30 years. Current hot problems such as the synchronization properties of networks of delay-coupled units, novel stabilization techniques, and the large delay limit of a delay differential equation are also addressed in this special issue. In addition, analytical and numerical tools for bifurcation problems with or without noise and two reviews on concrete questions are proposed. The first review deals with the rich dynamics of simple delay climate models for El Nino Southern Oscillations, and the second review concentrates on neuromorphic photonic circuits where optical elements are used to emulate spiking neurons. Finally, two interesting biological problems are considered in this Focus Issue, namely, multi-strain epidemic models and the interaction of glucose and insulin for more effective treatment.

  18. ADS National Programmes: China

    International Nuclear Information System (INIS)

    2015-01-01

    In China the conceptual study of an ADS concept which lasted for about five years ended in 1999. As one project of the National Basic Research Programme of China (973 Programme) in energy domain, which is sponsored by the China Ministry of Science and Technology (MOST), a five year programme of fundamental research of ADS physics and related technology was launched in 2000 and passed national review at the end of 2005. From 2007, another five year 973 Programme Key Technology Research of Accelerator Driven Subcritical System for Nuclear waste Transmutation started. The research activities were focused on HPPA physics and technology, reactor physics of external source driven subcritical assembly, nuclear data base and material study. For HPPA, a high current injector consisting of an ECR ion source, LEBT and an RFQ accelerating structure of 3.5 MeV has been built and were being improved. In reactor physics study, a series of neutron multiplication experimental study has been carrying out. The VENUS I facility has been constructed as the basic experimental platform for neutronics study in ADS blanket. VENUS I a zero power subcritical neutron multiplying assembly driven by external neutron produced by a pulsed neutron generator or 252Cf neutron source. The theoretical, experimental and simulation studies on nuclear data, material properties and nuclear fuel circulation related to ADS are carried out in order to provide the database for ADS system analysis. China Institute of Atomic Energy (CIAE), Institute of High Energy Physics (IHEP) and other Chinese institutes carried out the MOST project together. Besides CIAE, China Academy of Science (CAS) pays more and more attention to Advanced Nuclear Fuel Cycles (ANFC). A large programme of ANFC, including ADS and Th based nuclear fuel cycle, has been launched by CAS

  19. Advanced circuit simulation using Multisim workbench

    CERN Document Server

    Báez-López, David; Cervantes-Villagómez, Ofelia Delfina

    2012-01-01

    Multisim is now the de facto standard for circuit simulation. It is a SPICE-based circuit simulator which combines analog, discrete-time, and mixed-mode circuits. In addition, it is the only simulator which incorporates microcontroller simulation in the same environment. It also includes a tool for printed circuit board design.Advanced Circuit Simulation Using Multisim Workbench is a companion book to Circuit Analysis Using Multisim, published by Morgan & Claypool in 2011. This new book covers advanced analyses and the creation of models and subcircuits. It also includes coverage of transmissi

  20. Digital circuit boards mach 1 GHz

    CERN Document Server

    Morrison, Ralph

    2012-01-01

    A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

  1. Clocking Scheme for Switched-Capacitor Circuits

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    1998-01-01

    A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed.......A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed....

  2. Unbalanced Neuronal Circuits in Addiction

    OpenAIRE

    Volkow, Nora D.; Wang, Gen-Jack; Tomasi, Dardo; Baler, Ruben D.

    2013-01-01

    Through sequential waves of drug-induced neurochemical stimulation, addiction co-opts the brain's neuronal circuits that mediate reward, motivation, , to behavioral inflexibility and a severe disruption of self-control and compulsive drug intake. Brain imaging technologies have allowed neuroscientists to map out the neural landscape of addiction in the human brain and to understand how drugs modify it.

  3. A Low Noise Electronic Circuit

    NARCIS (Netherlands)

    Annema, Anne J.; Leenaerts, Dominicus M.W.; de Vreede, Petrus W.H.

    2002-01-01

    An electronic circuit, which can be used as a Low Noise Amplifier (LNA), comprises two complementary Field Effect Transistors (M1, M2; M5, M6), each having a gate, a source and a drain. The gates are connected together as a common input terminal, and the drains are connected together as a

  4. Circuit design for RF transceivers

    CERN Document Server

    Leenaerts, Domine; Vaucher, Cicero S

    2007-01-01

    Second edition of this successful 2001 RF Circuit Design book, has been updated, latest technology reviews have been added as well as several actual case studies. Due to the authors being active in industry as well as academia, this should prove to be an essential guide on RF Transceiver Design for students and engineers.

  5. Integrated Circuit Stellar Magnitude Simulator

    Science.gov (United States)

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  6. Simulated annealing and circuit layout

    NARCIS (Netherlands)

    Aarts, E.H.L.; Laarhoven, van P.J.M.

    1991-01-01

    We discuss the problem of approximately sotvlng circuit layout problems by simulated annealing. For this we first summarize the theoretical concepts of the simulated annealing algorithm using Ihe theory of homogeneous and inhomogeneous Markov chains. Next we briefly review general aspects of the

  7. RECRUITMENT FINANCED BY SAVED LEAVE (RSL PROGRAMME)

    CERN Multimedia

    Division du Personnel; Tel. 73903

    1999-01-01

    Transfer to the saved leave account and saved leave bonusStaff members participating in the RSL programme may opt to transfer up to 10 days of unused annual leave or unused compensatory leave into their saved leave account, at the end of the leave year, i.e. 30 September (as set out in the implementation procedure dated 27 August 1997).A leave transfer request form, which you should complete, sign and return, if you wish to use this possibility, has been addressed you. To allow the necessary time for the processing of your request, you should return it without delay.As foreseen in the implementation procedure, an additional day of saved leave will be granted for each full period of 20 days remaining in the saved leave account on 31 December 1999, for any staff member participating in the RSL programme until that date.For part-time staff members participating in the RSL programme, the above-mentioned days of leave (annual, compensatory and saved) are adjusted proportionally to their contractual working week as...

  8. Delay Insensitive Ternary CMOS Logic for Secure Hardware

    Directory of Open Access Journals (Sweden)

    Ravi S. P. Nair

    2015-09-01

    Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

  9. Stability and delay sensitivity of neutral fractional-delay systems.

    Science.gov (United States)

    Xu, Qi; Shi, Min; Wang, Zaihua

    2016-08-01

    This paper generalizes the stability test method via integral estimation for integer-order neutral time-delay systems to neutral fractional-delay systems. The key step in stability test is the calculation of the number of unstable characteristic roots that is described by a definite integral over an interval from zero to a sufficient large upper limit. Algorithms for correctly estimating the upper limits of the integral are given in two concise ways, parameter dependent or independent. A special feature of the proposed method is that it judges the stability of fractional-delay systems simply by using rough integral estimation. Meanwhile, the paper shows that for some neutral fractional-delay systems, the stability is extremely sensitive to the change of time delays. Examples are given for demonstrating the proposed method as well as the delay sensitivity.

  10. Experiments with arbitrary networks in time-multiplexed delay systems

    Science.gov (United States)

    Hart, Joseph D.; Schmadel, Don C.; Murphy, Thomas E.; Roy, Rajarshi

    2017-12-01

    We report a new experimental approach using an optoelectronic feedback loop to investigate the dynamics of oscillators coupled on large complex networks with arbitrary topology. Our implementation is based on a single optoelectronic feedback loop with time delays. We use the space-time interpretation of systems with time delay to create large networks of coupled maps. Others have performed similar experiments using high-pass filters to implement the coupling; this restricts the network topology to the coupling of only a few nearest neighbors. In our experiment, the time delays and coupling are implemented on a field-programmable gate array, allowing the creation of networks with arbitrary coupling topology. This system has many advantages: the network nodes are truly identical, the network is easily reconfigurable, and the network dynamics occur at high speeds. We use this system to study cluster synchronization and chimera states in both small and large networks of different topologies.

  11. Arbitrary digital pulse sequence generator with delay-loop timing

    Science.gov (United States)

    Hošák, Radim; Ježek, Miroslav

    2018-04-01

    We propose an idea of an electronic multi-channel arbitrary digital sequence generator with temporal granularity equal to two clock cycles. We implement the generator with 32 channels using a low-cost ARM microcontroller and demonstrate its capability to produce temporal delays ranging from tens of nanoseconds to hundreds of seconds, with 24 ns timing granularity and linear scaling of delay with respect to the number of delay loop iterations. The generator is optionally synchronized with an external clock source to provide 100 ps jitter and overall sequence repeatability within the whole temporal range. The generator is fully programmable and able to produce digital sequences of high complexity. The concept of the generator can be implemented using different microcontrollers and applied for controlling of various optical, atomic, and nuclear physics measurement setups.

  12. Effect of a Diagram on Primary Students' Understanding About Electric Circuits

    Science.gov (United States)

    Preston, Christine Margaret

    2017-09-01

    This article reports on the effect of using a diagram to develop primary students' conceptual understanding about electric circuits. Diagrammatic representations of electric circuits are used for teaching and assessment despite the absence of research on their pedagogical effectiveness with young learners. Individual interviews were used to closely analyse Years 3 and 5 (8-11-year-old) students' explanations about electric circuits. Data was collected from 20 students in the same school providing pre-, post- and delayed post-test dialogue. Students' thinking about electric circuits and changes in their explanations provide insights into the role of diagrams in understanding science concepts. Findings indicate that diagram interaction positively enhanced understanding, challenged non-scientific views and promoted scientific models of electric circuits. Differences in students' understanding about electric circuits were influenced by prior knowledge, meta-conceptual awareness and diagram conventions including a stylistic feature of the diagram used. A significant finding that students' conceptual models of electric circuits were energy rather than current based has implications for electricity instruction at the primary level.

  13. Delayed breast implant reconstruction

    DEFF Research Database (Denmark)

    Hvilsom, Gitte B.; Hölmich, Lisbet R.; Steding-Jessen, Marianne

    2012-01-01

    We evaluated the association between radiation therapy and severe capsular contracture or reoperation after 717 delayed breast implant reconstruction procedures (288 1- and 429 2-stage procedures) identified in the prospective database of the Danish Registry for Plastic Surgery of the Breast during...... of radiation therapy was associated with a non-significantly increased risk of reoperation after both 1-stage (HR = 1.4; 95% CI: 0.7-2.5) and 2-stage (HR = 1.6; 95% CI: 0.9-3.1) procedures. Reconstruction failure was highest (13.2%) in the 2-stage procedures with a history of radiation therapy. Breast...... reconstruction approaches other than implants should be seriously considered among women who have received radiation therapy....

  14. Delay tolerant networks

    CERN Document Server

    Gao, Longxiang; Luan, Tom H

    2015-01-01

    This brief presents emerging and promising communication methods for network reliability via delay tolerant networks (DTNs). Different from traditional networks, DTNs possess unique features, such as long latency and unstable network topology. As a result, DTNs can be widely applied to critical applications, such as space communications, disaster rescue, and battlefield communications. The brief provides a complete investigation of DTNs and their current applications, from an overview to the latest development in the area. The core issue of data forward in DTNs is tackled, including the importance of social characteristics, which is an essential feature if the mobile devices are used for human communication. Security and privacy issues in DTNs are discussed, and future work is also discussed.

  15. Global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms

    International Nuclear Information System (INIS)

    Wang Jian; Lu Junguo

    2008-01-01

    In this paper, we study the global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms. By constructing a suitable Lyapunov functional and utilizing some inequality techniques, we obtain a sufficient condition for the uniqueness and global exponential stability of the equilibrium solution for a class of fuzzy cellular neural networks with delays and reaction-diffusion terms. The result imposes constraint conditions on the network parameters independently of the delay parameter. The result is also easy to check and plays an important role in the design and application of globally exponentially stable fuzzy neural circuits

  16. Analytical and experimental study of two delay-coupled excitable units.

    Science.gov (United States)

    Weicker, Lionel; Erneux, Thomas; Keuninckx, Lars; Danckaert, Jan

    2014-01-01

    We investigate the onset of time-periodic oscillations for a system of two identical delay-coupled excitable (nonoscillatory) units. We first analyze these solutions by using asymptotic methods. The oscillations are described as relaxation oscillations exhibiting successive slow and fast changes. The analysis highlights the determinant role of the delay during the fast transition layers. We then study experimentally a system of two coupled electronic circuits that is modeled mathematically by the same delay differential equations. We obtain quantitative agreements between analytical and experimental bifurcation diagrams.

  17. Organizing of delay, input gate and memory of proportional chamber channel basing on D-trigger

    International Nuclear Information System (INIS)

    Vladimirov, S.V.; Kuzichev, V.F.; Rabin, N.V.

    1980-01-01

    Economical organization of delay, input gate and proportional chamber (PC) channel memory on the 155 TM2 D trigger basis is described. The channel consists of an amplifier; delay element permitting to synchronize PC signal and recording strobe-signal; input gate, where coincidence of the above signals occurs; memory element, where the data from a wire are recorded and stored; read gate through which the data are transmitted for further processing. Presented is one of the versions of circuit solution for delay element, input gate and momory element. Flowsheet peculiarity is the simplicity of fabrication and tuning as well as low cost of the device

  18. Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

    Directory of Open Access Journals (Sweden)

    Yoni Aizik

    2011-01-01

    Full Text Available A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

  19. The voltage—current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

    International Nuclear Information System (INIS)

    Bao Bo-Cheng; Feng Fei; Dong Wei; Pan Sai-Hu

    2013-01-01

    A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage—current relationships (VCRs) between two parallel memristive circuits — a parallel memristor and capacitor circuit (the parallel MC circuit), and a parallel memristor and inductor circuit (the parallel ML circuit) — are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and experimental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results

  20. Donor transplant programme

    International Nuclear Information System (INIS)

    Abu Bakar Sulaiman

    1999-01-01

    The transplantation of organs and tissues from one human to another human has become an essential and well established form of therapy for many types of organ and tissue failure. In Malaysia, kidney, cornea and bone marrow transplantation are well established. Recently, liver, bone and heart transplanation have been performed. Unfortunately, because of the lack of cadaveric organ donation, only a limited number of solid organ transplantation have been performed. The cadaveric organ donor rate in Malaysia is low at less than one per million population. The first tissue transplanted in Malaysia was the cornea which was performed in the early 1970s. At that time and even now the majority of corneas came from Sri Lanka. The first kidney transplant was performed in 1975 from a live related donor. The majority of the 629 kidney transplants done at Hospital Kuala Lumpur to date have been from live related donors. Only 35 were from cadaver donors. Similarly, the liver transplantation programme which started in 1995 are from live related donors. A more concerted effort has been made recently to increase the awareness of the public and the health professionals on organ and tissue donation. This national effort to promote organ and tissue donation seems to have gathered momentum in 1997 with the first heart transplant successfully performed at the National Heart Institute. The rate of cadaveric donors has also increased from a previous average of I to 2 per year to 6 per year in the last one year. These developments are most encouraging and may signal the coming of age of our transplantati on programme. The Ministry of Health in conjunction with various institutions, organizations and professional groups, have taken a number of proactive measures to facilitate the development of the cadaveric organ donation programme. Efforts to increase public awareness and to overcome the negative cultural attitude towards organ donation have been intensified. Equally important are efforts