1.5V fully programmable CMOS Membership Function Generator Circuit with proportional DC-voltage control

Directory of Open Access Journals (Sweden)

C. Muñiz-Montero

2013-06-01

Full Text Available A Membership Function Generator Circuit (MFGC with bias supply of 1.5 Volts and independent DC-voltage programmable functionalities is presented. The realization is based on a programmable differential current mirror and three compact voltage-to-current converters, allowing continuous and quasi-linear adjustment of the center position, height, width and slopes of the triangular/trapezoidal output waveforms. HSPICE simulation results of the proposed circuit using the parameters of a double-poly, three metal layers, 0.5 μm CMOS technology validate the functionality of the proposed architecture, which exhibits a maximum deviation of the linearity in the programmability of 7 %.

A Novel Programmable CMOS Fuzzifiers Using Voltage-to-Current Converter Circuit

Directory of Open Access Journals (Sweden)

K. P. Abdulla

2012-01-01

Full Text Available This paper presents a new voltage-input, current-output programmable membership function generator circuit (MFC using CMOS technology. It employs a voltage-to-current converter to provide the required current bias for the membership function circuit. The proposed MFC has several advantageous features. This MFC can be reconfigured to perform triangular, trapezoidal, S-shape, Z-Shape, and Gaussian membership forms. This membership function can be programmed in terms of its width, slope, and its center locations in its universe of discourses. The easily adjustable characteristics of the proposed circuit and its accuracy make it suitable for embedded system and industrial control applications. The proposed MFC is designed using the spice software, and simulation results are obtained.

Practical programmable circuits a guide to PLDs, state machines, and microcontrollers

CERN Document Server

Broesch, James D

1991-01-01

This is a practical guide to programmable logic devices. It covers all devices related to PLD: PALs, PGAs, state machines, and microcontrollers. Usefulness is evaluated; support needed in order to effectively use the devices is discussed. All examples are based on real-world circuits.

A new time-digital convert circuit based on digital delay line

International Nuclear Information System (INIS)

Liu Haifeng; Guo Ying; Zhang Zhi

2004-01-01

An introduction of a new method of time-digital convert circuit based on digital delay line is given. High precision and good reliability can be realized when it is combined with traditional counting convert method in the measurement of large scale pulse width and low frequency self-excitation oscillator. (authors)

Improved On-Chip Measurement of Delay in an FPGA or ASIC

Science.gov (United States)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Chaos in the fractional order logistic delay system: Circuit realization and synchronization

International Nuclear Information System (INIS)

Baskonus, Haci Mehmet; Hammouch, Zakia; Mekkaoui, Toufik; Bulut, Hasan

2016-01-01

In this paper, we present a numerical study and a circuit design to prove existence of chaos in the fractional order Logistic delay system. In addition, we investigate an active control synchronization scheme in this system. Numerical and cicruit simulations show the effectiveness and feasibility of this method.

LHCb: Radiation hard programmable delay line for LHCb Calorimeter Upgrade

CERN Multimedia

Mauricio Ferre, J; Vilasís Cardona, X; Picatoste Olloqui, E; Machefert, F; Lefrançois, J; Duarte, O

2013-01-01

This poster describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with a 4ps jitter and 18ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35um technology.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

Science.gov (United States)

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

SENARIET, A Programme To Solve Transient Flows Of Liquids In Complex Circuits

Science.gov (United States)

Vargas-Munoz, M.; Rodriguez-Fernandez, M.; Perena-Tapiador, A.

2011-05-01

SENARIET is a programme to study fluid transients in pipeline systems in order to obtain pressure and velocity distributions along a circuit. When a transient process occurs in periods of the same order of the pressure waves’ travelling time along a circuit (the order of the circuit length divided by the effective propagation speed), the compressibility effects in liquids have to be considered. Taking this effect into account, the appropriate equations of continuity and momentum are solved by the method of characteristics, to obtain pressure and velocity along pipes as a function of time. The simulated results have been compared to theoretical and experimental ones to validate and evaluate the precision of the software. The results help to perform efficient and accurate predictions in order to define the propulsion sub-system. This type of analysis is very important in order to evaluate the water hammer effects in propulsion systems used on spacecrafts and launchers.

Peak reading detector circuit

International Nuclear Information System (INIS)

Courtin, E.; Grund, K.; Traub, S.; Zeeb, H.

1975-01-01

The peak reading detector circuit serves for picking up the instants during which peaks of a given polarity occur in sequences of signals in which the extreme values, their time intervals, and the curve shape of the signals vary. The signal sequences appear in measuring the foetal heart beat frequence from amplitude-modulated ultrasonic, electrocardiagram, and blood pressure signals. In order to prevent undesired emission of output signals from, e. g., disturbing intermediate extreme values, the circuit consists of the series connections of a circuit to simulate an ideal diode, a strong unit, a discriminator for the direction of charging current, a time-delay circuit, and an electronic switch lying in the decharging circuit of the storage unit. The time-delay circuit thereby causes storing of a preliminary maximum value being used only after a certain time delay for the emission of the output signal. If a larger extreme value occurs during the delay time the preliminary maximum value is cleared and the delay time starts running anew. (DG/PB) [de

Precise delay measurement through combinatorial logic

Science.gov (United States)

Burke, Gary R. (Inventor); Chen, Yuan (Inventor); Sheldon, Douglas J. (Inventor)

2010-01-01

A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

Programmable dispersion on a photonic integrated circuit for classical and quantum applications.

Science.gov (United States)

Notaros, Jelena; Mower, Jacob; Heuck, Mikkel; Lupo, Cosmo; Harris, Nicholas C; Steinbrecher, Gregory R; Bunandar, Darius; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

2017-09-04

We demonstrate a large-scale tunable-coupling ring resonator array, suitable for high-dimensional classical and quantum transforms, in a CMOS-compatible silicon photonics platform. The device consists of a waveguide coupled to 15 ring-based dispersive elements with programmable linewidths and resonance frequencies. The ability to control both quality factor and frequency of each ring provides an unprecedented 30 degrees of freedom in dispersion control on a single spatial channel. This programmable dispersion control system has a range of applications, including mode-locked lasers, quantum key distribution, and photon-pair generation. We also propose a novel application enabled by this circuit - high-speed quantum communications using temporal-mode-based quantum data locking - and discuss the utility of the system for performing the high-dimensional unitary optical transformations necessary for a quantum data locking demonstration.

A programmable CCD driver circuit for multiphase CCD operation

International Nuclear Information System (INIS)

Ewin, A.J.; Reed, K.V.

1989-01-01

A programmable CCD driver circuit was designed to drive CCD's in multiphased modes. The purpose of the drive electronics was to operate developmental CCD imaging arrays for NASA's Moderate Resolution Imaging Spectrometer - Tiltable (MODIS-T). Five prototype arrays were designed. Valid's Graphics Editor (GED) was used to design the driver. With this driver design, any of the five arrays can be readout. Designing the driver with GED allowed functional simulation, timing verification, and certain packaging analyses to be done on the design before fabrication. The driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400 Kpixels/sec. Timing and packaging parameters were verified. the design uses 54 TTL component chips

A high-resolution programmable Vernier delay generator based on carry chains in FPGA.

Science.gov (United States)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 20  ° C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

A high-resolution programmable Vernier delay generator based on carry chains in FPGA

Science.gov (United States)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 2 0°C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

Science.gov (United States)

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS and LHC Transverse Dampers

CERN Document Server

Rossi, V

2002-01-01

In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC-type beams circulating in t...

On mill flow rate and fineness control in cement grinding circuits: instability and delayed measurements

International Nuclear Information System (INIS)

Lepore, R.; Boulvin, M.; Renotte, C.; Remy, M.

1999-01-01

A control structure for the mill flow rate and the product fineness is designed, with the feed flow rate and the classifier characteristic as the manipulated variables. Experimental results from a plant highlight the instability of the grinding circuit. A model previously developed by the authors stresses the major influence of the classifier nonlinearities onto this instability. A cascade control structure has been designed and implemented on site. The measurements of the product fineness, sensitive to material grindability fluctuations, are randomly time-delayed. The control structure uses a fineness estimator based on an adaptive scheme and a time delay compensator. (author)

Small Delay and High Performance AD/DA Converters of Lease Circuit System for AM&FM Broadcast

Science.gov (United States)

Takato, Kenji; Suzuki, Dai; Ishii, Takashi; Kobayashi, Masato; Yamada, Hirokazu; Amano, Shigeru

Many AM&FM broadcasting stations in Japan are connected by the leased circuit system of NTT. Small delay and high performance AD/DA converter was developed for the system. The system was designed based on ITU-T J.41 Recommendation (384kbps), the transmission signal is 11bit-32 kHz where the Gain-frequency characteristics between 40Hz to 15kHz have to be quite flat. The ΔΣAD/DA converter LSIs for audio application in the market today realize very high performance. However the performance is not enough for the leased circuit system. We found that it is not possible to meet the delay and Gain-frequency requirements only by using ΔΣAD/DA converter LSI in normal operation, because 15kHz the highest frequency and 16kHz Nyquist frequency are too close, therefore there are aliasing around Nyquist frequency. In this paper, we designed AD/DA architecture having small delay (1msec) and sharp cut off LPF (100dB attenuation at 16kHz, and 1500dB/Oct from 15kHz to 16kHz) by operating ΔΣAD/DA converter LSIs over-sampling rate such as 128kHz and by adding custom LPF designed Infinite Impulse Response (IIR) filter. The IIR filter is a 16th order elliptic type and it is consist of eight biquad filters in series. We described how to evaluate the stability of IIR filter theoretically by calculating frequency response, Pole and Zero Layout and impulse response of each biquad filter, and experimentally by adding overflow detection circuit on each filters and input overlord signal.

Multiple channel programmable coincidence counter

Science.gov (United States)

Arnone, Gaetano J.

1990-01-01

A programmable digital coincidence counter having multiple channels and featuring minimal dead time. Neutron detectors supply electrical pulses to a synchronizing circuit which in turn inputs derandomized pulses to an adding circuit. A random access memory circuit connected as a programmable length shift register receives and shifts the sum of the pulses, and outputs to a serializer. A counter is input by the adding circuit and downcounted by the seralizer, one pulse at a time. The decoded contents of the counter after each decrement is output to scalers.

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

Analysis and Implementation of Cryptographic Hash Functions in Programmable Logic Devices

Directory of Open Access Journals (Sweden)

Tautvydas Brukštus

2016-06-01

Full Text Available In this day’s world, more and more focused on data pro-tection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryp-tographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryp-tographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less effi-ciency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be inves-tigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integ-rated circuit made using different dimension technology. Choo-sing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Re-search show the calculation speed and stability of different prog-rammable logic circuits.

Programmable delay circuit for sparker signal analysis

Digital Repository Service at National Institute of Oceanography (India)

Pathak, D.

The sparker echo signal had been recorded along with the EPC recorder trigger on audio cassettes in a dual channel analog recorder. The sparker signal in the analog form had to be digitised for further signal processing techniques to be performed...

Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

Directory of Open Access Journals (Sweden)

Ruiping Cao

2014-01-01

Full Text Available In high-speed applications, MOS current mode logic (MCML is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP. However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

The impact of software and CAE tools on SEU in field programmable gate arrays

International Nuclear Information System (INIS)

Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

1999-01-01

Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements

Analysis of electronic circuits using digital computers; L'analyse des circuits electroniques par les calculateurs numeriques

Energy Technology Data Exchange (ETDEWEB)

Tapu, C [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1968-07-01

Various programmes have been proposed for studying electronic circuits with the help of computers. It is shown here how it possible to use the programme ECAP, developed by I.B.M., for studying the behaviour of an operational amplifier from different point of view: direct current, alternating current and transient state analysis, optimisation of the gain in open loop, study of the reliability. (author) [French] Differents programmes ont ete proposes pour l'etude des circuits electroniques a l'aide des calculateurs. On montre comment on peut utiliser le programme ECAP, mis au point par I. B. M., pour etudier le comportement d'un amplificateur operationnel, a differents points de vue: analyse en courant continu, courant alternatif et regime transitoire, optimalisation du gain en boucle ouverte, etude de la fiabilite. (auteur)

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

Science.gov (United States)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

A new fast and programmable trigger logic

International Nuclear Information System (INIS)

Fucci, A.; Amendolia, S.R.; Bertolucci, E.; Bottigli, U.; Bradaschia, C.; Foa, L.; Giazotto, A.; Giorgi, M.; Givoletti, M.; Lucardesi, P.; Menzione, A.; Passuello, D.; Quaglia, M.; Ristori, L.; Rolandi, L.; Salvadori, P.; Scribano, A.; Stanga, R.; Stefanini, A.; Vincelli, M.L.

1977-01-01

The NA1 (FRAMM) experiment, under construction for the CERN-SPS North Area, deals with more than 1000 counter signals which have to be combined together in order to build sophisticated and highly selective triggers. These requirements have led to the development of a low cost, combinatorial, fast electronics which can replace, in an advantageous way the standard NIM electronics at the trigger level. The essential performances of the basic circuit are: 1) programmability of any desired logical expression; 2) trigger time independent of the chosen expression; 3) reduced cost and compactness due to the use of commercial RAMs, PROMs, and PLAs; 4) short delay, less than 20 ns, between input and output pulses. (Auth.)

Timing Analysis of Genetic Logic Circuits using D-VASim

DEFF Research Database (Denmark)

Baig, Hasan; Madsen, Jan

and propagation delay analysis of single as well as cascaded geneticlogic circuits can be performed. D-VASim allows user to change the circuit parameters during runtime simulation to observe its effectson circuit’s timing behavior. The results obtained from D-VASim can be used not only to characterize the timing...... delay analysis may play a very significant role in the designing of genetic logic circuits. In thisdemonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagationdelay analysis of genetic logic circuits. Using D-VASim, the timing...... behavior of geneticlogic circuits but also to analyze the timing constraints of cascaded genetic logic circuits....

Scan cell design for enhanced delay fault testability

NARCIS (Netherlands)

van Brakel, Gerrit; van Brakel, G.; Xing, Yizi; Xing, Y.; Kerkhoff, Hans G.

1992-01-01

Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan

Structural and composition investigations at delayered locations of low k integrated circuit device by gas-assisted focused ion beam

Energy Technology Data Exchange (ETDEWEB)

Wang, Dandan, E-mail: dandan.wang@globalfoundries.com; Kee Tan, Pik; Yamin Huang, Maggie; Lam, Jeffrey; Mai, Zhihong [Technology Development Department, GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406 (Singapore)

2014-05-15

The authors report a new delayering technique – gas-assisted focused ion beam (FIB) method and its effects on the top layer materials of integrated circuit (IC) device. It demonstrates a highly efficient failure analysis with investigations on the precise location. After removing the dielectric layers under the bombardment of an ion beam, the chemical composition of the top layer was altered with the reduced oxygen content. Further energy-dispersive x-ray spectroscopy and Fourier transform infrared analysis revealed that the oxygen reduction lead to appreciable silicon suboxide formation. Our findings with structural and composition alteration of dielectric layer after FIB delayering open up a new insight avenue for the failure analysis in IC devices.

Managing contamination delay to improve Timing Speculation architectures

Directory of Open Access Journals (Sweden)

Naga Durga Prasad Avirneni

2016-08-01

Full Text Available Timing Speculation (TS is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.

A fortran programme for determining frequency responses for linear systems with time delays

International Nuclear Information System (INIS)

Milsom, P.R.

1966-11-01

In this report a digital computer programme for evaluating frequency responses is described. In its standard form the programme is capable of determining the gain and phase of up to 35 variables over a range of up to 30 frequencies for a system described by up to 65 equations. The equations must be either first order differential or algebraic and either type may include time delayed terms. Up to 50 such terms are permissible throughout the equation set. Provision is made for up to 10 inputs and up to 50 differentiated input terms are permitted throughout the equation set. However, it is possible for the user to increase a maximum dimension, albeit at the expense of another array dimension. In punching the data from the equations the user has no sorting or arranging of coefficients to do, and the equations may be in any order. The specifying of other input information, such as frequency range, the inputs to be perturbed and the variables for which frequency responses are required, is also very straightforward. (author)

Temperature Dependent Wire Delay Estimation in Floorplanning

DEFF Research Database (Denmark)

Winther, Andreas Thor; Liu, Wei; Nannarelli, Alberto

2011-01-01

Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this w......Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability....... In this work, we show that using wirelength as the evaluation metric does not always produce a floorplan with the shortest delay. We propose a temperature dependent wire delay estimation method for thermal aware floorplanning algorithms, which takes into account the thermal effect on wire delay. The experiment...

Development of a non-delay-line constant-fraction discriminator

International Nuclear Information System (INIS)

Yang Tao; Zhao Bo; Zhang Chi

2002-01-01

A Non-Delay-Line Constant-Fraction Discriminator (CFD) timing circuit is introduced. The delay line in the CFD is replaced with a low pass filter in this simplified circuit. The timing resolution of the CFD is better than 150 ps

Hybdrid integral circuit for proportional chambers

International Nuclear Information System (INIS)

Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

1978-01-01

Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

Dynamics of Nonlinear Time-Delay Systems

CERN Document Server

Lakshmanan, Muthusamy

2010-01-01

Synchronization of chaotic systems, a patently nonlinear phenomenon, has emerged as a highly active interdisciplinary research topic at the interface of physics, biology, applied mathematics and engineering sciences. In this connection, time-delay systems described by delay differential equations have developed as particularly suitable tools for modeling specific dynamical systems. Indeed, time-delay is ubiquitous in many physical systems, for example due to finite switching speeds of amplifiers in electronic circuits, finite lengths of vehicles in traffic flows, finite signal propagation times in biological networks and circuits, and quite generally whenever memory effects are relevant. This monograph presents the basics of chaotic time-delay systems and their synchronization with an emphasis on the effects of time-delay feedback which give rise to new collective dynamics. Special attention is devoted to scalar chaotic/hyperchaotic time-delay systems, and some higher order models, occurring in different bran...

Global synchronization criteria with channel time-delay for chaotic time-delay system

International Nuclear Information System (INIS)

Sun Jitao

2004-01-01

Based on the Lyapunov stabilization theory, matrix measure, and linear matrix inequality (LMIs), this paper studies the chaos synchronization of time-delay system using the unidirectional linear error feedback coupling with time-delay. Some generic conditions of chaos synchronization with time-delay in the transmission channel is established. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criteria under which the global chaos synchronization of the time-delay coupled systems is achieved

Economic testing of large integrated switching circuits - a challenge to the test engineer

International Nuclear Information System (INIS)

Kreinberg, W.

1978-01-01

With reference to large integrated switching circuits, one can use an incoming standard programme test or the customer's switching circuits. The author describes the development of suitable, extensive and economical test programmes. (orig.) [de

Low cost design of microprocessor EDAC circuit

International Nuclear Information System (INIS)

Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

2015-01-01

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

Modeling delay in genetic networks: from delay birth-death processes to delay stochastic differential equations.

Science.gov (United States)

Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Bennett, Matthew R; Josić, Krešimir; Ott, William

2014-05-28

Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

Energy Technology Data Exchange (ETDEWEB)

Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Bennett, Matthew R. [Department of Biochemistry and Cell Biology, Rice University, Houston, Texas 77204, USA and Institute of Biosciences and Bioengineering, Rice University, Houston, Texas 77005 (United States); Josić, Krešimir [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Department of Biology and Biochemistry, University of Houston, Houston, Texas 77204 (United States)

2014-05-28

Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

International Nuclear Information System (INIS)

Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William; Bennett, Matthew R.; Josić, Krešimir

2014-01-01

Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

Science.gov (United States)

Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

2010-01-01

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

Break-before-make CMOS inverter for power-efficient delay implementation.

Science.gov (United States)

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

A high-precision synchronization circuit for clock distribution

International Nuclear Information System (INIS)

Lu Chong; Tan Hongzhou; Duan Zhikui; Ding Yi

2015-01-01

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm 2 , and the power consumption is 1.64 mW at 500 MHz. (paper)

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

Directory of Open Access Journals (Sweden)

Michael S. Hsiao

2002-01-01

Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

The practical engineer-fine-tuning memory macros using variable internal delays

CERN Document Server

Gray, K

1999-01-01

Embedded memory blocks are extremely common in application-specific IC (ASIC) chips. In this era of design reuse, it is critical that these memory macros, as they are also called, should be as versatile as possible. Their $9 performance should be optimal, with adequate sense amplifier signal over the full manufacturing process range of the chip. Fortunately, several simple techniques exist for adapting memory macros to different applications running at $9 different speeds. The key is to design in delays that are variable and/or programmable. The approach is also helpful in debugging initial hardware where a memory macro is refusing to function because its timing is too fast and there $9 is insufficient internal delay for proper circuit operation. The techniques can also eliminate the process of redesigning and refabricating the initial hardware just to characterize it. A memory macro is made to function by internal $9 pulses, generated in the correct number, sequence and relationship by the internal timing ch...

Development of hybrid micro circuit based multi-channel programmable HV supply for BARC-pelletron experimental facility

International Nuclear Information System (INIS)

Manna, A.; Thombare, S.; Moitra, S.; Kuswarkar, M.; Punna, M.; Nair, P.M.; Diwakar, M.P.; Pithawa, C.K.

2013-01-01

Electronics Division, BARC has developed a Multi channel programmable HV bias supply system for charge particle detector array for use in BARC-TIFR Pelletron-LINAC facility. The HV supplies are compact in size due to use of hybrid micro-circuits developed indigenously and are modular in construction to achieve versatility, scalability and serviceability. All programming operations and monitoring are performed remotely through PC over Ethernet. Each supply has a built-in over voltage, over current and thermal overload protections for safe operation and employs a Zero Voltage Switching (ZVS) technique to reduce thermal stress on the inverter switches. This article describes salient design aspects and performance of the HV supply system. (author)

UWB delay and multiply receiver

Energy Technology Data Exchange (ETDEWEB)

Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

2013-09-10

An ultra-wideband (UWB) delay and multiply receiver is formed of a receive antenna; a variable gain attenuator connected to the receive antenna; a signal splitter connected to the variable gain attenuator; a multiplier having one input connected to an undelayed signal from the signal splitter and another input connected to a delayed signal from the signal splitter, the delay between the splitter signals being equal to the spacing between pulses from a transmitter whose pulses are being received by the receive antenna; a peak detection circuit connected to the output of the multiplier and connected to the variable gain attenuator to control the variable gain attenuator to maintain a constant amplitude output from the multiplier; and a digital output circuit connected to the output of the multiplier.

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

International Nuclear Information System (INIS)

Tang Lu; Wang Zhigong; Xue Hong; He Xiaohu; Xu Yong; Sun Ling

2010-01-01

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed. Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL. An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit. Through integrating the D-latch with 'OR' logic for dual-modulus operation, the delays associated with both the 'OR' and D-flip-flop (DFF) operations are reduced, and the complexity of the circuit is also decreased. The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model. The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system. The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz. The circuit exhibits a low RMS jitter of 3.3 ps. The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply. (semiconductor integrated circuits)

All optical programmable logic array (PLA)

Science.gov (United States)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

Science.gov (United States)

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

International Nuclear Information System (INIS)

Duan Shukai; Liao Xiaofeng

2007-01-01

A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments

Control circuits for the 1.3 GeV electron synchrotron

International Nuclear Information System (INIS)

Asaoka, S.; Shiino, K.; Yoshioka, M.; Norimura, K.

1980-01-01

Following control circuits for the 1.3 GeV electron synchrotron, Institute for Nuclear Study, University of Tokyo, have been designed and constructed. 1. Variable delay circuits for the timing pulse of the synchrotron. 2. An alarm circuit for sputter ion pumps. 3. A sample and hold circuit for digital display and computer control of the beam intensity. This report describes detailes of the circuits and their specificatons. (author)

Variable Delay Element For Jitter Control In High Speed Data Links

Science.gov (United States)

Livolsi, Robert R.

2002-06-11

A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.

Vernier Delay Unit

International Nuclear Information System (INIS)

Pierce, W.B.

1984-10-01

This module will accept differential ECL pulses from the auxiliary rear panel or NIM level pulses from the front panel. The pulses are produced at the output with a fixed delay that is software programmable in steps of 0.1 ns over the range of 0.1 to 10.5 ns. Multiple outputs are available at the front panel. Minimum delay through the module is 9 ns

A SHORT-TERM CIRCUIT RESISTANCE PROGRAMME REDUCED EPICARDIAL FAT IN OBESE AGED WOMEN.

Science.gov (United States)

Rosety, Miguel Angel; Pery, Maria Teresa; Rodriguez-Pareja, Maria Antonia; Diaz, Antonio; Rosety, Jesus; Garcia, Natalia; Brenes-Martin, Francisco; Rosety-Rodríguez, Manuel; Toro, Rocío; Ordoñez, Francisco Javier; Rosety, Ignacio

2015-11-01

this study was conducted to ascertain the effects of resistance circuit training on epicardial adipose tissue (EAT) in obese aged women. A secondary objective was to assess muscle damage induced by supervised resistance training to confirm the intervention program was effective and safe. in the present interventional study, a total of 48 obese aged women were recruited from the community. Twenty-four of them were randomly assigned to perform a 12-week resistance circuit training programme, 3-days per week. This training was circularly performed in 6 stations: arm curl, leg extension, seated row, leg curl, triceps extension and leg press. The Jamar handgrip electronic dynamometer was used to assess maximal handgrip strength of the dominant hand. Two experienced observers assessed EAT by transthoracic two-dimensional echocardiography. Lastly, serum samples were analysed using one-step sandwich assays for creatine kinase activity (CK) and myoglobin (MB) concentration. as was hypothesized, resistance training significantly reduced EAT thickness (8.4 ± 1.0 vs. 7.3 ± 1.3 mm; p = 0.014; d = 0.76) in the experimental group. Resistance training induced no significant changes in markers of muscle damage such as CK (181.6 ± 36.9 vs. 194.2 ± 37.8 U/l; p = 0.31) and MB (62.4 ± 7.1 vs. 67.3 ± 7.7 ng/ml; p = 0.26). No significant changes in any of the tested outcomes were found in the control group. resistance training reduced EAT in aged obese women. A secondary finding was that the training program was effective and safe. While current results are promising, future studies are still required to consolidate this approach in clinical application. Copyright AULA MEDICA EDICIONES 2014. Published by AULA MEDICA. All rights reserved.

Integrated circuit implementation of fuzzy controllers

OpenAIRE

Huertas Díaz, José Luis; Sánchez Solano, Santiago; Baturone Castillo, María Iluminada; Barriga Barros, Ángel

1996-01-01

This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno’s method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these...

Calculation programme for transient thermo-pneumatic flows; Programme de calcul pour les ecoulements transitoires thermopneumatiques

Energy Technology Data Exchange (ETDEWEB)

Coste, D [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1964-07-01

With a view to determining the changes occurring in gas reactors after cooling accidents, a calculation programme is established for unidimensional gas flows with pressure drops, heat exchanges and in certain cases blowing, in a reticulated lattice. Any schematization can be taken into account by the use of a set of indices. This programme, of which the FORTRAN list is given, is applied to particular cases of sudden pressure drops in the circuits. The results obtained are in good agreement with those obtained both from the graphical method using the characteristics and from experimental recorded data. (author) [French] En vue de determiner les evolutions des reacteurs a gaz apres accident de refroidissement, on etablit un programme de calcul pour les ecoulements gazeux unidimensionnels avec pertes de charge, echanges thermiques et eventuellement soufflage, en reseau maille. Toute schematisation peut etre prise en compte grace a un jeu d'indices. Ce programme, dont la liste FORTRAN est presentee, est applique a des cas particuliers de degonflage brutal de circuits. Ses resultats sont en bon accord, d'une part avec ceux de la methode graphique des caracteristiques, d'autre part avec des enregistrements experimentaux. (auteur)

Calculation programme for transient thermo-pneumatic flows; Programme de calcul pour les ecoulements transitoires thermopneumatiques

Energy Technology Data Exchange (ETDEWEB)

Coste, D. [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1964-07-01

With a view to determining the changes occurring in gas reactors after cooling accidents, a calculation programme is established for unidimensional gas flows with pressure drops, heat exchanges and in certain cases blowing, in a reticulated lattice. Any schematization can be taken into account by the use of a set of indices. This programme, of which the FORTRAN list is given, is applied to particular cases of sudden pressure drops in the circuits. The results obtained are in good agreement with those obtained both from the graphical method using the characteristics and from experimental recorded data. (author) [French] En vue de determiner les evolutions des reacteurs a gaz apres accident de refroidissement, on etablit un programme de calcul pour les ecoulements gazeux unidimensionnels avec pertes de charge, echanges thermiques et eventuellement soufflage, en reseau maille. Toute schematisation peut etre prise en compte grace a un jeu d'indices. Ce programme, dont la liste FORTRAN est presentee, est applique a des cas particuliers de degonflage brutal de circuits. Ses resultats sont en bon accord, d'une part avec ceux de la methode graphique des caracteristiques, d'autre part avec des enregistrements experimentaux. (auteur)

An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

Energy Technology Data Exchange (ETDEWEB)

Duan Shukai [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China); School of Electronic and Information Engineering, Southwest University, Chongqing 400715 (China)], E-mail: duansk@swu.edu.cn; Liao Xiaofeng [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China)], E-mail: xfliao@cqu.edu.cn

2007-09-10

A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments.

Analysis of electronic circuits using digital computers

International Nuclear Information System (INIS)

Tapu, C.

1968-01-01

Various programmes have been proposed for studying electronic circuits with the help of computers. It is shown here how it possible to use the programme ECAP, developed by I.B.M., for studying the behaviour of an operational amplifier from different point of view: direct current, alternating current and transient state analysis, optimisation of the gain in open loop, study of the reliability. (author) [fr

Synchronization circuit for shaping electron beam picosecond pulses

International Nuclear Information System (INIS)

Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.

1985-01-01

A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes

Non-noise instabilities in oscilloscope trigger circuits

International Nuclear Information System (INIS)

Burd, Aleksander

2011-01-01

The paper discusses two phenomena called tremor, which result in incorrect operation of the oscilloscope trigger circuits. Both of them change delays introduced by the trigger circuit, resulting in horizontal shifts of traces on the screen, but the origins of the two phenomena are different. Both kinds of tremors in the oscilloscope trigger circuits produce images on the screen, which often are similar to those resulting from the noise jitter. Hence, limited knowledge of tremor may be a source of improper interpretation of the oscilloscope measurements. On the other hand tremor can be considered as a different approach to the problem of flip-flop circuit's metastability

CHEETAH: circuit-switched high-speed end-to-end transport architecture

Science.gov (United States)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

A programmable artificial retina

International Nuclear Information System (INIS)

Bernard, T.M.; Zavidovique, B.Y.; Devos, F.J.

1993-01-01

An artificial retina is a device that intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environments and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare Boolean processors with halftoning facilities might be used, providing versatility from programmability. By setting the pixel memory size to 3 b, the authors have demonstrated both the technological practicality and the computational efficiency of this programmable Boolean retina concept. Using semi-static shifting structures together with some interaction circuitry, a minimal retina Boolean processor can be built with less than 30 transistors and controlled by as few as 6 global clock signals. The successful design, integration, and test of such a 65x76 Boolean retina on a 50-mm 2 CMOS 2-μm circuit are presented

Optically controllable molecular logic circuits

International Nuclear Information System (INIS)

Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

2015-01-01

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

Programmable full-adder computations in communicating three-dimensional cell cultures.

Science.gov (United States)

Ausländer, David; Ausländer, Simon; Pierrat, Xavier; Hellmann, Leon; Rachid, Leila; Fussenegger, Martin

2018-01-01

Synthetic biologists have advanced the design of trigger-inducible gene switches and their assembly into input-programmable circuits that enable engineered human cells to perform arithmetic calculations reminiscent of electronic circuits. By designing a versatile plug-and-play molecular-computation platform, we have engineered nine different cell populations with genetic programs, each of which encodes a defined computational instruction. When assembled into 3D cultures, these engineered cell consortia execute programmable multicellular full-adder logics in response to three trigger compounds.

Updating Procedures Can Reorganize the Neural Circuit Supporting a Fear Memory.

Science.gov (United States)

Kwapis, Janine L; Jarome, Timothy J; Ferrara, Nicole C; Helmstetter, Fred J

2017-07-01

Established memories undergo a period of vulnerability following retrieval, a process termed 'reconsolidation.' Recent work has shown that the hypothetical process of reconsolidation is only triggered when new information is presented during retrieval, suggesting that this process may allow existing memories to be modified. Reconsolidation has received increasing attention as a possible therapeutic target for treating disorders that stem from traumatic memories, yet little is known about how this process changes the original memory. In particular, it is unknown whether reconsolidation can reorganize the neural circuit supporting an existing memory after that memory is modified with new information. Here, we show that trace fear memory undergoes a protein synthesis-dependent reconsolidation process following exposure to a single updating trial of delay conditioning. Further, this reconsolidation-dependent updating process appears to reorganize the neural circuit supporting the trace-trained memory, so that it better reflects the circuit supporting delay fear. Specifically, after a trace-to-delay update session, the amygdala is now required for extinction of the updated memory but the retrosplenial cortex is no longer required for retrieval. These results suggest that updating procedures could be used to force a complex, poorly defined memory circuit to rely on a better-defined neural circuit that may be more amenable to behavioral or pharmacological manipulation. This is the first evidence that exposure to new information can fundamentally reorganize the neural circuit supporting an existing memory.

Flexible programmable logic module

Science.gov (United States)

Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

2001-01-01

The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

Optical programmable Boolean logic unit.

Science.gov (United States)

Chattopadhyay, Tanay

2011-11-10

Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.

High-explosive-driven delay line pulse generator

International Nuclear Information System (INIS)

Shearer, J.W.

1982-01-01

The inclusion of a delay line circuit into the design of a high-explosive-driven generator shortens the time constant of the output pulse. After a brief review of generator concepts and previously described pulse-shortening methods, a geometry is presented which incorporates delay line circuit techcniques into a coil generator. The circuit constants are adjusted to match the velocity of the generated electromagnetic wave to the detonation velocity of the high explosive. The proposed generator can be modeled by adding a variable inductance term to the telegrapher's equation. A particular solution of this equation is useful for exploring the operational parameters of the generator. The duration of the electromagnetic pulse equals the radial expansion time of the high-explosive-driven armature until it strikes the coil. Because the impedance of the generator is a constant, the current multiplication factor is limited only by nonlinear effects such as voltage breakdown, diffusion, and compression at high energies

arXiv A Programmable Delay Design for the sTGC Detector at the Upgraded New Small Wheel of the ATLAS Muon Spectrometer

CERN Document Server

INSPIRE-00225390; Guan, Liang; Chapman, John W; Zhou, Bing; Zhu, Junjie

2017-11-01

We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ∼ 3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. The approach is adaptable to other applications with similar phase shifting requirements. In addition, the design is resource efficient and is suitable for cost-effective digital implementation with a large number of channels.

Coplanar strips for Josephson voltage standard circuits

International Nuclear Information System (INIS)

Schubert, M.; May, T.; Wende, G.; Fritzsch, L.; Meyer, H.-G.

2001-01-01

We present a microwave circuit for Josephson voltage standards. Here, the Josephson junctions are integrated in a microwave transmission line designed as coplanar strips (CPS). The new layout offers the possibility of achieving a higher scale of integration and to considerably simplify the fabrication technology. The characteristic impedance of the CPS is about 50 Ω, and this should be of interest for programmable Josephson voltage standard circuits with SNS or SINIS junctions. To demonstrate the function of the microwave circuit design, conventional 10 V Josephson voltage standard circuits with 17000 Nb/AlO x /Nb junctions were prepared and tested. Stable Shapiro steps at the 10 V level were generated. Furthermore, arrays of 1400 SINIS junctions in this microwave layout exhibited first-order Shapiro steps. Copyright 2001 American Institute of Physics

Global chaos synchronization with channel time-delay

International Nuclear Information System (INIS)

Jiang Guoping; Zheng Weixing; Chen Guanrong

2004-01-01

This paper addresses a practical issue in chaos synchronization where there is a time-delay in the receiver as compared with the transmitter. A new synchronization scheme and a general criterion for global chaos synchronization are proposed and developed from the approach of unidirectional linear error feedback coupling with time-delay. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criterion under which the global chaos synchronization of the time-delay coupled systems is achieved

A Quantized Analog Delay for an ir-UWB Quadrature Downconversion Autocorrelation Receiver

NARCIS (Netherlands)

Bagga, S.; Zhang, L.; Serdijn, W.A.; Long, J.R.; Busking, E.B.

2005-01-01

A quantized analog delay is designed as a requirement for the autocorrelation function in the quadrature downconversion autocorrelation receiver (QDAR). The quantized analog delay is comprised of a quantizer, multiple binary delay lines and an adder circuit. Being the foremost element, the quantizer

Delay 25 an ASIC for timing adjustment in LHC

NARCIS (Netherlands)

Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.

A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Shikha Panwar

2014-01-01

Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

Multiwire proportional counter (lecture by an electromagnetic delay line)

International Nuclear Information System (INIS)

Bruere-Dawson, R.

1989-01-01

For track localisation of ionizing particles with multiwire proportional chamber, an electronic chain including amplifying, shaping and memorizing circuits is required for each wire. In order to lower the cost of this type of detector, an electromagnetic delay line is proposed among various possibilities. In this paper, different coupling modes between chamber and delay line are studied with their respective advantages. The realization of one meter long delay line with a unit delay time of 15 ns per cm is also presented [fr

Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

Science.gov (United States)

Abedini-Nassab, Roozbeh

Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into

Estimating Delays In ASIC's

Science.gov (United States)

Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

1994-01-01

Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

Delay line clipping in a scintillation camera system

International Nuclear Information System (INIS)

Hatch, K.F.

1979-01-01

The present invention provides a novel base line restoring circuit and a novel delay line clipping circuit in a scintillation camera system. Single and double delay line clipped signal waveforms are generated for increasing the operational frequency and fidelity of data detection of the camera system by base line distortion such as undershooting, overshooting, and capacitive build-up. The camera system includes a set of photomultiplier tubes and associated amplifiers which generate sequences of pulses. These pulses are pulse-height analyzed for detecting a scintillation having an energy level which falls within a predetermined energy range. Data pulses are combined to provide coordinates and energy of photopeak events. The amplifiers are biassed out of saturation over all ranges of pulse energy level and count rate. Single delay line clipping circuitry is provided for narrowing the pulse width of the decaying electrical data pulses which increase operating speed without the occurrence of data loss. (JTA)

The review of radiation effects of γ total dose in CMOS circuits

International Nuclear Information System (INIS)

Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

1992-01-01

Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

Circuit, especially for digital nuclear gyroscope systems

International Nuclear Information System (INIS)

Lowdenslager, J.R.

1974-01-01

The circuit with at least one or two spin generator shows a digital phase synchronizing loop in solid-state construction without movable mechanical parts. It is stable, may be turned in one direction any number of times without saturation, and also remains phase-synchronized when input signals are turned off. For this purpose, crystal oscillators with certain resonance frequencies are used. The spin generators are coupled at the outled side with filtering, squaring, and differential connections generating control impulses synchronous to the spin generators. Step divider circuits are connected to the oscillators, which act upon flip-flop registers. This is controlled by the filtering, squaring, and differential connections. Furthermore, field proportional control circuits with registers, advancing and delay circuits are provided, the registers being connected at the outlet side with digital adders and subtractors. The digital adder serves inertial-related purposes. (DG) [de

4-channel time delayed pulse generator

International Nuclear Information System (INIS)

Wetzel, L.F.S.; Rossi, J.O.; Del Bosco, E.

1987-02-01

It is described the project of a 4-channel delayed pulse generator employed to trigger the plasma centrifuge experiment of the Laboratorio Associado de Plasmas. The circuit delivers pulses with amplitude of 15V, full width at half maximum of 50μs and rise time of 0.7μs. The maximum time delay is 100ms. There are two channels with a fine adjustment of 0-1ms. The system can be manually or automatically driven. (author) [pt

Thermal Aware Floorplanning Incorporating Temperature Dependent Wire Delay Estimation

DEFF Research Database (Denmark)

Winther, AndreasThor; Liu, Wei; Nannarelli, Alberto

2015-01-01

Temperature has a negative impact on metal resistance and thus wire delay. In state-of-the-art VLSI circuits, large thermal gradients usually exist due to the uneven distribution of heat sources. The difference in wire temperature can lead to performance mismatch because wires of the same length...... can have different delay. Traditional floorplanning algorithms use wirelength to estimate wire performance. In this work, we show that this does not always produce a design with the shortest delay and we propose a floorplanning algorithm taking into account temperature dependent wire delay as one...

A monolithic constant-fraction discriminator using distributed R-C delay-line shaping

International Nuclear Information System (INIS)

Simpson, M.L.; Young, G.R.; Xu, M.

1995-01-01

A monolithic, CMOS, constant-fraction discriminator (CFD) was fabricated in the Orbit Semiconductor, 1.2 μ N-well process. This circuit uses an on-chip, distributed, R-C delay-line to realize the constant-fraction shaping. The delay-line is constructed from a narrow, 500-μ serpentine layer of polysilicon above a wide, grounded, second layer of polysilicon. This R-C delay-line generates about 1.1 ns of delay for 5 ns risetime signals with a slope degradation of only ≅ 15% and an amplitude reduction of about 6.1%. The CFD also features an automatic walk adjustment. The entire circuit, including the delay line, has a 200 μ pitch and is 950 μ long. The walk for a 5 ns risetime signal was measured as ± 100 ps over the 100:1 dynamic range from -15 mV to -1.5 mV. to -1.5 V. The CFD consumes 15 mW

Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

Science.gov (United States)

Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

2017-11-20

A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

The programme 'fission product deposition' at the IRB of Juelich nuclear research centre

International Nuclear Information System (INIS)

Gottaut, H.; Iniotakis, N.; Malinowski, J.; Muenchow, K.H.; Sackmann, B.

1976-01-01

The transport and deposition behaviour of the non-gaseous fission and activation products in the primary circuit of HTR-type reactors determines the possibility of inspection and maintenance of single components of the primary circuit as well as the safety of the reactor in normal operation and during accidents. For the investigation of these problems, the programme 'fission product deposition' was started at Juelich nuclear research centre in 1969 in cooperation with a number of industrial firms. The programme covers in-pile and out-of-pile experiments, in which the HTR conditions are simulated as realistically as possible, as well as various laboratory experiments and extensive theoretical studies. It is the objective of this work to establish a realistic physical model and computer programme with which the transport and deposition of nuclides in the primary circuit of HTR reactors can be calculated in advance. A report is given on the experimental and theoretical studies carried out at the IRB of Juelich nuclear research centre. (orig./AK) [de

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Directory of Open Access Journals (Sweden)

Ravi S. P. Nair

2015-09-01

Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

Science.gov (United States)

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Set of CAMAC modules on the base of large integrated circuits for an accelerator synchronization system

International Nuclear Information System (INIS)

Glejbman, Eh.M.; Pilyar, N.V.

1986-01-01

Parameters of functional moduli in the CAMAC standard developed for accelerator synchronization system are presented. They comprise BZN-8K and BZ-8K digital delay circuits, timing circuit and pulse selection circuit. In every module 3 large integral circuits of KR 580 VI53 type programmed timer, circuits of the given system bus bar interface with bus bars of crate, circuits of data recording control, 2 peripheric storage devices, circuits of initial regime setting, input and output shapers, circuits of installation and removal of blocking in channels are used

A self-adjusting delay circuit for pixel read-out chips

International Nuclear Information System (INIS)

Raith, B.

1997-01-01

A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

Programme for test generation for combinatorial and sequential systems

International Nuclear Information System (INIS)

Tran Huy Hoan

1973-01-01

This research thesis reports the computer-assisted search for tests aimed at failure detection in combinatorial and sequential logic circuits. As he wants to deal with complex circuits with many modules such as those met in large scale integrated circuits (LSI), the author used propagation paths. He reports the development of a method which is valid for combinatorial systems and for several sequential circuits comprising elementary logic modules and JK and RS flip-flops. This method is developed on an IBM 360/91 computer in PL/1 language. The used memory space is limited and adjustable with respect to circuit dimension. Computing time is short when compared to that needed by other programmes. The solution is practical and efficient for failure test and localisation

REASONS FOR PATIENT DELAYS & HEALTH SYSTEM DELAYS FOR TUBERCULOSIS IN SOUTH INDIA

Directory of Open Access Journals (Sweden)

Kapil Goel

2011-12-01

Full Text Available Background: Globally, the burden of Tuberculosis is escalating. Early diagnosis and prompt initiation of tuberculosis treatment is essential for an effective tuberculosis control programme. Objectives: To study the self reported reasons for patient and health system (diagnosis & treatment delays in Tuberculosis patients. Methods: A community based cross sectional study was conducted among 98 new sputum positive TB cases aged > 15 years registered under RNTCP from Oct 2006 to June 2007 & receiving treatment under DOTS in Udupi taluk by interviewing them. Results: Total 98 patients were recruited and 68% were males. Out of 17 patients with patient delays, 82% felt that their symptoms were not severe, 71% felt that patient delay was due to lack of awareness and 71% did not take it seriously. Out of 86 patients with health system delays, 82.6% of patients mentioned that doctor has not advised for sputum examination, 76.7% of patients told that they first consulted a private doctor, 21% of them mentioned that doctor was unaware to diagnose TB. Conclusion: Symptoms not severe is the main reason for the patient delay and doctor didn’t advise for sputum examination is the main reason for health system delays.

New reactor safety circuit for low-power-level operation

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

1978-01-01

In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

Mitigating the Effects of Poverty and Crime: The Long-Term Effects of an Early Intervention Programme for Children Who Were Developmentally Delayed and Prenatally Exposed to Cocaine

Science.gov (United States)

Ullery, Mary Anne; Gonzalez, Antonio; Katz, Lynne

2016-01-01

This study explores the long-term impact on participation in the Linda Ray Intervention Program (LRIP) for children (n = 54) who were developmentally delayed and prenatally exposed to cocaine. By identifying a group of programme graduates from a high crime/high poverty neighbourhood in Miami-Dade County using ArcGIS 10.2 software, a…

Multiplier less high-speed squaring circuit for binary numbers

Science.gov (United States)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Multi parametric card to personal computers interface based in ispLSI1016 circuits

International Nuclear Information System (INIS)

Osorio Deliz, J.F.; Toledo Acosta, R.B.; Arista Romeu, E.

1997-01-01

It is described the design and principal characteristic of the interface circuit for a 16 bit multi parametric add on card for IBM or compatible microcomputer which content two communication channels of direct memory access and bidirectional between the card and the computer, an interrupt controller, a programmable address register, a default add res register of the card, a four channels multiplexer, as well as the decoder logic of the 80C186 and computer. The circuit was designed with two programmable logic devices ispL1016, which allowed drastically to diminish the quantity of utilized components and get a more flexible design in less time better characteristics

Stochastic Mesocortical Dynamics and Robustness of Working Memory during Delay-Period.

Directory of Open Access Journals (Sweden)

Melissa Reneaux

Full Text Available The role of prefronto-mesoprefrontal system in the dopaminergic modulation of working memory during delayed response tasks is well-known. Recently, a dynamical model of the closed-loop mesocortical circuit has been proposed which employs a deterministic framework to elucidate the system's behavior in a qualitative manner. Under natural conditions, noise emanating from various sources affects the circuit's functioning to a great extent. Accordingly in the present study, we reformulate the model into a stochastic framework and investigate its steady state properties in the presence of constant background noise during delay-period. From the steady state distribution, global potential landscape and signal-to-noise ratio are obtained which help in defining robustness of the circuit dynamics. This provides insight into the robustness of working memory during delay-period against its disruption due to background noise. The findings reveal that the global profile of circuit's robustness is predominantly governed by the level of D1 receptor activity and high D1 receptor stimulation favors the working memory-associated sustained-firing state over the spontaneous-activity state of the system. Moreover, the circuit's robustness is further fine-tuned by the levels of excitatory and inhibitory activities in a way such that the robustness of sustained-firing state exhibits an inverted-U shaped profile with respect to D1 receptor stimulation. It is predicted that the most robust working memory is formed possibly at a subtle ratio of the excitatory and inhibitory activities achieved at a critical level of D1 receptor stimulation. The study also paves a way to understand various cognitive deficits observed in old-age, acute stress and schizophrenia and suggests possible mechanistic routes to the working memory impairments based on the circuit's robustness profile.

Stochastic Mesocortical Dynamics and Robustness of Working Memory during Delay-Period.

Science.gov (United States)

Reneaux, Melissa; Gupta, Rahul; Karmeshu

2015-01-01

The role of prefronto-mesoprefrontal system in the dopaminergic modulation of working memory during delayed response tasks is well-known. Recently, a dynamical model of the closed-loop mesocortical circuit has been proposed which employs a deterministic framework to elucidate the system's behavior in a qualitative manner. Under natural conditions, noise emanating from various sources affects the circuit's functioning to a great extent. Accordingly in the present study, we reformulate the model into a stochastic framework and investigate its steady state properties in the presence of constant background noise during delay-period. From the steady state distribution, global potential landscape and signal-to-noise ratio are obtained which help in defining robustness of the circuit dynamics. This provides insight into the robustness of working memory during delay-period against its disruption due to background noise. The findings reveal that the global profile of circuit's robustness is predominantly governed by the level of D1 receptor activity and high D1 receptor stimulation favors the working memory-associated sustained-firing state over the spontaneous-activity state of the system. Moreover, the circuit's robustness is further fine-tuned by the levels of excitatory and inhibitory activities in a way such that the robustness of sustained-firing state exhibits an inverted-U shaped profile with respect to D1 receptor stimulation. It is predicted that the most robust working memory is formed possibly at a subtle ratio of the excitatory and inhibitory activities achieved at a critical level of D1 receptor stimulation. The study also paves a way to understand various cognitive deficits observed in old-age, acute stress and schizophrenia and suggests possible mechanistic routes to the working memory impairments based on the circuit's robustness profile.

Comparative Effects of Circuit Training Programme on Speed and ...

African Journals Online (AJOL)

Stratified random sampling technique was used to select 40 pre-menarceal and 40 postmenarcheal girls who were later randomly assigned to experimental and control groups. At the end of the training programme, 40 subjects completed the post training measurements, so there were 10 subjects in each of the four study ...

A current-mode multi-valued adder circuit for multi-operand addition

Science.gov (United States)

Cini, Ugur; Morgül, Avni

2011-06-01

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

Electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and graphical user interface platform for aviation industries training purposes

Science.gov (United States)

Burhan, I.; Azman, A. A.; Othman, R.

2016-10-01

An electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and Visual Basic (VB) platform is fabricated as a supporting tool to existing teaching and learning process, and to achieve the objectives and learning outcomes towards enhancing the student's knowledge and hands-on skill, especially in electro pneumatic devices. The existing learning process for electro pneumatic courses conducted in the classroom does not emphasize on simulation and complex practical aspects. VB is used as the platform for graphical user interface (GUI) while PIC as the interface circuit between the GUI and hardware of electro pneumatic apparatus. Fabrication of electro pneumatic trainer interfacing between PIC and VB has been designed and improved by involving multiple types of electro pneumatic apparatus such as linear drive, air motor, semi rotary motor, double acting cylinder and single acting cylinder. Newly fabricated electro pneumatic trainer microcontroller interface can be programmed and re-programmed for numerous combination of tasks. Based on the survey to 175 student participants, 97% of the respondents agreed that the newly fabricated trainer is user friendly, safe and attractive, and 96.8% of the respondents strongly agreed that there is improvement in knowledge development and also hands-on skill in their learning process. Furthermore, the Lab Practical Evaluation record has indicated that the respondents have improved their academic performance (hands-on skills) by an average of 23.5%.

High voltage generator circuit with low power and high efficiency applied in EEPROM

International Nuclear Information System (INIS)

Liu Yan; Zhang Shilin; Zhao Yiqiang

2012-01-01

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

Implementation of programmable logic controller for proposed new instrumentation and control system of RTP

International Nuclear Information System (INIS)

Mohd Khairulezwan Abdul Manan; Mohd Idris Taib; Mohd Dzul Aiman Aslan

2010-01-01

Reactor Monitoring System is one of very important part of Reactor Instrumentation and Control system. Current monitoring system is using analog system whereby all circuits are discrete circuit and all displays and indicators are not digitalized. The proposed new system will use using a Commercial Off-The-Shelf, state of the art, Supervisory Control and Data Acquisition system such as Programmable Logic Controller as well as Computer System. The implementations of Programmable Logic Controller are used for Data Acquisition System and as a sub-system for Computer System where all the activities involved are stored for operation record and report as well as use for research purposes. Programmable Logic Controller receives galvanised or optically isolated signal from Reactor Protection System. Programmable Logic Controller also receives signal from other parameters as a digital and analog input related to reactor system. (author)

Comparative Effects of Circuit Training Programme on Speed and ...

African Journals Online (AJOL)

cce

the end of the training programme, 40 subjects completed the post training ... Speed is the rate of motion or velocity of the body or any of his part (Wilmore, 1977). ... Bulugbe (1991) reported improvement in running speed as a result of interval training. ..... The pre-menarcheal girls showed higher power performance than the ...

A TDC integrated circuit for drift chamber readout

International Nuclear Information System (INIS)

Passaseo, M.; Petrolo, E.; Veneziano, S.

1995-01-01

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 μm CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.)

A TDC integrated circuit for drift chamber readout

Energy Technology Data Exchange (ETDEWEB)

Passaseo, M. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Petrolo, E. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Veneziano, S. [Istituto Nazionale di Fisica Nucleare, Rome (Italy)

1995-12-11

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 {mu}m CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.).

A deadtime reduction circuit for thermal neutron coincidence counters with Amptek preamplifiers

International Nuclear Information System (INIS)

Bourret, S.C.; Krick, M.S.

1994-01-01

We have developed a deadtime reduction circuit for thermal neutron coincidence counters using Amptek preamplifier/amplifier/discriminator circuits. The principle is to remove the overlap between the output pulses from the Amptek circuits by adding a derandomizer between the Amptek circuits and the shift-register coincidence electronics. We implemented the derandomizer as an Actel programmable logic array; the derandomizer board is small and can be mounted in the high-voltage junction box with the Amptek circuits, if desired. Up to 32 Amptek circuits can be used with one derandomizer. The derandomizer has seven outputs: four groups of eight inputs, two groups of 16 inputs, and one group of 32 inputs. We selected these groupings to facilitate detector ring-ratio measurements. The circuit was tested with the five-ring research multiplicity counter, which has five output signals-one for each ring. The counter's deadtime was reduced from 70 to 30 ns

Safety of steel vessel Magnox pressure circuits

International Nuclear Information System (INIS)

Stokoe, T.Y.; Bolton, C.J.; Heffer, P.J.H.

1991-01-01

The maintenance of pressure circuit integrity is fundamental to nuclear safety at the steel vessel Magnox stations. To confirm continued pressure circuit integrity the CEGB, as part of the Long Term Safety Review, has carried out extensive assessment and inspection in recent years. The assessment methods and inspection techniques employed are based on the most modern available. Reactor pressure vessel integrity is confirmed by a combination of arguments including safety factors inferred from the successful pre-service overpressure test, leak-before-break analysis and probabilistic assessment. In the case of other parts of the pressure circuits that are more accessible, comprising the boiler shells and interconnecting gas duct work, in-service inspection is a major element of the safety substantiation. The assessment and inspection techniques and the materials property data have been underpinned for many years by extensive research and development programmes and in-reactor monitoring of representative samples has also been undertaken. The paper summarises the work carried out to demonstrate the long term integrity of the Magnox pressure circuits and provides examples of the results obtained. (author)

Test and Diagnosis for Small-Delay Defects

CERN Document Server

Tehranipoor, Mohammad; Chakrabarty, Krishnendu

2012-01-01

This book introduces new techniques for detecting and diagnosing small-delay defects (SDD) in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise. This book presents new techniques and methodologies to improve overall SDD detection with very small pattern sets. These methods can result in pattern counts as low as a traditional 1-detect pattern set and long path sensitization and SDD detection similar to or even better than n-detect or timing-aware pattern sets. The important design parameters and pattern-induced noises such as process variations,power supply noise (PSN) and crosstalk are taken into account in the methodologies presented. A diagnostic flow is also presented to identify whether the failure is ...

The Prince Henry Hospital dementia caregivers' training programme.

Science.gov (United States)

Brodaty, H; Gresham, M; Luscombe, G

1997-02-01

To describe the theory, elements and practice of a successful caregiver training programme; and report the 8-year outcome. Prospective, randomized control trial and longitudinal follow-up over approximately 8 years. Psychiatry unit, general teaching hospital, Sydney, Australia. 96 persons less than 80 years old with mild to moderate dementia and their cohabiting caregivers. All patients received a 10-day structured memory retraining and activity programme. Caregivers in the immediate and wait-list caregiver training groups received a structured, residential, intensive 10-day training programme, boosted by follow-ups and telephone conferences over 12 months. Those in the wait-list group entered the programme after waiting 6 months. The third group of caregivers received 10 days' respite (while patients underwent their memory retraining programme) and 12 months booster sessions as for the other groups. Nursing home admission; time until patient death. 64% of patients whose caregivers were in the immediate training group, 53% of wait-list group patients and 70% of memory retraining patients had died. Nursing home admission had occurred in 79% of the immediate training, 83% of the delayed and 90% of the memory retraining group. Eight-year survival analysis indicated that patients whose caregivers received training stayed at home significantly longer (p = 0.037) and tended to live longer (p = 0.08). Caregiver training programmes demonstrably can delay institutionalization of people with dementia.

A new circuit for at-speed scan SoC testing

International Nuclear Information System (INIS)

Lin Wei; Shi Wenlong

2013-01-01

It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. (semiconductor integrated circuits)

Modeling and simulation of floating gate nanocrystal FET devices and circuits

Science.gov (United States)

Hasaneen, El-Sayed A. M.

nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Analytical and experimental study of two delay-coupled excitable units.

Science.gov (United States)

Weicker, Lionel; Erneux, Thomas; Keuninckx, Lars; Danckaert, Jan

2014-01-01

We investigate the onset of time-periodic oscillations for a system of two identical delay-coupled excitable (nonoscillatory) units. We first analyze these solutions by using asymptotic methods. The oscillations are described as relaxation oscillations exhibiting successive slow and fast changes. The analysis highlights the determinant role of the delay during the fast transition layers. We then study experimentally a system of two coupled electronic circuits that is modeled mathematically by the same delay differential equations. We obtain quantitative agreements between analytical and experimental bifurcation diagrams.

Data readout system utilizing photonic integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

2013-10-11

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Computer programmes of the Power Research Institute for the analysis of processes in the primary coolant circuit and in the containment of a WWER plant in a loss-of-coolant accident

International Nuclear Information System (INIS)

Misak, J.

1976-01-01

A brief description is given of computer programmes for the analysis of loss-of-coolant accidents (LOCA) in WWER type reactors. The LENKA programme is intended for the thermal and hydraulic analysis of the consequences of such accidents in the primary coolant circuit. The SICHTA programme is intended for the detailed calculation of the time dependence of the axial and radial distribution of heat in fuel rods from steady-state to the flooding of the core. CHEMLOC is intended for the analysis of the heat history of the core and the extent of chemical reactions in LOCA when the emergency core cooling system is not operating. The TRACO I is intended for the analysis of the initial stage of the transient process in a full-pressure containment after LOCA (the computation of the time and spatial dependences of pressures and temperatures). TRACO III is intended for the computation of the long-term time dependence of pressure and temperature in the full-pressure containment after LOCA. (B.S.)

Programmable dc motor controller

Science.gov (United States)

Hopwood, J. E.

1982-11-01

A portable programmable dc motor controller, with features not available on commercial instruments was developed for controlling fixtures during welding processes. The controller can be used to drive any dc motor having tachometer feedback and motor requirements not exceeding 30 volts, 3 amperes. Among the controller's features are delayed start time, upslope time, speed, and downslope time.

Microcontroller based Integrated Circuit Tester

OpenAIRE

Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

2015-01-01

The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

G(sup 4)FET Implementations of Some Logic Circuits

Science.gov (United States)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

Predicting the behavior of microfluidic circuits made from discrete elements

Science.gov (United States)

Bhargava, Krisna C.; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah

2015-10-01

Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand.

Predicting the behavior of microfluidic circuits made from discrete elements.

Science.gov (United States)

Bhargava, Krisna C; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah

2015-10-30

Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand.

The design of programme-controlled gain and linear pulse amplifier

International Nuclear Information System (INIS)

Guan Xuemei; Chen Chunkai; Northeast Normal Univ., Changchun; Qiao Shuang; Zhou Chuansheng

2006-01-01

The authors have designed a kind of new-style programme-controlled gain and linear pulse amplifier with accurate gausses of CR-RC-CR shaping circuit structure. The use of non-volatile digital electric potential device and accurate operational amplifier makes the circuit structure simple greatly, makes the ability stronger that resists assault. It can realize multistage gain in succession and make the drift of temperature low and make the linearity of pulse well. (authors)

WHO Parents Skills Training (PST) programme for children with developmental disorders and delays delivered by Family Volunteers in rural Pakistan: study protocol for effectiveness implementation hybrid cluster randomized controlled trial.

Science.gov (United States)

Hamdani, S U; Akhtar, P; Zill-E-Huma; Nazir, H; Minhas, F A; Sikander, S; Wang, D; Servilli, C; Rahman, A

2017-01-01

Development disorders and delays are recognised as a public health priority and included in the WHO mental health gap action programme (mhGAP). Parents Skills Training (PST) is recommended as a key intervention for such conditions under the WHO mhGAP intervention guide. However, sustainable and scalable delivery of such evidence based interventions remains a challenge. This study aims to evaluate the effectiveness and scaled-up implementation of locally adapted WHO PST programme delivered by family volunteers in rural Pakistan. The study is a two arm single-blind effectiveness implementation-hybrid cluster randomised controlled trial. WHO PST programme will be delivered by 'family volunteers' to the caregivers of children with developmental disorders and delays in community-based settings. The intervention consists of the WHO PST along with the WHO mhGAP intervention for developmental disorders adapted for delivery using the android application on a tablet device. A total of 540 parent-child dyads will be recruited from 30 clusters. The primary outcome is child's functioning, measured by WHO Disability Assessment Schedule - child version (WHODAS-Child) at 6 months post intervention. Secondary outcomes include children's social communication and joint engagement with their caregiver, social emotional well-being, parental health related quality of life, family empowerment and stigmatizing experiences. Mixed method will be used to collect data on implementation outcomes. Trial has been retrospectively registered at ClinicalTrials.gov (NCT02792894). This study addresses implementation challenges in the real world by incorporating evidence-based intervention strategies with social, technological and business innovations. If proven effective, the study will contribute to scaled-up implementation of evidence-based packages for public mental health in low resource settings. Registered with ClinicalTrials.gov as Family Networks (FaNs) for Children with Developmental

Technology CAD for germanium CMOS circuit

Energy Technology Data Exchange (ETDEWEB)

Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

2006-12-15

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

Technology CAD for germanium CMOS circuit

International Nuclear Information System (INIS)

Saha, A.R.; Maiti, C.K.

2006-01-01

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

The primary circuit of the dragon high temperature reactor experiment

International Nuclear Information System (INIS)

Simon, R.

2005-01-01

The 20 MWth Dragon Reactor Experiment was the first HTGR (High Temperature Gas-cooled Reactor) with coated particle fuel. Its purpose was to test fuel and materials for the High Temperature Reactor programmes pursued in Europe 40 years ago. This paper describes the design and construction of the primary (helium) circuit. It summarizes the main design objectives, lists the performance data and explains the flow paths of the heat removal and helium purification systems. The principal circuit accidents postulated are discussed and the choice of the main construction materials is given. (author)

Synthesis of energy-efficient FSMs implemented in PLD circuits

Science.gov (United States)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Basic Guidelines for Application of Performance Standards to Commissioning of DCS Digital Circuits

Science.gov (United States)

1992-06-01

V6Z2J7 Canada Gustavo A. Cubas E. 1 Engineered Systems, Inc 2 Seccion De Transmission ATTN: Mr. David Gilfillan Direccion De Ingenieria Y Proyectos 14775...buffering, and and filter delay (for a voice circuit). Propagation delay is independent of data rate, while buffering delay is inversely proportional to...Complexe Des Jardins, 15th Fl. 171 N. Covington Drive 75 Rene Levesque West Bloomingdale, IL 60108 Montreal, PG H2Z Canada DISTRIBUTION LIST Department

Management of delayed nuclear power plant projects

Energy Technology Data Exchange (ETDEWEB)

NONE

1999-09-01

According to the available information at the IAEA PRIS (Power Reactor Information System) at the end of 1998 there were more than 40 nuclear power plant projects with delays of five or more years with respect to the originally scheduled commercial operation. The degree of conformance with original construction schedules showed large variations due to several issues, including financial, economic and public opinion factors. Taking into account the number of projects with several years delay in their original schedules, it was considered useful to identify the subject areas where exchange of experience among Member States would be mutually beneficial in identification of problems and development of guidance for successful management of the completion of these delayed projects. A joint programme of the IAEA Departments of Nuclear Energy (Nuclear Power Engineering Section) and Technical Co-operation (Europe Section, with additional support from the Latin America and West Asia Sections) was set up during the period 1997-1998. The specific aim of the programme was to provide assistance in the management of delayed nuclear power plants regarding measures to maintain readiness for resuming the project implementation schedule when the conditions permit. The integration of IAEA interdepartmental resources enabled the participation of 53 experts from 14 Member States resulting in a wider exchange of experience and dissemination of guidance. Under the framework of the joint programme, senior managers directly responsible for delayed nuclear power plant projects identified several issues or problem areas that needed to be addressed and guidance on management be provided. A work plan for the development of several working documents, addressing the different issues, was established. Subsequently these documents were merged into a single one to produce the present publication. This publication provides information and practical examples on necessary management actions to preserve

Management of delayed nuclear power plant projects

International Nuclear Information System (INIS)

1999-09-01

According to the available information at the IAEA PRIS (Power Reactor Information System) at the end of 1998 there were more than 40 nuclear power plant projects with delays of five or more years with respect to the originally scheduled commercial operation. The degree of conformance with original construction schedules showed large variations due to several issues, including financial, economic and public opinion factors. Taking into account the number of projects with several years delay in their original schedules, it was considered useful to identify the subject areas where exchange of experience among Member States would be mutually beneficial in identification of problems and development of guidance for successful management of the completion of these delayed projects. A joint programme of the IAEA Departments of Nuclear Energy (Nuclear Power Engineering Section) and Technical Co-operation (Europe Section, with additional support from the Latin America and West Asia Sections) was set up during the period 1997-1998. The specific aim of the programme was to provide assistance in the management of delayed nuclear power plants regarding measures to maintain readiness for resuming the project implementation schedule when the conditions permit. The integration of IAEA interdepartmental resources enabled the participation of 53 experts from 14 Member States resulting in a wider exchange of experience and dissemination of guidance. Under the framework of the joint programme, senior managers directly responsible for delayed nuclear power plant projects identified several issues or problem areas that needed to be addressed and guidance on management be provided. A work plan for the development of several working documents, addressing the different issues, was established. Subsequently these documents were merged into a single one to produce the present publication. This publication provides information and practical examples on necessary management actions to preserve

Generalized synchronization-based multiparameter estimation in modulated time-delayed systems

Science.gov (United States)

Ghosh, Dibakar; Bhattacharyya, Bidyut K.

2011-09-01

We propose a nonlinear active observer based generalized synchronization scheme for multiparameter estimation in time-delayed systems with periodic time delay. A sufficient condition for parameter estimation is derived using Krasovskii-Lyapunov theory. The suggested tool proves to be globally and asymptotically stable by means of Krasovskii-Lyapunov method. With this effective method, parameter identification and generalized synchronization of modulated time-delayed systems with all the system parameters unknown, can be achieved simultaneously. We restrict our study for multiple parameter estimation in modulated time-delayed systems with single state variable only. Theoretical proof and numerical simulation demonstrate the effectiveness and feasibility of the proposed technique. The block diagram of electronic circuit for multiple time delay system shows that the method is easily applicable in practical communication problems.

Superconducting flux flow digital circuits

International Nuclear Information System (INIS)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.

1993-01-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic

Design and analysis of a dual mode CMOS field programmable analog array

International Nuclear Information System (INIS)

Cheng Xiaoyan; Yang Haigang; Yin Tao; Wu Qisong; Zhang Hongfeng; Liu Fei

2014-01-01

This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. (semiconductor integrated circuits)

Programmable Baseband Filter for Multistandard Mobile Phones

DEFF Research Database (Denmark)

Jensen, Rasmus Glarborg; Christensen, Kåre Tais; Bruun, Erik

2003-01-01

of the input transconductor. The entire filter consumes between 2.5 mW and 7.5 mW, depending on the desired noise performance. It is implemented in a standard 0.25 mum CMOS process. A test circuit has been developed and fabricated and measurements show that both the required programmability and the required...

Effect of a Diagram on Primary Students' Understanding About Electric Circuits

Science.gov (United States)

Preston, Christine Margaret

2017-09-01

This article reports on the effect of using a diagram to develop primary students' conceptual understanding about electric circuits. Diagrammatic representations of electric circuits are used for teaching and assessment despite the absence of research on their pedagogical effectiveness with young learners. Individual interviews were used to closely analyse Years 3 and 5 (8-11-year-old) students' explanations about electric circuits. Data was collected from 20 students in the same school providing pre-, post- and delayed post-test dialogue. Students' thinking about electric circuits and changes in their explanations provide insights into the role of diagrams in understanding science concepts. Findings indicate that diagram interaction positively enhanced understanding, challenged non-scientific views and promoted scientific models of electric circuits. Differences in students' understanding about electric circuits were influenced by prior knowledge, meta-conceptual awareness and diagram conventions including a stylistic feature of the diagram used. A significant finding that students' conceptual models of electric circuits were energy rather than current based has implications for electricity instruction at the primary level.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

Science.gov (United States)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

Science.gov (United States)

Yuan, S. C.

2008-11-01

We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

Installations having pressurised fluid circuits

International Nuclear Information System (INIS)

Rigg, S.; Grant, J.

1977-01-01

Reference is made to nuclear installations having pressurised coolant flow circuits. Breaches in such circuits may quickly result in much damage to the plant. Devices such as non-return valves, orifice plates, and automatically operated shut-off valves have been provided to prevent or reduce fluid flow through a breached pipe line, but such devices have several disadvantages; they may present large restrictions to normal flow of coolant, and may depend on the operation of ancillary equipment, with consequent delay in bringing them into operation in an emergency. Other expedients that have been adopted to prevent or reduce reverse flow through an upstream breach comprise various forms of hydraulic counter flow brakes. The arrangement described has at least one variable fluid brake comprising a fluidic device connected into a duct in the pressurised circuit, the device having an inlet, an outlet, a vortex chamber between the inlet and outlet, a control jet for introducing fluid into the vortex chamber, connections communicating the inlet and the outlet into one part of the circuit and the control jet into another region at a complementary pressure so that, in the event of a breach in the circuit in one region, fluid passes from the other region to enter the vortex chamber to stimulate pressure to create a flow restricting vortex in the chamber that reduces flow through the breach. The system finds particular application to stream generating pressure tube reactors, such as the steam generating heavy water reactor at UKAEA, Winfrith. (U.K.)

Synthesis for robust synchronization of chaotic systems under output feedback control with multiple random delays

International Nuclear Information System (INIS)

Wen Guilin; Wang Qingguo; Lin Chong; Han Xu; Li Guangyao

2006-01-01

Synchronization under output feedback control with multiple random time delays is studied, using the paradigm in nonlinear physics-Chua's circuit. Compared with other synchronization control methods, output feedback control with multiple random delay is superior for a realistic synchronization application to secure communications. Sufficient condition for global stability of delay-dependent synchronization is established based on the LMI technique. Numerical simulations fully support the analytical approach, in spite of the random delays

Refractory silicides for integrated circuits

International Nuclear Information System (INIS)

Murarka, S.P.

1980-01-01

Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

Approaching the Processes in the Generator Circuit Breaker at Disconnection through Sustainability Concepts

Directory of Open Access Journals (Sweden)

Carmen A. Bulucea

2013-03-01

Full Text Available Nowadays, the electric connection circuits of power plants (based on fossil fuels as well as renewable sources entail generator circuit-breakers (GCBs at the generator terminals, since the presence of that electric equipment offers many advantages related to the sustainability of a power plant. In an alternating current (a.c. circuit the interruption of a short circuit is performed by the circuit-breaker at the natural passing through zero of the short-circuit current. During the current interruption, an electric arc is generated between the opened contacts of the circuit-breaker. This arc must be cooled and extinguished in a controlled way. Since the synchronous generator stator can flow via highly asymmetrical short-circuit currents, the phenomena which occur in the case of short-circuit currents interruption determine the main stresses of the generator circuit-breaker; the current interruption requirements of a GCB are significantly higher than for the distribution network circuit breakers. For shedding light on the proper moment when the generator circuit-breaker must operate, using the space phasor of the short-circuit currents, the time expression to the first zero passing of the short-circuit current is determined. Here, the manner is investigated in which various factors influence the delay of the zero passing of the short-circuit current. It is shown that the delay time is influenced by the synchronous machine parameters and by the load conditions which precede the short-circuit. Numerical simulations were conducted of the asymmetrical currents in the case of the sudden three-phase short circuit at the terminals of synchronous generators. Further in this study it is emphasized that although the phenomena produced in the electric arc at the terminals of the circuit-breaker are complicated and not completely explained, the concept of exergy is useful in understanding the physical phenomena. The article points out that just after the short-circuit

Nano/CMOS architectures using a field-programmable nanowire interconnect

International Nuclear Information System (INIS)

Snider, Gregory S; Williams, R Stanley

2007-01-01

A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 x to 25 x), reduced power, slightly lower clock speeds, and high defect tolerance-an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires

Topological Acoustic Delay Line

Science.gov (United States)

Zhang, Zhiwang; Tian, Ye; Cheng, Ying; Wei, Qi; Liu, Xiaojun; Christensen, Johan

2018-03-01

Topological protected wave engineering in artificially structured media is at the frontier of ongoing metamaterials research that is inspired by quantum mechanics. Acoustic analogues of electronic topological insulators have recently led to a wealth of new opportunities in manipulating sound propagation with strikingly unconventional acoustic edge modes immune to backscattering. Earlier fabrications of topological insulators are characterized by an unreconfigurable geometry and a very narrow frequency response, which severely hinders the exploration and design of useful devices. Here we establish topologically protected sound in reconfigurable phononic crystals that can be switched on and off simply by rotating its three-legged "atoms" without altering the lattice structure. In particular, we engineer robust phase delay defects that take advantage of the ultrabroadband reflection-free sound propagation. Such topological delay lines serve as a paradigm in compact acoustic devices, interconnects, and electroacoustic integrated circuits.

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

A survival programme

International Nuclear Information System (INIS)

Vester, F.

1978-01-01

The book is a non-speculative information source on ecological problems and their possible solutions. It is a 'programme' from a twofold point of view: it determines political and scientific-technological objectives and it transfers knowledge by mental steps with techniques of programmed instruction. Thus emphasis is laid on detailed problems, especially by conscionsly challenged redundancies, and, on the other hand, a greater context is presented. Selected facts are examined under their different aspects, interactions and control circuits are described. Each chapter will speak for itself after the introduction has been read but is related to other chapters by cross references, illustrative material, a glossary and a comprehensive list of references. The 'Survival Programme' is a realistic and challenging discussion with the problem of 'Ecology in the Industrial Age'. It adresses scientists from various disciplines but also offers itself as a compendium to laymen in search of information, members of citizens initiatives and responsible representants of the political and industrial world. (orig./HP) [de

High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

CERN Document Server

Palchaudhuri, Ayan

2016-01-01

This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

Electron commutator on integrated circuits

International Nuclear Information System (INIS)

Demidenko, V.V.

1975-01-01

The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru

Photonic integrated circuits unveil crisis-induced intermittency.

Science.gov (United States)

Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

2016-09-19

We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

Logic delays of 5-μm resistor coupled Josephson logic

International Nuclear Information System (INIS)

Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

1982-01-01

Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

Gravitational Lens Time Delays Using Polarization Monitoring

Directory of Open Access Journals (Sweden)

Andrew Biggs

2017-11-01

Full Text Available Gravitational lens time delays provide a means of measuring the expansion of the Universe at high redshift (and therefore in the ‘Hubble flow’ that is independent of local calibrations. It was hoped that many of the radio lenses found in the JVAS/CLASS survey would yield time delays as these were selected to have flat spectra and are dominated by multiple compact components. However, despite extensive monitoring with the Very Large Array (VLA, time delays have only been measured for three of these systems (out of 22. We have begun a programme to reanalyse the existing VLA monitoring data with the goal of producing light curves in polarized flux and polarization position angle, either to improve delay measurements or to find delays for new sources. Here, we present preliminary results on the lens system B1600+434 which demonstrate the presence of correlated and substantial polarization variability in each image.

Study of the phase delay in the amplitude-modulated harmonic oscillator

International Nuclear Information System (INIS)

Krupska, Aldona; Krupski, Marcin

2003-01-01

The delayed response of a damped harmonic oscillator (RLC circuit) to a slow periodic disturbance is presented. This communication is supplementary to the paper published recently (Krupska et al 2001 Eur. J. Phys. 22 133-8)

Non-Destructive Investigation on Short Circuit Capability of Wind-Turbine-Scale IGBT Power Modules

DEFF Research Database (Denmark)

Wu, Rui; Iannuzzo, Francesco; Wang, Huai

2014-01-01

This paper presents a comprehensive investigation on the short circuit capability of wind-turbine-scale IGBT power modules by means of a 6 kA/1.1 kV non-destructive testing system. A Field Programmable Gate Array (FPGA) supervising unit is adpoted to achieve an accurate time control for short...... circuit test, which enables to define the driving signals with an accuracy of 10 ns. Thanks to the capability and the effectiveness of the constructed setup, oscillations appearing during short circuits of the new-generation 1.7 kV/1 kA IGBT power modules have been evidenced and characterized under...

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Carbon Nanotubes-Based Digitally Programmable Current Follower

Directory of Open Access Journals (Sweden)

S. K. Tripathi

2018-01-01

Full Text Available The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET’s parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.

Engineering embedded systems physics, programs, circuits

CERN Document Server

Hintenaus, Peter

2015-01-01

This is a textbook for graduate and final-year-undergraduate computer-science and electrical-engineering students interested in the hardware and software aspects of embedded and cyberphysical systems design. It is comprehensive and self-contained, covering everything from the basics to case-study implementation. Emphasis is placed on the physical nature of the problem domain and of the devices used. The reader is assumed to be familiar on a theoretical level with mathematical tools like ordinary differential equation and Fourier transforms. In this book these tools will be put to practical use. Engineering Embedded Systems begins by addressing basic material on signals and systems, before introducing to electronics. Treatment of digital electronics accentuating synchronous circuits and including high-speed effects proceeds to micro-controllers, digital signal processors and programmable logic. Peripheral units and decentralized networks are given due weight. The properties of analog circuits and devices like ...

Miniaturization of Josephson logic circuits

International Nuclear Information System (INIS)

Ko, H.; Van Duzer, T.

1985-01-01

The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements

Design and implementation of SFQ programmable clock generators

International Nuclear Information System (INIS)

Ito, M.; Nakajima, N.; Fujiwara, K.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

2004-01-01

We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the variable number of SFQ pulses according to its internal state. The PCG is composed of an SFQ ring oscillator, a control circuit which counts up the number of SFQ pulses and stops the operation of the ring oscillator, and a decoder which defines the initial state of the control circuit. The PCG can generate the variable number of SFQ pulses ranging from 2 to 2 N , where N is the number of T flip-flops in the control circuit. The oscillation frequency of the PCG is designed to be ranging from 6.2 to 18.8 GHz. In this study, we have implemented a PCG generating SFQ pulses ranging from 2 to 2 4 using a cell-based design methodology and confirmed its correct functionality

Damping Resonant Current in a Spark-Gap Trigger Circuit to Reduce Noise

Science.gov (United States)

2009-06-01

DAMPING RESONANT CURRENT IN A SPARK- GAP TRIGGER CIRCUIT TO REDUCE NOISE E. L. Ruden Air Force Research Laboratory, Directed Energy Directorate, AFRL...REPORT TYPE N/A 3. DATES COVERED - 4. TITLE AND SUBTITLE Damping Resonant Current In A Spark- Gap Trigger Circuit To Reduce Noise 5a...thereby triggering 2 after delay 0, is 1. Each of the two rail- gaps (represented by 2) is trig- gered to close after the spark- gap (1) in the

Review of programmable systems associated with Fermilab experiments

International Nuclear Information System (INIS)

Nash, T.

1981-05-01

The design and application of programmable systems for Fermilab experiments are reviewed. The high luminosity fixed target environment at Fermilab has been a very fertile ground for the development of sophisticated, powerful triggering systems. A few of these are integrated systems designed to be flexible and to have broad application. Many are dedicated triggers taking advantage of large scale integrated circuits to focus on the specific needs of one experiment. In addition, the data acquisition requirements of large detectors, existing and planned, are being met with programmable systems to process the data. Offline reconstruction of data places a very heavy load on large general purpose computers. This offers a potentially very fruitful area for new developments involving programmable dedicated systems. Some of the present thinking at Fermilab regarding offline reconstruction processors will be described

Optical reversible programmable Boolean logic unit.

Science.gov (United States)

Chattopadhyay, Tanay

2012-07-20

Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.

Industrial infrastructure for the Indian nuclear power programme

International Nuclear Information System (INIS)

Srinivasan, M.R.

1986-04-01

For the inception of the Indian nuclear power programme, great emphasis has been laid on development of comprehensive indigenous capability in design, construction and operation of nuclear power plants. The choice of the pressurised heavy water reactor as the mainline for India's first generation nuclear power stations fitted into this perspective. Apart from the inherent advantages of high neutron economy, low fuelling costs and high capacity factors, this system offered significant opportunities for manufacture and design of all the components within the country. The development of indigenous capability has not been without its problems, namely cost overruns and delays. The main causes for these delays have been the developmental nature of the jobs involving learning process and continued tightening of the quality control requirements. The strategy of development to be pursued by any country is naturally dependent upon the size of the programme it wishes to embark upon and the state of industrial infrastructure in the country. The Indian experience has demonstrated that for development of a comprehensive capability, it is necessary to have a well formulated reactor policy, a good inter-disciplinary R and D base, a good base of conventional industrial infrastructure, a comprehensive manpower development programme and an innovative management. It is hoped that this experience will be of benefit to other developing countries embarking on their own nuclear programme

Monitoring of timely and delayed vaccinations: a nation-wide registry-based study of Norwegian children aged < 2 years.

Science.gov (United States)

Riise, Øystein Rolandsen; Laake, Ida; Bergsaker, Marianne Adeleide Riise; Nøkleby, Hanne; Haugen, Inger Lise; Storsæter, Jann

2015-11-13

Delayed vaccinations increase the risk for vaccine preventable diseases (VPDs). Monitoring of delayed vaccinations by using a national immunisation registry has not been studied in countries recommending a two-dose (3 and 5 months of age) primary series of e.g., pertussis vaccine. Surveillance/monitoring of all vaccinations may improve vaccination programmes functioning. We obtained information from the Norwegian immunisation registry (SYSVAK) on all programme vaccinations received at age up to 730 days in children born in 2010 (n = 63,382). Timely vaccinations were received up to 7 days after the recommended age. Vaccinations were considered delayed if they were received more than one month after the recommended age in the schedule. In vaccinated children, timely administration of the subsequent three doses of pertussis and one dose of measles occurred in 73.8, 47.6, 53.6 and 43.5 % respectively. Delay for one or more programme vaccinations (diphtheria, tetanus, pertussis, polio, Haemophilus influenza type B, invasive pneumococcal disease, measles, mumps or rubella) was present in 28,336 (44.7 %) children. Among those who were delayed the mean duration was 139 days. The proportion of children that had vaccinations delayed differed among counties (range 37.4 %-57.8 %). Immigrant children were more frequently delayed 52.3 % vs. 43.1 %, RR 1.21 (95 % CI 1.19, 1.24). Children scheduled for vaccines in the summer holiday month (July) were more frequently delayed than others (1(st) dose pertussis vaccine 6.5 % vs. 3.9 % RR 1.65 (95 % CI 1.48, 1.85). Priming against pertussis (2(nd) dose), pneumococcal (2(nd) dose) and measles (1(st) dose) was delayed in 16.8, 18.6 and 29.3 % respectively. Vaccinations were frequently delayed. Delayed vaccinations differed among counties and occurred more frequently during the summer vacation (July) and in the immigrant population. Monitoring improves programme surveillance and may be used on an annual basis.

Fiber optic sensors for monitoring sodium circuits and power grid cables

Energy Technology Data Exchange (ETDEWEB)

Kasinathan, M.; Sosamma, S.; Pandian, C.; Vijayakumar, V.; Chandramouli, S.; Nashine, B. K.; Rao, C. B.; Murali, N.; Rajan, K. K.; Jayakumar, T. [IGCAR, Kalpakkam (India)

2011-07-01

At Kalpakkam, India, a programme on development of Raman Distributed Temperature sensor (RDTS) for Fast Breeder Reactors (FBR) application is undertaken. Leak detection in sodium circuits of FBR is critical for the safety and performance of the reactors. It is demonstrated that RDTS can be usefully employed in monitoring sodium circuits and in tracking the percolating sodium in case of any leak. Aluminum Conductor Steel Reinforced (ACSR) cable is commonly used as overhead power transmission cable in power grid. A second application demonstrates the suitability of using RDTS to monitor this transmission cable for any defect. (authors)

Fractional Delayer Utilizing Hermite Interpolation with Caratheodory Representation

Directory of Open Access Journals (Sweden)

Qiang DU

2018-04-01

Full Text Available Fractional delay is indispensable for many sorts of circuits and signal processing applications. Fractional delay filter (FDF utilizing Hermite interpolation with an analog differentiator is a straightforward way to delay discrete signals. This method has a low time-domain error, but a complicated sampling module than the Shannon sampling scheme. A simplified scheme, which is based on Shannon sampling and utilizing Hermite interpolation with a digital differentiator, will lead a much higher time-domain error when the signal frequency approaches the Nyquist rate. In this letter, we propose a novel fractional delayer utilizing Hermite interpolation with Caratheodory representation. The samples of differential signal are obtained by Caratheodory representation from the samples of the original signal only. So, only one sampler is needed and the sampling module is simple. Simulation results for four types of signals demonstrate that the proposed method has significantly higher interpolation accuracy than Hermite interpolation with digital differentiator.

Nanoeletromechanical switch and logic circuits formed therefrom

Science.gov (United States)

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Deep learning with coherent nanophotonic circuits

Science.gov (United States)

Shen, Yichen; Harris, Nicholas C.; Skirlo, Scott; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Sun, Xin; Zhao, Shijie; Larochelle, Hugo; Englund, Dirk; Soljačić, Marin

2017-07-01

Artificial neural networks are computational network models inspired by signal processing in the brain. These models have dramatically improved performance for many machine-learning tasks, including speech and image recognition. However, today's computing hardware is inefficient at implementing neural networks, in large part because much of it was designed for von Neumann computing schemes. Significant effort has been made towards developing electronic architectures tuned to implement artificial neural networks that exhibit improved computational speed and accuracy. Here, we propose a new architecture for a fully optical neural network that, in principle, could offer an enhancement in computational speed and power efficiency over state-of-the-art electronics for conventional inference tasks. We experimentally demonstrate the essential part of the concept using a programmable nanophotonic processor featuring a cascaded array of 56 programmable Mach-Zehnder interferometers in a silicon photonic integrated circuit and show its utility for vowel recognition.

Analysis of the effects of time delay in clock recovery circuits based on Phase-locked loops

DEFF Research Database (Denmark)

Zibar, Darko; Oxenløwe, Leif Katsuo; Clausen, Anders

2004-01-01

Influence of time delay in a balanced optical phase-locked loops (OPLL) with a proportional integrator (Pl) filter is investigated using a delayed differential equation (DDE) is investigated. The limitations, which a time delay imposes on the Pl filter bandwidth, at increasing values of loop gain...

Proposal for a fast, zero suppressing circuit for the digitization of analog pulses over long memory times

International Nuclear Information System (INIS)

Bourgeois, F.

1984-01-01

This report describes the design principles of a fast (100 MHz) time and pulse height digitizer that can record up to 15 analog pulses over 10-80 μs memory times. Unlike other triggered circuits prepulse samples are recorded without the help of an analog delay line. The low power requirements of the circuit as well as its fast read-out characteristics make it very attractive for detectors with many digitizing channels. Conventional circuits are described as a reference for the evaluation of this new design. An ECL 10 K implementation of the circuit is presented in the third section. (orig.)

Reliability Of A Novel Intracardiac Electrogram Method For AV And VV Delay Optimization And Comparability To Echocardiography Procedure For Determining Optimal Conduction Delays In CRT Patients

Directory of Open Access Journals (Sweden)

N Reinsch

2009-03-01

Full Text Available Background: Echocardiography is widely used to optimize CRT programming. A novel intracardiac electrogram method (IEGM was recently developed as an automated programmer-based method, designed to calculate optimal atrioventricular (AV and interventricular (VV delays and provide optimized delay values as an alternative to standard echocardiographic assessment.Objective: This study was aimed at determining the reliability of this new method. Furthermore the comparability of IEGM to existing echocardiographic parameters for determining optimal conduction delays was verified.Methods: Eleven patients (age 62.9± 8.7; 81% male; 73% ischemic, previously implanted with a cardiac resynchronisation therapy defibrillator (CRT-D underwent both echocardiographic and IEGM-based delay optimization.Results: Applying the IEGM method, concordance of three consecutively performed measurements was found in 3 (27% patients for AV delay and in 5 (45% patients for VV delay. Intra-individual variation between three measurements as assessed by the IEGM technique was up to 20 ms (AV: n=6; VV: n=4. E-wave, diastolic filling time and septal-to-lateral wall motion delay emerged as significantly different between the echo and IEGM optimization techniques (p < 0.05. The final AV delay setting was significantly different between both methods (echo: 126.4 ± 29.4 ms, IEGM: 183.6 ± 16.3 ms; p < 0.001; correlation: R = 0.573, p = 0.066. VV delay showed significant differences for optimized delays (echo: 46.4 ± 23.8 ms, IEGM: 10.9 ± 7.0 ms; p <0.01; correlation: R = -0.278, p = 0.407.Conclusion: The automated programmer-based IEGM-based method provides a simple and safe method to perform CRT optimization. However, the reliability of this method appears to be limited. Thus, it remains difficult for the examiner to determine the optimal hemodynamic settings. Additionally, as there was no correlation between the optimal AV- and VV-delays calculated by the IEGM method and the echo

Configuration and debug of field programmable gate arrays using MATLAB[reg)/SIMULINK[reg

International Nuclear Information System (INIS)

Grout, I; Ryan, J; O'Shea, T

2005-01-01

Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB[reg] model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB[reg] model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK[reg] model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use

Novel concept of TDI readout circuit for LWIR detector

Science.gov (United States)

Kim, Byunghyuck; Yoon, Nanyoung; Lee, Hee Chul; Kim, Choong-Ki

2000-07-01

Noise property is the prime consideration in readout circuit design. The output noise caused by the photon noise, which dominates total noise in BLIP detectors, is limited by the integration time that an element looks at a specific point in the scene. Large integration time leads to a low noise performance. Time-delay integration (TDI) is used to effectively increase the integration time and reduce the photon noise. However, it increases the number of dead pixels and requires large integration capacitors and low noise output stage of the readout circuit. In this paper, to solve these problems, we propose a new concept of readout circuit, which performs background suppression, cell-to-cell background current non-uniformity compensation, and dead pixel correction using memory, ADC, DAC, and current copier cell. In simulation results, comparing with the conventional TDI readout circuit, the integration capacitor size can be reduced to 1/5 and trans-impedance gain can be increased by five times. Therefore, the new TDI readout circuit does not require large area and low noise output stage. And the error of skimming current is less than 2%, and the fixed pattern noise induced by cell-to-cell background current variation is reduced to less than 1%.

Universal file processing program for field programmable integrated circuits

International Nuclear Information System (INIS)

Freytag, D.R.; Nelson, D.J.

1985-01-01

A computer program is presented that translates logic equations into promburner files (or the reverse) for programmable logic devices of various kinds, namely PROMs FPLAs, FPLSs and PALs. The program achieves flexibility through the use of a database containing detailed information about the devices to be programmed. New devices can thus be accommodated through simple extensions of the database. When writing logic equations, the user can define logic combinations of signals as new logic variables for use in subsequent equations. This procedure yields compact and transparent expressions for logic operations, thus reducing the chances for error. A logic simulation program is also provided so that an independent check of the design can be performed at the software level

Design and implementation of a programming circuit in radiation-hardened FPGA

International Nuclear Information System (INIS)

Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

2011-01-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

Design and implementation of a programming circuit in radiation-hardened FPGA

Science.gov (United States)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

A programmable Escherichia coli consortium via tunable symbiosis.

Directory of Open Access Journals (Sweden)

Alissa Kerner

Full Text Available Synthetic microbial consortia that can mimic natural systems have the potential to become a powerful biotechnology for various applications. One highly desirable feature of these consortia is that they can be precisely regulated. In this work we designed a programmable, symbiotic circuit that enables continuous tuning of the growth rate and composition of a synthetic consortium. We implemented our general design through the cross-feeding of tryptophan and tyrosine by two E. coli auxotrophs. By regulating the expression of genes related to the export or production of these amino acids, we were able to tune the metabolite exchanges and achieve a wide range of growth rates and strain ratios. In addition, by inverting the relationship of growth/ratio vs. inducer concentrations, we were able to "program" the co-culture for pre-specified attributes with the proper addition of inducing chemicals. This programmable proof-of-concept circuit or its variants can be applied to more complex systems where precise tuning of the consortium would facilitate the optimization of specific objectives, such as increasing the overall efficiency of microbial production of biofuels or pharmaceuticals.

A note on exponential convergence of neural networks with unbounded distributed delays

Energy Technology Data Exchange (ETDEWEB)

Chu Tianguang [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)]. E-mail: chutg@pku.edu.cn; Yang Haifeng [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)

2007-12-15

This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network.

A note on exponential convergence of neural networks with unbounded distributed delays

International Nuclear Information System (INIS)

Chu Tianguang; Yang Haifeng

2007-01-01

This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network

Radiofrequency spark chambers and delay line resonators

International Nuclear Information System (INIS)

Sayag, Jacques

1971-01-01

According to a suggestion of A. Kastler, a spark chamber was excited by an undamped radiofrequency pulse and tracks about 1 mm wide obtained; the result was interpreted by computation of the coefficients of electronic amplification and partial ambipolar diffusion. This work led us to the construction of a new fast triggering undamped wave-train generator of very high tension (patent taken out by the C.E.A. under the no.: EN 7 134 650 the 27.9.1971). Since this apparatus uses a resonant storage line, its design implied a precise knowledge of high impedance delay lines. The experimental radiofrequency spectra of the input impedance of opened or short-circuited lines were plotted completely and analysed by the circuits theory, new measuring methods were established, dispersion relations accurately checked and the equivalence of the formulas, within the third order, with theses of Debye's Dipolar Absorption demonstrated. General properties of Hilbert's transform were also investigated. From the experimental point of view, the electromagnetic energy storage process was extended to the case of a liquid nitrogen-immersed resonant delay line. The good behavior of the cryogenic experiment, where the main difficulty of icing was overcame by the construction of special electrodes, offers great promise for extrapolation to superconductivity. (author) [fr

The management of cardiovascular disease in the Netherlands: analysis of different programmes

Directory of Open Access Journals (Sweden)

Jane M. Cramm

2013-08-01

Full Text Available Background: Disease management programmes are increasingly used to improve the efficacy and effectiveness of chronic care delivery.But, disease management programme development and implementation is a complex undertaking that requires effective decision-making.Choices made in the earliest phases of programme development are crucial, as they ultimately impact costs, outcomes and sustainability. Methods: To increase our understanding of the choices that primary healthcare practices face when implementing such programmes and to stimulate successful implementation and sustainability, we compared the early implementation of eight cardiovascular disease management programmes initiated and managed by healthcare practices in various regions of the Netherlands. Using a mixed-methods design, we identified differences in and challenges to programme implementation in terms of context, patient characteristics, disease management level, healthcare utilisation costs, development costs and health-related quality of life. Results: Shifting to a multidisciplinary, patient-centred care pathway approach to disease management is demanding for organisations, professionals and patients, and is especially vulnerable when sustainable change is the goal. Funding is an important barrier to sustainable implementation of cardiovascular disease management programmes, although development costs of the individual programmes varied considerably in relation to the length of the development period. The large number of professionals involved in combination with duration of programme development was the largest cost drivers. While Information and Communication Technology systems to support the new care pathways did not directly contribute to higher costs, delays in implementation indirectly did. Conclusions: Developing and implementing cardiovascular disease management programmes is time-consuming and challenging. Multidisciplinary, patient-centred care demands multifaceted changes

The management of cardiovascular disease in the Netherlands: analysis of different programmes

Directory of Open Access Journals (Sweden)

Jane M. Cramm

2013-08-01

Full Text Available Background: Disease management programmes are increasingly used to improve the efficacy and effectiveness of chronic care delivery.But, disease management programme development and implementation is a complex undertaking that requires effective decision-making.Choices made in the earliest phases of programme development are crucial, as they ultimately impact costs, outcomes and sustainability.Methods: To increase our understanding of the choices that primary healthcare practices face when implementing such programmes and to stimulate successful implementation and sustainability, we compared the early implementation of eight cardiovascular disease management programmes initiated and managed by healthcare practices in various regions of the Netherlands. Using a mixed-methods design, we identified differences in and challenges to programme implementation in terms of context, patient characteristics, disease management level, healthcare utilisation costs, development costs and health-related quality of life.Results: Shifting to a multidisciplinary, patient-centred care pathway approach to disease management is demanding for organisations, professionals and patients, and is especially vulnerable when sustainable change is the goal. Funding is an important barrier to sustainable implementation of cardiovascular disease management programmes, although development costs of the individual programmes varied considerably in relation to the length of the development period. The large number of professionals involved in combination with duration of programme development was the largest cost drivers. While Information and Communication Technology systems to support the new care pathways did not directly contribute to higher costs, delays in implementation indirectly did.Conclusions: Developing and implementing cardiovascular disease management programmes is time-consuming and challenging. Multidisciplinary, patient-centred care demands multifaceted changes in

The management of cardiovascular disease in the Netherlands: analysis of different programmes.

Science.gov (United States)

Cramm, Jane M; Tsiachristas, Apostolos; Walters, Bethany H; Adams, Samantha A; Bal, Roland; Huijsman, Robbert; Rutten-Van Mölken, Maureen P M H; Nieboer, Anna P

2013-01-01

Disease management programmes are increasingly used to improve the efficacy and effectiveness of chronic care delivery. But, disease management programme development and implementation is a complex undertaking that requires effective decision-making. Choices made in the earliest phases of programme development are crucial, as they ultimately impact costs, outcomes and sustainability. To increase our understanding of the choices that primary healthcare practices face when implementing such programmes and to stimulate successful implementation and sustainability, we compared the early implementation of eight cardiovascular disease management programmes initiated and managed by healthcare practices in various regions of the Netherlands. Using a mixed-methods design, we identified differences in and challenges to programme implementation in terms of context, patient characteristics, disease management level, healthcare utilisation costs, development costs and health-related quality of life. Shifting to a multidisciplinary, patient-centred care pathway approach to disease management is demanding for organisations, professionals and patients, and is especially vulnerable when sustainable change is the goal. Funding is an important barrier to sustainable implementation of cardiovascular disease management programmes, although development costs of the individual programmes varied considerably in relation to the length of the development period. The large number of professionals involved in combination with duration of programme development was the largest cost drivers. While Information and Communication Technology systems to support the new care pathways did not directly contribute to higher costs, delays in implementation indirectly did. Developing and implementing cardiovascular disease management programmes is time-consuming and challenging. Multidisciplinary, patient-centred care demands multifaceted changes in routine care. As care pathways become more complex, they

The management of cardiovascular disease in the Netherlands: analysis of different programmes

Science.gov (United States)

Cramm, Jane M.; Tsiachristas, Apostolos; Walters, Bethany H.; Adams, Samantha A.; Bal, Roland; Huijsman, Robbert; Rutten-Van Mölken, Maureen P.M.H.; Nieboer, Anna P.

2013-01-01

Background Disease management programmes are increasingly used to improve the efficacy and effectiveness of chronic care delivery. But, disease management programme development and implementation is a complex undertaking that requires effective decision-making. Choices made in the earliest phases of programme development are crucial, as they ultimately impact costs, outcomes and sustainability. Methods To increase our understanding of the choices that primary healthcare practices face when implementing such programmes and to stimulate successful implementation and sustainability, we compared the early implementation of eight cardiovascular disease management programmes initiated and managed by healthcare practices in various regions of the Netherlands. Using a mixed-methods design, we identified differences in and challenges to programme implementation in terms of context, patient characteristics, disease management level, healthcare utilisation costs, development costs and health-related quality of life. Results Shifting to a multidisciplinary, patient-centred care pathway approach to disease management is demanding for organisations, professionals and patients, and is especially vulnerable when sustainable change is the goal. Funding is an important barrier to sustainable implementation of cardiovascular disease management programmes, although development costs of the individual programmes varied considerably in relation to the length of the development period. The large number of professionals involved in combination with duration of programme development was the largest cost drivers. While Information and Communication Technology systems to support the new care pathways did not directly contribute to higher costs, delays in implementation indirectly did. Conclusions Developing and implementing cardiovascular disease management programmes is time-consuming and challenging. Multidisciplinary, patient-centred care demands multifaceted changes in routine care. As

Short- circuit tests of circuit breakers

OpenAIRE

Chorovský, P.

2015-01-01

This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.

STICAP: A linear circuit analysis program with stiff systems capability. Volume 1: Theory manual. [network analysis

Science.gov (United States)

Cooke, C. H.

1975-01-01

STICAP (Stiff Circuit Analysis Program) is a FORTRAN 4 computer program written for the CDC-6400-6600 computer series and SCOPE 3.0 operating system. It provides the circuit analyst a tool for automatically computing the transient responses and frequency responses of large linear time invariant networks, both stiff and nonstiff (algorithms and numerical integration techniques are described). The circuit description and user's program input language is engineer-oriented, making simple the task of using the program. Engineering theories underlying STICAP are examined. A user's manual is included which explains user interaction with the program and gives results of typical circuit design applications. Also, the program structure from a systems programmer's viewpoint is depicted and flow charts and other software documentation are given.

Engineering genetic circuit interactions within and between synthetic minimal cells

Science.gov (United States)

Adamala, Katarzyna P.; Martin-Alarcon, Daniel A.; Guthrie-Honea, Katriona R.; Boyden, Edward S.

2017-05-01

Genetic circuits and reaction cascades are of great importance for synthetic biology, biochemistry and bioengineering. An open question is how to maximize the modularity of their design to enable the integration of different reaction networks and to optimize their scalability and flexibility. One option is encapsulation within liposomes, which enables chemical reactions to proceed in well-isolated environments. Here we adapt liposome encapsulation to enable the modular, controlled compartmentalization of genetic circuits and cascades. We demonstrate that it is possible to engineer genetic circuit-containing synthetic minimal cells (synells) to contain multiple-part genetic cascades, and that these cascades can be controlled by external signals as well as inter-liposomal communication without crosstalk. We also show that liposomes that contain different cascades can be fused in a controlled way so that the products of incompatible reactions can be brought together. Synells thus enable a more modular creation of synthetic biology cascades, an essential step towards their ultimate programmability.

Non-Destructive Techniques in the Tacis and Phare Nuclear Safety Programmes

International Nuclear Information System (INIS)

Bieth, Michel

2002-01-01

Decisions regarding the verification of design plant lifetime and potential license renewal periods involve a determination of the component and circuit condition. In Service Inspection of key reactor components becomes a crucial consideration for continued safe plant operation. The determination of the equipment properties by Non Destructive Techniques during periodic intervals is an important aspect of the assessment of fitness-for-service and safe operation of nuclear power plants The Tacis and Phare were established since 1991 by the European Union as support mechanisms through which projects could be identified and addressed satisfactorily. In Nuclear Safety, the countries mainly concerned are Russia, Ukraine, Armenia, and Kazakhstan for the Tacis programme, and Bulgaria, Czech Republic, Hungary, Slovak Republic, Lithuania, Romania and Slovenia for the Phare programme. The Tacis and Phare programs concerning the Nuclear Power Plants consist of: - On Site Assistance and Operational Safety, - Design Safety, - Regulatory Authorities, - Waste management, and are focused on reactor safety issues, contributing to the improvement in the safety of East European reactors and providing technology and safety culture transfer. The main parts of these programmes are related to the On-Site Assistance and to the Design Safety of VVER and RBMK Nuclear power plants where Non Destructive Techniques for In Service Inspection of the primary circuit components are addressed. (authors)

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Directory of Open Access Journals (Sweden)

Yoni Aizik

2011-01-01

Full Text Available A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

Investigation of SFQ integrated circuits using Nb fabrication technology

International Nuclear Information System (INIS)

Numata, H.; Tanaka, M.; Kitagawa, Y.; Tahara, S.

1999-01-01

In NEC's standard process, the minimum junction size is 2 μm and the critical current density (J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation (σ) of the critical current (I C ) was 0.9% for the 2 μm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits. (author)

Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors

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Pankiewicz Bogdan

2017-03-01

Full Text Available In this paper a programmable input mode instrumentation amplifier (IA utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA, which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC. IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.

Designed cell consortia as fragrance-programmable analog-to-digital converters.

Science.gov (United States)

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Is the use of albumin in colloid prime solution of cardiopulmonary bypass circuit justified?

NARCIS (Netherlands)

Boks, RH; van Herwerden, LA; Takkenberg, JJM; van Oeveren, W; Gu, YJ; Wijers, MJ; Bogers, AJJC

Background. Albumin in the priming solution precoats the surface of the cardiopulmonary bypass circuit, supposedly causing delayed adsorption of fibrinogen and reduced activation and adhesion of platelets. This action may result in lower transoxygenator resistance. Because our institution uses a

A review of programmable systems associated with Fermilab experiments

International Nuclear Information System (INIS)

Nash, T.

1981-01-01

In this paper we review the design and application of programmable systems for Fermilab experiments. The high luminosity fixed target environment at Fermilab has been a very fertile ground for the development of sophisticated, powerful triggering systems. A few of these are integrated systems designed to be flexible and to have broad application. Many are dedicated triggers taking advantage of large scale integrated circuits to focus on the specific needs of one experiment. In addition, the data acquisition requirements of large detectors, existing and planned, are being met with programmable systems to process the data. Offline reconstruction of data places a very heavy load on large general purpose computers. This offers a potentially very fruitful area for new developments involving programmable dedicated systems. Some of the present thinking at Fermilab regarding offline reconstruction processors will be described. (orig.)

High mortality during tuberculosis treatment does not indicate long diagnostic delays in Vietnam: a cohort study

Directory of Open Access Journals (Sweden)

Sy Dinh N

2007-08-01

Full Text Available Abstract Background Delay in tuberculosis diagnosis and treatment initiation may increase disease severity and mortality. In evaluations of tuberculosis control programmes high fatality rates during tuberculosis treatment, are used as an indicator of long delays in low HIV-prevalence settings. However, data for this presumed association between delay and fatality are lacking. We assessed the association between diagnostic delay and mortality of new smear-positive pulmonary tuberculosis patients in Vietnam. Methods Follow-up of a patient cohort included in a survey of diagnostic delay in 70 randomly selected districts. Data on diagnosis and treatment were extracted from routine registers. Patients who had died during the course of treatment were compared to those with reported cure, completed treatment or failure (survivors. Results Complete data were available for 1881/2093 (89.9% patients, of whom 82 (4.4% had died. Fatality was 4.5% for patients with ≤ 4 weeks delay, 5.0% for 5- ≤ 8 weeks delay (aOR 1.11, 95%CI 0.67–1.84 and 3.2% for > 9 weeks delay (aOR 0.69, 95%CI 0.37–1.30. Fatality tended to decline with increasing delay but this was not significant. Fatality was not associated with median diagnostic delay at district level (Spearman's rho = -0.08, P = 0.5. Conclusion Diagnostic delay is not associated with treatment mortality in Vietnam at individual nor district level, suggesting that high case fatality should not be used as an indicator of long diagnostic delay in national tuberculosis programmes.

OCaLustre : une extension synchrone d'OCaml pour la programmation de microcontrôleurs

OpenAIRE

Varoumas , Steven; Vaugon , Benoît; Chailloux , Emmanuel

2017-01-01

International audience; Les microcontrôleurs sont des circuits intégrés programmables dont le domaine d'application se concentre essentiellement dans le contrôle d'objets interagissant avec leur environnement. En effet, les programmes exécutés sur microcontrôleurs ont souvent pour rôle de réagir rapidement avec les composants qui les entourent, et de modifier leurs signaux de sortie dès lors que les signaux qu'ils reçoivent en entrée changent. Ainsi, la programmation synchrone à flots de donn...

Delayed Dopamine Signaling of Energy Level Builds Appetitive Long-Term Memory in Drosophila

OpenAIRE

Pierre-Yves Musso; Paul Tchenio; Thomas Preat

2015-01-01

Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level t...

Non-Foster Circuits for High Performance Antennas: Advantages and Practical Limitations

Science.gov (United States)

Jacob, Minu Mariam

The demand for miniaturized, broadband communication systems has created a need for electrically small, broadband antennas. However, all passive electrically small antennas have a fundamental gain-bandwidth limitation related to their electrical size, as first described by Wheeler and Chu. This limitation can be overcome using active non-Foster circuits (negative inductors and/or negative capacitors), which can deliver a broadband input match with active matching techniques, or can help reduce phase dispersion using negative delay effects. This thesis will illustrate the advantages of non-Foster circuits in obtaining broadband small antennas, in addition to examining their practical limitations due to noise in receive applications, and nonlinearity in transmit applications.

Super-transient scaling in time-delay autonomous Boolean network motifs

Energy Technology Data Exchange (ETDEWEB)

D' Huys, Otti, E-mail: otti.dhuys@phy.duke.edu; Haynes, Nicholas D. [Department of Physics, Duke University, Durham, North Carolina 27708 (United States); Lohmann, Johannes [Department of Physics, Duke University, Durham, North Carolina 27708 (United States); Institut für Theoretische Physik, Technische Universität Berlin, Hardenbergstraße 36, 10623 Berlin (Germany); Gauthier, Daniel J. [Department of Physics, Duke University, Durham, North Carolina 27708 (United States); Department of Physics, The Ohio State University, Columbus, Ohio 43210 (United States)

2016-09-15

Autonomous Boolean networks are commonly used to model the dynamics of gene regulatory networks and allow for the prediction of stable dynamical attractors. However, most models do not account for time delays along the network links and noise, which are crucial features of real biological systems. Concentrating on two paradigmatic motifs, the toggle switch and the repressilator, we develop an experimental testbed that explicitly includes both inter-node time delays and noise using digital logic elements on field-programmable gate arrays. We observe transients that last millions to billions of characteristic time scales and scale exponentially with the amount of time delays between nodes, a phenomenon known as super-transient scaling. We develop a hybrid model that includes time delays along network links and allows for stochastic variation in the delays. Using this model, we explain the observed super-transient scaling of both motifs and recreate the experimentally measured transient distributions.

Commutation circuit for an HVDC circuit breaker

Science.gov (United States)

Premerlani, William J.

1981-01-01

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

Delays in switching patients onto second-line antiretroviral treatment ...

African Journals Online (AJOL)

Background: South Africa has one of the largest antiretroviral treatment (ART) programmes globally. In addition to increasing access to ART, it is important that the health system also focuses on the appropriate management of patients who fail first-line ART. Delays in switching patients onto second-line ART can adversely ...

Introduction to Focus Issue: Time-delay dynamics

Science.gov (United States)

Erneux, Thomas; Javaloyes, Julien; Wolfrum, Matthias; Yanchuk, Serhiy

2017-11-01

The field of dynamical systems with time delay is an active research area that connects practically all scientific disciplines including mathematics, physics, engineering, biology, neuroscience, physiology, economics, and many others. This Focus Issue brings together contributions from both experimental and theoretical groups and emphasizes a large variety of applications. In particular, lasers and optoelectronic oscillators subject to time-delayed feedbacks have been explored by several authors for their specific dynamical output, but also because they are ideal test-beds for experimental studies of delay induced phenomena. Topics include the control of cavity solitons, as light spots in spatially extended systems, new devices for chaos communication or random number generation, higher order locking phenomena between delay and laser oscillation period, and systematic bifurcation studies of mode-locked laser systems. Moreover, two original theoretical approaches are explored for the so-called Low Frequency Fluctuations, a particular chaotical regime in laser output which has attracted a lot of interest for more than 30 years. Current hot problems such as the synchronization properties of networks of delay-coupled units, novel stabilization techniques, and the large delay limit of a delay differential equation are also addressed in this special issue. In addition, analytical and numerical tools for bifurcation problems with or without noise and two reviews on concrete questions are proposed. The first review deals with the rich dynamics of simple delay climate models for El Nino Southern Oscillations, and the second review concentrates on neuromorphic photonic circuits where optical elements are used to emulate spiking neurons. Finally, two interesting biological problems are considered in this Focus Issue, namely, multi-strain epidemic models and the interaction of glucose and insulin for more effective treatment.

Noise distribution of a peak track and hold circuit

International Nuclear Information System (INIS)

Seller, Paul; Hardie, Alec L.; Morrissey, Quentin

2012-01-01

Noise in linear electronic circuits is well characterised in terms of power spectral density in the frequency domain and the Normal probability density function in the time domain. For instance a charge preamplifier followed by a simple time independent pulse shaping circuit produces an output with a predictable, easily calculated Normal density function. By the Ergodic Principle this is true if the signal is sampled randomly in time or the experiment is run many times and measured at a fixed time after the circuit is released from reset. Apart from well defined cases, the time of the sample after release of reset does not affect the density function. If this signal is then passed through a peak track-and-hold circuit the situation is very different. The probability density function of the sampled signal is no longer Normal and the function changes with the time of the sample after release of reset. This density function can be classified by the Gumbel probability density function which characterises the Extreme Value Distribution of a defined number of Normally distributed values. The number of peaks in the signal is an important factor in the analysis. This issue is analysed theoretically and compared with a time domain noise simulation programme. This is then related to a real electronic circuit used for low-noise X-ray measurements and shows how the low-energy resolution of this system is significantly degraded when using a peak track-and-hold.

High temperature alloys for the primary circuit of a prototype nuclear process heat plant

International Nuclear Information System (INIS)

Ennis, P.J.; Schuster, H.

1979-01-01

As part of a comprehensive materials test programme for the High Temperature Reactor Project 'Prototype Plant for Nuclear Process Heat' (PNP), high temperature alloys are being investigated for primary circuit components operating at temperatures above 750 0 C. On the basis of important material parameters, in particular corrosion behaviour and mechanical properties in primary coolant helium, the potential of candidate alloys is discussed. By comparing specific PNP materials data with the requirements of PNP and those of conventional plant, the implications for the materials programme and component design are given. (orig.)

Global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms

International Nuclear Information System (INIS)

Wang Jian; Lu Junguo

2008-01-01

In this paper, we study the global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms. By constructing a suitable Lyapunov functional and utilizing some inequality techniques, we obtain a sufficient condition for the uniqueness and global exponential stability of the equilibrium solution for a class of fuzzy cellular neural networks with delays and reaction-diffusion terms. The result imposes constraint conditions on the network parameters independently of the delay parameter. The result is also easy to check and plays an important role in the design and application of globally exponentially stable fuzzy neural circuits

QCA Gray Code Converter Circuits Using LTEx Methodology

Science.gov (United States)

Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish Kumar; Maji, Bansibadan

2018-04-01

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The "defect-tolerant analysis" of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost α for the n-bit converter layouts.

Digitally Programmable High-Q Voltage Mode Universal Filter

Directory of Open Access Journals (Sweden)

D. Singh

2013-12-01

Full Text Available A new low-voltage low-power CMOS current feedback amplifier (CFA is presented in this paper. This is used to realize a novel digitally programmable CFA (DPCFA using transistor arrays and MOS switches. The proposed realizations nearly allow rail-to-rail swing capability at all the ports. Class-AB output stage ensures low power dissipation and high current drive capability. The proposed CFA/ DPCFA operates at supply voltage of ±0.75 V and exhibits bandwidth better than 95 MHz. An application of the DPCFA to realize a novel voltage mode high-Q digitally programmable universal filter (UF is given. Performances of all the proposed circuits are verified by PSPICE simulation using TSMC 0.25μm technology parameters.

Oscillator circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

Measuring circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

Delay Estimator and Improved Proportionate Multi-Delay Adaptive Filtering Algorithm

Directory of Open Access Journals (Sweden)

E. Verteletskaya

2012-04-01

Full Text Available This paper pertains to speech and acoustic signal processing, and particularly to a determination of echo path delay and operation of echo cancellers. To cancel long echoes, the number of weights in a conventional adaptive filter must be large. The length of the adaptive filter will directly affect both the degree of accuracy and the convergence speed of the adaptation process. We present a new adaptive structure which is capable to deal with multiple dispersive echo paths. An adaptive filter according to the present invention includes means for storing an impulse response in a memory, the impulse response being indicative of the characteristics of a transmission line. It also includes a delay estimator for detecting ranges of samples within the impulse response having relatively large distribution of echo energy. These ranges of samples are being indicative of echoes on the transmission line. An adaptive filter has a plurality of weighted taps, each of the weighted taps having an associated tap weight value. A tap allocation/control circuit establishes the tap weight values in response to said detecting means so that only taps within the regions of relatively large distributions of echo energy are turned on. Thus, the convergence speed and the degree of estimation in the adaptation process can be improved.

Carry-chain propagation delay impacts on resolution of FPGA-based TDC

International Nuclear Information System (INIS)

Dong Lei; Yang Junfeng; Song Kezhu

2014-01-01

The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

How to induce multiple delays in coupled chaotic oscillators?

Energy Technology Data Exchange (ETDEWEB)

Bhowmick, Sourav K. [CSIR-Indian Institute of Chemical Biology, Jadavpur, Kolkata 700032 (India); Department of Electronics, Asutosh College, Kolkata 700026 (India); Ghosh, Dibakar [Physics and Applied Mathematics Unit, Indian Statistical Institute, Kolkata 700108 (India); Roy, Prodyot K. [Department of Physics, Presidency University, Kolkata 700073 (India); Kurths, Jürgen [Potsdam Institute for Climate Impact Research, 14473 Potsdam (Germany); Institute for Physics, Humboldt University, 12489 Berlin (Germany); Dana, Syamal K. [CSIR-Indian Institute of Chemical Biology, Jadavpur, Kolkata 700032 (India)

2013-12-15

Lag synchronization is a basic phenomenon in mismatched coupled systems, delay coupled systems, and time-delayed systems. It is characterized by a lag configuration that identifies a unique time shift between all pairs of similar state variables of the coupled systems. In this report, an attempt is made how to induce multiple lag configurations in coupled systems when different pairs of state variables attain different time shift. A design of coupling is presented to realize this multiple lag synchronization. Numerical illustration is given using examples of the Rössler system and the slow-fast Hindmarsh-Rose neuron model. The multiple lag scenario is physically realized in an electronic circuit of two Sprott systems.

Resonance circuits for adiabatic circuits

Directory of Open Access Journals (Sweden)

C. Schlachta

2003-01-01

Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

FLANDES, Flange Design for He Circuits by Taylor-Forge Method

International Nuclear Information System (INIS)

Pitchford, B.E.

1977-01-01

1 - Nature of the physical problem solved: Flange design for helium circuits. 2 - Method of solution: This is a flange design programme based on the Taylor forge method with an additional calculation of flange rotation and bolt load change during the application of internal pressure. The method relates only to the integral hub type of flange, with or without a secondary O-ring seal but will deal also with the flange and cover plate case

Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

Science.gov (United States)

Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

2011-06-06

We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

Active component modeling for analog integrated circuit design. Model parametrization and implementation in the SPICE-PAC circuit simulator; Modelisation de composants actifs pour la CAO de circuits integres analogiques. Parametrage et implantation de modeles dans le simulateur SPICE-PAC

Energy Technology Data Exchange (ETDEWEB)

Marchal, Xavier

1992-06-19

. The first approach, physically based, is often time-consuming and results can be not accurate enough over all useful physical range. The second approach is achieved through the use of an optimizing program, FIT-PAC, which is closely associated to the modular circuit Simulator SPICE-PAC; a detailed description of it is given for a better overall understanding of the topic. FIT-PAC adjusts simultaneously ail parameters values, through use of 2 complementary optimizing methods: simulated annealing and SIMPLEX (or polytope) algorithms. We found this approach to be more efficient, systematic and easier to use than the Levenberg-Marquardt based fitting programs; this is due to the tact that neither simulated annealing nor simplex need the evaluation of the objective parametrization function gradient; this gradient can be very tedious to evaluate in many cases. We present results and discuss them in the case of static (DC) and dynamic (TRAN) MOS SPICE LEVEL 3 parameters determination. (author) [French] L'essor de l'industrie electronique est du principalement a l'integration accrue de dispositifs semi-conducteurs sur un meme support. Les programmes de conception assistee par ordinateur (CAO) sont les outils indispensables des concepteurs; ils permettent, avant fabrication, le test exhaustif de circuits complexes en evaluant leurs performances pour des conditions de fonctionnement normales ou extremes. Parmi tous ces logiciels, ceux de simulation electrique sont les plus largement utilises. Nous presentons les principaux en insistant sur le programme SPICE (Simulation Program with Integrated Circuit Emphasis) de Berkeley, reconnu comme la reference de la simulation de circuits. Cependant ce programme ne permet que des analyses standard; nous detaillons le programme SPICE-PAC qui possede toutes les fonctionnalites de SPICE, dont il est derive, mais permet, du fait de sa structure modulaire, des analyses nouvelles et variees. Cependant les programmes de simulation les plus

Arbitrary digital pulse sequence generator with delay-loop timing

Science.gov (United States)

Hošák, Radim; Ježek, Miroslav

2018-04-01

We propose an idea of an electronic multi-channel arbitrary digital sequence generator with temporal granularity equal to two clock cycles. We implement the generator with 32 channels using a low-cost ARM microcontroller and demonstrate its capability to produce temporal delays ranging from tens of nanoseconds to hundreds of seconds, with 24 ns timing granularity and linear scaling of delay with respect to the number of delay loop iterations. The generator is optionally synchronized with an external clock source to provide 100 ps jitter and overall sequence repeatability within the whole temporal range. The generator is fully programmable and able to produce digital sequences of high complexity. The concept of the generator can be implemented using different microcontrollers and applied for controlling of various optical, atomic, and nuclear physics measurement setups.

Inspection qualification programme for VVER reactors and review of round robin test results

International Nuclear Information System (INIS)

Horacek, L.; Zdarek, J.

1998-01-01

Experience obtained, especially from in-service inspections of VVER 440-type reactor pressure vessels and from the Czech round test trials with international participation of ultrasonic teams, has highlighted the need for an in-service inspection qualification programme in the Czech Republic focused on NDT procedures, equipment and personnel. Recently, several national and international regional projects included in the PHARE programme (projects 4.1.2/93 and 1.02/94), briefly described, have been initiated. These projects are to cover step by step the programme of the in-service inspection qualification in view of technical justification as well as of practical assessment-performance demonstration-for all the main VVER-type primary circuit components. (orig.)

Multi-purpose logical device with integrated circuit for the automation of mine water disposal

Energy Technology Data Exchange (ETDEWEB)

Pop, E.; Pasculescu, M.

1980-06-01

After an analysis of the waste water disposal as an object of automation, the author presents a BASIC-language programme established to simulate the automated control system on a digital computer. Then a multi-purpose logical device with integrated circuits for the automation of the mine water disposal is presented. (In Romanian)

Impact of Compensatory Intervention in 6- to 18-Month-Old Babies at Risk of Motor Development Delays

Science.gov (United States)

Müller, Alessandra Bombarda; Saccani, Raquel; Valentini, Nadia Cristina

2017-01-01

Purpose: Research indicates that delayed motor development observed in the first years of life can be prevented through compensatory intervention programmes that provide proper care during this critical period of child development. Method: This study analysed the impact of a 12-week compensatory motor intervention programme on 32 babies with…

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Levi, M.E.

1995-12-01

Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over many thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be, achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2μm and 0.8μm technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better solution for the TDC circuit

A Cytomorphic Chip for Quantitative Modeling of Fundamental Bio-Molecular Circuits.

Science.gov (United States)

2015-08-01

We describe a 0.35 μm BiCMOS silicon chip that quantitatively models fundamental molecular circuits via efficient log-domain cytomorphic transistor equivalents. These circuits include those for biochemical binding with automatic representation of non-modular and loading behavior, e.g., in cascade and fan-out topologies; for representing variable Hill-coefficient operation and cooperative binding; for representing inducer, transcription-factor, and DNA binding; for probabilistic gene transcription with analogic representations of log-linear and saturating operation; for gain, degradation, and dynamics of mRNA and protein variables in transcription and translation; and, for faithfully representing biological noise via tunable stochastic transistor circuits. The use of on-chip DACs and ADCs enables multiple chips to interact via incoming and outgoing molecular digital data packets and thus create scalable biochemical reaction networks. The use of off-chip digital processors and on-chip digital memory enables programmable connectivity and parameter storage. We show that published static and dynamic MATLAB models of synthetic biological circuits including repressilators, feed-forward loops, and feedback oscillators are in excellent quantitative agreement with those from transistor circuits on the chip. Computationally intensive stochastic Gillespie simulations of molecular production are also rapidly reproduced by the chip and can be reliably tuned over the range of signal-to-noise ratios observed in biological cells.

Hybrid CMOS/Molecular Integrated Circuits

Science.gov (United States)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Note concerning the Ecasac programme; Note sur le programme ecasac

Energy Technology Data Exchange (ETDEWEB)

Bras, D [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1969-07-01

The analytical programme developed by the firm I.B.M. for ECAP electronic circuits, operated initially on the IBM 1620 computer with a certain limitation on the size of the network studied, but already equipped from the conversational angle (type-writer). The IBM 360 computers made it possible to increase the size of the network treated to 50 nodes and 200 branches, but the conversational aspect was suppressed in the ECAP 360 version. With a view to making use of the possibilities of hybrid computers, we have adapted this latter version to the EAI 8400 computer. Without diminishing it in any way, we have modified it so as to provide it with conversational characteristics by using the computers control panel; to give it still further flexibility we have made it possible to record curves during the calculation operation, and to obtain a division of the printed results. To obtain the curves, use was made of analog digital converters of the interface of the hybrid unit EAI 8900 of which the EAI 8400 computer represents the numerical section. The modifications made concern in particular the A.C. analysis and the transient analysis. They facilitate and complete the input of the data; they allow modifications to be made for the calculation of these analyses; they also improve the presentation of the results and facilitate their interpretation. They constitute finally the version ECASAC, i.e. the programme ECAP 360 made conversational by use of a type-writer, with automatic output of the curves. (author) [French] Le programme d'analyse de circuits electroniques ECAP, mis au point par la firme I.B.M., a d'abord fonctionne sur ordinateur IBM 1620 avec une certaine limitation pour la taille du reseau etudie, mais deja une optique conversationnelle (machine a ecrire). Les ordinateurs IBM 360 ont permis d'accroitre la taille du reseau permis a 50 noeuds et 200 branches, mais par contre l'optique conversationnelle fut supprimee dans la version ECAP 360. Dans le but d

Universal programmable logic gate and routing method

Science.gov (United States)

Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Project Circuits in a Basic Electric Circuits Course

Science.gov (United States)

Becker, James P.; Plumb, Carolyn; Revia, Richard A.

2014-01-01

The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

Design of acoustic logging signal source of imitation based on field programmable gate array

Science.gov (United States)

Zhang, K.; Ju, X. D.; Lu, J. Q.; Men, B. Y.

2014-08-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes.

Research on laser detonation pulse circuit with low-power based on super capacitor

Science.gov (United States)

Wang, Hao-yu; Hong, Jin; He, Aifeng; Jing, Bo; Cao, Chun-qiang; Ma, Yue; Chu, En-yi; Hu, Ya-dong

2018-03-01

According to the demand of laser initiating device miniaturization and low power consumption of weapon system, research on the low power pulse laser detonation circuit with super capacitor. Established a dynamic model of laser output based on super capacitance storage capacity, discharge voltage and programmable output pulse width. The output performance of the super capacitor under different energy storage capacity and discharge voltage is obtained by simulation. The experimental test system was set up, and the laser diode of low power pulsed laser detonation circuit was tested and the laser output waveform of laser diode in different energy storage capacity and discharge voltage was collected. Experiments show that low power pulse laser detonation based on super capacitor energy storage circuit discharge with high efficiency, good transient performance, for a low power consumption requirement, for laser detonation system and low power consumption and provide reference light miniaturization of engineering practice.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

Science.gov (United States)

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

Science.gov (United States)

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

Directory of Open Access Journals (Sweden)

Chen Yang

2017-06-01

Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Predicting the life-time benefit of school-based smoking prevention programmes.

Science.gov (United States)

Jit, Mark; Aveyard, Paul; Barton, Pelham; Meads, Catherine A

2010-06-01

School-based smoking prevention programmes may delay the age of smoking initiation, but do not appear to achieve lasting reductions in smoking prevalence beyond school-leaving age. We explored whether delaying the age at which someone initiates smoking may have life-time benefits by increasing the likelihood of quitting in later life. Data from the General Household Survey of Great Britain were used in a logistic regression model to examine the association between age at which someone initiates regular smoking and the probability that the person will quit smoking later in life. The effect of confounding variables (sex, ethnicity, socio-economic class, education and geographical location) was taken into account. The predicted relationship was used in a cohort model to estimate the life-time reduction in smoking prevalence and all-cause mortality of a school-based smoking prevention programme. Age of regular smoking initiation was associated strongly with the probability of quitting later in life (coefficient -0.103, P < 0.001). The strength of the association was slightly reduced but still significant when confounding variables were included (coefficient -0.075, P < 0.001). An intervention that delays smoking initiation without decreasing smoking prevalence at age 18 may reduce adult smoking prevalence by 0.13-0.32% (depending on age) and all-cause mortality by 0.09% over the life-time of the sample. School-based smoking prevention programmes have potential for a beneficial effect over the life-time of the participants even if they have no apparent effect at school-leaving age.

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Directory of Open Access Journals (Sweden)

Stephen Brown

1996-01-01

Full Text Available This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

Science.gov (United States)

Russinoff, David M.

1995-01-01

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Delayed self-regulation and time-dependent chemical drive leads to novel states in epigenetic landscapes

Science.gov (United States)

Mitra, Mithun K.; Taylor, Paul R.; Hutchison, Chris J.; McLeish, T. C. B.; Chakrabarti, Buddhapriya

2014-01-01

The epigenetic pathway of a cell as it differentiates from a stem cell state to a mature lineage-committed one has been historically understood in terms of Waddington's landscape, consisting of hills and valleys. The smooth top and valley-strewn bottom of the hill represent their undifferentiated and differentiated states, respectively. Although mathematical ideas rooted in nonlinear dynamics and bifurcation theory have been used to quantify this picture, the importance of time delays arising from multistep chemical reactions or cellular shape transformations have been ignored so far. We argue that this feature is crucial in understanding cell differentiation and explore the role of time delay in a model of a single-gene regulatory circuit. We show that the interplay of time-dependent drive and delay introduces a new regime where the system shows sustained oscillations between the two admissible steady states. We interpret these results in the light of recent perplexing experiments on inducing the pluripotent state in mouse somatic cells. We also comment on how such an oscillatory state can provide a framework for understanding more general feedback circuits in cell development. PMID:25165605

Generation of optical vortices in an integrated optical circuit

Science.gov (United States)

Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

2017-09-01

In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

Design and performance analysis of delay insensitive multi-ring structures

DEFF Research Database (Denmark)

Sparsø, Jens; Staunstrup, Jørgen

1993-01-01

A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm....... The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings...... that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks....

A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique

Directory of Open Access Journals (Sweden)

Trong-Tu Bui

2013-01-01

Full Text Available We present a compact and low-power rank-order searching (ROS circuit that can be used for building associative memories and rank-order filters (ROFs by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.

Nonlinear dynamics based digital logic and circuits.

Science.gov (United States)

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Organizing of delay, input gate and memory of proportional chamber channel basing on D-trigger

International Nuclear Information System (INIS)

Vladimirov, S.V.; Kuzichev, V.F.; Rabin, N.V.

1980-01-01

Economical organization of delay, input gate and proportional chamber (PC) channel memory on the 155 TM2 D trigger basis is described. The channel consists of an amplifier; delay element permitting to synchronize PC signal and recording strobe-signal; input gate, where coincidence of the above signals occurs; memory element, where the data from a wire are recorded and stored; read gate through which the data are transmitted for further processing. Presented is one of the versions of circuit solution for delay element, input gate and momory element. Flowsheet peculiarity is the simplicity of fabrication and tuning as well as low cost of the device

Programmable autonomous synthesis of single-stranded DNA

Science.gov (United States)

Kishi, Jocelyn Y.; Schaus, Thomas E.; Gopalkrishnan, Nikhil; Xuan, Feng; Yin, Peng

2018-02-01

DNA performs diverse functional roles in biology, nanotechnology and biotechnology, but current methods for autonomously synthesizing arbitrary single-stranded DNA are limited. Here, we introduce the concept of primer exchange reaction (PER) cascades, which grow nascent single-stranded DNA with user-specified sequences following prescribed reaction pathways. PER synthesis happens in a programmable, autonomous, in situ and environmentally responsive fashion, providing a platform for engineering molecular circuits and devices with a wide range of sensing, monitoring, recording, signal-processing and actuation capabilities. We experimentally demonstrate a nanodevice that transduces the detection of a trigger RNA into the production of a DNAzyme that degrades an independent RNA substrate, a signal amplifier that conditionally synthesizes long fluorescent strands only in the presence of a particular RNA signal, molecular computing circuits that evaluate logic (AND, OR, NOT) combinations of RNA inputs, and a temporal molecular event recorder that records in the PER transcript the order in which distinct RNA inputs are sequentially detected.

Development of reconfigurable analog and digital circuits for plasma diagnostics measurement systems

International Nuclear Information System (INIS)

Srivastava, Amit Kumar; Sharma, Atish; Raval, Tushar

2009-01-01

In long pulse discharge tokamak, a large number of diagnostic channels are being used to understand the complex behavior of plasma. Different diagnostics demand different types of analog and digital processing for plasma parameters measurement. This leads to variable requirements of signal processing for diagnostic measurement. For such types of requirements, we have developed hardware with reconfigurable electronic devices, which provide flexible solution for rapid development of measurement system. Here the analog processing is achieved by Field Programmable Analog Array (FPAA) integrated circuit while reconfigurable digital devices (CPLD/FPGA) achieve digital processing. FPAA's provide an ideal integrated platform for implementing low to medium complexity analog signal processing. With dynamic reconfigurability, the functionality of the FPAA can be reconfigured in-system by the designer or on the fly by a microprocessor. This feature is quite useful to manipulate the tuning or the construction of any part of the analog circuit without interrupting operation of the FPAA, thus maintaining system integrity. The hardware operation control logic circuits are configured in the reconfigurable digital devices (CPLD/FPGA) to control proper hardware functioning. These reconfigurable devices provide the design flexibility and save the component space on the board. It also provides the flexibility for various setting through software. The circuit controlling commands are either issued by computer/processor or generated by circuit itself. (author)

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

Science.gov (United States)

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

Directory of Open Access Journals (Sweden)

Santiago T. Pérez Suárez

2013-12-01

Full Text Available This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

The Polish National Investment Fund Programme: Mass Privatisation With a Difference?

OpenAIRE

Iraj Hashi

2000-01-01

The Polish mass privatisation programme (MPP), though debated at length in the early phase of transition, was implemented with a long delay which led to the deterioration of the financial position of many of the companies in the scheme and the loss of, at least, some of the potential benefits of such schemes. The most important lesson of the programme for other countries is that mass privatisation should be implemented quickly in order to avoid uncertainty and to prevent opportunistic behavio...

Insights into iodine behaviour and speciation in the Phébus primary circuit

International Nuclear Information System (INIS)

Girault, N.; Payot, F.

2013-01-01

analyses that were performed using equilibrium gas-phase chemistry models evidenced that it becomes necessary to reconsider iodine species behaviour along their transport in the RCS not only as a function of oxido-reducing conditions, material release kinetics, but also in the light of potential kinetics limitations in vapour chemical transformations. Indeed, even if a strong connection between B, Cs, Mo, Cd and I chemistry was evidenced; in general, calculations were only partly satisfactory in reproducing the main aspects of the observed iodine/caesium behaviour and speciation. A better prediction of the volatile iodine speciation, the level of association of I to Cs and the gaseous iodine occurrence are the main objective of the experimental international and cooperative programme CHIP launched by IRSN in support of the Phébus FP programme interpretation. This programme was especially dedicated to investigate the kinetic limitations of iodine chemical reactions in a model primary circuit

Wavy Channel TFT-Based Digital Circuits

KAUST Repository

Hanna, Amir

2016-02-23

We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

Wavy Channel TFT-Based Digital Circuits

KAUST Repository

Hanna, Amir; Hussain, Aftab M.; Hussain, Aftab M.; Hussain, Aftab M.; Omran, Hesham; Alsharif, Sarah M.; Salama, Khaled N.; Hussain, Muhammad Mustafa

2016-01-01

We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

An improved superconducting neural circuit and its application for a neural network solving a combinatorial optimization problem

International Nuclear Information System (INIS)

Onomi, T; Nakajima, K

2014-01-01

We have proposed a superconducting Hopfield-type neural network for solving the N-Queens problem which is one of combinatorial optimization problems. The sigmoid-shape function of a neuron output is represented by the output of coupled SQUIDs gate consisting of a single-junction and a double-junction SQUIDs. One of the important factors for an improvement of the network performance is an improvement of a threshold characteristic of a neuron circuit. In this paper, we report an improved design of coupled SQUID gates for a superconducting neural network. A step-like function with a steep threshold at a rising edge is desirable for a neuron circuit to solve a combinatorial optimization problem. A neuron circuit is composed of two coupled SQUIDs gates with a cascade connection in order to obtain such characteristics. The designed neuron circuit is fabricated by a 2.5 kA/cm 2 Nb/AlOx/Nb process. The operation of a fabricated neuron circuit is experimentally demonstrated. Moreover, we discuss about the performance of the neural network using the improved neuron circuits and delayed negative self-connections.

Inductive circuit arrangements

International Nuclear Information System (INIS)

Mansfield, Peter; Coxon, R.J.

1987-01-01

A switched coil arrangement is connected in a bridge configuration of four switches S 1 , S 2 , S 3 and S 4 which are each shunted by diodes D 1 , D 2 , D 3 and D 4 so that current can flow in either direction through a coil L depending on the setting of the switches. A capacitor C is connected across the bridge through a switch S 5 to receive the inductive energy stored in coil L on breaking the current flow path through the coil. The electrostatic energy stored in capacitor C can then be used to supply current through the coil in the reverse direction either immediately or after a time delay. Coil L may be a superconductive coil. Losses in the circuit can be made up by a trickle charge of capacitor C from a separate supply V 2 . The device may be used in nuclear magnetic resonance imaging. (author)

Effects of two physical education programmes on health- and skill-related physical fitness of Albanian children

DEFF Research Database (Denmark)

Jarani, J; Grøntved, Anders; Muca, F

2016-01-01

This study aims to evaluate the effectiveness of two school-based physical education (PE) programmes (exercise-based and games-based) compared with traditional PE, on health- and skill-related physical fitness components in children in Tirana, Albania. Participants were 378 first-grade (6.8 years...... intervention programmes were taught by professional PE teachers using station/circuit teaching framework while CG referred to traditional PE school lessons by a general teacher. All programmes ran in parallel and lasted 5 months, having the same frequency (twice weekly) and duration (45 min). Heart rate (HR......) monitoring showed that intensity during PE lessons was significantly higher in the intervention groups compared with control (P

Ultra-low power integrated circuit design circuits, systems, and applications

CERN Document Server

Li, Dongmei; Wang, Zhihua

2014-01-01

This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

Spiking neuron devices consisting of single-flux-quantum circuits

International Nuclear Information System (INIS)

Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito

2006-01-01

Single-flux-quantum (SFQ) circuits can be used for making spiking neuron devices, which are useful elements for constructing intelligent, brain-like computers. The device we propose is based on the leaky integrate-and-fire neuron (IFN) model and uses a SFQ pulse as an action signal or a spike of neurons. The operation of the neuron device is confirmed by computer simulator. It can operate with a short delay of 100 ps or less and is the highest-speed neuron device ever reported

Memorizing circuit for long pulses; Circuit de memoire pour impulsions longues; Zapominayushchee ustrojstvo dlya dlitel'nykh impul'sov; Circuito memorizador para impulsos de larga duracion

Energy Technology Data Exchange (ETDEWEB)

Coli, M; Horn, G [Sorin Centro Ricerche Nucleari di Saluggia (Italy)

1962-04-15

The circuit allows unlimited memorization of a positive pulse of any shape, and retains both amplitude and width. Theoretically a rectangular pulse of amplitude A and width t produced as a single pulse when t = 0 can be reproduced in its own area after any time {tau}, so that it may be retained on an oscilloscope synchronized at a repetition frequency {approx_equal} 1/{tau}. The rise form of pulse is not memorized, so that the pulse rise and decay time retained by the oscilloscope are those inherent to the memorizing circuit. Basically the circuit may be considered as being formed by two stretching circuits. These transform the input width from t to t + {tau}. The lengthened pulses of opposite phases are added to obtain at the output a pulse of amplitude A and width t. The delay {tau} is controlled by two monostables triggered at an interval t (delay control circuit) by a saturated amplifier which squares the input and gives two pulses, through a differentiating circuit (delay-measuring circuit). The output pulse is fed back to the input through an attenuator and a delay line. The cycle is repeated with a repetition rate of {approx} l/{tau}. The memorized pulse has a width from 50 {mu}s to over 10 ms. The repetition rate may vary from 10{sup 4} Hz to 30 Hz and less. Another circuit, obtained by using the same principle, is described in the original paper. It can also memorize input pulse shape apart from the amplitude and width. (author) [French] Le circuit permet la memorisation illimitee d'une impulsion positive de n'importe quelle forme; il en conserve a la fois l'amplitude et la largeur. Theoriquement, une impulsion rectangulaire d'une amplitude A et d'une largeur t, produite sous forme d'impulsion unique a un temps t = 0, peut etre reproduite apres un temps {tau}, ce qui permet de la conserver sur un oscilloscope synchronise a une frequence de repetition {approx_equal} 1/{tau}. La forme de la montee de l'impulsion n'etant pas memorisee, les temps de montee et

Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

International Nuclear Information System (INIS)

Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

2005-01-01

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

Bidirectional automatic release of reserve for low voltage network made with low capacity PLCs

Science.gov (United States)

Popa, I.; Popa, G. N.; Diniş, C. M.; Deaconu, S. I.

2018-01-01

The article presents the design of a bidirectional automatic release of reserve made on two types low capacity programmable logic controllers: PS-3 from Klöckner-Moeller and Zelio from Schneider. It analyses the electronic timing circuits that can be used for making the bidirectional automatic release of reserve: time-on delay circuit and time-off delay circuit (two types). In the paper are present the sequences code for timing performed on the PS-3 PLC, the logical functions for the bidirectional automatic release of reserve, the classical control electrical diagram (with contacts, relays, and time relays), the electronic control diagram (with logical gates and timing circuits), the code (in IL language) made for the PS-3 PLC, and the code (in FBD language) made for Zelio PLC. A comparative analysis will be carried out on the use of the two types of PLC and will be present the advantages of using PLCs.

Electronic circuit encyclopedia 2

Energy Technology Data Exchange (ETDEWEB)

Park, Sun Ho

1992-10-15

This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

Electronic circuit encyclopedia 2

International Nuclear Information System (INIS)

Park, Sun Ho

1992-10-01

This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

Integrated biocircuits: engineering functional multicellular circuits and devices

Science.gov (United States)

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Solid-state circuits

CERN Document Server

Pridham, G J

2013-01-01

Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

Description and characterization of the ACRR's programmable transient rod withdrawal mode

International Nuclear Information System (INIS)

Boldt, K.R.; Sullivan, W.H.; Kefauver, H.L.

1980-01-01

To satisfy experiment needs for Sandia's Advanced Reactor Safety Program, a programmable Transient Rod Withdrawal (TRW) mode has been developed for the Annular Core Research Reactor (ACRR). The programmable mode is a modification of the existing continuous-withdrawal TRW mode and permits speed and direction changes during the pulse sequence. Basically, a TRW operation is similar to a routine pulse operation except that transient rods are mechanically withdrawn rather than pneumatically fired. Being a pulse-type operation, the TRW mode complies with pulse-mode safety system settings. Control system interlocks prevent the pneumatic firing of rods in the TRW mode. The hardware for the programmable TRW mode includes three ACRR transient rods, the ACRR timer, two rod programmers, a minicomputer and a summing circuit for position indication. Each ACRR transient rod is mechanically driven by a stepping motor (rated torque at 4.24 joules) and is capable of a maximum TRW speed of 26.7 centimeters/ second. The maximum reactivity insertion rate is $2.45/second with a transient rod bank worth of $3.00 and $3.47/second with a bank worth of $4.25, which is expected to be installed soon. The ACRR timer is a multifunctional timer used in all operating modes of the reactor. In the programmable TRW mode, the timer starts the rod programmers and drops regulating rods to terminate the operation. Programmed withdrawal capability is provided by one of two rod programmers (a hardwire-based unit and a microprocessor-based unit). The hardwire unit has eight intervals in which speed, direction and distance are selected by switches on the front panel. The microprocessor-based unit has the capability of 64 intervals in which speed, direction, and distance or time can be specified. Programming this unit is accomplished from the front panel or by inputting data from an HP-9845. minicomputer via a digital I/O interface. Self-test programs in the software provide a continual check of an operating

Sistem Proteksi Arus Bocor Menggunakan Earth Leakage Circuit Breaker Berbasis Arduino

Directory of Open Access Journals (Sweden)

Syukriyadin Syukriyadin

2017-02-01

Full Text Available Touching a live part of electrical equipment either intentionally or unintentionally can cause an electric shock. The touch can occur directly or indirectly and results in the flow of electric current through the human body to the ground. This electric current is known as the leakage current and can have fatal effects on the human body such as burns, cramps, faint and death. This paper aims to design a prototype protection model of the earth leakage circuit breaker device based on Arduino (ELCBA to protect the human body from the electrical hazards. The performance of the ELCBA is investigated by detecting the earth leakage current to the grounding system (TN.  The prototype is designed and simulated by using Proteus software. Based on the response test carried out on the prototype, it can be concluded that the ELCBA can operate properly to disconnect the electric circuit if the leakage current is detected greater than or equal to 30 mA with a time delay of 15 ms and to reclose the circuit again after 5 minutes.

The design of infrared information collection circuit based on embedded technology

Science.gov (United States)

Liu, Haoting; Zhang, Yicong

2013-07-01

S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

Effectiveness of the Language Intervention Programme for Preschool Children.

Science.gov (United States)

Lousada, Marisa; Ramalho, Margarida; Marques, Carolina

2016-01-01

This paper investigates the effectiveness of the Language Intervention Programme for the treatment of 14 preschool-aged children with primary language impairment. We used a waiting list control design, in which half the sample (7 children) received immediate intervention with the Language Intervention Programme, whereas the remaining children received treatment after a 4-week delay. The intervention consisted of 8 individual biweekly sessions. Outcome measures of language ability (receptive semantic and morphosyntactic, expressive semantic and morphosyntactic, and metalinguistic) were taken before and after intervention. After 4 weeks of intervention, the experimental group showed significant improvements in language (receptive, expressive and metalinguistic skills), but no differences were found for those in the waiting control group. After 4 weeks of intervention for the control group, significant progress in language was also observed. The Language Intervention Programme was found to be effective in treating language skills of children with language impairment, providing clinical evidence for speech and language therapists to employ this programme for the treatment of preschool children with language disorders. © 2016 S. Karger AG, Basel.

Multiple constant multiplication optimizations for field programmable gate arrays

CERN Document Server

Kumm, Martin

2016-01-01

This work covers field programmable gate array (FPGA)-specific optimizations of circuits computing the multiplication of a variable by several constants, commonly denoted as multiple constant multiplication (MCM). These optimizations focus on low resource usage but high performance. They comprise the use of fast carry-chains in adder-based constant multiplications including ternary (3-input) adders as well as the integration of look-up table-based constant multipliers and embedded multipliers to get the optimal mapping to modern FPGAs. The proposed methods can be used for the efficient implementation of digital filters, discrete transforms and many other circuits in the domain of digital signal processing, communication and image processing. Contents Heuristic and ILP-Based Optimal Solutions for the Pipelined Multiple Constant Multiplication Problem Methods to Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary (3-Input) Adders An Optimized Multiple Constant Multiplication Architecture ...

COSTANZA, 1-D 2 Group Space-Dependent Reactor Dynamics of Spatial Reactor with 1 Group Delayed Neutrons

International Nuclear Information System (INIS)

Agazzi, A.; Gavazzi, C.; Vincenti, E.; Monterosso, R.

1964-01-01

1 - Nature of physical problem solved: The programme studies the spatial dynamics of reactor TESI, in the two group and one space dimension approximation. Only one group of delayed neutrons is considered. The programme simulates the vertical movement of the control rods according to any given movement law. The programme calculates the evolution of the fluxes and temperature and precursor concentration in space and time during the power excursion. 2 - Restrictions on the complexity of the problem: The maximum number of lattice points is 100

RECRUITMENT FINANCED BY SAVED LEAVE (RSL PROGRAMME)

CERN Multimedia

Division du Personnel; Tel. 73903

1999-01-01

Transfer to the saved leave account and saved leave bonusStaff members participating in the RSL programme may opt to transfer up to 10 days of unused annual leave or unused compensatory leave into their saved leave account, at the end of the leave year, i.e. 30 September (as set out in the implementation procedure dated 27 August 1997).A leave transfer request form, which you should complete, sign and return, if you wish to use this possibility, has been addressed you. To allow the necessary time for the processing of your request, you should return it without delay.As foreseen in the implementation procedure, an additional day of saved leave will be granted for each full period of 20 days remaining in the saved leave account on 31 December 1999, for any staff member participating in the RSL programme until that date.For part-time staff members participating in the RSL programme, the above-mentioned days of leave (annual, compensatory and saved) are adjusted proportionally to their contractual working week as...

Collective of mechatronics circuit

International Nuclear Information System (INIS)

1987-02-01

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

Collective of mechatronics circuit

Energy Technology Data Exchange (ETDEWEB)

NONE

1987-02-15

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

OpenAIRE

石橋, 孝昭

2012-01-01

This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

Contamination of a PWR primary circuit by fuel pins with failed cladding

International Nuclear Information System (INIS)

Janvier, J.C.; Chagrot, M.

1979-01-01

The safety authorities in the principal nuclear countries appear to be attaching increasing importance to keeping reactor primary circuits as contamination-free as possible. Therefore, the consequences of cladding failures and especially of those resulting from fabrication defects have to be evaluated, for when these failures become systematic in nature they constitute an important source of contamination in pressurized-water reactors. The Grenoble Nuclear Research Centre is implementing a programme on the study of such failures with a view to analysing the behaviour of failed fuel elements. A distinction is made between two types of cladding failure, depending on whether the primary water enters the fuel pin as soon as the circuits are pressurized (fabrication defect) or whether the failure is caused during operation. The emission of gaseous fission products and halogens has been analysed in different operating modes (steady-state or transient), and in spite of the complexity of the phenomena involved, some results have been obtained which already enable one to evaluate fission product contamination of the primary circuit. (author)

Note: Large active area solid state photon counter with 20 ps timing resolution and 60 fs detection delay stability

Science.gov (United States)

Prochazka, Ivan; Kodet, Jan; Eckl, Johann; Blazej, Josef

2017-10-01

We are reporting on the design, construction, and performance of a photon counting detector system, which is based on single photon avalanche diode detector technology. This photon counting device has been optimized for very high timing resolution and stability of its detection delay. The foreseen application of this detector is laser ranging of space objects, laser time transfer ground to space and fundamental metrology. The single photon avalanche diode structure, manufactured on silicon using K14 technology, is used as a sensor. The active area of the sensor is circular with 200 μm diameter. Its photon detection probability exceeds 40% in the wavelength range spanning from 500 to 800 nm. The sensor is operated in active quenching and gating mode. A new control circuit was optimized to maintain high timing resolution and detection delay stability. In connection to this circuit, timing resolution of the detector is reaching 20 ps FWHM. In addition, the temperature change of the detection delay is as low as 70 fs/K. As a result, the detection delay stability of the device is exceptional: expressed in the form of time deviation, detection delay stability of better than 60 fs has been achieved. Considering the large active area aperture of the detector, this is, to our knowledge, the best timing performance reported for a solid state photon counting detector so far.

Programmable Electronic Safety Systems

International Nuclear Information System (INIS)

Parry, R.

1993-05-01

Traditionally safety systems intended for protecting personnel from electrical and radiation hazards at particle accelerator laboratories have made extensive use of electromechanical relays. These systems have the advantage of high reliability and allow the designer to easily implement failsafe circuits. Relay based systems are also typically simple to design, implement, and test. As systems, such as those presently under development at the Superconducting Super Collider Laboratory (SSCL), increase in size, and the number of monitored points escalates, relay based systems become cumbersome and inadequate. The move toward Programmable Electronic Safety Systems is becoming more widespread and accepted. In developing these systems there are numerous precautions the designer must be concerned with. Designing fail-safe electronic systems with predictable failure states is difficult at best. Redundancy and self-testing are prime examples of features that should be implemented to circumvent and/or detect failures. Programmable systems also require software which is yet another point of failure and a matter of great concern. Therefore the designer must be concerned with both hardware and software failures and build in the means to assure safe operation or shutdown during failures. This paper describes features that should be considered in developing safety systems and describes a system recently installed at the Accelerator Systems String Test (ASST) facility of the SSCL

Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Directory of Open Access Journals (Sweden)

Huei Chaeng Chin

2014-01-01

Full Text Available Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET for applications in ultralarge-scale integration (ULSI is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP and power-delay product (PDP of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg, for subthreshold swing (SS, drain-induced barrier lowering (DIBL, and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

Delayed Maturation of Fast-Spiking Interneurons Is Rectified by Activation of the TrkB Receptor in the Mouse Model of Fragile X Syndrome.

Science.gov (United States)

Nomura, Toshihiro; Musial, Timothy F; Marshall, John J; Zhu, Yiwen; Remmers, Christine L; Xu, Jian; Nicholson, Daniel A; Contractor, Anis

2017-11-22

Fragile X syndrome (FXS) is a neurodevelopmental disorder that is a leading cause of inherited intellectual disability, and the most common known cause of autism spectrum disorder. FXS is broadly characterized by sensory hypersensitivity and several developmental alterations in synaptic and circuit function have been uncovered in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABA-mediated neurotransmission and fast-spiking (FS) GABAergic interneurons are central to cortical circuit development in the neonate. Here we demonstrate that there is a delay in the maturation of the intrinsic properties of FS interneurons in the sensory cortex, and a deficit in the formation of excitatory synaptic inputs on to these neurons in neonatal Fmr1 KO mice. Both these delays in neuronal and synaptic maturation were rectified by chronic administration of a TrkB receptor agonist. These results demonstrate that the maturation of the GABAergic circuit in the sensory cortex is altered during a critical developmental period due in part to a perturbation in BDNF-TrkB signaling, and could contribute to the alterations in cortical development underlying the sensory pathophysiology of FXS. SIGNIFICANCE STATEMENT Fragile X (FXS) individuals have a range of sensory related phenotypes, and there is growing evidence of alterations in neuronal circuits in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABAergic interneurons are central to the correct formation of circuits during cortical critical periods. Here we demonstrate a delay in the maturation of the properties and synaptic connectivity of interneurons in Fmr1 KO mice during a critical period of cortical development. The delays both in cellular and synaptic maturation were rectified by administration of a TrkB receptor agonist, suggesting reduced BDNF-TrkB signaling as a contributing factor. These results provide evidence that the function of fast-spiking interneurons is disrupted due to a deficiency in neurotrophin

Cycles of self-pulsations in a photonic integrated circuit.

Science.gov (United States)

Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

2015-12-01

We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

Science.gov (United States)

Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

2015-01-01

Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

Experiments with arbitrary networks in time-multiplexed delay systems

Science.gov (United States)

Hart, Joseph D.; Schmadel, Don C.; Murphy, Thomas E.; Roy, Rajarshi

2017-12-01

We report a new experimental approach using an optoelectronic feedback loop to investigate the dynamics of oscillators coupled on large complex networks with arbitrary topology. Our implementation is based on a single optoelectronic feedback loop with time delays. We use the space-time interpretation of systems with time delay to create large networks of coupled maps. Others have performed similar experiments using high-pass filters to implement the coupling; this restricts the network topology to the coupling of only a few nearest neighbors. In our experiment, the time delays and coupling are implemented on a field-programmable gate array, allowing the creation of networks with arbitrary coupling topology. This system has many advantages: the network nodes are truly identical, the network is easily reconfigurable, and the network dynamics occur at high speeds. We use this system to study cluster synchronization and chimera states in both small and large networks of different topologies.

An analysis of periodic solutions of bi-directional associative memory networks with time-varying delays

International Nuclear Information System (INIS)

Cao Jinde; Jiang Qiuhao

2004-01-01

In this Letter, several sufficient conditions are derived for the existence and uniqueness of periodic oscillatory solution for bi-directional associative memory (BAM) networks with time-varying delays by employing a new Lyapunov functional and an elementary inequality, and all other solutions of the BAM networks converge exponentially to the unique periodic solution. These criteria are presented in terms of system parameters and have important leading significance in the design and applications of periodic neural circuits for delayed BAM. As an illustration, two numerical examples are worked out using the results obtained

Design of an improved RCD buffer circuit for full bridge circuit

Science.gov (United States)

Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

2017-05-01

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

Analog circuit design designing dynamic circuit response

CERN Document Server

Feucht, Dennis

2010-01-01

This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

Synthetic multicellular oscillatory systems: controlling protein dynamics with genetic circuits

International Nuclear Information System (INIS)

Koseska, Aneta; Volkov, Evgenii; Kurths, Juergen

2011-01-01

Synthetic biology is a relatively new research discipline that combines standard biology approaches with the constructive nature of engineering. Thus, recent efforts in the field of synthetic biology have given a perspective to consider cells as 'programmable matter'. Here, we address the possibility of using synthetic circuits to control protein dynamics. In particular, we show how intercellular communication and stochasticity can be used to manipulate the dynamical behavior of a population of coupled synthetic units and, in this manner, finely tune the expression of specific proteins of interest, e.g. in large bioreactors.

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

Science.gov (United States)

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

Four-deep charge-time and pulse-width scaling discriminator for delay line MWPC's

International Nuclear Information System (INIS)

Lee, K.L.; Kirsten, F.A.; Grigorian, A.; Guiragossian, Z.G.T.

1976-01-01

A discriminator has been developed for digitizing both intercepted total charge and location of electromagnetic shower and particle trajectories in multi-wire proportional chambers read by delay lines. Determination of shower trajectory is aided by video signal integration followed by centroid-locating discrimination. Calibrated run-down of the signal integrating capacitor gives the charge information above a given threshold level. The discriminator is designed to handle up to four shower-induced video signals per event by incorporating steering circuits within the module. Each video signal is examined for time over an adjustable threshold. Video pulses with separation of less than 20 nsec are treated as a single pulse. Counter-logic circuits indicate the number of video signals digitized. These signal processing circuits provide a first level of data sifting which otherwise must be carried out with additional discriminator channels and added complexity in data recognition

Design of acoustic logging signal source of imitation based on field programmable gate array

International Nuclear Information System (INIS)

Zhang, K; Ju, X D; Lu, J Q; Men, B Y

2014-01-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes. (paper)

Decimal multiplication using compressor based-BCD to binary converter

Directory of Open Access Journals (Sweden)

Sasidhar Mukkamala

2018-02-01

Full Text Available The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit using parallel architecture. The proposed converters, along with binary coded decimal (BCD adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA and Application Specific Integrated Circuit (ASIC with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.

Development of ball surface acoustic wave trace moisture analyzer using burst waveform undersampling circuit

Science.gov (United States)

Tsuji, Toshihiro; Oizumi, Toru; Fukushi, Hideyuki; Takeda, Nobuo; Akao, Shingo; Tsukahara, Yusuke; Yamanaka, Kazushi

2018-05-01

The measurement and control of trace moisture, where the water concentration is lower than 1 ppmv [-76.2 °C for the frost point (°CFP)], are essential for improving the yield rate of semiconductor devices and for ensuring their reliability. A ball surface acoustic wave (SAW) sensor with a sol-gel silica coating exhibited useful characteristics for a trace moisture analyzer (TMA) when the temperature drift of the delay time output was precisely compensated using two-frequency measurement (TFM), where the temperature-compensated relative delay time change (RDTC) was obtained by subtracting the RDTC at the fundamental frequency from that at the third harmonic frequency on an identical propagation path. However, the cost of the measurement circuit was a problem. In this study, a burst waveform undersampling (BUS) circuit based on the theory of undersampling measurement was developed as a practical means. The BUS circuit was useful for precise temperature compensation of the RDTC, and the ball SAW TMA was prototyped by calibrating the RDTC using a TMA based on cavity ring-down spectroscopy (CRDS), which is the most reliable method for trace moisture measurement. The ball SAW TMA outputted a similar concentration to that obtained by the CRDS TMA, and its response time at a set concentration in N2 with a flow rate of 1 l/min was about half that of the CRDS TMA, suggesting that moisture of -80 °CFP was measured within only 1 min. The detection limit at a signal-to-noise ratio of 3 was estimated to be 0.05 ppbv, comparable with that of the CRDS TMA. From these results, it was demonstrated that a practical ball SAW TMA can be realized using the developed BUS circuit.

Addressing the third delay: implementing a novel obstetric triage system in Ghana.

Science.gov (United States)

Goodman, David M; Srofenyoh, Emmanuel K; Ramaswamy, Rohit; Bryce, Fiona; Floyd, Liz; Olufolabi, Adeyemi; Tetteh, Cecilia; Owen, Medge D

2018-01-01

Institutional delivery has been proposed as a method for reducing maternal morbidity and mortality, but little is known about how referral hospitals in low-resource settings can best manage the expected influx of patients. In this study, we assess the impact of an obstetric triage improvement programme on reducing hospital-based delay in a referral hospital in Accra, Ghana. An Active Implementation Framework is used to describe a 5-year intervention to introduce and monitor obstetric triage capabilities. Baseline data, collected from September to November 2012, revealed significant delays in patient assessment on arrival. A triage training course and monitoring of quality improvement tools occurred in 2013 and 2014. Implementation barriers led to the construction of a free-standing obstetric triage pavilion, opened January 2015, with dedicated midwives. Data were collected at three time intervals following the triage pavilion opening and compared with baseline including: referral indications, patient and labour characteristics, waiting time from arrival to assessment and the documentation of a care plan. An obstetric triage improvement programme reduced the median (IQR) patient waiting time from facility arrival to first assessment by a midwife from 40 min (15-100) to 5 min (2-6) (p<0.001) over the 5-year intervention. The triage pavilion enhanced performance resulting in the elimination of previous delays associated with the time of admission and disease acuity. Care plan documentation increased from 51% to 96%. Obstetric triage, when properly implemented, reduced delay in a busy, low-resource hospital. The implementation process was sustained under local leadership during transition to a new hospital.

The British flue gas desulphurisation programme

Energy Technology Data Exchange (ETDEWEB)

Longhurst, J.W.S.

1989-09-01

Retrofitting UK power plants with flue gas desulfurization equipment should reduce SO{sub 2} emission by around 15%. Three systems appear suitable for UK installations: limestone/gypsum, regenerative Wellman Lord, and spray dry. The CEGB has used limestone/gypsum at Drax A B, West Burton, Fawley and Kingsnorth, and Wellman Lord at Fiddlers Ferry. Despite the environmental benefits, however, there is concern that the negative aspects of the programme (choice of technology, waste disposal, by-product disposal) may delay implementation and thus threaten Britain's aim of 30% reduction by 1999. 3 tabs.

Factors associated with delays in treatment initiation after tuberculosis diagnosis in two districts of India.

Directory of Open Access Journals (Sweden)

Durba Paul

Full Text Available BACKGROUND: Excessive time between diagnosis and initiation of tuberculosis (TB treatment contributes to ongoing TB transmission and should be minimized. In India, Revised National TB Control Programme (RNTCP focuses on indicator start of treatment within 7 days of diagnosis for patients with sputum smear-positive PTB for monitoring DOTS implementation. OBJECTIVES: To determine length of time between diagnosis and initiation of treatment and factors associated with delays of more than 7 days in smear-positive pulmonary TB. METHODS: Using existing programme records such as the TB Register, treatment cards, and the laboratory register, we conducted a retrospective cohort study of all patients with smear-positive pulmonary TB registered from July-September 2010 in two districts in India. A random sample of patients with pulmonary TB who experienced treatment delay of more than 7 days was interviewed using structured questionnaire. RESULTS: 2027 of 3411 patients registered with pulmonary TB were smear-positive. 711(35% patients had >7 days between diagnosis and treatment and 262(13% had delays >15 days. Mean duration between TB diagnosis and treatment initiation was 8 days (range = 0-128 days. Odds of treatment delay >7 days was 1.8 times more likely among those who had been previously treated (95% confidence interval [CI] 1.5-2.3 and 1.6 (95% CI 1.3-1.8 times more likely among those diagnosed in health facilities without microscopy centers. The main factors associated with a delay >7 days were: patient reluctance to start a re-treatment regimen, patients seeking second opinions, delay in transportation of drugs to the DOT centers and delay in initial home visits. To conclude, treatment delay >7 days was associated with a number of factors that included history of previous treatment and absence of TB diagnostic services in the local health facility. Decentralized diagnostic facilities and improved referral procedures may reduce such treatment

MOS Current Mode Logic Near Threshold Circuits

Directory of Open Access Journals (Sweden)

Alexander Shapiro

2014-06-01

Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

Paediatric surgery outreach: analysis of referrals to a tertiary paediatric surgery service to plan an outreach programme Kwa-Zulu Natal, South Africa.

Science.gov (United States)

Manickchund, Yashoda; Hadley, G P

2017-10-01

Paediatric surgical disease is a neglected health problem. Patients travel great distances to tertiary level care for management. This study aimed at analysing referral patterns to design an outreach programme for paediatric surgery in KwaZulu Natal. Data forms of patients referred to the service between January and July 2016 were correlated with the clinical record. Delays in management were compared to morbidity and mortality. Out of 781, 158 referrals were accepted as emergencies. The majority (62%) were children aged < 1 year. Gastro-intestinal problems (38.4%) and congenital anomalies (26.9%) formed the majority. Patients who died had a significantly longer delay in transfer. Longer total delay was associated with statistically significant greater morbidity. In a setting where a large rural population is served by single-centre tertiary care, delays exist and contribute to morbidity. The authors advocate the establishment of an outreach programme to address these issues.

Pulse advancement and delay in an integrated optical two-port ring-resonator circuit: direct experimental observations

NARCIS (Netherlands)

Uranus, H.P.; Zhuang, L.; Roeloffzen, C.G.H.; Hoekstra, Hugo

We report experimental observations of the negative-group-velocity (v_g) phenomenon in an integrated-optical two-port ring-resonator circuit. We demonstrate that when the v_g is negative, the (main) peak of output pulse appears earlier than the peak of a reference pulse, while for a positive v_g,

A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

International Nuclear Information System (INIS)

Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

1991-01-01

The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

Emergency Diesel: Safety-related instrumentation and control with programmable logic controllers

International Nuclear Information System (INIS)

Breidenich, G.; Luedtke, M.

2004-01-01

This report presents a new concept for the design of emergency diesel equipment protection circuits as a part of the safety related instrumentation in the nuclear power plant Biblis, units A and B. The concept was implemented with state of the art SIMATIC S7/316 programmable logic controllers (PLCs) and can be adapted to any system with high availability requirements (e.g. power plant turbines, aircraft engines, mining pumps etc). (orig.)

Multi-channel control circuit for real-time control of events in Aditya tokamak

Energy Technology Data Exchange (ETDEWEB)

Edappala, Praveenlal, E-mail: praveen@ipr.res.in; Shah, Minsha; Rajpal, Rachana; Tanna, R.L.; Ghosh, Joydeep; Chattopadhyay, P.K.; Jha, R.

2016-11-15

Highlights: • Low cost microcontroller based control circuit. • The control hardware can be programmed/configured very easily for different applications. • Microcontroller programming is done in assembly language so that precise timing can be achieved with micro seconds resolution. • Successful implementation of this circuit in noisy tokamak environment. • Efficient noise and burst elimination. • Can be integrated in to the other subsystems. • Low cost solution for implementing feedback control in small and medium size tokamaks and other experiments requiring feedback control. - Abstract: Tokamak plasma is prone to many random events having potential for causing severe damages to the machine, such as disruptions, production and elimination of high-energy runaway electrons etc. These events can be mitigated by obtaining pre-cursor signal leading to these events and then taking proper measures just before their onset to avoid their happenings, like disruptions can be mitigated by massive gas injection or putting a bias voltage on an electrode placed inside the plasma, the runaways can be mitigated by gas injection and by applying specific magnetic fields. Hence for real time control of these events, the pre-cursors should be electronically recorded and the mitigation techniques should be initiated by sending triggers to their individual operational systems. To implement these methodologies of real-time controlling of events in Aditya Tokamak, a low cost multi-channel Micro-Controller based timing circuit is designed and developed in-house. This circuit first compares the precursor signals fed into it with the pre-set values and gives a trigger output whenever the signals overshoot the pre-set values. The circuit readies itself for operation along with start of the tokamak discharge and waits up to an initial pre-determined delay and then initiates a trigger at the time of overshooting of precursor signal. The circuit is fully integrated and assembled in

Single-chip pulse programmer for magnetic resonance imaging using a 32-bit microcontroller.

Science.gov (United States)

Handa, Shinya; Domalain, Thierry; Kose, Katsumi

2007-08-01

A magnetic resonance imaging (MRI) pulse programmer has been developed using a single-chip microcontroller (ADmicroC7026). The microcontroller includes all the components required for the MRI pulse programmer: a 32-bit RISC CPU core, 62 kbytes of flash memory, 8 kbytes of SRAM, two 32-bit timers, four 12-bit DA converters, and 40 bits of general purpose I/O. An evaluation board for the microcontroller was connected to a host personal computer (PC), an MRI transceiver, and a gradient driver using interface circuitry. Target (embedded) and host PC programs were developed to enable MRI pulse sequence generation by the microcontroller. The pulse programmer achieved a (nominal) time resolution of approximately 100 ns and a minimum time delay between successive events of approximately 9 micros. Imaging experiments using the pulse programmer demonstrated the effectiveness of our approach.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

Science.gov (United States)

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Scaling of graphene integrated circuits.

Science.gov (United States)

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Application of complex programmable logic devices in memory radiation effects test system

International Nuclear Information System (INIS)

Li Yonghong; He Chaohui; Yang Hailiang; He Baoping

2005-01-01

The application of the complex programmable logic device (CPLD) in electronics is emphatically discussed. The method of using software MAX + plus II and CPLD are introduced. A new test system for memory radiation effects is established by using CPLD devices-EPM7128C84-15. The old test system's function are realized and, moreover, a number of small scale integrated circuits are reduced and the test system's reliability is improved. (authors)

A novel integrated circuit for semiconductor radiation detectors with sparse readout

International Nuclear Information System (INIS)

Zhang Yacong; Chen Zhognjian; Lu Wengao; Zhao Baoying; Ji Lijiu

2008-01-01

A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 μ DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100 k/s per channel. (authors)

Engineering fluidic delays in paper-based devices using laser direct-writing.

Science.gov (United States)

He, P J W; Katis, I N; Eason, R W; Sones, C L

2015-10-21

We report the use of a new laser-based direct-write technique that allows programmable and timed fluid delivery in channels within a paper substrate which enables implementation of multi-step analytical assays. The technique is based on laser-induced photo-polymerisation, and through adjustment of the laser writing parameters such as the laser power and scan speed we can control the depth and/or the porosity of hydrophobic barriers which, when fabricated in the fluid path, produce controllable fluid delay. We have patterned these flow delaying barriers at pre-defined locations in the fluidic channels using either a continuous wave laser at 405 nm, or a pulsed laser operating at 266 nm. Using this delay patterning protocol we generated flow delays spanning from a few minutes to over half an hour. Since the channels and flow delay barriers can be written via a common laser-writing process, this is a distinct improvement over other methods that require specialist operating environments, or custom-designed equipment. This technique can therefore be used for rapid fabrication of paper-based microfluidic devices that can perform single or multistep analytical assays.

Mutations in KPTN Cause Macrocephaly, Neurodevelopmental Delay, and Seizures

Science.gov (United States)

Baple, Emma L.; Maroofian, Reza; Chioza, Barry A.; Izadi, Maryam; Cross, Harold E.; Al-Turki, Saeed; Barwick, Katy; Skrzypiec, Anna; Pawlak, Robert; Wagner, Karin; Coblentz, Roselyn; Zainy, Tala; Patton, Michael A.; Mansour, Sahar; Rich, Phillip; Qualmann, Britta; Hurles, Matt E.; Kessels, Michael M.; Crosby, Andrew H.

2014-01-01

The proper development of neuronal circuits during neuromorphogenesis and neuronal-network formation is critically dependent on a coordinated and intricate series of molecular and cellular cues and responses. Although the cortical actin cytoskeleton is known to play a key role in neuromorphogenesis, relatively little is known about the specific molecules important for this process. Using linkage analysis and whole-exome sequencing on samples from families from the Amish community of Ohio, we have demonstrated that mutations in KPTN, encoding kaptin, cause a syndrome typified by macrocephaly, neurodevelopmental delay, and seizures. Our immunofluorescence analyses in primary neuronal cell cultures showed that endogenous and GFP-tagged kaptin associates with dynamic actin cytoskeletal structures and that this association is lost upon introduction of the identified mutations. Taken together, our studies have identified kaptin alterations responsible for macrocephaly and neurodevelopmental delay and define kaptin as a molecule crucial for normal human neuromorphogenesis. PMID:24239382

Programmable electronic safety systems

International Nuclear Information System (INIS)

Parry, R.R.

1993-01-01

Traditionally safety systems intended for protecting personnel from electrical and radiation hazards at particle accelerator laboratories have made extensive use of electromechanical relays. These systems have the advantage of high reliability and allow the designer to easily implement fail-safe circuits. Relay based systems are also typically simple to design, implement, and test. As systems, such as those presently under development at the Superconducting Super Collider Laboratory (SSCL), increase in size, and the number of monitored points escalates, relay based systems become cumbersome and inadequate. The move toward Programmable Electronic Safety Systems is becoming more widespread and accepted. In developing these systems there are numerous precautions the designer must be concerned with. Designing fail-safe electronic systems with predictable failure states is difficult at best. Redundancy and self-testing are prime examples of features that should be implemented to circumvent and/or detect failures. Programmable systems also require software which is yet another point of failure and a matter of great concern. Therefore the designer must be concerned with both hardware and software failures and build in the means to assure safe operation or shutdown during failures. This paper describes features that should be considered in developing safety systems and describes a system recently installed at the Accelerator Systems String Test (ASST) facility of the SSCL

Memory, microprocessor, and ASIC

CERN Document Server

Chen, Wai-Kai

2003-01-01

System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

Circuit analysis for dummies

CERN Document Server

Santiago, John

2013-01-01

Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

Programmable neural processing on a smartdust for brain-computer interfaces.

Science.gov (United States)

Yuwen Sun; Shimeng Huang; Oresko, Joseph J; Cheng, Allen C

2010-10-01

Brain-computer interfaces (BCIs) offer tremendous promise for improving the quality of life for disabled individuals. BCIs use spike sorting to identify the source of each neural firing. To date, spike sorting has been performed by either using off-chip analysis, which requires a wired connection penetrating the skull to a bulky external power/processing unit, or via custom application-specific integrated circuits that lack the programmability to perform different algorithms and upgrades. In this research, we propose and test the feasibility of performing on-chip, real-time spike sorting on a programmable smartdust, including feature extraction, classification, compression, and wireless transmission. A detailed power/performance tradeoff analysis using DVFS is presented. Our experimental results show that the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

Science.gov (United States)

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Field programmable gate array reliability analysis using the dynamic flow graph methodology

Energy Technology Data Exchange (ETDEWEB)

McNelles, Phillip; Lu, Lixuan [Faculty of Energy Systems and Nuclear Science, University of Ontario Institute of Technology (UOIT), Ontario (Canada)

2016-10-15

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the 'IEEE 1164 standard', registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

A review of the U.K. fast reactor programme: March 1978

Energy Technology Data Exchange (ETDEWEB)

Smith, R D [United Kingdom Atomic Energy Authority, Risley (United Kingdom)

1978-07-01

The review of the UK fast reactor programme covers the description of Dounreay Fast Reactor shut down after seventeen years of successful operation; description of prototype fast reactor (PFR); core design parameters safety features and plant design for commercial demonstration fast reactor (CDFR). Engineering development is related to large sodium rigs, coolant circuit hydraulics and vibration, instrumentation and components. The subjects of interest are material development, sodium technology, fast reactor fuel, fuel cycle, reactor safety, reactor performance studies.

A review of the U.K. fast reactor programme: March 1978

International Nuclear Information System (INIS)

Smith, R.D.

1978-01-01

The review of the UK fast reactor programme covers the description of Dounreay Fast Reactor shut down after seventeen years of successful operation; description of prototype fast reactor (PFR); core design parameters safety features and plant design for commercial demonstration fast reactor (CDFR). Engineering development is related to large sodium rigs, coolant circuit hydraulics and vibration, instrumentation and components. The subjects of interest are material development, sodium technology, fast reactor fuel, fuel cycle, reactor safety, reactor performance studies

Current limiter circuit system

Science.gov (United States)

Witcher, Joseph Brandon; Bredemann, Michael V.

2017-09-05

An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

Loss-to-follow-up and delay to treatment initiation in Pakistan's national tuberculosis control programme.

Science.gov (United States)

Ali, Syed Mustafa; Naureen, Farah; Noor, Arif; Fatima, Irum; Viney, Kerri; Ishaq, Muhammad; Anjum, Naveed; Rashid, Aamna; Haider, Ghulam Rasool; Khan, Muhammad Aamir; Aamir, Javariya

2018-03-09

Researchers and policy-makers have identified loss to follow-up as a major programmatic problem. Therefore, the objective of this study is to quantify TB related pre-treatment loss to follow up and treatment delay in private sector health care facilities in Pakistan. This was a retrospective, descriptive cohort study using routinely collected programmatic data from TB referral, diagnosis and treatment registers. Data from 48 private healthcare facilities were collected using an online questionnaire prepared in ODK Collect, for the period October 2015 to March 2016. Data were analysed using SPSS. We calculated the: (1) number and proportion of patients who were lost to follow-up during the diagnostic period, (2) number and proportion of patients with pre-treatment loss to follow-up, and (3) the number of days between diagnosis and initiation of treatment. One thousand five hundred ninety-six persons with presumptive TB were referred to the laboratory. Of these, 96% (n = 1538) submitted an on-the-spot sputum sample. Of the 1538 people, 1462 (95%) people subsequently visited the laboratory to submit the early morning (i.e. the second) sample. Hence, loss to follow-up during the diagnostic process was 8% overall (n = 134). Of the 1462 people who submitted both sputum samples, 243 (17%) were diagnosed with sputum smear-positive pulmonary TB and 231 were registered for anti-TB treatment, hence, loss in the pre-treatment phase was 4.9% (n = 12). 152 persons with TB (66%) initiated TB treatment either on the day of TB diagnosis or the next day. A further 79 persons with TB (34%) commenced TB treatment within a mean time of 7 days (range 2 to 64 days). Concentrated efforts should be made by the National TB Control Programme to retain TB patients and innovative methods such as text reminders and behavior change communication may need to be used and tested.

The voltage—current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

International Nuclear Information System (INIS)

Bao Bo-Cheng; Feng Fei; Dong Wei; Pan Sai-Hu

2013-01-01

A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage—current relationships (VCRs) between two parallel memristive circuits — a parallel memristor and capacitor circuit (the parallel MC circuit), and a parallel memristor and inductor circuit (the parallel ML circuit) — are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and experimental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results

Subwavelength grating enabled on-chip ultra-compact optical true time delay line.

Science.gov (United States)

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R

2016-07-26

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth.

Structure of the EGF receptor transactivation circuit integrates multiple signals with cell context

Energy Technology Data Exchange (ETDEWEB)

Joslin, Elizabeth J.; Shankaran, Harish; Opresko, Lee K.; Bollinger, Nikki; Lauffenburger, Douglas A.; Wiley, H. S.

2010-05-10

Transactivation of the epidermal growth factor receptor (EGFR) has been proposed to be a mechanism by which a variety of cellular inputs can be integrated into a single signaling pathway, but the regulatory topology of this important system is unclear. To understand the transactivation circuit, we first created a “non-binding” reporter for ligand shedding. We then quantitatively defined how signals from multiple agonists were integrated both upstream and downstream of the EGFR into the extracellular signal regulated kinase (ERK) cascade in human mammary epithelial cells. We found that transactivation is mediated by a recursive autocrine circuit where ligand shedding drives EGFR-stimulated ERK that in turn drives further ligand shedding. The time from shedding to ERK activation is fast (<5 min) whereas the recursive feedback is slow (>15 min). Simulations showed that this delay in positive feedback greatly enhanced system stability and robustness. Our results indicate that the transactivation circuit is constructed so that the magnitude of ERK signaling is governed by the sum of multiple direct inputs, while recursive, autocrine ligand shedding controls signal duration.

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

Science.gov (United States)

2010-07-01

... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

Directory of Open Access Journals (Sweden)

David Bol

2011-01-01

Full Text Available Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.

Spent Fuel Challenges Facing Small and New Nuclear Programmes

International Nuclear Information System (INIS)

McCombie, C.

2015-01-01

In order to ensure that the radioactive wastes in any country are managed safely, it is necessary to have an established legislative and regulatory framework and also to create the necessary organizations for implementation and for oversight of waste management operations and facility development. Guidance on these issues is given in the Joint Convention and a number of other IAEA documents. The IAEA, and also the EC, have in addition published key overarching strategic advisory documents for new nuclear programmes. These tend to imply that all nuclear programmes, however large or small, should be pressing ahead urgently towards early implementation of geological repositories. In practice, however, in small programmes there are neither economic nor technical drivers for early implementation of deep geological repositories; constructing simpler facilities for the disposal of the larger volume of low-level waste has higher priority. Nevertheless, in all countries political decisions have to be taken and policies set in place to ensure that geological disposal will implemented without unjustified delay. This paper distils out a set of key messages for small programmes. Amongst the most critical are the following. Even if disposal is far off, planning and organization should begin at the initiation of the programme; this can help with technical and economic optimization and (importantly) also with public and political acceptance. Important lessons can be learned from advanced programmes — but these must be adapted to allow for the different boundary conditions of new and small programmes. The key differences relate to the timescales involved, and the resources available. There is a range of waste management and waste disposal options open to new programmes. It is not necessary to choose definitive solutions at the outset; options can be kept open, but a minimum level of engagement is required for all open options. (author)

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

International Nuclear Information System (INIS)

Bonacini, S.

2007-11-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

Programmer for automatic gamma spectrometry; Ordonnateur de sequence pour spectrometrie gamma automatique

Energy Technology Data Exchange (ETDEWEB)

Romanetti, R [Commissariat a l' Energie Atomique, Cadarache (France). Centre d' Etudes Nucleaires

1968-04-01

With this apparatus, which is constructed of logical integrated circuits, it is possible both to synchronize an automatic gamma spectrometry assembly and to record the spectra on punched cards. An IBM terminal will make it possible with the help of analysis by the least squares method and by a direct dialogue with an IBM 360 computer to obtain analytical results almost instantaneously. (author) [French] Cet appareil, realise en circuits integres logiques, permet d'une part de synchroniser un ensemble automatique de spectrometrie gamma et d'autre part d'enregistrer les spectres sur cartes perforees. Un terminal IBM permettra, a l'aide d'un programme d'analyse par la methode des moindres carres et par un dialogue direct avec un ordinateur IBM 360, de disposer presque intanstanement des resultats des analyses. (auteur)

30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

Science.gov (United States)

2010-07-01

... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

Science.gov (United States)

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

FLATT - a computer programme for calculating flow and temperature transients in nuclear fuels

International Nuclear Information System (INIS)

Venkat Raj, V.; Koranne, S.M.

1976-01-01

FLATT is a computer code written in Fortran language for BESM-6 computer. The code calculates the flow transients in the coolant circuit of a nuclear reactor, caused by pump failure, and the consequent temperature transients in the fuel, clad, and the coolant. In addition any desired flow transient can be fed into the programme and the resulting temperature transients can be calculated. A case study is also presented. (author)

Finnish research programmes on nuclear power plant safety

International Nuclear Information System (INIS)

Puska, E. K.

2010-01-01

The current Finnish national research programme on nuclear power plant safety SAFIR2010 for the years 2007-2010 as well as the coming SAFIR2014 programme for the years 2011-2014 are based on the chapter 7a, 'Ensuring expertise', of the Finnish Nuclear Energy Act. The objective of this chapter is realised in the research work and education of experts in the projects of these research programmes. SAFIR2010 research programme is divided in eight research areas that are Organisation and human, Automation and control room, Fuel and reactor physics, Thermal hydraulics, Severe accidents, Structural safety of reactor circuit, Construction safety, and Probabilistic Safety Analysis (PSA). All the research areas include both projects in their own area and interdisciplinary co-operational projects. Research projects of the programme are chosen on the basis of annual call for proposals. In 2010 research is carried out in 33 projects in SAFIR2010. VTT is the responsible research organisation in 26 of these projects and VTT is also the coordination unit of SAFIR2010 and SAFIR2014. In 2007-2009 SAFIR2010 produced 497 Specified research results (Deliverables), 618 Publications, and 33 Academic degrees. SAFIR2010 programme covers approximately half of the reactor safety research volume in Finland currently. In 2010 the programme volume is EUR 7.1 million and 47 person years. The major funding partners are VYR with EUR 2.96 million, VTT with EUR 2.66 million, Fortum with EUR 0.28 million, TVO with EUR 0.19 million, NKS with EUR 0.15 million, EU with only EUR 0.03 million and other partners with EUR 0.85 million. The new decisions-in-principle on Olkiluoto unit 4 for Teollisuuden Voima and new nuclear power plant for Fennovoima ratified by the Finnish Parliament on 1 July 2010 increase the annual funding collected according to the Finnish Nuclear Energy Act from Fennovoima, Fortum and Teollisuuden Voima for the SAFIR2014 programme to EUR 5.2 million from the current level of EUR 3

Power ion beam production in a magnetic-insulated diode placed in a circuit with an inductive storage with a plasmoerosion circuit breaker

International Nuclear Information System (INIS)

Anan'in, P.S.; Karpov, V.B.; Krasik, Ya.E.; Paul', E.A.

1991-01-01

Consideration is given to results of experimental studies of modes of operation of plasma current breaker and magnetic insulated diode, placed parallel in a circuit with inductive storage and microsecond generator, as well as parameters of high-power ion beam, generated in gas-filled diode. Magnetic field of mirror configuration, which enabled to locate the gas-filled diode dose to breaking region was used for decrease of electrodynamic plasma transfer. It is shown that time delay (of the order of ten and more) of power maximum in gas-filled diode with respect to power maximum in plasma breaker is observed when using passive plasma source on anode

Volumetric and chemical control auxiliary circuit for a PWR primary circuit

International Nuclear Information System (INIS)

Costes, D.

1990-01-01

The volumetric and chemical control circuit has an expansion tank with at least one water-steam chamber connected to the primary circuit by a sampling pipe and a reinjection pipe. The sampling pipe feeds jet pumps controlled by valves. An action on these valves and pumps regulates the volume of the water in the primary circuit. A safety pipe controlled by a flap automatically injects water from the chamber into the primary circuit in case of ruptures. The auxiliary circuit has also systems for purifying the water and controlling the boric acid and hydrogen content [fr

Stability Analysis of Nonlinear Time–Delayed Systems with Application to Biological Models

Directory of Open Access Journals (Sweden)

Kruthika H.A.

2017-03-01

Full Text Available In this paper, we analyse the local stability of a gene-regulatory network and immunotherapy for cancer modelled as nonlinear time-delay systems. A numerically generated kernel, using the sum-of-squares decomposition of multivariate polynomials, is used in the construction of an appropriate Lyapunov–Krasovskii functional for stability analysis of the networks around an equilibrium point. This analysis translates to verifying equivalent LMI conditions. A delay-independent asymptotic stability of a second-order model of a gene regulatory network, taking into consideration multiple commensurate delays, is established. In the case of cancer immunotherapy, a predator–prey type model is adopted to describe the dynamics with cancer cells and immune cells contributing to the predator–prey population, respectively. A delay-dependent asymptotic stability of the cancer-free equilibrium point is proved. Apart from the system and control point of view, in the case of gene-regulatory networks such stability analysis of dynamics aids mimicking gene networks synthetically using integrated circuits like neurochips learnt from biological neural networks, and in the case of cancer immunotherapy it helps determine the long-term outcome of therapy and thus aids oncologists in deciding upon the right approach.

A computer programme to monitor the performance of an X-ray fluorescence spectrometer

International Nuclear Information System (INIS)

Simpolo, G.F.

1985-01-01

A BASIC computer programme has been developed that measures the long- and short-term stability of an X-ray spectrometer and operational errors (and compares them with the limits specified by the manufacturer) and the dead time of the associated detectors. The programme also carries out checks on the spectrometer with regard to the performance of different combinations of the crystals, the detectors, the collimators, the sin 2 THETA angles, the apertures, the tracking of the sin 2 THETA amplifier, the operation of the second-order spectrum circuits, the operation of the automatic pulse-height analyser, the condition of the detectors, the condition of the X-ray tube, spectral contamination by the tube spectrum, and physical contamination by analytical specimens. Although the measurements take 15 hours, there is no disruption to normal, routine laboratory work since the measurements can be made automatically after routine work has been completed. Only four sample positions are required for this monitoring programme

Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

Energy Technology Data Exchange (ETDEWEB)

Bugnet, H.

1995-11-21

The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

Intuitive analog circuit design

CERN Document Server

Thompson, Marc

2013-01-01

Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

The circuit designer's companion

CERN Document Server

Williams, Tim

1991-01-01

The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1972-01-01

Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

Monitoring Sodium Circuits and ACSR cables using Fiber Optic Sensors

International Nuclear Information System (INIS)

Kasinathan, M.; Sosamma, S.; Babu-Rao, C.; Kumar, Anish; Purna-Chandra-Rao, B.; Murali, N; Jayakumar, T.

2013-06-01

Raman Distributed Temperature Sensors (RDTS) are attractive for the monitoring of coolant loop systems in nuclear power plants and monitoring of overhead power transmission lines. This paper discusses deployment of RDTS on double walled pipelines of primary sodium circuits in Fast Breeder Reactors (FBR). It is demonstrated as a proof-of-concept on a test loop with water as the leaking medium. Path delay multiplexing is adopted to improve the spatial resolution from 1.02 m to 0.5 m. A second application focuses on the influence of environmental factors on the detectability of defects in the ACSR cables using RDTS. (authors)

Signal sampling circuit

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2011-01-01

A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

Signal sampling circuit

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2010-01-01

A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

Electric circuits essentials

CERN Document Server

REA, Editors of

2012-01-01

REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

CERN Document Server

Bonacini, Sandro; Kloukinas, Kostas

2007-01-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

Approximate circuits for increased reliability

Science.gov (United States)

Hamlet, Jason R.; Mayo, Jackson R.

2015-08-18

Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

Two-phase flow in the cooling circuit of a cryogenic rocket engine

Science.gov (United States)

Preclik, D.

1992-07-01

Transient two-phase flow was investigated for the hydrogen cooling circuit of the HM7 rocket engine. The nuclear reactor code ATHLET/THESEUS was adapted to cryogenics and applied to both principal and prototype experiments for validation and simulation purposes. The cooling circuit two-phase flow simulation focused on the hydrogen prechilling and pump transient phase prior to ignition. Both a single- and a multichannel model were designed and employed for a valve leakage flow, a nominal prechilling flow, and a prechilling with a subsequent pump-transient flow. The latter case was performed in order to evaluate the difference between a nominal and a delayed turbo-pump start-up. It was found that an extension of the nominal prechilling sequence in the order of 1 second is sufficient to finally provide for liquid injection conditions of hydrogen which, as commonly known, is undesirable for smooth ignition and engine starting transients.

Short-circuit logic

NARCIS (Netherlands)

Bergstra, J.A.; Ponse, A.

2010-01-01

Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of

Delayed Dopamine Signaling of Energy Level Builds Appetitive Long-Term Memory in Drosophila

Directory of Open Access Journals (Sweden)

Pierre-Yves Musso

2015-02-01

Full Text Available Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level that the activity of two pairs of dopaminergic neurons is necessary and sufficient to signal energy level to the olfactory memory center. Accordingly, we have identified in these dopaminergic neurons a delayed calcium trace that correlates with appetitive long-term memory formation. Altogether, these findings demonstrate that the Drosophila brain remembers food quality through a two-step mechanism that consists of the integration of olfactory and gustatory sensory information and then post-ingestion energetic value.

Delayed dopamine signaling of energy level builds appetitive long-term memory in Drosophila.

Science.gov (United States)

Musso, Pierre-Yves; Tchenio, Paul; Preat, Thomas

2015-02-24

Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level that the activity of two pairs of dopaminergic neurons is necessary and sufficient to signal energy level to the olfactory memory center. Accordingly, we have identified in these dopaminergic neurons a delayed calcium trace that correlates with appetitive long-term memory formation. Altogether, these findings demonstrate that the Drosophila brain remembers food quality through a two-step mechanism that consists of the integration of olfactory and gustatory sensory information and then post-ingestion energetic value. Copyright © 2015 The Authors. Published by Elsevier Inc. All rights reserved.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Science.gov (United States)

Gupta, Neha; Parihar, Priyanka; Neema, Vaibhav

2018-04-01

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

International Nuclear Information System (INIS)

Holland, S.

1991-11-01

A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

Temporary authorization for use: does the French patient access programme for unlicensed medicines impact market access after formal licensing?

Science.gov (United States)

Degrassat-Théas, Albane; Paubel, Pascal; Parent de Curzon, Olivier; Le Pen, Claude; Sinègre, Martine

2013-04-01

To reach the French market, a new drug requires a marketing authorization (MA) and price and reimbursement agreements. These hurdles could delay access to new and promising drugs. Since 1992, French law authorizes the use of unlicensed drugs on an exceptional and temporary basis through a compassionate-use programme, known as Temporary Authorization for Use (ATU). This programme was implemented to improve early access to drugs under development or authorized abroad. However, it is suspected to be inflationary, bypassing public bodies in charge of health technology assessment (HTA) and of pricing. The aim of this study is to observe the market access after the formal licensing of drugs that went through this compassionate-use programme. We included all ATUs that received an MA between 1 January 2005 and 30 June 2010. We first examined market access delays from these drugs using the standard administrative path. We positioned this result in relation to launch delays observed in France (for all outpatient drugs) and in other major European markets. Second, we assessed the bargaining power of a hospital purchaser after those drugs had obtained an MA by calculating the price growth rate after the approval. During the study period, 77 ATUs were formally licensed. The study concluded that, from the patient's perspective, licensing and public bodies' review time was shortened by a combined total of 36 months. The projected 11-month review time of public bodies may be longer than delays usually observed for outpatient drugs. Nonetheless, the study revealed significant benefits for French patient access based on comparable processing to launch time with those of other European countries with tight price control policies. In return, a 12 % premium, on average, is paid to pharmaceutical companies while drugs are under this status (sub-analysis on 56 drugs). In many instances, the ATU programme responds to a public health need by accelerating the availability of new drugs

Multi-channel logical circuit module used for high-speed, low amplitude signals processing and QDC gate signals generation

International Nuclear Information System (INIS)

Su Hong; Li Xiaogang; Zhu Haidong; Ma Xiaoli; Yin Weiwei; Li Zhuyu; Jin Genming; Wu Heyu

2001-01-01

A new kind of logical circuit will be introduced in brief. There are 16 independent channels in the module. The module receives low amplitude signals(≥40 mV), and processes them to amplify, shape, delay, sum and etc. After the processing each channel produces 2 pairs of ECL logical signal to feed the gate of QDC as the gate signal of QDC. The module consists of high-speed preamplifier unit, high-speed discriminate unit, delaying and shaping unit, summing unit and trigger display unit. The module is developed for 64 CH. 12 BIT Multi-event QDC. The impedance of QDC is 110 Ω. Each gate signal of QDC requires a pair of differential ECL level, Min. Gate width 30 ns and Max. Gate width 1 μs. It has showed that the outputs of logical circuit module satisfy the QDC requirements in experiment. The module can be used on data acquisition system to acquire thousands of data at high-speed ,high-density and multi-parameter, in heavy particle nuclear physics experiment. It also can be used to discriminate multi-coincidence events

Two-dimensional non-volatile programmable p-n junctions

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

The Implementation and Evaluation of a Project-Oriented Problem-Based Learning Module in a First Year Engineering Programme

Science.gov (United States)

McLoone, Seamus C.; Lawlor, Bob J.; Meehan, Andrew R.

2016-01-01

This paper describes how a circuits-based project-oriented problem-based learning educational model was integrated into the first year of a Bachelor of Engineering in Electronic Engineering programme at Maynooth University, Ireland. While many variations of problem based learning exist, the presented model is closely aligned with the model used in…

Load testing circuit

DEFF Research Database (Denmark)

2009-01-01

A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...

Timergenerator circuits manual

CERN Document Server

Marston, R M

2013-01-01

Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

Design of arithmetic circuits in quantum dot cellular automata nanotechnology

CERN Document Server

Sridharan, K

2015-01-01

This research monograph focuses on the design of arithmetic circuits in Quantum Dot Cellular Automata (QCA). Using the fact that the 3-input majority gate is a primitive in QCA, the book sets out to discover hitherto unknown properties of majority logic in the context of arithmetic circuit designs. The pursuit for efficient adders in QCA takes two forms. One involves application of the new results in majority logic to existing adders. The second involves development of a custom adder for QCA technology. A QCA adder named as hybrid adder is proposed and it is shown that it outperforms existing multi-bit adders with respect to area and delay. The work is extended to the design of a low-complexity multiplier for signed numbers in QCA. Furthermore the book explores two aspects unique to QCA technology, namely thermal robustness and the role of interconnects. In addition, the book introduces the reader to QCA layout design and simulation using QCADesigner. Features & Benefits: This research-based book: ·  �...

30 CFR 75.601-1 - Short circuit protection; ratings and settings of circuit breakers.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit protection; ratings and settings... Trailing Cables § 75.601-1 Short circuit protection; ratings and settings of circuit breakers. Circuit breakers providing short circuit protection for trailing cables shall be set so as not to exceed the...

Computational modeling of stuttering caused by impairments in a basal ganglia thalamo-cortical circuit involved in syllable selection and initiation

Science.gov (United States)

Civier, Oren; Bullock, Daniel; Max, Ludo; Guenther, Frank H.

2013-01-01

A typical white-matter integrity and elevated dopamine levels have been reported for individuals who stutter. We investigated how such abnormalities may lead to speech dysfluencies due to their effects on a syllable-sequencing circuit that consists of basal ganglia (BG), thalamus, and left ventral premotor cortex (vPMC). “Neurally impaired” versions of the neurocomputational speech production model GODIVA were utilized to test two hypotheses: (1) that white-matter abnormalities disturb the circuit via corticostriatal projections carrying copies of executed motor commands, and (2) that dopaminergic abnormalities disturb the circuit via the striatum. Simulation results support both hypotheses: in both scenarios, the neural abnormalities delay readout of the next syllable’s motor program, leading to dysfluency. The results also account for brain imaging findings during dysfluent speech. It is concluded that each of the two abnormality types can cause stuttering moments, probably by affecting the same BG-thalamus-vPMC circuit. PMID:23872286

Embedding the dynamics of a single delay system into a feed-forward ring.

Science.gov (United States)

Klinshov, Vladimir; Shchapin, Dmitry; Yanchuk, Serhiy; Wolfrum, Matthias; D'Huys, Otti; Nekorkin, Vladimir

2017-10-01

We investigate the relation between the dynamics of a single oscillator with delayed self-feedback and a feed-forward ring of such oscillators, where each unit is coupled to its next neighbor in the same way as in the self-feedback case. We show that periodic solutions of the delayed oscillator give rise to families of rotating waves with different wave numbers in the corresponding ring. In particular, if for the single oscillator the periodic solution is resonant to the delay, it can be embedded into a ring with instantaneous couplings. We discover several cases where the stability of a periodic solution for the single unit can be related to the stability of the corresponding rotating wave in the ring. As a specific example, we demonstrate how the complex bifurcation scenario of simultaneously emerging multijittering solutions can be transferred from a single oscillator with delayed pulse feedback to multijittering rotating waves in a sufficiently large ring of oscillators with instantaneous pulse coupling. Finally, we present an experimental realization of this dynamical phenomenon in a system of coupled electronic circuits of FitzHugh-Nagumo type.

Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II.

Science.gov (United States)

Keivanian, Farshid; Mehrshad, Nasser; Bijari, Abolfazl

2016-01-01

D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study. The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.

Sequential circuit design for radiation hardened multiple voltage integrated circuits

Science.gov (United States)

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

A review of the HDR research programme

International Nuclear Information System (INIS)

Talja, H.; Koski, K.; Rintamaa, R.; Keskinen, R.

1995-10-01

In the German HDR (Heissdampfreaktor, hot steam reactor) reactor safety programme, experiments and simulating numerical analyses have been undertaken since 1976 to study the integrity and safety of light water reactors under operational and faulted conditions. The last experiments of the programme were conducted in 1991. The post test analyses have been finished by March 1994 and the last final reports were obtained a few months later. The report aims to inform the utilities and the regulatory body of Finland about the contents of the lokset HDR research programme and to consider the applicability of the results to safety analyses of Finnish nuclear power plants. The report centers around the thermal shock and piping component experiments within the last or third phase of the HDR programme. Investigations into severe reactor accidents, fire safety and non-destructive testing, also conducted during the third phase, are not considered. The report presents a review of the following experiment groups: E21 (crack growth under corrosive conditions, loading due to thermal stratification), E22 (leak rate and leak detection experiments of through-cracked piping), E23 (thermal transient and stratification experiments for a pipe nozzle), E31 (vibration of cracked piping due to blow down and closure of isolation valve), E32 (seismically induced vibrations of cracked piping), E33 (condensation phenomena in horizontal piping during emergency cooling). A comprehensive list of reference reports, received by VTT and containing a VTT more detailed description, is given for each experiment group. The review is focused on the loading conditions and their theoretical modelling. A comparison of theoretical and experimental results is presented for each experiment group. The safety margins are finally assessed with special reference to leak-before-break, a well known principle for assuring the integrity of primary circuit piping of nuclear power plants. (orig.) (71 figs., 5 tabs.)

Low latency asynchronous interface circuits

Science.gov (United States)

Sadowski, Greg

2017-06-20

In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

Institutional provisions for administration of rural development programmes: experience from Fadama 111 development programme in Taraba state, Nigeria

Directory of Open Access Journals (Sweden)

M.U. Dimelu

2014-12-01

Full Text Available The study examined institutional provisions in the implementation of Fadama 111 Development Project in Taraba State, Nigeria during 2008-2013. All the staff of the project (57 from eight out of 16 local government areas participated in the programme was used in the study. Data were collected with questionnaire and analysed using descriptive statistics. The results showed strong linkages of the state Fadama coordinating office with government parastaltals and organizations at different levels of the project implementation. There were strong adherence to rules and regulations guiding staff recruitment, financial management, preparation of local development plan, environmental compliance and friendliness, and group formation. The project was constrained by several institutional factors namely delay in the payment of counterpart fund by the government (M=3.39, lack of transport and other logistic supports (M=3.06, lack of payment of counterpart fund by the government (M=3.04 and others. The study recommends that policy makers and development planner should ensure functional mechanisms that could foster and enhance linkages, and support adherence to rules and regulations prescribed for implementation of development programmes.

Piezoelectric drive circuit

Science.gov (United States)

Treu, C.A. Jr.

1999-08-31

A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

Application of programmable controllers to oil fired boiler light-off system

International Nuclear Information System (INIS)

Copeland, H.C.; Gallaway, E.N.

1978-01-01

A programmable controller has been used to improve the reliability of an oil-fired boiler burner control system. An outdated and failing Germanium discrete transistor logic control system was replaced with a modern solid state large scale integrated circuit programmable controller. The ease of making this conversion at a modest expenditure during a limited boiler outage is explained, as well as pitfalls and problems encountered. Light-off reliability with fuel savings were prime objectives. The boiler, rated at 575,000 lb/hr at 450 psig, is used as a backup steam supply for the dual purpose N Reactor at Hanford, Washington, which supplies 860 MWe to the Bonneville Power Administration and weapons grade Plutonium for the Department of Energy. High reliability in light-off and load ascension from standby is required of the boiler which serves as the backup power supply for the reactor

A Simple Snap Oscillator with Coexisting Attractors, Its Time-Delayed Form, Physical Realization, and Communication Designs

Science.gov (United States)

Rajagopal, Karthikeyan; Jafari, Sajad; Akgul, Akif; Karthikeyan, Anitha; Çiçek, Serdar; Shekofteh, Yasser

2018-05-01

In this paper, we report a novel chaotic snap oscillator with one nonlinear function. Dynamic analysis of the system shows the existence of bistability. To study the time delay effects on the proposed snap oscillator, we introduce multiple time delay in the fourth state equation. Investigation of dynamical properties of the time-delayed system shows that the snap oscillator exhibits the same multistable properties as the nondelayed system. The new multistable hyperjerk chaotic system has been tested in chaos shift keying and symmetric choc shift keying modulated communication designs for engineering applications. It has been determined that the symmetric chaos shift keying modulated communication system implemented with the new chaotic system is more successful than the chaos shift keying modulation for secure communication. Also, circuit implementation of the chaotic snap oscillator with tangent function is carried out showing its feasibility.

Feedback in analog circuits

CERN Document Server

Ochoa, Agustin

2016-01-01

This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

International Nuclear Information System (INIS)

Fiorini, C.; Porro, M.

2006-01-01

We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

The Nordic programme for nuclear safety 1990-1993

International Nuclear Information System (INIS)

1991-08-01

The status report concerning the Nordic Nuclear Safety Programme for 1990-1993 contains a summary of the current situation regarding research projects, presented by the four coordinators, and a survey of the related economy. It is stated that all seventeen projects are running satisfactorily and a number of working descriptions have been published. Project leaders work with contracts with consultant firms, research organizations and individuals, contact meetings including lectures and discussions, mini-seminars where participants actually work at the same time, coordination of nationally financed research projects and individual contributions. Problems related to a certain lack of qualified persons for whom it is possible to coordinate this Nordic work with their daily responsibilities have led to delays in relation to the working plans and this has resulted in the fact that not all the grants have been utilized as yet. Sub-programmes are dealt with individually, and lists of publications are presented. (AB) (10 refs.)

Fine Output Voltage Control Method considering Time-Delay of Digital Inverter System for X-ray Computed Tomography

Science.gov (United States)

Shibata, Junji; Kaneko, Kazuhide; Ohishi, Kiyoshi; Ando, Itaru; Ogawa, Mina; Takano, Hiroshi

This paper proposes a new output voltage control for an inverter system, which has time-delay and nonlinear load. In the next generation X-ray computed tomography of a medical device (X-ray CT) that uses the contactless power transfer method, the feedback signal often contains time-delay due to AD/DA conversion and error detection/correction time. When the PID controller of the inverter system is received the adverse effects of the time-delay, the controller often has an overshoot and a oscillated response. In order to overcome this problem, this paper proposes a compensation method based on the Smith predictor for an inverter system having a time-delay and the nonlinear loads which are the diode bridge rectifier and X-ray tube. The proposed compensation method consists of the hybrid Smith predictor system based on an equivalent analog circuit and DSP. The experimental results confirm the validity of the proposed system.

A One-to-One Programme for At-Risk Readers Delivered by Older Adult Volunteers

Science.gov (United States)

Fives, Allyn; Kearns, Noreen; Devaney, Carmel; Canavan, John; Russell, Dan; Lyons, Rena; Eaton, Patricia; O'Brien, Aoife

2013-01-01

This paper is based on a randomized controlled trial (RCT) evaluation of a reading programme delivered by older adult volunteers for at-risk early readers. Wizards of Words (WoW) was targeted at socially disadvantaged children in first and second grade experiencing delays in reading but who were not eligible for formal literacy supports. The…

A Programmable Biopotential Aquisition Front-end with a Resistance-free Current-balancing Instrumentation Amplifier

Directory of Open Access Journals (Sweden)

FARAGO, P.

2018-05-01

Full Text Available The development of wearable biomedical equipment benefits from low-power and low-voltage circuit techniques for reduced battery size and battery, or even battery-less, operation. This paper proposes a fully-differential low-power resistance-free programmable instrumentation amplifier for the analog front-end of biopotential monitoring systems. The proposed instrumentation amplifier implements the current balancing technique. Low power consumption is achieved with subthreshold biasing. To reduce chip area and enable integration, passive resistances have been replaced with active equivalents. Accordingly, the instrumentation amplifier gain is expressed as the ratio of two transconductance values. The proposed instrumentation amplifier exhibits two degrees of freedom: one to set the desired range and the other for fine-tuning of the voltage gain. The proposed IA is employed in a programmable biopotential acquisition front-end. The programmable frequency-selective behavior is achieved by having the lower cutoff frequency of a Gm-C Tow-Thomas biquad varied in a constant-C tuning approach. The proposed solutions and the programmability of the operation parameters to the specifications of particular bio-medical signals are validated on a 350nm CMOS process.

Synthetic biology devices and circuits for RNA-based 'smart vaccines': a propositional review.

Science.gov (United States)

Andries, Oliwia; Kitada, Tasuku; Bodner, Katie; Sanders, Niek N; Weiss, Ron

2015-02-01

Nucleic acid vaccines have been gaining attention as an alternative to the standard attenuated pathogen or protein based vaccine. However, an unrealized advantage of using such DNA or RNA based vaccination modalities is the ability to program within these nucleic acids regulatory devices that would provide an immunologist with the power to control the production of antigens and adjuvants in a desirable manner by administering small molecule drugs as chemical triggers. Advances in synthetic biology have resulted in the creation of highly predictable and modular genetic parts and devices that can be composed into synthetic gene circuits with complex behaviors. With the recent advent of modified RNA gene delivery methods and developments in the RNA replicon platform, we foresee a future in which mammalian synthetic biologists will create genetic circuits encoded exclusively on RNA. Here, we review the current repertoire of devices used in RNA synthetic biology and propose how programmable 'smart vaccines' will revolutionize the field of RNA vaccination.

Analog circuits cookbook

CERN Document Server

Hickman, Ian

2013-01-01

Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.

Electric circuits and signals

CERN Document Server

Sabah, Nassir H

2007-01-01

Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...

[Shunt and short circuit].

Science.gov (United States)

Rangel-Abundis, Alberto

2006-01-01

Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

Energy Technology Data Exchange (ETDEWEB)

Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

2015-01-21

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

International Nuclear Information System (INIS)

Zhang, Jie; Zhou, Dongming

2015-01-01

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage

Macromodels of digital integrated circuits for program packages of circuit engineering design

Science.gov (United States)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

Science.gov (United States)

Wu, Chung-Yu; Cheng, Cheng-Hsiang; Chen, Zhi-Xin

2018-06-01

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

Effect of a structured diabetes education programme in primary care on hospitalizations and emergency department visits among people with Type 2 diabetes mellitus: results from the Patient Empowerment Programme.

Science.gov (United States)

Wong, C K H; Wong, W C W; Wan, Y F; Chan, A K C; Chan, F W K; Lam, C L K

2016-10-01

To assess whether a structured diabetes education programme, the Patient Empowerment Programme, was associated with a lower rate of all-cause hospitalization and emergency department visits in a population-based cohort of patients with Type 2 diabetes mellitus in primary care. A cohort of 24 250 patients was evaluated using a linked administrative database during 2009-2013. We selected 12 125 patients with Type 2 diabetes who had at least one Patient Empowerment Programme session attendance. Patients who did not participate in the Patient Empowerment Programme were matched one-to-one with patients who did, using the propensity score method. Hospitalization events and emergency department visits were the events of interest. Cox proportional hazard and negative binomial regressions were performed to estimate the hazard ratios for the initial event, and incidence rate ratios for the number of events. During a median 30.5 months of follow-up, participants in the Patient Empowerment Programme had a lower incidence of an initial hospitalization event (22.1 vs 25.2%; hazard ratio 0.879; P Patient Empowerment Programme. Participation in the Patient Empowerment Programme was associated with a significantly lower number of emergency department visits (incidence rate ratio 0.903; P patients annually in those who did not participate in the Patient Empowerment Programme vs. 36.2 per 100 patients annually in those who did. There were significantly fewer hospitalization episodes (incidence rate ratio 0.854; P patients annually in those who did not participate in the Patient Empowerment Programme vs. 16.9 hospitalizations per 100 patients annually in those who did. Among patients with Type 2 diabetes, the Patient Empowerment Programme was shown to be effective in delaying the initial hospitalization event and in reducing their frequency. © 2015 Diabetes UK.

Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience

International Nuclear Information System (INIS)

Bugnet, H.

1995-01-01

The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs

Design lessons from using programmable controllers in the MFTF-B personnel safety and interlocks system

International Nuclear Information System (INIS)

Branum, J.D.

1983-01-01

Applying programmable controllers in critical applications such as personnel safety and interlocks systems requires special considerations in the design of both hardware and software. All modern programmable controller systems feature extensive internal diagnostic capabilities to protect against problems such as program memory errors; however most, if not all present designs lack an intrinsic capability for detecting and countering failures on the field-side of their I/O modules. Many of the most common styles of I/O modules can also introduce potentially dangerous sneak circuits, even without component failure. This paper presents the most significant lessons learned to date in the design of the MFTF-B Personnel Safety and Interlocks System, which utilizes two non-redundant programmable controllers with over 800 I/O points each. Specific problems recognized during the design process as well as those discovered during initial testing and operation are discussed along with their specific solutions in hardware and software

Circuit arrangement of an electronic component for the design of fail-safe protective circuits

International Nuclear Information System (INIS)

Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

1974-01-01

The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

Comparison of modified driver circuit and capacitor-transfer circuit in longitudinally excited N2 laser.

Science.gov (United States)

Uno, Kazuyuki; Akitsu, Tetsuya; Nakamura, Kenshi; Jitsuno, Takahisa

2013-04-01

We developed a modified driver circuit composed of a capacitance and a spark gap, called a direct-drive circuit, for a longitudinally excited gas laser. The direct-drive circuit uses a large discharge impedance caused by a long discharge length of the longitudinal excitation scheme and eliminates the buffer capacitance used in the traditional capacitor-transfer circuit. We compared the direct-drive circuit and the capacitor-transfer circuit in a longitudinally excited N2 laser (wavelength: 337 nm). Producing high output energy with the capacitor-transfer circuit requires a large storage capacitance and a discharge tube with optimum dimensions (an inner diameter of 4 mm and a length of 10 cm in this work); in contrast, the direct-drive circuit requires a high breakdown voltage, achieved with a small storage capacitance and a large discharge tube. Additionally, for the same input energy of 792 mJ, the maximum output energy of the capacitor-transfer circuit was 174.2 μJ, and that of the direct-drive circuit was 344.7 μJ.

Measurement of time delays in gated radiotherapy for realistic respiratory motions

International Nuclear Information System (INIS)

Chugh, Brige P.; Quirk, Sarah; Conroy, Leigh; Smith, Wendy L.

2014-01-01

Purpose: Gated radiotherapy is used to reduce internal motion margins, escalate target dose, and limit normal tissue dose; however, its temporal accuracy is limited. Beam-on and beam-off time delays can lead to treatment inefficiencies and/or geographic misses; therefore, AAPM Task Group 142 recommends verifying the temporal accuracy of gating systems. Many groups use sinusoidal phantom motion for this, under the tacit assumption that use of sinusoidal motion for determining time delays produces negligible error. The authors test this assumption by measuring gating time delays for several realistic motion shapes with increasing degrees of irregularity. Methods: Time delays were measured on a linear accelerator with a real-time position management system (Varian TrueBeam with RPM system version 1.7.5) for seven motion shapes: regular sinusoidal; regular realistic-shape; large (40%) and small (10%) variations in amplitude; large (40%) variations in period; small (10%) variations in both amplitude and period; and baseline drift (30%). Film streaks of radiation exposure were generated for each motion shape using a programmable motion phantom. Beam-on and beam-off time delays were determined from the difference between the expected and observed streak length. Results: For the system investigated, all sine, regular realistic-shape, and slightly irregular amplitude variation motions had beam-off and beam-on time delays within the AAPM recommended limit of less than 100 ms. In phase-based gating, even small variations in period resulted in some time delays greater than 100 ms. Considerable time delays over 1 s were observed with highly irregular motion. Conclusions: Sinusoidal motion shapes can be considered a reasonable approximation to the more complex and slightly irregular shapes of realistic motion. When using phase-based gating with predictive filters even small variations in period can result in time delays over 100 ms. Clinical use of these systems for patients

Measurement of time delays in gated radiotherapy for realistic respiratory motions

Energy Technology Data Exchange (ETDEWEB)

Chugh, Brige P.; Quirk, Sarah; Conroy, Leigh; Smith, Wendy L., E-mail: Wendy.Smith@albertahealthservices.ca [Department of Medical Physics, Tom Baker Cancer Centre, Calgary, Alberta T2N 4N2 (Canada)

2014-09-15

Purpose: Gated radiotherapy is used to reduce internal motion margins, escalate target dose, and limit normal tissue dose; however, its temporal accuracy is limited. Beam-on and beam-off time delays can lead to treatment inefficiencies and/or geographic misses; therefore, AAPM Task Group 142 recommends verifying the temporal accuracy of gating systems. Many groups use sinusoidal phantom motion for this, under the tacit assumption that use of sinusoidal motion for determining time delays produces negligible error. The authors test this assumption by measuring gating time delays for several realistic motion shapes with increasing degrees of irregularity. Methods: Time delays were measured on a linear accelerator with a real-time position management system (Varian TrueBeam with RPM system version 1.7.5) for seven motion shapes: regular sinusoidal; regular realistic-shape; large (40%) and small (10%) variations in amplitude; large (40%) variations in period; small (10%) variations in both amplitude and period; and baseline drift (30%). Film streaks of radiation exposure were generated for each motion shape using a programmable motion phantom. Beam-on and beam-off time delays were determined from the difference between the expected and observed streak length. Results: For the system investigated, all sine, regular realistic-shape, and slightly irregular amplitude variation motions had beam-off and beam-on time delays within the AAPM recommended limit of less than 100 ms. In phase-based gating, even small variations in period resulted in some time delays greater than 100 ms. Considerable time delays over 1 s were observed with highly irregular motion. Conclusions: Sinusoidal motion shapes can be considered a reasonable approximation to the more complex and slightly irregular shapes of realistic motion. When using phase-based gating with predictive filters even small variations in period can result in time delays over 100 ms. Clinical use of these systems for patients

Three-dimensional multi-terminal superconductive integrated circuit inductance extraction

International Nuclear Information System (INIS)

Fourie, Coenrad J; Wetzstein, Olaf; Kunert, Jürgen; Ortlepp, Thomas

2011-01-01

Accurate inductance calculations are critical for the design of both digital and analogue superconductive integrated circuits, and three-dimensional calculations are gaining importance with the advent of inductive biasing, inductive coupling and sky plane shielding for RSFQ cells. InductEx, an extraction programme based on the three-dimensional calculation software FastHenry, was proposed earlier. InductEx uses segmentation techniques designed to accurately model the geometries of superconductive integrated circuit structures. Inductance extraction for complex multi-terminal three-dimensional structures from current distributions calculated by FastHenry is discussed. Results for both a reflection plane modelling an infinite ground plane and a finite segmented ground plane that allows inductive elements to extend over holes in the ground plane are shown. Several SQUIDs were designed for and fabricated with IPHT's 1 kA cm −2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures that span different layers, include vias, inductively coupled control lines and ground plane holes. We measured the loop inductance of these SQUIDs and show how the results are used to calibrate the layer parameters in InductEx and verify the extraction accuracy. We also show that, with proper modelling, FastHenry can be fast enough to be used for the extraction of typical RSFQ cell inductances.

Delays in the diagnosis and treatment of tuberculosis patients in Vietnam: a cross-sectional study

Directory of Open Access Journals (Sweden)

Khanh Vu T

2007-06-01

Full Text Available Abstract Background Treatment delay is an important indicator of access to tuberculosis diagnosis and treatment. Analyses of patient delay (i.e. time interval between onset of symptoms and first consultation of a health care provider and health care delay (i.e. time interval between first consultation and start of treatment can inform policies to improve access. This study assesses the patient, health care provider and total delay in diagnosis and treatment of new smear-positive pulmonary tuberculosis patients, and the risk factors for long delay, in Vietnam. Methods A cross-sectional survey of new patients treated by the National Tuberculosis Control Programme was conducted in 70 randomly selected districts in Vietnam. All consecutively registered patients in one quarter of 2002 were interviewed using a pre-coded structured questionnaire. Results Median (range delay was 4 weeks (1–48 for total, 3 (1–48 weeks for patient and 1 (0–25 week for health care delay. Patients with long total delay (≥ 12 weeks, 15% accounted for 49% of the cumulative number of delay-weeks. Independent risk factors (p 5 km distance from a health facility or in the northern area. For long health care delay (≥ 6 weeks this was urban setting, residence in the central area and initial visit to a communal health post, TB hospital or the private sector. Conclusion Analyses of patient and treatment delays can indicate target groups and areas for health education and strengthening of the referral system, in particular between the private sector and the NTP.

Aging evaluation of electrical circuits using the ECCAD [Electrical Circuit Characterization and Diagnostic] system

International Nuclear Information System (INIS)

Edson, J.L.

1988-01-01

As a part of the Nuclear Regulatory Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport Atomic Power Station Decommissioning Project. The objective of this work was to evaluate the effectiveness of the Electrical Circuit Characterization and Diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Flasck, J.M.; Levi, M.E.

1996-01-01

Phase-locked loops have been employed in the past to obtain sub-nanosecond time resolution in high energy physics and nuclear science applications. An alternative solution based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Mueller C-element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multichannel, time-to-digital converter (TDC) targeted for one specific frequency. The two circuits, DLL and TDC, are implemented in CMOS 1.2 microm and 0.8 microm technologies, respectively. Test results show a timing jitter of less than 30 ps for the DLL circuit and less than 190 ps integral and differential nonlinearity for the TDC circuit

Means and method of sampling flow related variables from a waterway in an accurate manner using a programmable calculator

Science.gov (United States)

Rand E. Eads; Mark R. Boolootian; Steven C. [Inventors] Hankin

1987-01-01

Abstract - A programmable calculator is connected to a pumping sampler by an interface circuit board. The calculator has a sediment sampling program stored therein and includes a timer to periodically wake up the calculator. Sediment collection is controlled by a Selection At List Time (SALT) scheme in which the probability of taking a sample is proportional to its...

Multi-Layer E-Textile Circuits

Science.gov (United States)

Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

2012-01-01

Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

Dissolvable fluidic time delays for programming multi-step assays in instrument-free paper diagnostics.

Science.gov (United States)

Lutz, Barry; Liang, Tinny; Fu, Elain; Ramachandran, Sujatha; Kauffman, Peter; Yager, Paul

2013-07-21

Lateral flow tests (LFTs) are an ingenious format for rapid and easy-to-use diagnostics, but they are fundamentally limited to assay chemistries that can be reduced to a single chemical step. In contrast, most laboratory diagnostic assays rely on multiple timed steps carried out by a human or a machine. Here, we use dissolvable sugar applied to paper to create programmable flow delays and present a paper network topology that uses these time delays to program automated multi-step fluidic protocols. Solutions of sucrose at different concentrations (10-70% of saturation) were added to paper strips and dried to create fluidic time delays spanning minutes to nearly an hour. A simple folding card format employing sugar delays was shown to automate a four-step fluidic process initiated by a single user activation step (folding the card); this device was used to perform a signal-amplified sandwich immunoassay for a diagnostic biomarker for malaria. The cards are capable of automating multi-step assay protocols normally used in laboratories, but in a rapid, low-cost, and easy-to-use format.

Analog circuit design

CERN Document Server

Dobkin, Bob

2012-01-01

Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

ESD analog circuits and design

CERN Document Server

Voldman, Steven H

2014-01-01

A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

Energy Technology Data Exchange (ETDEWEB)

Aunet, Snorre

2002-06-01

This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

Study on Oscillations during Short Circuit of MW-Scale IGBT Power Modules by Means of a 6-kA/1.1-kV Nondestructive Testing System

DEFF Research Database (Denmark)

Wu, Rui; Diaz Reigosa, Paula; Iannuzzo, Francesco

2015-01-01

This paper uses a 6-kA/1.1-kV nondestructive testing system for the analysis of the short-circuit behavior of insulated-gate bipolar transistor (IGBT) power modules. A field-programmable gate array enables the definition of control signals to an accuracy of 10 ns. Multiple 1.7-kV/1-kA IGBT power...... modules displayed severe divergent oscillations, which were subsequently characterized. Experimental tests indicate that nonnegligible circuit stray inductance plays an important role in the divergent oscillations. In addition, the temperature dependence of the transconductance is proposed as an important...

analysis and implementation of reactor protection system circuits - case study Egypt's 2 nd research reactor-

International Nuclear Information System (INIS)

Elnokity, O.E.M.

2006-01-01

this work presents a way to design and implement the trip unit of a reactor protection system (RPS) using a field programmable gate arrays (FPGA). instead of the traditional embedded microprocessor based interface design method, a proposed tailor made FPGA based circuit is built to substitute the trip unit (TU), which is used in Egypt's 2 nd research reactor ETRR-2. the existing embedded system is built around the STD32 field computer bus which is used in industrial and process control applications. it is modular, rugged, reliable, and easy-to-use and is able to support a large mix of I/O cards and to easily change its configuration in the future. therefore, the same bus is still used in the proposed design. the state machine of this bus is designed based around its timing diagrams and implemented in VHDL to interface the designed TU circuit

'Speedy' superconducting circuits

International Nuclear Information System (INIS)

Holst, T.

1994-01-01

The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1968-01-01

Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

New nuclear programmes must not neglect waste management - 59077

International Nuclear Information System (INIS)

McCombie, Charles

2012-01-01

Many established nuclear power programmes have learned to their dismay that waste management and disposal are not tasks that can be postponed at will if public and political acceptance is a prerequisite for progress. In fact, some programmes that recognised this back in the 1970's and 1980's moved into leading positions in repository development. This happened, for example, in Sweden and Switzerland where already in the 1970's Laws were passed specifying that safe disposal must be demonstrated before new nuclear plants could operate. In recent years, it has become recognised that, in order to ensure that the radioactive wastes in any country are managed safely, it is necessary to have an established legislative and regulatory framework and also to create the necessary organizations for implementation and for oversight of waste management operations and facility development. Guidance on these issues is given in the Joint Convention and a number of other IAEA documents. The IAEA, and also the EC, have in addition published key overarching advisory documents for new nuclear programmes. These are useful for strategic planning but, when it comes to actual implementation projects, the advice tends to imply that all nuclear programmes, however large or small, should be pressing ahead urgently towards early operation of geological repositories. In practice, however, in small programmes there are neither economic nor technical drivers for early implementation of deep geological repositories. Constructing simpler facilities for the disposal of the larger volume of low-level wastes has higher priority. Nevertheless, in all countries political decisions have to be taken and policies set in place to ensure that geological disposal will implemented without unjustified delay. This paper distils out a set of key messages for new programmes. Amongst the most critical are the following. Even if disposal is far off, planning and organization should begin at the initiation of the

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

Science.gov (United States)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Unstable oscillators based hyperchaotic circuit

DEFF Research Database (Denmark)

Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.

1999-01-01

A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Results from the UK 3rd generation programme: Albion

Science.gov (United States)

McEwen, R. K.; Axcell, C.; Knowles, P.; Hoade, K. P.; Wilson, M.; Dennis, P. N. J.; Backhouse, P.; Gordon, N. T.

2008-10-01

Following the development of 1st Generation systems in the 1970s, thermal imaging has been in service with the UK armed forces for over 25 years and has proven itself to be a battle winning technology. More recently the wider accessibility to similar technologies within opposing forces has reduced the military advantage provided by these 1st Generation systems and a clear requirement has been identified by the UK MOD for thermal imaging sensors providing increased detection, recognition and identification (DRI) ranges together with a simplified logistical deployment burden and reduced through-life costs. In late 2005, the UK MOD initiated a programme known as "Albion" to develop high performance 3rd Generation single waveband infrared detectors to meet this requirement. At the same time, under a separate programme supporting higher risk technology, a dual waveband infrared detector was also developed. The development phase of the Albion programme has now been completed and prototype detectors are now available and have been integrated into demonstration thermal imaging cameras. The Albion programme has now progressed into the second phase, incorporating both single and dual waveband devices, focussing on low rate initial production (LRIP) and qualification of the devices for military applications. All of the detectors have been fabricated using cadmium mercury telluride material (CMT), grown by metal organic vapour phase epitaxy (MOVPE) on low cost, gallium arsenide (GaAs) substrates and bump bonded to the silicon read out circuit (ROIC). This paper discusses the design features of the 3rd Generation detectors developed in the UK together with the results obtained from the prototype devices both in the laboratory and when integrated into field deployable thermal imaging cameras.

Replacement of the Pumps for Fuel Channel Cooling Circuit of the Maria Research Reactor

Energy Technology Data Exchange (ETDEWEB)

Krzysztoszek, G.; Mieleszczenko, W.; Moldysz, A. [National Centre for Nuclear Research, Otwock–Świerk (Poland)

2014-08-15

The high flux Maria research reactor is operated by the National Centre for Nuclear Research in Świerk. It is a pool type reactor with pressurized fuel channels located in the beryllium matrix. According to the Global Threat Reduction Initiative programme our goal is to convert the Maria reactor from HEU to LEU fuel. Hydraulic losses in the new LEU fuel produced by CERCA are about 30% higher than the existing HEU fuel of type MR-6. For the MR-6 fuel were installed four two speed pumps. These pumps performed the function of the main circulations pumps during reactor operation with residual pumping power provided by emergency pumps. In the new system four main pumps will be used for circulating coolant while the reactor is operation with three auxiliary pumps for decay heat removal after reactor shutdown, meaning that the conversion of Maria research reactor will be possible after increasing flow in the primary cooling circuit of the fuel channels. The technical design of replacement of the pumps in the primary fuel channel cooling circuit was finished in April 2011 and accepted by the Safety Committee. After delivery of the new pumps we are planning to upgrade the primary fuel channel cooling circuit during October–November 2012. (author)

Circuits and filters handbook

CERN Document Server

Chen, Wai-Kai

2003-01-01

A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

MOS integrated circuit design

CERN Document Server

Wolfendale, E

2013-01-01

MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

Security electronics circuits manual

CERN Document Server

MARSTON, R M

1998-01-01

Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

Changes to the shuttle circuits

CERN Multimedia

GS Department

2011-01-01

To fit with passengers expectation, there will be some changes to the shuttle circuits as from Monday 10 October. See details on http://cern.ch/ShuttleService (on line on 7 October). Circuit No. 5 is cancelled as circuit No. 1 also stops at Bldg. 33. In order to guarantee shorter travel times, circuit No. 1 will circulate on Meyrin site only and circuit No. 2, with departures from Bldg. 33 and 500, on Prévessin site only. Site Services Section

Troubleshooting analog circuits

CERN Document Server

Pease, Robert A

1991-01-01

Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other

Optoelectronics circuits manual

CERN Document Server

Marston, R M

2013-01-01

Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.

A review of literature on delays in seeking care for tuberculosis in different Indian states

Directory of Open Access Journals (Sweden)

Janmejaya Samal

2017-01-01

Full Text Available The passive case-finding approach of Revised National Tuberculosis (TB Control Programme in India strongly affects the health-seeking behavior of TB patients, the timing of help seeking as well as the subsequent delays associated with the same. Studies carried out in different parts of India reveal a host of several factors for delay in seeking help and the reasons for not seeking help at all. Important reasons for delayed health-seeking behavior include financial constraint, symptoms are not severe (as perceived by the patients, work pressure, lack of awareness, first consulted nonpublic sector, inaccessibility to health facility, home remedy, social stigma, self-medication, transport problem, and dissatisfaction with health facility. Similarly, the median patient delay ranged from 7 to 56 days as reported by various studies. Health-seeking behavior and related delays are of utmost importance in TB care from two important perspectives; first, TB requires timely treatment, and second, it requires protracted treatment. Required level of knowledge and a positive health behavior helps the patients in taking timely help from an appropriate health facility. Moreover, timely help-seeking prevents further spread of the disease and helps in establishing a TB-free society.

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

Integrated circuit and method of arbitration in a network on an integrated circuit.

NARCIS (Netherlands)

2011-01-01

The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input

Electronic Circuit Analysis Language (ECAL)

Science.gov (United States)

Chenghang, C.

1983-03-01

The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

OpenAIRE

Artem Ganiyev; Jan Vitasek

2010-01-01

This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

Regulatory heterochronies and loose temporal scaling between sea star and sea urchin regulatory circuits.

Science.gov (United States)

Gildor, Tsvia; Hinman, Veronica; Ben-Tabou-De-Leon, Smadar

2017-01-01

It has long been argued that heterochrony, a change in relative timing of a developmental process, is a major source of evolutionary innovation. Heterochronic changes of regulatory gene activation could be the underlying molecular mechanism driving heterochronic changes through evolution. Here, we compare the temporal expression profiles of key regulatory circuits between sea urchin and sea star, representative of two classes of Echinoderms that shared a common ancestor about 500 million years ago. The morphologies of the sea urchin and sea star embryos are largely comparable, yet, differences in certain mesodermal cell types and ectodermal patterning result in distinct larval body plans. We generated high resolution temporal profiles of 17 mesodermally-, endodermally- and ectodermally-expressed regulatory genes in the sea star, Patiria miniata, and compared these to their orthologs in the Mediterranean sea urchin, Paracentrotus lividus. We found that the maternal to zygotic transition is delayed in the sea star compared to the sea urchin, in agreement with the longer cleavage stage in the sea star. Interestingly, the order of gene activation shows the highest variation in the relatively diverged mesodermal circuit, while the correlations of expression dynamics are the highest in the strongly conserved endodermal circuit. We detected loose scaling of the developmental rates of these species and observed interspecies heterochronies within all studied regulatory circuits. Thus, after 500 million years of parallel evolution, mild heterochronies between the species are frequently observed and the tight temporal scaling observed for closely related species no longer holds.

Magnonic logic circuits

International Nuclear Information System (INIS)

Khitun, Alexander; Bao Mingqiang; Wang, Kang L

2010-01-01

We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

Monolithic microwave integrated circuit water vapor radiometer

Science.gov (United States)

Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

1991-01-01

A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

Electrical Circuits and Water Analogies

Science.gov (United States)

Smith, Frederick A.; Wilson, Jerry D.

1974-01-01

Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

Optimal planning of series resistor to control time constant of test circuit for high-voltage AC circuit-breakers

OpenAIRE

Yoon-Ho Kim; Jung-Hyeon Ryu; Jin-Hwan Kim; Kern-Joong Kim

2016-01-01

The equivalent test circuit that can deliver both short-circuit current and recovery voltage is used to verify the performance of high-voltage circuit breakers. Most of the parameters in this circuit can be obtained by using a simple calculation or a simulation program. The ratings of the circuit breaker include rated short-circuit breaking current, rated short-circuit making current, rated operating sequence of the circuit breaker and rated short-time current. Among these ratings, the short-...

Interface Circuit For Printer Port

Science.gov (United States)

Tucker, Jerry H.; Yadlowsky, Ann B.

1991-01-01

Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

A Two-Layer Gene Circuit for Decoupling Cell Growth from Metabolite Production.

Science.gov (United States)

Lo, Tat-Ming; Chng, Si Hui; Teo, Wei Suong; Cho, Han-Saem; Chang, Matthew Wook

2016-08-01

We present a synthetic gene circuit for decoupling cell growth from metabolite production through autonomous regulation of enzymatic pathways by integrated modules that sense nutrient and substrate. The two-layer circuit allows Escherichia coli to selectively utilize target substrates in a mixed pool; channel metabolic resources to growth by delaying enzymatic conversion until nutrient depletion; and activate, terminate, and re-activate conversion upon substrate availability. We developed two versions of controller, both of which have glucose nutrient sensors but differ in their substrate-sensing modules. One controller is specific for hydroxycinnamic acid and the other for oleic acid. Our hydroxycinnamic acid controller lowered metabolic stress 2-fold and increased the growth rate 2-fold and productivity 5-fold, whereas our oleic acid controller lowered metabolic stress 2-fold and increased the growth rate 1.3-fold and productivity 2.4-fold. These results demonstrate the potential for engineering strategies that decouple growth and production to make bio-based production more economical and sustainable. Copyright © 2016 The Authors. Published by Elsevier Inc. All rights reserved.

Maximum Acceleration Recording Circuit

Science.gov (United States)

Bozeman, Richard J., Jr.

1995-01-01

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

Four-junction superconducting circuit

Science.gov (United States)

Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

2016-01-01

We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

Evaluating the effectiveness of a metacognitive programme for disadvantaged learners in the Foundation Phase

Directory of Open Access Journals (Sweden)

Louis Benjamin

2016-02-01

Full Text Available Learners in South Africa lag behind in literacy and numeracy skills relative to their peers in other countries. This is ascribed to a lack of quality education in the preschool and Foundation Phases of schooling, and conditions related to poverty. The Basic Concepts Mediated Learning Programme (BCMLP aims to promote the conceptual development of young children through training teachers to be mediators in a metacognitive educational programme. The BCMLP was implemented in the Foundation Phase (Grade R to Grade 3 in two schools in impoverished areas of the Northern Cape over three years (20082010. Baseline testing found that children at both schools experienced significant delays in their conceptual and scholastic development. After being trained as mediators, teachers implemented this approach with groups, eventually integrating it into the curriculum. There was variable continuity of implementation at the two schools, with one school only implementing the programme for the first year. The conceptual development and scholastic functioning of learners were monitored pre-intervention to post-intervention. Results found that implementation of the programme was consistent with considerable improvements in conceptual and scholastic functioning. Further, improvements were more pronounced, where the programme was implemented continually for three years. The researcher concluded that the programme made a positive impact on participating learners' knowledge and understanding of basic conceptual systems and scholastic functioning.

Control circuit for transformer relay

International Nuclear Information System (INIS)

Wyatt, G.A.

1984-01-01

A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

Adder design using a 5-input majority gate in a novel “multilayer gate design paradigm” for quantum dot cellular automata circuits

International Nuclear Information System (INIS)

Kumar, Rohit; Ghosh, Bahniman; Gupta, Shoubhik

2015-01-01

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input–output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact. (paper)

Integrated coherent matter wave circuits

International Nuclear Information System (INIS)

Ryu, C.; Boshier, M. G.

2015-01-01

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

Model Comparison Exercise Circuit Training Game and Circuit Ladder Drills to Improve Agility and Speed

Directory of Open Access Journals (Sweden)

Susilaturochman Hendrawan Koestanto

2017-11-01

Full Text Available The purpose of this study was to compare: (1 the effect of circuit training game and circuit ladder drill for the agility; (2 the effect of circuit training game and circuit ladder drill on speed; (3 the difference effect of circuit training game and circuit ladder drill for the speed (4 the difference effect of circuit training game and circuit ladder drill on agility. The type of this research was quantitative with quasi-experimental methods. The design of this research was Factorial Design, with analysing data using ANOVA. The process of data collection was done by using 30 meters sprint speed test and shuttle run test during the pretest and posttest. Furthermore, the data was analyzed by using SPSS 22.0 series. Result: The circuit training game exercise program and circuit ladder drill were significant to increase agility and speed (sig 0.000 < α = 0.005 Group I, II, III had significant differences (sig 0.000 < α = 0.005. The mean of increase in speed of group I = 0.20 seconds, group II = 0.31 seconds, and group III = 0.11 seconds. The average increase agility to group I = 0.34 seconds group II = 0.60 seconds, group III = 0.13 seconds. Based on the analysis above, it could be concluded that there was an increase in the speed and agility of each group after being given a training.

Comminution circuits for compact itabirites

Directory of Open Access Journals (Sweden)

Pedro Ferreira Pinto

Full Text Available Abstract In the beneficiation of compact Itabirites, crushing and grinding account for major operational and capital costs. As such, the study and development of comminution circuits have a fundamental importance for feasibility and optimization of compact Itabirite beneficiation. This work makes a comparison between comminution circuits for compact Itabirites from the Iron Quadrangle. The circuits developed are: a crushing and ball mill circuit (CB, a SAG mill and ball mill circuit (SAB and a single stage SAG mill circuit (SSSAG. For the SAB circuit, the use of pebble crushing is analyzed (SABC. An industrial circuit for 25 million tons of run of mine was developed for each route from tests on a pilot scale (grinding and industrial scale. The energy consumption obtained for grinding in the pilot tests was compared with that reported by Donda and Bond. The SSSAG route had the lowest energy consumption, 11.8kWh/t and the SAB route had the highest energy consumption, 15.8kWh/t. The CB and SABC routes had a similar energy consumption of 14.4 kWh/t and 14.5 kWh/t respectively.

30 CFR 77.506-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Science.gov (United States)

2010-07-01

... short circuit protection; minimum requirements. 77.506-1 Section 77.506-1 Mineral Resources MINE SAFETY...-1 Electric equipment and circuits; overload and short circuit protection; minimum requirements. Devices providing either short circuit protection or protection against overload shall conform to the...

Bistability and hysteresis in the emergence of pulses in microstrip Gunn-diode circuits

Energy Technology Data Exchange (ETDEWEB)

Yurchenko, V. B., E-mail: v.yurchenko@nuim.ie [O. Ya. Usikov Institute for Radiophysics and Electronics, National Academy of Sciences of Ukraine, 12 Proskura St., Kharkiv 61085 (Ukraine); Electrical and Electronic Engineering Department, Gazi University, Celal Bayar Bulvari, Ankara 06570 (Turkey); Yurchenko, L. V. [O. Ya. Usikov Institute for Radiophysics and Electronics, National Academy of Sciences of Ukraine, 12 Proskura St., Kharkiv 61085 (Ukraine)

2014-12-15

We develop time-domain simulations of microwave and THz radiation sources built as arrays of active devices when the radiation wavelength is small as compared to spacing between electronic components. We pursue an approach when the system is represented by equations with time-delay feedback that could generate chaos and other forms of complicated dynamics. The approach simplifies simulations of ultra-wideband effects and exceeds capabilities of frequency-domain methods. As a model case, we simulated a microstrip circuit with Gunn diode and a remote resonator emitting the radiation towards infinity. We observed the emergence of either the continuous waves or the trains of high-frequency pulses depending on the bias conditions. We found bistability and hysteresis in the onset of different oscillation modes that depends on the way of driving the bias voltage into the domain of instability of the given system. The results would allow one to improve the design of THz radiation sources with time-delay coupling between components.

Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

KAUST Repository

Hanna, Amir

2015-12-04

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.