WorldWideScience

Sample records for polished silicon wafer

  1. Chemical polishing of epitoxial silicon wafer

    International Nuclear Information System (INIS)

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  2. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Science.gov (United States)

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  3. Damage-free polishing of monocrystalline silicon wafers without chemical additives

    International Nuclear Information System (INIS)

    Biddut, A.Q.; Zhang, L.C.; Ali, Y.M.; Liu, Z.

    2008-01-01

    This investigation explores the possibility and identifies the mechanism of damage-free polishing of monocrystalline silicon without chemical additives. Using high resolution electron microscopy and contact mechanics, the study concludes that a damage-free polishing process without chemicals is feasible. All forms of damages, such as amorphous Si, dislocations and plane shifting, can be eliminated by avoiding the initiation of the β-tin phase of silicon during polishing. When using 50 nm abrasives, the nominal pressure to achieve damage-free polishing is 20 kPa

  4. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  5. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  6. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  7. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  8. Industrial Silicon Wafer Solar Cells

    OpenAIRE

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  9. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  10. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  11. Lamb wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  12. Making Porous Luminescent Regions In Silicon Wafers

    Science.gov (United States)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  13. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  14. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    International Nuclear Information System (INIS)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  15. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  16. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  17. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  18. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    Science.gov (United States)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  19. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    Science.gov (United States)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  20. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  1. High frequency guided wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  2. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  3. Polishing of silicon based advanced ceramics

    Science.gov (United States)

    Klocke, Fritz; Dambon, Olaf; Zunke, Richard; Waechter, D.

    2009-05-01

    Silicon based advanced ceramics show advantages in comparison to other materials due to their extreme hardness, wear and creep resistance, low density and low coefficient of thermal expansion. As a matter of course, machining requires high efforts. In order to reach demanded low roughness for optical or tribological applications a defect free surface is indispensable. In this paper, polishing of silicon nitride and silicon carbide is investigated. The objective is to elaborate scientific understanding of the process interactions. Based on this knowledge, the optimization of removal rate, surface quality and form accuracy can be realized. For this purpose, fundamental investigations of polishing silicon based ceramics are undertaken and evaluated. Former scientific publications discuss removal mechanisms and wear behavior, but the scientific insight is mainly based on investigations in grinding and lapping. The removal mechanisms in polishing are not fully understood due to complexity of interactions. The role of, e.g., process parameters, slurry and abrasives, and their influence on the output parameters is still uncertain. Extensive technological investigations demonstrate the influence of the polishing system and the machining parameters on the stability and the reproducibility. It is shown that the interactions between the advanced ceramics and the polishing systems is of great relevance. Depending on the kind of slurry and polishing agent the material removal mechanisms differ. The observed effects can be explained by dominating mechanical or chemo-mechanical removal mechanisms. Therefore, hypotheses to state adequate explanations are presented and validated by advanced metrology devices, such as SEM, AFM and TEM.

  4. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  5. Guided ultrasonic wave beam skew in silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  6. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Science.gov (United States)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  7. Preparation and characterisation of immobilised humic acid on silicon wafer

    International Nuclear Information System (INIS)

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  8. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  9. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    International Nuclear Information System (INIS)

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  10. Cohesive zone model for direct silicon wafer bonding

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  11. Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

    International Nuclear Information System (INIS)

    Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

    2005-01-01

    This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

  12. Surface etching technologies for monocrystalline silicon wafer solar cells

    Science.gov (United States)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  13. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  14. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    NARCIS (Netherlands)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  15. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  16. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  17. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  18. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  19. Contacting graphene in a 200 mm wafer silicon technology environment

    Science.gov (United States)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  20. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Science.gov (United States)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  1. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  2. Tests of a silicon wafer based neutron collimator

    International Nuclear Information System (INIS)

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  3. Tests of a silicon wafer based neutron collimator

    CERN Document Server

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  4. Coherent spin transport through a 350 micron thick silicon wafer.

    Science.gov (United States)

    Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

    2007-10-26

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  5. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  6. XPS, UV–vis spectroscopy and AFM studies on removal mechanisms of Si-face SiC wafer chemical mechanical polishing (CMP)

    International Nuclear Information System (INIS)

    Zhou, Yan; Pan, Guoshun; Shi, Xiaolei; Xu, Li; Zou, Chunli; Gong, Hua; Luo, Guihai

    2014-01-01

    Highlights: • CMP removal mechanism of Si-face SiC wafer is investigated through XPS analysis. • UV–vis spectroscopy is used to study CMP removal mechanisms. • CMP removal model of Si-face SiC wafer is proposed. • The variations of atomic step morphology on ultra-smooth surface via AFM is studied. - Abstract: Chemical mechanical polishing (CMP) removal mechanisms of on-axis Si-face SiC wafer have been investigated through X-ray photoelectron spectroscopy (XPS), UV–visible (UV–vis) spectroscopy and atomic force microscopy (AFM). XPS results indicate that silicon oxide is formed on Si-face surface polished by the slurry including oxidant H 2 O 2 , but not that after immersing in H 2 O 2 solution. UV–vis spectroscopy curves prove that • OH hydroxyl radical could be generated only under CMP polishing by the slurry including H 2 O 2 and abrasive, so as to promote oxidation of Si-face to realize the effective removal; meanwhile, alkali KOH during CMP could induce the production of more radicals to improve the removal. On the other side, ultra-smooth polished surface with atomic step structure morphology and extremely low Ra of about 0.06 nm (through AFM) is obtained using the developed slurry with silica nanoparticle abrasive. Through investigating the variations of the atomic step morphology on the surface polished by different slurries, it's reveals that CMP removal mechanism involves a simultaneous process of surface chemical reaction and nanoparticle atomic scale abrasion

  7. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  8. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Directory of Open Access Journals (Sweden)

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  9. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  10. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    Science.gov (United States)

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

  11. Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

    Science.gov (United States)

    Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

    2013-01-02

    Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

  12. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    International Nuclear Information System (INIS)

    Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

  13. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  14. Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

    Science.gov (United States)

    Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

    2017-10-01

    Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

  15. Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

    International Nuclear Information System (INIS)

    Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

    2003-01-01

    Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

  16. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  17. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    International Nuclear Information System (INIS)

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  18. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  19. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    NARCIS (Netherlands)

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  20. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    Science.gov (United States)

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  1. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  2. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    International Nuclear Information System (INIS)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  3. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

    2014-01-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  4. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  5. Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

    Directory of Open Access Journals (Sweden)

    Shisheng Cai

    2017-03-01

    Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

  6. Characterisation and stabilisation of the surface region of a highly polished silicon crystal sphere

    International Nuclear Information System (INIS)

    Kenny, M.J.; Wielunski, L.S.

    1999-01-01

    Full text: Typically a single crystal silicon wafer has a native oxide layer a few nm thick which changes slowly with time. A number of parameters such as hydrocarbons, water vapour, storage environment can affect this layer. The thickness of the layer is also orientation dependent. In the case of a silicon sphere the situation becomes more complex, because all orientations are present and the process of polishing involves a higher pressure and also high local temperatures. A highly polished single crystal sphere 93.6 mm in diameter is being used to determine the Avogadro constant with an uncertainty of ≤ 1 x 10 -8 . This will then be used to obtain an atomic definition of the kilogram. The composition and structure of the surface oxide layer play an important role in this measurement. Firstly the density of the oxide layer is different from that of silicon. Secondly since the diameter is measured by optical interferometry, corrections must be applied for the phase change in the reflected light beam due to the surface layer. Thirdly the orientation dependence of the layer complicated the corrections to be applied. Fourthly if measurements are made over a period of time, any changes in the surface layer must be taken into account. Given the accuracy required in the determination, the surface layer is a determining factor in the final result. A number of techniques such as spectroscopic ellipsometry and ion beam analysis are being used to study the composition and structure of the surface of a silicon sphere. Cleaning techniques such as HF and low temperature ultraviolet (ozone) are being developed to produce a clean surface. The next step involves deposition of a stable and uniform surface oxide layer a few nm thick. Techniques being investigated for this include ultra violet ozone deposition at 450 deg C and plasma deposition. The paper describes work at the NML in achieving an appropriate stable surface on the silicon sphere

  7. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  8. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  9. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  10. DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

    Directory of Open Access Journals (Sweden)

    V. A. Solodukha

    2016-01-01

    Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

  11. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  12. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    Science.gov (United States)

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  13. Switchable static friction of piezoelectric composite-silicon wafer contacts

    NARCIS (Netherlands)

    Ende, D.A. van den; Fischer, H.R.; Groen, W.A.; Zwaag, S. van der

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  14. Switchable static friction of piezoelectric composite—silicon wafer contacts

    NARCIS (Netherlands)

    Van den Ende, D.A.; Fischer, H.R.; Groen, W.A.; Van der Zwaag, S.

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  15. Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

    Science.gov (United States)

    Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

    2018-06-01

    Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

  16. Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

    Science.gov (United States)

    Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

    2018-05-01

    Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

  17. Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

    Science.gov (United States)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-30

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  18. Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

    International Nuclear Information System (INIS)

    Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

    2006-01-01

    The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

  19. Sample pretreatment for the determination of metal impurities in silicon wafer

    International Nuclear Information System (INIS)

    Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

    1999-01-01

    The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

  20. Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

    2012-03-01

    Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

  1. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    International Nuclear Information System (INIS)

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  2. Fabrication of silicon condenser microphones using single wafer technology

    NARCIS (Netherlands)

    Scheeper, P.R.; van der Donk, A.G.H.; Olthuis, Wouter; Bergveld, Piet

    1992-01-01

    A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-¿m plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm2), covered with a thin

  3. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    Science.gov (United States)

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  4. Micro-spectroscopy on silicon wafers and solar cells

    Directory of Open Access Journals (Sweden)

    Gundel Paul

    2011-01-01

    Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

  5. Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

    Energy Technology Data Exchange (ETDEWEB)

    Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

    2012-09-15

    We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

  6. External self-gettering of nickel in float zone silicon wafers

    Science.gov (United States)

    Gay, N.; Martinuzzi, S.

    1997-05-01

    During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

  7. Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

    Science.gov (United States)

    Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

    2018-06-01

    Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

  8. An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

    International Nuclear Information System (INIS)

    Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

    2007-01-01

    The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

  9. Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

    Science.gov (United States)

    Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

    2018-01-01

    Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

  10. High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

    Energy Technology Data Exchange (ETDEWEB)

    Antoniadis, H.

    2011-03-01

    Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink high efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.

  11. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  12. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Directory of Open Access Journals (Sweden)

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  13. Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

    2014-02-07

    Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

  14. The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

    Directory of Open Access Journals (Sweden)

    Gnilenko A. B.

    2012-02-01

    Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

  15. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    International Nuclear Information System (INIS)

    Vega, M; Lasorsa, C; Lerner, B; Perez, M; Granell, P

    2016-01-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production. (paper)

  16. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    Science.gov (United States)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  17. Eutectic and solid-state wafer bonding of silicon with gold

    International Nuclear Information System (INIS)

    Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

    2012-01-01

    Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  18. Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

    International Nuclear Information System (INIS)

    Ngo, H-D; Hiess, Andre; Seidemann, Volker; Studzinski, Daniel; Lange, Martin; Leib, Juergen; Shariff, Dzafir; Ashraf, Huma; Steel, Mike; Atabo, Lilian; Reast, Jon

    2006-01-01

    This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained and plasma configurations are described elsewhere. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters

  19. Detection of trace contamination of copper on a silicon wafer with TXRF

    International Nuclear Information System (INIS)

    Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

    2000-01-01

    The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

  20. Formation of cross-cutting structures with different porosity on thick silicon wafers

    Directory of Open Access Journals (Sweden)

    Vera A. Yuzova

    2017-06-01

    The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

  1. EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    S. A. Chizhik

    2013-01-01

    Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

  2. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    Science.gov (United States)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  3. Process induced sub-surface damage in mechanically ground silicon wafers

    International Nuclear Information System (INIS)

    Yang Yu; De Munck, Koen; Teixeira, Ricardo Cotrin; Swinnen, Bart; De Wolf, Ingrid; Verlinden, Bert

    2008-01-01

    Micro-Raman spectroscopy, scanning electron microcopy, atomic force microscopy and preferential etching were used to characterize the sub-surface damage induced by the rough and fine grinding steps used to make ultra-thin silicon wafers. The roughly and ultra-finely ground silicon wafers were examined on both the machined (1 0 0) planes and the cross-sectional (1 1 0) planes. They reveal similar multi-layer damage structures, consisting of amorphous, plastically deformed and elastically stressed layers. However, the thickness of each layer in the roughly ground sample is much higher than its counterpart layers in the ultra-finely ground sample. The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30 MPa, respectively. In each case, the top amorphous layer is believed to be the result of sequential phase transformations (Si-I to Si-II to amorphous Si). These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in rough grinding, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks

  4. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.

    2018-01-02

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  5. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.; Kutbee, Arwa T.; Khan, Sherjeel M.; Sepulveda, Adrian C.; Wicaksono, Irmandy; Nour, Maha A.; Wehbe, Nimer; Almislem, Amani Saleh Saad; Ghoneim, Mohamed T.; Sevilla, Galo T.; Syed, Ahad; Shaikh, Sohail F.; Hussain, Muhammad Mustafa

    2018-01-01

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  6. Combined Ultrasonic Elliptical Vibration and Chemical Mechanical Polishing of Monocrystalline Silicon

    Directory of Open Access Journals (Sweden)

    Liu Defu

    2016-01-01

    Full Text Available An ultrasonic elliptical vibration assisted chemical mechanical polishing(UEV-CMP is employed to achieve high material removal rate and high surface quality in the finishing of hard and brittle materials such as monocrystalline silicon, which combines the functions of conventional CMP and ultrasonic machining. In theultrasonic elliptical vibration aided chemical mechanical polishingexperimental setup developed by ourselves, the workpiece attached at the end of horn can vibrate simultaneously in both horizontal and vertical directions. Polishing experiments are carried out involving monocrystalline silicon to confirm the performance of the proposed UEV-CMP. The experimental results reveal that the ultrasonic elliptical vibration can increase significantly the material removal rate and reduce dramatically the surface roughness of monocrystalline silicon. It is found that the removal rate of monocrystalline silicon polished by UEV-CMP is increased by approximately 110% relative to that of conventional CMP because a passive layer on the monocrystalline silicon surface, formed by the chemical action of the polishing slurry, will be removed not only by the mechanical action of CMP but also by ultrasonic vibration action. It indicates that the high efficiency and high quality CMP of monocrystalline silicon can be performed with the proposed UEV-CMP technique.

  7. Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

    Science.gov (United States)

    Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

    This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

  8. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Science.gov (United States)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  9. High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

    CERN Document Server

    Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

    2003-01-01

    Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

  10. Effect of Processing Parameters on Thickness of Columnar Structured Silicon Wafers Directly Grown from Silicon Melts

    Directory of Open Access Journals (Sweden)

    Jin-Seok Lee

    2012-01-01

    Full Text Available In order to obtain optimum growth conditions for desired thickness and more effective silicon feedstock usage, effects of processing parameters such as preheated substrate temperatures, time intervals, moving velocity of substrates, and Ar gas blowing rates on silicon ribbon thickness were investigated in the horizontal growth process. Most of the parameters strongly affected in the control of ribbon thickness with columnar grain structure depended on the solidification rate. The thickness of the silicon ribbon decreased with an increasing substrate temperature, decreasing time interval, and increasing moving velocity of the substrate. However, the blowing of Ar gas onto a liquid layer existing on the surface of solidified ribbon contributed to achieving smooth surface roughness but did not closely affect the change of ribbon thickness in the case of a blowing rate of ≥0.65 Nm3/h because the thickness of the solidified layer was already determined by the exit height of the reservoir.

  11. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    International Nuclear Information System (INIS)

    Mou, Chun-Yueh; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-01-01

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate

  12. Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

    Science.gov (United States)

    Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

    2014-07-21

    Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

  13. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mou, Chun-Yueh, E-mail: cymou165@gmail.com; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-06-30

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate.

  14. Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

    Science.gov (United States)

    Wang, Shing-Dar; Chen, Ting-Wei

    2018-06-01

    In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

  15. Analysis of borophosphosilicate glass layers on silicon wafers by X-ray emission from photon and electron excitation

    International Nuclear Information System (INIS)

    Elgersma, O.; Borstrok, J.J.M.

    1989-01-01

    Phosphorus and oxygen concentrations in the homogeneous layer of borosilicate glass (BPSG) deposited on Si-integrated circuits are determined by X-ray fluorescence from photon excitation. The X-ray emission from electron excitation in an open X-ray tube instrument yields a sufficiently precise determination of the boron content. The thickness of the layer can be derived from silicon Kα-fluorescence. A calibration model is proposed for photon as well as for electron excitation. The experimentally determined parameters in this model well agree with those derived from fundamental parameters for X-ray absorption and emission. The chemical surrounding of silicon affects strongly the peak profile of the silicon Kβ-emission. This enables to distinguish emission from the silicon atoms in the wafer and from the silicon atoms in the silicon oxide complexes of the BPSG-layer. (author)

  16. Effect of PECVD SiNx/SiOy Nx –Si interface property on surface passivation of silicon wafer

    International Nuclear Information System (INIS)

    Jia Xiao-Jie; Zhou Chun-Lan; Zhou Su; Wang Wen-Jing; Zhu Jun-Jie

    2016-01-01

    It is studied in this paper that the electrical characteristics of the interface between SiO y N x /SiN x stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiO y N x layer on interface parameters, such as interface state density Di t and fixed charge Q f , and the surface passivation quality of silicon are observed. Capacitance–voltage measurements reveal that inserting a thin SiO y N x layer between the SiN x and the silicon wafer can suppress Q f in the film and D it at the interface. The positive Q f and D it and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiO y N x film increasing. Prepared by deposition at a low temperature and a low ratio of N 2 O/SiH 4 flow rate, the SiO y N x /SiN x stacks result in a low effective surface recombination velocity (S eff ) of 6 cm/s on a p-type 1 Ω·cm–5 Ω·cm FZ silicon wafer. The positive relationship between S eff and D it suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. (paper)

  17. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    Science.gov (United States)

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  18. Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

    International Nuclear Information System (INIS)

    Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

    2012-01-01

    Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

  19. Reliability assessment of ultra-thin HfO{sub 2} films deposited on silicon wafer

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Wei-En [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Chang, Chia-Wei [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Chang, Yong-Qing [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Yao, Chih-Kai [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Liao, Jiunn-Der, E-mail: jdliao@mail.ncku.edu.tw [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China)

    2012-09-01

    Highlights: Black-Right-Pointing-Pointer Nano-mechanical properties on annealed ultra-thin HfO{sub 2} film are studied. Black-Right-Pointing-Pointer By AFM analysis, hardness of the crystallized HfO{sub 2} film significantly increases. Black-Right-Pointing-Pointer By nano-indention, the film hardness increases with less contact stiffness. Black-Right-Pointing-Pointer Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO{sub 2}) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO{sub 2} films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO{sub 2} films deposited on silicon wafers (HfO{sub 2}/SiO{sub 2}/Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO{sub 2} (nominal thickness Almost-Equal-To 10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO{sub 2} phases for the atomic layer deposited HfO{sub 2}. The HfSi{sub x}O{sub y} complex formed at the interface between HfO{sub 2} and SiO{sub 2}/Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO{sub 2} film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically

  20. Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

    2016-02-15

    Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

  1. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Science.gov (United States)

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  2. Quantitative analysis of phosphosilicate glass films on silicon wafers for calibration of x-ray fluorescence spectrometry standards

    International Nuclear Information System (INIS)

    Weissman, S.H.

    1983-01-01

    The phosphorus and silicon contents of phosphosilicate glass films deposited by chemical vapor deposition (CVD) on silicon wafers were determined. These films were prepared for use as x-ray fluorescence (XRF) spectrometry standards. The thin films were removed from the wafer by etching with dilute hydrofluoric acid, and the P and Si concentrations in solution were determined by inductively coupled plasma atomic emission spectroscopy (ICP). The calculated phosphorus concentration ranged from 2.2 to 12 wt %, with an uncertainty of 2.73 to 10.1 relative percent. Variation between the calculated weight loss (summation of P 2 O 5 and SiO 2 amounts as determined by ICP) and the measured weight loss (determined gravimetrically) averaged 4.9%. Results from the ICP method, Fourier transform-infrared spectroscopy (FT-IR), dispersive infrared spectroscopy, electron microprobe, and x-ray fluorescence spectroscopy for the same samples are compared

  3. Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

    Science.gov (United States)

    Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

    2013-05-06

    Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

  4. Femtosecond versus nanosecond laser machining: comparison of induced stresses and structural changes in silicon wafers

    International Nuclear Information System (INIS)

    Amer, M.S.; El-Ashry, M.A.; Dosser, L.R.; Hix, K.E.; Maguire, J.F.; Irwin, Bryan

    2005-01-01

    Laser micromachining has proven to be a very successful tool for precision machining and microfabrication with applications in microelectronics, MEMS, medical device, aerospace, biomedical, and defense applications. Femtosecond (FS) laser micromachining is usually thought to be of minimal heat-affected zone (HAZ) local to the micromachined feature. The assumption of reduced HAZ is attributed to the absence of direct coupling of the laser energy into the thermal modes of the material during irradiation. However, a substantial HAZ is thought to exist when machining with lasers having pulse durations in the nanosecond (NS) regime. In this paper, we compare the results of micromachining a single crystal silicon wafer using a 150-femtosecond and a 30-nanosecond lasers. Induced stress and amorphization of the silicon single crystal were monitored using micro-Raman spectroscopy as a function of the fluence and pulse duration of the incident laser. The onset of average induced stress occurs at lower fluence when machining with the femtosecond pulse laser. Induced stresses were found to maximize at fluence of 44 J cm -2 and 8 J cm -2 for nanosecond and femtosecond pulsed lasers, respectively. In both laser pulse regimes, a maximum induced stress is observed at which point the induced stress begins to decrease as the fluence is increased. The maximum induced stress was comparable at 2.0 GPa and 1.5 GPa for the two lasers. For the nanosecond pulse laser, the induced amorphization reached a plateau of approximately 20% for fluence exceeding 22 J cm -2 . For the femtosecond pulse laser, however, induced amorphization was approximately 17% independent of the laser fluence within the experimental range. These two values can be considered nominally the same within experimental error. For femtosecond laser machining, some effect of the laser polarization on the amount of induced stress and amorphization was also observed

  5. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Science.gov (United States)

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  6. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  7. Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

    Science.gov (United States)

    Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

    2017-09-01

    SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

  8. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    Science.gov (United States)

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  9. Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

    Directory of Open Access Journals (Sweden)

    Di Di

    2014-01-01

    Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

  10. Beneficial defects: exploiting the intrinsic polishing-induced wafer roughness for the catalyst-free growth of Ge in-plane nanowires.

    Science.gov (United States)

    Persichetti, Luca; Sgarlata, Anna; Mori, Stefano; Notarianni, Marco; Cherubini, Valeria; Fanfoni, Massimo; Motta, Nunzio; Balzarotti, Adalberto

    2014-01-01

    We outline a metal-free fabrication route of in-plane Ge nanowires on Ge(001) substrates. By positively exploiting the polishing-induced defects of standard-quality commercial Ge(001) wafers, micrometer-length wires are grown by physical vapor deposition in ultra-high-vacuum environment. The shape of the wires can be tailored by the epitaxial strain induced by subsequent Si deposition, determining a progressive transformation of the wires in SiGe faceted quantum dots. This shape transition is described by finite element simulations of continuous elasticity and gives hints on the equilibrium shape of nanocrystals in the presence of tensile epitaxial strain. 81.07.Gf; 68.35.bg; 68.35.bj; 62.23.Eg.

  11. Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

    Science.gov (United States)

    Norris, D J; Myronov, M; Leadley, D R; Walther, T

    2017-12-01

    We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

  12. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    Science.gov (United States)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  13. Synthesis of thermoresponsive poly(N-isopropylacrylamide) brush on silicon wafer surface via atom transfer radical polymerization

    Energy Technology Data Exchange (ETDEWEB)

    Turan, Eylem; Demirci, Serkan [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey); Caykara, Tuncer, E-mail: caykara@gazi.edu.t [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey)

    2010-08-31

    Thermoresponsive poly(N-isopropylacrylamide) [poly(NIPAM)] brush on silicon wafer surface was prepared by combining the self-assembled monolayer of initiator and atom transfer radical polymerization (ATRP). The resulting polymer brush was characterized by in situ reflectance Fourier transform infrared spectroscopy, atomic force microscopy and ellipsometry techniques. Gel permeation chromatography determination of the number-average molecular weight and polydispersity index of the brush detached from the silicon wafer surface suggested that the surface-initiated ATRP method can provide relatively homogeneous polymer brush. Contact angle measurements exhibited a two-stage increase upon heating over the board temperature range 25-45 {sup o}C, which is in contrast to the fact that free poly(NIPAM) homopolymer in aqueous solution exhibits a phase transition at ca. 34 {sup o}C within a narrow temperature range. The first de-wetting transition takes place at 27 {sup o}C, which can be tentatively attributed to the n-cluster induced collapse of the inner region of poly(NIPAM) brush close to the silicon surface; the second de-wetting transition occurs at 38 {sup o}C, which can be attributed to the outer region of poly(NIPAM) brush, possessing much lower chain density compared to that of the inner part.

  14. Development of polishing methods for Chemical Vapor Deposited Silicon Carbide mirrors for synchrotron radiation

    International Nuclear Information System (INIS)

    Fuchs, B.A.; Brown, N.J.

    1987-01-01

    Material properties of Chemical Vapor Deposited Silicon Carbide (CVD SiC) make it ideal for use in mirrors for synchrotron radiation experiments. We developed methods to grind and polish flat samples of CVD SiC down to measured surface roughness values as low as 1.1 Angstroms rms. We describe the processing details, including observations we made during trial runs with alternative processing recipes. We conclude that pitch polishing using progressively finer diamond abrasive, augmented with specific water based lubricants and additives, produces superior results. Using methods based on these results, a cylindrical and a toroidal mirror, each about 100 x 300mm, were respectively finished by Continental Optical and Frank Cooke, Incorporated. WYCO Interferometry shows these mirrors have surface roughness less than 5.7 Angstroms rms. These mirrors have been installed on the LLNL/UC X-ray Calibration and Standards Facility at the Stanford Synthrotron Radiation Laboratory

  15. Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

    Science.gov (United States)

    Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

    2013-04-01

    In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

  16. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    Science.gov (United States)

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  17. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    International Nuclear Information System (INIS)

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  18. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    International Nuclear Information System (INIS)

    Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

    2010-01-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  19. Interfacial Characteristics of TiN Coatings on SUS304 and Silicon Wafer Substrates with Pulsed Laser Thermal Shock

    International Nuclear Information System (INIS)

    Seo, Nokun; Jeon, Seol; Choi, Youngkue; Shin, Hyun-Gyoo; Lee, Heesoo; Jeon, Min-Seok

    2014-01-01

    TiN coatings prepared on different substrates that had different coefficients of thermal expansion were subjected to pulsed laser thermal shock and observed by using FIB milling to compare the deterioration behaviors. TiN coating on SUS304, which had a larger CTE (⁓17.3 × 10 - 6 /℃) than the coating was degraded with pores and cracks on the surface and showed significant spalling of the coating layer over a certain laser pulses. TiN coating on silicon wafer with a smaller CTE value, ⁓4.2 × 10‒6 /℃, than the coating exhibited less degradation of the coating layer at the same ablation condition. Cracks propagated at the interface were observed in the coating on the silicon wafer, which induced a compressive stress to the coating. The coating on the SUS304 showed less interface cracks while the tensile stress was applied to the coating. Delamination of the coating layer related to the intercolumnar cracks at the interface was observed in both coatings through bright-field TEM analysis.

  20. Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

    International Nuclear Information System (INIS)

    Takahara, Hikari; Mori, Yoshihiro; Shibata, Harumi; Shimazaki, Ayako; Shabani, Mohammad B.; Yamagami, Motoyuki; Yabumoto, Norikuni; Nishihagi, Kazuo; Gohshi, Yohichi

    2013-01-01

    Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10 9 and 5 × 10 10 atoms/cm 2 Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO 2 , silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10 10 atoms/cm 2 . • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies

  1. Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

    International Nuclear Information System (INIS)

    Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

    2002-01-01

    Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

  2. Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

    Science.gov (United States)

    Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

    2013-08-20

    To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

  3. Sidewall patterning - A new wafer-scale method for accurate patterning of vertical silicon structures

    NARCIS (Netherlands)

    Westerik, P. J.; Vijselaar, W. J.C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G.E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that

  4. Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

    Energy Technology Data Exchange (ETDEWEB)

    Rouault de Coligny, P.

    2002-09-15

    This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

  5. A Reuse Evaluation for Solar-Cell Silicon Wafers via Shift Revolution and Tool Rotation Using Magnetic Assistance in Ultrasonic Electrochemical Micromachining

    Directory of Open Access Journals (Sweden)

    P. S. Pa

    2013-01-01

    Full Text Available A new reuse fabrication using a tool module with rotation and revolution through a process of magnetic assistance in ultrasonic electrochemical micromachining (UEMM for removal of the surface layers from silicon wafers of solar cells is demonstrated. The target of the proposed reuse fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach to removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. The high revolution speed of the shift with the high rotation speed of the designed tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. High frequency and high power of ultrasonic with large electrolyte flow rate and high magnetic strengths with a small distance between the two magnets provide a large discharge effect and good removal; only a short period of time is required to remove the epoxy film and Si3N4 layer easily and cleanly.

  6. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Science.gov (United States)

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  7. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

    2017-01-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

  8. Ion-implanted capacitively coupled silicon strip detectors with integrated polysilicon bias resistors processed on a 100 mm wafer

    International Nuclear Information System (INIS)

    Hietanen, I.; Lindgren, J.; Orava, R.; Tuuva, T.; Voutilainen, M.; Brenner, R.; Andersson, M.; Leinonen, K.; Ronkainen, H.

    1991-01-01

    Double-sided silicon strip detectors with integrated coupling capacitors and polysilicon resistors have been processed on a 100 mm wafer. A detector with an active area of 19x19 mm 2 was connected to LSI readout electronics and tested. The strip pitch of the detector is 25 μm on the p-side and 50 μm on the n-side. The readout pitch is 50 μm on both sides. The number of readout strips is 774 and the total number of strips is 1161. On the p-side a signal-to-noise of 35 has been measured using a 90 Sr β-source. The n-side has been studied using a laser. (orig.)

  9. Fabrication of an integrated ΔE-E-silicon detector by wafer bonding using cobalt disilicide

    International Nuclear Information System (INIS)

    Thungstroem, G.; Veldhuizen, E.J. van; Westerberg, L.; Norlin, L.-O.; Petersson, C.S.

    1997-01-01

    The problem concerning mechanical stability of thin self-supporting ΔE detector in a ΔE-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The ΔE-detector has a thickness of 6.5 μm and the E detector 290 μm with an area of 24.8 mm 2 . The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.)

  10. Fabrication of an integrated {Delta}E-E-silicon detector by wafer bonding using cobalt disilicide

    Energy Technology Data Exchange (ETDEWEB)

    Thungstroem, G. [Mid-Sweden Univ., Sundsvall (Sweden). Dept. of Inf. Technol.]|[Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden); Veldhuizen, E.J. van [Uppsala University, Department of Radiation Science, Box 535, S-751 21 Uppsala (Sweden); Westerberg, L. [Uppsala University, The Svedberg Laboratory, Box 533, S-751 21 Uppsala (Sweden); Norlin, L.-O. [Royal Institute of Technology, Department of Physics, Frescativaegen 24, S-104 05 Stockholm (Sweden); Petersson, C.S. [Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden)

    1997-06-01

    The problem concerning mechanical stability of thin self-supporting {Delta}E detector in a {Delta}E-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The {Delta}E-detector has a thickness of 6.5 {mu}m and the E detector 290 {mu}m with an area of 24.8 mm{sup 2}. The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.).

  11. Preliminary reduction of chromium ore using Si sludge generated in silicon wafer manufacturing process

    Directory of Open Access Journals (Sweden)

    Jung W.-G.

    2018-01-01

    Full Text Available In order to promote the recycling of by-product from Si wafer manufacturing process and to develop environment-friend and low cost process for ferrochrome alloy production, a basic study was performed on the preliminary reduction reaction between chromium ore and the Si sludge, comprised of SiC and Si particles, which is recovered from the Si wafer manufacturing process for the semiconductor and solar cell industries. Pellets were first made by mixing chromium ore, Si sludge, and some binders in the designed mixing ratios and were then treated at different temperatures in the 1116°C–1388°C range in an ambient atmosphere. Cordierite and SiO2 were confirmed to be formed in the products after the reduction. Additionally, metal particles were observed in the product with Fe, Cr, and Si components. It is found that temperatures above 1300°C are necessary for the reduction of the chromium ore by the Si sludge. The reduction ratio for Fe was evaluated quantitatively for our experimental conditions, and the proper mixing ratio was suggested for the pre-reduction of the chromium ore by the Si sludge. This study provides basic information for the production of ferrochrome alloys on the pre-reduction of chromium ore using Si sludge.

  12. Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

    Science.gov (United States)

    Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

    2016-11-01

    The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

  13. Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

    Directory of Open Access Journals (Sweden)

    Ali Attaran

    2014-01-01

    Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

  14. Possibility of whole-surface analysis of a silicon wafer with ordinary straight TXRF

    International Nuclear Information System (INIS)

    Mori, Y.; Uemura, K.; Iizuka, Y.

    2000-01-01

    For the analysis of average metal concentration on a semiconductor surface, we customarily use the wet techniques (AAS, typically), that require skilled operators or expensive automated machines for sample pretreatment. The straight TXRF require no pretreatment, on the other hand. However, its detection area is too small (1-2 cm 2 ) to conduct a whole-surface analysis. In fact, it takes more than one day per one wafer (500 s/point x 100-300 points) for a complete mapping. Therefore it has been believed that the whole-surface analysis with straight TXRF is impracticable. It should be noted that the absolute lower limit of detection (LLD) of the straight TXRF is superior to AAS. As an example, the absolute LLD of TXRF for Fe is 0.2 pg (500 s integration), while that of AAS is l0 pg. The required integration time for TXRF to obtain the same LLD of AAS is calculated to be only 0.2 s. This means, in principle, that the whole-surface contamination can be measured in some ten seconds by accumulating 0.2 s mapping. But actually, the adjustment of glancing angle requires several ten seconds per one point, so the above mapping still takes several hours. That is why such a measurement has not been applied to daily analysis so far. However, the influence of glancing angle errors is expected to be reduced through the multi-point measurement. Figure 1 shows an accumulated spectrum of 20 s x 25 points mapping for an IAP wafer doped with Ni. In this measurement, glancing angles were not precisely controlled (the error of glancing angle is ±15 %). A spectrum of 500 s x 1 point measurement for the same wafer is shown in Figure 2. Figures 1 and 2 are almost identical. This suggests that the reduction of glancing angle errors actually works well through multi-points measurement. This method is expected to give better results by increasing the number of measuring points. The overall variation for the final measurement value obtained by multi-point measurement can be assessed by the

  15. Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Takaura, Norikatsu

    1997-10-01

    As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular

  16. Radiation hardness of silicon detectors manufactured on wafers from various sources

    International Nuclear Information System (INIS)

    Dezillie, B.; Bates, S.; Glaser, M.; Lemeilleur, F.; Leroy, C.

    1997-01-01

    Impurity concentrations in the initial silicon material are expected to play an important role for the radiation hardness of silicon detectors, during their irradiation and for their evolution with time after irradiation. This work reports on the experimental results obtained with detectors manufactured using various float-zone (FZ) and epitaxial-grown material. Preliminary results comparing the changes in leakage current and full depletion voltage of FZ and epitaxial detectors as a function of fluence and of time after 10 14 cm -2 proton irradiation are given. The measurement of charge collection efficiency for epitaxial detectors is also presented. (orig.)

  17. Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

    Science.gov (United States)

    Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

    2017-02-15

    An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

  18. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  19. Internal Friction and Young's Modulus Measurements on SiO2 and Ta2O5 Films Done with an Ultra-High Q Silicon-Wafer Suspension

    Directory of Open Access Journals (Sweden)

    Granata M.

    2015-04-01

    Full Text Available In order to study the internal friction of thin films a nodal suspension system called GeNS (Gentle Nodal Suspension has been developed. The key features of this system are: i the possibility to use substrates easily available like silicon wafers; ii extremely low excess losses coming from the suspension system which allows to measure Q factors in excess of 2×108 on 3” diameter wafers; iii reproducibility of measurements within few percent on mechanical losses and 0.01% on resonant frequencies; iv absence of clamping; v the capability to operate at cryogenic temperatures. Measurements at cryogenic temperatures on SiO2 and at room temperature only on Ta2O5 films deposited on silicon are presented.

  20. Neutron activation analysis of low-level element contents in silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Goerner, W [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Berger, A [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Niese, S [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Koehler, M [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Matthes, M [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Gawlik, D [Hahn-Meitner-Institut, Berlin (Germany)

    1997-03-01

    Semiconductor silicon is among the purest materials having ever been produced by modern technology. Thus, it is quite suitable as a primary reference material validating the correctness and the detection capabilities of developed analytical methods. Among them neutron activation analysis plays a competitive role. The U.S. National Institute of Science and Technology (NIST) has initiated and carried out an interlaboratory comparison in order to study the spread of analytical results worldwide evolved by several laboratories dealing with specimens of extreme purity. The outcome of the experiment was intended to review the capabilities of NAA as well as to differentiate between bulk and surface contamination. (orig./DG)

  1. Laser-fired contact formation on metallized and passivated silicon wafers under short pulse durations

    Science.gov (United States)

    Raghavan, Ashwin S.

    The objective of this work is to develop a comprehensive understanding of the physical processes governing laser-fired contact (LFC) formation under microsecond pulse durations. Primary emphasis is placed on understanding how processing parameters influence contact morphology, passivation layer quality, alloying of Al and Si, and contact resistance. In addition, the research seeks to develop a quantitative method to accurately predict the contact geometry, thermal cycles, heat and mass transfer phenomena, and the influence of contact pitch distance on substrate temperatures in order to improve the physical understanding of the underlying processes. Finally, the work seeks to predict how geometry for LFCs produced with microsecond pulses will influence fabrication and performance factors, such as the rear side contacting scheme, rear surface series resistance and effective rear surface recombination rates. The characterization of LFC cross-sections reveals that the use of microsecond pulse durations results in the formation of three-dimensional hemispherical or half-ellipsoidal contact geometries. The LFC is heavily alloyed with Al and Si and is composed of a two-phase Al-Si microstructure that grows from the Si wafer during resolidification. As a result of forming a large three-dimensional contact geometry, the total contact resistance is governed by the interfacial contact area between the LFC and the wafer rather than the planar contact area at the original Al-Si interface within an opening in the passivation layer. By forming three-dimensional LFCs, the total contact resistance is significantly reduced in comparison to that predicted for planar contacts. In addition, despite the high energy densities associated with microsecond pulse durations, the passivation layer is well preserved outside of the immediate contact region. Therefore, the use of microsecond pulse durations can be used to improve device performance by leading to lower total contact resistances

  2. Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

    Science.gov (United States)

    Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

    2013-03-25

    n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

  3. Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

    International Nuclear Information System (INIS)

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

    2013-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

  4. Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

    Directory of Open Access Journals (Sweden)

    Nigel T. Maidment

    2008-08-01

    Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

  5. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    International Nuclear Information System (INIS)

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  6. Corporate array of micromachined dipoles on silicon wafer for 60 GHz communication systems

    KAUST Repository

    Sallam, M. O.

    2013-03-01

    In this paper, an antenna array operating at 60 GHz and realized on 0.675 mm thick silicon substrate is presented. The array is constructed using four micromachined half-wavelength dipoles fed by a corporate feeding network. Isolation between the antenna array and its feeding network is achieved via a ground plane. This arrangement leads to maximizing the broadside radiation with relatively high front-to-back ratio. Simulations have been carried out using both HFSS and CST, which showed very good agreement. Results reveal that the proposed antenna array has good radiation characteristics, where the directivity, gain, and radiation efficiency are around 10.5 dBi, 9.5 dBi, and 79%, respectively. © 2013 IEEE.

  7. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  8. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Science.gov (United States)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  9. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  10. Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

    International Nuclear Information System (INIS)

    Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

    1993-01-01

    The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

  11. Linear self-assembly and grafting of gold nanorods into arrayed micrometer-long nanowires on a silicon wafer via a combined top-down/bottom-up approach.

    Science.gov (United States)

    Lestini, Elena; Andrei, Codrin; Zerulla, Dominic

    2018-01-01

    Macroscopically long wire-like arrangements of gold nanoparticles were obtained by controlled evaporation and partial coalescence of an aqueous colloidal solution of capped CTAB-Au nanorods onto a functionalised 3-mercaptopropyl trimethoxysilane (MPTMS) silicon substrate, using a removable, silicon wafer with a hydrophobic surface that serves as a "handrail" for the initial nanorods' linear self-assembly. The wire-like structures display a quasi-continuous pattern by thermal annealing of the gold nanorods when the solvent (i.e. water) is evaporated at temperatures rising from 20°C to 140°C. Formation of both single and self-replicating parallel 1D-superstructures consisting of two or even three wires is observed and explained under such conditions.

  12. Research status in ultra-precision machining of silicon carbide parts by oxidation-assisted polishing

    Directory of Open Access Journals (Sweden)

    Xinmin SHEN

    2016-10-01

    Full Text Available Oxidation-assisted polishing is an important machining method for obtaining SiC parts with high precision. Through plasma oxidation, thermal oxidation, and anodic oxidation, soft oxide can be obtained on the RS-SiC substrate. With the assistance of abrasive polishing to remove the oxide rapidly, the material removal rate can be increased and the surface quality can be improved. The research results indicate that the surface roughness root-mean-square (RMS and roughness-average (Ra can reach 0.626 nm and 0.480 nm by plasma oxidation-assisted polishing; in thermal oxidation-assisted polishing, the RMS and Ra can be 0.920 nm and 0.726 nm; in anodic oxidation, the calculated oxidation rate is 5.3 nm/s based on Deal-Grove model, and the RMS and Ra are 4.428 nm and 3.453 nm respectively in anodic oxidation-assisted polishing. The oxidation-assisted polishing can be propitious to improve the process level in machining RS-SiC, which would promote the application of SiC parts in optics and ceramics fields.

  13. Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

    Energy Technology Data Exchange (ETDEWEB)

    Tiriolo, Raffaele [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Rangnekar, Neel [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Zhang, Han [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Shete, Meera [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Bai, Peng [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Nelson, John [Characterization Facility, University of Minnesota, 12 Shepherd Labs, 100 Union St. S.E. Minneapolis MN 55455 USA; Karapetrova, Evguenia [Surface Scattering and Microdiffraction, X-ray Science Division, Argonne National Laboratory, 9700 S. Cass Ave, Building 438-D002 Argonne IL 60439 USA; Macosko, Christopher W. [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Siepmann, Joern Ilja [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Lamanna, Ernesto [Department of Health Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Lavano, Angelo [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Tsapatsis, Michael [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA

    2017-05-08

    A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.

  14. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    NARCIS (Netherlands)

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  15. Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

    International Nuclear Information System (INIS)

    Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

    2009-01-01

    Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

  16. An experimental and theoretical study of pendellösung fringes in synchrotron section topographs of silicon wafers.

    Science.gov (United States)

    Partanen, J; Tuomi, T

    1990-01-01

    X-ray section topographs of nearly perfect Czochralski-grown wafers were made with synchrotron radiation having a continuous spectrum. An intensity curve measured from the x-ray film is compared to the calculated curve obtained using the dynamical theory of x-ray diffraction. A computer simulation of the topograph is also presented. A good agreement between theory and experiment is found except in the middle part of the topograph.

  17. Manipulation of polystyrene nanoparticles on a silicon wafer in the peak force tapping mode in water: pH-dependent friction and adhesion force

    Energy Technology Data Exchange (ETDEWEB)

    Schiwek, Simon; Stark, Robert W., E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de; Dietz, Christian, E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany); Physics of Surfaces, Institute of Materials Science, Technische Universität Darmstadt, Alarich-Weiss-Str. 16, 64287 Darmstadt (Germany); Heim, Lars-Oliver [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany)

    2015-03-14

    The friction force between nanoparticles and a silicon wafer is a crucial parameter for cleaning processes in the semiconductor industry. However, little is known about the pH-dependency of the friction forces and the shear strength at the interface. Here, we push polystyrene nanoparticles, 100 nm in diameter, with the tip of an atomic force microscope and measure the pH-dependency of the friction, adhesion, and normal forces on a silicon substrate covered with a native silicon dioxide layer. The peak force tapping mode was applied to control the vertical force on these particles. We successively increased the applied load until the particles started to move. The main advantage of this technique over single manipulation processes is the achievement of a large number of manipulation events in short time and in a straightforward manner. Geometrical considerations of the interaction forces at the tip-particle interface allowed us to calculate the friction force and shear strength from the applied normal force depending on the pH of an aqueous solution. The results clearly demonstrated that particle removal should be performed with a basic solution at pH 9 because of the low interaction forces between particle and substrate.

  18. Elastocapillary folding of three dimensional micro-structures using water pumped through the wafer via a silicon nitride tube

    NARCIS (Netherlands)

    Legrain, A.B.H.; Berenschot, Johan W.; Sanders, Remco G.P.; Ma, Kechun; Tas, Niels Roelof; Abelmann, Leon

    2011-01-01

    In this paper we present the first investigation of a batch method for folding of threedimensional micrometer-sized silicon nitride structures by capillary forces. Silicon nitride tubes have been designed and fabricated using DRIE at the center of the planar origami patterns of the structures. Water

  19. Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

    Science.gov (United States)

    Egelkrout, D. W.

    1981-01-01

    Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

  20. Serial section scanning electron microscopy (S3EM) on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Science.gov (United States)

    Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

    2012-01-01

    High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3)EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3) volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3)EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3)EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  1. Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Directory of Open Access Journals (Sweden)

    Heinz Horstmann

    Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  2. A simple chemical method for the separation of phosphorus interfering the trace element determinations by neutron activation analysis in high doped silicon wafers

    International Nuclear Information System (INIS)

    Wagler, H.; Flachowsky, J.

    1986-01-01

    Neutron activation analysis is one of the most available method for the determination of trace elements, but in the case of P-doped silicon wafers the 32 P-activity interferes the gamma spectrometry. It is not possible to determine the trace elements without chemical manipulations. On the other hand, time consuming chemical separations should be avoided. Therefore, a simple and rapid P-separation method has to be developed, in which the following twelve trace elements should be taken into consideration: Ag, As, Au, Co, Cr, Cu, Fe, Mo, Na, Sb, W, and Zn. After acid oxidative dissolution of the activated sample, P is present as phosphate ion. The phosphate ion is removed by precipitation as BiPO 4 . (author)

  3. Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives: Synthesis and the effects on chemical mechanical polishing (CMP) performances of sapphire wafers

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Tingting; Lei, Hong, E-mail: hong_lei2005@aliyun.com

    2017-08-15

    Highlights: • The novel Nd{sup 3+}-doped colloidal SiO{sub 2} abrasives were synthesized by seed-introduced method. • The Nd{sup 3+}-doped colloidal SiO{sub 2} abrasives exhibited lower Ra and higher MRR on sapphire during CMP. • The cores SiO{sub 2} were coated by the shells (SiO{sub 2}, Nd{sub 2}Si{sub 2}O{sub 7} and Nd(OH){sub 3}) via chemical bonds and hydrogen bonds. • XPS analysis revealed the solid-state chemical reaction between Nd{sup 3+}-doped colloidal SiO{sub 2} abrasives and sapphire during CMP. - Abstract: Abrasive is one of the most important factors in chemical mechanical polishing (CMP). In order to improve the polishing qualities of sapphire substrates, the novel Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives were prepared by seed-induced growth method. In this work, there were a series of condensation reactions during the synthesis process of Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives and the silica cores were coated by shells (which contains SiO{sub 2}, Nd{sub 2}Si{sub 2}O{sub 7} and Nd(OH){sub 3}) via chemical bonds and hydrogen bonds in the Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives, which made the composite abrasives’ core-shell structure more sTable Scanning electron microscopy (SEM) showed that Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives were spherical and uniform in size. And the acting mechanisms of Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives on sapphire in CMP were investigated. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis and X-ray photoelectron spectroscopy (XPS) analysis demonstrated that the solid-state chemical reactions between the shells (which contained SiO{sub 2}, Nd{sub 2}Si{sub 2}O{sub 7} and Nd(OH){sub 3}) of Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives and the sapphire occurred during the CMP process. Furthermore, Nd{sup 3+}-doped colloidal SiO{sub 2} composite abrasives exhibited lower surface roughness and

  4. Crystallization behavior of polyethylene on silicon wafers in solution casting processes traced by time-resolved measurements of synchrotron grazing-incidence small-angle and wide-angle X-ray scattering

    International Nuclear Information System (INIS)

    Sasaki, S; Masunaga, H; Takata, M; Itou, K; Tashiro, K; Okuda, H; Takahara, A

    2009-01-01

    Crystallization behavior of polyethylene (PE) on silicon wafers in solution casting processes has been successfully traced by time-resolved grazing-incidence small-angle and wide-angle X-ray scattering (GISWAXS) measurements utilizing synchrotron radiation. A p-xylene solution of PE kept at ca. 343 K was dropped on a silicon wafer at ca. 298 K. While the p-xylene evaporated naturally from the dropped solution sample, PE chains crystallized to be a thin film. Raman spectral measurements were performed simultaneously with the GISWAXS measurements to evaluate quantitatively the p-xylene the dropped solution contained. Grazing-incidence wide-angle X-ray scattering (GIWAXS) patterns indicated nucleation and crystal growth in the dropped solution and the following as-cast film. GIWAXS and Raman spectral data revealed that crystallization of PE was enhanced after complete evaporation of the p-xylene from the dropped solution. The [110] and [200] directions of the orthorhombic PE crystal became relatively parallel to the wafer surface with time, which implied that the flat-on lamellae with respect to the wafer surface were mainly formed in the as-cast film. On the other hand, grazing-incidence small-angle X-ray scattering (GISAXS) patterns implied formation of isolated lamellae in the dropped solution. The lamellae and amorphous might alternatively be stacked in the preferred direction perpendicular to the wafer surface. The synchrotron GISWAXS experimental method could be applied for kinetic study on hierarchical structure of polymer thin films.

  5. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  6. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  7. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers.

    Science.gov (United States)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K(alpha)0.28 keV and Al K(alpha)1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K(alpha) (approximately 6 nm rms) is significantly larger than approximately 1 nm at Al K(alpha). This can be explained by different coherent lengths at two energies.

  8. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y.; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K{alpha}0.28 keV and Al K{alpha}1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K{alpha} ({approx}6 nm rms) is significantly larger than {approx}1 nm at Al K{alpha}. This can be explained by different coherent lengths at two energies.

  9. Characterization of the first double-sided 3D radiation sensors fabricated at FBK on 6-inch silicon wafers

    International Nuclear Information System (INIS)

    Sultan, D.M.S.; Mendicino, R.; Betta, G.-F. Dalla; Boscardin, M.; Ronchin, S.; Zorzi, N.

    2015-01-01

    Following 3D pixel sensor production for the ATLAS Insertable B-Layer, Fondazione Bruno Kessler (FBK) fabrication facility has recently been upgraded to process 6-inch wafers. In 2014, a test batch was fabricated to check for possible issues relevant to this upgrade. While maintaining a double-sided fabrication technology, some process modifications have been investigated. We report here on the technology and the design of this batch, and present selected results from the electrical characterization of sensors and test structures. Notably, the breakdown voltage is shown to exceed 200 V before irradiation, much higher than in earlier productions, demonstrating robustness in terms of radiation hardness for forthcoming productions aimed at High Luminosity LHC upgrades

  10. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    International Nuclear Information System (INIS)

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  11. Novel ceria-polymer microcomposites for chemical mechanical polishing

    International Nuclear Information System (INIS)

    Coutinho, Cecil A.; Mudhivarthi, Subrahmanya R.; Kumar, Ashok; Gupta, Vinay K.

    2008-01-01

    Abrasive particles are key components in slurries for chemical mechanical polishing (CMP). Since the particle characteristics determine surface quality of wafers during polishing, in this research, novel abrasive composite particles have been developed. These composite particles contain nanoparticles of ceria dispersed within cross-linked, polymeric microspheres such that the average mass fraction of ceria is approximately 50% in the particles. The microspheres are formed by co-polymerization of N-isopropylacrylamide (NIPAM) with 3-(trimethoxysilyl)propyl methacrylate (MPS) and contain interpenetrating (IP) chains of poly(acrylic acid) (PAAc). Infrared spectroscopy, dynamic light scattering, and transmission electron microscopy are employed to characterize the composite particles. Planarization of silicon dioxide wafers is studied on a bench-top CMP tester and the polished surfaces are characterized by ellipsometry, atomic force and optical microscopy. Slurries formed from the composite ceria-polymer particles lead to lower topographical variations and surface roughness than slurries of only ceria nanoparticles even though both slurries achieve similar removal rates of ∼100 nm/min for similar ceria content. Polishing with the novel composite particles gives surfaces devoid of scratches and particle deposition, which makes these particles suitable for the next generation slurries in CMP

  12. Novel ceria-polymer microcomposites for chemical mechanical polishing

    Energy Technology Data Exchange (ETDEWEB)

    Coutinho, Cecil A. [Department of Chemical and Biomedical Engineering, University of South Florida (United States); Mudhivarthi, Subrahmanya R.; Kumar, Ashok [Nanomaterials and Nanomanufacturing Research Center, University of South Florida (United States); Department of Mechanical Engineering, University of South Florida (United States); Gupta, Vinay K. [Department of Chemical and Biomedical Engineering, University of South Florida (United States)], E-mail: vkgupta@eng.usf.edu

    2008-12-30

    Abrasive particles are key components in slurries for chemical mechanical polishing (CMP). Since the particle characteristics determine surface quality of wafers during polishing, in this research, novel abrasive composite particles have been developed. These composite particles contain nanoparticles of ceria dispersed within cross-linked, polymeric microspheres such that the average mass fraction of ceria is approximately 50% in the particles. The microspheres are formed by co-polymerization of N-isopropylacrylamide (NIPAM) with 3-(trimethoxysilyl)propyl methacrylate (MPS) and contain interpenetrating (IP) chains of poly(acrylic acid) (PAAc). Infrared spectroscopy, dynamic light scattering, and transmission electron microscopy are employed to characterize the composite particles. Planarization of silicon dioxide wafers is studied on a bench-top CMP tester and the polished surfaces are characterized by ellipsometry, atomic force and optical microscopy. Slurries formed from the composite ceria-polymer particles lead to lower topographical variations and surface roughness than slurries of only ceria nanoparticles even though both slurries achieve similar removal rates of {approx}100 nm/min for similar ceria content. Polishing with the novel composite particles gives surfaces devoid of scratches and particle deposition, which makes these particles suitable for the next generation slurries in CMP.

  13. Strain of laser annealed silicon surfaces

    Science.gov (United States)

    Nemanich, R. J.; Haneman, D.

    1982-05-01

    High resolution Raman scattering measurements have been carried out on pulse and continuous-wave laser annealed silicon samples with various surface preparations. These included polished and ion-bombarded wafers, and saw-cut crystals. The pulse annealing treatments were carried out in ultrahigh vacuum and in air. The residual strain was inferred from the frequency shift of the first-order Raman active mode of Si, and was detectable in the range 10-2-10-3 in all except the polished samples.

  14. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  15. Temperature-dependent interface characteristic of silicon wafer bonding based on an amorphous germanium layer deposited by DC-magnetron sputtering

    Science.gov (United States)

    Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

    2018-03-01

    We report a near-bubble-free low-temperature silicon (Si) wafer bonding with a thin amorphous Ge (a-Ge) intermediate layer. The DC-magnetron-sputtered a-Ge film on Si is demonstrated to be extremely flat (RMS = 0.28 nm) and hydrophilic (contact angle = 3°). The effect of the post-annealing temperature on the surface morphology and crystallinity of a-Ge film at the bonded interface is systematically identified. The relationship among the bubble density, annealing temperature, and crystallinity of a-Ge film is also clearly clarified. The crystallization of a-Ge film firstly appears at the bubble region. More interesting feature is that the crystallization starts from the center of the bubbles and sprawls to the bubble edge gradually. The H2 by-product is finally absorbed by intermediate Ge layer with crystalline phase after post annealing. Moreover, the whole a-Ge film out of the bubble totally crystallizes when the annealing time increases. This Ge integration at the bubble region leads to the decrease of the bubble density, which in turn increases the bonding strength.

  16. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  17. Electrodeposition of three-dimensionally assembled platinum spheres on a gold-coated silicon wafer, and its application to nonenzymatic sensing of glucose

    International Nuclear Information System (INIS)

    Roh, Seongjin; Kim, Jongwon

    2015-01-01

    We report on a method of single-step electrodeposition of three-dimensionally (3-D) assembled Pt spheres on a gold-coated silicon wafer. The 3-D interconnected Pt spheres could be electrodeposited by applying a negative potential (−0.8 V, vs. Ag/AgCl) in neutral electrolytes containing KClO 4 . The application of such a negative potential is not possible in acidic solutions because of the formation of hydrogen. Scanning electron microscopy revealed that the seed Pt particles first grew to a certain size, and then form Pt spheres interconnected in multiple layers. The resulting 3-D assembled Pt sphere structures warrants a high surface area, and this property was utilized for the selective and sensitive amperometric determination of glucose at a working potential of 0.4 V (vs. Ag/AgCl), at near neutral pH values and in the presence of 0.1 M chloride. This straightforward method for the fabrication of 3-D assembled Pt sphere structures offers new opportunities for electroanalytical and electrocatalytic sensing based on porous Pt surfaces (author)

  18. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  19. Doping profile measurement on textured silicon surface

    Science.gov (United States)

    Essa, Zahi; Taleb, Nadjib; Sermage, Bernard; Broussillou, Cédric; Bazer-Bachi, Barbara; Quillec, Maurice

    2018-04-01

    In crystalline silicon solar cells, the front surface is textured in order to lower the reflection of the incident light and increase the efficiency of the cell. This texturing whose dimensions are a few micrometers wide and high, often makes it difficult to determine the doping profile measurement. We have measured by secondary ion mass spectrometry (SIMS) and electrochemical capacitance voltage profiling the doping profile of implanted phosphorus in alkaline textured and in polished monocrystalline silicon wafers. The paper shows that SIMS gives accurate results provided the primary ion impact angle is small enough. Moreover, the comparison between these two techniques gives an estimation of the concentration of electrically inactive phosphorus atoms.

  20. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  1. Xe{sup +} ion beam induced rippled structures on Si miscut wafers

    Energy Technology Data Exchange (ETDEWEB)

    Hanisch, Antje; Grenzer, Joerg [Forschungszentrum Dresden-Rossendorf, Dresden (Germany); Biermanns, Andreas; Pietsch, Ullrich [Institute of Physics, University of Siegen (Germany)

    2009-07-01

    We report on the influence of the initial roughness and crystallography of the substrate on the formation of self-organized ripple structures on semiconductors surfaces by noble gas ion bombardment. The Bradley-Harper theory predicts that an initial roughness is most important for starting the sputtering process which in the ends leads to the evolution of regular patterns. We produced periodic structures with intermediate Xe{sup +} ion energies (5-70 keV) at different incidence and azimuthal angles which lead to the assumption that also crystallography plays a role at the beginning of ripple evolution. Most of the previous investigations started from the original roughness of a polished silicon wafer. We used (001) silicon wafers with a miscut angle of 1 , 5 and 10 towards[110]. We studied the ripple formation keeping the ion beam parallel to the[111],[-1-11] or[-111] direction, i.e. parallel, antiparallel or perpendicular to the miscut direction[110]. The parallel and antiparallel case implies a variation of the incidence angle with increased roughness over the surface step terraces. The perpendicular orientation means almost no roughness. The results were compared to normal Si(001) and Si(111) wafers.

  2. Silicon-based metallic micro grid for electron field emission

    International Nuclear Information System (INIS)

    Kim, Jaehong; Jeon, Seok-Gy; Kim, Jung-Il; Kim, Geun-Ju; Heo, Duchang; Shin, Dong Hoon; Sun, Yuning; Lee, Cheol Jin

    2012-01-01

    A micro-scale metal grid based on a silicon frame for application to electron field emission devices is introduced and experimentally demonstrated. A silicon lattice containing aperture holes with an area of 80 × 80 µm 2 and a thickness of 10 µm is precisely manufactured by dry etching the silicon on one side of a double-polished silicon wafer and by wet etching the opposite side. Because a silicon lattice is more rigid than a pure metal lattice, a thin layer of Au/Ti deposited on the silicon lattice for voltage application can be more resistant to the geometric stress caused by the applied electric field. The micro-fabrication process, the images of the fabricated grid with 88% geometric transparency and the surface profile measurement after thermal feasibility testing up to 700 °C are presented. (paper)

  3. Chemical Mechanical Polishing Optimization for 4H-SiC

    National Research Council Canada - National Science Library

    Neslen, Craig

    2000-01-01

    .... Preliminary chemical mechanical polishing (CMP) studies of 1 3/8" 4H-SiC wafers were performed in an attempt to identify the polishing parameter values that result in a maximum material removal rate and thus reduce substrate polishing time...

  4. Comparison of aggregation behaviors between ionic liquid-type imidazolium gemini surfactant [C12-4-C12im]Br2 and its monomer [C12mim]Br on silicon wafer.

    Science.gov (United States)

    Ao, Mingqi; Xu, Guiying; Pang, Jinyu; Zhao, Taotao

    2009-09-01

    The aggregation of ionic liquid-type imidazolium gemini surfactant [C(12)-4-C(12)im]Br(2) on silicon wafer, which is compared with its monomer [C(12)mim]Br, have been studied. AFM morphology images and contact angle measurements suggest that the aggregations of [C(12)-4-C(12)im]Br(2) and [C(12)mim]Br on silicon wafer follow different mechanisms. Below the critical surface aggregation concentrations (CSAC), both surfactant molecules are adsorbed with their hydrophobic tails facing the air. But above the CSAC, [C(12)-4-C(12)im]Br(2) molecules finally form a bilayer structure with hydrophilic head groups facing the air, whereas [C(12)mim]Br molecules form a multilayer structure, and with increasing its concentration, the layer numbers increase with the hydrophobic chains and hydrophilic head groups facing the air by turns. Besides, the watery wettability of [C(12)-4-C(12)im]Br(2)-treated silica surface is lower than that of [C(12)mim]Br at the concentration of 5.0 cmc, and the infrared spectroscopy suggests that the poorer watery wettability of [C(12)-4-C(12)im]Br(2) may be relative to the less-ordered packing of methylene chains inside the aggregate. These different aggregation behaviors for the two surfactants ascribe to the different molecular structures and electrostatic interactions. This work would have certain theoretical guidance meaning on the modification of solid surface.

  5. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  6. Analysis of temperature profiles and the mechanism of silicon substrate plastic deformation under epitaxial growth

    International Nuclear Information System (INIS)

    Mirkurbanov, H.A.; Sazhnev, S.V.; Timofeev, V.N.

    2004-01-01

    Full text: Thermal treatment of silicon wafers holds one of the major place in the manufacturing of semi-conductor devices. Thermal treatment includes wafer annealing, thermal oxidation, epitaxial growing etc. Quality of wafers in the high-temperature processes (900-1200 deg C) is estimated by the density of structural defects, including areas of plastic deformation, which are shown as the slip lines appearance. Such areas amount to 50-60 % of total wafer surface. The plastic deformation is caused by the thermal stresses. Experimental and theoretical researches allowed to determine thermal balance and to construct a temperature profiles throughout the plate surface. Thermal stresses are caused by temperature drop along the radius of a wafer and at the basic peripheral ring. The threshold temperature drop between center f a wafer and its peripherals (ΔT) for slip lines appearance, amounts to 15-17 deg. C. At the operating temperature of 900-1200 deg. C and ΔT>20 deg. C, the stresses reach the silicon yield point. According to the results of the researches of structure and stress profiles in a wafer, the mechanism of slip lines formation has been constructed. A source of dislocations is the rear broken layer of thickness 8-10 microns, formed after polishing. The micro-fissures with a density 10 5 -10 6 cm -2 are the sources of dislocations. Dislocations move on a surface of a wafer into a slip plane (111). On a wafer surface with orientation (111) it is possible to allocate zones where the tangential stress vector is most favorably directed with respect to a slip plane leaving on a surface, i.e. the shift stresses are maximal in the slip plane. The way to eliminate plastic deformation is to lower the temperature drop to a level of <15 deg. C and elimination of the broken layer in wafer

  7. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  8. Investigating reliability attributes of silicon photovoltaic cells - An overview

    Science.gov (United States)

    Royal, E. L.

    1982-01-01

    Reliability attributes are being developed on a wide variety of advanced single-crystal silicon solar cells. Two separate investigations: cell-contact integrity (metal-to-silicon adherence), and cracked cells identified with fracture-strength-reducing flaws are discussed. In the cell-contact-integrity investigation, analysis of contact pull-strength data shows that cell types made with different metallization technologies, i.e., vacuum, plated, screen-printed and soldered, have appreciably different reliability attributes. In the second investigation, fracture strength was measured using Czochralski wafers and cells taken at various stages of processing and differences were noted. Fracture strength, which is believed to be governed by flaws introduced during wafer sawing, was observed to improve (increase) after chemical polishing and other process steps that tend to remove surface and edge flaws.

  9. A Study of Polishing Feature of Ultrasonic-Assisted Vibration Method in Bamboo Charcoal

    Directory of Open Access Journals (Sweden)

    Hsin-Min Lee

    2017-01-01

    Full Text Available Focusing on the feature of porosity in bamboo charcoal, this study applies the ultrasonic-assisted vibration method to perform surface polishing of the silicon wafer workpiece. The self-developed bamboo charcoal polishing spindle and ultrasonic- assisted vibration mechanism are attached to a single lapping machine. In the machining process, ultrasonic vibration enables the diamond slurry to smoothly pass through the microscopic holes of bamboo charcoal; the end of the bamboo charcoalis able to continue machining on the surface of the workpiece through the grasping force which exists in the microscopic holes. Under the polishing and machining parameters of ultrasonic-assisted vibration, with a diamond slurry concentration of 0.3%, the experimental results show a polishing time of 20 min, a loading of 25 N on the workpiece surface, a spindle speed of 1200 rpm, a vibration frequency of 30 kHz and the original surface roughness value of Ra 0.252 μm equals that of a mirror-like surface at Ra 0.017 μm. These research results prove that by using bamboo charcoal and ultrasonic-assisted vibration for polishing, a very good improvement can be achieved on the workpiece surface.

  10. Surface qualities after chemical-mechanical polishing on thin films

    International Nuclear Information System (INIS)

    Fu, Wei-En; Lin, Tzeng-Yow; Chen, Meng-Ke; Chen, Chao-Chang A.

    2009-01-01

    Demands for substrate and film surface planarizations significantly increase as the feature sizes of Integrated Circuit (IC) components continue to shrink. Chemical Mechanical Polishing (CMP), incorporating chemical and mechanical interactions to planarize chemically modified surface layers, has been one of the major manufacturing processes to provide global and local surface planarizations in IC fabrications. Not only is the material removal rate a concern, the qualities of the CMP produced surface are critical as well, such as surface finish, defects and surface stresses. This paper is to examine the CMP produced surface roughness on tungsten or W thin films based on the CMP process conditions. The W thin films with thickness below 1000 nm on silicon wafer were chemical-mechanical polished at different down pressures and platen speeds to produce different surface roughness. The surface roughness measurements were performed by an atomic force microscope (DI D3100). Results show that the quality of surface finish (R a value) is determined by the combined effects of down pressures and platen speeds. An optimal polishing condition is, then, possible for selecting the down pressures and platen speeds.

  11. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Science.gov (United States)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  12. The Covalent Binding of Photosensitive Dyes to Monocrystalline Silicon Surface and Their Spectral Response

    Institute of Scientific and Technical Information of China (English)

    郭志新; 郝纪祥; 张祖训; 曹子祥

    1993-01-01

    A chemical method is proposed to bond photo-sensitive dyes directly to the surface of polished monocrystalline silicon. A methincyanine dye and a trimethincyanine dye have been bonded covalently onto silicon surface through Si—N bond, which are characterized by XPS technique and laser Raman spectra. Photovoltaic effect has been observed with the In/dye/n-Si sandwich devices composed of the dye-bonded n-Si wafers. Significant spectral response shows the characteristic absorptance maxima of the bonded dyes.

  13. Low surface damage dry etched black silicon

    Science.gov (United States)

    Plakhotnyuk, Maksym M.; Gaudig, Maria; Davidsen, Rasmus Schmidt; Lindhard, Jonas Michael; Hirsch, Jens; Lausch, Dominik; Schmidt, Michael Stenbæk; Stamate, Eugen; Hansen, Ole

    2017-10-01

    Black silicon (bSi) is promising for integration into silicon solar cell fabrication flow due to its excellent light trapping and low reflectance, and a continuously improving passivation. However, intensive ion bombardment during the reactive ion etching used to fabricate bSi induces surface damage that causes significant recombination. Here, we present a process optimization strategy for bSi, where surface damage is reduced and surface passivation is improved while excellent light trapping and low reflectance are maintained. We demonstrate that reduction of the capacitively coupled plasma power, during reactive ion etching at non-cryogenic temperature (-20 °C), preserves the reflectivity below 1% and improves the effective minority carrier lifetime due to reduced ion energy. We investigate the effect of the etching process on the surface morphology, light trapping, reflectance, transmittance, and effective lifetime of bSi. Additional surface passivation using atomic layer deposition of Al2O3 significantly improves the effective lifetime. For n-type wafers, the lifetime reaches 12 ms for polished and 7.5 ms for bSi surfaces. For p-type wafers, the lifetime reaches 800 μs for both polished and bSi surfaces.

  14. UV laser-induced high resolution cleaving of Si wafers for micro-nano devices and polymeric waveguide characterization

    International Nuclear Information System (INIS)

    Casquel, R.; Holgado, M.; Garcia-Ballesteros, J.J.; Zinoviev, K.; Fernandez-Sanchez, C.; Sanza, F.J.; Molpeceres, C.; Laguna, M.F.; Llobera, A.; Ocana, J.L.; Dominguez, C.

    2011-01-01

    In this work we propose a method for cleaving silicon-based photonic chips by using a laser based micromachining system, consisting of a ND:YVO 4 laser emitting at 355 nm in nanosecond pulse regime and a micropositioning system. The laser makes grooved marks placed at the desired locations and directions where cleaves have to be initiated, and after several processing steps, a crack appears and propagate along the crystallographic planes of the silicon wafer. This allows cleavage of the chips automatically and with high positioning accuracy, and provides polished vertical facets with better quality than the obtained with other cleaving process, which eases the optical characterization of photonic devices. This method has been found to be particularly useful when cleaving small-sized chips, where manual cleaving is hard to perform; and also for polymeric waveguides, whose facets get damaged or even destroyed with polishing or manual cleaving processing. Influence of length of the grooved line and speed of processing is studied for a variety of silicon chips. An application for cleaving and characterizing sol-gel waveguides is presented. The total amount of light coupled is higher than when using any other procedure.

  15. UV laser-induced high resolution cleaving of Si wafers for micro-nano devices and polymeric waveguide characterization

    Energy Technology Data Exchange (ETDEWEB)

    Casquel, R., E-mail: rafael.casquel@upm.es [Centro Laser UPM, Universidad Politecnica de Madrid, Campus Sur UPM, 28031 Madrid (Spain); Holgado, M.; Garcia-Ballesteros, J.J. [Centro Laser UPM, Universidad Politecnica de Madrid, Campus Sur UPM, 28031 Madrid (Spain); Zinoviev, K.; Fernandez-Sanchez, C. [Instituto de Microelectronica de Barcelona, Centro Nacional de Microelectronica - CSIC, Campus Universidad Autonoma de Barcelona, 08193 Bellaterra, Barcelona (Spain); Sanza, F.J.; Molpeceres, C.; Laguna, M.F. [Centro Laser UPM, Universidad Politecnica de Madrid, Campus Sur UPM, 28031 Madrid (Spain); Llobera, A. [Instituto de Microelectronica de Barcelona, Centro Nacional de Microelectronica - CSIC, Campus Universidad Autonoma de Barcelona, 08193 Bellaterra, Barcelona (Spain); Ocana, J.L. [Centro Laser UPM, Universidad Politecnica de Madrid, Campus Sur UPM, 28031 Madrid (Spain); Dominguez, C. [Instituto de Microelectronica de Barcelona, Centro Nacional de Microelectronica - CSIC, Campus Universidad Autonoma de Barcelona, 08193 Bellaterra, Barcelona (Spain)

    2011-04-01

    In this work we propose a method for cleaving silicon-based photonic chips by using a laser based micromachining system, consisting of a ND:YVO{sub 4} laser emitting at 355 nm in nanosecond pulse regime and a micropositioning system. The laser makes grooved marks placed at the desired locations and directions where cleaves have to be initiated, and after several processing steps, a crack appears and propagate along the crystallographic planes of the silicon wafer. This allows cleavage of the chips automatically and with high positioning accuracy, and provides polished vertical facets with better quality than the obtained with other cleaving process, which eases the optical characterization of photonic devices. This method has been found to be particularly useful when cleaving small-sized chips, where manual cleaving is hard to perform; and also for polymeric waveguides, whose facets get damaged or even destroyed with polishing or manual cleaving processing. Influence of length of the grooved line and speed of processing is studied for a variety of silicon chips. An application for cleaving and characterizing sol-gel waveguides is presented. The total amount of light coupled is higher than when using any other procedure.

  16. Development of thin film measurement program of wafer for spin etcher

    International Nuclear Information System (INIS)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  17. Development of thin film measurement program of wafer for spin etcher

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  18. Study of Pneumatic Servo Loading System in Double-Sided Polishing

    International Nuclear Information System (INIS)

    Qian, N; Ruan, J; Li, W

    2006-01-01

    The precise double-sided polishing process is one of the main methods to get the ultra-smooth surface of workpiece. In double-sided polishing machine, a loading system is required to be able to precisely control the load superimposed on the workpiece, while the polishing is being carried out. A pneumatic servo loading system is proposed for this purpose. In the pneumatic servo system, the servo valve, which acts both the electrical to mechanical converter and the power amplifier, has a substantial influence on the performance of the loading system. Therefore a specially designed pneumatic digital servo valve is applied in the control system. In this paper, the construction of the pneumatic servo loading system in double-sided polishing machine and control strategy associated with the digital servo valve are first addressed. The mathematical model of the system established and the hardware of the pneumatic servo system is designed. Finally, the experiments are carried out by measuring the practical load on the workpiece and the quality of the surface finish. It is demonstrated that the error rate of load is less than 5% and a super-smooth surface of silicon wafer with roughness Ra 0.401 nm can be obtained

  19. Wafer edge overlay control solution for N7 and beyond

    Science.gov (United States)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  20. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Directory of Open Access Journals (Sweden)

    N. Daix

    2014-08-01

    Full Text Available We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  1. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Energy Technology Data Exchange (ETDEWEB)

    Daix, N., E-mail: dai@zurich.ibm.com; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J. [IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Hartmann, J. M. [CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France); Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D. [IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  2. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Science.gov (United States)

    Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  3. Nickel in silicon: Room-temperature in-diffusion and interaction with radiation defects

    Energy Technology Data Exchange (ETDEWEB)

    Yarykin, Nikolai [Institute of Microelectronics Technology, RAS, Chernogolovka (Russian Federation); Weber, Joerg [Technische Universitaet Dresden (Germany)

    2017-07-15

    Nickel is incorporated into silicon wafers during chemomechanical polishing in an alkaline Ni-contaminated slurry at room temperature. The nickel in-diffusion is detected by DLTS depth profiles of a novel Ni{sub 183} level, which is formed due to a reaction between the diffusing nickel and the VO centers introduced before the polishing. The Ni{sub 183} profile extends up to 10 μm after a 2 min polishing. The available data provide a lower estimate for the room-temperature nickel diffusivity D{sub Ni} > 10{sup -9} cm{sup 2} s{sup -1}. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  4. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Science.gov (United States)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  5. Reticle variation influence on manufacturing line and wafer device performance

    Science.gov (United States)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  6. Effects of indium concentration on the properties of In-doped ZnO films: Applications to silicon wafer solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Djessas, K. [Université de Perpignan Via Domitia (UPVD), Laboratoire Procédés, Matériaux et Energie Solaire (PROMES—CNRS), TECNOSUD, Rambla de la thermodynamique, 66100 Perpignan (France); Bouchama, I., E-mail: bouchama.idris@yahoo.fr [Université de Perpignan Via Domitia (UPVD), Laboratoire Procédés, Matériaux et Energie Solaire (PROMES—CNRS), TECNOSUD, Rambla de la thermodynamique, 66100 Perpignan (France); Département d' Electronique, Faculté de Technologie, Université de Msila, 28000 (Algeria); Gauffier, J.L. [Département de Physique, INSA de Toulouse, 135 Avenue de Rangueil, 31077 Toulouse Cedex 4 (France); Ayadi, Z. Ben [Laboratoire de Physique des Matériaux et des Nanomatériaux appliquée à l' Environnement (LaPhyMNE), Université de Gabès, Faculté des Sciences de Gabès, Cité Erriadh Manara Zrig, 6072 Gabès (Tunisia)

    2014-03-31

    In the present paper, high-quality In-doped ZnO (ZnO:In) thin films have been prepared by rf-magnetron sputtering on glass and p-type monocrystalline silicon substrates from an aerogel nanopowder target material. The nanoparticles with the [In]/[Zn] ratio varying between 0.01 and 0.05 were synthesized by the sol–gel method and the structural properties have been analyzed. The effect of different dopant concentrations on the electrical, optical, structural and morphological properties of the films has been investigated. The obtained ZnO:In films at room temperature are polycrystalline with a hexagonal structure and a highly preferred orientation with the c-axis perpendicular to the substrate. Scanning electron microscopy and atomic force microscopy have been applied for a morphology characterization of the films' cross-section and surface. The results revealed a typical columnar structure and very smooth surface. Films with good optical transmittance, around 85%, within the visible wavelength region, and low resistivity in the range of 10{sup −3} Ω·cm and high mobility of 4 cm{sup 2}/Vs, were produced at low substrate temperature. On the other hand, we have studied the position of the p–n junction involved in an Au/In{sub 2}O{sub 3}:SnO{sub 2}/ZnO:In(n)/c-Si(p)/Al structure by electron beam induced current. Current density–voltage characterizations in the dark and under illumination were also performed. The cell exhibits an efficiency of 6%. - Highlights: • ZnO:In thin films were prepared by rf-magnetron sputtering. • No significant changes were observed in the ZnO:In properties. • In-doped ZnO shows superior electric properties compared with pure ZnO. • Interesting photovoltaic effect observed in ITO/ZnO:In(n)/c-Si(p) heterostructure • Good quality of p–n junction in the ZnO:In(n)/c-Si(p) solar cell.

  7. Genesis of nanostructured, magnetically tunable ceramics from the pyrolysis of cross-linked polyferrocenylsilane networks and formation of shaped macroscopic objects and micron scale patterns by micromolding inside silicon wafers.

    Science.gov (United States)

    Ginzburg, Madlen; MacLachlan, Mark J; Yang, San Ming; Coombs, Neil; Coyle, Thomas W; Raju, Nandyala P; Greedan, John E; Herber, Rolfe H; Ozin, Geoffrey A; Manners, Ian

    2002-03-20

    The ability to form molded or patterned metal-containing ceramics with tunable properties is desirable for many applications. In this paper we describe the evolution of a ceramic from a metal-containing polymer in which the variation of pyrolysis conditions facilitates control of ceramic structure and composition, influencing magnetic and mechanical properties. We have found that pyrolysis under nitrogen of a well-characterized cross-linked polyferrocenylsilane network derived from the ring-opening polymerization (ROP) of a spirocyclic [1]ferrocenophane precursor gives shaped macroscopic magnetic ceramics consisting of alpha-Fe nanoparticles embedded in a SiC/C/Si(3)N(4) matrix in greater than 90% yield up to 1000 degrees C. Variation of the pyrolysis temperature and time permitted control over the nucleation and growth of alpha-Fe particles, which ranged in size from around 15 to 700 A, and the crystallization of the surrounding matrix. The ceramics contained smaller alpha-Fe particles when prepared at temperatures lower than 900 degrees C and displayed superparamagnetic behavior, whereas the materials prepared at 1000 degrees C contained larger alpha-Fe particles and were ferromagnetic. This flexibility may be useful for particular materials applications. In addition, the composition of the ceramic was altered by changing the pyrolysis atmosphere to argon, which yielded ceramics that contain Fe(3)Si(5). The ceramics have been characterized by a combination of physical techniques, including powder X-ray diffraction, TEM, reflectance UV-vis/near-IR spectroscopy, elemental analysis, XPS, SQUID magnetometry, Mössbauer spectroscopy, nanoindentation, and SEM. Micromolding of the spirocyclic [1]ferrocenophane precursor within soft lithographically patterned channels housed inside silicon wafers followed by thermal ROP and pyrolysis enabled the formation of predetermined micron scale designs of the magnetic ceramic.

  8. Polish visit

    CERN Document Server

    2003-01-01

    On 6 October, Professor Michal Kleiber, Polish Minister of Science and Chairman of the State Committee for Scientific Research, visited CERN and met both the current and designated Director General, Luciano Maiani and Robert Aymar. Professor Kleiber visited the CMS and ATLAS detector assembly halls, the underground cavern for ATLAS, and the LHC superconducting magnet string test hall. Michal Kleiber (left), Polish minister of science and Jan Krolikowski, scientist at Warsaw University and working for CMS, who shows the prototypes of the Muon Trigger board of CMS.

  9. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  10. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  11. Ellipsometry measurements of thickness of oxide and water layers on spherical and flat silicon surfaces

    International Nuclear Information System (INIS)

    Kenny, M.J.; Netterfield, R.; Wielunski, L.S.

    1998-01-01

    Full text: Ellipsometry has been used to measure the thickness of oxide layers on single crystal silicon surfaces, both flat and spherical and also to measure the extent of adsorption of moisture on the surface as a function of partial water vapour pressure. The measurements form part of an international collaborative project to make a precise determination of the Avogadro constant (ΔN A /N A -8 ) which will then be used to obtain an absolute definition of the kilogram, rather than one in terms of an artefact. Typically the native oxide layer on a cleaned silicon wafer is about 2 nm thick. On a polished sphere this oxide layer is typically 8 to 10 nm thick, the increased thickness being attributed to parameters related to the polishing process. Ellipsometry measurements on an 89 mm diameter polished silicon sphere at both VUW and CSIRO indicated a SiO 2 layer at 7 to 10 nm thick. It was observed that this thickness varied regularly. The crystal orientation of the sphere was determined using electron patterns generated from an electron microscope and the oxide layer was then measured through 180 arcs of great circles along (110) and (100) planes. It was observed that the thickness varied systematically with orientation. The minimum thickness was 7.4 nm at the axis (softest direction in silicon) and the greatest thickness was 9.5 nm at the axis (hardest direction in silicon). This is similar to an orientation dependent cubic pattern which has been observed to be superimposed on polished silicon spheres. At VUW, the sphere was placed in an evacuated bell jar and the ellipsometry signal was observed as the water vapour pressure was progressively increased up to saturation. The amount of water vapour adsorbed at saturation was one or two monolayers, indicating that the sphere does not wet

  12. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  13. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    International Nuclear Information System (INIS)

    Heib, F.; Hempelmann, R.; Munief, W.M.; Ingebrandt, S.; Fug, F.; Possart, W.; Groß, K.; Schmitt, M.

    2015-01-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ a and the receding θ r contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple line dis

  14. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    Energy Technology Data Exchange (ETDEWEB)

    Heib, F., E-mail: f.heib@mx.uni-saarland.de [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Hempelmann, R. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Munief, W.M.; Ingebrandt, S. [Department of Informatics and Microsystem Technology, University of Applied Sciences, Kaiserslautern, 66482 Zweibrücken (Germany); Fug, F.; Possart, W. [Department of Adhesion and Interphases in Polymers, Saarland University, 66123 Saarbrücken (Germany); Groß, K.; Schmitt, M. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany)

    2015-07-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ{sub a} and the receding θ{sub r} contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple

  15. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  16. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  17. Silicon Wafer X-ray Mirror

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  18. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  19. Development of low-cost silicon crystal growth techniques for terrestrial photovoltaic solar energy conversion

    Science.gov (United States)

    Zoutendyk, J. A.

    1976-01-01

    Because of the growing need for new sources of electrical energy, photovoltaic solar energy conversion is being developed. Photovoltaic devices are now being produced mainly from silicon wafers obtained from the slicing and polishing of cylindrically shaped single crystal ingots. Inherently high-cost processes now being used must either be eliminated or modified to provide low-cost crystalline silicon. Basic to this pursuit is the development of new or modified methods of crystal growth and, if necessary, crystal cutting. If silicon could be grown in a form requiring no cutting, a significant cost saving would potentially be realized. Therefore, several techniques for growth in the form of ribbons or sheets are being explored. In addition, novel techniques for low-cost ingot growth and cutting are under investigation.

  20. Solid state MEMS devices on flexible and semi-transparent silicon (100) platform

    KAUST Repository

    Ahmed, Sally; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2014-01-01

    We report fabrication of MEMS thermal actuators on flexible and semi-transparent silicon fabric released from bulk silicon (100). We fabricated the devices first and then released the top portion of the silicon (≈ 19 μm) which is flexible and semi-transparent. We also performed chemical mechanical polishing to reuse the remaining wafer. A tested thermal actuator with 3 μm wide 240 μm hot arm and 10 μm wide 185 μm long cold arm deflected by 1.7 μm at 1 V. The fabricated thermal actuators exhibit similar performance before and after bending. We believe the demonstrated process will expand the horizon of flexible electronics into MEMS world devices. © 2014 IEEE.

  1. Indium tin oxide thin-films prepared by vapor phase pyrolysis for efficient silicon based solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Simashkevich, Alexei, E-mail: alexeisimashkevich@hotmail.com [Institute of Applied Physics, 5 Academiei str., Chisinau, MD-2028, Republic of Moldova (Moldova, Republic of); Serban, Dormidont; Bruc, Leonid; Curmei, Nicolai [Institute of Applied Physics, 5 Academiei str., Chisinau, MD-2028, Republic of Moldova (Moldova, Republic of); Hinrichs, Volker [Institut für Heterogene Materialsysteme, Helmholtz-Zentrum Berlin für Materialien und Energie GmbH, Lise-Meitner Campus, Hahn-Meitner-Platz 1, 14109 Berlin (Germany); Rusu, Marin [Institute of Applied Physics, 5 Academiei str., Chisinau, MD-2028, Republic of Moldova (Moldova, Republic of); Institut für Heterogene Materialsysteme, Helmholtz-Zentrum Berlin für Materialien und Energie GmbH, Lise-Meitner Campus, Hahn-Meitner-Platz 1, 14109 Berlin (Germany)

    2016-07-01

    The vapor phase pyrolysis deposition method was developed for the preparation of indium tin oxide (ITO) thin films with thicknesses ranging between 300 and 400 nm with the sheet resistance of 10–15 Ω/sq. and the transparency in the visible region of the spectrum over 80%. The layers were deposited on the (100) surface of the n-type silicon wafers with the charge carriers concentration of ~ 10{sup 15} cm{sup −3}. The morphology of the ITO layers deposited on Si wafers with different surface morphologies, e.g., smooth (polished), rough (irregularly structured) and textured (by inversed pyramids) was investigated. The as-deposited ITO thin films consist of crystalline columns with the height of 300–400 nm and the width of 50–100 nm. Photovoltaic parameters of mono- and bifacial solar cells of Cu/ITO/SiO{sub 2}/n–n{sup +} Si/Cu prepared on Si (100) wafers with different surface structures were studied and compared. A maximum efficiency of 15.8% was achieved on monofacial solar cell devices with the textured Si surface. Bifacial photovoltaic devices from 100 μm thick Si wafers with the smooth surface have demonstrated efficiencies of 13.0% at frontal illumination and 10% at rear illumination. - Highlights: • ITO thin films prepared by vapor phase pyrolysis on Si (100) wafers with a smooth (polished), rough (irregularly structured) and textured (by inversed pyramids) surface. • Monofacial ITO/SiO2/n-n+Si solar cells with an efficiency of 15.8% prepared and bifacial PV devices with front- and rear-side efficiencies up to 13% demonstrated. • Comparative studies of photovoltaic properties of solar cells with different morphologies of the Si wafer surface presented.

  2. Ultra-thin silicon oxide layers on crystalline silicon wafers: Comparison of advanced oxidation techniques with respect to chemically abrupt SiO{sub 2}/Si interfaces with low defect densities

    Energy Technology Data Exchange (ETDEWEB)

    Stegemann, Bert, E-mail: bert.stegemann@htw-berlin.de [HTW Berlin - University of Applied Sciences, 12459 Berlin (Germany); Gad, Karim M. [University of Freiburg, Department of Microsystems Engineering - IMTEK, 79110 Freiburg (Germany); Balamou, Patrice [HTW Berlin - University of Applied Sciences, 12459 Berlin (Germany); Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany); Sixtensson, Daniel [Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany); Vössing, Daniel; Kasemann, Martin [University of Freiburg, Department of Microsystems Engineering - IMTEK, 79110 Freiburg (Germany); Angermann, Heike [Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany)

    2017-02-15

    Highlights: • Fabrication of ultrathin SiO{sub 2} tunnel layers on c-Si. • Correlation of electronic and chemical SiO{sub 2}/Si interface properties revealed by XPS/SPV. • Chemically abrupt SiO{sub 2}/Si interfaces generate less interface defect states considerable. - Abstract: Six advanced oxidation techniques were analyzed, evaluated and compared with respect to the preparation of high-quality ultra-thin oxide layers on crystalline silicon. The resulting electronic and chemical SiO{sub 2}/Si interface properties were determined by a combined x-ray photoemission (XPS) and surface photovoltage (SPV) investigation. Depending on the oxidation technique, chemically abrupt SiO{sub 2}/Si interfaces with low densities of interface states were fabricated on c-Si either at low temperatures, at short times, or in wet-chemical environment, resulting in each case in excellent interface passivation. Moreover, the beneficial effect of a subsequent forming gas annealing (FGA) step for the passivation of the SiO{sub 2}/Si interface of ultra-thin oxide layers has been proven. Chemically abrupt SiO{sub 2}/Si interfaces have been shown to generate less interface defect states.

  3. Fabrication of novel AFM probe with high-aspect-ratio ultra-sharp three-face silicon nitride tips

    NARCIS (Netherlands)

    Vermeer, Rolf; Berenschot, Johan W.; Sarajlic, Edin; Tas, Niels Roelof; Jansen, Henricus V.

    In this paper we present the wafer-scale fabrication of molded AFM probes with high aspect ratio ultra-sharp three-plane silicon nitride tips. Using $\\langle$111$\\rangle$ silicon wafers a dedicated process is developed to fabricate molds in the silicon wafer that have a flat triangular bottom

  4. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  5. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  6. The effect of baking conditions on the effective contact areas of screen-printed silver layer on silicon substrate

    Energy Technology Data Exchange (ETDEWEB)

    Tietun Sun; Jianmin Miao; Rongming Lin; Yongqing Fu [Nanyang Technological Univ., Micromachines Lab., Singapore (Singapore)

    2005-01-01

    In this paper, Ag-based paste was screen-printed on polished as well as on textured p-type (100) single crystalline silicon wafers. Three types of baking processes were studied: the tube furnace, the belt furnace and the hot plate baking. The effective contact areas of Ag/Si system were measured with a novel method, namely metal insulator semiconductor structure measurement. The results show that after baking on the hot plate at 400 deg C for 5 min, the size and number of pores in the Ag film layer as well as at the interface between silver layer and silicon decreases significantly, the effective contact area also increases about 20%, particularly on the textured silicon substrate. (Author)

  7. The effect of baking conditions on the effective contact areas of screen-printed silver layer on silicon substrate

    Energy Technology Data Exchange (ETDEWEB)

    Sun, Tietun; Miao, Jianmin; Lin, Rongming; Fu, Yongqing [Micromachines Laboratory, School of Mechanical and Production Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2005-01-01

    In this paper, Ag-based paste was screen-printed on the polished as well as on the textured p-type (100) single crystalline silicon wafers. Three types of baking processes were studied: the tube furnace, the belt furnace and the hot plate baking. The effective contact areas of Ag/Si system were measured with a novel method, namely metal insulator semiconductor structure measurement. The results show that after baking on the hot plate at 400{sup o}C for 5min, the size and number of pores in the Ag film layer as well as at the interface between silver layer and silicon decreases significantly, the effective contact area also increases about 20%, particularly on the textured silicon substrate.

  8. Seedless electroplating on patterned silicon

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2006-01-01

    Nickel thin films have been electrodeposited without the use of an additional seed layer, on highly doped silicon wafers. These substrates conduct sufficiently well to allow deposition using a peripherical electrical contact on the wafer. Films 2 μm thick have been deposited using a nickel sulfamate

  9. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    Science.gov (United States)

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  10. Development of clean chemical mechanical polishing systems; Clean CMP system

    Energy Technology Data Exchange (ETDEWEB)

    Tsujimura, M.; Hosokawa, M. [Ebara Corp., Tokyo (Japan)

    1998-10-20

    Described herein are clean chemical mechanical polishing (CMP) systems developed by Ebara. A CMP system needs advanced peripheral techniques, in addition to those for grinding adopted by the conventional system, in order to fully exhibit its inherent functions. An integrated design concept is essential for the CMP steps, including slurry supplying, polishing, washing, process controlling and waste fluid treatment. The Ebara has adopted a standard concept `Clean CMP, dry-in and dry-out of wafers,` and provided world`s highest grades of techniques for inter-layer insulating film, shallow trench isolation, plug and wiring. The head for the polishing module is specially designed by FEM, to improve homogeneity of wafers from the center to edges. The dresser is also specially designed, to improve pad surface topolody after dressing. A slurry dipsersing method is developed to reduce slurry consumption. Various washing modules, designed to have the same external shape, can be allocated to various functions. 10 figs.

  11. Transformational silicon electronics

    KAUST Repository

    Rojas, Jhonathan Prieto

    2014-02-25

    In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

  12. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  13. 450mm wafer patterning with jet and flash imprint lithography

    Science.gov (United States)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  14. Quasimetallic silicon micromachined photonic crystals

    International Nuclear Information System (INIS)

    Temelkuran, B.; Bayindir, Mehmet; Ozbay, E.; Kavanaugh, J. P.; Sigalas, M. M.; Tuttle, G.

    2001-01-01

    We report on fabrication of a layer-by-layer photonic crystal using highly doped silicon wafers processed by semiconductor micromachining techniques. The crystals, built using (100) silicon wafers, resulted in an upper stop band edge at 100 GHz. The transmission and defect characteristics of these structures were found to be analogous to metallic photonic crystals. We also investigated the effect of doping concentration on the defect characteristics. The experimental results agree well with predictions of the transfer matrix method simulations

  15. Proposed method of assembly for the BCD silicon strip vertex detector modules

    International Nuclear Information System (INIS)

    Lindenmeyer, C.

    1989-01-01

    The BCD Silicon strip Vertex Detector is constructed of 10 identical central region modules and 18 similar forward region modules. This memo describes a method of assembling these modules from individual silicon wafers. Each wafer is fitted with associated front end electronics and cables and has been tested to insure that only good wafers reach the final assembly stage. 5 figs

  16. Sol-gel derived antireflective coatings for silicon

    Energy Technology Data Exchange (ETDEWEB)

    Brinker, C J; Harrington, M S

    1981-08-01

    The preparation of TiO2-SiO2 AR coatings, containing from 30 to 95 mol % TiO2, from alkoxide precursor solutions (titanium tetraethoxide and silicon tetraethoxide) by a sol-gel process is presented. The preparation of the solutions is described, which involves the separate partial hydrolysis of one or both alkoxides prior to their mixing (Yoldas, 1980). The solutions are applied to polished, circular (1 and 2 in. diameter) silicon wafers by a spinning process. The coated wafers are successively heated in air at each of the following temperatures: 200, 300, 350, 400, and 450 C, and optical measurements are performed on them after each heat treatment. The durability of 90 and 95% TiO2 coatings is evaluated in both acidic and basic environments, and reflectivity, film thickness, and refractive index are measured as a function of exposure time. It is shown that sol-gel films applied at 400 C reveal broad regions of antireflectance compared to other titanium-based films.

  17. Increasing the efficiency of silicon heterojunction solar cells and modules by light soaking

    KAUST Repository

    Kobayashi, Eiji; De Wolf, Stefaan; Levrat, Jacques; Descoeudres, Antoine; Despeisse, Matthieu; Haug, Franz-Josef; Ballif, Christophe

    2017-01-01

    Silicon heterojunction solar cells use crystalline silicon (c-Si) wafers as optical absorbers and employ bilayers of doped/intrinsic hydrogenated amorphous silicon (a-Si:H) to form passivating contacts. Recently, we demonstrated that such solar

  18. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  19. Functional Median Polish

    KAUST Repository

    Sun, Ying; Genton, Marc G.

    2012-01-01

    polish is demonstrated by comparing its performance with the traditional functional ANOVA fitted by means under different outlier models in simulation studies. The functional median polish is illustrated on various applications in climate science

  20. Silicon hybrid integration

    International Nuclear Information System (INIS)

    Li Xianyao; Yuan Taonu; Shao Shiqian; Shi Zujun; Wang Yi; Yu Yude; Yu Jinzhong

    2011-01-01

    Recently,much attention has concentrated on silicon based photonic integrated circuits (PICs), which provide a cost-effective solution for high speed, wide bandwidth optical interconnection and optical communication.To integrate III-V compounds and germanium semiconductors on silicon substrates,at present there are two kinds of manufacturing methods, i.e., heteroepitaxy and bonding. Low-temperature wafer bonding which can overcome the high growth temperature, lattice mismatch,and incompatibility of thermal expansion coefficients during heteroepitaxy, has offered the possibility for large-scale heterogeneous integration. In this paper, several commonly used bonding methods are reviewed, and the future trends of low temperature wafer bonding envisaged. (authors)

  1. Hybrid Integrated Platforms for Silicon Photonics

    Science.gov (United States)

    Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

    2010-01-01

    A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  2. Hybrid Integrated Platforms for Silicon Photonics

    Directory of Open Access Journals (Sweden)

    John E. Bowers

    2010-03-01

    Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  3. Cancer morbidity among polishers.

    Science.gov (United States)

    Järvholm, B; Thiringer, G; Axelson, O

    1982-01-01

    The mortality pattern among 86 men was determined to investigate the possible hazards of polishing steel. The men had polished steel with polishing paste for at least five years. The polishing pastes had contained tallow, beeswax, carnauba wax, alundum, carborundum, ferric oxide, and chalk. A total of 18 men had died compared with 13.3 expected. Four had died of stomach cancer compared with 0.44 expected (p less than 0.005). The mortality for other causes of death was not increased. The study does not permit any definite conclusion but indicates a possible cancer hazard among polishers. PMID:7066237

  4. Porous Silicon Nanowires

    Science.gov (United States)

    Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

    2011-01-01

    In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

  5. Surface Passivation for Silicon Heterojunction Solar Cells

    NARCIS (Netherlands)

    Deligiannis, D.

    2017-01-01

    Silicon heterojunction solar cells (SHJ) are currently one of the most promising solar cell technologies in the world. The SHJ solar cell is based on a crystalline silicon (c-Si) wafer, passivated on both sides with a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer. Subsequently, p-type

  6. Investigation of silicon sensors quality as a function of the ohmic side processing technology

    CERN Document Server

    Bloch, P; Golubkov, S A; Golutvin, I A; Egorov, N; Konjkov, K; Kozlov, Y; Peisert, Anna; Sidorov, A; Zamiatin, N I; Cheremuhin, A E

    2002-01-01

    Silicon sensors designed for the CMS Preshower detector must have a high breakdown voltage in order to be fully efficient after a strong irradiation. Studies made by several groups left bracket 1,2,3 right bracket have underlined the importance of the p**+ side geometrical parameters, such as the metal width and the number and spacing of guard rings. We have in addition investigated the effects related to the ohmic side processing and found that the breakdown voltage depends strongly on the depth of the effective "dead" n**+ layer. By increasing this thickness from mum to 2.5mum, the fraction of sensors with breakdown voltage higher than 500V increased from 22% to more than 80%. On the other hand, it was noticed that the starting surface quality of the wafer (double side polished or single side polished) does not affect the detectors parameters for a given production technology. The thick n**+-layer protects against initial wafer surface and defects caused by the technological treatment during the detector pr...

  7. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  8. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    OpenAIRE

    Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

    2018-01-01

    A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

  9. Physical mechanisms of Cu-Cu wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  10. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  11. Liquid phase epitaxial growth of silicon on porous silicon for photovoltaic applications

    International Nuclear Information System (INIS)

    Berger, S.; Quoizola, S.; Fave, A.; Kaminski, A.; Perichon, S.; Barbier, D.; Laugier, A.

    2001-01-01

    The aim of this experiment is to grow a thin silicon layer ( 2 atmosphere, and finally LPE silicon growth with different temperature profiles in order to obtain a silicon layer on the sacrificial porous silicon (p-Si). We observed a pyramidal growth on the surface of the (100) porous silicon but the coalescence was difficult to obtain. However, on a p-Si (111) oriented wafer, homogeneous layers were obtained. (orig.)

  12. Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

    NARCIS (Netherlands)

    Haneveld, J.; Berenschot, Johan W.; Maury, P.A.; Jansen, Henricus V.

    2005-01-01

    A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7-20 nm wide, 40-100 nm high and centimeters long. All dimensions are easily

  13. Health Information in Polish (polski)

    Science.gov (United States)

    ... Tools You Are Here: Home → Multiple Languages → Polish (polski) URL of this page: https://medlineplus.gov/languages/polish.html Health Information in Polish (polski) To use the sharing features on this page, ...

  14. Silicon nanowire-based solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S [Institute of Photonic Technology, Albert-Einstein-Strasse 9, D-07745 Jena (Germany)], E-mail: thomas.stelzner@ipht-jena.de

    2008-07-23

    The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm{sup 2} open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm{sup -2} were obtained.

  15. Silicon nanowire-based solar cells

    International Nuclear Information System (INIS)

    Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S

    2008-01-01

    The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm 2 open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm -2 were obtained

  16. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  17. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

    Science.gov (United States)

    Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

    2013-11-22

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  18. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    Science.gov (United States)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  19. Polish Cartographical Review

    Directory of Open Access Journals (Sweden)

    Nedjeljko Frančula

    2017-07-01

    Full Text Available The Polish Cartographical Review (PCR journal has been published in English four times a year since 2015. The journal is in open access and it is published by De Gruyter Open. It is edited by Polish scientists in collaboration with international experts.

  20. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  1. Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

    Directory of Open Access Journals (Sweden)

    Kae Dal Kwack

    2011-01-01

    Full Text Available A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

  2. Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

    Science.gov (United States)

    Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

    2011-01-01

    A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

  3. Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

    Science.gov (United States)

    Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

    2011-01-01

    A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light. PMID:22319353

  4. Laser plasma generation of hydrogen-free diamond-like carbon thin films on Zr-2.5Nb CANDU pressure tube materials and silicon wafers with a pulsed high-power CO2 laser

    International Nuclear Information System (INIS)

    Ebrahim, N.A.; Mouris, J.F.; Hoffmann, C.R.J.; Davis, R.W.

    1995-06-01

    We report the first experiments on the laser plasma deposition of hydrogen-free, diamond-like carbon (DLC) films on Zr-2.5Nb CANDU pressure-tube materials and silicon substrates, using the short-pulse, high-power, CO 2 laser in the High-Power Laser Laboratory at Chalk River Laboratories. The films were (AFM). The thin films show the characteristic signature of DLC films in the Raman spectra obtained using a krypton-ion (Kr + ) laser. The Vickers ultra-low-load microhardness tests show hardness of the coated surface of approximately 7000 Kg force mm -2 , which is consistent with the hardness associated with DLC films. AFM examination of the film morphology shows diamond-like crystals distributed throughout the film, with film thicknesses of up to 0.5 μm generated with 50 laser pulses. With significantly more laser pulses, it is expected that very uniform diamond-like films would be produced. These experiments suggest that it should be possible to deposit hydrogen-free, diamond-like films of relevance to nuclear reactor components with a high-power and high-repetition-rate laser facility. (author). 7 refs., 2 tabs., 15 figs

  5. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  6. Polish polar research (outline

    Directory of Open Access Journals (Sweden)

    Krzysztof Ludwik Birkenmajer

    2017-12-01

    Full Text Available The article describes Polish research and discoveries in the Arctic and the Antarctic since the 19th century. The author is a geologist and since 1956 has been engaged in scientific field research on Spitsbergen, Greenland and Antarctica (23 expeditions. For many years chairman of the Committee on Polar Research of the Polish Academy of Sciences, he is now its Honorary Chairman.

  7. Silicon epitaxy on textured double layer porous silicon by LPCVD

    International Nuclear Information System (INIS)

    Cai Hong; Shen Honglie; Zhang Lei; Huang Haibin; Lu Linfeng; Tang Zhengxia; Shen Jiancang

    2010-01-01

    Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521 cm -1 have a width of 7.8 cm -1 , which reveals the high crystalline quality of the silicon epitaxy.

  8. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  9. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  10. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  11. Multiproject wafers: not just for million-dollar mask sets

    Science.gov (United States)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  12. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Xianshu eLuo

    2015-04-01

    Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

  13. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  14. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  15. Chemical polishing of partially oxidized T-111 alloy

    International Nuclear Information System (INIS)

    Teaney, P.E.

    1974-01-01

    The specimens were pressure-mounted in Bakelite and ground through 600 grit on silicon carbide papers. The specimens were rough-polished on a vibratory polisher for 4 to 6 h, using a water slurry of one micron alumina on Texmet, followed by 0.3-μ alumina on Texmet overnight. Final polishing was accomplished by continuous swabbing with a chemical polish. A chemical polish consisting of ten parts lactic acid, four parts nitric acid, and four parts hydrofluoric acid worked well for the T-111 parent material specimens; however, in the partially oxidized specimens, considerable pitting and staining occurred in the oxygen-affected zone and in the transition zone between the oxygen-affected zone and the parent material. A chemical polish was developed for the partially oxidized specimens by adjusting the ratio of the acids to ten parts lactic acid, two parts nitric acid, and two parts hydrofluoric acid. This slowed the chemical attack on the oxygen-affected zone considerably and, with continuous swabbing, the pitting and stain could be avoided. The specimens were rinsed and checked occasionally on the metallograph to determine when the proper polish had been obtained. Some specimens required intermittent polishing times up to 1 / 2 hour. No relationship could be established between the oxygen content of the specimen and the time required for chemical polishing in the partially oxidized specimens. However, the microstructure of the transition zone was the most difficult to obtain, and specimens with uniform reaction zones across the width of the specimen polished quicker than those with the transition zone

  16. Polycrystalline Silicon Gettered by Porous Silicon and Heavy Phosphorous Diffusion

    Institute of Scientific and Technical Information of China (English)

    LIU Zuming(刘祖明); Souleymane K Traore; ZHANG Zhongwen(张忠文); LUO Yi(罗毅)

    2004-01-01

    The biggest barrier for photovoltaic (PV) utilization is its high cost, so the key for scale PV utilization is to further decrease the cost of solar cells. One way to improve the efficiency, and therefore lower the cost, is to increase the minority carrier lifetime by controlling the material defects. The main defects in grain boundaries of polycrystalline silicon gettered by porous silicon and heavy phosphorous diffusion have been studied. The porous silicon was formed on the two surfaces of wafers by chemical etching. Phosphorous was then diffused into the wafers at high temperature (900℃). After the porous silicon and diffusion layers were removed, the minority carrier lifetime was measured by photo-conductor decay. The results show that the lifetime's minority carriers are increased greatly after such treatment.

  17. Reduction of absorption loss in multicrystalline silicon via combination of mechanical grooving and porous silicon

    Energy Technology Data Exchange (ETDEWEB)

    Ben Rabha, Mohamed; Mohamed, Seifeddine Belhadj; Dimassi, Wissem; Gaidi, Mounir; Ezzaouia, Hatem; Bessais, Brahim [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, Technopole de Borj-Cedria, BP 95, 2050 Hammam-Lif (Tunisia)

    2011-03-15

    Surface texturing of silicon wafer is a key step to enhance light absorption and to improve the solar cell performances. While alkaline-texturing of single crystalline silicon wafers was well established, no efficient chemical solution has been successfully developed for multicrystalline silicon wafers. Thus, the use of alternative new methods for effective texturization of multicrystalline silicon is worth to be investigated. One of the promising texturing techniques of multicrystalline silicon wafers is the use of mechanical grooves. However, most often, physical damages occur during mechanical grooves of the wafer surface, which in turn require an additional step of wet processing-removal damage. Electrochemical surface treatment seems to be an adequate solution for removing mechanical damage throughout porous silicon formation. The topography of untreated and porous silicon-treated mechanically textured surface was investigated using scanning electron microscopy (SEM). As a result of the electrochemical surface treatment, the total reflectivity drops to about 5% in the 400-1000 nm wavelength range and the effective minority carrier diffusion length enhances from 190 {mu}m to about 230 {mu}m (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  18. Near-infrared free carrier absorption in heavily doped silicon

    International Nuclear Information System (INIS)

    Baker-Finch, Simeon C.; McIntosh, Keith R.; Yan, Di; Fong, Kean Chern; Kho, Teng C.

    2014-01-01

    Free carrier absorption in heavily doped silicon can have a significant impact on devices operating in the infrared. In the near infrared, the free carrier absorption process can compete with band to band absorption processes, thereby reducing the number of available photons to optoelectronic devices such as solar cells. In this work, we fabricate 18 heavily doped regions by phosphorus and boron diffusion into planar polished silicon wafers; the simple sample structure facilitates accurate and precise measurement of the free carrier absorptance. We measure and model reflectance and transmittance dispersion to arrive at a parameterisation for the free carrier absorption coefficient that applies in the wavelength range between 1000 and 1500 nm, and the range of dopant densities between ∼10 18 and 3 × 10 20  cm −3 . Our measurements indicate that previously published parameterisations underestimate the free carrier absorptance in phosphorus diffusions. On the other hand, published parameterisations are generally consistent with our measurements and model for boron diffusions. Our new model is the first to be assigned uncertainty and is well-suited to routine device analysis

  19. Mechanistic, kinetic, and processing aspects of tungsten chemical mechanical polishing

    Science.gov (United States)

    Stein, David

    This dissertation presents an investigation into tungsten chemical mechanical polishing (CMP). CMP is the industrially predominant unit operation that removes excess tungsten after non-selective chemical vapor deposition (CVD) during sub-micron integrated circuit (IC) manufacture. This work explores the CMP process from process engineering and fundamental mechanistic perspectives. The process engineering study optimized an existing CMP process to address issues of polish pad and wafer carrier life. Polish rates, post-CMP metrology of patterned wafers, electrical test data, and synergy with a thermal endpoint technique were used to determine the optimal process. The oxidation rate of tungsten during CMP is significantly lower than the removal rate under identical conditions. Tungsten polished without inhibition during cathodic potentiostatic control. Hertzian indenter model calculations preclude colloids of the size used in tungsten CMP slurries from indenting the tungsten surface. AFM surface topography maps and TEM images of post-CMP tungsten do not show evidence of plow marks or intergranular fracture. Polish rate is dependent on potassium iodate concentration; process temperature is not. The colloid species significantly affects the polish rate and process temperature. Process temperature is not a predictor of polish rate. A process energy balance indicates that the process temperature is predominantly due to shaft work, and that any heat of reaction evolved during the CMP process is negligible. Friction and adhesion between alumina and tungsten were studied using modified AFM techniques. Friction was constant with potassium iodate concentration, but varied with applied pressure. This corroborates the results from the energy balance. Adhesion between the alumina and the tungsten was proportional to the potassium iodate concentration. A heuristic mechanism, which captures the relationship between polish rate, pressure, velocity, and slurry chemistry, is presented

  20. Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

    Science.gov (United States)

    Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

    2017-09-01

    The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

  1. Functional Median Polish

    KAUST Repository

    Sun, Ying

    2012-08-03

    This article proposes functional median polish, an extension of univariate median polish, for one-way and two-way functional analysis of variance (ANOVA). The functional median polish estimates the functional grand effect and functional main factor effects based on functional medians in an additive functional ANOVA model assuming no interaction among factors. A functional rank test is used to assess whether the functional main factor effects are significant. The robustness of the functional median polish is demonstrated by comparing its performance with the traditional functional ANOVA fitted by means under different outlier models in simulation studies. The functional median polish is illustrated on various applications in climate science, including one-way and two-way ANOVA when functional data are either curves or images. Specifically, Canadian temperature data, U. S. precipitation observations and outputs of global and regional climate models are considered, which can facilitate the research on the close link between local climate and the occurrence or severity of some diseases and other threats to human health. © 2012 International Biometric Society.

  2. I-line stepper based overlay evaluation method for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  3. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  4. Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

    NARCIS (Netherlands)

    Popovich, V.A.

    2013-01-01

    Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

  5. Silicon Nanowire Fabrication Using Edge and Corner Lithography

    NARCIS (Netherlands)

    Yagubizade, H.; Berenschot, Johan W.; Jansen, Henricus V.; Elwenspoek, Michael Curt; Tas, Niels Roelof

    2010-01-01

    This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features

  6. 1366 Project Silicon: Reclaiming US Silicon PV Leadership

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2016-02-16

    1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

  7. Morphological and optical properties of n-type porous silicon

    Indian Academy of Sciences (India)

    type silicon wafer have been reported in the present article. Method of PS fabrication is by photo-assisted electrochemical etching with different etching current densities ( J ). Porosity and PS layer thickness, obtained by the gravimetric method, ...

  8. Fe-N{sub x}/C assisted chemical–mechanical polishing for improving the removal rate of sapphire

    Energy Technology Data Exchange (ETDEWEB)

    Xu, Li, E-mail: xl0522@126.com [State Key Laboratory of Tribology, Tsinghua University, Beijing 100084 (China); Shenzhen Key Laboratory of Micro/Nano Manufacturing, Research Institute of Tsinghua University in Shenzhen, Shenzhen 518057 (China); Zou, Chunli; Shi, Xiaolei [State Key Laboratory of Tribology, Tsinghua University, Beijing 100084 (China); Shenzhen Key Laboratory of Micro/Nano Manufacturing, Research Institute of Tsinghua University in Shenzhen, Shenzhen 518057 (China); Pan, Guoshun, E-mail: pangs@tsinghua.edu.cn [State Key Laboratory of Tribology, Tsinghua University, Beijing 100084 (China); Shenzhen Key Laboratory of Micro/Nano Manufacturing, Research Institute of Tsinghua University in Shenzhen, Shenzhen 518057 (China); Luo, Guihai; Zhou, Yan [State Key Laboratory of Tribology, Tsinghua University, Beijing 100084 (China); Shenzhen Key Laboratory of Micro/Nano Manufacturing, Research Institute of Tsinghua University in Shenzhen, Shenzhen 518057 (China)

    2015-07-15

    Highlights: • A novel non-noble metal catalyst (Fe-N{sub x}/C) was prepared. • Fe-N{sub x}/C shows remarkable catalytic activity for improving the removal rate of sapphire in alkaline solution. • The optimum CMP removal by Fe-N{sub x}/C yielded a superior surface finish of 0.078 nm the average roughness. • Fe{sub 2}O{sub 3}, Fe{sub 3}O{sub 4}, pyridinic N as well as pyrrolic N group possibly serving as the catalytic sites. • A soft hydration layer (boehmite, AlO(OH)) was generated on the surface of sapphire during CMP process. - Abstract: In this paper, a novel non-noble metal catalyst (Fe-N{sub x}/C) is used to improve the removal mass of sapphire as well as obtain atomically smooth sapphire wafer surfaces. The results indicate that Fe-N{sub x}/C shows good catalytic activity towards sapphire removal rate. And the material removal rates (MRRs) are found to vary with the catalyst content in the polishing fluid. Especially that when the polishing slurry mixes with 16 ppm Fe-N{sub x}/C shows the maximum MRR and its removal mass of sapphire is 38.43 nm/min, more than 15.44% larger than traditional CMP using the colloidal silicon dioxide (SiO{sub 2}) without Fe-N{sub x}/C. Catalyst-assisted chemical–mechanical polishing of sapphire is studied with X-ray photoelectron spectroscopy (XPS). It is found that the formation of a soft hydration layer (boehmite, γ-AlOOH or γ-AlO(OH)) on sapphire surface facilitates the material removal and achieving fine surface finish on basal plane. Abrasives (colloid silica together with magnetite, ingredient of Fe-N{sub x}/C) with a hardness between boehmite and sapphire polish the c-plane of sapphire with good surface finish and efficient removal. Fe{sub 2}O{sub 3}, Fe{sub 3}O{sub 4}, pyridinic N as well as pyrrolic N group would be the catalytical active sites and accelerate this process. Surface quality is characterized with atomic force microscopy (AFM). The optimum CMP removal by Fe-N{sub x}/C also yields a superior

  9. Use of porous silicon to minimize oxidation induced stacking fault defects in silicon

    International Nuclear Information System (INIS)

    Shieh, S.Y.; Evans, J.W.

    1992-01-01

    This paper presents methods for minimizing stacking fault defects, generated during oxidation of silicon, include damaging the back of the wafer or depositing poly-silicon on the back. In either case a highly defective structure is created and this is capable of gettering either self-interstitials or impurities which promote nucleation of stacking fault defects. A novel method of minimizing these defects is to form a patch of porous silicon on the back of the wafer by electrochemical etching. Annealing under inert gas prior to oxidation may then result in the necessary gettering. Experiments were carried out in which wafers were subjected to this treatment. Subsequent to oxidation, the wafers were etched to remove oxide and reveal defects. The regions of the wafer adjacent to the porous silicon patch were defect-free, whereas remote regions had defects. Deep level transient spectroscopy has been used to examine the gettering capability of porous silicon, and the paper discusses the mechanism by which the porous silicon getters

  10. Fabrication of heterojunction solar cells by using microcrystalline hydrogenated silicon oxide film as an emitter

    International Nuclear Information System (INIS)

    Banerjee, Chandan; Sritharathikhun, Jaran; Konagai, Makoto; Yamada, Akira

    2008-01-01

    Wide gap, highly conducting n-type hydrogenated microcrystalline silicon oxide (μc-SiO : H) films were prepared by very high frequency plasma enhanced chemical vapour deposition at a very low substrate temperature (170 deg. C) as an alternative to amorphous silicon (a-Si : H) for use as an emitter layer of heterojunction solar cells. The optoelectronic properties of n-μc-SiO : H films prepared for the emitter layer are dark conductivity = 0.51 S cm -1 at 20 nm thin film, activation energy = 23 meV and E 04 = 2.3 eV. Czochralski-grown 380 μm thick p-type (1 0 0) oriented polished silicon wafers with a resistivity of 1-10 Ω cm were used for the fabrication of heterojunction solar cells. Photovoltaic parameters of the device were found to be V oc = 620 mV, J sc = 32.1 mA cm -2 , FF = 0.77, η = 15.32% (active area efficiency)

  11. Fabrication of a silicon oxide stamp by edge lithography reinforced with silicon nitride for nanoimprint lithography

    NARCIS (Netherlands)

    Zhao, Yiping; Berenschot, Johan W.; de Boer, M.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

    2008-01-01

    The fabrication of a stamp reinforced with silicon nitride is presented for its use in nanoimprint lithography. The fabrication process is based on edge lithography using conventional optical lithography and wet anisotropic etching of 110 silicon wafers. SiO2 nano-ridges of 20 nm in width were

  12. Polish Higher Education: Intersectoral Distinctiveness

    Science.gov (United States)

    Musial, Joanna

    2014-01-01

    This study analyzes degrees of differences between the private and public sectors of Polish higher education. It finds them to be strong: Polish private institutions function very differently from Polish public institutions and these differences correspond with those found in the literature on higher education elsewhere in the world. Polish…

  13. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  14. Single crystalline silicon solar cells with rib structure

    Directory of Open Access Journals (Sweden)

    Shuhei Yoshiba

    2017-02-01

    Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  15. Single wafer rapid thermal multiprocessing

    International Nuclear Information System (INIS)

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  16. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  17. Influence of the Molecular Adhesion Force on the Indentation Depth of a Particle into the Wafer Surface in the CMP Process

    Directory of Open Access Journals (Sweden)

    Zhou Jianhua

    2014-01-01

    Full Text Available By theoretical calculation, the external force on the particle conveyed by pad asperities and the molecular adhesion force between particle and wafer are compared and analyzed quantitatively. It is confirmed that the molecular adhesion force between particle and wafer has a great influence on the chemical mechanical polishing (CMP material removal process. Considering the molecular adhesion force between particle and wafer, a more precise model for the indentation of a particle into the wafer surface is developed in this paper, and the new model is compared with the former model which neglected the molecular adhesion force. Through theoretical analyses, an approach and corresponding critical values are applied to estimate whether the molecular adhesion force in CMP can be neglected. These methods can improve the precision of the material removal model of CMP.

  18. Study of irradiation induced defects in silicon

    International Nuclear Information System (INIS)

    Pal, Gayatri; Sebastian, K.C.; Somayajulu, D.R.S.; Chintalapudi, S.N.

    2000-01-01

    Pure high resistivity (6000 ohm-cm) silicon wafers were recoil implanted with 1.8 MeV 111 In ions. As-irradiated wafers showed a 13 MHz quadrupole interaction frequency, which was not observed earlier. The annealing behaviour of these defects in the implanted wafers was studied between room temperature and 1073 K. At different annealing temperatures two more interaction frequencies corresponding to defect complexes D2 and D3 are observed. Even though the experimental conditions were different, these are identical to the earlier reported ones. Based on an empirical point charge model calculation, an attempt is made to identify the configuration of these defect complexes. (author)

  19. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  20. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  1. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    Administrator

    post-fabrication wet-chemical etching in phosphoric acid. A MEFOUED1,2,*, M FATHI1, ... and RCA decontamination stages by putting them in a bath made of ... found to be decreasing after chemical attack as shown in figure 2. In order to ...

  2. Wafer Cakes of Improved Amino Acid Structure

    Directory of Open Access Journals (Sweden)

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  3. On the design and implementation of a wafer yield editor

    NARCIS (Netherlands)

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  4. Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

    Science.gov (United States)

    Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

    2017-06-01

    In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

  5. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  6. Effect finishing and polishing procedures on the surface roughness of IPS Empress 2 ceramic.

    Science.gov (United States)

    Boaventura, Juliana Maria Capelozza; Nishida, Rodrigo; Elossais, André Afif; Lima, Darlon Martins; Reis, José Mauricio Santos Nunes; Campos, Edson Alves; de Andrade, Marcelo Ferrarezi

    2013-01-01

    To evaluate the surface roughness of IPS Empress 2 ceramic when treated with different finishing/polishing protocols. Sixteen specimens of IPS Empress 2 ceramic were made from wax patterns obtained using a stainless steel split mold. The specimens were glazed (Stage 0-S0, control) and divided into two groups. The specimens in Group 1 (G1) were finished/polished with a KG Sorensen diamond point (S1), followed by KG Sorensen siliconized points (S2) and final polishing with diamond polish paste (S3). In Group 2 (G2), the specimens were finished/polished using a Shofu diamond point (S1), as well as Shofu siliconized points (S2) and final polishing was performed using Porcelize paste (S3). After glazing (S0) and following each polishing procedure (S1, S2 or S3), the surface roughness was measured using TALYSURF Series 2. The average surface roughness results were analyzed using ANOVA followed by Tukey post-hoc tests (α = 0.01) RESULTS: All of the polishing procedures yielded higher surface roughness values when compared to the control group (S0). S3 yielded lower surface roughness values when compared to S1 and S2. The proposed treatments negatively affected the surface roughness of the glazed IPS Empress 2 ceramic.

  7. Effect of alkaline slurry on the electric character of the pattern Cu wafer

    International Nuclear Information System (INIS)

    Hu Yi; Liu Yuling; Liu Xiaoyan; He Yangang; Wang Liran; Zhang Baoguo

    2011-01-01

    For process integration considerations, we will investigate the impact of chemical mechanical polishing (CMP) on the electrical characteristics of the pattern Cu wafer. In this paper, we investigate the impacts of the CMP process with two kinds of slurry, one of which is acid slurry of SVTC and the other is FA/O alkaline slurry purchased from Tianjin Jingling Microelectronic Material Limited. Three aspects were investigated: resistance, capacitance and leakage current. The result shows that after polishing by the slurry of FA/O, the resistance is lower than the SVTC. After polishing by the acid slurry and FA/O alkaline slurry, the difference in capacitance is not very large. The values are 0.1 nF and 0.12 nF, respectively. The leakage current of the film polished by the slurry of FA/O is 0.01 nA, which is lower than the slurry of SVTC. The results show that the slurry of FA/O produced less dishing and oxide loss than the slurry of SVTC. (semiconductor technology)

  8. Compton recoil electron tracking with silicon strip detectors

    International Nuclear Information System (INIS)

    O'Neill, T.J.; Ait-Ouamer, F.; Schwartz, I.; Tumer, O.T.; White, R.S.; Zych, A.D.

    1992-01-01

    The application of silicon strip detectors to Compton gamma ray astronomy telescopes is described in this paper. The Silicon Compton Recoil Telescope (SCRT) tracks Compton recoil electrons in silicon strip converters to provide a unique direction for Compton scattered gamma rays above 1 MeV. With strip detectors of modest positional and energy resolutions of 1 mm FWHM and 3% at 662 keV, respectively, 'true imaging' can be achieved to provide an order of magnitude improvement in sensitivity to 1.6 x 10 - 6 γ/cm 2 -s at 2 MeV. The results of extensive Monte Carlo calculations of recoil electrons traversing multiple layers of 200 micron silicon wafers are presented. Multiple Coulomb scattering of the recoil electron in the silicon wafer of the Compton interaction and the next adjacent wafer is the basic limitation to determining the electron's initial direction

  9. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  10. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  11. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  12. Polish Semantic Parser

    Directory of Open Access Journals (Sweden)

    Agnieszka Grudzinska

    2000-01-01

    Full Text Available Amount of information transferred by computers grows very rapidly thus outgrowing the average man's capability of reception. It implies computer programs increase in the demand for which would be able to perform an introductory classitication or even selection of information directed to a particular receiver. Due to the complexity of the problem, we restricted it to understanding short newspaper notes. Among many conceptions formulated so far, the conceptual dependency worked out by Roger Schank has been chosen. It is a formal language of description of the semantics of pronouncement integrated with a text understanding algorithm. Substantial part of each text transformation system is a semantic parser of the Polish language. It is a module, which as the first and the only one has an access to the text in the Polish language. lt plays the role of an element, which finds relations between words of the Polish language and the formal registration. It translates sentences written in the language used by people into the language theory. The presented structure of knowledge units and the shape of understanding process algorithms are universal by virtue of the theory. On the other hand the defined knowledge units and the rules used in the algorithms ure only examples because they are constructed in order to understand short newspaper notes.

  13. Flexible Thermoelectric Generators on Silicon Fabric

    KAUST Repository

    Sevilla, Galo T.

    2012-11-01

    In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

  14. neutron transmutation doping of silicon a thesis submitted to nuclear engineering department for the degree of master of science in nuclear engineering

    International Nuclear Information System (INIS)

    Abdel Gawwad, M.M.

    2003-01-01

    When silicon is irradiated by thermal neutrons the objective is to produce a number of phosphorus atoms in the target sample, in order to obtain a given resistivity after treatment. The resistivity of the sample is decreased by the transmutation of the silicon (by neutrons) to phosphorus. After the sample irradiation and decay, the radiochemical cleaning is used to clean the sample. the next step is the sample heat treatment to remove the damage caused by fast neutrons( E> 0.1 MeV). after that, the sample is cut int wafer and polished. The characterization must be carried. out to characterize the specifications of the final product. the present work aims to: find an optimization of the silicon doping processes:sample preparation, for irradiation by cleaning the sample before irradiation to avoid impurity activation. process, by calculating the fluence required to reach the required resistivity. Decay of irradiated sample, it takes four days at least to be handled. handling, it must be carefully to avoid the mechanical damage since the silicon is hard material. etching , to remove the defected layer from the sample . heat treatment , to release the damage caused during irradiation. characterization, to measure the final resistivity and the minority carrier life . hence, calculating the irradiation constant for ETRR-2

  15. Low temperature spalling of silicon: A crack propagation study

    Energy Technology Data Exchange (ETDEWEB)

    Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

    2017-06-08

    Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.

  16. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  17. 120 mm Single-crystalline perovskite and wafers: towards viable applications

    Institute of Scientific and Technical Information of China (English)

    Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

    2017-01-01

    As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75% RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

  18. Porous silicon carbide (SIC) semiconductor device

    Science.gov (United States)

    Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

    1996-01-01

    Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

  19. The way to zeros: The future of semiconductor device and chemical mechanical polishing technologies

    Science.gov (United States)

    Tsujimura, Manabu

    2016-06-01

    For the last 60 years, the development of cutting-edge semiconductor devices has strongly emphasized scaling; the effort to scale down current CMOS devices may well achieve the target of 5 nm nodes by 2020. Planarization by chemical mechanical polishing (CMP), is one technology essential for supporting scaling. This paper summarizes the history of CMP transitions in the planarization process as well as the changing degree of planarity required, and, finally, introduces innovative technologies to meet the requirements. The use of CMP was triggered by the replacement of local oxidation of silicon (LOCOS) as the element isolation technology by shallow trench isolation (STI) in the 1980s. Then, CMP’s use expanded to improving embedability of aluminum wiring, tungsten (W) contacts, Cu wiring, and, more recently, to its adoption in high-k metal gate (HKMG) and FinFET (FF) processes. Initially, the required degree of planarity was 50 nm, but now 0 nm is required. Further, zero defects on a post-CMP wafer is now the goal, and it is possible that zero psi CMP loading pressure will be required going forward. Soon, it seems, everything will have to be “zero” and perfect. Although the process is also chemical in nature, the CMP process is actually mechanical with a load added using slurry particles several tens of nm in diameter. Zero load in the loading process, zero nm planarity with no trace of processing, and zero residual foreign material, including the very slurry particles used in the process, are all required. This article will provide an overview of how to achieve these new requirements and what technologies should be employed.

  20. Floating Silicon Method

    Energy Technology Data Exchange (ETDEWEB)

    Kellerman, Peter

    2013-12-21

    The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

  1. Hydrogen-induced structural changes in polycrystalline silicon as revealed by positron lifetime spectroscopy

    International Nuclear Information System (INIS)

    Arole, V.M.; Takwale, M.G.; Bhide, V.G.

    1989-01-01

    Hydrogen passivation of polycrystalline silicon wafer is carried out in order to reduce the deleterious effects of grain boundaries. A systematic variation is made in the process parameters implemented during hydrogen passivation and the results of room temperature resistivity measurements are reported. As an efficient tool to study the structure change, positron lifetime spectroscopic measurements are performed on original and hydrogenated polycrystalline silicon wafers and a systematic correlation is sought between the changes that take place in the electrical and structural properties of polycrystalline silicon wafer, brought about by hydrogen passivation. (author)

  2. Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

    Directory of Open Access Journals (Sweden)

    Liu Haijun

    2015-12-01

    Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

  3. Silicon-micromachined microchannel plates

    CERN Document Server

    Beetz, C P; Steinbeck, J; Lemieux, B; Winn, D R

    2000-01-01

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of approx 0.5 to approx 25 mu m, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposite...

  4. Polishing and toothbrushing alters the surface roughness and gloss of composite resins.

    Science.gov (United States)

    Kamonkhantikul, Krid; Arksornnukit, Mansuang; Takahashi, Hidekazu; Kanehira, Masafumi; Finger, Werner J

    2014-01-01

    This study aimed to investigate the surface roughness and gloss of composite resins after using two polishing systems and toothbrushing. Six composite resins (Durafill VS, Filtek Z250, Filtek Z350 XT, Kalore, Venus Diamond, and Venus Pearl) were evaluated after polishing with two polishing systems (Sof-Lex, Venus Supra) and after toothbrushing up to 40,000 cycles. Surface roughness (Ra) and gloss were determined for each composite resin group (n=6) after silicon carbide paper grinding, polishing, and toothbrushing. Two-way ANOVA indicated significant differences in both Ra and gloss between measuring stages for the composite resins tested, except Venus Pearl, which showed significant differences only in gloss. After polishing, the Filtek Z350 XT, Kalore, and Venus Diamond showed significant increases in Ra, while all composite resin groups except the Filtek Z350 XT and Durafill VS with Sof-Lex showed increases in gloss. After toothbrushing, all composite resin demonstrated increases in Ra and decreases in gloss.

  5. Surface Passivation and Antireflection Behavior of ALD on n-Type Silicon for Solar Cells

    Directory of Open Access Journals (Sweden)

    Ing-Song Yu

    2013-01-01

    Full Text Available Atomic layer deposition, a method of excellent step coverage and conformal deposition, was used to deposit TiO2 thin films for the surface passivation and antireflection coating of silicon solar cells. TiO2 thin films deposited at different temperatures (200°C, 300°C, 400°C, and 500°C on FZ n-type silicon wafers are in the thickness of 66.4 nm ± 1.1 nm and in the form of self-limiting growth. For the properties of surface passivation, Si surface is effectively passivated by the 200°C deposition TiO2 thin film. Its effective minority carrier lifetime, measured by the photoconductance decay method, is improved 133% at the injection level of  cm−3. Depending on different deposition parameters and annealing processes, we can control the crystallinity of TiO2 and find low-temperature TiO2 phase (anatase better passivation performance than the high-temperature one (rutile, which is consistent with the results of work function measured by Kelvin probe. In addition, TiO2 thin films on polished Si wafer serve as good ARC layers with refractive index between 2.13 and 2.44 at 632.8 nm. Weighted average reflectance at AM1.5G reduces more than half after the deposition of TiO2. Finally, surface passivation and antireflection properties of TiO2 are stable after the cofire process of conventional crystalline Si solar cells.

  6. A metallic buried interconnect process for through-wafer interconnection

    International Nuclear Information System (INIS)

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G

    2008-01-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated

  7. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  8. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Science.gov (United States)

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  9. The impact of silicon feedstock on the PV module cost

    NARCIS (Netherlands)

    del Coso, G.; del Cañizo, C.; Sinke, W.C.

    2010-01-01

    The impact of the use of new (solar grade) silicon feedstock materials on the manufacturing cost of wafer-based crystalline silicon photovoltaic modules is analyzed considering effects of material cost, efficiency of utilisation, and quality. Calculations based on data provided by European industry

  10. A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

    Energy Technology Data Exchange (ETDEWEB)

    Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

    2016-12-15

    In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  11. The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

    International Nuclear Information System (INIS)

    Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

    2004-01-01

    We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

  12. Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

    Science.gov (United States)

    Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

    2018-01-01

    Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

  13. Silicon microphotonic waveguides

    International Nuclear Information System (INIS)

    Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

    2004-01-01

    Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

  14. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  15. [Lysenkoism in Polish botany].

    Science.gov (United States)

    Köhler, Piotr

    2008-01-01

    Lysenkoism in Poland was never an autonomous phenomenon. The whole array of reasons for which it appeared in Polish science would require a separate study--here it only needs to be pointed out that the major reasons included terror on the part of the security service, lawlessness, the ubiquitous atmosphere of intimidation and terror, censorship, the diminishing sphere of civil liberties, political show trials, propaganda and denunciations. An important role in facilitating the introduction of Lysenkoism was played also by the reorganization of science after World War Two, the isolation of Polish science from science in the West, as well as the damage it had suffered during the war. At first, Lysenkoism was promoted in Poland by a small group of enthusiastic and uncritical proponents. A overview of the events connected with the ten years of Lysenkoism in Poland (end of 1948--beginning of 1958) shows a two-tier picture of how the 'idea' was propagated. The first tier consisted in the activities of the Association of Marxist Naturalists [Koło Przyrodników-Marksistów], which it engaged in since the end of 1948. The Association was later transformed into a Union of Marxist Naturalists, and this in turn merged, in 1952, with the Copernican Society of Polish Naturalists [Polskie Towarzystwo Przyrodników im. Kopernika]. It was that society which promoted Lysenkoism longest, until the end of 1956. The propaganda and training activities of the circle and the society prepared ground for analogous activities of the newly formed Polish Academy of Science (PAN), which--since its very establishment in 1952--engaged in promoting Lysenkoism through its Second Division. These activities were aimed at naturalists, initially at those who were prominent scientists (eg. the conference at Kuźnice, 1950/1951), and then at those who were only starting their academic career (including national courses in new biology at Dziwnów, 1952, or Kortowo, 1953 and 1955). The end to promoting

  16. Polish Americans. Second, Revised Edition.

    Science.gov (United States)

    Lopata, Helen Znaniecka

    This book examines Polonia, the Polish ethnic community in America created by three giant waves of immigration between 1880 and 1990. The complicated history of this ethnic group is reflected in the lives of increasing numbers of Polish Americans, including recent immigrants brought by political and economic changes, as they achieve middle class…

  17. Study on structural properties of epitaxial silicon films on annealed double layer porous silicon

    International Nuclear Information System (INIS)

    Yue Zhihao; Shen Honglie; Cai Hong; Lv Hongjie; Liu Bin

    2012-01-01

    In this paper, epitaxial silicon films were grown on annealed double layer porous silicon by LPCVD. The evolvement of the double layer porous silicon before and after thermal annealing was investigated by scanning electron microscope. X-ray diffraction and Raman spectroscopy were used to investigate the structural properties of the epitaxial silicon thin films grown at different temperature and different pressure. The results show that the surface of the low-porosity layer becomes smooth and there are just few silicon-bridges connecting the porous layer and the substrate wafer. The qualities of the epitaxial silicon thin films become better along with increasing deposition temperature. All of the Raman peaks of silicon films with different deposition pressure are situated at 521 cm -1 under the deposition temperature of 1100 °C, and the Raman intensity of the silicon film deposited at 100 Pa is much closer to that of the monocrystalline silicon wafer. The epitaxial silicon films are all (4 0 0)-oriented and (4 0 0) peak of silicon film deposited at 100 Pa is more symmetric.

  18. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    International Nuclear Information System (INIS)

    Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

    2014-01-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  20. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  1. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  2. Wafer plane inspection for advanced reticle defects

    Science.gov (United States)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  3. Noncontact sheet resistance measurement technique for wafer inspection

    Science.gov (United States)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  4. Covalent biofunctionalization of silicon nitride surfaces

    NARCIS (Netherlands)

    Arafat, A.; Giesbers, M.; Rosso, M.; Sudhölter, E.J.R.; Schroën, C.G.P.H.; White, R.G.; Li Yang,; Linford, M.R.; Zuilhof, H.

    2007-01-01

    Covalently attached organic monolayers on etched silicon nitride (SixN4; x 3) surfaces were prepared by reaction of SixN4-coated wafers with neat or solutions of 1-alkenes and 1-alkynes in refluxing mesitylene. The surface modification was monitored by measurement of the static water contact angle,

  5. Micromachining of buried micro channels in silicon

    NARCIS (Netherlands)

    de Boer, Meint J.; Tjerkstra, R.W.; Berenschot, Johan W.; Jansen, Henricus V.; Burger, G.J.; Burger, G.J.; Gardeniers, Johannes G.E.; Elwenspoek, Michael Curt; van den Berg, Albert

    A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the

  6. Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

    Science.gov (United States)

    Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

    Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

  7. Ion beam figuring of silicon aspheres

    Science.gov (United States)

    Demmler, Marcel; Zeuner, Michael; Luca, Alfonz; Dunger, Thoralf; Rost, Dirk; Kiontke, Sven; Krüger, Marcus

    2011-03-01

    Silicon lenses are widely used for infrared applications. Especially for portable devices the size and weight of the optical system are very important factors. The use of aspherical silicon lenses instead of spherical silicon lenses results in a significant reduction of weight and size. The manufacture of silicon lenses is more challenging than the manufacture of standard glass lenses. Typically conventional methods like diamond turning, grinding and polishing are used. However, due to the high hardness of silicon, diamond turning is very difficult and requires a lot of experience. To achieve surfaces of a high quality a polishing step is mandatory within the manufacturing process. Nevertheless, the required surface form accuracy cannot be achieved through the use of conventional polishing methods because of the unpredictable behavior of the polishing tools, which leads to an unstable removal rate. To overcome these disadvantages a method called Ion Beam Figuring can be used to manufacture silicon lenses with high surface form accuracies. The general advantage of the Ion Beam Figuring technology is a contactless polishing process without any aging effects of the tool. Due to this an excellent stability of the removal rate without any mechanical surface damage is achieved. The related physical process - called sputtering - can be applied to any material and is therefore also applicable to materials of high hardness like Silicon (SiC, WC). The process is realized through the commercially available ion beam figuring system IonScan 3D. During the process, the substrate is moved in front of a focused broad ion beam. The local milling rate is controlled via a modulated velocity profile, which is calculated specifically for each surface topology in order to mill the material at the associated positions to the target geometry. The authors will present aspherical silicon lenses with very high surface form accuracies compared to conventionally manufactured lenses.

  8. Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

    Energy Technology Data Exchange (ETDEWEB)

    Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

    1997-11-30

    This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

  9. Electroless porous silicon formation applied to fabrication of boron-silica-glass cantilevers

    DEFF Research Database (Denmark)

    Teva, Jordi; Davis, Zachary James; Hansen, Ole

    2010-01-01

    This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5-1 mm3) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases...... where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing...... for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH...

  10. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2013-01-01

    (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

  11. Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

    Science.gov (United States)

    Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

    2018-05-01

    An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

  12. Roadmap for integration of InP based photonics and silicon electronics

    NARCIS (Netherlands)

    Williams, K.A.

    2015-01-01

    We identify the synergies and a roadmap for the intimate integration of InP photonic integrated circuits and Silicon electronic ICs using wafer-scale processes. Advantages are foreseen in terms of bandwidth, energy savings and package simplification.

  13. Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

    International Nuclear Information System (INIS)

    Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

    2004-01-01

    Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

  14. Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

    Institute of Scientific and Technical Information of China (English)

    潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

    2011-01-01

    Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95% active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

  15. Models of nanoparticles movement, collision, and friction in chemical mechanical polishing (CMP)

    Energy Technology Data Exchange (ETDEWEB)

    Ilie, Filip, E-mail: filip@meca.omtr.pub.ro [Polytechnic University of Bucharest, Department of Machine Elements and Tribology (Romania)

    2012-03-15

    Nanoparticles have been widely used in polishing slurry such as chemical mechanical polishing (CMP) process. The movement of nanoparticles in polishing slurry and the interaction between nanoparticles and solid surface are very important to obtain an atomic smooth surface in CMP process. Polishing slurry contains abrasive nanoparticles (with the size range of about 10-100 nm) and chemical reagents. Abrasive nanoparticles and hydrodynamic pressure are considered to cause the polishing effect. Nanoparticles behavior in the slurry with power-law viscosity shows great effect on the wafer surface in polishing process. CMP is now a standard process of integrated circuit manufacturing at nanoscale. Various models can dynamically predict the evolution of surface topography for any time point during CMP. To research, using a combination of individual nanoscale friction measurements for CMP of SiO{sub 2}, in an analytical model, to sum these effects, and the results scale CMP experiments, can guide the research and validate the model. CMP endpoint measurements, such as those from motor current traces, enable verification of model predictions, relating to friction and wear in CMP and surface topography evolution for different types of CMP processes and patterned chips. In this article, we explore models of the microscopic frictional force based on the surface topography and present both experimental and theoretical studies on the movement of nanoparticles in polishing slurry and collision between nanoparticles, as well as between the particles and solid surfaces in time of process CMP. Experimental results have proved that the nanoparticle size and slurry properties have great effects on the polishing results. The effects of the nanoparticle size and the slurry film thickness are also discussed.

  16. Polishing large NaCl windows on a continuous polisher

    International Nuclear Information System (INIS)

    Williamson, R.

    1979-01-01

    The Helios and Antares CO 2 fusion laser systems incorporate numerous large sodium chloride windows. These must be refinished periodically, making necessary a consistent and predictable polishing capability. A continuous polisher (or annular lap) which might at Kirtland's Developmental Optical Facility. Large NaCl windows had not been polished on this type of machine. The machine has proven itself capable of producing lambda/16 figures at 633 nm (HeNe) with extremely smooth surfaces on glass. Since then, we have been working exclusively on NaCl optics. Due to different polishing parameters between NaCl and glass, and the slight solubility of the pitch in the slurry, this phase presents new problems. The work on glass will be reviewed. Results on NaCl to date will be reported. The potential of this type of machine relative to prisms, thin and irregularly shaped optics will be discussed

  17. Nanostructured silicon ferromagnet collected by a permanent neodymium magnet.

    Science.gov (United States)

    Okuno, Takahisa; Thürmer, Stephan; Kanoh, Hirofumi

    2017-11-30

    Nanostructured silicon (N-Si) was prepared by anodic electroetching of p-type silicon wafers. The obtained magnetic particles were separated by a permanent neodymium magnet as a magnetic nanostructured silicon (mN-Si). The N-Si and mN-Si exhibited different magnetic properties: the N-Si exhibited ferromagnetic-like behaviour, whereas the mN-Si exhibited superparamagnetic-like behaviour.

  18. Organization of silicon nanocrystals by localized electrochemical etching

    International Nuclear Information System (INIS)

    Ayari-Kanoun, Asma; Drouin, Dominique; Beauvais, Jacques; Lysenko, Vladimir; Nychyporuk, Tetyana; Souifi, Abdelkader

    2009-01-01

    An approach to form a monolayer of organized silicon nanocrystals on a monocrystalline Si wafer is reported. Ordered arrays of nanoholes in a silicon nitride layer were obtained by combining electron beam lithography and plasma etching. Then, a short electrochemical etching current pulse led to formation of a single Si nanocrystal per each nanohole. As a result, high quality silicon nanocrystal arrays were formed with well controlled and reproducible morphologies. In future, this approach can be used to fabricate single electron devices.

  19. Methods and mechanisms of gettering of silicon structures in the production of integrated circuits

    Directory of Open Access Journals (Sweden)

    Pilipenko V. A.

    2013-05-01

    Full Text Available Increasing the degree of integration of hardware components imposes more stringent requirements for the reduction of the concentration of contaminants and oxidation stacking faults in the original silicon wafers with its preservation in the IC manufacturing process cycle. This causes high relevance of the application of gettering in modern microelectronic technology. The existing methods of silicon wafers gettering and the mechanisms of their occurrence are considered.

  20. TXRF analysis of trace metals in thin silicon nitride films

    International Nuclear Information System (INIS)

    Vereecke, G.; Arnauts, S.; Verstraeten, K.; Schaekers, M.; Heyrts, M.M.

    2000-01-01

    As critical dimensions of integrated circuits continue to decrease, high dielectric constant materials such as silicon nitride are being considered to replace silicon dioxide in capacitors and transistors. The achievement of low levels of metal contamination in these layers is critical for high performance and reliability. Existing methods of quantitative analysis of trace metals in silicon nitride require high amounts of sample (from about 0.1 to 1 g, compared to a mass of 0.2 mg for a 2 nm thick film on a 8'' silicon wafer), and involve digestion steps not applicable to films on wafers or non-standard techniques such as neutron activation analysis. A novel approach has recently been developed to analyze trace metals in thin films with analytical techniques currently used in the semiconductor industry. Sample preparation consists of three steps: (1) decomposition of the silicon nitride matrix by moist HF condensed at the wafer surface to form ammonium fluosilicate. (2) vaporization of the fluosilicate by a short heat treatment at 300 o C. (3) collection of contaminants by scanning the wafer surface with a solution droplet (VPD-DSC procedure). The determination of trace metals is performed by drying the droplet on the wafer and by analyzing the residue by TXRF, as it offers the advantages of multi-elemental analysis with no dilution of the sample. The lower limits of detection for metals in 2 nm thick films on 8'' silicon wafers range from about 10 to 200 ng/g. The present study will focus on the matrix effects and the possible loss of analyte associated with the evaporation of the fluosilicate salt, in relation with the accuracy and the reproducibility of the method. The benefits of using an internal standard will be assessed. Results will be presented from both model samples (ammonium fluoride contaminated with metallic salts) and real samples (silicon nitride films from a production tool). (author)

  1. Mechanics of wafer bonding: Effect of clamping

    Science.gov (United States)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  2. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  3. a Study of Oxygen Precipitation in Heavily Doped Silicon.

    Science.gov (United States)

    Graupner, Robert Kurt

    Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation

  4. Detection of paint polishing defects

    Science.gov (United States)

    Rebeggiani, S.; Wagner, M.; Mazal, J.; Rosén, B.-G.; Dahlén, M.

    2018-06-01

    Surface finish plays a major role on perceived product quality, and is the first thing a potential buyer sees. Today end-of-line repairs of the body of cars and trucks are inevitably to secure required surface quality. Defects that occur in the paint shop, like dust particles, are eliminated by manual sanding/polishing which lead to other types of defects when the last polishing step is not performed correctly or not fully completed. One of those defects is known as ‘polishing roses’ or holograms, which are incredibly hard to detect in artificial light but are clearly visible in sunlight. This paper will present the first tests with a measurement set-up newly developed to measure and analyse polishing roses. The results showed good correlations to human visual evaluations where repaired panels were estimated based on the defects’ intensity, severity and viewing angle.

  5. Tooth polishing: The current status

    Directory of Open Access Journals (Sweden)

    Madhuri Alankar Sawai

    2015-01-01

    Full Text Available Healthy teeth and gums make a person feel confident and fit. As people go about their daily routines and with different eating and drinking habits, the tooth enamel turns yellowish or gets stained. Polishing traditionally has been associated with the prophylaxis procedure in most dental practices, which patients know and expect. However, with overzealous use of polishing procedure, there is wearing of the superficial tooth structure. This would lead to more accumulation of local deposits. Also, it takes a long time for the formation of the fluoride-rich layer of the tooth again. Hence, now-a-days, polishing is not advised as a part of routine oral prophylaxis procedure but is done selectively based on the patients′ need. The article here, gives an insight on the different aspects of the polishing process along with the different methods and agents used for the same.

  6. Lysenko affair and Polish botany.

    Science.gov (United States)

    Köhler, Piotr

    2011-01-01

    This article describes the slight impact of Lysenkoism upon Polish botany. I begin with an account of the development of plant genetics in Poland, as well as the attitude of scientists and the Polish intelligentsia toward Marxist philosophy prior to the World War II. Next I provide a short history of the introduction and demise of Lysenkoism in Polish science, with a focus on events in botany, in context with key events in Polish science from 1939 to 1958. The article outlines the little effects of Lysenkoism upon botanists and their research, as well as how botanists for the most part rejected what was often termed the "new biology." My paper shows that though Lysenko's theories received political support, and were actively promoted by a small circle of scientists and Communist party activists, they were never accepted by most botanists. Once the political climate in Poland altered after the events of 1956, Lysenko's theories were immediately abandoned.

  7. Carbon dioxide capture using resin-wafer electrodeionization

    Science.gov (United States)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  8. Wafer plane inspection with soft resist thresholding

    Science.gov (United States)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  9. NTD Silicon; Product Characteristics, Main Uses and Growth Potential

    International Nuclear Information System (INIS)

    Hansen, M. G.; Bjorling, C. F.

    2013-01-01

    Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain

  10. NTD Silicon; Product Characteristics, Main Uses and Growth Potential

    Energy Technology Data Exchange (ETDEWEB)

    Hansen, M. G.; Bjorling, C. F. [Topsil Semiconductor Materials A/S, Odense (Denmark)

    2013-07-01

    Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain.

  11. Wafer-shape metrics based foundry lithography

    Science.gov (United States)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  12. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  13. Elastic emission polishing

    Energy Technology Data Exchange (ETDEWEB)

    Loewenthal, M.; Loseke, K.; Dow, T.A.; Scattergood, R.O.

    1988-12-01

    Elastic emission polishing, also called elastic emission machining (EEM), is a process where a stream of abrasive slurry is used to remove material from a substrate and produce damage free surfaces with controlled surface form. It is a noncontacting method utilizing a thick elasto-hydrodynamic film formed between a soft rotating ball and the workpiece to control the flow of the abrasive. An apparatus was built in the Center, which consists of a stationary spindle, a two-axis table for the workpiece, and a pump to circulate the working fluid. The process is controlled by a programmable computer numerical controller (CNC), which presently can operate the spindle speed and movement of the workpiece in one axis only. This apparatus has been used to determine material removal rates on different material samples as a function of time, utilizing zirconium oxide (ZrO{sub 2}) particles suspended in distilled water as the working fluid. By continuing a study of removal rates the process should become predictable, and thus create a new, effective, yet simple tool for ultra-precision mechanical machining of surfaces.

  14. Signal development in irradiated silicon detectors

    CERN Document Server

    Kramberger, Gregor; Mikuz, Marko

    2001-01-01

    This work provides a detailed study of signal formation in silicon detectors, with the emphasis on detectors with high concentration of irradiation induced defects in the lattice. These defects give rise to deep energy levels in the band gap. As a consequence, the current induced by charge motion in silicon detectors is signifcantly altered. Within the framework of the study a new experimental method, Charge correction method, based on transient current technique (TCT) was proposed for determination of effective electron and hole trapping times in irradiated silicon detectors. Effective carrier trapping times were determined in numerous silicon pad detectors irradiated with neutrons, pions and protons. Studied detectors were fabricated on oxygenated and non-oxygenated silicon wafers with different bulk resistivities. Measured effective carrier trapping times were found to be inversely proportional to fuence and increase with temperature. No dependence on silicon resistivity and oxygen concentration was observ...

  15. Low-temperature Au/a-Si wafer bonding

    International Nuclear Information System (INIS)

    Jing, Errong; Xiong, Bin; Wang, Yuelin

    2011-01-01

    The Si/SiO 2 /Ti/Au–Au/Ti/a-Si/SiO 2 /Si bonding structure, which can also be used for the bonding of non-silicon material, was investigated for the first time in this paper. The bond quality test showed that the bond yield, bond repeatability and average shear strength are higher for this bonding structure. The interfacial microstructure analysis indicated that the Au-induced crystallization of the amorphous silicon process leads to big Si grains extending across the bond interface and Au filling the other regions of the bond interface, which result into a strong and void-free bond interface. In addition, the Au-induced crystallization reaction leads to a change in the IR images of the bond interface. Therefore, the IR microscope can be used to evaluate and compare the different bond strengths qualitatively. Furthermore, in order to verify the superiority of the bonding structure, the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si (i.e. no Ti/Au layer on the a-Si surface) and Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structures (i.e. Au thermocompression bonding) were also investigated. For the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si bonding structure, the poor bond quality is due to the native oxide layer on the a-Si surface, and for the Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structure, the poor bond quality is caused by the wafer surface roughness which prevents intimate contact and limits the interdiffusion at the bond interface.

  16. Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

    Directory of Open Access Journals (Sweden)

    Azrul Azlan Hamzah

    2008-11-01

    Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

  17. Silicon heterojunction solar cell passivation in combination with nanocrystalline silicon oxide emitters

    NARCIS (Netherlands)

    Gatz, H.A.; Rath, J.K.; Verheijen, M.A.; Kessels, W.M.M.; Schropp, R.E.I.

    2016-01-01

    Silicon heterojunction solar cells (SHJ) are well known for their high efficiencies, enabled by their remarkably high open-circuit voltages (VOC). A key factor in achieving these values is a good passivation of the crystalline wafer interface. One of the restrictions during SHJ solar cell production

  18. Mechanically flexible optically transparent porous mono-crystalline silicon substrate

    KAUST Repository

    Rojas, Jhonathan Prieto; Syed, Ahad A.; Hussain, Muhammad Mustafa

    2012-01-01

    For the first time, we present a simple process to fabricate a thin (≥5μm), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon <100> wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates. © 2012 IEEE.

  19. Superacid Passivation of Crystalline Silicon Surfaces.

    Science.gov (United States)

    Bullock, James; Kiriya, Daisuke; Grant, Nicholas; Azcatl, Angelica; Hettick, Mark; Kho, Teng; Phang, Pheng; Sio, Hang C; Yan, Di; Macdonald, Daniel; Quevedo-Lopez, Manuel A; Wallace, Robert M; Cuevas, Andres; Javey, Ali

    2016-09-14

    The reduction of parasitic recombination processes commonly occurring within the silicon crystal and at its surfaces is of primary importance in crystalline silicon devices, particularly in photovoltaics. Here we explore a simple, room temperature treatment, involving a nonaqueous solution of the superacid bis(trifluoromethane)sulfonimide, to temporarily deactivate recombination centers at the surface. We show that this treatment leads to a significant enhancement in optoelectronic properties of the silicon wafer, attaining a level of surface passivation in line with state-of-the-art dielectric passivation films. Finally, we demonstrate its advantage as a bulk lifetime and process cleanliness monitor, establishing its compatibility with large area photoluminescence imaging in the process.

  20. Transistors using crystalline silicon devices on glass

    Science.gov (United States)

    McCarthy, Anthony M.

    1995-01-01

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

  1. Polish Toxic Currency Options

    Directory of Open Access Journals (Sweden)

    Waldemar Gontarski

    2009-06-01

    Full Text Available Toxic currency options are defined on the basis of the opposition to the nature (essence of an option contract, which is justified in terms of norms founded on the general law clause of characteristics (nature of a relation (which represents an independent premise for imposing restrictions on the freedom of contracts. So-understood toxic currency options are unlawful. Indeed they contravene iuris cogentis regulations. These include for instance option contracts, which are concluded with a bank, if the bank has not informed about option risk before concluding the contract; or the barrier options, which focus only on the protection of bank’s interests. Therefore, such options may appear to be invalid. Therefore, performing contracts for toxic currency options may be qualified as a criminal mismanagement. For the sake of security, the manager should then take into consideration filing a claim for stating invalidity (which can be made in a court verdict. At the same time, if the supervisory board member in a commercial company, who can also be a subject to mismanagement offences, commits an omission involving lack of reaction (for example, if he/she fails to notify of the suspected offence committed by the management board members acting to the company’s detriment when the management board makes the company conclude option contracts which are charged with absolute invalidity the supervisory board member so acting may be considered to act to the company’s detriment. In the most recent Polish jurisprudence and judicature the standard of a “good host” is treated to be the last resort for determining whether the manager’s powers resulting from criminal regulations were performed. The manager of the exporter should not, as a rule, issue any options. Issuing options always means assuming an obligation. In the case of currency put options it is an absolute obligation to purchase a given amount in euro at exchange rate set in advance. On the

  2. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  3. Silicon (100)/SiO2 by XPS

    Energy Technology Data Exchange (ETDEWEB)

    Jensen, David S.; Kanyal, Supriya S.; Madaan, Nitesh; Vail, Michael A.; Dadson, Andrew; Engelhard, Mark H.; Linford, Matthew R.

    2013-09-25

    Silicon (100) wafers are ubiquitous in microfabrication and, accordingly, their surface characteristics are important. Herein, we report the analysis of Si (100) via X-ray photoelectron spectroscopy (XPS) using monochromatic Al K radiation. Survey scans show that the material is primarily silicon and oxygen, and the Si 2p region shows two peaks that correspond to elemental silicon and silicon dioxide. Using these peaks the thickness of the native oxide (SiO2) was estimated using the equation of Strohmeier.1 The oxygen peak is symmetric. The material shows small amounts of carbon, fluorine, and nitrogen contamination. These silicon wafers are used as the base material for subsequent growth of templated carbon nanotubes.

  4. Bias-assisted KOH etching of macroporous silicon membranes

    International Nuclear Information System (INIS)

    Mathwig, K; Geilhufe, M; Müller, F; Gösele, U

    2011-01-01

    This paper presents an improved technique to fabricate porous membranes from macroporous silicon as a starting material. A crucial step in the fabrication process is the dissolution of silicon from the backside of the porous wafer by aqueous potassium hydroxide to open up the pores. We improved this step by biasing the silicon wafer electrically against the KOH. By monitoring the current–time characteristics a good control of the process is achieved and the yield is improved. Also, the etching can be stopped instantaneously and automatically by short-circuiting Si and KOH. Moreover, the bias-assisted etching allows for the controlled fabrication of silicon dioxide tube arrays when the silicon pore walls are oxidized and inverted pores are released.

  5. Silicon Nanowire Field-effect Chemical Sensor

    OpenAIRE

    Chen, S.

    2011-01-01

    This thesis describes the work that has been done on the project “Design and optimization of silicon nanowire for chemical sensing‿, including Si-NW fabrication, electrical/electrochemical modeling, the application as ISFET, and the build-up of Si- NW/LOC system for automatic sample delivery. A novel top-down fabrication technique was presented for single-crystal Si-NW fabrication realized with conventional microfabrication technique. High quality triangular Si-NWs were made with high wafer-s...

  6. Influence of Si wafer thinning processes on (sub)surface defects

    Energy Technology Data Exchange (ETDEWEB)

    Inoue, Fumihiro, E-mail: fumihiro.inoue@imec.be [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Uedono, Akira [Division of Applied Physics, Faculty of Pure and Applied Science, University of Tsukuba, Tsukuba, Ibaraki 305-8573 (Japan)

    2017-05-15

    Highlights: • Mono-vacancy free Si-thinning can be accomplished by combining several thinning techniques. • The grinding damage needs to be removed prior to dry etching, otherwise vacancies remain in the Si at a depth around 0.5 to 2 μm after Si wafer thickness below 5 μm. • The surface of grinding + CMP + dry etching is equivalent mono vacancy level as that of grinding + CMP. - Abstract: Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5–2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in

  7. Low-temperature micro-photoluminescence spectroscopy on laser-doped silicon with different surface conditions

    Science.gov (United States)

    Han, Young-Joon; Franklin, Evan; Fell, Andreas; Ernst, Marco; Nguyen, Hieu T.; Macdonald, Daniel

    2016-04-01

    Low-temperature micro-photoluminescence spectroscopy (μ-PLS) is applied to investigate shallow layers of laser-processed silicon for solar cell applications. Micron-scale measurement (with spatial resolution down to 1 μm) enables investigation of the fundamental impact of laser processing on the electronic properties of silicon as a function of position within the laser-processed region, and in particular at specific positions such as at the boundary/edge of processed and unprocessed regions. Low-temperature μ-PLS enables qualitative analysis of laser-processed regions by identifying PLS signals corresponding to both laser-induced doping and laser-induced damage. We show that the position of particular luminescence peaks can be attributed to band-gap narrowing corresponding to different levels of subsurface laser doping, which is achieved via multiple 248 nm nanosecond excimer laser pulses with fluences in the range 1.5-4 J/cm2 and using commercially available boron-rich spin-on-dopant precursor films. We demonstrate that characteristic defect PL spectra can be observed subsequent to laser doping, providing evidence of laser-induced crystal damage. The impact of laser parameters such as fluence and number of repeat pulses on laser-induced damage is also analyzed by observing the relative level of defect PL spectra and absolute luminescence intensity. Luminescence owing to laser-induced damage is observed to be considerably larger at the boundaries of laser-doped regions than at the centers, highlighting the significant role of the edges of laser-doped region on laser doping quality. Furthermore, by comparing the damage signal observed after laser processing of two different substrate surface conditions (chemically-mechanically polished and tetramethylammonium hydroxide etched), we show that wafer preparation can be an important factor impacting the quality of laser-processed silicon and solar cells.

  8. Polish-German bilingualism at school. A Polish perspective

    Directory of Open Access Journals (Sweden)

    Pulaczewska, Hanna

    2014-03-01

    Full Text Available This article presents the institutional frames for the acquisition of Polish literacy skills in Germany and the maintenance of Polish-German bilingualism after the repatriation of bilingual children to Poland. These processes are examined in the context of recent developments in the European domestic job market. While the European Union has placed proficiency in several languages among its educational objectives, and foreign languages have been made obligatory school subjects in all member countries, the potential advantages of internal European migrations for producing high-proficiency bilinguals are being ignored. Bilingualism resulting from migration and biculturalism enjoys little social prestige in the host countries. In Germany, there is significant regional variation in how school authorities react to challenges posed by the presence of minority languages. In many cases, the linguistic potential of many second-generation migrants and re-emigrants gets largely wasted because of lacking interest and incentives from German and Polish institutions alike.

  9. Effect of polishing instruments and polishing regimens on surface topography and phase transformation of monolithic zirconia: An evaluation with XPS and XRD analysis.

    Science.gov (United States)

    Al-Haj Husain, Nadin; Camilleri, Josette; Özcan, Mutlu

    2016-12-01

    Polishing procedures might alter monolithic zirconia (MZ) surface resulting in phase changes that can be deleterious for clinical performance and antagonist tooth wear. This study investigated the topographical features and phase transformation in MZ after polishing with different regimens simulating the clinical workflow. ​ MZ specimens (Katana Zirconia HT, Kuraray-Noritake) (12×12×1.8 mm(3)) were grinded and polished using one of the five systems assessed: BG: Silicone carbide polishers (Brownie, Greenie, Super Greenie); CG: Diamond impregnated ceramic polisher kit (Ceragloss); EV: Synthetically bonded grinder interspersed with diamond (EVE Kit); SL: Urethane coated paper with aluminium oxide grits (Soflex Finishing and Polishing System Kit) and DB: Diamond bur (8 µm). Polished specimens were initially roughened with 220 µm diamond burs (Grinding Bur-GB) (10 s, 160.000160,000 rpm) and considered for baseline measurements. Polishing regimens were performed for 10 s using a slow-speed hand piece under water-cooling except for SL, in a custom made device (750 g; 5000 and 75,000 rpm). Surface roughnesses, phase changes (XRD) were assessed, surface characterization was performed (SEM, EDS). The highest roughness was obtained with the EV system (1.11 µm) compared to those of other systems (0.13-0.4 µm) (pθ and minor peak at 34.94°2θ. While GB, CG, EV, SL and DB exhibited a peak shift to the left, BG demonstrated a right peak shift on the 2θ scale. Monoclinic phase change was not noted in any of the groups. All polishing methods, except BG, exhibited a peak shift towards the lower angles of the 2-theta scale. Since the peak shifts were in the order of fractions of an angle they are attributed to stress formation rather than a phase change in the material. Thus, all polishing systems tested may not be detrimental for the phase transformation of MZ. EV system resulted in the highest roughness and none of the polishing regimens restored the polishability to the

  10. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  11. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  12. Effect of conditioner load on the polishing pad surface during chemical mechanical planarization process

    Energy Technology Data Exchange (ETDEWEB)

    Shin, Cheol Min; Qin, Hong Yi; Hong, Seok Jun; Jeon, Sang Hyuk; Kulkarni, Atul; Kim, Tae Sun [Sungkyunkwan University, Suwon (Korea, Republic of)

    2016-12-15

    During the Chemical mechanical planarization (CMP), the pad conditioning process can affect the pad surface characteristics. Among many CMP process parameters, the improper applied load on the conditioner arm may have adverse effects on the polyurethane pad. In this work, we evaluated the pad surface properties under the various conditioner arm applied during pad conditioning process. The conditioning pads were evaluated for surface topography, surface roughness parameters such as Rt and Rvk and Material removal rate (MRR) and within-wafer non-uniformity after wafer polishing. We observed that, the pad asperities were collapsed in the direction of conditioner rotation and blocks the pad pores applied conditioner load. The Rvk value and MRR were founded to be in relation with 4 > 1 > 7 kgF conditioner load. Hence, this study shows that, 4 kgF applied load by conditioner is most suitable for the pad conditioning during CMP.

  13. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  14. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  15. Sensing roughness and polish direction

    DEFF Research Database (Denmark)

    Jakobsen, Michael Linde; Olesen, Anders Sig; Larsen, Henning Engelbrecht

    2016-01-01

    As a part of the work carried out in a project supported by the Danish Council for Technology and Innovation, we have investigated the option of smoothing standard CNC-machined surfaces. In the process of constructing optical prototypes, involving custom-designed optics, the development cost...... and time consumption can become prohibitive in a research budget. Machining the optical surfaces directly is expensive and time consuming. Alternatively, a more standardized and cheaper machining method can be used, calling for the object to be manually polished. During the polishing process, the operator...... needs information about the RMS-value of the surface roughness and the current direction of the scratches introduced by the polishing process. The RMS-value indicates to the operator how far he is from the final finish, and the scratch orientation is often specified by the customer in order to avoid...

  16. Method of fabricating porous silicon carbide (SiC)

    Science.gov (United States)

    Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

    1995-01-01

    Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

  17. Silicone metalization

    Energy Technology Data Exchange (ETDEWEB)

    Maghribi, Mariam N. (Livermore, CA); Krulevitch, Peter (Pleasanton, CA); Hamilton, Julie (Tracy, CA)

    2008-12-09

    A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

  18. Waveguide silicon nitride grating coupler

    Science.gov (United States)

    Litvik, Jan; Dolnak, Ivan; Dado, Milan

    2016-12-01

    Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

  19. Cannabinoids cases in polish athletes

    OpenAIRE

    A Pokrywka; Z Obmiński; D Kwiatkowska; R Grucza

    2009-01-01

    The aim of this study was to investigate the number of cases and the profiles of Polish athletes who had occasionally been using marijuana or hashish throughout the period of 1998-2004, with respect to: sex, age, and discipline of sport as well as the period of testing (in- and out-of-competition). Results of the study were compared with some data reported by other WADA accredited anti-doping laboratories. Totally, 13 631 urine samples taken from Polish athletes of both sexes, aged 10-67 year...

  20. Graphite Composite Panel Polishing Fixture

    Science.gov (United States)

    Hagopian, John; Strojny, Carl; Budinoff, Jason

    2011-01-01

    The use of high-strength, lightweight composites for the fixture is the novel feature of this innovation. The main advantage is the light weight and high stiffness-to-mass ratio relative to aluminum. Meter-class optics require support during the grinding/polishing process with large tools. The use of aluminum as a polishing fixture is standard, with pitch providing a compliant layer to allow support without deformation. Unfortunately, with meter-scale optics, a meter-scale fixture weighs over 120 lb (.55 kg) and may distort the optics being fabricated by loading the mirror and/or tool used in fabrication. The use of composite structures that are lightweight yet stiff allows standard techniques to be used while providing for a decrease in fixture weight by almost 70 percent. Mounts classically used to support large mirrors during fabrication are especially heavy and difficult to handle. The mount must be especially stiff to avoid deformation during the optical fabrication process, where a very large and heavy lap often can distort the mount and optic being fabricated. If the optic is placed on top of the lapping tool, the weight of the optic and the fixture can distort the lap. Fixtures to support the mirror during fabrication are often very large plates of aluminum, often 2 in. (.5 cm) or more in thickness and weight upwards of 150 lb (68 kg). With the addition of a backing material such as pitch and the mirror itself, the assembly can often weigh over 250 lb (.113 kg) for a meter-class optic. This innovation is the use of a lightweight graphite panel with an aluminum honeycomb core for use as the polishing fixture. These materials have been used in the aerospace industry as structural members due to their light weight and high stiffness. The grinding polishing fixture consists of the graphite composite panel, fittings, and fixtures to allow interface to the polishing machine, and introduction of pitch buttons to support the optic under fabrication. In its

  1. Origin of high oxide to nitride polishing selectivity of ceria-based slurry in the presence of picolinic acid

    International Nuclear Information System (INIS)

    Wang Liang-Yong; Liu Bo; Song Zhi-Tang; Liu Wei-Li; Feng Song-Lin; David Huang; Babu, S.V

    2011-01-01

    We report on the investigation of the origin of high oxide to nitride polishing selectivity of ceria-based slurry in the presence of picolinic acid. The oxide to nitride removal selectivity of the ceria slurry with picolinic acid is as high as 76.6 in the chemical mechanical polishing. By using zeta potential analyzer, particle size analyzer, horizon profilometer, thermogravimetric analysis and Fourier transform infrared spectroscopy, the pre- and the post-polished wafer surfaces as well as the pre- and the post-used ceria-based slurries are compared. Possible mechanism of high oxide to nitride selectivity with using ceria-based slurry with picolinic acid is discussed. (interdisciplinary physics and related areas of science and technology)

  2. Origin of high oxide to nitride polishing selectivity of ceria-based slurry in the presence of picolinic acid

    Institute of Scientific and Technical Information of China (English)

    Wang Liang-Yong; Liu Bo; Song Zhi-Tang; Liu Wei-Li; Feng Song-Lin; David Huang; S.V Babu

    2011-01-01

    We report on the investigation of the origin of high oxide to nitride polishing selectivity of ceria-based slurry in the presence of picolinic acid. The oxide to nitride removal selectivity of the ceria slurry with picolinic acid is as high as 76.6 in the chemical mechanical polishing. By using zeta potential analyzer, particle size analyzer, horizon profilometer, thermogravimetric analysis and Fourier transform infrared spectroscopy, the pre-and the post-polished wafer surfaces as well as the pre-and the post-used ceria-based slurries are compared. Possible mechanism of high oxide to nitride selectivity with using ceria-based slurry with picolinic acid is discussed.

  3. Impact of SiO2 on Al–Al thermocompression wafer bonding

    International Nuclear Information System (INIS)

    Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

    2015-01-01

    Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

  4. FY 1999 report on the results of R and D projects by local consortiums for immediate effects. R and D regarding high quality/high performance of lithium tantalate single crystal's solidifying growth and SAW wafer; 1999 nendo sankabutsu tankessho no ikusei to wafer no kohinshitsu konoritsuka ni kansuru kenkyu kaihatsu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-05-01

    The R and D project has been implemented for establishing, e.g., methods for growing oxide single crystals (e.g., lithium tantalate, LiTaO{sub 3}) to have the large and/or long products, technologies for polishing/cleaing the wafer products, and technologies for evaluating device performance. For solidifying growth and production technologies for lithium tantalate single crystals, pulling-up of the single crystal, 154 mm in body length and 12.9 kg, is succeeded by reducing temperature gradient at the crystal solid-liquid interface, increasing oxygen concentration, and improving the seed-sustaining system. Bright prospects have been obtained for the automated crystal pulling-up system, and high-precision control of crystal weight. For technologies for polishing/cleaning the wafers, the investigated cleaning methods include ELID polishing, mechanochemical polishing, and supersonic cleaning which uses two frequency bands of multi-supersonic and megasonic waves. For development of the technologies for evaluation/examination of the highly functional devices, the non-contact type method has been developed, which can measure the absolute level of SAW speed at a high speed and precision. (NEDO)

  5. FY 1999 report on the results of R and D projects by local consortiums for immediate effects. R and D regarding high quality/high performance of lithium tantalate single crystal's solidifying growth and SAW wafer; 1999 nendo sankabutsu tankessho no ikusei to wafer no kohinshitsu konoritsuka ni kansuru kenkyu kaihatsu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-05-01

    The R and D project has been implemented for establishing, e.g., methods for growing oxide single crystals (e.g., lithium tantalate, LiTaO{sub 3}) to have the large and/or long products, technologies for polishing/cleaing the wafer products, and technologies for evaluating device performance. For solidifying growth and production technologies for lithium tantalate single crystals, pulling-up of the single crystal, 154 mm in body length and 12.9 kg, is succeeded by reducing temperature gradient at the crystal solid-liquid interface, increasing oxygen concentration, and improving the seed-sustaining system. Bright prospects have been obtained for the automated crystal pulling-up system, and high-precision control of crystal weight. For technologies for polishing/cleaning the wafers, the investigated cleaning methods include ELID polishing, mechanochemical polishing, and supersonic cleaning which uses two frequency bands of multi-supersonic and megasonic waves. For development of the technologies for evaluation/examination of the highly functional devices, the non-contact type method has been developed, which can measure the absolute level of SAW speed at a high speed and precision. (NEDO)

  6. A continuous Czochralski silicon crystal growth system

    Science.gov (United States)

    Wang, C.; Zhang, H.; Wang, T. H.; Ciszek, T. F.

    2003-03-01

    Demand for large silicon wafers has driven the growth of silicon crystals from 200 to 300 mm in diameter. With the increasing silicon ingot sizes, melt volume has grown dramatically. Melt flow becomes more turbulent as melt height and volume increase. To suppress turbulent flow in a large silicon melt, a new Czochralski (CZ) growth furnace has been designed that has a shallow melt. In this new design, a crucible consists of a shallow growth compartment in the center and a deep feeding compartment around the periphery. Two compartments are connected with a narrow annular channel. A long crystal may be continuously grown by feeding silicon pellets into the dedicated feeding compartment. We use our numerical model to simulate temperature distribution and velocity field in a conventional 200-mm CZ crystal growth system and also in the new shallow crucible CZ system. By comparison, advantages and disadvantages of the proposed system are observed, operating conditions are determined, and the new system is improved.

  7. Micro benchtop optics by bulk silicon micromachining

    Science.gov (United States)

    Lee, Abraham P.; Pocha, Michael D.; McConaghy, Charles F.; Deri, Robert J.

    2000-01-01

    Micromachining of bulk silicon utilizing the parallel etching characteristics of bulk silicon and integrating the parallel etch planes of silicon with silicon wafer bonding and impurity doping, enables the fabrication of on-chip optics with in situ aligned etched grooves for optical fibers, micro-lenses, photodiodes, and laser diodes. Other optical components that can be microfabricated and integrated include semi-transparent beam splitters, micro-optical scanners, pinholes, optical gratings, micro-optical filters, etc. Micromachining of bulk silicon utilizing the parallel etching characteristics thereof can be utilized to develop miniaturization of bio-instrumentation such as wavelength monitoring by fluorescence spectrometers, and other miniaturized optical systems such as Fabry-Perot interferometry for filtering of wavelengths, tunable cavity lasers, micro-holography modules, and wavelength splitters for optical communication systems.

  8. Evaluation of environmental impacts during chemical mechanical polishing (CMP) for sustainable manufacturing

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Hyun Seop; Park, Sun Joon; Jeong, Hae Do [Pusan National University, Busan (Korea, Republic of)

    2013-02-15

    Reducing energy consumption has become a critical issue in manufacturing. The semiconductor industry in particular is confronted with environmental regulations on pollution associated with electric energy, chemical, and ultrapure water (UPW) consumptions. This paper presents the results of an evaluation of the environmental impacts during chemical mechanical polishing (CMP), a key process for planarization of dielectrics and metal films in ultra-large-scale integrated circuits. The steps in the CMP process are idling, conditioning, wetting, wafer loading/unloading, head dropping, polishing, and rinsing. The electric energy, CMP slurry, and UPW consumptions associated with the process and their impacts on global warming are evaluated from an environmental standpoint. The estimates of electric energy, slurry, and UPW consumptions as well as the associated greenhouse gas emissions presented in this paper will provide a technical aid for reducing the environmental burden associated with electricity consumption during the CMP process.

  9. Polish-Bulgarian-Russian, Bulgarian-Polish-Russian or Russian-Bulgarian-Polish dictionary?

    Directory of Open Access Journals (Sweden)

    Violetta Koseska-Toszewa

    2015-11-01

    Full Text Available Polish-Bulgarian-Russian, Bulgarian-Polish-Russian or Russian-Bulgarian-Polish dictionary? The trilingual dictionary (M. Duszkin, V. Koseska, J. Satoła and A. Tzoneva is being elaborated based on a working Polish-Bulgarian-Russian electronic parallel corpus authored by Maksim Duszkin, Violetta Koseska-Toszewa and Joanna Satoła-Staśkowiak, and works by A. Tzoneva. It is the first corpus comparing languages belonging to three different Slavic language groups: western, southern and eastern. Works on the dictionary are based on Gramatyka konfrontatywna bułgarsko-polska (Bulgarian-Polish confrontative grammar and the proposed there semantic-oriented interlanguage. Two types of classifiers have been introduced into the dictionary: classic and semantic. The trilingual dictionary will present a consistent and homogeneous set of facts of grammar and semantics. The Authors point out that in a traditional dictionary it is not clear for example whether aspect should be understood as imperfective / perfective form of a verb or as its meaning. Therefore in the dictionary forms and meaning are separated in a regular way. Imperfective verb form has two meanings: state and configuration of states and events culminating in state. Also perfective verb form has two meanings: event and configuration of states and events culminating in event. These meanings are described by the semantic classifiers, respectively, state and event, state1 and event1. The way of describing language units, mentioned in the article, gives a possibility to present language material (Polish, Bulgarian, Russian in any required order, hence the article’s title.

  10. Fabrication of the similar porous alumina silicon template for soft UV nanoimprint lithography

    Energy Technology Data Exchange (ETDEWEB)

    Sun, Tangyou [Wuhan National Laboratory for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China); Xu, Zhimou, E-mail: xuzhimou@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China); Zhao, Wenning; Wu, Xinghui; Liu, Sisi; Zhang, Zheng; Wang, Shuangbao; Liu, Wen [Wuhan National Laboratory for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China); Liu, Shiyuan [State Key Laboratory of Digital Manufacturing Equipment and Technology, Huazhong University of Science and Technology, Wuhan 430074 (China); Peng, Jing [College of Sciences, Wuhan University of Science and Technology, Wuhan 430081 (China)

    2013-07-01

    High density honeycombed nanostructures of porous alumina template (PAT) have been widely used to the fabrication of various electronic, optoelectronic, magnetic, and energy storage devices. However, patterning structures at sub-100 nm feature size with large area and low cost is of great importance and hardness on which semiconductor manufacture technology depends. In this paper, soft UV nanoimprint lithography (SUNIL) by using PAT as the initial mold is studied in detail. The results reveal a significant incompatibility between these two candidates. The native nonflatness of the PAT surface is about 100 nm in the range of 2–5 μm. Resist detaches from the substrate because of the mold deformation in the nonflat SUNIL. A two-inch similar porous alumina silicon (Si) template with nanopore size of 50–100 nm is fabricated. I–t curve conducted anodization and subsequent inductive coupled plasma (ICP) dry etching are applied to ensure the uniformity of the fabricated template. The surface flatness of the similar porous alumina Si template is the same as the polished Si wafer, which perfectly matches NIL.

  11. Cannabinoids cases in polish athletes

    Directory of Open Access Journals (Sweden)

    A Pokrywka

    2009-07-01

    Full Text Available The aim of this study was to investigate the number of cases and the profiles of Polish athletes who had occasionally been using marijuana or hashish throughout the period of 1998-2004, with respect to: sex, age, and discipline of sport as well as the period of testing (in- and out-of-competition. Results of the study were compared with some data reported by other WADA accredited anti-doping laboratories. Totally, 13 631 urine samples taken from Polish athletes of both sexes, aged 10-67 years, performing 46 disciplines of sport were tested. Cannabinoids were detected in 267 samples. Among Polish athletes the relative number of positive THC (tetrahydrocannabinol samples was one of the highest in Europe. The group of young Polish athletes (aged 16-24 years was the most THC-positive. THC-positive cases were noted more frequently in male athletes tested during out of competitions. The so-called contact sports (rugby, ice hockey, skating, boxing, badminton, body building and acrobatic sports were those sports, where the higher risk of cannabis use was observed. The legal interpretation of some positive cannabinoids results would be difficult because of some accidental and unintentional use of the narcotics by sportsmen. It was concluded that national anti-doping organizations (NADO’s, which are competent to judge whether the anti-doping rules were violated, should take into account the possibility of non-intentional doping use of cannabinoids via passive smoking of marijuana.

  12. Fabrication of Through via Holes in Ultra-Thin Fused Silica Wafers for Microwave and Millimeter-Wave Applications

    Directory of Open Access Journals (Sweden)

    Xiao Li

    2018-03-01

    Full Text Available Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave circuits and 3D integration. In this work, etching through via holes in ultra-thin fused silica wafers using deep reactive-ion etching (DRIE and laser ablation was developed and analyzed. The experimental setup and process parameters for both methods are presented and compared. For DRIE, three types of mask materials including KMPR 1035 (Nippon Kayaku, Tokyo, Japan photoresist, amorphous silicon and chromium—with their corresponding optimized processing recipes—were tested, aiming at etching through a 100 μm fused silica wafer. From the experiments, we concluded that using chromium as the masking material is the best choice when using DRIE. However, we found that the laser ablation method with a laser pulse fluence of 2.89 J/cm2 and a pulse overlap of 91% has advantages over DRIE. The laser ablation method has a simpler process complexity, while offering a fair etching result. In particular, the sidewall profile angle is measured to be 75° to the bottom surface of the wafer, which is ideal for the subsequent metallization process. As a demonstration, a two-inch wafer with 624 via holes was processed using both technologies, and the laser ablation method showed better efficiency compared to DRIE.

  13. Analysis of the silicon market: Will thin films profit?

    International Nuclear Information System (INIS)

    Sark, W.G.J.H.M. van; Brandsen, G.W.; Fleuster, M.; Hekkert, M.P.

    2007-01-01

    The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010

  14. Analysis of the silicon market: Will thin films profit?

    Energy Technology Data Exchange (ETDEWEB)

    Sark, W.G.J.H.M. van; Brandsen, G.W. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Science, Technology and Society; Fleuster, M. [Solland Solar Energy, Heerlen (Netherlands); Hekkert, M.P. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Innovation Studies

    2007-06-15

    The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010. (author)

  15. Micro filtration membrane sieve with silicon micro machining for industrial and biomedical applications

    NARCIS (Netherlands)

    van Rijn, C.J.M.; Elwenspoek, Michael Curt

    1995-01-01

    With the use of silicon micromachining an inorganic membrane sieve for microfiltration is constructed, having a siliconnitride membrane layer with thickness typically 1 pm and perforations typically between 0.5 pm and 10 pm in diameter. As a support a -silicon wafer with openings of loo0 pm in

  16. Laser direct writing of oxide structures on hydrogen-passivated silicon surfaces

    DEFF Research Database (Denmark)

    Müllenborn, Matthias; Birkelund, Karen; Grey, Francois

    1996-01-01

    on amorphous and crystalline silicon surfaces in order to determine the depassivation mechanism. The minimum linewidth achieved is about 450 nm using writing speeds of up to 100 mm/s. The process is fully compatible with local oxidation of silicon by scanning probe lithography. Wafer-scale patterns can...

  17. Silicon-photonics light source realized by III-V/Si grating-mirror laser

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2010-01-01

    waveguide are made in the Si layer of a silicon-on-insulator wafer by using Si-electronics-compatible processing. The HCG works as a highly-reflective mirror for vertical resonance and at the same time routes light to the in-plane output waveguide. Numerical simulations show superior performance compared...... to existing silicon light sources....

  18. Porous silicon in solar cell structures : a review of achievements and modern directions of further use

    NARCIS (Netherlands)

    Yerokhov, VY; Melnyk, [No Value

    1999-01-01

    Porous silicon, which is being obtained by electrochemical etching of silicon wafers in electrolytes on the base of hydrofluoric acid, recently attracted the attention of specialists in photovoltaics even more due to a number of its unique properties. However, at present, acceptable results are

  19. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  20. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    International Nuclear Information System (INIS)

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  1. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  2. Voltage-assisted polymer wafer bonding

    International Nuclear Information System (INIS)

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  3. Thermoelectric properties of boron and boron phosphide CVD wafers

    Energy Technology Data Exchange (ETDEWEB)

    Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

    1997-10-01

    Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

  4. Effect of silicon solar cell processing parameters and crystallinity on mechanical strength

    Energy Technology Data Exchange (ETDEWEB)

    Popovich, V.A.; Yunus, A.; Janssen, M.; Richardson, I.M. [Delft University of Technology, Department of Materials Science and Engineering, Delft (Netherlands); Bennett, I.J. [Energy Research Centre of the Netherlands, Solar Energy, PV Module Technology, Petten (Netherlands)

    2011-01-15

    Silicon wafer thickness reduction without increasing the wafer strength leads to a high breakage rate during subsequent handling and processing steps. Cracking of solar cells has become one of the major sources of solar module failure and rejection. Hence, it is important to evaluate the mechanical strength of solar cells and influencing factors. The purpose of this work is to understand the fracture behavior of silicon solar cells and to provide information regarding the bending strength of the cells. Triple junctions, grain size and grain boundaries are considered to investigate the effect of crystallinity features on silicon wafer strength. Significant changes in fracture strength are found as a result of metallization morphology and crystallinity of silicon solar cells. It is observed that aluminum paste type influences the strength of the solar cells. (author)

  5. A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

    International Nuclear Information System (INIS)

    Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

    1990-01-01

    The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

  6. CHARACTERIZATION OF THE ELECTROPHYSICAL PROPERTIES OF SILICON-SILICON DIOXIDE INTERFACE USING PROBE ELECTROMETRY METHODS

    Directory of Open Access Journals (Sweden)

    V. А. Pilipenko

    2017-01-01

    Full Text Available Introduction of submicron design standards into microelectronic industry and a decrease of the gate dielectric thickness raise the importance of the analysis of microinhomogeneities in the silicon-silicon dioxide system. However, there is very little to no information on practical implementation of probe electrometry methods, and particularly scanning Kelvin probe method, in the interoperational control of real semiconductor manufacturing process. The purpose of the study was the development of methods for nondestructive testing of semiconductor wafers based on the determination of electrophysical properties of the silicon-silicon dioxide interface and their spatial distribution over wafer’s surface using non-contact probe electrometry methods.Traditional C-V curve analysis and scanning Kelvin probe method were used to characterize silicon- silicon dioxide interface. The samples under testing were silicon wafers of KEF 4.5 and KDB 12 type (orientation <100>, diameter 100 mm.Probe electrometry results revealed uniform spatial distribution of wafer’s surface potential after its preliminary rapid thermal treatment. Silicon-silicon dioxide electric potential values were also higher after treatment than before it. This potential growth correlates with the drop in interface charge density. At the same time local changes in surface potential indicate changes in surface layer structure.Probe electrometry results qualitatively reflect changes of interface charge density in silicon-silicon dioxide structure during its technological treatment. Inhomogeneities of surface potential distribution reflect inhomogeneity of damaged layer thickness and can be used as a means for localization of interface treatment defects.

  7. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    CERN Document Server

    Bronuzzi, J.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

  8. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    International Nuclear Information System (INIS)

    Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

  9. Silicon-Rich Silicon Carbide Hole-Selective Rear Contacts for Crystalline-Silicon-Based Solar Cells.

    Science.gov (United States)

    Nogay, Gizem; Stuckelberger, Josua; Wyss, Philippe; Jeangros, Quentin; Allebé, Christophe; Niquille, Xavier; Debrot, Fabien; Despeisse, Matthieu; Haug, Franz-Josef; Löper, Philipp; Ballif, Christophe

    2016-12-28

    The use of passivating contacts compatible with typical homojunction thermal processes is one of the most promising approaches to realizing high-efficiency silicon solar cells. In this work, we investigate an alternative rear-passivating contact targeting facile implementation to industrial p-type solar cells. The contact structure consists of a chemically grown thin silicon oxide layer, which is capped with a boron-doped silicon-rich silicon carbide [SiC x (p)] layer and then annealed at 800-900 °C. Transmission electron microscopy reveals that the thin chemical oxide layer disappears upon thermal annealing up to 900 °C, leading to degraded surface passivation. We interpret this in terms of a chemical reaction between carbon atoms in the SiC x (p) layer and the adjacent chemical oxide layer. To prevent this reaction, an intrinsic silicon interlayer was introduced between the chemical oxide and the SiC x (p) layer. We show that this intrinsic silicon interlayer is beneficial for surface passivation. Optimized passivation is obtained with a 10-nm-thick intrinsic silicon interlayer, yielding an emitter saturation current density of 17 fA cm -2 on p-type wafers, which translates into an implied open-circuit voltage of 708 mV. The potential of the developed contact at the rear side is further investigated by realizing a proof-of-concept hybrid solar cell, featuring a heterojunction front-side contact made of intrinsic amorphous silicon and phosphorus-doped amorphous silicon. Even though the presented cells are limited by front-side reflection and front-side parasitic absorption, the obtained cell with a V oc of 694.7 mV, a FF of 79.1%, and an efficiency of 20.44% demonstrates the potential of the p + /p-wafer full-side-passivated rear-side scheme shown here.

  10. Fabrication and Modification of Nanoporous Silicon Particles

    Science.gov (United States)

    Ferrari, Mauro; Liu, Xuewu

    2010-01-01

    Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion

  11. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  12. Tungsten chemical vapor deposition characteristics using SiH4 in a single wafer system

    International Nuclear Information System (INIS)

    Rosler, R.S.; Mendonca, J.; Rice, M.J. Jr.

    1988-01-01

    Several workers have recently begun using silane as a high-rate, low-temperature alternative to hydrogen for the reduction of WF 6 in the chemical vapor deposition of W. The deposition and film characteristics of both selective and blanket W using this new chemistry are explored in a radiantly heated single wafer system using closed-loop temperature control with a thermocouple in direct contact with the backside of the wafer. Selective W deposition rates of up to 1.5 μm/min were measured over the temperature range 250--550 0 C with blanket W rates typically 2--5 x lower. Resistivity is in the 10--15 μΩcm range at 300 0 C for SiH 4 /WF 6 ratios of 0.2 to 1.0, while above 400 0 C the range is 7.5--8.5 μΩcm. Si content in the W films is quite low at 10 16 to 10 17 atoms/cm 3 . Adhesion to silicon is excellent at temperatures of 350 0 C and above. Selective W using SiH 4 reduction for doped silicon contact fill shows none of the consumption or encroachment problems common to H 2 reduction, although selectivity is more sensitive. Contact resistance for p + and n + silicon contacts are comparable to aluminum controls and to previously published data. Blanket deposition into narrow geometries gives ≥0% step coverage and without keyholes in the 250--450 0 C deposition temperature range. For low-SiH 4 flows, deposition at 500 0 C causes small keyholes, while at 550 0 C even larger keyholes result. At higher SiH 4 flows, keyholes are typically not seen from 250 to 550 0 C

  13. Doping of silicon by carbon during laser ablation process

    Science.gov (United States)

    Raciukaitis, G.; Brikas, M.; Kazlauskiene, V.; Miskinis, J.

    2007-04-01

    Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

  14. Doping of silicon by carbon during laser ablation process

    International Nuclear Information System (INIS)

    Raciukaitis, G; Brikas, M; Kazlauskiene, V; Miskinis, J

    2007-01-01

    Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting

  15. Atomic and electronic structures of novel silicon surface structures

    Energy Technology Data Exchange (ETDEWEB)

    Terry, J.H. Jr.

    1997-03-01

    The modification of silicon surfaces is presently of great interest to the semiconductor device community. Three distinct areas are the subject of inquiry: first, modification of the silicon electronic structure; second, passivation of the silicon surface; and third, functionalization of the silicon surface. It is believed that surface modification of these types will lead to useful electronic devices by pairing these modified surfaces with traditional silicon device technology. Therefore, silicon wafers with modified electronic structure (light-emitting porous silicon), passivated surfaces (H-Si(111), Cl-Si(111), Alkyl-Si(111)), and functionalized surfaces (Alkyl-Si(111)) have been studied in order to determine the fundamental properties of surface geometry and electronic structure using synchrotron radiation-based techniques.

  16. Silicon photonics: some remaining challenges

    Science.gov (United States)

    Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

    2016-03-01

    This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

  17. Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

    Directory of Open Access Journals (Sweden)

    Kwang Hong Lee

    2015-01-01

    Full Text Available A method to remove the misfit dislocations and reduce the threading dislocations density (TDD in the germanium (Ge epilayer growth on a silicon (Si substrate is presented. The Ge epitaxial film is grown directly on the Si (001 donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001 handle wafer to form a germanium-on-insulator (GOI substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

  18. Porous silicon: Synthesis and optical properties

    International Nuclear Information System (INIS)

    Naddaf, M.; Awad, F.

    2006-01-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  19. Porous silicon: Synthesis and optical properties

    International Nuclear Information System (INIS)

    Naddaf, M.; Awad, F.

    2006-06-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  20. Chemical strategies for modifications of the solar cell process, from wafering to emitter diffusion; Chemische Ansaetze zur Neuordnung des Solarzellenprozesses ausgehend vom Wafering bis hin zur Emitterdiffusion

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, Kuno

    2009-11-06

    The paper describes the classic standard industrial solar cell based on monocrystalline silicon and describes new methods of fabrication. The first is an alternative wafering concept using laser microjet cutting instead of multiwire cutting. This method originally uses pure, deionized water; it was modified so that the liquid jet will not only be a liquid light conductor but also a transport medium for etching fluids supporting thermal abrasion of silicon by the laser jet. Two etching fluids were tested experimentally; it was found that water-free fluids based on perfluorinated solvents with very slight additions of gaseous chlorine are superior to all other options. In the second section, the wet chemical process steps between wafering and emitter diffusion (i.e. the first high-temperature step) was to be modified. Alternatives to 2-propanol were to be found in the experimental part. Purification after texturing was to be rationalized in order to reduce the process cost, either by using less chemical substances or by achieving shorter process times. 1-pentanol and p-toluolsulfonic acid were identified as two potential alternatives to 2-propanol as texture additives. Finally, it could be shown that wire-cut substrates processed with the new texturing agents have higher mechanical stabilities than substrates used with the classic texturing agent 2-propanol. [German] Im ersten Kapitel wird die klassische Standard-Industrie-Solarzelle auf der Basis monokristallinen Siliziums vorgestellt. Der bisherige Herstellungsprozess der Standard-Industrie-Solarzelle, der in wesentlichen Teilen darauf abzielt, diese Verluste zu minimieren, dient als Referenz fuer die Entwicklung neuer Fertigungsverfahren, wie sie in dieser Arbeit vorgestellt werden. Den ersten thematischen Schwerpunkt bildet die Entwicklung eines alternativen Wafering-Konzeptes zum Multi-Drahtsaegen. Die Basis des neuen, hier vorgestellten Wafering-Prozesses bildet das Laser-Micro-Jet-Verfahren. Dieses System

  1. Silicon heterojunction solar cells with novel fluorinated n-type nanocrystalline silicon oxide emitters on p-type crystalline silicon

    Science.gov (United States)

    Dhar, Sukanta; Mandal, Sourav; Das, Gourab; Mukhopadhyay, Sumita; Pratim Ray, Partha; Banerjee, Chandan; Barua, Asok Kumar

    2015-08-01

    A novel fluorinated phosphorus doped silicon oxide based nanocrystalline material have been used to prepare heterojunction solar cells on flat p-type crystalline silicon (c-Si) Czochralski (CZ) wafers. The n-type nc-SiO:F:H material were deposited by radio frequency plasma enhanced chemical vapor deposition. Deposited films were characterized in detail by using atomic force microscopy (AFM), high resolution transmission electron microscopy (HRTEM), Raman, fourier transform infrared spectroscopy (FTIR) and optoelectronics properties have been studied using temperature dependent conductivity measurement, Ellipsometry, UV-vis spectrum analysis etc. It is observed that the cell fabricated with fluorinated silicon oxide emitter showing higher initial efficiency (η = 15.64%, Jsc = 32.10 mA/cm2, Voc = 0.630 V, FF = 0.77) for 1 cm2 cell area compare to conventional n-a-Si:H emitter (14.73%) on flat c-Si wafer. These results indicate that n type nc-SiO:F:H material is a promising candidate for heterojunction solar cell on p-type crystalline wafers. The high Jsc value is associated with excellent quantum efficiencies at short wavelengths (<500 nm).

  2. Polish energy-system modernisation

    International Nuclear Information System (INIS)

    Drozdz, M.

    2003-01-01

    The Polish energy-system needs intensive investments in new technologies, which are energy efficient, clean and cost effective. Since the early 1990s, the Polish economy has had practically full access to modern technological devices, equipment and technologies. Introducing new technologies is a difficult task for project teams, constructors and investors. The author presents a set of principles for project teams useful in planning and energy modernisation. Several essential features are discussed: Energy-efficient appliances and systems; Choice of energy carriers, media and fuels; Optimal tariffs, maximum power and installed power; Intelligent, integrated, steering systems; Waste-energy recovery; Renewable-energy recovery. In practice there are several difficulties connected with planning and realising good technological and economic solutions. The author presents his own experiences of energy-system modernisation of industrial processes and building new objects. (Author)

  3. Energy savings in Polish buildings

    Energy Technology Data Exchange (ETDEWEB)

    Markel, L.C.; Gula, A.; Reeves, G.

    1995-12-31

    A demonstration of low-cost insulation and weatherization techniques was a part of phase 1 of the Krakow Clean Fossil Fuels and Energy Efficient Project. The objectives were to identify a cost-effective set of measures to reduce energy used for space heating, determine how much energy could be saved, and foster widespread implementation of those measures. The demonstration project focused on 4 11-story buildings in a Krakow housing cooperative. Energy savings of over 20% were obtained. Most important, the procedures and materials implemented in the demonstration project have been adapted to Polish conditions and applied to other housing cooperatives, schools, and hospitals. Additional projects are being planned, in Krakow and other cities, under the direction of FEWE-Krakow, the Polish Energie Cities Network, and Biuro Rozwoju Krakowa.

  4. SAFETY PLATFORM OF POLISH TRANSPORT

    Directory of Open Access Journals (Sweden)

    Katarzyna CHRUZIK

    2016-03-01

    Full Text Available Analyzing the level of Polish transport safety culture can be seen that it is now dependent on the culture of safety management within the organization and the requirements and recommendations of law in this field for different modes of transport (air, rail, road, water. Of the four basic types of transport requirements are widely developed in the aviation, rail, and water – the sea. In order to harmonize the requirements for transport safety so it appears advisable to develop a platform for exchange of safety information for different modes of transport, and the development of good practices multimodal offering the possibility of improving Polish transport safety. Described in the publication of the proposal in addition to the alignment platform experience and knowledge in the field of transport safety in all its kinds, it can also be a tool for perfecting new operators of public transport.

  5. Polishing compound for plastic surfaces

    Science.gov (United States)

    Stowell, M.S.

    1991-01-01

    This invention is comprised of a polishing compound for plastic materials. The compound includes approximately by approximately by weight 25 to 80 parts at least one petroleum distillate lubricant, 1 to 12 parts mineral spirits, 50 to 155 parts abrasive paste, and 15 to 60 parts water. Preferably, the compound includes approximately 37 to 42 parts at least one petroleum distillate lubricant, up to 8 parts mineral spirits, 95 to 110 parts abrasive paste, and 50 to 55 parts water. The proportions of the ingredients are varied in accordance with the particular application. The compound is used on PLEXIGLAS{trademark}, LEXAN{trademark}, LUCITE{trademark}, polyvinyl chloride (PVC), and similar plastic materials whenever a smooth, clear polished surface is desired.

  6. Effect of potential steps on porous silicon formation

    International Nuclear Information System (INIS)

    Cheng Xuan; Feng Zude; Luo Guangfeng

    2003-01-01

    Porous silicon microstructures were fabricated by applying potential steps through which both anodic and cathodic potentials were periodically applied to silicon wafers. The electrochemical behaviors of porous silicon layers were examined by performing polarization measurements, followed by analyzing the open-circuit potential (E ocp ) and the reaction rate in terms of corrosion current density (j corr ). The surface morphologies and surface products of porous silicon were characterized by scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). It was found that the values of E ocp and j corr varied more significantly and irregularly during different polarization stages when the potentials were continuously applied to the wafer surface, while virtually unchanged after 2 min of periodic potential application. In addition, slower reaction rates were observed with applying potential steps, as indicated by smaller values of j corr . The enhancement on refreshment of silicon surfaces by periodic potential polarization significantly accelerated the growth of porous silicon. The microstructures became more uniformed and better defined due to the improved passivating nature of wafer surfaces

  7. Pulsed Laser Interactions with Silicon Nano structures in Emitter Formation

    International Nuclear Information System (INIS)

    Huat, V.L.C.; Leong, C.S.; Kamaruzzaman Sopian, Saleem Hussain Zaidi

    2015-01-01

    Silicon wafer thinning is now approaching fundamental limits for wafer thickness owing to thermal expansion mismatch between Al and Si, reduced yields in wet-chemical processing as a result of fragility, and reduced optical absorption. An alternate manufacturing approach is needed to eliminate current manufacturing issues. In recent years, pulsed lasers have become readily available and costs have been significantly reduced. Pulsed laser interactions with silicon, in terms of micromachining, diffusions, and edge isolation, are well known, and have become industrial manufacturing tools. In this paper, pulsed laser interactions with silicon nano structures were identified as the most desirable solution for the fundamental limitations discussed above. Silicon nano structures have the capability for extremely high absorption that significantly reduces requirements for laser power, as well as thermal shock to the thinner wafer. Laser-assisted crystallization, in the presence of doping materials, leads to nano structure profiles that are highly desirable for sunlight absorption. The objective of this paper is the replacement of high temperature POCl_3 diffusion by laser-assisted phosphorus layers. With these improvements, complete low-temperature processing of thinner wafers was achievable with 3.7 % efficiency. Two-dimensional laser scanning was proved to be able to form uniformly annealed surfaces with higher fill factor and open-circuit voltage. (author)

  8. Quality Tests of Double-Sided Silicon Strip Detectors

    CERN Document Server

    Cambon, T; CERN. Geneva; Fintz, P; Guillaume, G; Jundt, F; Kuhn, C; Lutz, Jean Robert; Pagès, P; Pozdniakov, S; Rami, F; Sparavec, K; Dulinski, W; Arnold, L

    1997-01-01

    The quality of the SiO2 insulator (AC coupling between metal and implanted strips) of double-sided Silicon strip detectors has been studied by using a probe station. Some tests performed on 23 wafers are described and the results are discussed. Remark This note seems to cause problems with ghostview but it can be printed without any problem.

  9. Surface Roughness, Microhardness, and Microleakage of a Silorane-Based Composite Resin after Immediate or Delayed Finishing/Polishing

    Directory of Open Access Journals (Sweden)

    Fernanda Carvalho Rezende Lins

    2016-01-01

    Full Text Available Objective. This study evaluated the effect of immediate or delayed finishing/polishing using different systems on the surface roughness, hardness, and microleakage of a silorane-based composite. Material and Methods. Specimens were made with silorane-based composite (Filtek P90, 3M ESPE and assigned to the treatments: control (light-cured; aluminum oxide discs (Sof-Lex, 3M ESPE; diamond-impregnated silicone tips (Astropol, Ivoclar Vivadent; aluminum oxide-impregnated silicone tips (Enhance, Dentsply. Half of the specimens were finished/polished immediately and the rest after 7 days. Surface roughness (Ra, μm; n=20 and Vickers microhardness (50 g; 45 s; n=10 were measured. Cavities were prepared in bovine incisors and filled with Filtek P90. The fillings received immediate or delayed finishing/polishing (n=10 and were subjected to dye penetration test (0.5% basic fuchsin, 24 h. Data were analyzed by ANOVA and Scheffe, Kruskal-Wallis, and Mann-Whitney tests (p<0.05. Results. The finishing/polishing system significantly influenced roughness and microhardness (p<0.0001. For enamel, microleakage was not affected by the finishing/polishing system (p=0.309. For dentin, Sof-Lex discs and Astropol points promoted greater microleakage than Enhance points (p=0.033. Conclusion. Considering roughness, microhardness, and microleakage together, immediate finishing/polishing of a silorane-based composite using aluminum oxide discs may be recommended.

  10. Efficiency Enhancement of Silicon Solar Cells by Porous Silicon Technology

    Directory of Open Access Journals (Sweden)

    Eugenijus SHATKOVSKIS

    2012-09-01

    Full Text Available Silicon solar cells produced by a usual technology in p-type, crystalline silicon wafer were investigated. The manufactured solar cells were of total thickness 450 mm, the junction depth was of 0.5 mm – 0.7 mm. Porous silicon technologies were adapted to enhance cell efficiency. The production of porous silicon layer was carried out in HF: ethanol = 1 : 2 volume ratio electrolytes, illuminating by 50 W halogen lamps at the time of processing. The etching current was computer-controlled in the limits of (6 ÷ 14 mA/cm2, etching time was set in the interval of (10 ÷ 20 s. The characteristics and performance of the solar cells samples was carried out illuminating by Xenon 5000 K lamp light. Current-voltage characteristic studies have shown that porous silicon structures produced affect the extent of dark and lighting parameters of the samples. Exactly it affects current-voltage characteristic and serial resistance of the cells. It has shown, the formation of porous silicon structure causes an increase in the electric power created of solar cell. Conversion efficiency increases also respectively to the initial efficiency of cell. Increase of solar cell maximum power in 15 or even more percent is found. The highest increase in power have been observed in the spectral range of Dl @ (450 ÷ 850 nm, where ~ 60 % of the A1.5 spectra solar energy is located. It has been demonstrated that porous silicon technology is effective tool to improve the silicon solar cells performance.DOI: http://dx.doi.org/10.5755/j01.ms.18.3.2428

  11. Careers of young Polish chemists

    OpenAIRE

    Kosmulski, Marek

    2014-01-01

    Typical young Polish scientist is an alumnus of doctoral studies at the same university and department where he/she completed his/her Master degree. The career is continued by receiving a habilitation at the same university and department. Then a holder of habilitation is promoted to a tenured position at the same university and department. Detailed analysis of scientific careers of 154 recent Ph.D. recipients and of 16 habilitation candidates in chemistry from University of Warsaw is present...

  12. The silicon vertex tracker for star and future applications of silicon drift detectors

    International Nuclear Information System (INIS)

    Bellwied, Rene

    2001-01-01

    The Silicon Vertex Tracker (SVT) for the STAR experiment at the Relativistic Heavy Ion Collider at Brookhaven National Laboratory has recently been completed and installed. First data were taken in July 2001. The SVT is based on a novel semi-conductor technology called Silicon Drift Detectors. 216 large area (6 by 6 cm) Silicon wafers were employed to build a three barrel device capable of vertexing and tracking in a high occupancy environment. Its intrinsic radiation hardness, its operation at room temperature and its excellent position resolution (better than 20 micron) in two dimensions with a one dimensional detector readout, make this technology very robust and inexpensive and thus a viable alternative to CCD, Silicon pixel and Silicon strip detectors in a variety of applications from fundamental research in high-energy and nuclear physics to astrophysics to medical imaging. I will describe the development that led to the STAR-SVT, its performance and possible applications for the near future

  13. Dislocation behavior of surface-oxygen-concentration controlled Si wafers

    International Nuclear Information System (INIS)

    Asazu, Hirotada; Takeuchi, Shotaro; Sannai, Hiroya; Sudo, Haruo; Araki, Koji; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira

    2014-01-01

    We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer. - Highlights: • Surface-oxygen-concentration controlled Si wafers have been made. • The oxygen concentration was controlled by high temperature rapid thermal oxidation. • Dislocation behavior in the surface area of the Si wafers has been investigated. • Rosette size decreased with increasing of interstitial oxygen atoms. • The interstitial oxygen atoms have a pinning effect of dislocations at the surface

  14. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  15. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    Science.gov (United States)

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  16. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  17. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  18. 19th Polish Control Conference

    CERN Document Server

    Kacprzyk, Janusz; Oprzędkiewicz, Krzysztof; Skruch, Paweł

    2017-01-01

    This volume contains the proceedings of the KKA 2017 – the 19th Polish Control Conference, organized by the Department of Automatics and Biomedical Engineering, AGH University of Science and Technology in Kraków, Poland on June 18–21, 2017, under the auspices of the Committee on Automatic Control and Robotics of the Polish Academy of Sciences, and the Commission for Engineering Sciences of the Polish Academy of Arts and Sciences. Part 1 deals with general issues of modeling and control, notably flow modeling and control, sliding mode, predictive, dual, etc. control. In turn, Part 2 focuses on optimization, estimation and prediction for control. Part 3 is concerned with autonomous vehicles, while Part 4 addresses applications. Part 5 discusses computer methods in control, and Part 6 examines fractional order calculus in the modeling and control of dynamic systems. Part 7 focuses on modern robotics. Part 8 deals with modeling and identification, while Part 9 deals with problems related to security, fault ...

  19. Silicon fabric for multi-functional applications

    KAUST Repository

    Sevilla, Galo T.; Rojas, Jhonathan Prieto; Ahmed, Sally; Hussain, Aftab M.; Inayat, Salman Bin; Hussain, Muhammad Mustafa

    2013-01-01

    This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

  20. Silicon fabric for multi-functional applications

    KAUST Repository

    Sevilla, Galo T.

    2013-06-01

    This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

  1. Microelectronic temperature sensor; silicon temperature sensor

    International Nuclear Information System (INIS)

    Beitner, M.; Kanert, W.; Reichert, H.

    1982-01-01

    The goal of this work was to develop a silicon temperature sensor with a sensitivity and a reliability as high and a tolerance as small as possible, for use in measurement and control. By employing the principle of spreading-resistance, using silicon doped by neutron transmutation, and trimming of the single wafer tolerances of resistance less than +- 5% can be obtained; overstress tests yielded a long-term stability better than 0.2%. Some applications show the advantageous use of this sensor. (orig.) [de

  2. Performance characteristics and radiation damage results from the Fermilab E706 silicon microstrip detector system

    Energy Technology Data Exchange (ETDEWEB)

    Engels, E Jr; Mani, S; Orris, D; Shepard, P F; Weerasundara, P D; Choudhary, B C; Joshi, U; Kapoor, V; Shivpuri, R; Baker, W

    1989-07-01

    A charged particle spectrometer containing a 7120-channel silicon microstrip detector system, one component of Fermilab experiment E706 to study direct photon production in hadron-hadron collisions, was utilized in a run in which 6 million events were recorded. We describe the silicon system, provide early results of track and vertex reconstruction, and present data on the radiation damage to the silicon wafers resulting from the narrow high intensity beam. (orig.).

  3. Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

    Science.gov (United States)

    Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Chattopadhyay, Goutam (Inventor); Perez, Jose Vicente Siles (Inventor); Lin, Robert H. (Inventor); Mehdi, Imran (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Peralta, Alejandro (Inventor)

    2016-01-01

    A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

  4. Fabrication of micromirrors with pyramidal shape using anisotropic etching of silicon

    OpenAIRE

    Moktadir, Z.; Vijaya Prakash, G.; Trupke, M.; Koukharenko, E.; Kraft, M.; Baumberg, J.J.; Eriksson, S.; Hinds, E.A.

    2005-01-01

    Gold micro-mirrors have been formed in silicon in an inverted pyramidal shape. The pyramidal structures are created in the (100) surface of a silicon wafer by anisotropic etching in potassium hydroxide. High quality micro-mirrors are then formed by sputtering gold onto the smooth silicon (111) faces of the pyramids. These mirrors show great promise as high quality optical devices suitable for integration into MOEMS systems.

  5. Combination of gettering and etching in multicrystalline silicon used in solar cells processing

    International Nuclear Information System (INIS)

    Dimassi, W.; Bouaicha, M.; Nouri, H.; Ben Nasrallah, S.; Bessais, B.

    2006-01-01

    Undesired impurities can be removed away from multicrystalline silicon (mc-Si) wafers by combining porous silicon (PS) formation and heat treatments. The gettering procedure used in this work is based on the formation of a PS film at both back and front sides of the mc-Si wafers, followed by a heat treatment. The latter was achieved in an infrared furnace at different temperatures and during various periods. We show that when the based material undergoes such a gettering, the electrical properties (short-circuit current, open-circuit voltage, serial and shunt resistances) and the electronic parameters (diffusion length and grain boundary recombination velocity) of the corresponding solar cells can be improved only if some regions of the wafers are etched. Compared to reference cells based on untreated wafers, the diffusion length and grain boundary recombination velocity of solar cells fabricated from gettered and etched samples was improved by about 30% and reduced by a factor of 10, respectively

  6. Numerical simulation of signals of photothermal radiometry in silicon monocrystals; Simulacion numerica de senales de radiometria fototermica en mono cristales de silicio

    Energy Technology Data Exchange (ETDEWEB)

    Campos C, I. [Facultad de Ciencias, Universidad Autonoma de San Luis Potosi, 78000 San Luis Potosi (Mexico); Rodriguez, M.E. [Fisica Aplicada y Tecnologia Avanzada, Universidad Nacional Autonoma de Mexico, 76000 Juriquilla, Queretaro (Mexico); Ruiz, F. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Av. Carranza 2425-A, 78210 San Luis Potosi (Mexico)

    2002-07-01

    By using the theoretical model proposed by Mandelis et al. and a numerical simulations. We have analysed the generation of photoinduced black body radiation (photothermal radiometry signal) on monocrystalline silicon wafers. We report the particular role of each one of the main parameters involved on the photothermal signal. The parameter values were taken of the reported values for industrial silicon wafers. We show a discuss the obtained results. (Author)

  7. Silicon-micromachined microchannel plates

    International Nuclear Information System (INIS)

    Beetz, Charles P.; Boerstler, Robert; Steinbeck, John; Lemieux, Bryan; Winn, David R.

    2000-01-01

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of ∼0.5 to ∼25 μm, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposited or nucleated in the channels or the first strike surface. Results on resistivity, secondary emission and gain are presented

  8. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  9. Tribochemical interaction between nanoparticles and surfaces of selective layer during chemical mechanical polishing

    International Nuclear Information System (INIS)

    Ilie, Filip

    2013-01-01

    Nanoparticles have been widely used in polish slurries such as those in the chemical mechanical polishing (CMP) process. For understanding the mechanisms of CMP, an atomic force microscope (AFM) is used to characterize polished surfaces of selective layers, after a set of polishing experiments. To optimize the CMP polishing process, one needs to get information on the interaction between the nano-abrasive slurry nanoparticles and the surface of selective layer being polished. The slurry used in CMP process of the solid surfaces is slurry with large nanoparticle size colloidal silica sol nano-abrasives. Silica sol nano-abrasives with large nanoparticle are prepared and characterized by transmission electron microscopy, particles colloidal size, and Zeta potential in this paper. The movement of nanoparticles in liquid and the interaction between nanoparticles and solid surfaces coating with selective layer are very important to obtain an atomic alloy smooth surface in the CMP process. We investigate the nanoparticle adhesion and removal processes during CMP and post-CMP cleaning. The mechanical interaction between nanoparticles and the wafer surface was studied using a microcontact wear model. This model considers the nanoparticle effects between the polishing interfaces during load balancing. Experimental results on polishing and cleaning are compared with numerical analysis. This paper suggests that during post-CMP cleaning, a combined effort in chemical and mechanical interaction (tribochemical interactions) would be effective in removal of small nanoparticles during cleaning. For large nanoparticles, more mechanical forces would be more effective. CMP results show that the removal rate has been improved to 367 nm/min and root mean square (RMS) of roughness has been reduced from 4.4 to 0.80 nm. Also, the results show that the silica sol nano-abrasives about 100 nm are of higher stability (Zeta potential is −65 mV) and narrow distribution of nanoparticle

  10. Integrated optical MEMS using through-wafer vias and bump-bonding.

    Energy Technology Data Exchange (ETDEWEB)

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  11. Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

    Science.gov (United States)

    Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

    2018-05-01

    Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

  12. Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

    Directory of Open Access Journals (Sweden)

    Zhiwei Zhang

    2018-05-01

    Full Text Available Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young’s modulus, ultimate tensile strength (UTS, and strain at fracture is observed.

  13. Formation and properties of porous silicon layers

    International Nuclear Information System (INIS)

    Vitanov, P.; Kamenova, M.; Dimova-Malinovska, D.

    1993-01-01

    Preparation, properties and application of porous silicon films are investigated. Porous silicon structures were formed by an electrochemical etching process resulting in selective dissolution of the silicon substrate. The silicon wafers used with a resistivity of 5-10Ω.cm were doped with B to concentrations 6x10 18 -1x10 19 Ω.cm -3 in the temperature region 950 o C-1050 o C. The density of each porous films was determined from the weight loss during the anodization and it depends on the surface resistivity of the Si wafer. The density decreases with decreasing of the surface resistivity. The surface of the porous silicon layers was studied by X-ray photoelectron spectroscopy which indicates the presence of SiF 4 . The kinetic dependence of the anode potential and the porous layer thickness on the time of anodization in a galvanostatic regime for the electrolytes with various HF concentration were studied. In order to compare the properties of the resulting porous layers and to establish the dependence of the porosity on the electrolyte, three types of electrolytes were used: concentrated HF, diluted HF:H 2 O=1:1 and ethanol-hydrofluoric solutions HF:C 2 H 5 OH:H 2 O=2:1:1. High quality uniform and reproducible layers were formed using aqueous-ethanol-hydrofluoric electrolyte. Both Kikuchi's line and ring patterns were observed by TEM. The porous silicon layer was single crystal with the same orientation as the substrate. The surface shows a polycrystalline structure only. The porous silicon layers exhibit visible photoluminescence (PL) at room temperature under 480 nm Ar + laser line excitation. The peak of PL was observed at about 730 nm with FWHM about 90 nm. Photodiodes was made with a W-porous silicon junction. The current voltage and capacity voltage characteristics were similar to those of an isotype heterojunction diode. (orig.)

  14. Improved surface quality of anisotropically etched silicon {111} planes for mm-scale optics

    International Nuclear Information System (INIS)

    Cotter, J P; Hinds, E A; Zeimpekis, I; Kraft, M

    2013-01-01

    We have studied the surface quality of millimetre-scale optical mirrors produced by etching CZ and FZ silicon wafers in potassium hydroxide to expose the {111} planes. We find that the FZ surfaces have four times lower noise power at spatial frequencies up to 500 mm −1 . We conclude that mirrors made using FZ wafers have higher optical quality. (technical note)

  15. The tourism attractiveness of Polish libraries

    OpenAIRE

    Miedzińska, Magdalena; Tanaś, Sławoj

    2009-01-01

    The aim of the article is to draw the reader's attention to the tourism attractiveness of renowned Polish libraries. These have attained a tourism function due to tourism exploration and penetration, but remain in the shadow of other Polish cultural assets. The article outlines the historical geography of Polish libraries, an analysis of tourism assets and an attempt to classify and catalogue libraries in Poland.

  16. development and evaluation of lyophilized thiolated-chitosan wafers

    African Journals Online (AJOL)

    User

    THIOLATED-CHITOSAN WAFERS FOR BUCCAL DELIVERY. OF PROTEIN ... of the thiolated polymer incorporating per polymer weight, 10 % each of glycerol as plasticizer, D-mannitol as ..... delivery systems: in vitro stability, in vivo fate, and ...

  17. Enhanced light emission in photonic crystal nanocavities with Erbium-doped silicon nanocrystals

    International Nuclear Information System (INIS)

    Makarova, Maria; Sih, Vanessa; Vuckovic, Jelena; Warga, Joe; Li Rui; Dal Negro, Luca

    2008-01-01

    Photonic crystal nanocavities are fabricated in silicon membranes covered by thermally annealed silicon-rich nitride films with Erbium-doped silicon nanocrystals. Silicon nitride films were deposited by sputtering on top of silicon on insulator wafers. The nanocavities were carefully designed in order to enhance emission from the nanocrystal sensitized Erbium at the 1540 nm wavelength. Experimentally measured quality factors of ∼6000 were found to be consistent theoretical predictions. The Purcell factor of 1.4 was estimated from the observed 20-fold enhancement of Erbium luminescence

  18. Automated reticle inspection data analysis for wafer fabs

    Science.gov (United States)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  19. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  20. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Science.gov (United States)

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.