Radiation evaluation of commercial ferroelectric nonvolatile memories

International Nuclear Information System (INIS)

Benedetto, J.M.; DeLancey, W.M.; Oldham, T.R.; McGarrity, J.M.; Tipton, C.W.; Brassington, M.; Fisch, D.E.

1991-01-01

This paper reports on ferroelectric (FE) on complementary metal-oxide semiconductor (CMOS) 4-kbit nonvolatile memories, 8-bit octal latches (with and without FE), and process control test chips that were used to establish a baseline characterization of the radiation response of CMOS/FE integrated devices and to determine whether the additional FE processing caused significant degradation to the baseline CMOS process. Functional failure of all 4-kbit memories and octal latches occurred at total doses of between 2 and 4 krad(Si), most likely due to field- oxide effects in the underlying CMOS. No significant difference was observed between the radiation responses of devices with and without the FE film in this commercial process

Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template

International Nuclear Information System (INIS)

Miura, Atsushi; Yamashita, Ichiro; Uraoka, Yukiharu; Fuyuki, Takashi; Tsukamoto, Rikako; Yoshii, Shigeo

2008-01-01

We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co 3 O 4 ) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented

A memristor-based nonvolatile latch circuit

International Nuclear Information System (INIS)

Robinett, Warren; Pickett, Matthew; Borghetti, Julien; Xia Qiangfei; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2010-01-01

Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

Fabrication and operation methods of a one-time programmable (OTP) nonvolatile memory (NVM) based on a metal-oxide-semiconductor structure

International Nuclear Information System (INIS)

Cho, Seongjae; Lee, Junghoon; Jung, Sunghun; Park, Sehwan; Park, Byunggook

2011-01-01

In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array based on a metal-insulator-semiconductor (MIS) structure is proposed. The Iindividual memory device has a vertical channel of a silicon diode. Historically, OTP memories were widely used for read-only-memories (ROMs), in which the most basic system architecture model was to store central processing unit (CPU) instructions. By grafting the nanoscale fabrication technology and novel structuring onto the concept of the OTP memory, innovative high-density NVM appliances for mobile storage media may be possible. The program operation is performed by breaking down the thin oxide layer between the pn diode structure and the wordline (WL). The programmed state can be identified by an operation that reads the leakage currents through the broken oxide. Since the proposed OTP NVM is based on neither a transistor structure nor a charge storing mechanism, it is highly reliable and functional for realizing the ultra-large scale integration. The operation physics and the fabrication processes are also explained in detail.

Nonvolatile memory design magnetic, resistive, and phase change

CERN Document Server

Li, Hai

2011-01-01

The manufacture of flash memory, which is the dominant nonvolatile memory technology, is facing severe technical barriers. So much so, that some emerging technologies have been proposed as alternatives to flash memory in the nano-regime. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing introduces three promising candidates: phase-change memory, magnetic random access memory, and resistive random access memory. The text illustrates the fundamental storage mechanism of these technologies and examines their differences from flash memory techniques. Based on the latest advances,

Carbon nanomaterials for non-volatile memories

Science.gov (United States)

Ahn, Ethan C.; Wong, H.-S. Philip; Pop, Eric

2018-03-01

Carbon can create various low-dimensional nanostructures with remarkable electronic, optical, mechanical and thermal properties. These features make carbon nanomaterials especially interesting for next-generation memory and storage devices, such as resistive random access memory, phase-change memory, spin-transfer-torque magnetic random access memory and ferroelectric random access memory. Non-volatile memories greatly benefit from the use of carbon nanomaterials in terms of bit density and energy efficiency. In this Review, we discuss sp2-hybridized carbon-based low-dimensional nanostructures, such as fullerene, carbon nanotubes and graphene, in the context of non-volatile memory devices and architectures. Applications of carbon nanomaterials as memory electrodes, interfacial engineering layers, resistive-switching media, and scalable, high-performance memory selectors are investigated. Finally, we compare the different memory technologies in terms of writing energy and time, and highlight major challenges in the manufacturing, integration and understanding of the physical mechanisms and material properties.

Nonvolatile Rad-Hard Holographic Memory

Science.gov (United States)

Chao, Tien-Hsin; Zhou, Han-Ying; Reyes, George; Dragoi, Danut; Hanna, Jay

2001-01-01

We are investigating a nonvolatile radiation-hardened (rad-hard) holographic memory technology. Recently, a compact holographic data storage (CHDS) breadboard utilizing an innovative electro-optic scanner has been built and demonstrated for high-speed holographic data storage and retrieval. The successful integration of this holographic memory breadboard has paved the way for follow-on radiation resistance test of the photorefractive (PR) crystal, Fe:LiNbO3. We have also started the investigation of using two-photon PR crystals that are doubly doped with atoms of iron group (Ti, Cr, Mn, Cu) and of rare-earth group (Nd, Tb) for nonvolatile holographic recordings.

Method for refreshing a non-volatile memory

Science.gov (United States)

Riekels, James E.; Schlesinger, Samuel

2008-11-04

A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

Nonvolatile Memory Technology for Space Applications

Science.gov (United States)

Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

2010-01-01

This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

Flexible graphene–PZT ferroelectric nonvolatile memory

International Nuclear Information System (INIS)

Lee, Wonho; Ahn, Jong-Hyun; Kahya, Orhan; Toh, Chee Tat; Özyilmaz, Barbaros

2013-01-01

We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr 0.35 ,Ti 0.65 )O 3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol–gel methods, respectively. Such PZT films show a high remnant polarization (P r ) of 30 μC cm −2 and a coercive voltage (V c ) of 3.5 V under a voltage loop over ±11 V. The graphene–PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits. (paper)

Flexible graphene-PZT ferroelectric nonvolatile memory.

Science.gov (United States)

Lee, Wonho; Kahya, Orhan; Toh, Chee Tat; Ozyilmaz, Barbaros; Ahn, Jong-Hyun

2013-11-29

We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr0.35,Ti0.65)O3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol–gel methods, respectively. Such PZT films show a high remnant polarization (Pr) of 30 μC cm−2 and a coercive voltage (Vc) of 3.5 V under a voltage loop over ±11 V. The graphene–PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Overview of emerging nonvolatile memory technologies.

Science.gov (United States)

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

Overview of emerging nonvolatile memory technologies

Science.gov (United States)

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

Electrostatically telescoping nanotube nonvolatile memory device

International Nuclear Information System (INIS)

Kang, Jeong Won; Jiang Qing

2007-01-01

We propose a nonvolatile memory based on carbon nanotubes (CNTs) serving as the key building blocks for molecular-scale computers and investigate the dynamic operations of a double-walled CNT memory element by classical molecular dynamics simulations. The localized potential energy wells achieved from both the interwall van der Waals energy and CNT-metal binding energy make the bistability of the CNT positions and the electrostatic attractive forces induced by the voltage differences lead to the reversibility of this CNT memory. The material for the electrodes should be carefully chosen to achieve the nonvolatility of this memory. The kinetic energy of the CNT shuttle experiences several rebounds induced by the collisions of the CNT onto the metal electrodes, and this is critically important to the performance of such an electrostatically telescoping CNT memory because the collision time is sufficiently long to cause a delay of the state transition

Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

KAUST Repository

Semple, James; Wyatt-Moon, Gwenhivir; Georgiadou, Dimitra G.; McLachlan, Martyn A.; Anthopoulos, Thomas D.

2017-01-01

Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

KAUST Repository

Semple, James

2017-01-02

Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

Organic Nonvolatile Memory Devices Based on Ferroelectricity

NARCIS (Netherlands)

Naber, Ronald C. G.; Asadi, Kamal; Blom, Paul W. M.; de Leeuw, Dago M.; de Boer, Bert

2010-01-01

A memory functionality is a prerequisite for many applications of electronic devices. Organic nonvolatile memory devices based on ferroelectricity are a promising approach toward the development of a low-cost memory technology. In this Review Article we discuss the latest developments in this area

Organic nonvolatile memory devices based on ferroelectricity

NARCIS (Netherlands)

Naber, R.C.G.; Asadi, K.; Blom, P.W.M.; Leeuw, D.M. de; Boer, B. de

2010-01-01

A memory functionality is a prerequisite for many applications of electronic devices. Organic nonvolatile memory devices based on ferroelectricity are a promising approach toward the development of a low-cost memory technology. In this Review Article we discuss the latest developments in this area

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

Energy Technology Data Exchange (ETDEWEB)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P. [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Chakraborty, S. [Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064 (India); Mukherjee, Rabibrata [Department of Chemical Engineering, Indian Institute of Technology, Kharagpur 721302 (India)

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

Active non-volatile memory post-processing

Energy Technology Data Exchange (ETDEWEB)

Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

2017-04-11

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

Phosphorene/ZnO Nano-Heterojunctions for Broadband Photonic Nonvolatile Memory Applications.

Science.gov (United States)

Hu, Liang; Yuan, Jun; Ren, Yi; Wang, Yan; Yang, Jia-Qin; Zhou, Ye; Zeng, Yu-Jia; Han, Su-Ting; Ruan, Shuangchen

2018-06-10

High-performance photonic nonvolatile memory combining photosensing and data storage with low power consumption ensures the energy efficiency of computer systems. This study first reports in situ derived phosphorene/ZnO hybrid heterojunction nanoparticles and their application in broadband-response photonic nonvolatile memory. The photonic nonvolatile memory consistently exhibits broadband response from ultraviolet (380 nm) to near infrared (785 nm), with controllable shifts of the SET voltage. The broadband resistive switching is attributed to the enhanced photon harvesting, a fast exciton separation, as well as the formation of an oxygen vacancy filament in the nano-heterojunction. In addition, the device exhibits an excellent stability under air exposure compared with reported pristine phosphorene-based nonvolatile memory. The superior antioxidation capacity is believed to originate from the fast transfer of lone-pair electrons of phosphorene. The unique assembly of phosphorene/ZnO nano-heterojunctions paves the way toward multifunctional broadband-response data-storage techniques. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

Science.gov (United States)

Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

2011-06-01

Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

Non-volatile memory based on the ferroelectric photovoltaic effect

Science.gov (United States)

Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

2013-01-01

The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

Physical principles and current status of emerging non-volatile solid state memories

Science.gov (United States)

Wang, L.; Yang, C.-H.; Wen, J.

2015-07-01

Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

Metal-organic molecular device for non-volatile memory storage

International Nuclear Information System (INIS)

Radha, B.; Sagade, Abhay A.; Kulkarni, G. U.

2014-01-01

Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organic complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.

Design exploration of emerging nano-scale non-volatile memory

CERN Document Server

Yu, Hao

2014-01-01

This book presents the latest techniques for characterization, modeling and design for nano-scale non-volatile memory (NVM) devices.  Coverage focuses on fundamental NVM device fabrication and characterization, internal state identification of memristic dynamics with physics modeling, NVM circuit design, and hybrid NVM memory system design-space optimization. The authors discuss design methodologies for nano-scale NVM devices from a circuits/systems perspective, including the general foundations for the fundamental memristic dynamics in NVM devices.  Coverage includes physical modeling, as well as the development of a platform to explore novel hybrid CMOS and NVM circuit and system design.   • Offers readers a systematic and comprehensive treatment of emerging nano-scale non-volatile memory (NVM) devices; • Focuses on the internal state of NVM memristic dynamics, novel NVM readout and memory cell circuit design, and hybrid NVM memory system optimization; • Provides both theoretical analysis and pr...

Channel equalization techniques for non-volatile memristor memories

KAUST Repository

Naous, Rawan

2016-03-16

Channel coding and information theoretic approaches have been utilized in conventional non-volatile memories to overcome their inherent design limitations of leakage, coupling and refresh rates. However, the continuous scaling and integration constraints set on the current devices directed the attention towards emerging memory technologies as suitable alternatives. Memristive devices are prominent candidates to replace the conventional electronics due to its non-volatility and small feature size. Nonetheless, memristor-based memories still encounter an accuracy limitation throughout the read operation addressed as the sneak path phenomenon. The readout data is corrupted with added distortion that increases significantly the bit error rate and jeopardizes the reliability of the read operation. A novel technique is applied to alleviate this distorting effect where the communication channel model is proposed for the memory array. Noise cancellation principles are applied with the aid of preset pilots to extract channel information and adjust the readout values accordingly. The proposed technique has the virtue of high speed, energy efficiency, and low complexity design while achieving high reliability and error-free decoding.

Channel equalization techniques for non-volatile memristor memories

KAUST Repository

Naous, Rawan; Zidan, Mohammed A.; Salem, Ahmed Sultan; Salama, Khaled N.

2016-01-01

Channel coding and information theoretic approaches have been utilized in conventional non-volatile memories to overcome their inherent design limitations of leakage, coupling and refresh rates. However, the continuous scaling and integration constraints set on the current devices directed the attention towards emerging memory technologies as suitable alternatives. Memristive devices are prominent candidates to replace the conventional electronics due to its non-volatility and small feature size. Nonetheless, memristor-based memories still encounter an accuracy limitation throughout the read operation addressed as the sneak path phenomenon. The readout data is corrupted with added distortion that increases significantly the bit error rate and jeopardizes the reliability of the read operation. A novel technique is applied to alleviate this distorting effect where the communication channel model is proposed for the memory array. Noise cancellation principles are applied with the aid of preset pilots to extract channel information and adjust the readout values accordingly. The proposed technique has the virtue of high speed, energy efficiency, and low complexity design while achieving high reliability and error-free decoding.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

International Nuclear Information System (INIS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-01-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

Energy Technology Data Exchange (ETDEWEB)

Jovanović, B., E-mail: bojan.jovanovic@lirmm.fr, E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L. [LIRMM—University of Montpellier 2/UMR CNRS 5506, 161 Rue Ada, 34095 Montpellier (France)

2014-04-07

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Role of Non-Volatile Memories in Automotive and IoT Markets

Science.gov (United States)

2017-03-01

Standard Manufacturing Supply Long Term Short to Medium Term Density Up to 16MB Up to 2MB IO Configuration Up to x128 Up to x32 Design for Test...Role of Non-Volatile Memories in Automotive and IoT Markets Vipin Tiwari Director, Business Development and Product Marketing SST – A Wholly Own...microcontrollers (MCU) and certainly one of the most challenging elements to master. This paper addresses the role of non-volatile memories for

Quasi-unipolar pentacene films embedded with fullerene for non-volatile organic transistor memories

Energy Technology Data Exchange (ETDEWEB)

Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung; Kang, Moon Sung, E-mail: mskang@ssu.ac.kr [Department of Chemical Engineering, Soongsil University, Seoul 156-743 (Korea, Republic of)

2015-02-09

Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while the electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.

Capacitance characteristics of metal-oxide-semiconductor capacitors with a single layer of embedded nickel nanoparticles for the application of nonvolatile memory

International Nuclear Information System (INIS)

Wei, Li; Ling, Xu; Wei-Ming, Zhao; Hong-Lin, Ding; Zhong-Yuan, Ma; Jun, Xu; Kun-Ji, Chen

2010-01-01

This paper reports that metal-oxide-semiconductor (MOS) capacitors with a single layer of Ni nanoparticles were successfully fabricated by using electron-beam evaporation and rapid thermal annealing for application to nonvolatile memory. Experimental scanning electron microscopy images showed that Ni nanoparticles of about 5 nm in diameter were clearly embedded in the SiO 2 layer on p-type Si (100). Capacitance–voltage measurements of the MOS capacitor show large flat-band voltage shifts of 1.8 V, which indicate the presence of charge storage in the nickel nanoparticles. In addition, the charge-retention characteristics of MOS capacitors with Ni nanoparticles were investigated by using capacitance–time measurements. The results showed that there was a decay of the capacitance embedded with Ni nanoparticles for an electron charge after 10 4 s. But only a slight decay of the capacitance originating from hole charging was observed. The present results indicate that this technique is promising for the efficient formation or insertion of metal nanoparticles inside MOS structures. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

International Nuclear Information System (INIS)

Wang Guangli; Chen Yubin; Shi Yi; Pu Lin; Pan Lijia; Zhang Rong; Zheng Youdou

2010-01-01

A novel two-step method is employed, for the first time, to fabricate nonvolatile memory devices that have metal nanocrystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concern for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method. (semiconductor devices)

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

International Nuclear Information System (INIS)

Ni Henan; Wu Liangcai; Song Zhitang; Hui Chun

2009-01-01

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO 2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time. (semiconductor devices)

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser; Bhansali, Unnat Sampatraj; Alshareef, Husam N.

2012-01-01

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

KAUST Repository

Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2015-01-01

Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

Directory of Open Access Journals (Sweden)

Mohamed T. Ghoneim

2015-07-01

Full Text Available Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT, the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

KAUST Repository

Ghoneim, Mohamed T.

2015-07-23

Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

The influence of thickness on memory characteristic based on nonvolatile tuning behavior in poly(N-vinylcarbazole) films

International Nuclear Information System (INIS)

Sun, Yanmei; Ai, Chunpeng; Lu, Junguo; Li, Lei; Wen, Dianzhong; Bai, Xuduo

2016-01-01

The memory characteristic based on nonvolatile tuning behavior in indium tin oxide/poly(N-vinylcarbazole)/aluminum (ITO/PVK/Al) was investigated, the different memory behaviors were first observed in PVK film as the film thickness changing. By control of PVK film thickness with different spinning speeds, the nonvolatile behavior of ITO/PVK/Al sandwich structure can be tuned in a controlled manner. Obviously different nonvolatile behaviors, such as (i) flash memory behavior and (ii) write-once-read-many times (WORM) memory behavior are from the current–voltage (I–V) characteristics of the PVK films. The results suggest that the film thickness plays a key part in determining the memory type of the PVK. - Highlights: • The different memory behaviors were observed in PVK film. • The nonvolatile behavior of ITO/PVK/Al sandwich structure can be tuned. • The film thickness plays a key part in determining the memory type of the PVK.

Large scale integration of flexible non-volatile, re-addressable memories using P(VDF-TrFE) and amorphous oxide transistors

International Nuclear Information System (INIS)

Gelinck, Gerwin H; Cobb, Brian; Van Breemen, Albert J J M; Myny, Kris

2015-01-01

Ferroelectric polymers and amorphous metal oxide semiconductors have emerged as important materials for re-programmable non-volatile memories and high-performance, flexible thin-film transistors, respectively. However, realizing sophisticated transistor memory arrays has proven to be a challenge, and demonstrating reliable writing to and reading from such a large scale memory has thus far not been demonstrated. Here, we report an integration of ferroelectric, P(VDF-TrFE), transistor memory arrays with thin-film circuitry that can address each individual memory element in that array. n-type indium gallium zinc oxide is used as the active channel material in both the memory and logic thin-film transistors. The maximum process temperature is 200 °C, allowing plastic films to be used as substrate material. The technology was scaled up to 150 mm wafer size, and offers good reproducibility, high device yield and low device variation. This forms the basis for successful demonstration of memory arrays, read and write circuitry, and the integration of these. (paper)

A review of emerging non-volatile memory (NVM) technologies and applications

Science.gov (United States)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

ZnO as dielectric for optically transparent non-volatile memory

International Nuclear Information System (INIS)

Salim, N. Tjitra; Aw, K.C.; Gao, W.; Wright, Bryon E.

2009-01-01

This paper discusses the application of a DC sputtered ZnO thin film as a dielectric in an optically transparent non-volatile memory. The main motivation for using ZnO as a dielectric is due to its optical transparency and mechanical flexibility. We have established the relationship between the electrical resistivity (ρ) and the activation energy (E a ) of the electron transport in the conduction band of the ZnO film. The ρ of 2 x 10 4 -5 x 10 7 Ω-cm corresponds to E a of 0.36-0.76 eV, respectively. The k-value and optical band-gap for films sputtered with Ar:O 2 ratio of 4:1 are 53 ± 3.6 and 3.23 eV, respectively. In this paper, the basic charge storage element for a non-volatile memory is a triple layer dielectric structure in which a 50 nm thick ZnO film is sandwiched between two layers of methyl silsesquioxane sol-gel dielectric of varying thickness. A pronounced clockwise capacitance-voltage (C-V) hysteresis was observed with a memory window of 6 V. The integration with a solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene resulted in an optically transparent organic field effect transistor non-volatile memory (OFET-NVM). We have demonstrated that this OFET-NVM can be electrically programmed and erased at low voltage (± 10 V) with a threshold voltage shift of 4.0 V.

Phase change materials in non-volatile storage

OpenAIRE

Ielmini, Daniele; Lacaita, Andrea L.

2011-01-01

After revolutionizing the technology of optical data storage, phase change materials are being adopted in non-volatile semiconductor memories. Their success in electronic storage is mostly due to the unique properties of the amorphous state where carrier transport phenomena and thermally-induced phase change cooperate to enable high-speed, low-voltage operation and stable data retention possible within the same material. This paper reviews the key physical properties that make this phase so s...

Overview of radiation effects on emerging non-volatile memory technologies

Directory of Open Access Journals (Sweden)

Fetahović Irfan S.

2017-01-01

Full Text Available In this paper we give an overview of radiation effects in emergent, non-volatile memory technologies. Investigations into radiation hardness of resistive random access memory, ferroelectric random access memory, magneto-resistive random access memory, and phase change memory are presented in cases where these memory devices were subjected to different types of radiation. The obtained results proved high radiation tolerance of studied devices making them good candidates for application in radiation-intensive environments. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. 171007

Anomalous Threshold Voltage Variability of Nitride Based Charge Storage Nonvolatile Memory Devices

Directory of Open Access Journals (Sweden)

Meng Chuan Lee

2013-01-01

Full Text Available Conventional technology scaling is implemented to meet the insatiable demand of high memory density and low cost per bit of charge storage nonvolatile memory (NVM devices. In this study, effect of technology scaling to anomalous threshold voltage ( variability is investigated thoroughly on postcycled and baked nitride based charge storage NVM devices. After long annealing bake of high temperature, cell’s variability of each subsequent bake increases within stable distribution and found exacerbate by technology scaling. Apparent activation energy of this anomalous variability was derived through Arrhenius plots. Apparent activation energy (Eaa of this anomalous variability is 0.67 eV at sub-40 nm devices which is a reduction of approximately 2 times from 110 nm devices. Technology scaling clearly aggravates this anomalous variability, and this poses reliability challenges to applications that demand strict control, for example, reference cells that govern fundamental program, erase, and verify operations of NVM devices. Based on critical evidence, this anomalous variability is attributed to lateral displacement of trapped charges in nitride storage layer. Reliability implications of this study are elucidated. Moreover, potential mitigation methods are proposed to complement technology scaling to prolong the front-runner role of nitride based charge storage NVM in semiconductor flash memory market.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

Science.gov (United States)

Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

2018-02-01

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Science.gov (United States)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Design considerations for a radiation hardened nonvolatile memory

International Nuclear Information System (INIS)

Murray, J.R.

1993-01-01

Sub-optimal design practices can reduce the radiation hardness of a circuit even though it is fabricated in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standard digital circuit, where high voltages and unusual bias conditions are required. This paper will discuss the design technique's used in the development of a 64K EEPROM (Electrically Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques

Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

Energy Technology Data Exchange (ETDEWEB)

Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

2014-10-20

High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

International Nuclear Information System (INIS)

Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

2014-01-01

High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser

2012-03-21

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance non-volatile organic ferroelectric memory on banknotes.

Science.gov (United States)

Khan, M A; Bhansali, Unnat S; Alshareef, H N

2012-04-24

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

Science.gov (United States)

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Use of non-volatile memories for SSC detector readout

International Nuclear Information System (INIS)

Fennelly, A.J.; Woosley, J.K.; Johnson, M.B.

1990-01-01

Use of non-volatile memory units at the end of each fiber optic bunch/strand would substantially increase information available from experiments by providing a complete event history, in addition to easing real time processing requirements. This may be an alternative to enhancing technology to optical computing techniques. Available and low-risk projected technologies will be surveyed, with costing addressed. Some discussion will be given to covnersion of optical signals, to electronic information, concepts for providing timing pulses to the memory units, and to the magnetoresistive (MRAM) and ferroelectric (FERAM) random access memory technologies that may be utilized in the prototype system

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Science.gov (United States)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Two-dimensional non-volatile programmable p-n junctions

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H2Pc heterojunction

International Nuclear Information System (INIS)

Karimov, Khasan S.; Muqeet Rehman, M.; Zameer Abbas, S.; Ahmad, Zubair; Touati, Farid; Mahroof-Tahir, M.

2015-01-01

A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H 2 Pc are fabricated by vacuum deposition of the CuPc and H 2 Pc films on preliminary deposited metallic (Ag and Cu) electrodes. The gap between Ag and Cu electrodes is 30–40 μm. For the current–voltage (I–V) characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120–150. Under the switching condition, the electric current increases ∼ 80–100 times. A comparison between the forward and reverse I–V characteristics shows the presence of rectifying behavior. (paper)

Nonvolatile Memory Elements Based on the Intercalation of Organic Molecules Inside Carbon Nanotubes

Science.gov (United States)

Meunier, Vincent; Kalinin, Sergei V.; Sumpter, Bobby G.

2007-02-01

We propose a novel class of nonvolatile memory elements based on the modification of the transport properties of a conducting carbon nanotube by the presence of an encapsulated molecule. The guest molecule has two stable orientational positions relative to the nanotube that correspond to conducting and nonconducting states. The mechanism, governed by a local gating effect of the molecule on the electronic properties of the nanotube host, is studied using density functional theory. The mechanisms of reversible reading and writing of information are illustrated with a F4TCNQ molecule encapsulated inside a metallic carbon nanotube. Our results suggest that this new type of nonvolatile memory element is robust, fatigue-free, and can operate at room temperature.

Highly Stretchable Non-volatile Nylon Thread Memory

Science.gov (United States)

Kang, Ting-Kuo

2016-04-01

Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

Science.gov (United States)

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Piezoelectric control of magnetoelectric coupling driven non-volatile memory switching and self cooling effects in FE/FSMA multiferroic heterostructures

Science.gov (United States)

Singh, Kirandeep; Kaur, Davinder

2017-02-01

The manipulation of magnetic states and materials' spin degree-of-freedom via a control of an electric (E-) field has been recently pursued to develop magnetoelectric (ME) coupling-driven electronic data storage devices with high read/write endurance, fast dynamic response, and low energy dissipation. One major hurdle for this approach is to develop reliable materials which should be compatible with prevailing silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology, simultaneously allowing small voltage for the tuning of magnetization switching. In this regard, multiferroic heterostructures where ferromagnetic (FM) and ferroelectric (FE) layers are alternatively grown on conventional Si substrates are promising as the piezoelectric control of magnetization switching is anticipated to be possible by an E-field. In this work, we study the ferromagnetic shape memory alloys based PbZr0.52Ti0.48O3/Ni50Mn35In15 (PZT/Ni-Mn-In) multiferroic heterostructures, and investigate their potential for CMOS compatible non-volatile magnetic data storage applications. We demonstrate the voltage-impulse controlled nonvolatile, reversible, and bistable magnetization switching at room temperature in Si-integrated PZT/Ni-Mn-In thin film multiferroic heterostructures. We also thoroughly unveil the various intriguing features in these materials, such as E-field tuned ME coupling and magnetocaloric effect, shape memory induced ferroelectric modulation, improved fatigue endurance as well as Refrigeration Capacity (RC). This comprehensive study suggests that these novel materials have a great potential for the development of unconventional nanoscale memory and refrigeration devices with self-cooling effect and enhanced refrigeration efficiency, thus providing a new venue for their applications.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

Energy Technology Data Exchange (ETDEWEB)

Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S., E-mail: miaoxs@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074 (China); School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China)

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

International Nuclear Information System (INIS)

Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

2013-01-01

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices

Controlled fabrication of Si nanocrystal delta-layers in thin SiO2 layers by plasma immersion ion implantation for nonvolatile memories

International Nuclear Information System (INIS)

Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M.; Spiegel, Y.; Torregrosa, F.; Normand, P.; Dimitrakis, P.; Kapetanakis, E.; Sahu, B. S.; Slaoui, A.

2013-01-01

Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO 2 films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories

Low-temperature process steps for realization of non-volatile memory devices

NARCIS (Netherlands)

Brunets, I.; Boogaard, A.; Aarnink, Antonius A.I.; Kovalgin, Alexeij Y.; Wolters, Robertus A.M.; Holleman, J.; Schmitz, Jurriaan

2007-01-01

In this work, the low-temperature process steps required for the realization of nano-crystal non-volatile memory cells are discussed. An amorphous silicon film, crystallized using a diode pumped solid state green laser irradiating at 532 nm, is proposed as an active layer. The deposition of the

Low-field Switching Four-state Nonvolatile Memory Based on Multiferroic Tunnel Junctions

Science.gov (United States)

Yau, H. M.; Yan, Z. B.; Chan, N. Y.; Au, K.; Wong, C. M.; Leung, C. W.; Zhang, F. Y.; Gao, X. S.; Dai, J. Y.

2015-08-01

Multiferroic tunneling junction based four-state non-volatile memories are very promising for future memory industry since this kind of memories hold the advantages of not only the higher density by scaling down memory cell but also the function of magnetically written and electrically reading. In this work, we demonstrate a success of this four-state memory in a material system of NiFe/BaTiO3/La0.7Sr0.3MnO3 with improved memory characteristics such as lower switching field and larger tunneling magnetoresistance (TMR). Ferroelectric switching induced resistive change memory with OFF/ON ratio of 16 and 0.3% TMR effect have been achieved in this multiferroic tunneling structure.

Zinc Cadmium Selenide Cladded Quantum Dot Based Electroluminescent and Nonvolatile Memory Devices

Science.gov (United States)

Al-Amody, Fuad H.

This dissertation presents electroluminescent (EL) and nonvolatile memory devices fabricated using pseudomorphic ZnCdSe-based cladded quantum dots (QDs). These dots were grown using our own in-school built novel reactor. The EL device was fabricated on a substrate of ITO (indium tin oxide) coated glass with the quantum dots sandwiched between anode and cathode contacts with a small barrier layer on top of the QDs. The importance of these cladded dots is to increase the quantum yield of device. This device is unique as they utilize quantum dots that are pseudomorphic (nearly lattice-matched core and the shell of the dot). In the case of floating quantum dot gate nonvolatile memory, cladded ZnCdSe quantum dots are deposited on single crystalline gate insulator (ZnMgS/ZnMgSe), which is grown using metal-organic chemical vapor deposition (MOCVD). The control gate dielectric layer of the nonvolatile memory is Si3N4 or SiO2 and is grown using plasma enhanced chemical vapor deposition (PECVD). The cladded dots are grown using an improved methodology of photo-assisted microwave plasma metal-organic chemical vapor deposition (PMP-MOCVD) enhanced reactor. The cladding composition of the core and shell of the dots was engineered by the help of ultraviolet light which changed the incorporation of zinc (and hence composition of ZnCdSe). This makes ZnxCd1--xSe-ZnyCd1--y Se QDs to have a low composition of zinc in the core than the cladding (x

Controlled fabrication of Si nanocrystal delta-layers in thin SiO{sub 2} layers by plasma immersion ion implantation for nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M. [CEMES-CNRS and Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse Cedex 04 (France); Spiegel, Y.; Torregrosa, F. [IBS, Rue G Imbert Prolongée, ZI Peynier-Rousset, 13790 Peynier (France); Normand, P.; Dimitrakis, P.; Kapetanakis, E. [NCSRD, Terma Patriarchou Gregoriou, 15310 Aghia Paraskevi (Greece); Sahu, B. S.; Slaoui, A. [ICube, 23 Rue du Loess, 67037 Strasbourg Cedex 2 (France)

2013-12-16

Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.

Flexible All-Inorganic Perovskite CsPbBr3 Nonvolatile Memory Device.

Science.gov (United States)

Liu, Dongjue; Lin, Qiqi; Zang, Zhigang; Wang, Ming; Wangyang, Peihua; Tang, Xiaosheng; Zhou, Miao; Hu, Wei

2017-02-22

All-inorganic perovskite CsPbX 3 (X = Cl, Br, or I) is widely used in a variety of photoelectric devices such as solar cells, light-emitting diodes, lasers, and photodetectors. However, studies to understand the flexible CsPbX 3 electrical application are relatively scarce, mainly due to the limitations of the low-temperature fabricating process. In this study, all-inorganic perovskite CsPbBr 3 films were successfully fabricated at 75 °C through a two-step method. The highly crystallized films were first employed as a resistive switching layer in the Al/CsPbBr 3 /PEDOT:PSS/ITO/PET structure for flexible nonvolatile memory application. The resistive switching operations and endurance performance demonstrated the as-prepared flexible resistive random access memory devices possess reproducible and reliable memory characteristics. Electrical reliability and mechanical stability of the nonvolatile device were further tested by the robust current-voltage curves under different bending angles and consecutive flexing cycles. Moreover, a model of the formation and rupture of filaments through the CsPbBr 3 layer was proposed to explain the resistive switching effect. It is believed that this study will offer a new setting to understand and design all-inorganic perovskite materials for future stable flexible electronic devices.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

International Nuclear Information System (INIS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

Energy Technology Data Exchange (ETDEWEB)

Han, Jinhua; Wang, Wei, E-mail: wwei99@jlu.edu.cn; Ying, Jun; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

2014-01-06

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

Energy Technology Data Exchange (ETDEWEB)

DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

1999-11-01

Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

Organic nonvolatile memory devices with charge trapping multilayer graphene film

International Nuclear Information System (INIS)

Ji, Yongsung; Choe, Minhyeok; Cho, Byungjin; Song, Sunghoon; Yoon, Jongwon; Ko, Heung Cho; Lee, Takhee

2012-01-01

We fabricated an array-type organic nonvolatile memory device with multilayer graphene (MLG) film embedded in polyimide (PI) layers. The memory devices showed a high ON/OFF ratio (over 10 6 ) and a long retention time (over 10 4 s). The switching of the Al/PI/MLG/PI/Al memory devices was due to the presence of the MLG film inserted into the PI layers. The double-log current–voltage characteristics could be explained by the space-charge-limited current conduction based on a charge-trap model. A conductive atomic force microscopy found that the conduction paths in the low-resistance ON state were distributed in a highly localized area, which was associated with a carbon-rich filamentary switching mechanism. (paper)

Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Science.gov (United States)

Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

2011-08-01

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

Graphene-quantum-dot nonvolatile charge-trap flash memories

International Nuclear Information System (INIS)

Sin Joo, Soong; Kim, Jungkil; Seok Kang, Soo; Kim, Sung; Choi, Suk-Ho; Won Hwang, Sung

2014-01-01

Nonvolatile flash-memory capacitors containing graphene quantum dots (GQDs) of 6, 12, and 27 nm average sizes (d) between SiO 2 layers for use as charge traps have been prepared by sequential processes: ion-beam sputtering deposition (IBSD) of 10 nm SiO 2 on a p-type wafer, spin-coating of GQDs on the SiO 2 layer, and IBSD of 20 nm SiO 2 on the GQD layer. The presence of almost a single array of GQDs at a distance of ∼13 nm from the SiO 2 /Si wafer interface is confirmed by transmission electron microscopy and photoluminescence. The memory window estimated by capacitance–voltage curves is proportional to d for sweep voltages wider than  ± 3 V, and for d = 27 nm the GQD memories show a maximum memory window of 8 V at a sweep voltage of  ± 10 V. The program and erase speeds are largest at d = 12 and 27 nm, respectively, and the endurance and data-retention properties are the best at d = 27 nm. These memory behaviors can be attributed to combined effects of edge state and quantum confinement. (papers)

A room-temperature non-volatile CNT-based molecular memory cell

Science.gov (United States)

Ye, Senbin; Jing, Qingshen; Han, Ray P. S.

2013-04-01

Recent experiments with a carbon nanotube (CNT) system confirmed that the innertube can oscillate back-and-forth even under a room-temperature excitation. This demonstration of relative motion suggests that it is now feasible to build a CNT-based molecular memory cell (MC), and the key to bring the concept to reality is the precision control of the moving tube for sustained and reliable read/write (RW) operations. Here, we show that by using a 2-section outertube design, we are able to suitably recalibrate the system energetics and obtain the designed performance characteristics of a MC. Further, the resulting energy modification enables the MC to operate as a non-volatile memory element at room temperatures. Our paper explores a fundamental understanding of a MC and its response at the molecular level to roadmap a novel approach in memory technologies that can be harnessed to overcome the miniaturization limit and memory volatility in memory technologies.

Nonvolatile rewritable memory device based on solution-processable graphene/poly(3-hexylthiophene) nanocomposite

Energy Technology Data Exchange (ETDEWEB)

Zhang, Li, E-mail: lizhang9@zzu.edu.cn [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China); Li, Ye; Shi, Jun [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China); Shi, Gaoquan [Department of Chemistry, Tsinghua University, Beijing 100084 (China); Cao, Shaokui, E-mail: Caoshaokui@zzu.edu.cn [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China)

2013-11-01

An electrically bistable device utilizing a nanocomposite of hexadecylamine-functionalized graphene oxide (HDAGO) with poly(3-hexylthiophene) (P3HT) is demonstrated. The device has an ITO/P3HT-HDAGO/Al sandwich structure, in which the composite film of P3HT-HDAGO was prepared by simple solution phase mixing of the exfoliated HDAGO monolayers with P3HT matrix and a spin-coating method. The memory device exhibits typical bistable electrical switching behavior and a nonvolatile rewritable memory effect, with a turn-on voltage of about 1.5 V and an ON/OFF-state current ratio of 10{sup 5}. Under ambient conditions, both the ON and OFF states are stable under a constant voltage stress or a continuous pulse voltage stress at a read voltage of 1 V. The conduction mechanism is deduced from the modeling of the nature of currents in both states, and the electrical switching behavior can be attributed to the electric-field-induced charge transfer between P3HT and HDAGO nanosheets. - Highlights: • Nonvolatile rewritable memory effect in P3HT–graphene composite is demonstrated. • The memory device was fabricated through a simple solution processing technique. • The device shows a remarkable electrical bistable behavior and excellent stability. • Memory mechanism is deduced from the modeling of the currents in both states.

Nonvolatile rewritable memory device based on solution-processable graphene/poly(3-hexylthiophene) nanocomposite

International Nuclear Information System (INIS)

Zhang, Li; Li, Ye; Shi, Jun; Shi, Gaoquan; Cao, Shaokui

2013-01-01

An electrically bistable device utilizing a nanocomposite of hexadecylamine-functionalized graphene oxide (HDAGO) with poly(3-hexylthiophene) (P3HT) is demonstrated. The device has an ITO/P3HT-HDAGO/Al sandwich structure, in which the composite film of P3HT-HDAGO was prepared by simple solution phase mixing of the exfoliated HDAGO monolayers with P3HT matrix and a spin-coating method. The memory device exhibits typical bistable electrical switching behavior and a nonvolatile rewritable memory effect, with a turn-on voltage of about 1.5 V and an ON/OFF-state current ratio of 10 5 . Under ambient conditions, both the ON and OFF states are stable under a constant voltage stress or a continuous pulse voltage stress at a read voltage of 1 V. The conduction mechanism is deduced from the modeling of the nature of currents in both states, and the electrical switching behavior can be attributed to the electric-field-induced charge transfer between P3HT and HDAGO nanosheets. - Highlights: • Nonvolatile rewritable memory effect in P3HT–graphene composite is demonstrated. • The memory device was fabricated through a simple solution processing technique. • The device shows a remarkable electrical bistable behavior and excellent stability. • Memory mechanism is deduced from the modeling of the currents in both states

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

International Nuclear Information System (INIS)

Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

2005-01-01

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

The retention characteristics of nonvolatile SNOS memory transistors in a radiation environment: Experiment and model

International Nuclear Information System (INIS)

McWhorter, P.J.; Miller, S.L.; Dellin, T.A.; Axness, C.L.

1987-01-01

Experimental data and a model to accurately and quantitatively predict the data are presented for retention of SNOS memory devices over a wide range of dose rates. A wide range of SNOS stack geometries are examined. The model is designed to aid in screening nonvolatile memories for use in a radiation environment

BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

Energy Technology Data Exchange (ETDEWEB)

Mudge, Trevor [Univ. of Michigan, Ann Arbor, MI (United States)

2017-12-15

This work was part of a larger project, Blackcomb2, centered at Oak Ridge National Labs (Jeff Vetter PI) to investigate the opportunities for replacing or supplementing DRAM main memory with nonvolatile memory (NVmemory) in Exascale memory systems. The goal was to reduce the energy consumed by in future supercomputer memory systems and to improve their resiliency. Building on the accomplishments of the original Blackcomb Project, funded in 2010, the goal for Blackcomb2 was to identify, evaluate, and optimize the most promising emerging memory technologies, architecture hardware and software technologies, which are essential to provide the necessary memory capacity, performance, resilience, and energy efficiency in Exascale systems. Capacity and energy are the key drivers.

An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags

International Nuclear Information System (INIS)

Jia Xiaoyun; Feng Peng; Zhang Shengguang; Wu Nanjian; Zhao Baiqin; Liu Su

2013-01-01

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler—Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm 2 and 0.12 mm 2 , respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s). (semiconductor integrated circuits)

Microwave oven fabricated hybrid memristor devices for non-volatile memory storage

International Nuclear Information System (INIS)

Verrelli, E; Gray, R J; O’Neill, M; Kemp, N T; Kelly, S M

2014-01-01

Novel hybrid non-volatile memories made using an ultra-fast microwave heating method are reported for the first time. The devices, consisting of aligned ZnO nanorods embedded in poly (methyl methacrylate), require no forming step and exhibit reliable and reproducible bipolar resistive switching at low voltages and with low power usage. We attribute these properties to a combination of the high aspect ratio of the nanorods and the polymeric hybrid structure of the device. The extremely easy, fast and low-cost solution based method of fabrication makes possible the simple and quick production of cheap memory cells. (paper)

A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

Science.gov (United States)

Liu, S. Q.; Wu, N. J.; Ignatiev, A.

2001-01-01

A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

Negative effect of Au nanoparticles on an IGZO TFT-based nonvolatile memory device

Energy Technology Data Exchange (ETDEWEB)

Lim, Myunghoon; Yoo, Gwangwe; Lee, Jongtaek; Jeong, Seokwon; Roh, Yonghan; Park, Jinhong; Kwon, Namyong [Sungkyunkwan University, Suwon (Korea, Republic of); Jung, Wooshik [Stanford University, Stanford, CA (United States)

2014-02-15

In this letter, the electrical characteristics of nonvolatile memory devices based on back gate type indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are investigated in terms of the Au nanoparticles (NPs) employed in the floating gate-stack of the device. The size of the Au NPs is controlled using a by 500 .deg. C annealing process after the Au thin-film deposition. The size and the roughness of the Au NPs were observed by using scanning electron microscopy, atomic force microscopy, and transmission electron microscopy. In order to analyze the electrical properties according to Au NP size, we measured the current-voltage (I{sub D}-V{sub G}) characteristics of the nonvolatile memory devices fabricated without Au NPs and with Au NPs of various sizes. The size of the Au NP increased, so did the surface roughness of the gate. This resulted in increased carrier scattering, which subsequently degraded the on-current of the memory device. In addition, inter-diffusion between the Au and the α-IGZO through the non-uniform Al{sub 2}O{sub 3} tunneling layer seemed to further degrade the device performance.

Integration of ammonia-plasma-functionalized graphene nanodiscs as charge trapping centers for nonvolatile memory applications

KAUST Repository

Wang, Jer-Chyi

2016-11-23

Graphene nanodiscs (GNDs), functionalized using NH3 plasma, as charge trapping sites (CTSs) for non-volatile memory applications have been investigated in this study. The fabrication process relies on the patterning of Au nanoparticles (Au-NPs), whose thicknesses are tuned to adjust the GND density and size upon etching. A GND density as high as 8 × 1011 cm−2 and a diameter of approximately 20 nm are achieved. The functionalization of GNDs by NH3 plasma creates Nsingle bondH+ functional groups that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the memory window becomes more than 2.4 V and remains stable after 104 operating cycles. The charge loss is less than 10% for a 10-year data retention testing, making this low-temperature process suitable for low-cost non-volatile memory applications on flexible substrates.

Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices

Directory of Open Access Journals (Sweden)

Fu-Chien Chiu

2013-01-01

Full Text Available Bipolar resistance switching characteristics are demonstrated in Pt/ZnO/Pt nonvolatile memory devices. A negative differential resistance or snapback characteristic can be observed when the memory device switches from a high resistance state to a low resistance state due to the formation of filamentary conducting path. The dependence of pulse width and temperature on set/reset voltages was examined in this work. The exponentially decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1 s. Hence, to switch the ZnO memory devices, a minimum set/reset voltage is required. The set voltage decreases linearly with the temperature whereas the reset voltage is nearly temperature-independent. In addition, the ac cycling endurance can be over 106 switching cycles, whereas, the dependence of HRS/LRS resistance distribution indicates that a significant memory window closure may take place after about 102  dc switching cycles.

Nonvolatile memory effect of tungsten nanocrystals under oxygen plasma treatments

International Nuclear Information System (INIS)

Chen, Shih-Cheng; Chang, Ting-Chang; Chen, Wei-Ren; Lo, Yuan-Chun; Wu, Kai-Ting; Sze, S.M.; Chen, Jason; Liao, I.H.; Yeh, Fon-Shan

2010-01-01

In this work, an oxygen plasma treatment was used to improve the memory effect of nonvolatile W nanocrystal memory, including memory window, retention and endurance. To investigate the role of the oxygen plasma treatment in charge storage characteristics, the X-ray photon-emission spectra (XPS) were performed to analyze the variation of chemical composition for W nanocrystal embedded oxide both with and without the oxygen plasma treatment. In addition, the transmission electron microscopy (TEM) analyses were also used to identify the microstructure in the thin film and the size and density of W nanocrystals. The device with the oxygen plasma treatment shows a significant improvement of charge storage effect, because the oxygen plasma treatment enhanced the quality of silicon oxide surrounding the W nanocrystals. Therefore, the data retention and endurance characteristics were also improved by the passivation.

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

Science.gov (United States)

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

Science.gov (United States)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

Science.gov (United States)

Natsui, Masanori; Hanyu, Takahiro

2018-04-01

In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

Non-volatile memory devices with redox-active diruthenium molecular compound

International Nuclear Information System (INIS)

Pookpanratana, S; Zhu, H; Bittle, E G; Richter, C A; Li, Q; Hacker, C A; Natoli, S N; Ren, T

2016-01-01

Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al 2 O 3 /molecule/SiO 2 /Si structure. The bulky ruthenium redox molecule is attached to the surface by using a ‘click’ reaction and the monolayer structure is characterized by x-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The ‘click’ reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices. (paper)

Charge trapping characteristics of Au nanocrystals embedded in remote plasma atomic layer-deposited Al2O3 film as the tunnel and blocking oxides for nonvolatile memory applications

International Nuclear Information System (INIS)

Lee, Jaesang; Kim, Hyungchul; Park, Taeyong; Ko, Youngbin; Ryu, Jaehun; Jeon, Heeyoung; Park, Jingyu; Jeon, Hyeongtag

2012-01-01

Remote plasma atomic layer deposited (RPALD) Al 2 O 3 films were investigated to apply as tunnel and blocking layers in the metal-oxide-semiconductor capacitor memory utilizing Au nanocrystals (NCs) for nonvolatile memory applications. The interface stability of an Al 2 O 3 film deposited by RPALD was studied to observe the effects of remote plasma on the interface. The interface formed during RPALD process has high oxidation states such as Si +3 and Si +4 , indicating that RPALD process can grow more stable interface which has a small amount of fixed oxide trap charge. The significant memory characteristics were also observed in this memory device through the electrical measurement. The memory device exhibited a relatively large memory window of 5.6 V under a 10/-10 V program/erase voltage and also showed the relatively fast programming/erasing speed and a competitive retention characteristic after 10 4 s. These results indicate that Al 2 O 3 films deposited via RPALD can be applied as the tunnel and blocking oxides for next-generation flash memory devices.

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

Directory of Open Access Journals (Sweden)

Sparsh Mittal

2017-02-01

Full Text Available Non-volatile memories (NVMs offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory and STT-RAM (spin transfer torque RAM. We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

Preparation of NiFe binary alloy nanocrystals for nonvolatile memory applications

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

In this work,an idea which applies binary alloy nanocrystal floating gate to nonvolatile memory application was introduced.The relationship between binary alloy’s work function and its composition was discussed theoretically.A nanocrystal floating gate structure with NiFe nanocrystals embedded in SiO2 dielectric layers was fabricated by magnetron sputtering.The micro-structure and composition deviation of the prepared NiFe nanocrystals were also investigated by TEM and EDS.

Intrinsic Ge nanowire nonvolatile memory based on a simple core–shell structure

International Nuclear Information System (INIS)

Chen, Wen-Hua; Liu, Chang-Hai; Li, Qin-Liang; Sun, Qi-Jun; Liu, Jie; Gao, Xu; Sun, Xuhui; Wang, Sui-Dong

2014-01-01

Intrinsic Ge nanowires (NWs) with a Ge core covered by a thick Ge oxide shell are utilized to achieve nanoscale field-effect transistor nonvolatile memories, which show a large memory window and a high ON/OFF ratio with good retention. The retainable surface charge trapping is considered to be responsible for the memory effect, and the Ge oxide shell plays a key role as the insulating tunneling dielectric which must be thick enough to prevent stored surface charges from leaking out. Annealing the device in air is demonstrated to be a simple and effective way to attain thick Ge oxide on the Ge NW surface, and the Ge-NW-based memory corresponding to thick Ge oxide exhibits a much better retention capability compared with the case of thin Ge oxide. (paper)

The origin of traps and the effect of nitrogen plasma in oxide-nitride-oxide structures for non-volatile memories

International Nuclear Information System (INIS)

Kim, W. S.; Kwak, D. W.; Oh, J. S.; Lee, D. W.; Cho, H. Y.

2010-01-01

Ultrathin oxide-nitride-oxide (ONO) dielectric stacked layers are fundamental structures of silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory devices in which information is known to be stored as charges trapped in silicon nitride. Deep-level transient spectroscopy (DLTS) and a capacitance-voltage (CV) analysis were introduced to observe the trap behavior related to the memory effect in memory devices. The DLTS results verified that the nitride-related traps were a dominant factor in the memory effect. The energy of hole traps was 0.307 eV above the balance band. To improve the memory effects of the non-volatile memory devices with ONO structures, we introduced a nitrogen plasma treatment. After the N-plasma treatment, the flat-band voltage shift (ΔV FB ) was increased by about 1.5 times. The program and the erase (P-E) characteristics were also shown to be better than those for the as-ONO structure. In addition, the retention characteristics were improved by over 2.4 times.

Comparison of discrete-storage nonvolatile memories: advantage of hybrid method for fabrication of Au nanocrystal nonvolatile memory

International Nuclear Information System (INIS)

Wang Qin; Jia Rui; Guan Weihua; Li Weilong; Liu Qi; Hu Yuan; Long Shibing; Chen Baoqin; Liu Ming; Ye Tianchun; Lu Wensheng; Jiang Long

2008-01-01

In this paper, the memory characteristics of two kinds of metal-oxide-semiconductor (MOS) capacitors embedded with Au nanocrytals are investigated: hybrid MOS with nanocrystals (NCs) fabricated by chemical syntheses and rapid thermal annealing (RTA) MOS with NCs fabricated by RTA. For both kinds of devices, the capacitance versus voltage (C-V) curves clearly indicate the charge storage in the NCs. The hybrid MOS, however, shows a larger memory window, as compared with RTA MOS. The retention characteristics of the two MOS devices are also investigated. The capacitance versus time (C-t) measurement shows that the hybrid MOS capacitor embedded with Au nanocrystals has a longer retention time. The mechanism of longer retention time for hybrid MOS capacitor is qualitatively discussed

A radiation-tolerant, low-power non-volatile memory based on silicon nanocrystal quantum dots

OpenAIRE

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; De Blauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO_2 is a critical aspect of the performance ...

The MONOS memory transistor: application in a radiation-hard nonvolatile RAM

International Nuclear Information System (INIS)

Brown, W.D.

1985-01-01

The MONOS (metal-oxide-nitride-oxide-silicon) device is a prime candidate for use as the nonvolatile memory element in a radiation-hardened RAM (random-access memory). The endurance, retention and radiation properties of MONOS memory transistors have been studied as a function of post nitride deposition annealing. Following the nitride layer deposition, all devices were subjected to an 800 0 C oxidation step and some were then annealed at 900 0 C in nitrogen. The nitrogen anneal produces an increase in memory window size of approximately 40%. The memory window center of the annealed devices is shifted toward more positive voltages and is more stable with endurance cycling. Endurance cycling to 10 9 cycles produces a 20% increase in memory window size and a 60% increase in decay rate. For a radiation total dose of 10 6 rads (Si), the memory window size is essentially unchanged and the decay rate increases approximately 13%. A combination of 10 9 cycles and 10 6 rads (Si) reduces the decades of retention (in sec) from 6.3 to 4.3 for a +- 23-V 16-μsec write/erase pulse. (author)

Modeling of SONOS Memory Cell Erase Cycle

Science.gov (United States)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat H.

2011-01-01

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

Phase-change materials for non-volatile memory devices: from technological challenges to materials science issues

Science.gov (United States)

Noé, Pierre; Vallée, Christophe; Hippert, Françoise; Fillot, Frédéric; Raty, Jean-Yves

2018-01-01

Chalcogenide phase-change materials (PCMs), such as Ge-Sb-Te alloys, have shown outstanding properties, which has led to their successful use for a long time in optical memories (DVDs) and, recently, in non-volatile resistive memories. The latter, known as PCM memories or phase-change random access memories (PCRAMs), are the most promising candidates among emerging non-volatile memory (NVM) technologies to replace the current FLASH memories at CMOS technology nodes under 28 nm. Chalcogenide PCMs exhibit fast and reversible phase transformations between crystalline and amorphous states with very different transport and optical properties leading to a unique set of features for PCRAMs, such as fast programming, good cyclability, high scalability, multi-level storage capability, and good data retention. Nevertheless, PCM memory technology has to overcome several challenges to definitively invade the NVM market. In this review paper, we examine the main technological challenges that PCM memory technology must face and we illustrate how new memory architecture, innovative deposition methods, and PCM composition optimization can contribute to further improvements of this technology. In particular, we examine how to lower the programming currents and increase data retention. Scaling down PCM memories for large-scale integration means the incorporation of the PCM into more and more confined structures and raises materials science issues in order to understand interface and size effects on crystallization. Other materials science issues are related to the stability and ageing of the amorphous state of PCMs. The stability of the amorphous phase, which determines data retention in memory devices, can be increased by doping the PCM. Ageing of the amorphous phase leads to a large increase of the resistivity with time (resistance drift), which has up to now hindered the development of ultra-high multi-level storage devices. A review of the current understanding of all these

Testing of modern semiconductor memory structures

NARCIS (Netherlands)

Gaydadjiev, G.N.

2007-01-01

In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application

Semiconductor-based, large-area, flexible, electronic devices

Science.gov (United States)

Goyal, Amit [Knoxville, TN

2011-03-15

Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

Science.gov (United States)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Amorphous Semiconductors: From Photocatalyst to Computer Memory

Science.gov (United States)

Sundararajan, Mayur

encouraging but inconclusive. Then the method was successfully demonstrated on mesoporous TiO2SiO 2 by showing a shift in its optical bandgap. One of the special class of amorphous semiconductors is chalcogenide glasses, which exhibit high ionic conductivity even at room temperature. When metal doped chalcogenide glasses are under an electric field, they become electronically conductive. These properties are exploited in the computer memory storage application of Conductive Bridging Random Access Memory (CBRAM). CBRAM is a non-volatile memory that is a strong contender to replace conventional volatile RAMs such as DRAM, SRAM, etc. This technology has already been commercialized, but the working mechanism is still not clearly understood especially the nature of the conductive bridge filament. In this project, the CBRAM memory cells are fabricated by thermal evaporation method with Agx(GeSe 2)1-x as the solid electrolyte layer, Ag as the active electrode and Au as the inert electrode. By careful use of cyclic voltammetry, the conductive filaments were grown on the surface and the bulk of the solid electrolyte. The comparison between the two filaments revealed major differences leading to contradiction with the existing working mechanism. After compiling all the results, a modified working mechanism is proposed. SAXS is a powerful tool to characterize nanostructure of glasses. The analysis of the SAXS data to get useful information are usually performed by different programs. In this project, Irena and GIFT programs were compared by performing the analysis of the SAXS data of glass and glass ceramics samples. Irena was shown to be not suitable for the analysis of SAXS data that has a significant contribution from interparticle interactions. GIFT was demonstrated to be better suited for such analysis. Additionally, the results obtained by programs for samples with low interparticle interactions were shown to be consistent.

A graphene-based non-volatile memory

Science.gov (United States)

Loisel, Loïc.; Maurice, Ange; Lebental, Bérengère; Vezzoli, Stefano; Cojocaru, Costel-Sorin; Tay, Beng Kang

2015-09-01

We report on the development and characterization of a simple two-terminal non-volatile graphene switch. After an initial electroforming step during which Joule heating leads to the formation of a nano-gap impeding the current flow, the devices can be switched reversibly between two well-separated resistance states. To do so, either voltage sweeps or pulses can be used, with the condition that VSET achieve reversible switching on more than 100 cycles with resistance ratio values of 104. This approach of graphene memory is competitive as compared to other graphene approaches such as redox of graphene oxide, or electro-mechanical switches with suspended graphene. We suggest a switching model based on a planar electro-mechanical switch, whereby electrostatic, elastic and friction forces are competing to switch devices ON and OFF, and the stability in the ON state is achieved by the formation of covalent bonds between the two stretched sides of the graphene, hence bridging the nano-gap. Developing a planar electro-mechanical switch enables to obtain the advantages of electro-mechanical switches while avoiding most of their drawbacks.

Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

Science.gov (United States)

Huh, In; Cheon, Woo Young; Choi, Woo Young

2016-04-01

A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

A direct metal transfer method for cross-bar type polymer non-volatile memory applications

International Nuclear Information System (INIS)

Kim, Tae-Wook; Lee, Kyeongmi; Oh, Seung-Hwan; Wang, Gunuk; Kim, Dong-Yu; Jung, Gun-Young; Lee, Takhee

2008-01-01

Polymer non-volatile memory devices in 8 x 8 array cross-bar architecture were fabricated by a non-aqueous direct metal transfer (DMT) method using a two-step thermal treatment. Top electrodes with a linewidth of 2 μm were transferred onto the polymer layer by the DMT method. The switching behaviour of memory devices fabricated by the DMT method was very similar to that of devices fabricated by the conventional shadow mask method. The devices fabricated using the DMT method showed three orders of magnitude of on/off ratio with stable resistance switching, demonstrating that the DMT method can be a simple process to fabricate organic memory array devices

Non-volatile main memory management methods based on a file system.

Science.gov (United States)

Oikawa, Shuichi

2014-01-01

There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Soochow University, Suzhou, Jiangsu 215123 (China)

2016-07-11

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

Discrete Charge Storage Nonvolatile Memory Based on Si Nanocrystals with Nitridation Treatment

International Nuclear Information System (INIS)

Xian-Gao, Zhang; Kun-Ji, Chen; Zhong-Hui, Fang; Xin-Ye, Qian; Guang-Yuan, Liu; Xiao-Fan, Jiang; Zhong-Yuan, Ma; Jun, Xu; Xin-Fan, Huang; Jian-Xin, Ji; Fei, He; Kuang-Bao, Song; Jun, Zhang; Hui, Wan; Rong-Hua, Wang

2010-01-01

A nonvolatile memory device with nitrided Si nanocrystals embedded in a Boating gate was fabricated. The uniform Si nanocrystals with high density (3 × 10 11 cm −2 ) were deposited on ultra-thin tunnel oxide layer (∼ 3 nm) and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanocrystals, which slows the charge loss rate. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Memory characteristics of Au nanocrystals embedded in metal-oxide-semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide

International Nuclear Information System (INIS)

Wang, C.-C.; Chiou, Y.-K.; Chang, C.-H.; Tseng, J.-Y.; Wu, L.-J.; Chen, C.-Y.; Wu, T.-B.

2007-01-01

The nonvolatile memory characteristics of metal-oxide-semiconductor (MOS) structures containing Au nanocrystals in the Al 2 O 3 /SiO 2 matrix were studied. In this work, we have demonstrated that the use of Al 2 O 3 as control oxide prepared by atomic-layer-deposition enhances the erase speed of the MOS capacitors. A giant capacitance-voltage hysteresis loop and a very short erase time which is lower than 1 ms can be obtained. Compared with the conventional floating-gate electrically erasable programmable read-only memories, the erase speed was promoted drastically. In addition, very low leakage current and large turn-around voltage resulting from electrons or holes stored in the Au nanocrystals were found in the current-voltage relation of the MOS capacitors

Ferroelectric-gate field effect transistor memories device physics and applications

CERN Document Server

Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

2016-01-01

This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

The charge storage characteristics of ZrO2 nanocrystallite-based charge trap nonvolatile memory

International Nuclear Information System (INIS)

Tang Zhen-Jie; Li Rong; Yin Jiang

2013-01-01

ZrO 2 nanocrystallite-based charge trap flash memory capacitors incorporating a (ZrO 2 ) 0.6 (SiO 2 ) 0.4 pseudobinary high-k oxide film as the charge trapping layer were prepared and investigated. The precipitation reaction in the charge trapping layer, forming ZrO 2 nanocrystallites during rapid thermal annealing, was investigated by transmission electron microscopy and X-ray diffraction. It was observed that a ZrO 2 nanocrystallite-based memory capacitor after post-annealing at 850 °C for 60 s exhibits a maximum memory window of about 6.8 V, good endurance and a low charge loss of ∼25% over a period of 10 years (determined by extrapolating the charge loss curve measured experimentally), even at 85 °C. Such 850 °C-annealed memory capacitors appear to be candidates for future nonvolatile flash memory device applications

Origami-based tunable truss structures for non-volatile mechanical memory operation.

Science.gov (United States)

Yasuda, Hiromi; Tachi, Tomohiro; Lee, Mia; Yang, Jinkyu

2017-10-17

Origami has recently received significant interest from the scientific community as a method for designing building blocks to construct metamaterials. However, the primary focus has been placed on their kinematic applications by leveraging the compactness and auxeticity of planar origami platforms. Here, we present volumetric origami cells-specifically triangulated cylindrical origami (TCO)-with tunable stability and stiffness, and demonstrate their feasibility as non-volatile mechanical memory storage devices. We show that a pair of TCO cells can develop a double-well potential to store bit information. What makes this origami-based approach more appealing is the realization of two-bit mechanical memory, in which two pairs of TCO cells are interconnected and one pair acts as a control for the other pair. By assembling TCO-based truss structures, we experimentally verify the tunable nature of the TCO units and demonstrate the operation of purely mechanical one- and two-bit memory storage prototypes.Origami is a popular method to design building blocks for mechanical metamaterials. Here, the authors assemble a volumetric origami-based structure, predict its axial and rotational movements during folding, and demonstrate the operation of mechanical one- and two-bit memory storage.

Semiconductor-based, large-area, flexible, electronic devices on {110} oriented substrates

Science.gov (United States)

Goyal, Amit

2014-08-05

Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110} textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

[100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

Science.gov (United States)

Goyal, Amit

2015-03-24

Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure

International Nuclear Information System (INIS)

Kim, Tae-Wook; Choi, Hyejung; Oh, Seung-Hwan; Jo, Minseok; Wang, Gunuk; Cho, Byungjin; Kim, Dong-Yu; Hwang, Hyunsang; Lee, Takhee

2009-01-01

The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 μm 2 to 200 x 200 nm 2 . From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I ON /I OFF ∼10 4 ), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10 000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

Atomically Smooth Epitaxial Ferroelectric Thin Films for the Development of a Nonvolatile, Ultrahigh Density, Fast, Low Voltage, Radiation-Hard Memory

National Research Council Canada - National Science Library

Ahn, Charles H

2006-01-01

The goal of this research is to fabricate atomically smooth, single crystalline, complex oxide thin film nanostructures for use in a nonvolatile, ultrahigh density, fast, low voltage, radiation-hard memory...

Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices

Science.gov (United States)

Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

2016-01-01

Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr07377d

Ferroelectric polymer gates for non-volatile field effect control of ferromagnetism in (Ga, Mn)As layers

International Nuclear Information System (INIS)

Stolichnov, I; Riester, S W E; Mikheev, E; Setter, N; Rushforth, A W; Edmonds, K W; Campion, R P; Foxon, C T; Gallagher, B L; Jungwirth, T; Trodahl, H J

2011-01-01

(Ga, Mn)As and other diluted magnetic semiconductors (DMS) attract a great deal of attention for potential spintronic applications because of the possibility of controlling the magnetic properties via electrical gating. Integration of a ferroelectric gate on the DMS channel adds to the system a non-volatile memory functionality and permits nanopatterning via the polarization domain engineering. This topical review is focused on the multiferroic system, where the ferromagnetism in the (Ga, Mn)As DMS channel is controlled by the non-volatile field effect of the spontaneous polarization. Use of ferroelectric polymer gates in such heterostructures offers a viable alternative to the traditional oxide ferroelectrics generally incompatible with DMS. Here we review the proof-of-concept experiments demonstrating the ferroelectric control of ferromagnetism, analyze the performance issues of the ferroelectric gates and discuss prospects for further development of the ferroelectric/DMS heterostructures toward the multiferroic field effect transistor. (topical review)

Stability of semiconductor memory characteristics in a radiation environment

OpenAIRE

Fetahović, I.; Vujisić, M.; Stanković, K.; Dolićanin, E.

2015-01-01

Radiation defects in electronic device can occur in a process of its fabrication or during use. Miniaturization trends in industry and increase in level of integration of electronic components have negative affect on component's behavior in a radiation environment. The aim of this paper is to analyze radiation effects in semiconductor memories and to establish how ionizing radiation influences characteristics and functionality of semiconductor memories. Both the experimental procedure and sim...

Switching speed in resistive random access memories (RRAMS) based on plastic semiconductor

NARCIS (Netherlands)

Rocha, P.R.F.; Gomes, H.L.; Kiazadeh, A.; Chen, Qian; Leeuw, de D.M.; Meskers, S.C.J.

2011-01-01

This work addresses non-volatile memories based on metal-oxide polymer diodes. We make a thorough investigation into the static and dynamic behavior. Current-voltage characteristics with varying voltage ramp speed demonstrate that the internal capacitive double-layer structure inhibits the switching

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

Science.gov (United States)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

Directory of Open Access Journals (Sweden)

Fabrizio Riente

2017-05-01

Full Text Available Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

{100} or 45.degree.-rotated {100}, semiconductor-based, large-area, flexible, electronic devices

Science.gov (United States)

Goyal, Amit [Knoxville, TN

2012-05-15

Novel articles and methods to fabricate the same resulting in flexible, {100} or 45.degree.-rotated {100} oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

Energy Technology Data Exchange (ETDEWEB)

De, Arup [Univ. of California, San Diego, CA (United States)

2014-01-01

Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

Science.gov (United States)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

75 FR 14467 - In the Matter of: Certain Dynamic Random Access Memory Semiconductors and Products Containing...

Science.gov (United States)

2010-03-25

... Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of... semiconductors and products containing same, including memory modules, by reason of infringement of certain... importation of certain dynamic random access memory semiconductors or products containing the same, including...

Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

KAUST Repository

Ghoneim, Mohamed T.

2015-04-24

A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol-gel coating cycles required (i.e., more cost-effective), and, fabrication wise, is more suitable for further scaling of lateral dimensions to the nano-scale due to the larger feature size-to-depth aspect ratio (critical for ultra-high density non-volatile memory applications). Utilizing the inverse proportionality between substrate\\'s thickness and its flexibility, traditional PZT based FeRAM on silicon is transformed through a transfer-less manufacturable process into a flexible form that matches organic electronics\\' flexibility while preserving the superior performance of silicon CMOS electronics. Each memory cell in a FeRAM array consists of two main elements; a select/access transistor, and a storage ferroelectric capacitor. Flexible transistors on silicon have already been reported. In this work, we focus on the storage ferroelectric capacitors, and report, for the first time, its performance after transformation into a flexible version, and assess its key memory parameters while bent at 0.5 cm minimum bending radius.

Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

Energy Technology Data Exchange (ETDEWEB)

Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

2010-09-01

Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

Conjugated donor-acceptor-acceptor (D-A-A) molecule for organic nonvolatile resistor memory.

Science.gov (United States)

Dong, Lei; Li, Guangwu; Yu, An-Dih; Bo, Zhishan; Liu, Cheng-Liang; Chen, Wen-Chang

2014-12-01

A new donor-acceptor-acceptor (D-A-A) type of conjugated molecule, N-(4-(N',N'-diphenyl)phenylamine)-4-(4'-(2,2-dicyanovinyl)phenyl) naphthalene-1,8-dicarboxylic monoimide (TPA-NI-DCN), consisting of triphenylamine (TPA) donors and naphthalimide (NI)/dicyanovinylene (DCN) acceptors was synthesized and characterized. In conjunction with previously reported D-A based materials, the additional DCN moiety attached as end group in the D-A-A configuration can result in a stable charge transfer (CT) and charge-separated state to maintain the ON state current. The vacuum-deposited TPA-NI-DCN device fabricated as an active memory layer was demonstrated to exhibit write-once-read-many (WORM) switching characteristics of organic nonvolatile memory due to the strong polarity of the TPA-NI-DCN moiety. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Radiation-hardened nonvolatile MNOS RAM

International Nuclear Information System (INIS)

Wrobel, T.F.; Dodson, W.H.; Hash, G.L.; Jones, R.V.; Nasby, R.D.; Olson, R.J.

1983-01-01

A radiation hardened nonvolatile MNOS RAM is being developed at Sandia National Laboratories. The memory organization is 128 x 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The devices have memory retention after a dose-rate exposure of 1E12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s

Nonvolatile Memory Materials for Neuromorphic Intelligent Machines.

Science.gov (United States)

Jeong, Doo Seok; Hwang, Cheol Seong

2018-04-18

Recent progress in deep learning extends the capability of artificial intelligence to various practical tasks, making the deep neural network (DNN) an extremely versatile hypothesis. While such DNN is virtually built on contemporary data centers of the von Neumann architecture, physical (in part) DNN of non-von Neumann architecture, also known as neuromorphic computing, can remarkably improve learning and inference efficiency. Particularly, resistance-based nonvolatile random access memory (NVRAM) highlights its handy and efficient application to the multiply-accumulate (MAC) operation in an analog manner. Here, an overview is given of the available types of resistance-based NVRAMs and their technological maturity from the material- and device-points of view. Examples within the strategy are subsequently addressed in comparison with their benchmarks (virtual DNN in deep learning). A spiking neural network (SNN) is another type of neural network that is more biologically plausible than the DNN. The successful incorporation of resistance-based NVRAM in SNN-based neuromorphic computing offers an efficient solution to the MAC operation and spike timing-based learning in nature. This strategy is exemplified from a material perspective. Intelligent machines are categorized according to their architecture and learning type. Also, the functionality and usefulness of NVRAM-based neuromorphic computing are addressed. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

Science.gov (United States)

Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

2018-09-01

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

Poly (vinylidene fluoride-trifluoroethylene/barium titanate nanocomposite for ferroelectric nonvolatile memory devices

Directory of Open Access Journals (Sweden)

Uvais Valiyaneerilakkal

2013-04-01

Full Text Available The effect of barium titanate (BaTiO3 nanoparticles (particle size <100nm on the ferroelectric properties of poly (vinylidenefluoride-trifluoroethylene P(VDF-TrFE copolymer has been studied. Different concentrations of nanoparticles were added to P(VDF-TrFE using probe sonication, and uniform thin films were made. Polarisation - Electric field (P-E hysteresis analysis shows an increase in remnant polarization (Pr and decrease in coercive voltage (Vc. Piezo-response force microscopy analysis shows the switching capability of the polymer composite. The topography and surface roughness was studied using atomic force microscopy. It has been observed that this nanocomposite can be used for the fabrication of non-volatile ferroelectric memory devices.

Effect of Ag nanoparticles on resistive switching of polyfluorene-based organic non-volatile memory devices

International Nuclear Information System (INIS)

Kim, Tae-Wook; Oh, Seung-Hwan; Choi, Hye-Jung; Wang, Gun-Uk; Kim, Dong-Yu; Hwang, Hyun-Sang; Lee, Tak-Hee

2010-01-01

The effects of Ag nanoparticles on the switching behavior of polyfluorene-based organic nonvolatile memory devices were investigated. Polyfluorene-derivatives (WPF-oxy-F) with and without Ag nanoparticles were synthesized, and the presence of Ag nanoparticles in Ag-WPF-oxy-F was identified by transmission electron microscopy and X-ray photoelectron spectroscopy analyses. The Ag-nanoparticles did not significantly affect the basic switching performances, such as the current-voltage characteristics, the distribution of on/off resistance, and the retention. The pulse switching time of Ag-WPF-oxy-F was faster than that of WPF-oxy-F. Ag-WPF-oxy-F memory devices showed an area dependence in the high resistance state, implying that formation of a Ag metallic channel for current conduction.

Nonvolatile resistive switching in Pt/laALO3/srTiO3 heterostructures

KAUST Repository

Wu, S.; Luo, X.; Turner, S.; Peng, H.; Lin, W.; Ding, J.; David, A.; Wang, B.; Van, Tendeloo, G.; Wang, J.; Wu, Tao

2013-01-01

Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO3/SrTiO3 heterostructures

Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS2 quantum dot-polymethylmethacrylate nanocomposites

International Nuclear Information System (INIS)

Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan; Kim, Sang Wook

2014-01-01

Nonvolatile memory devices based on CuInS 2 (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10 −10 was maintained for 8 × 10 3 cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10 6 cycles converged to 2.40 × 10 −10 , indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

Science.gov (United States)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

Science.gov (United States)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Fabrication and characterization of metal-ferroelectric (PbZr0.6Ti0.4O3)-insulator (La2O3)-semiconductor capacitors for nonvolatile memory applications

Science.gov (United States)

Juan, Trevor Pi-Chun; Lin, Cheng-Li; Shih, Wen-Chieh; Yang, Chin-Chieh; Lee, Joseph Ya-Min; Shye, Der-Chi; Lu, Jong-Hong

2009-03-01

Metal-ferroelectric-insulator-semiconductor thin-film capacitors with Pb(Zr0.6,Ti0.4)O3 (PZT) ferroelectric layer and high-k lanthanum oxide (La2O3) insulator layer were fabricated. The outdiffusion of atoms between La2O3 and silicon was examined by the secondary-ion-mass spectroscopy. The size of memory window as a function of PZT annealing temperature was discussed. The maximum memory window saturated to 0.7 V, which is close to the theoretical memory window ΔW ≈2dfEc≈0.8 V with higher annealing temperatures above 700 °C. The memory window starts to decrease due to charge injection when the sweep voltage is higher than 5 V at 600 °C-annealed samples. The C-V flatband voltage shift (ΔVFB) as a function of charge injection was characterized in this work. An energy band diagram of the Al/PZT//La2O3/p-Si system was proposed to explain the memory window and the flatband voltage shift.

Electric field mediated non-volatile tuning magnetism in CoPt/PMN-PT heterostructure for magnetoelectric memory devices

Science.gov (United States)

Yang, Y. T.; Li, J.; Peng, X. L.; Wang, X. Q.; Wang, D. H.; Cao, Q. Q.; Du, Y. W.

2016-02-01

We report a power efficient non-volatile magnetoelectric memory in the CoPt/(011)PMN-PT heterostructure. Two reversible and stable electric field induced coercivity states (i.e., high-HC or low-HC) are obtained due to the strain mediated converse magnetoelectric effect. The reading process of the different coercive field information written by electric fields is demonstrated by using a magnetoresistance read head. This result shows good prospects in the application of novel multiferroic devices.

Evaluation of Recent Technologies of Nonvolatile RAM

Science.gov (United States)

Nuns, Thierry; Duzellier, Sophie; Bertrand, Jean; Hubert, Guillaume; Pouget, Vincent; Darracq, FrÉdÉric; David, Jean-Pierre; Soonckindt, Sabine

2008-08-01

Two types of recent nonvolatile random access memories (NVRAM) were evaluated for radiation effects: total dose and single event upset and latch-up under heavy ions and protons. Complementary irradiation with a laser beam provides information on sensitive areas of the devices.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

Science.gov (United States)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

International Nuclear Information System (INIS)

Sung, Sihyun; Kim, Tae Whan

2017-01-01

Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10 3 and 1.4 × 10 3 , respectively. The retention times of the devices before and after bending remained same 1 × 10 4 s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

Energy Technology Data Exchange (ETDEWEB)

Sung, Sihyun; Kim, Tae Whan, E-mail: twk@hanyang.ac.kr

2017-07-31

Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10{sup 3} and 1.4 × 10{sup 3}, respectively. The retention times of the devices before and after bending remained same 1 × 10{sup 4} s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

Dependence of the organic nonvolatile memory performance on the location of ultra-thin Ag film

International Nuclear Information System (INIS)

Jiao Bo; Wu Zhaoxin; He Qiang; Mao Guilin; Hou Xun; Tian Yuan

2010-01-01

We demonstrated organic nonvolatile memory devices based on 4,4',4''-tris[N-(3-methylphenyl)-N-phenylamino] triphenylamine (m-MTDATA) inserted by an ultra-thin Ag film. The memory devices with different locations of ultra-thin Ag film in m-MTDATA were investigated, and it was found that the location of the Ag film could affect the performance of the organic memory, such as ON/OFF ratio, retention time and cycling endurance. When the Ag film was located at the ITO/m-MTDATA interface, the largest ON/OFF ratio (about 10 5 ) could be achieved, but the cycling endurance was poor. When the Ag film was located in the middle region of the m-MTDATA layer, the ON/OFF ratios came down by about 10 3 , but better performance of cycling endurance was exhibited. When the Ag film was located close to the Al electrode, the ON/OFF ratios and the retention time of this device decreased sharply and the bistable phenomenon almost disappeared. Our works show a simple approach to improve the performance of organic memory by adjusting the location of the metal film.

NVL-C: Static Analysis Techniques for Efficient, Correct Programming of Non-Volatile Main Memory Systems

Energy Technology Data Exchange (ETDEWEB)

Lee, Seyong [ORNL; Vetter, Jeffrey S [ORNL

2016-01-01

Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation in mind, we present NVL-C: a novel programming system that facilitates the efficient and correct programming of NVM main memory systems. The NVL-C programming abstraction extends C with a small set of intuitive language features that target NVM main memory, and can be combined directly with traditional C memory model features for DRAM. We have designed these new features to enable compiler analyses and run-time checks that can improve performance and guard against a number of subtle programming errors, which, when left uncorrected, can corrupt NVM-stored data. Moreover, to enable recovery of data across application or system failures, these NVL-C features include a flexible directive for specifying NVM transactions. So that our implementation might be extended to other compiler front ends and languages, the majority of our compiler analyses are implemented in an extended version of LLVM's intermediate representation (LLVM IR). We evaluate NVL-C on a number of applications to show its flexibility, performance, and correctness.

History and the future perspective of the ferroelectric memory; Kyoyudentai memory no rekishiteki haikei to tenbo

Energy Technology Data Exchange (ETDEWEB)

Tarui, Y [Waseda University, Tokyo (Japan)

1998-10-01

Development work is in progress on ferroelectric memory. The memory is a most suitable non-volatile memory which can be incorporated into IC cards, with its higher speed, lower voltage operation, smaller power consumption, and greater number of rewriting times than EEPROM, DRAM and SRAM. Taking as an opportunity the announcement on an experiment as performed by the authors to control semiconductor charge by using electric depolarization of ferroelectric materials, reports have been made one after another on experiments on thin metal films on TGS or BaTiO3, and experiments on semiconductor films formed on ferroelectric crystals or ceramics substrates by using vacuum deposition. In order to solve problems in ferroelectric materials, thin films of PZT and PLZT have emerged, whose good hysteresis characteristics have also been reported. Thereafter, an announcement was made on a material with bismuth layer like perovskite structure. The material is characterized with having very little film fatigue degradation after rewriting of about 10 {sup 12} times. In scaling a ferroelectric memory, if voltage is decreased in proportion with the size, the operation can be reduced proportionately according to the voltage reduction. This paper introduces a method to constitute a ferroelectric memory. 22 refs., 11 figs., 2 tabs.

Fabrication of Pb (Zr, Ti) O3 Thin Film for Non-Volatile Memory Device Application

International Nuclear Information System (INIS)

Mar Lar Win

2011-12-01

Ferroelectric lead zirconate titanate powder was composed of mainly the oxides of titanium, zirconium and lead. PZT powder was firstly prepared by thermal synthesis at different Zr/Ti ratios with various sintering temperatures. PZT thin film was fabricated on SiO2/Si substrate by using thermal evaporation method. Physical and elemental analysis were carried out by using SEM, EDX and XRD The ferroelectric properties and the switching behaviour of the PZT thin films were investigated. The ferroelectric properties and switching properties of the PZT thin film (near morphotropic phase boundary sintered at 800 C) could function as a nonvolatile memory.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

International Nuclear Information System (INIS)

Nedic, Stanko; Welland, Mark; Tea Chun, Young; Chu, Daping; Hong, Woong-Ki

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10 5 , a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10 4 s

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

Science.gov (United States)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Nonvolatile organic write-once-read-many-times memory devices based on hexadecafluoro-copper-phthalocyanine

Science.gov (United States)

Wang, Lidan; Su, Zisheng; Wang, Cheng

2012-05-01

Nonvolatile organic write-once-read-many-times memory device was demonstrated based on hexadecafluoro-copper-phthalocyanine (F16CuPc) single layer sandwiched between indium tin oxide (ITO) anode and Al cathode. The as fabricated device remains in ON state and it can be tuned to OFF state by applying a reverse bias. The ON/OFF current ratio of the device can reach up to 2.3 × 103. Simultaneously, the device shows long-term storage stability and long retention time in air. The ON/OFF transition is attributed to the formation and destruction of the interfacial dipole layer in the ITO/F16CuPc interface, and such a mechanism is different from previously reported ones.

75 FR 44283 - In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same...

Science.gov (United States)

2010-07-28

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-707] In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of a... importation of certain dynamic random access memory semiconductors and products containing same, including...

Nonvolatile memory characteristics influenced by the different crystallization of Ni-Si and Ni-N nanocrystals

International Nuclear Information System (INIS)

Chen, W.-R.; Yeh, J.-L.; Chang, C.-Y.; Chang, T.-C.; Chen, S.-C.

2008-01-01

The formation of Ni-Si and Ni-N nanocrystals by sputtering a Ni 0.3 Si 0.7 target in argon and nitrogen environment were proposed in this paper. A transmission electron microscope analysis shows the nanocrystals embedded in the nitride layer. X-ray photoelectron spectroscopy and x-ray diffraction also offer the chemical material analysis of nanocrystals with surrounding dielectric and the crystallization of nanocrystals for different thermal annealing treatments. Nonvolatile Ni-Si nanocrystal memories reveal superior electrical characteristics for charge storage capacity and reliability due to the improvement of thermal annealing treatment. In addition, we used energy band diagrams to explain the significance of surrounding dielectric for reliability

A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture

International Nuclear Information System (INIS)

Wu, Ming-Chi; Tseng, Tseung-Yuen; Jang, Wen-Yueh; Lin, Chen-Hsi

2012-01-01

Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO 2 /Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO 2 /Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO 2 -based RRAM is a prospective alternative for nonvolatile multilevel memory device applications. (paper)

High reliable and stable organic field-effect transistor nonvolatile memory with a poly(4-vinyl phenol) charge trapping layer based on a pn-heterojunction active layer

Energy Technology Data Exchange (ETDEWEB)

Xiang, Lanyi; Ying, Jun; Han, Jinhua; Zhang, Letian, E-mail: zlt@jlu.edu.cn, E-mail: wwei99@jlu.edu.cn; Wang, Wei, E-mail: zlt@jlu.edu.cn, E-mail: wwei99@jlu.edu.cn [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

2016-04-25

In this letter, we demonstrate a high reliable and stable organic field-effect transistor (OFET) based nonvolatile memory (NVM) with a polymer poly(4-vinyl phenol) (PVP) as the charge trapping layer. In the unipolar OFETs, the inreversible shifts of the turn-on voltage (V{sub on}) and severe degradation of the memory window (ΔV{sub on}) at programming (P) and erasing (E) voltages, respectively, block their application in NVMs. The obstacle is overcome by using a pn-heterojunction as the active layer in the OFET memory, which supplied a holes and electrons accumulating channel at the supplied P and E voltages, respectively. Both holes and electrons transferring from the channels to PVP layer and overwriting the trapped charges with an opposite polarity result in the reliable bidirectional shifts of V{sub on} at P and E voltages, respectively. The heterojunction OFET exhibits excellent nonvolatile memory characteristics, with a large ΔV{sub on} of 8.5 V, desired reading (R) voltage at 0 V, reliable P/R/E/R dynamic endurance over 100 cycles and a long retention time over 10 years.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

Science.gov (United States)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-07-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices.

Introduction to magnetic random-access memory

CERN Document Server

Dieny, Bernard; Lee, Kyung-Jin

2017-01-01

Magnetic random-access memory (MRAM) is poised to replace traditional computer memory based on complementary metal-oxide semiconductors (CMOS). MRAM will surpass all other types of memory devices in terms of nonvolatility, low energy dissipation, fast switching speed, radiation hardness, and durability. Although toggle-MRAM is currently a commercial product, it is clear that future developments in MRAM will be based on spin-transfer torque, which makes use of electrons’ spin angular momentum instead of their charge. MRAM will require an amalgamation of magnetics and microelectronics technologies. However, researchers and developers in magnetics and in microelectronics attend different technical conferences, publish in different journals, use different tools, and have different backgrounds in condensed-matter physics, electrical engineering, and materials science. This book is an introduction to MRAM for microelectronics engineers written by specialists in magnetic mat rials and devices. It presents the bas...

Different importance of the volatile and non-volatile fractions of an olfactory signature for individual social recognition in rats versus mice and short-term versus long-term memory.

Science.gov (United States)

Noack, Julia; Richter, Karin; Laube, Gregor; Haghgoo, Hojjat Allah; Veh, Rüdiger W; Engelmann, Mario

2010-11-01

When tested in the olfactory cued social recognition/discrimination test, rats and mice differ in their retention of a recognition memory for a previously encountered conspecific juvenile: Rats are able to recognize a given juvenile for approximately 45 min only whereas mice show not only short-term, but also long-term recognition memory (≥ 24 h). Here we modified the social recognition/social discrimination procedure to investigate the neurobiological mechanism(s) underlying the species differences. We presented a conspecific juvenile repeatedly to the experimental subjects and monitored the investigation duration as a measure for recognition. Presentation of only the volatile fraction of the juvenile olfactory signature was sufficient for both short- and long-term recognition in mice but not rats. Applying additional volatile, mono-molecular odours to the "to be recognized" juveniles failed to affect short-term memory in both species, but interfered with long-term recognition in mice. Finally immunocytochemical analysis of c-Fos as a marker for cellular activation, revealed that juvenile exposure stimulated areas involved in the processing of olfactory signals in both the main and the accessory olfactory bulb in mice. In rats, we measured an increased c-Fos synthesis almost exclusively in cells of the accessory olfactory bulb. Our data suggest that the species difference in the retention of social recognition memory is based on differences in the processing of the volatile versus non-volatile fraction of the individuals' olfactory signature. The non-volatile fraction is sufficient for retaining a short-term social memory only. Long-term social memory - as observed in mice - requires a processing of both the volatile and non-volatile fractions of the olfactory signature. Copyright © 2010 Elsevier Inc. All rights reserved.

Memory Effect on Adaptive Decision Making with a Chaotic Semiconductor Laser

Directory of Open Access Journals (Sweden)

Takatomo Mihana

2018-01-01

Full Text Available We investigate the effect of a memory parameter on the performance of adaptive decision making using a tug-of-war method with the chaotic oscillatory dynamics of a semiconductor laser. We experimentally generate chaotic temporal waveforms of the semiconductor laser with optical feedback and apply them for adaptive decision making in solving a multiarmed bandit problem that aims at maximizing the total reward from slot machines whose hit probabilities are dynamically switched. We examine the dependence of making correct decisions on different values of the memory parameter. The degree of adaptivity is found to be enhanced with a smaller memory parameter, whereas the degree of convergence to the correct decision is higher for a larger memory parameter. The relations among the adaptivity, environmental changes, and the difficulties of the problem are also discussed considering the requirement of past decisions. This examination of ultrafast adaptive decision making highlights the importance of memorizing past events and paves the way for future photonic intelligence.

Inkjet-printing of non-volatile organic resistive devices and crossbar array structures

Science.gov (United States)

Sax, Stefan; Nau, Sebastian; Popovic, Karl; Bluemel, Alexander; Klug, Andreas; List-Kratochvil, Emil J. W.

2015-09-01

Due to the increasing demand for storage capacity in various electronic gadgets like mobile phones or tablets, new types of non-volatile memory devices have gained a lot of attention over the last few years. Especially multilevel conductance switching elements based on organic semiconductors are of great interest due to their relatively simple device architecture and their small feature size. Since organic semiconductors combine the electronic properties of inorganic materials with the mechanical characteristics of polymers, this class of materials is suitable for solution based large area device preparation techniques. Consequently, inkjet based deposition techniques are highly capable of facing preparation related challenges. By gradually replacing the evaporated electrodes with inkjet printed silver, the preparation related influence onto device performance parameters such as the ON/OFF ratio was investigated with IV measurements and high resolution transmission electron microscopy. Due to the electrode surface roughness the solvent load during the printing of the top electrode as well as organic layer inhomogeneity's the utilization in array applications is hampered. As a prototypical example a 1diode-1resistor element and a 2×2 subarray from 5×5 array matrix were fully characterized demonstrating the versatility of inkjet printing for device preparation.

Four-state non-volatile memory in a multiferroic spin filter tunnel junction

Science.gov (United States)

Ruan, Jieji; Li, Chen; Yuan, Zhoushen; Wang, Peng; Li, Aidong; Wu, Di

2016-12-01

We report a spin filter type multiferroic tunnel junction with a ferromagnetic/ferroelectric bilayer barrier. Memory functions of a spin filter magnetic tunnel junction and a ferroelectric tunnel junction are combined in this single device, producing four non-volatile resistive states that can be read out in a non-destructive manner. This concept is demonstrated in a LaNiO3/Pr0.8Ca0.2MnO3/BaTiO3/La0.7Sr0.3MnO3 all-oxide tunnel junction. The ferromagnetic insulator Pr0.8Ca0.2MnO3 serves as the spin filter and the ferromagnetic metal La0.7Sr0.3MnO3 is the spin analyzer. The ferroelectric polarization reversal in the BaTiO3 barrier switches the tunneling barrier height to produce a tunneling electroresistance. The ferroelectric switching also modulates the spin polarization and the spin filtering efficiency in Pr0.8Ca0.2MnO3.

Non-volatile resistive switching in the Mott insulator (V1-xCrx)2O3

Science.gov (United States)

Querré, M.; Tranchant, J.; Corraze, B.; Cordier, S.; Bouquet, V.; Députier, S.; Guilloux-Viry, M.; Besland, M.-P.; Janod, E.; Cario, L.

2018-05-01

The discovery of non-volatile resistive switching in Mott insulators related to an electric-field-induced insulator to metal transition (IMT) has paved the way for their use in a new type of non-volatile memories, the Mott memories. While most of the previous studies were dedicated to uncover the resistive switching mechanism and explore the memory potential of chalcogenide Mott insulators, we present here a comprehensive study of resistive switching in the canonical oxide Mott insulator (V1-xCrx)2O3. Our work demonstrates that this compound undergoes a non-volatile resistive switching under electric field. This resistive switching is induced by a Mott transition at the local scale which creates metallic domains closely related to existing phases of the temperature-pressure phase diagram of (V1-xCrx)2O3. Our work demonstrates also reversible resistive switching in (V1-xCrx)2O3 crystals and thin film devices. Preliminary performances obtained on 880 nm thick layers with 500 nm electrodes show the strong potential of Mott memories based on the Mott insulator (V1-xCrx)2O3.

Air-stable memory array of bistable rectifying diodes based on ferroelectric-semiconductor polymer blends

Science.gov (United States)

Kumar, Manasvi; Sharifi Dehsari, Hamed; Anwar, Saleem; Asadi, Kamal

2018-03-01

Organic bistable diodes based on phase-separated blends of ferroelectric and semiconducting polymers have emerged as promising candidates for non-volatile information storage for low-cost solution processable electronics. One of the bottlenecks impeding upscaling is stability and reliable operation of the array in air. Here, we present a memory array fabricated with an air-stable amine-based semiconducting polymer. Memory diode fabrication and full electrical characterizations were carried out in atmospheric conditions (23 °C and 45% relative humidity). The memory diodes showed on/off ratios greater than 100 and further exhibited robust and stable performance upon continuous write-read-erase-read cycles. Moreover, we demonstrate a 4-bit memory array that is free from cross-talk with a shelf-life of several months. Demonstration of the stability and reliable air operation further strengthens the feasibility of the resistance switching in ferroelectric memory diodes for low-cost applications.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

Science.gov (United States)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-01-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

Hybrid dual gate ferroelectric memory for multilevel information storage

KAUST Repository

Khan, Yasser

2015-01-01

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200°C), and demonstrate excellent performance with high hole mobility of 2.7 cm2 V-1 s-1, large memory window of ∼18 V, and a low sub-threshold swing ∼-4 V dec-1. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.

75 FR 20564 - Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit...

Science.gov (United States)

2010-04-20

... DEPARTMENT OF COMMERCE International Trade Administration [C-580-851] Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit for Preliminary Results of Countervailing Duty... access memory semiconductors from the Republic of Korea, covering the period January 1, 2008 through...

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

Science.gov (United States)

Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

2017-08-01

In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

Science.gov (United States)

Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

2015-09-01

Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

Nonvolatile resistive switching in Pt/laALO3/srTiO3 heterostructures

KAUST Repository

Wu, S.

2013-12-12

Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO3/SrTiO3 heterostructures, where the conducting layer near the LaAlO3/SrTiO3 interface serves as the "unconventional"bottom electrode although both oxides are band insulators. Interestingly, the switching between low-resistance and high-resistance states is accompanied by reversible transitions between tunneling and Ohmic characteristics in the current transport perpendicular to the planes of the heterojunctions. We propose that the observed resistive switching is likely caused by the electric-field-induced drift of charged oxygen vacancies across the LaAlO3/SrTiO3 interface and the creation of defect-induced gap states within the ultrathin LaAlO3 layer. These metal-oxide-oxide heterojunctions with atomically smooth interfaces and defect-controlled transport provide a platform for the development of nonvolatile oxide nanoelectronics that integrate logic and memory devices.

Electric-Field-Driven Dual Vacancies Evolution in Ultrathin Nanosheets Realizing Reversible Semiconductor to Half-Metal Transition.

Science.gov (United States)

Lyu, Mengjie; Liu, Youwen; Zhi, Yuduo; Xiao, Chong; Gu, Bingchuan; Hua, Xuemin; Fan, Shaojuan; Lin, Yue; Bai, Wei; Tong, Wei; Zou, Youming; Pan, Bicai; Ye, Bangjiao; Xie, Yi

2015-12-02

Fabricating a flexible room-temperature ferromagnetic resistive-switching random access memory (RRAM) device is of fundamental importance to integrate nonvolatile memory and spintronics both in theory and practice for modern information technology and has the potential to bring about revolutionary new foldable information-storage devices. Here, we show that a relatively low operating voltage (+1.4 V/-1.5 V, the corresponding electric field is around 20,000 V/cm) drives the dual vacancies evolution in ultrathin SnO2 nanosheets at room temperature, which causes the reversible transition between semiconductor and half-metal, accompanyied by an abrupt conductivity change up to 10(3) times, exhibiting room-temperature ferromagnetism in two resistance states. Positron annihilation spectroscopy and electron spin resonance results show that the Sn/O dual vacancies in the ultrathin SnO2 nanosheets evolve to isolated Sn vacancy under electric field, accounting for the switching behavior of SnO2 ultrathin nanosheets; on the other hand, the different defect types correspond to different conduction natures, realizing the transition between semiconductor and half-metal. Our result represents a crucial step to create new a information-storage device realizing the reversible transition between semiconductor and half-metal with flexibility and room-temperature ferromagnetism at low energy consumption. The as-obtained half-metal in the low-resistance state broadens the application of the device in spintronics and the semiconductor to half-metal transition on the basis of defects evolution and also opens up a new avenue for exploring random access memory mechanisms and finding new half-metals for spintronics.

Coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO3/In memristive devices

International Nuclear Information System (INIS)

Yang, M; Bao, D H; Li, S W

2013-01-01

Memristive devices are triggering innovations in the fields of nonvolatile memory, digital logic, analogue circuits, neuromorphic engineering, and so on. Creating new memristive devices with unique characteristics would be significant for these emergent applications. Here we report the coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO 3 (NSTO)/In memristive devices. The Pt/NSTO interface contributes a nonvolatile resistive switching behaviour, whereas the NSTO/In interface displays a volatile hysteresis loop. Combining the two interfaces in the Pt/NSTO/In devices leads to the unique coexistence of nonvolatility and volatility. The results imply more opportunities to invent new memristive devices by engineering both interfaces in metal/insulator/metal structures. (paper)

76 FR 2336 - Dynamic Random Access Memory Semiconductors From the Republic of Korea: Final Results of...

Science.gov (United States)

2011-01-13

... Semiconductors From the Republic of Korea: Final Results of Countervailing Duty Administrative Review AGENCY... administrative review of the countervailing duty order on dynamic random access memory semiconductors from the... to a change in the net subsidy rate. The final net subsidy rate for Hynix Semiconductor, Inc. is...

Contamination aspects in integrating high dielectric constant and ferroelectric materials into CMOS processes

OpenAIRE

Boubekeur, Hocine

2004-01-01

n memory technology, new materials are being intensively investigated to overcome the integration limits of conventional dielectrics for Giga-bit scale integration, or to be able to produce new types of non-volatile low power memories such as FeRAM. Perovskite type high dielectric constant films for use in Giga-bit scale memories or layered perovskite films for use in non-volatile memories involve materials to semiconductor process flows, which entail a high risk of contamination. The introdu...

Field testing for cosmic ray soft errors in semiconductor memories

International Nuclear Information System (INIS)

O'Gorman, T.J.; Ross, J.M.; Taber, A.H.; Ziegler, J.F.; Muhlfeld, H.P.; Montrose, C.J.; Curtis, H.W.; Walsh, J.L.

1996-01-01

This paper presents a review of experiments performed by IBM to investigate the causes of soft errors in semiconductor memory chips under field test conditions. The effects of alpha-particles and cosmic rays are separated by comparing multiple measurements of the soft-error rate (SER) of samples of memory chips deep underground and at various altitudes above the earth. The results of case studies on four different memory chips show that cosmic rays are an important source of the ionizing radiation that causes soft errors. The results of field testing are used to confirm the accuracy of the modeling and the accelerated testing of chips

Atomic layer-deposited Al–HfO{sub 2}/SiO{sub 2} bi-layers towards 3D charge trapping non-volatile memory

Energy Technology Data Exchange (ETDEWEB)

Congedo, Gabriele, E-mail: gabriele.congedo@mdm.imm.cnr.it; Wiemer, Claudia; Lamperti, Alessio; Cianci, Elena; Molle, Alessandro; Volpe, Flavio G.; Spiga, Sabina, E-mail: sabina.spiga@mdm.imm.cnr

2013-04-30

A metal/oxide/high-κ dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO{sub 2} as tunnel oxide, Al–HfO{sub 2} as charge trapping layer, SiO{sub 2} as blocking oxide and TaN metal gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900 °C in N{sub 2}, as required for standard complementary metal–oxide–semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of ± 20 V to ± 12 V. When compared to a benchmark structure including thin Si{sub 3}N{sub 4} as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (κ) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-κ based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices. - Highlights: ► Charge trapping device with Al–HfO{sub 2} storage layer is fabricated and characterized. ► Al–HfO{sub 2} and SiO{sub 2} blocking oxides are deposited by atomic layer deposition. ► The oxide stack shows a good thermal stability after annealing at 900 °C. ► The device can be efficiently programmed/erased and retention is excellent. ► The oxide stack could be used for 3D-stacked Flash non-volatile memories.

Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

Science.gov (United States)

Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

2009-01-01

We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Chi, Li-Feng, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn [Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

2015-03-23

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

International Nuclear Information System (INIS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-01-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process

Non-exponential resistive switching in Ag2S memristors: a key to nanometer-scale non-volatile memory devices.

Science.gov (United States)

Gubicza, Agnes; Csontos, Miklós; Halbritter, András; Mihály, György

2015-03-14

The dynamics of resistive switchings in nanometer-scale metallic junctions formed between an inert metallic tip and an Ag film covered by a thin Ag2S layer are investigated. Our thorough experimental analysis and numerical simulations revealed that the resistance change upon a switching bias voltage pulse exhibits a strongly non-exponential behaviour yielding markedly different response times at different bias levels. Our results demonstrate the merits of Ag2S nanojunctions as nanometer-scale non-volatile memory cells with stable switching ratios, high endurance as well as fast response to write/erase, and an outstanding stability against read operations at technologically optimal bias and current levels.

Nonvolatile Resistive Switching in Pt/LaAlO_{3}/SrTiO_{3} Heterostructures

Directory of Open Access Journals (Sweden)

Shuxiang Wu

2013-12-01

Full Text Available Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO_{3}/SrTiO_{3} heterostructures, where the conducting layer near the LaAlO_{3}/SrTiO_{3} interface serves as the “unconventional” bottom electrode although both oxides are band insulators. Interestingly, the switching between low-resistance and high-resistance states is accompanied by reversible transitions between tunneling and Ohmic characteristics in the current transport perpendicular to the planes of the heterojunctions. We propose that the observed resistive switching is likely caused by the electric-field-induced drift of charged oxygen vacancies across the LaAlO_{3}/SrTiO_{3} interface and the creation of defect-induced gap states within the ultrathin LaAlO_{3} layer. These metal-oxide-oxide heterojunctions with atomically smooth interfaces and defect-controlled transport provide a platform for the development of nonvolatile oxide nanoelectronics that integrate logic and memory devices.

Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

Science.gov (United States)

Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

2017-10-01

The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

Emerging memory technologies design, architecture, and applications

CERN Document Server

2014-01-01

This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits. • Provides a comprehensive reference on designing modern circuits with emerging, non-volatile memory technologies, such as MRAM and PCRAM; • Explores new design opportunities offered by emerging memory technologies, from a holistic perspective; • Describes topics in technology, modeling, architecture and applications; • Enables circuit designers to ex...

Effects of annealing temperature in a metal alloy nano-dot memory

International Nuclear Information System (INIS)

Lee, Jung Min; Lee, Gae Hun; Song, Yun Heub; Bea, Ji Cheol; Tanaka, Tetsu

2011-01-01

The annealing temperature dependence of the capacitance-voltage (C-V) characteristic has been studied in a metal-oxide semiconductor structure containing FePt nano-dots. Several in-situ annealing temperatures from 400 to ∼700 .deg. C in a high vacuum ambience (under 1 x 10 -5 Pa) were evaluated in view of the cell's characteristics and its reliability. Here, we demonstrate that the annealing temperature is significant for memory performance in an alloy metal nano-dot structure. A higher in-situ temperature provides better retention and a more reliable memory window. In the sample with an in-situ annealing condition of 700 .deg. C for 30 min, a memory window of 9.2 V at the initial stage was obtained, and a memory window of 6.2 V after 10 years was estimated, which is reliable for a non-volatile memory. From these results, the annealing condition for an alloy metal nano-dot memory is one of the critical parameters for the memory characteristics, and should be optimized for better memory performance.

Multistate nonvolatile straintronics controlled by a lateral electric field.

Science.gov (United States)

Iurchuk, V; Doudin, B; Kundys, B

2014-07-23

We present a multifunctional and multistate permanent memory device based on lateral electric field control of a strained surface. Sub-coercive electrical writing of a remnant strain of a PZT substrate imprints stable and rewritable resistance changes on a CoFe overlayer. A proof-of-principle device, with the simplest resistance strain gage design, is shown as a memory cell exhibiting 17-memory states of high reproducibility and reliability for nonvolatile operations. Magnetoresistance of the film also depends on the cell state, and indicates a rewritable change of magnetic properties persisting in the remnant strain of the substrate. This makes it possible to combine strain, magnetic and resistive functionalities in a single memory element, and suggests that sub-coercive stress studies are of interest for straintronics applications.

Non-volatile nano-floating gate memory with Pt-Fe{sub 2}O{sub 3} composite nanoparticles and indium gallium zinc oxide channel

Energy Technology Data Exchange (ETDEWEB)

Hu, Quanli [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Lee, Seung Chang; Baek, Yoon-Jae [Myongji University, Department of Materials Science and Engineering (Korea, Republic of); Lee, Hyun Ho [Myongji University, Department of Chemical Engineering (Korea, Republic of); Kang, Chi Jung [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Kim, Hyun-Mi; Kim, Ki-Bum [Seoul National University, Department of Materials Science and Engineering (Korea, Republic of); Yoon, Tae-Sik, E-mail: tsyoon@mju.ac.kr [Myongji University, Department of Nano Science and Engineering (Korea, Republic of)

2013-02-15

Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe{sub 2}O{sub 3} composite nanoparticles with a mostly core-shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe{sub 2}O{sub 3} nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles' layer could be formed with a density of {approx}3 Multiplication-Sign 10{sup 11} cm{sup -2} by a solution-based dip-coating process. The Pt core ({approx}3 nm in diameter) and Fe{sub 2}O{sub 3}-shell ({approx}6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current-voltage measurement with a threshold voltage shift of {approx}4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of {approx}0.66 V after pulse programming at +20 V for 1 s with retention > {approx}65 % after 10{sup 4} s. These results demonstrate the feasibility of using colloidal nanoparticles with core-shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

Graphene-based hybrid structures combined with functional materials of ferroelectrics and semiconductors.

Science.gov (United States)

Jie, Wenjing; Hao, Jianhua

2014-06-21

Fundamental studies and applications of 2-dimensional (2D) graphene may be deepened and broadened via combining graphene sheets with various functional materials, which have been extended from the traditional insulator of SiO2 to a versatile range of dielectrics, semiconductors and metals, as well as organic compounds. Among them, ferroelectric materials have received much attention due to their unique ferroelectric polarization. As a result, many attractive characteristics can be shown in graphene/ferroelectric hybrid systems. On the other hand, graphene can be integrated with conventional semiconductors and some newly-discovered 2D layered materials to form distinct Schottky junctions, yielding fascinating behaviours and exhibiting the potential for various applications in future functional devices. This review article is an attempt to illustrate the most recent progress in the fabrication, operation principle, characterization, and promising applications of graphene-based hybrid structures combined with various functional materials, ranging from ferroelectrics to semiconductors. We focus on mechanically exfoliated and chemical-vapor-deposited graphene sheets integrated in numerous advanced devices. Some typical hybrid structures have been highlighted, aiming at potential applications in non-volatile memories, transparent flexible electrodes, solar cells, photodetectors, and so on.

Multistate storage nonvolatile memory device based on ferroelectricity and resistive switching effects of SrBi2Ta2O9 films

Science.gov (United States)

Song, Zhiwei; Li, Gang; Xiong, Ying; Cheng, Chuanpin; Zhang, Wanli; Tang, Minghua; Li, Zheng; He, Jiangheng

2018-05-01

A memory device with a Pt/SrBi2Ta2O9(SBT)/Pt(111) structure was shown to have excellent combined ferroelectricity and resistive switching properties, leading to higher multistate storage memory capacity in contrast to ferroelectric memory devices. In this device, SBT polycrystalline thin films with significant (115) orientation were fabricated on Pt(111)/Ti/SiO2/Si(100) substrates using CVD (chemical vapor deposition) method. Measurement results of the electric properties exhibit reproducible and reliable ferroelectricity switching behavior and bipolar resistive switching effects (BRS) without an electroforming process. The ON/OFF ratio of the resistive switching was found to be about 103. Switching mechanisms for the low resistance state (LRS) and high resistance state (HRS) currents are likely attributed to the Ohmic and space charge-limited current (SCLC) behavior, respectively. Moreover, the ferroelectricity and resistive switching effects were found to be mutually independent, and the four logic states were obtained by controlling the periodic sweeping voltage. This work holds great promise for nonvolatile multistate memory devices with high capacity and low cost.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

Science.gov (United States)

Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

2014-09-01

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm2/V s. The unidirectional shift of turn-on voltage (Von) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (VP/VE) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm2/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the VP/VE of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional Von shift. As a result, an enlarged memory window of 28.6 V at the VP/VE of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

Organic nonvolatile resistive memory devices based on thermally deposited Au nanoparticle

Science.gov (United States)

Jin, Zhiwen; Liu, Guo; Wang, Jizheng

2013-05-01

Uniform Au nanoparticles (NPs) are formed by thermally depositing nominal 2-nm thick Au film on a 10-nm thick polyimide film formed on a Al electrode, and then covered by a thin polymer semiconductor film, which acts as an energy barrier for electrons to be injected from the other Al electrode (on top of polymer film) into the Au NPs, which are energetically electron traps in such a resistive random access memory (RRAM) device. The Au NPs based RRAM device exhibits estimated retention time of 104 s, cycle times of more than 100, and ON-OFF ratio of 102 to 103. The carrier transport properties are also analyzed by fitting the measured I-V curves with several conduction models.

Low temperature synthesis and electrical characterization of germanium doped Ti-based nanocrystals for nonvolatile memory

International Nuclear Information System (INIS)

Feng, Li-Wei; Chang, Chun-Yen; Chang, Ting-Chang; Tu, Chun-Hao; Wang, Pai-Syuan; Lin, Chao-Cheng; Chen, Min-Chen; Huang, Hui-Chun; Gan, Der-Shin; Ho, New-Jin; Chen, Shih-Ching; Chen, Shih-Cheng

2011-01-01

Chemical and electrical characteristics of Ti-based nanocrystals containing germanium, fabricated by annealing the co-sputtered thin film with titanium silicide and germanium targets, were demonstrated for low temperature applications of nonvolatile memory. Formation and composition characteristics of nanocrystals (NCs) at various annealing temperatures were examined by transmission electron microscopy and X-ray photon-emission spectroscopy, respectively. It was observed that the addition of germanium (Ge) significantly reduces the proposed thermal budget necessary for Ti-based NC formation due to the rise of morphological instability and agglomeration properties during annealing. NC structures formed after annealing at 500 °C, and separated well at 600 °C annealing. However, it was also observed that significant thermal desorption of Ge atoms occurs at 600 °C due to the sublimation of formatted GeO phase and results in a serious decrease of memory window. Therefore, an approach to effectively restrain Ge thermal desorption is proposed by encapsulating the Ti-based trapping layer with a thick silicon oxide layer before 600 °C annealing. The electrical characteristics of data retention in the sample with the 600 °C annealing exhibited better performance than the 500 °C-annealed sample, a result associated with the better separation and better crystallization of the NC structures.

Multistate nonvolatile straintronics controlled by a lateral electric field

International Nuclear Information System (INIS)

Iurchuk, V; Doudin, B; Kundys, B

2014-01-01

We present a multifunctional and multistate permanent memory device based on lateral electric field control of a strained surface. Sub-coercive electrical writing of a remnant strain of a PZT substrate imprints stable and rewritable resistance changes on a CoFe overlayer. A proof-of-principle device, with the simplest resistance strain gage design, is shown as a memory cell exhibiting 17-memory states of high reproducibility and reliability for nonvolatile operations. Magnetoresistance of the film also depends on the cell state, and indicates a rewritable change of magnetic properties persisting in the remnant strain of the substrate. This makes it possible to combine strain, magnetic and resistive functionalities in a single memory element, and suggests that sub-coercive stress studies are of interest for straintronics applications. (fast track communication)

A study of selenium nanoparticles as charge storage element for flexible semi-transparent memory devices

Science.gov (United States)

Alotaibi, Sattam; Nama Manjunatha, Krishna; Paul, Shashi

2017-12-01

Flexible Semi-Transparent electronic memory would be useful in coming years for integrated flexible transparent electronic devices. However, attaining such flexibility and semi-transparency leads to the boundaries in material composition. Thus, impeding processing speed and device performance. In this work, we present the use of inorganic stable selenium nanoparticles (Se-NPs) as a storage element and hydrogenated amorphous carbon (a-C:H) as an insulating layer in two terminal non-volatile physically flexible and semi-transparent capacitive memory devices (2T-NMDs). Furthermore, a-C:H films can be deposited at very low temperature (industrial technique called Plasma Enhanced Chemical Vapour Deposition (PECVD) which is available in many existing fabrication labs. Self-assembled Se-NPs has several unique features including deposition at room temperature by simple vacuum thermal evaporation process without the need for further optimisation. This facilitates the fabrication of memory on a flexible substrate. Moreover, the memory behaviour of the Se-NPs was found to be more distinct than those of the semiconductor and metal nanostructures due to higher work function compared to the commonly used semiconductor and metal species. The memory behaviour was observed from the hysteresis of current-voltage (I-V) measurements while the two distinguishable electrical conductivity states (;0; and "1") were studied by current-time (I-t) measurements.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

Science.gov (United States)

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

Science.gov (United States)

Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

2012-11-01

We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

International Nuclear Information System (INIS)

Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

2014-01-01

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm 2 /V s. The unidirectional shift of turn-on voltage (V on ) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V P /V E ) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm 2 /V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V P /V E of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V on shift. As a result, an enlarged memory window of 28.6 V at the V P /V E of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

Directory of Open Access Journals (Sweden)

Luís Vitório Cargnini

2014-08-01

Full Text Available Static random access memory (SRAM is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications

International Nuclear Information System (INIS)

Zhang Junyu; Wang Yong; Liu Jing; Zhang Manhong; Xu Zhongguang; Huo Zongliang; Liu Ming

2012-01-01

We introduce a novel 2 T P-channel nano-crystal memory structure for low power and high speed embedded non-volatile memory (NVM) applications. By using the band-to-band tunneling-induced hot-electron (BTBTIHE) injection scheme, both high-speed and low power programming can be achieved at the same time. Due to the use of a select transistor, the 'erased states' can be set to below 0 V, so that the periphery HV circuit (high-voltage generating and management) and read-out circuit can be simplified. Good memory cell performance has also been achieved, including a fast program/erase (P/E) speed (a 1.15 V memory window under 10 μs program pulse), an excellent data retention (only 20% charge loss for 10 years). The data shows that the device has strong potential for future embedded NVM applications. (semiconductor devices)

Non-volatile MOS RAM cell with capacitor-isolated nodes that are radiation accessible for rendering a non-permanent programmed information in the cell of a non-volatile one

NARCIS (Netherlands)

Widdershoven, Franciscus P.; Annema, Anne J.; Storms, Maurits M.N.; Pelgrom, Marcellinus J.M.; Pelgrom, Marcel J M

2001-01-01

A non-volatile, random access memory cell comprises first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a MOS RAM cell. The output node of each inverter is selectively connected via the conductor paths of

Reducing the influence of STI on SONOS memory through optimizing added boron implantation technology

International Nuclear Information System (INIS)

Xu Yue; Yan Feng; Li Zhiguo; Yang Fan; Wang Yonggang; Chang Jianguang

2010-01-01

The influence of shallow trench isolation (STI) on a 90 nm polysilicon-oxide-nitride-oxide-silicon structure non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology. (semiconductor devices)

Novel Organic Phototransistor-Based Nonvolatile Memory Integrated with UV-Sensing/Green-Emissive Aggregation Enhanced Emission (AEE)-Active Aromatic Polyamide Electret Layer.

Science.gov (United States)

Cheng, Shun-Wen; Han, Ting; Huang, Teng-Yung; Chang Chien, Yu-Hsin; Liu, Cheng-Liang; Tang, Ben Zhong; Liou, Guey-Sheng

2018-05-30

A novel aggregation enhanced emission (AEE)-active polyamide TPA-CN-TPE with a high photoluminesence characteristic was successfully synthesized by the direct polymerization of 4-cyanotriphenyl diamine (TPA-CN) and tetraphenylethene (TPE)-containing dicarboxylic acid. The obtained luminescent polyamide plays a significant role as the polymer electret layer in organic field-effect transistors (OFETs)-type memory. The strong green emission of TPA-CN-TPE under ultraviolet (UV) irradiation can be directly absorbed by the pentacene channel, displaying a light-induced programming and voltage-driven erasing organic phototransistor-based nonvolatile memory. Memory window can be effectively manipulated between the programming and erasing states by applying UV light illumination and electrical field, respectively. The photoinduced memory behavior can be maintained for over 10 4 s between these two states with an on/off ratio of 10 4 , and the memory switching can be steadily operated for many cycles. With high photoresponsivity ( R) and photosensitivity ( S), this organic phototransistor integrated with AEE-active polyamide electret layer could serve as an excellent candidate for UV photodetectors in optical applications. For comparison, an AEE-inactive aromatic polyimide TPA-PIS electret with much weaker solid-state emission was also applied in the same OFETs device architecture, but this device did not show any UV-sensitive and UV-induced memory characteristics, which further confirmed the significance of the light-emitting capability of the electret layer.

Electrical bistabilities and memory stabilities of nonvolatile bistable devices fabricated utilizing C60 molecules embedded in a polymethyl methacrylate layer

International Nuclear Information System (INIS)

Cho, Sung Hwan; Lee, Dong Ik; Jung, Jae Hun; Kim, Tae Whan

2009-01-01

Current-voltage (I-V) measurements on Al/fullerene (C 60 ) molecules embedded in polymethyl methacrylate/Al devices at 300 K showed a current bistability due to the existence of the C 60 molecules. The on/off ratio of the current bistability for the memory devices was as large as 10 3 . The retention time of the devices was above 2.5 x 10 4 s at room temperature, and cycling endurance tests on these devices indicated that the ON and OFF currents showed no degradation until 50 000 cycles. Carrier transport mechanisms for the nonvolatile bistable devices are described on the basis of the I-V experimental and fitting results.

Investigations of Photovoltaic Ferroelectric-Semiconductor Nonvolatile Memory.

Science.gov (United States)

1981-03-01

HEWLETT-PACKARD BOX 3310 100 MARKET ST APT 1 3404 EAST HARMONY RD2U ATTN J. M. KIRSCH, MTS ATTN R. SCHAEFER ATTN L. W. JAMES, MTS FULLERTON, CA 92633...RADIO SYS SPERRY UNICORN 1300 S ROGERS 367 ORCHARD STREET 52-21 65 PL AT’rN J. F. PRATHER, MGR CEN ATTN I. A. PAULL, ES ATTN W. BURSTEIN, ENGR

Bipolar resistive switching in graphene oxide based metal insulator metal structure for non-volatile memory applications

Science.gov (United States)

Singh, Rakesh; Kumar, Ravi; Kumar, Anil; Kashyap, Rajesh; Kumar, Mukesh; Kumar, Dinesh

2018-05-01

Graphene oxide based devices have attracted much attention recently because of their possible application in next generation electronic devices. In this study, bipolar resistive switching characteristics of graphene oxide based metal insulator metal structure were investigated for nonvolatile memories. The graphene oxide was prepared by the conventional Hummer's method and deposited on ITO coated glass by spin-coating technique. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament inside the graphene oxide. The conduction mechanism for low and high resistance states are dominated by two mechanism the ohmic conduction and space charge limited current (SCLC) mechanism, respectively. Atomic Force Microscopy, X-ray diffraction, Cyclic-Voltammetry were conducted to observe the morphology, structure and behavior of the material. The fabricated device with Al/GO/ITO structure exhibited reliable bipolar resistive switching with set & reset voltage of -2.3 V and 3V respectively.

Electrical bistabilities and memory mechanisms of nonvolatile organic bistable devices based on exfoliated muscovite-type mica nanoparticle/poly(methylmethacrylate) nanocomposites

Science.gov (United States)

Lim, Won Gyu; Lee, Dea Uk; Na, Han Gil; Kim, Hyoun Woo; Kim, Tae Whan

2018-02-01

Organic bistable devices (OBDs) with exfoliated mica nanoparticles (NPs) embedded into an insulating poly(methylmethacrylate) (PMMA) layer were fabricated by using a spin-coating method. Current-voltage (I-V) curves for the Al/PMMA/exfoliated mica NP/PMMA/indium-tin-oxide/glass devices at 300 K showed a clockwise current hysteresis behavior due to the existence of the exfoliated muscovite-type mica NPs, which is an essential feature for bistable devices. Write-read-erase-read data showed that the OBDs had rewritable nonvolatile memories and an endurance number of ON/OFF switching for the OBDs of 102 cycles. An ON/OFF ratio of 1 × 103 was maintained for retention times larger than 1 × 104 s. The memory mechanisms of the fabricated OBDs were described by using the trapping and the tunneling processes within a PMMA active layer containing exfoliated muscovite-type mica NPs on the basis of the energy band diagram and the I-V curves.

High-performance solution-processed polymer ferroelectric field-effect transistors

NARCIS (Netherlands)

Naber, RCG; Tanase, C; Blom, PWM; Gelinck, GH; Marsman, AW; Touwslager, FJ; Setayesh, S; De Leeuw, DM; Naber, Ronald C.G.; Gelinck, Gerwin H.; Marsman, Albert W.; Touwslager, Fred J.

We demonstrate a rewritable, non-volatile memory device with flexible plastic active layers deposited from solution. The memory device is a ferroelectric field-effect transistor (FeFET) made with a ferroelectric fluoropolymer and a bisalkoxy-substituted poly(p-phenylene vinylene) semiconductor

Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

International Nuclear Information System (INIS)

Son, Dang Ngoc; Van Duy, Nguyen; Jung, Sungwook; Yi, Junsin

2010-01-01

Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiN x films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application

Empirical study of the metal-nitride-oxide-semiconductor device characteristics deduced from a microscopic model of memory traps

International Nuclear Information System (INIS)

Ngai, K.L.; Hsia, Y.

1982-01-01

A graded-nitride gate dielectric metal-nitride-oxide-semiconductor (MNOS) memory transistor exhibiting superior device characteristics is presented and analyzed based on a qualitative microscopic model of the memory traps. The model is further reviewed to interpret some generic properties of the MNOS memory transistors including memory window, erase-write speed, and the retention-endurance characteristic features

Modeling and simulation of floating gate nanocrystal FET devices and circuits

Science.gov (United States)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

Boost Up Carrier Mobility for Ferroelectric Organic Transistor Memory via Buffering Interfacial Polarization Fluctuation

Science.gov (United States)

Sun, Huabin; Wang, Qijing; Li, Yun; Lin, Yen-Fu; Wang, Yu; Yin, Yao; Xu, Yong; Liu, Chuan; Tsukagoshi, Kazuhito; Pan, Lijia; Wang, Xizhang; Hu, Zheng; Shi, Yi

2014-11-01

Ferroelectric organic field-effect transistors (Fe-OFETs) have been attractive for a variety of non-volatile memory device applications. One of the critical issues of Fe-OFETs is the improvement of carrier mobility in semiconducting channels. In this article, we propose a novel interfacial buffering method that inserts an ultrathin poly(methyl methacrylate) (PMMA) between ferroelectric polymer and organic semiconductor layers. A high field-effect mobility (μFET) up to 4.6 cm2 V-1 s-1 is obtained. Subsequently, the programming process in our Fe-OFETs is mainly dominated by the switching between two ferroelectric polarizations rather than by the mobility-determined charge accumulation at the channel. Thus, the ``reading'' and ``programming'' speeds are significantly improved. Investigations show that the polarization fluctuation at semiconductor/insulator interfaces, which affect the charge transport in conducting channels, can be suppressed effectively using our method.

Resistive switching effect of N-doped MoS2-PVP nanocomposites films for nonvolatile memory devices

Science.gov (United States)

Wu, Zijin; Wang, Tongtong; Sun, Changqi; Liu, Peitao; Xia, Baorui; Zhang, Jingyan; Liu, Yonggang; Gao, Daqiang

2017-12-01

Resistive memory technology is very promising in the field of semiconductor memory devices. According to Liu et al, MoS2-PVP nanocomposite can be used as an active layer material for resistive memory devices due to its bipolar resistive switching behavior. Recent studies have also indicated that the doping of N element can reduce the band gap of MoS2 nanosheets, which is conducive to improving the conductivity of the material. Therefore, in this paper, we prepared N-doped MoS2 nanosheets and then fabricated N-doped MoS2-PVP nanocomposite films by spin coating. Finally, the resistive memory [C. Tan et al., Chem. Soc. Rev. 44, 2615 (2015)], device with ITO/N-doped MoS2-PVP/Pt structure was fabricated. Study on the I-V characteristics shows that the device has excellent resistance switching effect. It is worth mentioning that our device possesses a threshold voltage of 0.75 V, which is much better than 3.5 V reported previously for the undoped counterparts. The above research shows that N-doped MoS2-PVP nanocomposite films can be used as the active layer of resistive switching memory devices, and will make the devices have better performance.

Rotator side chains trigger cooperative transition for shape and function memory effect in organic semiconductors.

Science.gov (United States)

Chung, Hyunjoong; Dudenko, Dmytro; Zhang, Fengjiao; D'Avino, Gabriele; Ruzié, Christian; Richard, Audrey; Schweicher, Guillaume; Cornil, Jérôme; Beljonne, David; Geerts, Yves; Diao, Ying

2018-01-18

Martensitic transition is a solid-state phase transition involving cooperative movement of atoms, mostly studied in metallurgy. The main characteristics are low transition barrier, ultrafast kinetics, and structural reversibility. They are rarely observed in molecular crystals, and hence the origin and mechanism are largely unexplored. Here we report the discovery of martensitic transition in single crystals of two different organic semiconductors. In situ microscopy, single-crystal X-ray diffraction, Raman and nuclear magnetic resonance spectroscopy, and molecular simulations combined indicate that the rotating bulky side chains trigger cooperative transition. Cooperativity enables shape memory effect in single crystals and function memory effect in thin film transistors. We establish a molecular design rule to trigger martensitic transition in organic semiconductors, showing promise for designing next-generation smart multifunctional materials.

Silicon integrated circuits part A : supplement 2

CERN Document Server

Kahng, Dawon

1981-01-01

Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

Single electron-spin memory with a semiconductor quantum dot

International Nuclear Information System (INIS)

Young, Robert J; Dewhurst, Samuel J; Stevenson, R Mark; Atkinson, Paola; Bennett, Anthony J; Ward, Martin B; Cooper, Ken; Ritchie, David A; Shields, Andrew J

2007-01-01

We show storage of the circular polarization of an optical field, transferring it to the spin-state of an individual electron confined in a single semiconductor quantum dot. The state is subsequently read out through the electronically-triggered emission of a single photon. The emitted photon shares the same polarization as the initial pulse but has a different energy, making the transfer of quantum information between different physical systems possible. With an applied magnetic field of 2 T, spin memory is preserved for at least 1000 times more than the exciton's radiative lifetime

Transparent Memory For Harsh Electronics

KAUST Repository

Ho, C. H.; Duran Retamal, Jose Ramon; Yang, P. K.; Lee, C. P.; Tsai, M. L.; Kang, C. F.; He, Jr-Hau

2017-01-01

As a new class of non-volatile memory, resistive random access memory (RRAM) offers not only superior electronic characteristics, but also advanced functionalities, such as transparency and radiation hardness. However, the environmental tolerance

Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

Science.gov (United States)

Zand, Ramtin; DeMara, Ronald F.

2017-12-01

In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

International Nuclear Information System (INIS)

Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

2009-01-01

Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

Simple Atomic Quantum Memory Suitable for Semiconductor Quantum Dot Single Photons

Science.gov (United States)

Wolters, Janik; Buser, Gianni; Horsley, Andrew; Béguin, Lucas; Jöckel, Andreas; Jahn, Jan-Philipp; Warburton, Richard J.; Treutlein, Philipp

2017-08-01

Quantum memories matched to single photon sources will form an important cornerstone of future quantum network technology. We demonstrate such a memory in warm Rb vapor with on-demand storage and retrieval, based on electromagnetically induced transparency. With an acceptance bandwidth of δ f =0.66 GHz , the memory is suitable for single photons emitted by semiconductor quantum dots. In this regime, vapor cell memories offer an excellent compromise between storage efficiency, storage time, noise level, and experimental complexity, and atomic collisions have negligible influence on the optical coherences. Operation of the memory is demonstrated using attenuated laser pulses on the single photon level. For a 50 ns storage time, we measure ηe2 e 50 ns=3.4 (3 )% end-to-end efficiency of the fiber-coupled memory, with a total intrinsic efficiency ηint=17 (3 )%. Straightforward technological improvements can boost the end-to-end-efficiency to ηe 2 e≈35 %; beyond that, increasing the optical depth and exploiting the Zeeman substructure of the atoms will allow such a memory to approach near unity efficiency. In the present memory, the unconditional read-out noise level of 9 ×10-3 photons is dominated by atomic fluorescence, and for input pulses containing on average μ1=0.27 (4 ) photons, the signal to noise level would be unity.

Organic ferroelectric opto-electronic memories

NARCIS (Netherlands)

Asadi, K.; Li, M.; Blom, P.W.M.; Kemerink, M.; Leeuw, D.M. de

2011-01-01

Memory is a prerequisite for many electronic devices. Organic non-volatile memory devices based on ferroelectricity are a promising approach towards the development of a low-cost memory technology based on a simple cross-bar array. In this review article we discuss the latest developments in this

Development of novel nonvolatile memory devices using the colossal magnetoresistive oxide praseodymium-calcium-manganese trioxide

Science.gov (United States)

Papagianni, Christina

Pr0.7Ca0.3MnO3 (PCMO) manganese oxide belongs in the family of materials known as transition metal oxides. These compounds have received increased attention due to their perplexing properties such as Colossal Magnetoresistance effect, Charge-Ordered phase, existence of phase-separated states etc. In addition, it was recently discovered that short electrical pulses in amplitude and duration are sufficient to induce reversible and non-volatile resistance changes in manganese perovskite oxide thin films at room temperature, known as the EPIR effect. The existence of the EPIR effect in PCMO thin films at room temperature opens a viable way for the realization of fast, high-density, low power non-volatile memory devices in the near future. The purpose of this study is to investigate, optimize and understand the properties of Pr0.7Ca0.3MnO 3 (PCMO) thin film devices and to identify how these properties affect the EPIR effect. PCMO thin films were deposited on various substrates, such as metals, and conducting and insulating oxides, by pulsed laser and radio frequency sputtering methods. Our objective was to understand and compare the induced resistive states. We attempted to identify the induced resistance changes by considering two resistive models to be equivalent to our devices. Impedance spectroscopy was also utilized in a wide temperature range that was extended down to 70K. Fitted results of the temperature dependence of the resistance states were also included in this study. In the same temperature range, we probed the resistance changes in PCMO thin films and we examined whether the phase transitions affect the EPIR effect. In addition, we included a comparison of devices with electrodes consisting of different size and different materials. We demonstrated a direct relation between the EPIR effect and the phase diagram of bulk PCMO samples. A model that could account for the observed EPIR effect is presented.

Atomic crystals resistive switching memory

International Nuclear Information System (INIS)

Liu Chunsen; Zhang David Wei; Zhou Peng

2017-01-01

Facing the growing data storage and computing demands, a high accessing speed memory with low power and non-volatile character is urgently needed. Resistive access random memory with 4F 2 cell size, switching in sub-nanosecond, cycling endurances of over 10 12 cycles, and information retention exceeding 10 years, is considered as promising next-generation non-volatile memory. However, the energy per bit is still too high to compete against static random access memory and dynamic random access memory. The sneak leakage path and metal film sheet resistance issues hinder the further scaling down. The variation of resistance between different devices and even various cycles in the same device, hold resistive access random memory back from commercialization. The emerging of atomic crystals, possessing fine interface without dangling bonds in low dimension, can provide atomic level solutions for the obsessional issues. Moreover, the unique properties of atomic crystals also enable new type resistive switching memories, which provide a brand-new direction for the resistive access random memory. (topical reviews)

Surface directed phase separation of semiconductor ferroelectric polymer blends and their use in non-volatile memories

NARCIS (Netherlands)

Breemen, A.J.J.M. van; Zaba, T.; Khikhlovskyi, V.; Michels, J.; Janssen, R.; Kemerink, M.; Gelinck, G.

2015-01-01

The polymer phase separation of P(VDF-TrFE):F8BT blends is studied in detail. Its morphology is key to the operation and performance of memory diodes. In this study, it is demonstrated that it is possible to direct the semiconducting domains of a phase-separating mixture of P(VDF-TrFE) and F8BT in a

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

Science.gov (United States)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

Laser Nanosoldering of Golden and Magnetite Particles and its Possible Application in 3D Printing Devices and Four-Valued Non-Volatile Memories

Directory of Open Access Journals (Sweden)

Jaworski Jacek

2015-12-01

Full Text Available In recent years the 3D printing methods have been developing rapidly. This article presents researches about a new composite consisted of golden and magnetite nanoparticles which could be used for this technique. Preparation of golden nanoparticles by laser ablation and their soldering by laser green light irradiation proceeded in water environment. Magnetite was obtained on chemical way. During experiments it was tested a change of a size of nanoparticles during laser irradiation, surface plasmon resonance, zeta potential. The obtained golden - magnetite composite material was magnetic after laser irradiation. On the end there was considered the application it for 3D printing devices, water filters and four-valued non-volatile memories.

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Science.gov (United States)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2016-04-01

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

Science.gov (United States)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Tunable Injection Barrier in Organic Resistive Switches Based on Phase-Separated Ferroelectric-Semiconductor Blends

NARCIS (Netherlands)

Asadi, Kamal; de Boer, Tom G.; Blom, Paul W. M.; de Leeuw, Dago M.

2009-01-01

Organic non-volatile resistive bistable diodes based on phase-separated blends of ferroelectric and semiconducting polymers are fabricated. The polarization field of the ferroelectric modulates the injection barrier at the semiconductor-electrode contact and, hence, the resistance of the comprising

Tunable injection barrier in organic resistive switches based on phase-separated ferroelectric-semiconductor blends

NARCIS (Netherlands)

Asadi, K.; Boer, T.G. de; Blom, P.W.M.; Leeuw, D.M. de

2009-01-01

Organic non-volatile resistive bistable diodes based on phase-separated blends of ferroelectric and semiconducting polymers are fabricated. The polarization field of the ferroelectric modulates the injection barrier at the semiconductor-electrode contact and, hence, the resistance of the comprising

Transparent Oxide Semiconductors for Emerging Electronics

KAUST Repository

Caraveo-Frescas, Jesus Alfonso

2013-11-01

Transparent oxide electronics have emerged as promising materials to shape the future of electronics. While several n-type oxides have been already studied and demonstrated feasibility to be used as active materials in thin film transistors, high performance p-type oxides have remained elusive. This dissertation is devoted to the study of transparent p-type oxide semiconductor tin monoxide and its use in the fabrication of field effect devices. A complete study on the deposition of tin monoxide thin films by direct current reactive magnetron sputtering is performed. Carrier density, carrier mobility and conductivity are studied over a set of deposition conditions where p-type conduction is observed. Density functional theory simulations are performed in order to elucidate the effect of native defects on carrier mobility. The findings on the electrical properties of SnO thin films are then translated to the fabrication of thin films transistors. The low processing temperature of tin monoxide thin films below 200 oC is shown advantageous for the fabrication of fully transparent and flexible thin film transistors. After careful device engineering, including post deposition annealing temperature, gate dielectric material, semiconductor thickness and source and drain electrodes material, thin film transistors with record device performance are demonstrated, achieving a field effect mobility >6.7 cm2V-1s-1. Device performance is further improved to reach a field effect mobility of 10.8 cm2V-1s-1 in SnO nanowire field effect transistors fabricated from the sputtered SnO thin films and patterned by electron beam lithography. Downscaling device dimension to nano scale is shown beneficial for SnO field effect devices not only by achieving a higher hole mobility but enhancing the overall device performance including better threshold voltage, subthreshold swing and lower number of interfacial defects. Use of p-type semiconductors in nonvolatile memory applications is then

Intrinsic nanofilamentation in resistive switching

KAUST Repository

Wu, Xing; Cha, Dong Kyu; Bosman, Michel; Raghavan, Nagarajan; Migas, Dmitri B.; Borisenko, Victor E.; Zhang, Xixiang; Li, Kun; Pey, Kin-Leong

2013-01-01

-chip circuitry and non-volatile memory storage. Here, we provide insight into the mechanisms that govern highly reproducible controlled resistive switching via a nanofilament by using an asymmetric metal-insulator-semiconductor structure. In-situ transmission

A study on electromechanical carbon nanotube memory devices

International Nuclear Information System (INIS)

Kang, Jeong Won; Hwang, Ho Jung

2005-01-01

Electromechanical operations of carbon-nanotube (CNT) bridge memory device were investigated by using atomistic simulations based on empirical potentials. The nanotube-bridge memory device was operated by the electrostatic and the van der Waals forces acting on the nanotube-bridge. For the CNT bridge memory device, the van der Waals interactions between the CNT bridge and the oxide were very important. As the distance between the CNT bridge and the oxide decreased and the van der Waals interaction energy increased, the pull-in bias of the CNT-bridge decreased and the nonvolatility of the nanotube-bridge memory device increased, while the pull-out voltages increased. When the materials composed of the oxide film are different, since the van der Waals interactions must be also different, the oxide materials must be carefully selected for the CNT-bridge memory device to work as a nonvolatile memory.

Phase change memory

CERN Document Server

Qureshi, Moinuddin K

2011-01-01

As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions t

Emerging memories: resistive switching mechanisms and current status

International Nuclear Information System (INIS)

Jeong, Doo Seok; Thomas, Reji; Katiyar, R S; Scott, J F; Kohlstedt, H; Petraru, A; Hwang, Cheol Seong

2012-01-01

The resistance switching behaviour of several materials has recently attracted considerable attention for its application in non-volatile memory (NVM) devices, popularly described as resistive random access memories (RRAMs). RRAM is a type of NVM that uses a material(s) that changes the resistance when a voltage is applied. Resistive switching phenomena have been observed in many oxides: (i) binary transition metal oxides (TMOs), e.g. TiO 2 , Cr 2 O 3 , FeO x and NiO; (ii) perovskite-type complex TMOs that are variously functional, paraelectric, ferroelectric, multiferroic and magnetic, e.g. (Ba,Sr)TiO 3 , Pb(Zr x Ti 1−x )O 3 , BiFeO 3 and Pr x Ca 1−x MnO 3 ; (iii) large band gap high-k dielectrics, e.g. Al 2 O 3 and Gd 2 O 3 ; (iv) graphene oxides. In the non-oxide category, higher chalcogenides are front runners, e.g. In 2 Se 3 and In 2 Te 3 . Hence, the number of materials showing this technologically interesting behaviour for information storage is enormous. Resistive switching in these materials can form the basis for the next generation of NVM, i.e. RRAM, when current semiconductor memory technology reaches its limit in terms of density. RRAMs may be the high-density and low-cost NVMs of the future. A review on this topic is of importance to focus concentration on the most promising materials to accelerate application into the semiconductor industry. This review is a small effort to realize the ambitious goal of RRAMs. Its basic focus is on resistive switching in various materials with particular emphasis on binary TMOs. It also addresses the current understanding of resistive switching behaviour. Moreover, a brief comparison between RRAMs and memristors is included. The review ends with the current status of RRAMs in terms of stability, scalability and switching speed, which are three important aspects of integration onto semiconductors. (review article)

Emerging memories: resistive switching mechanisms and current status

Science.gov (United States)

Jeong, Doo Seok; Thomas, Reji; Katiyar, R. S.; Scott, J. F.; Kohlstedt, H.; Petraru, A.; Hwang, Cheol Seong

2012-07-01

The resistance switching behaviour of several materials has recently attracted considerable attention for its application in non-volatile memory (NVM) devices, popularly described as resistive random access memories (RRAMs). RRAM is a type of NVM that uses a material(s) that changes the resistance when a voltage is applied. Resistive switching phenomena have been observed in many oxides: (i) binary transition metal oxides (TMOs), e.g. TiO2, Cr2O3, FeOx and NiO; (ii) perovskite-type complex TMOs that are variously functional, paraelectric, ferroelectric, multiferroic and magnetic, e.g. (Ba,Sr)TiO3, Pb(Zrx Ti1-x)O3, BiFeO3 and PrxCa1-xMnO3 (iii) large band gap high-k dielectrics, e.g. Al2O3 and Gd2O3; (iv) graphene oxides. In the non-oxide category, higher chalcogenides are front runners, e.g. In2Se3 and In2Te3. Hence, the number of materials showing this technologically interesting behaviour for information storage is enormous. Resistive switching in these materials can form the basis for the next generation of NVM, i.e. RRAM, when current semiconductor memory technology reaches its limit in terms of density. RRAMs may be the high-density and low-cost NVMs of the future. A review on this topic is of importance to focus concentration on the most promising materials to accelerate application into the semiconductor industry. This review is a small effort to realize the ambitious goal of RRAMs. Its basic focus is on resistive switching in various materials with particular emphasis on binary TMOs. It also addresses the current understanding of resistive switching behaviour. Moreover, a brief comparison between RRAMs and memristors is included. The review ends with the current status of RRAMs in terms of stability, scalability and switching speed, which are three important aspects of integration onto semiconductors.

1 Gb Radiation Hardened Nonvolatile Memory Development, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The objective of this effort is to identify, characterize and develop advanced semiconductor materials and fabrication process techniques, and design and produce a...

CCST [Center for Compound Semiconductor Technology] research briefs

International Nuclear Information System (INIS)

Zipperian, T.E.; Voelker, E.R.

1989-12-01

This paper discusses the following topics: theoretical predictions of valence and conduction band offsets in III-V semiconductors; reflectance modulation of a semiconductor superlattice optical mirror; magnetoquantum oscillations of the phonon-drag thermoelectric power in quantum wells; correlation between photoluminescence line shape and device performance of p-channel strained-layer materials; control of threading dislocations in heteroepitaxial structures; improved growth of CdTe on GaAs by patterning; role of structure threading dislocations in relaxation of highly strained single-quantum-well structures; InAlAs growth optimization using reflection mass spectrometry; nonvolatile charge storage in III-V heterostructures; optically triggered thyristor switches; InAsSb strained-layer superlattice infrared detectors with high detectivities; resonant periodic gain surface-emitting semiconductor lasers; performance advantages of strained-quantum-well lasers in AlGaAs/InGaAs; optical integrated circuit for phased-array radar antenna control; and deposition and novel device fabrication from Tl 2 Ca 2 Ba 2 Cu 3 O y thin films

Novel ferroelectric capacitor for non-volatile memory storage and biomedical tactile sensor applications

International Nuclear Information System (INIS)

Liu, Shi Yang; Chua, Lynn; Tan, Kian Chuan; Valavan, S.E.

2010-01-01

We report on novel ferroelectric thin film compositions for use in non-volatile memory storage and biomedical tactile sensor applications. The lead zirconate titanate (PZT) composition was modified by lanthanum (La 3+ ) (PLZT) and vanadium (V 5+ ) (PZTV, PLZTV) doping. Hybrid films with PZTV and PLZTV as top layers are also made using seed layers of differing compositions using sol-gel and spin coating methods. La 3+ doping decreased the coercive field, polarization and leakage current, while increasing the relative permittivity. V 5+ doping, while having similar effects, results in an enhanced polarization, with comparable dielectric loss characteristics. Complex doping of both La 3+ and V 5+ in PLZTV, while reducing the polarization relative to PZTV, significantly decreases the coercive field. Hybrid films have a greater uniformity of grain formation than non-hybrid films, thus decreasing the coercive field, leakage current and polarization fatigue while increasing the relative permittivity. Analysis using X-ray diffraction (XRD) verified the retention of the PZT perovskite structure in the novel films. PLZT/PZTV has been identified as an optimal ferroelectric film composition due to its desirable ferroelectric, fatigue and dielectric properties, including the highest observed remnant polarization (P r ) of ∼ 25 μC/cm 2 , saturation polarization (P sat ) of ∼ 58 μC/cm 2 and low coercive field (E c ) of ∼ 60 kV/cm at an applied field of ∼ 1000 kV/cm, as well as a low leakage current density of ∼ 10 -5 A/cm 2 at 500 kV/cm and fatigue resistance of up to ∼ 10 10 switching cycles.

Novel applications of non-volatile memories

Energy Technology Data Exchange (ETDEWEB)

Duthie, I

1982-01-01

The author reviews briefly the evolution of the programmable memory and the alternative technologies, before discussing the operation of a small EEPROM when used in conjunction with a microprocessor for typical applications. Some applications are reviewed and the opportunities which eeproms can offer for new applications are presented, together with the requirements for artificial intelligence to become a reality.

Transport and Fatigue Properties of Ferroelectric Polymer P(VDF-TrFE) For Nonvolatile Memory Applications

KAUST Repository

Hanna, Amir

2012-06-01

Organic ferroelectrics polymers have recently received much interest for use in nonvolatile memory devices. The ferroelectric copolymer poly(vinylidene fluoride- trifluoroethylene) , P(VDF-TrFE), is a promising candidate due to its relatively high remnant polarization, low coercive field, fast switching times, easy processability, and low Curie transition. However, no detailed study of charge injection and current transport properties in P(VDF-TrFE) have been reported in the literature yet. Charge injection and transport are believed to affect various properties of ferroelectric films such as remnant polarization values and polarization fatigue behavior.. Thus, this thesis aims to study charge injection in P(VDF-TrFE) and its transport properties as a function of electrode material. Injection was studied for Al, Ag, Au and Pt electrodes. Higher work function metals such as Pt have shown less leakage current compared to lower work function metals such as Al for more than an order of magnitude. That implied n-type conduction behavior for P(VDF-TrFE), as well as electrons being the dominant injected carrier type. Charge transport was also studied as a function of temperature, and two major transport regimes were identified: 1) Thermionic emission over a Schottky barrier for low fields (E < 25 MV/m). 2) Space-Charge-Limited regime at higher fields (25 < E <120 MV/m). We have also studied the optical imprint phenomenon, the polarization fatigue resulting from a combination of broad band optical illumination and DC bias near the switching field. A setup was designed for the experiment, and validated by reproducing the reported effect in polycrystalline Pb(Zr,Ti)O3 , PZT, film. On the other hand, P(VDF-TrFE) film showed no polarization fatigue as a result of optical imprint test, which could be attributed to the large band gap of the material, and the low intensity of the UV portion of the arc lamp white light used for the experiment. Results suggest using high work

Observing the amorphous-to-crystalline phase transition in Ge{sub 2}Sb{sub 2}Te{sub 5} non-volatile memory materials from ab initio molecular-dynamics simulations

Energy Technology Data Exchange (ETDEWEB)

Lee, T.H.; Elliott, S.R. [Department of Chemistry, University of Cambridge, Lensfield Road, CB2 1EW Cambridge (United Kingdom)

2012-10-15

Phase-change memory is a promising candidate for the next generation of non-volatile memory devices. This technology utilizes reversible phase transitions between amorphous and crystalline phases of a recording material, and has been successfully used in rewritable optical data storage, revealing its feasibility. In spite of the importance of understanding the nucleation and growth processes that play a critical role in the phase transition, this understanding is still incomplete. Here, we present observations of the early stages of crystallization in Ge{sub 2}Sb{sub 2}Te{sub 5} materials through ab initio molecular-dynamics simulations. Planar structures, including fourfold rings and planes, play an important role in the formation and growth of crystalline clusters in the amorphous matrix. At the same time, vacancies facilitate crystallization by providing space at the glass-crystalline interface for atomic diffusion, which results in fast crystal growth, as observed in simulations and experiments. The microscopic mechanism of crystallization presented here may deepen our understanding of the phase transition occurring in real devices, providing an opportunity to optimize the memory performance of phase-change materials. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture

OpenAIRE

senni , sophiane; Torres , Lionel; Sassatelli , Gilles; Gamatié , Abdoulaye; Mussard , Bruno

2015-01-01

International audience; Most die area of today's systems-on-chips is occupied by memories. Hence, a significant proportion of total power is spent on memory systems. Moreover, since processing elements have to be fed with instructions and data from memories, memory plays a key role for system's performance. As a result, memories are a critical part of future embedded systems. Continuing CMOS scaling leads to manufacturing constraints and power consumption issues for the current three main mem...

Tuning the resistive switching memory in a metal–ferroelectric–semiconductor capacitor by field effect structure

Energy Technology Data Exchange (ETDEWEB)

Wang, S.Y., E-mail: shouyu.wang@yahoo.com [College of Physics and Electronic Information Science, Tianjin Normal University, Tianjin 300074 (China); Guo, F.; Wang, X. [College of Physics and Electronic Information Science, Tianjin Normal University, Tianjin 300074 (China); Liu, W.F., E-mail: wfliu@tju.edu.cn [Department of Applied Physics, Faculty of Science, Tianjin University, Weijin Road, Nankai District, Tianjin 300072 (China); Gao, J., E-mail: jugao@hku.hk [Department of Physics, the University of Hong Kong, Pokfulam Road (Hong Kong)

2015-11-30

Highlights: • Bistable or tristable electrically conducting state is observed. • Coefficient can be tuned in situ by modulating carrier's density. • The RS effects may be of significance for multi-source controlled memory devices. - Abstract: Resistive switching (RS) effects based on a correlation between ferroelectric polarization and conductivity might become of particular interest for nonvolatile memory applications, because they are not subjected to the scaling restrictions. Here we report on RS behaviors modulated by a reversal of ferroelectric polarization in heterostructures comprising of a ferroelectric layer and a semiconducting manganite film. It is found that electrically conducting state is bistable or even tristable; and via the polarization flipping, a maximum resistive switching coefficient (R{sub max}/R{sub min}) is found to be larger than 3000 with bias of 6 V in Ag/BaTiO{sub 3}/La{sub 0.8}Ca{sub 0.2}MnO{sub 3} at room temperature. More importantly, employing field-effect structure with ferroelectric PMN-PT as substrate, we found that the resistive switching behaviors can be tuned in situ by modulating the concentration of carriers in the semiconducting manganite layer. Possible mechanisms are discussed on the basis of the interplay of bound ferroelectric charges, charged defects in ferroelectric layer and mobile carriers in manganite thin films. The giant RS effects observed here may be of significance for memory devices by combing electronic conduction with magnetic, spintronic, and optical functionalities.

Radiation Damage in Electronic Memory Devices

OpenAIRE

Fetahović, Irfan; Pejović, Milić; Vujisić, Miloš

2013-01-01

This paper investigates the behavior of semiconductor memories exposed to radiation in order to establish their applicability in a radiation environment. The experimental procedure has been used to test radiation hardness of commercial semiconductor memories. Different types of memory chips have been exposed to indirect ionizing radiation by changing radiation dose intensity. The effect of direct ionizing radiation on semiconductor memory behavior has been analyzed by using Monte Carlo simula...

High frequency electromechanical memory cells based on telescoping carbon nanotubes.

Science.gov (United States)

Popov, A M; Lozovik, Y E; Kulish, A S; Bichoutskaia, E

2010-07-01

A new method to increase the operational frequency of electromechanical memory cells based on the telescoping motion of multi-walled carbon nanotubes through the selection of the form of the switching voltage pulse is proposed. The relative motion of the walls of carbon nanotubes can be controlled through the shape of the interwall interaction energy surface. This allows the use of the memory cells in nonvolatile or volatile regime, depending on the structure of carbon nanotube. Simulations based on ab initio and semi-empirical calculations of the interwall interaction energies are used to estimate the switching voltage and the operational frequency of volatile cells with the electrodes made of carbon nanotubes. The lifetime of nonvolatile memory cells is also predicted.

Efficient Management for Hybrid Memory in Managed Language Runtime

OpenAIRE

Wang , Chenxi; Cao , Ting; Zigman , John; Lv , Fang; Zhang , Yunquan; Feng , Xiaobing

2016-01-01

Part 1: Memory: Non-Volatile, Solid State Drives, Hybrid Systems; International audience; Hybrid memory, which leverages the benefits of traditional DRAM and emerging memory technologies, is a promising alternative for future main memory design. However popular management policies through memory-access recording and page migration may invoke non-trivial overhead in execution time and hardware space. Nowadays, managed language applications are increasingly dominant in every kind of platform. M...

Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

Science.gov (United States)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

Status and Prospects of ZnO-Based Resistive Switching Memory Devices

Science.gov (United States)

Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

2016-08-01

In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

Field-effect transistor memories based on ferroelectric polymers

Science.gov (United States)

Zhang, Yujia; Wang, Haiyang; Zhang, Lei; Chen, Xiaomeng; Guo, Yu; Sun, Huabin; Li, Yun

2017-11-01

Field-effect transistors based on ferroelectrics have attracted intensive interests, because of their non-volatile data retention, rewritability, and non-destructive read-out. In particular, polymeric materials that possess ferroelectric properties are promising for the fabrications of memory devices with high performance, low cost, and large-area manufacturing, by virtue of their good solubility, low-temperature processability, and good chemical stability. In this review, we discuss the material characteristics of ferroelectric polymers, providing an update on the current development of ferroelectric field-effect transistors (Fe-FETs) in non-volatile memory applications. Program supported partially by the NSFC (Nos. 61574074, 61774080), NSFJS (No. BK20170075), and the Open Partnership Joint Projects of NSFC-JSPS Bilateral Joint Research Projects (No. 61511140098).

State of the art in semiconductor detectors

International Nuclear Information System (INIS)

Rehak, P.; Gatti, E.

1990-01-01

The state of the art in semiconductor detectors for elementary particle physics and X-ray astronomy is briefly reviewed. Semiconductor detectors are divided into two groups; i) classical semiconductor diode detectors and ii) semiconductor memory detectors. Principles of signal formation for both groups of detectors are described and their performance is compared. New developments of silicon detectors are reported here. (orig.)

State of the art in semiconductor detectors

International Nuclear Information System (INIS)

Rehak, P.; Gatti, E.

1989-01-01

The state of the art in semiconductor detectors for elementary particle physics and x-ray astronomy is briefly reviewed. Semiconductor detectors are divided into two groups; classical semiconductor diode detectors; and semiconductor memory detectors. Principles of signal formation for both groups of detectors are described and their performance is compared. New developments of silicon detectors are reported here. 13 refs., 8 figs

Calculation of neutron-induced single-event upset cross sections for semiconductor memory devices

International Nuclear Information System (INIS)

Ikeuchi, Taketo; Watanabe, Yukinobu; Nakashima, Hideki; Sun, Weili

2001-01-01

Neutron-induced single-event upset (SEU) cross sections for semiconductor memory devices are calculated by the Burst Generation Rate (BGR) method using LA150 data and QMD calculation in the neutron energy range between 20 MeV and 10 GeV. The calculated results are compared with the measured SEU cross sections for energies up to 160 MeV, and the validity of the calculation method and the nuclear data used is verified. The kind of reaction products and the neutron energy range that have the most effect on SEU are discussed. (author)

Radiation Damage in Electronic Memory Devices

Directory of Open Access Journals (Sweden)

Irfan Fetahović

2013-01-01

Full Text Available This paper investigates the behavior of semiconductor memories exposed to radiation in order to establish their applicability in a radiation environment. The experimental procedure has been used to test radiation hardness of commercial semiconductor memories. Different types of memory chips have been exposed to indirect ionizing radiation by changing radiation dose intensity. The effect of direct ionizing radiation on semiconductor memory behavior has been analyzed by using Monte Carlo simulation method. Obtained results show that gamma radiation causes decrease in threshold voltage, being proportional to the absorbed dose of radiation. Monte Carlo simulations of radiation interaction with material proved to be significant and can be a good estimation tool in probing semiconductor memory behavior in radiation environment.

Models for Total-Dose Radiation Effects in Non-Volatile Memory

Energy Technology Data Exchange (ETDEWEB)

Campbell, Philip Montgomery; Wix, Steven D.

2017-04-01

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models and compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.

Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

Science.gov (United States)

Xu, Meili; Xiang, Lanyi; Xu, Ting; Wang, Wei; Xie, Wenfa; Zhou, Dayu

2017-10-01

Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V-1 s-1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

Scaling Techniques for Massive Scale-Free Graphs in Distributed (External) Memory

KAUST Repository

Pearce, Roger; Gokhale, Maya; Amato, Nancy M.

2013-01-01

We present techniques to process large scale-free graphs in distributed memory. Our aim is to scale to trillions of edges, and our research is targeted at leadership class supercomputers and clusters with local non-volatile memory, e.g., NAND Flash

Fast Magnetoresistive Random-Access Memory

Science.gov (United States)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1991-01-01

Magnetoresistive binary digital memories of proposed new type expected to feature high speed, nonvolatility, ability to withstand ionizing radiation, high density, and low power. In memory cell, magnetoresistive effect exploited more efficiently by use of ferromagnetic material to store datum and adjacent magnetoresistive material to sense datum for readout. Because relative change in sensed resistance between "zero" and "one" states greater, shorter sampling and readout access times achievable.

Feasibility and limitations of anti-fuses based on bistable non-volatile switches for power electronic applications

Science.gov (United States)

Erlbacher, T.; Huerner, A.; Bauer, A. J.; Frey, L.

2012-09-01

Anti-fuse devices based on non-volatile memory cells and suitable for power electronic applications are demonstrated for the first time using silicon technology. These devices may be applied as stand alone devices or integrated using standard junction-isolation into application-specific and smart-power integrated circuits. The on-resistance of such devices can be permanently switched by nine orders of magnitude by triggering the anti-fuse with a positive voltage pulse. Extrapolation of measurement data and 2D TCAD process and device simulations indicate that 20 A anti-fuses with 10 mΩ can be reliably fabricated in 0.35 μm technology with a footprint of 2.5 mm2. Moreover, this concept offers distinguished added-values compared to existing mechanical relays, e.g. pre-test, temporary and permanent reset functions, gradual turn-on mode, non-volatility, and extendibility to high voltage capability.

Effect of CuPc layer insertion on the memory performance of CdS nanocomposite diodes

Energy Technology Data Exchange (ETDEWEB)

Tripathi, S.K., E-mail: surya@pu.ac.in; Kaur, Ramneek; Jyoti

2016-09-15

Highlights: • CdS nanocomposite as an active layer investigated for memory device application. • Effect of copper phthalocyanine layer insertion on the memory performance studied. • Bipolar switching behaviour with high ON/OFF ratio ∼1.4 × 10{sup 4}. • Series resistance and interface states dominate the electrical properties of the device. - Abstract: In the present work, semiconductor diodes with CdS nanocomposite as an active layer have been fabricated and investigated for memory device applications. The effect of copper phthalocyanine (CuPc) layer insertion between the bottom electrode and CdS nanocomposite has been studied. I–V characteristics show electrical hysteresis behaviour vital for memory storage application. The as-fabricated devices exhibit bipolar switching behaviour with OFF to ON state transition at positive bias and vice versa. Device with CuPc layer exhibits I{sub ON}/I{sub OFF} ratio ∼ 1.4 × 10{sup 4}. Possible conduction mechanism has been described on the basis of theoretical current conduction models. The frequency dispersion capacitance, series resistance and conductance of the devices have been studied and discussed. At low frequency, the series resistance and the interface states dominate the electrical properties of the device. The results indicate that the multilayered devices open up the possibility of new generation non-volatile memory devices with low cost, high density and stability.

Non Volatile Flash Memory Radiation Tests

Science.gov (United States)

Irom, Farokh; Nguyen, Duc N.; Allen, Greg

2012-01-01

Commercial flash memory industry has experienced a fast growth in the recent years, because of their wide spread usage in cell phones, mp3 players and digital cameras. On the other hand, there has been increased interest in the use of high density commercial nonvolatile flash memories in space because of ever increasing data requirements and strict power requirements. Because of flash memories complex structure; they cannot be treated as just simple memories in regards to testing and analysis. It becomes quite challenging to determine how they will respond in radiation environments.

Dual-functional Memory and Threshold Resistive Switching Based on the Push-Pull Mechanism of Oxygen Ions

KAUST Repository

Huang, Yi-Jen; Chao, Shih-Chun; Lien, Der-Hsien; Wen, Cheng-Yen; He, Jr-Hau; Lee, Si-Chen

2016-01-01

The combination of nonvolatile memory switching and volatile threshold switching functions of transition metal oxides in crossbar memory arrays is of great potential for replacing charge-based flash memory in very-large-scale integration. Here, we

Quest for high-Curie temperature MnxGe1-x diluted magnetic semiconductors for room-temperature spintronics applications

Science.gov (United States)

Nie, Tianxiao; Tang, Jianshi; Wang, Kang L.

2015-09-01

In this paper, we report the non-equilibrium growth of various Mn-doped Ge dilute magnetic semiconductor nanostructures using molecular-beam epitaxy, including quantum dots, nanodisks and nanowires. Their detailed structural and magnetic properties are characterized. By comparing the results with those in MnxGe1-x thin films, it is affirmed that the use of nanostructures helps eliminate crystalline defects and meanwhile enhance the carrier-mediate ferromagnetism from substantial quantum confinements. Our systematic studies provide a promising platform to build nonvolatile spinFET and other novel spintronic devices based upon dilute magnetic semiconductor nanostructures.

Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture.

Science.gov (United States)

Zhu, Bowen; Wang, Hong; Liu, Yaqing; Qi, Dianpeng; Liu, Zhiyuan; Wang, Hua; Yu, Jiancan; Sherburne, Matthew; Wang, Zhaohui; Chen, Xiaodong

2016-02-24

Skin-inspired haptic-memory devices, which can retain pressure information after the removel of external pressure by virtue of the nonvolatile nature of the memory devices, are achieved. The rise of haptic-memory devices will allow for mimicry of human sensory memory, opening new avenues for the design of next-generation high-performance sensing devices and systems. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Memory and pressure studies in NaxCoO2 cobaltites

International Nuclear Information System (INIS)

Garbarino, G; Bouvier, P; Crichton, W A; Mezouar, M; Regueiro, M Nunez; Lejay, P; Armand, M; Foo, M L; Cava, R J

2009-01-01

We present a detailed study on the memory effect results in Na 0.5 paragraph 5CoO 2 single crystals. We analyze the temperature dependence of the nonvolatile current-pulse-induced resistance memory state. These results allow us to have more insight in the mobility of Na + ions induced by current and their effect on the memory effect. We also developed X-ray diffraction studies under pressure at ambient temperature in the N a0.5 CoO 2 powder compound. An orthorhombic to hexagonal phase transition was observed at 9GPa. This transition can be explained taking into account the Na ions displacement between two allowed positions. These structural results allow us to confirm that the non-volatile resistive commutation can be interpreted by the displacement of the Na ions induced by the current pulses.

Identification of nonvolatile compounds in clove (Syzygium aromaticum) from Manado

Science.gov (United States)

Fathoni, A.; Saepudin, E.; Cahyana, A. H.; Rahayu, D. U. C.; Haib, J.

2017-07-01

Syzygium aromaticum (clove) are native to Indonesia and have been widely used in food industry due to their flavor. Nonvolatile compounds contribute to flavor, mainly in their taste. Currently, there is very little information available about nonvolatile compounds in clove. Identification of nonvolatile compounds is important to improve clove's value. Compound extraction was conducted by maceration in ethanol. Fractionations of the extract were performed by using gravity column chromatography on silica gel and Sephadex LH-20 as stationary phase. Nonvolatile compounds were identified by Liquid Chromatography-Tandem Mass Spectrometry (LC-MS/MS). LC-MS/MS was operated in negative mode with 0.1 % formic acid in water and acetonitrile as mobile phase. Nonvolatile compounds were identified by fragment analysis and compared to references. Several compounds had been identified and characterized asquinic acid, monogalloylglucose, gallic acid, digalloylglucose, isobiflorin, biflorin, ellagic acid, hydroxygallic acid, luteolin, quercetin, naringenin, kaempferol, isorhamnetin, dimethoxyluteolin, and rhamnetin. These compounds had two main flavor perceptions, i.e. astringent, and bitter.

Pulse number control of electrical resistance for multi-level storage based on phase change

International Nuclear Information System (INIS)

Nakayama, K; Takata, M; Kasai, T; Kitagawa, A; Akita, J

2007-01-01

Phase change nonvolatile memory devices composed of SeSbTe chalcogenide semiconductor thin film were fabricated. The resistivity of the SeSbTe system was investigated to apply to multi-level data storage. The chalcogenide semiconductor acts as a programmable resistor that has a large dynamic range. The resistance of the chalcogenide semiconductor can be set to intermediate resistances between the amorphous and crystalline states using electric pulses of a specified power, and it can be controlled by repetition of the electric pulses. The size of the memory cell used in this work is 200 nm thick with a contact area of 1 μm diameter. The resistance of the chalcogenide semiconductor gradually varies from 41 kΩ to 840 Ω within octal steps. The resistance of the chalcogenide semiconductor decreases with increasing number of applied pulses. The step-down characteristic of the resistance can be explained as the crystalline region of the active phase change region increases with increasing number of applied pulses. The extent of crystallization was also estimated by the overall resistivity of the active region of the memory cell

Low Cost Writeable RFID Tag With MRAM Memory

National Research Council Canada - National Science Library

Beech, Russell

1998-01-01

This program's goal was to develop a writeable RFID tag using an integrated, permeable core coil as the inductor/antenna for communication and power transfer and MRAM as the low write energy, nonvolatile memory...

Next generation spin torque memories

CERN Document Server

Kaushik, Brajesh Kumar; Kulkarni, Anant Aravind; Prajapati, Sanjay

2017-01-01

This book offers detailed insights into spin transfer torque (STT) based devices, circuits and memories. Starting with the basic concepts and device physics, it then addresses advanced STT applications and discusses the outlook for this cutting-edge technology. It also describes the architectures, performance parameters, fabrication, and the prospects of STT based devices. Further, moving from the device to the system perspective it presents a non-volatile computing architecture composed of STT based magneto-resistive and all-spin logic devices and demonstrates that efficient STT based magneto-resistive and all-spin logic devices can turn the dream of instant on/off non-volatile computing into reality.

Magnetic vortex racetrack memory

Science.gov (United States)

Geng, Liwei D.; Jin, Yongmei M.

2017-02-01

We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications.

Low-resistivity C54-TiSi2 as a sidewall-confinement nanoscale electrode for three-dimensional vertical resistive memory

KAUST Repository

Duran Retamal, Jose Ramon; Kang, Chen-Fang; Yang, Po-Kang; Lee, Chuan-Pei; Lien, Der-Hsien; Ho, Chih-Hsiang; He, Jr-Hau

2014-01-01

A three-dimensional (3D) double-layer HfO2-based vertical-resistive random access memory (VRRAM) with low-resistivity C54-TiSi2 as horizontal electrodes is demonstrated using complementary metal-oxide semiconductor processing. The electrical measurements show bipolar resistive switching by using C54-TiSi2 as electrodes for resistive switching (RS) applications. The statistical analysis exhibits cycle-to-cycle and cell-to-cell stable non-volatile properties with robust endurance (100 cycles) and long term data retention (104s), suggesting that the ultrathin sidewall of C54-TiSi2 nanoscale electrodes serve to confine and stabilize the random nature of the conducting nanofilaments. The superior RS characteristics demonstrated here highlight the applicability of C54-TiSi2 sidewall-confinement nanoscale electrodes to VRRAM.

Low-resistivity C54-TiSi2 as a sidewall-confinement nanoscale electrode for three-dimensional vertical resistive memory

KAUST Repository

Duran Retamal, Jose Ramon

2014-11-03

A three-dimensional (3D) double-layer HfO2-based vertical-resistive random access memory (VRRAM) with low-resistivity C54-TiSi2 as horizontal electrodes is demonstrated using complementary metal-oxide semiconductor processing. The electrical measurements show bipolar resistive switching by using C54-TiSi2 as electrodes for resistive switching (RS) applications. The statistical analysis exhibits cycle-to-cycle and cell-to-cell stable non-volatile properties with robust endurance (100 cycles) and long term data retention (104s), suggesting that the ultrathin sidewall of C54-TiSi2 nanoscale electrodes serve to confine and stabilize the random nature of the conducting nanofilaments. The superior RS characteristics demonstrated here highlight the applicability of C54-TiSi2 sidewall-confinement nanoscale electrodes to VRRAM.

Nonvolatile Resistive Switching Memory Utilizing Cobalt Embedded in Gelatin

Directory of Open Access Journals (Sweden)

Cheng-Jung Lee

2017-12-01

Full Text Available This study investigates the preparation and electrical properties of Al/cobalt-embedded gelatin (CoG/ indium tin oxide (ITO resistive switching memories. Co. elements can be uniformly distributed in gelatin without a conventional dispersion procedure, as confirmed through energy dispersive X-ray analyzer and X-ray photoelectron spectroscopy observations. With an appropriate Co. concentration, Co. ions can assist the formation of an interfacial AlOx layer and improve the memory properties. High ON/OFF ratio, good retention capability, and good endurance switching cycles are demonstrated with 1 M Co. concentration, in contrast to 0.5 M and 2 M memory devices. This result can be attributed to the suitable thickness of the interfacial AlOx layer, which acts as an oxygen reservoir and stores and releases oxygen during switching. The Co. element in a solution-processed gelatin matrix has high potential for bio-electronic applications.

GMAG Dissertation Award Talk: Zero-moment Half-Metallic Ferrimagnetic Semiconductors

Science.gov (United States)

Jamer, Michelle E.

2015-03-01

Low- and zero-moment half-metallic ferrimagnetic semiconductors have been proposed for advanced applications, such as nonvolatile RAM memory and quantum computing. These inverse-Heusler materials could be used to generate spin-polarized electron or hole currents without the associated harmful fringing magnetic fields. Such materials are expected to exhibit low to zero magnetic moment at room temperature, which makes them well-positioned for future spin-based devices. However, these compounds have been shown to suffer from disorder. This work focuses on the synthesis of these compounds and the investigation of their structural, magnetic, and transport properties. Cr2CoGa and Mn3Al thin films were synthesized by molecular beam epitaxy, and V3Al and Cr2CoAl were synthesized via arc-melting. Rietveld analysis was used to determine the degree of ordering in the sublattices as a function of annealing. The atomic moments were measured by X-ray magnetic circular and linear dichroism confirmed antiferromagnetic alignment of sublattices and the desired near-zero moment in several compounds. In collaboration with George E. Sterbinsky, Photon Sciences Directorate, Brookhaven National Laboratory; Dario Arena Photon Sciences Directorate, Brookhaven National Laboratory; Laura H. Lewis, Chemical Engineering, Northeastern University; and Don Heiman, Physics, Northeastern University. NSF-ECCS-1402738, NSF-DMR-0907007.

Space Qualified, Radiation Hardened, Dense Monolithic Flash Memory, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Radiation hardened nonvolatile memories for space is still primarily confined to EEPROM. There is high density effective or cost effective NVM solution available to...

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

Science.gov (United States)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

Semiconductor detectors in nuclear and particle physics

International Nuclear Information System (INIS)

Rehak, P.; Gatti, E.

1992-01-01

Semiconductor detectors for elementary particle physics and nuclear physics in the energy range above 1 GeV are briefly reviewed. In these two fields semiconductor detectors are used mainly for the precise position sensing. In a typical experiment, the position of a fast charged particle crossing a relatively thin semiconductor detector is measured. The position resolution achievable by semiconductor detectors is compared with the resolution achievable by gas filled position sensing detectors. Semiconductor detectors are divided into two groups: Classical semiconductor diode detectors and semiconductor memory detectors. Principles of the signal formation and the signal read-out for both groups of detectors are described. New developments of silicon detectors of both groups are reported

Electrical memory features of ferromagnetic CoFeAlSi nano-particles embedded in metal-oxide-semiconductor matrix

International Nuclear Information System (INIS)

Lee, Ja Bin; Kim, Ki Woong; Lee, Jun Seok; An, Gwang Guk; Hong, Jin Pyo

2011-01-01

Half-metallic Heusler material Co 2 FeAl 0.5 Si 0.5 (CFAS) nano-particles (NPs) embedded in metal-oxide-semiconductor (MOS) structures with thin HfO 2 tunneling and MgO control oxides were investigated. The CFAS NPs were prepared by rapid thermal annealing. The formation of well-controlled CFAS NPs on thin HfO 2 tunneling oxide was confirmed by atomic force microscopy (AFM). Memory characteristics of CFAS NPs in MOS devices exhibited a large memory window of 4.65 V, as well as good retention and endurance times of 10 5 cycles and 10 9 s, respectively, demonstrating the potential of CFAS NPs as promising candidates for use in charge storage.

Searching Room Temperature Ferromagnetism in Wide Gap Semiconductors Fe-doped Strontium Titanate and Zinc Oxide

CERN Document Server

Pereira, LMC; Wahl, U

Scientific findings in the very beginning of the millennium are taking us a step further in the new paradigm of technology: spintronics. Upgrading charge-based electronics with the additional degree of freedom of the carriers spin-state, spintronics opens a path to the birth of a new generation of devices with the potential advantages of non-volatility and higher processing speed, integration densities and power efficiency. A decisive step towards this new age lies on the attribution of magnetic properties to semiconductors, the building block of today's electronics, that is, the realization of ferromagnetic semiconductors (FS) with critical temperatures above room temperature. Unfruitful search for intrinsic RT FS lead to the concept of Dilute(d) Magnetic Semiconductors (DMS): ordinary semiconductor materials where 3 d transition metals randomly substitute a few percent of the matrix cations and, by some long-range mechanism, order ferromagnetically. The times are of intense research activity and the last fe...

Large non-volatile tuning of magnetism mediated by electric field in Fe–Al/Pb(Mg1/3Nb2/3)O3–PbTiO3 heterostructure

International Nuclear Information System (INIS)

Chen, Zhendong; Gao, Cunxu; Wei, Yanping; Zhang, Peng; Wang, Yutian; Zhang, Chao; Ma, Zhikun

2017-01-01

Electric-field control of magnetism is now an attractive trend to approach a new kind of fast, low-power-cost memory device. In this work, we report a strong non-volatile electric control of magnetism in an Fe–Al/Pb(Mg 1/3 Nb 2/3 )O 3 –PbTiO 3 heterostructure. In this system, a 90° rotation of the in-plane uniaxial magnetic anisotropy is exhibited during the increase of the external electric field, which means the easy axis turns into a hard axis and the hard axis turns into an easy one. Additionally, a non-volatile switch of the remanence is observed after a sweeping of the electric field from 0 kV cm −1 to  ±  10 kV cm −1 , then back to 0 kV cm −1 . More interestingly, a 20% non-volatile magnetic state tuning driven by individual pulse electric fields is shown in contrast to large tuning up to 120% caused by pulse electric fields with small assistant pulse magnetic fields, which means a 180° reverse of the magnetization. These remarkable behaviors demonstrated in this heterostructure reveal a promising potential application in magnetic memory devices mediated by electric fields. (paper)

Strain-controlled nonvolatile magnetization switching

Science.gov (United States)

Geprägs, S.; Brandlmaier, A.; Brandt, M. S.; Gross, R.; Goennenwein, S. T. B.

2014-11-01

We investigate different approaches towards a nonvolatile switching of the remanent magnetization in single-crystalline ferromagnets at room temperature via elastic strain using ferromagnetic thin film/piezoelectric actuator hybrids. The piezoelectric actuator induces a voltage-controllable strain along different crystalline directions of the ferromagnetic thin film, resulting in modifications of its magnetization by converse magnetoelastic effects. We quantify the magnetization changes in the hybrids via ferromagnetic resonance spectroscopy and superconducting quantum interference device magnetometry. These measurements demonstrate a significant strain-induced change of the magnetization, limited by an inefficient strain transfer and domain formation in the particular system studied. To overcome these obstacles, we address practicable engineering concepts and use a model to demonstrate that a strain-controlled, nonvolatile magnetization switching should be possible in appropriately engineered ferromagnetic/piezoelectric actuator hybrids.

Electric Field Tuning Non-volatile Magnetism in Half-Metallic Alloys Co2FeAl/Pb(Mg1/3Nb2/3)O3-PbTiO3 Heterostructure

Science.gov (United States)

Dunzhu, Gesang; Wang, Fenglong; Zhou, Cai; Jiang, Changjun

2018-03-01

We reported the non-volatile electric field-mediated magnetic properties in the half-metallic Heusler alloy Co2FeAl/Pb(Mg1/3Nb2/3)O3-PbTiO3 heterostructure at room temperature. The remanent magnetization with different applied electric field along [100] and [01-1] directions was achieved, which showed the non-volatile remanent magnetization driven by an electric field. The two giant reversible and stable remanent magnetization states were obtained by applying pulsed electric field. This can be attributed to the piezostrain effect originating from the piezoelectric substrate, which can be used for magnetoelectric-based memory devices.

Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling

Science.gov (United States)

Heidecker, Jason

2010-01-01

This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.

Organic Ferroelectric-Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half-Selection Problem.

Science.gov (United States)

Zhao, Qiang; Wang, Hanlin; Ni, Zhenjie; Liu, Jie; Zhen, Yonggang; Zhang, Xiaotao; Jiang, Lang; Li, Rongjin; Dong, Huanli; Hu, Wenping

2017-09-01

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF-TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low-cost and easy-fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half-selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm 2 V -1 s -1 (average) for 2,6-diphenylanthracene (DPA) and electron mobility of 0.124 cm 2 V -1 s -1 (average) for N,N'-1H,1H-perfluorobutyl dicyanoperylenecarboxydiimide (PDI-FCN 2 ) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric-based pixelated memory module fabrication. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Applications of nuclear microprobes in the semiconductor industry

International Nuclear Information System (INIS)

Takai, M.

1996-01-01

Possible nuclear microprobe applications in semiconductor industries are discussed. A unique technique using soft-error mapping and ion beam induced current measurements for reliability testing of dynamic random access memories such as soft-error immunity and noise carrier suppression has been developed for obtaining design parameters of future memory devices. Nano-probes and small installation areas are required for the use of microprobes in the semiconductor industry. Issues arising from microprobe applications such as damage induced by the probe beam are clarified. (orig.)

Semiconductor detectors in nuclear and particle physics

International Nuclear Information System (INIS)

Rehak, P.; Gatti, E.

1995-01-01

Semiconductor detectors for elementary particle physics and nuclear physics in the energy range above 1 GeV are briefly reviewed. In these two fields semiconductor detectors are used mainly for the precise position sensing. In a typical experiment, the position of a fast charged particle crossing a relatively thin semiconductor detector is measured. The position resolution achievable by semiconductor detectors is compared with the resolution achievable by gas filled position sensing detectors. Semiconductor detectors are divided into two groups; (i) classical semiconductor diode detectors and (ii) semiconductor memory detectors. Principles of the signal formation and the signal read-out for both groups of detectors are described. New developments of silicon detectors of both groups are reported. copyright 1995 American Institute of Physics

Single-event phenomena on recent semiconductor devices. Charge-type multiple-bit upsets in high integrated memories

International Nuclear Information System (INIS)

Makihara, Akiko; Shindou, Hiroyuki; Nemoto, Norio; Kuboyama, Satoshi; Matsuda, Sumio; Ohshima, Takeshi; Hirao, Toshio; Itoh, Hisayoshi

2001-01-01

High integrated memories are used in solid state data recorder (SSDR) of the satellite for accumulating observation data. Single event upset phenomena which turn over an accumulated data in the memory cells are caused by heavy ion incidence. Studies on single-bit upset and multiple-bit upset phenomena in the high integrated memory cells are in progress recently. 16 Mbit DRAM (Dynamic Random Access Memories) and 64 Mbit DRAM are irradiated by heavy ion species, such as iodine, bromine and nickel, in comparison with the irradiation damage in the cosmic environment. Data written on the memory devices are read out after the irradiation. The memory cells in three kinds of states, all of charged state, all of discharged state, and an alternative state of charge and discharge, are irradiated for sorting out error modes caused by heavy ion incidence. The soft error in a single memory cells is known as a turn over from charged state to discharged state. Electrons in electron-hole pair generated by heavy ion incidence are captured in a diffusion region between capacitor electrodes of semiconductor. The charged states in the capacitor electrodes before the irradiation are neutralized and changed to the discharged states. According to high integration of the memories, many of the cells are affected by a single ion incidence. The multiple-bit upsets, however, are generated in the memory cells of discharged state before the irradiation, also. The charge-type multiple-bit upsets is considered as that error data are written on the DRAM during refresh cycle of a sense-up circuit and a pre-charge circuit which control the DRAM. (M. Suetake)

Multicolour fluorescent memory based on the interaction of hydroxy terphenyls with fluoride anions.

Science.gov (United States)

Akamatsu, Masaaki; Mori, Taizo; Okamoto, Ken; Sakai, Hideki; Abe, Masahiko; Hill, Jonathan P; Ariga, Katsuhiko

2014-12-01

Memory operations based on variation of a molecule's properties are important because they may lead to device miniaturization to the molecular scale or increasingly complex information processing protocols beyond the binary level. Molecular memory also introduces possibilities related to information-storage security where chemical information (or reagents) might be used as an encryption key, in this case, acidic/basic reagents. Chemical memory that possesses both volatile and non-volatile functionality requires reversible conversion between at least two chemically different stable or quasi-stable states. Here we have developed the phenol-phenoxide equilibrium of phenol fluorophores as a data storage element, which can be used to write or modulate data using chemical reagents. The properties of this system allow data to be stored and erased either in non-volatile or volatile modes. We also demonstrate non-binary switching of states made possible by preparation of  a composite containing the molecular memory elements. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Towards Terabit Memories

Science.gov (United States)

Hoefflinger, Bernd

Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet

Silicon nano crystal-based non-volatile memory devices

International Nuclear Information System (INIS)

Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

2006-01-01

In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

Science.gov (United States)

MacLeod, Todd C.; Sims, W. Herb; Varnavas, Kosta A.; Ho, Fat D.

2011-01-01

NASA is planning on going beyond Low Earth orbit with manned exploration missions. The radiation environment for most Low Earth orbit missions is harsher than at the Earth's surface but much less harsh than deep space. Development of new electronics is needed to meet the requirements of high performance, radiation tolerance, and reliability. The need for both Volatile and Non-volatile memory has been identified. Emerging Non-volatile memory technologies (FRAM, C-RAM,M-RAM, R-RAM, Radiation Tolerant FLASH, SONOS, etc.) need to be investigated for use in Space missions. An opportunity arose to fly a small memory experiment on a high inclination satellite (FASTSAT). An off-the-shelf 512K Ramtron FRAM was chosen to be tested in the experiment.

Memory and pressure studies in Na{sub x}CoO{sub 2} cobaltites

Energy Technology Data Exchange (ETDEWEB)

Garbarino, G; Bouvier, P; Crichton, W A; Mezouar, M [European Synchrotron Radiation Facility, Grenoble (France); Regueiro, M Nunez; Lejay, P [MCBT, Institut Neel, Grenoble (France); Armand, M [LRCS, Universite Picardie Jules-Verne Amiens, Amiens (France); Foo, M L; Cava, R J, E-mail: gaston.garbarino@esrf.f [Department of Chemistry and Materials Institute, Princeton University, New Jersey (United States)

2009-03-01

We present a detailed study on the memory effect results in Na{sub 0.5} paragraph 5CoO{sub 2} single crystals. We analyze the temperature dependence of the nonvolatile current-pulse-induced resistance memory state. These results allow us to have more insight in the mobility of Na{sup +} ions induced by current and their effect on the memory effect. We also developed X-ray diffraction studies under pressure at ambient temperature in the N{sub a0.5}CoO{sub 2} powder compound. An orthorhombic to hexagonal phase transition was observed at 9GPa. This transition can be explained taking into account the Na ions displacement between two allowed positions. These structural results allow us to confirm that the non-volatile resistive commutation can be interpreted by the displacement of the Na ions induced by the current pulses.

Design of SMART alarm system using main memory database

International Nuclear Information System (INIS)

Jang, Kue Sook; Seo, Yong Seok; Park, Keun Oak; Lee, Jong Bok; Kim, Dong Hoon

2001-01-01

To achieve design goal of SMART alarm system, first of all we have to decide on how to handle and manage alarm information and how to use database. So this paper analyses concepts and deficiencies of main memory database applied in real time system. And this paper sets up structure and processing principles of main memory database using nonvolatile memory such as flash memory and develops recovery strategy and process board structures using these. Therefore this paper shows design of SMART alarm system is suited functions and requirements

High-Density Stacked Ru Nanocrystals for Nonvolatile Memory Application

International Nuclear Information System (INIS)

Ping, Mao; Zhi-Gang, Zhang; Li-Yang, Pan; Jun, Xu; Pei-Yi, Chen

2009-01-01

Stacked ruthenium (Ru) nanocrystals (NCs) are formed by rapid thermal annealing for the whole gate stacks and embedded in memory structure, which is compatible with conventional CMOS technology. Ru NCs with high density (3 × 10 12 cm −2 ), small size (2–4 nm) and good uniformity both in aerial distribution and morphology are formed. Attributed to the higher surface trap density, a memory window of 5.2 V is obtained with stacked Ru NCs in comparison to that of 3.5 V with single-layer samples. The stacked Ru NCs device also exhibits much better retention performance because of Coulomb blockade and vertical uniformity between stacked Ru NCs

Organic ferroelectric/semiconducting nanowire hybrid layer for memory storage

NARCIS (Netherlands)

Cai, R.; Kassa, H.G.; Haouari, R.; Marrani, A.; Geerts, Y.H.; Ruzié, C.; Breemen, A.J.J.M. van; Gelinck, G.H.; Nysten, B.; Hu, Z.; Jonas, A.M.

2016-01-01

Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and

Phase change memory based on SnSe{sub 4} alloy

Energy Technology Data Exchange (ETDEWEB)

Karanja, J.M.; Karimi, P.M.; Njoroge, W.K. [Physics Department, Kenyatta University, P.O. Box 43844, Nairobi (Kenya); Wamwangi, D.M., E-mail: Daniel.Wamwangi@wits.ac.za [School of Physics, University of the Witwatersrand, Private Bag 3, 2050 (South Africa)

2013-01-01

A phase change alloy has been synthesized and characterized. The reversible phase transitions between amorphous and crystalline states of SnSe{sub 4} films have been studied using variable electrical pulses and X-ray diffraction. Temperature dependent sheet resistance measurements have shown two distinct resistivity states of more than two orders of magnitude. This high electrical contrast makes the alloy suitable for nonvolatile phase change memory applications. X-ray diffraction has attributed the large electrical contrast to an amorphous–crystalline phase transition. The nonvolatile memory cells have been fabricated using a simple sandwich structure (metal/chalcogenide thin film/metal). A threshold voltage of 3.71 V has been determined for this phase change random access memory cell. Memory switching was initiated using the voltage pulses of 3.71 V, 90 ns, 1.3 V and 26 μs, for the crystallization and amorphization process, respectively. - Highlights: ► Phase transition of SnSe{sub 4} alloys with high set resistivity of 1.43 Ωm ► High transition temperatures of 174 °C ► Transition due to amorphous–crystalline changes ► Threshold switching at a high threshold voltage of 3.71 V.

Logic computation in phase change materials by threshold and memory switching.

Science.gov (United States)

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Magnetic vortex racetrack memory

Energy Technology Data Exchange (ETDEWEB)

Geng, Liwei D.; Jin, Yongmei M., E-mail: ymjin@mtu.edu

2017-02-01

We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications. - Highlights: • Advance fundamental knowledge of current-driven magnetic vortex phenomena. • Report appealing new magnetic racetrack memory based on current-controlled magnetic vortices in nanowires. • Provide a novel approach to adjust current magnitude for data propagation. • Overcome the limitations of domain wall racetrack memory.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

Science.gov (United States)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

On-chip photonic memory elements employing phase-change materials.

Science.gov (United States)

Rios, Carlos; Hosseini, Peiman; Wright, C David; Bhaskaran, Harish; Pernice, Wolfram H P

2014-03-05

Phase-change materials integrated into nanophotonic circuits provide a flexible way to realize tunable optical components. Relying on the enormous refractive-index contrast between the amorphous and crystalline states, such materials are promising candidates for on-chip photonic memories. Nonvolatile memory operation employing arrays of microring resonators is demonstrated as a route toward all-photonic chipscale information processing. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile field effect transistors based on protons and Si/SiO2Si structures

International Nuclear Information System (INIS)

Warren, W.L.; Vanheusden, K.; Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Knoll, M.G.; Devine, R.A.B.

1997-01-01

Recently, the authors have demonstrated that annealing Si/SiO 2 /Si structures in a hydrogen containing ambient introduces mobile H + ions into the buried SiO 2 layer. Changes in the H + spatial distribution within the SiO 2 layer were electrically monitored by current-voltage (I-V) measurements. The ability to directly probe reversible protonic motion in Si/SiO 2 /Si structures makes this an exemplar system to explore the physics and chemistry of hydrogen in the technologically relevant Si/SiO 2 structure. In this work, they illustrate that this effect can be used as the basis for a programmable nonvolatile field effect transistor (NVFET) memory that may compete with other Si-based memory devices. The power of this novel device is its simplicity; it is based upon standard Si/SiO 2 /Si technology and forming gas annealing, a common treatment used in integrated circuit processing. They also briefly discuss the effects of radiation on its retention properties

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

Science.gov (United States)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

Atomic layer deposition for semiconductors

CERN Document Server

Hwang, Cheol Seong

2014-01-01

This edited volume discusses atomic layer deposition (ALD) for all modern semiconductor devices, moving from the basic chemistry of ALD and modeling of ALD processes to sections on ALD for memories, logic devices, and machines.

Anisotropic modulation of magnetic properties and the memory effect in a wide-band (011)-Pr0.7Sr0.3MnO3/PMN-PT heterostructure

KAUST Repository

Zhao, Ying-Ying

2015-04-24

Memory effect of electric-field control on magnetic behavior in magnetoelectric composite heterostructures has been a topic of interest for a long time. Although the piezostrain and its transfer across the interface of ferroelectric/ferromagnetic films are known to be important in realizing magnetoelectric coupling, the underlying mechanism for nonvolatile modulation of magnetic behaviors remains a challenge. Here, we report on the electric-field control of magnetic properties in wide-band (011)-Pr0.7Sr0.3MnO3/0.7Pb(Mg1/3Nb2/3)O3-0.3PbTiO3 heterostructures. By introducing an electric-field-induced in-plane anisotropic strain field during the cooling process from room temperature, we observe an in-plane anisotropic, nonvolatile modulation of magnetic properties in a wide-band Pr0.7Sr0.3MnO3 film at low temperatures. We attribute this anisotropic memory effect to the preferential seeding and growth of ferromagnetic (FM) domains under the anisotropic strain field. In addition, we find that the anisotropic, nonvolatile modulation of magnetic properties gradually diminishes as the temperature approaches FM transition, indicating that the nonvolatile memory effect is temperature dependent. By taking into account the competition between thermal energy and the potential barrier of the metastable magnetic state induced by the anisotropic strain field, this distinct memory effect is well explained, which provides a promising approach for designing novel electric-writing magnetic memories.

Lower Bounds in the Asymmetric External Memory Model

DEFF Research Database (Denmark)

Jacob, Riko; Sitchinava, Nodari

2017-01-01

Motivated by the asymmetric read and write costs of emerging non-volatile memory technologies, we study lower bounds for the problems of sorting, permuting and multiplying a sparse matrix by a dense vector in the asymmetric external memory model (AEM). Given an AEM with internal (symmetric) memory...... of size M, transfers between symmetric and asymmetric memory in blocks of size B and the ratio ω between write and read costs, we show Ω(min (N, ωN/B logω M/B N/B) lower bound for the cost of permuting N input elements. This lower bound also applies to the problem of sorting N elements. This proves...

Single-Chip Computers With Microelectromechanical Systems-Based Magnetic Memory

NARCIS (Netherlands)

Carley, L. Richard; Bain, James A.; Fedder, Gary K.; Greve, David W.; Guillou, David F.; Lu, Michael S.C.; Mukherjee, Tamal; Santhanam, Suresh; Abelmann, Leon; Min, Seungook

This article describes an approach for implementing a complete computer system (CPU, RAM, I/O, and nonvolatile mass memory) on a single integrated-circuit substrate (a chip)—hence, the name "single-chip computer." The approach presented combines advances in the field of microelectromechanical

Integration of organic based Schottky junctions for crossbar non-volatile memory applications

DEFF Research Database (Denmark)

Katsia, E.; Tallarida, G.; Ferrari, S.

2008-01-01

Small size Schottky junctions using two different synthesized organic semiconductors (oligophenylene-vinylenes) were integrated by standard UV lithography into crossbar arrays. The proposed integration scheme can be applied to a wide class of organics without affecting material properties. Current...

Structural and Electrical Characteristics of Metal-Ferroelectric Pb1.1(Zr0.40Ti0.60O3-Insulator (ZnO-Silicon Capacitors for Nonvolatile Applications

Directory of Open Access Journals (Sweden)

S. R. Krishnamoorthi

2013-01-01

Full Text Available In this work metal-ferroelectric-insulator-semiconductor (MFIS thin-film structures using Pb1.1Zr0.40Ti0.60O3 (PZT as the ferroelectric layer and zinc oxide (ZnO as the insulator layer were fabricated on n-type (100 Si substrate. Pb1.1Zr0.40Ti0.60O3 and ZnO thin films were prepared on Si by the sol-gel route and thermal deposition method, respectively. On the optimized PZT (140 nm and ZnO (40 nm films were examined by scanning electron microscope (SEM. From AFM data the root mean square (r.m.s. roughness of the film surface is 13.11 nm. The leakage current density of ZnO/n-Si (MIS structure was as low as 1.8 × 10−8 A/cm2 at 2.5 V. The capacitance versus voltage (C-V characteristics of the annealed ZnO/Si (MIS diode indicated the good interface properties and no hysteresis was observed. Au/PZT (140 nm/ZnO (40 nm/Si (100 leakage-current density was about 5.7 × 10−8 A/cm2 at positive bias voltage of 3 V. The large memory window width in C-V (capacitance-voltage curve of Au/PZT/ZnO/Si capacitor was about 2.9 V under ±12 V which thus possibly enables nonvolatile applications. The memory window as a function of temperature was also discussed.

A non-destructive crossbar architecture of multi-level memory-based resistor

Science.gov (United States)

Sahebkarkhorasani, Seyedmorteza

Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6mum to 22 mum. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation.

Radiation tolerance of amorphous semiconductors

International Nuclear Information System (INIS)

Nicolaides, R.V.; DeFeo, S.; Doremus, L.W.

1976-01-01

In an attempt to determine the threshold radiation damage in amorphous semiconductors, radiation tests were performed on amorphous semiconductor thin film materials and on threshold and memory devices. The influence of flash x-rays and neutron radiation upon the switching voltages, on- and off-state characteristics, dielectric response, optical transmission, absorption band edge and photoconductivity were measured prior to, during and following irradiation. These extensive tests showed the high radiation tolerance of amorphous semiconductor materials. Electrical and optical properties, other than photoconductivity, have a neutron radiation tolerance threshold above 10 17 nvt in the steady state and 10 14 nvt in short (50 μsec to 16 msec) pulses. Photoconductivity increases by 1 1 / 2 orders of magnitude at the level of 10 14 nvt (short pulses of 50 μsec). Super flash x-rays up to 5000 rads (Si), 20 nsec, do not initiate switching in off-state samples which are voltage biased up to 90 percent of the threshold voltage. Both memory and threshold amorphous devices are capable of switching on and off during nuclear radiation transients at least as high as 2 x 10 14 nvt in 50 μsec pulses

The future of memory

Science.gov (United States)

Marinella, M.

In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

Self-patterning of arrays of ferroelectric capacitors: description by theory of substrate mediated strain interactions

International Nuclear Information System (INIS)

Dawber, M; Szafraniak, I; Alexe, M; Scott, J F

2003-01-01

Self-patterning presents an appealing alternative to lithography for the production of arrays of nanoscale ferroelectric capacitors for use in high density non-volatile memory devices. However current levels of registration achieved experimentally are far from adequate for this application. To provide a guide for experiment we have applied the theories developed for self-patterning of semiconductor nanocrystals to two self-patterning systems of potential interest for ferroelectric memory applications, metallic bismuth oxide on bismuth titanate and ferroelectric lead zirconate titanate on strontium titanate. (letter to the editor)

Nuclear data relevant to single event upsets in semiconductor memories induced by cosmic-ray neutrons and protons

International Nuclear Information System (INIS)

Watanabe, Yukinobu

2008-01-01

The role of nuclear data is examined in the study of single event upset (SEU) phenomena in semiconductor memories caused by cosmic-ray neutrons and protons. Neutron and proton SEU cross sections are calculated with a simplified semi-empirical model using experimental heavy-ion SEU cross-sections and a dedicated database of neutron and proton induced reactions on 28 Si. Some impacts of the nuclear reaction data on SEU simulation are analyzed by investigating relative contribution of secondary ions and neutron elastic scattering to SEU and influence of simultaneous multiple ions emission on SEU. (author)

A nanowire magnetic memory cell based on a periodic magnetic superlattice

International Nuclear Information System (INIS)

Song, J-F; Bird, J P; Ochiai, Y

2005-01-01

We analyse the operation of a semiconductor nanowire-based memory cell. Large changes in the nanowire conductance result when the magnetization of a periodic array of nanoscale magnetic gates, which comprise the other key component of the memory cell, is switched between distinct configurations by an external magnetic field. The resulting conductance change provides the basis for a robust memory effect, which can be implemented in a semiconductor structure compatible with conventional semiconductor integrated circuits

The role of EEPROM devices in upcoming ISDN applications

Science.gov (United States)

Nette, Herbert L.

1991-02-01

Integrated Services Digital Network (ISDN) equipments are rapidly becoming a major market for semiconductor chips. Although at first glance this growing market appears to be geared at logic chips, nonvolatile memories represent important support chips and will become a significant segment of this market. Challenges in these applications consist in operating EEPROMs at lower voltages and lower power and embedding them on ever more complex communications processor chips.

Optically controlled electroresistance and electrically controlled photovoltage in ferroelectric tunnel junctions

KAUST Repository

Jin Hu, Wei; Wang, Zhihong; Yu, Weili; Wu, Tao

2016-01-01

Ferroelectric tunnel junctions (FTJs) have recently attracted considerable interest as a promising candidate for applications in the next-generation non-volatile memory technology. In this work, using an ultrathin (3 nm) ferroelectric Sm0.1Bi0.9FeO3 layer as the tunnelling barrier and a semiconducting Nb-doped SrTiO3 single crystal as the bottom electrode, we achieve a tunnelling electroresistance as large as 105. Furthermore, the FTJ memory states could be modulated by light illumination, which is accompanied by a hysteretic photovoltaic effect. These complimentary effects are attributed to the bias- and light-induced modulation of the tunnel barrier, both in height and width, at the semiconductor/ferroelectric interface. Overall, the highly tunable tunnelling electroresistance and the correlated photovoltaic functionalities provide a new route for producing and non-destructively sensing multiple non-volatile electronic states in such FTJs.

Optically controlled electroresistance and electrically controlled photovoltage in ferroelectric tunnel junctions

KAUST Repository

Jin Hu, Wei

2016-02-29

Ferroelectric tunnel junctions (FTJs) have recently attracted considerable interest as a promising candidate for applications in the next-generation non-volatile memory technology. In this work, using an ultrathin (3 nm) ferroelectric Sm0.1Bi0.9FeO3 layer as the tunnelling barrier and a semiconducting Nb-doped SrTiO3 single crystal as the bottom electrode, we achieve a tunnelling electroresistance as large as 105. Furthermore, the FTJ memory states could be modulated by light illumination, which is accompanied by a hysteretic photovoltaic effect. These complimentary effects are attributed to the bias- and light-induced modulation of the tunnel barrier, both in height and width, at the semiconductor/ferroelectric interface. Overall, the highly tunable tunnelling electroresistance and the correlated photovoltaic functionalities provide a new route for producing and non-destructively sensing multiple non-volatile electronic states in such FTJs.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

Science.gov (United States)

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Peculiarities of charge transport in a semiconductor gas discharge electronic devices

International Nuclear Information System (INIS)

Koch, E.; Chivi, M.; Salamov, B.G.; Salamov, B.G.

2009-01-01

The memory effect in planar semiconductor gas discharge system at different pressures (15-760) and interelectrode distance (60-445 μm) were experimentally studied. The study was performed on the bases of current-voltage characteristic (CVC) measurements with the time lag of several hours of afterglow periods. The influence of the active space-charge remaining from previous discharge on the breakdown voltage has been analyzed using the CVC method for different conductivity of semiconductor GaAs photocathode. On the other hand, the CVC data for subsequent dates present a correlation of memory effect and hysteresis behaviour. The explanation of such relation is based on the influence of long-lived active charges on the electronic transport mechanism of semiconductor material

Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

International Nuclear Information System (INIS)

Liu, L.; Xu, J. P.; Ji, F.; Chen, J. X.; Lai, P. T.

2012-01-01

Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH 3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH 3 -annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO 2 interface.

Determination of uranium and thorium in semiconductor memory materials by high fluence neutron activation analysis

International Nuclear Information System (INIS)

Dyer, F.F.; Emery, J.F.; Northcutt, K.J.; Scott, R.M.

1981-01-01

Uranium and thorium were measured by absolute neutron activation analysis in high-purity materials used to manufacture semiconductor memories. The main thrust of the study concerned aluminum and aluminum alloys used as sources for thin film preparation, evaporated metal films, and samples from the Czochralski silicon crystal process. Average levels of U and Th were found for the source alloys to be approx. 65 and approx. 45 ppB, respectively. Levels of U and Th in silicon samples fell in the range of a few parts per trillion. Evaporated metal films contained about 1 ppB U and Th, but there is some question about these results due to the possibility of contamination

Three-terminal resistive switching memory in a transparent vertical-configuration device

International Nuclear Information System (INIS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

Directory of Open Access Journals (Sweden)

Chun Zhao

2014-10-01

Full Text Available Oxide materials with large dielectric constants (so-called high-k dielectrics have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs. A novel characterization (pulse capacitance-voltage method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future.

Deep electron traps in HfO_2-based metal-oxide-semiconductor capacitors

International Nuclear Information System (INIS)

Salomone, L. Sambuco; Lipovetzky, J.; Carbonetto, S.H.; García Inza, M.A.; Redin, E.G.; Campabadal, F.

2016-01-01

Hafnium oxide (HfO_2) is currently considered to be a good candidate to take part as a component in charge-trapping nonvolatile memories. In this work, the electric field and time dependences of the electron trapping/detrapping processes are studied through a constant capacitance voltage transient technique on metal-oxide-semiconductor capacitors with atomic layer deposited HfO_2 as insulating layer. A tunneling-based model is proposed to reproduce the experimental results, obtaining fair agreement between experiments and simulations. From the fitting procedure, a band of defects is identified, located in the first 1.7 nm from the Si/HfO_2 interface at an energy level E_t = 1.59 eV below the HfO_2 conduction band edge with density N_t = 1.36 × 10"1"9 cm"−"3. A simplified analytical version of the model is proposed in order to ease the fitting procedure for the low applied voltage case considered in this work. - Highlights: • We characterized deep electron trapping/detrapping in HfO_2 structures. • We modeled the experimental results through a tunneling-based model. • We obtained an electron trap energy level of 1.59 eV below conduction band edge. • We obtained a spatial trap distribution extending 1.7 nm within the insulator. • A simplified tunneling front model is able to reproduce the experimental results.

Novel room temperature ferromagnetic semiconductors

Energy Technology Data Exchange (ETDEWEB)

Gupta, Amita [KTH Royal Inst. of Technology, Stockholm (Sweden)

2004-06-01

Today's information world, bits of data are processed by semiconductor chips, and stored in the magnetic disk drives. But tomorrow's information technology may see magnetism (spin) and semiconductivity (charge) combined in one 'spintronic' device that exploits both charge and 'spin' to carry data (the best of two worlds). Spintronic devices such as spin valve transistors, spin light emitting diodes, non-volatile memory, logic devices, optical isolators and ultra-fast optical switches are some of the areas of interest for introducing the ferromagnetic properties at room temperature in a semiconductor to make it multifunctional. The potential advantages of such spintronic devices will be higher speed, greater efficiency, and better stability at a reduced power consumption. This Thesis contains two main topics: In-depth understanding of magnetism in Mn doped ZnO, and our search and identification of at least six new above room temperature ferromagnetic semiconductors. Both complex doped ZnO based new materials, as well as a number of nonoxides like phosphides, and sulfides suitably doped with Mn or Cu are shown to give rise to ferromagnetism above room temperature. Some of the highlights of this work are discovery of room temperature ferromagnetism in: (1) ZnO:Mn (paper in Nature Materials, Oct issue, 2003); (2) ZnO doped with Cu (containing no magnetic elements in it); (3) GaP doped with Cu (again containing no magnetic elements in it); (4) Enhancement of Magnetization by Cu co-doping in ZnO:Mn; (5) CdS doped with Mn, and a few others not reported in this thesis. We discuss in detail the first observation of ferromagnetism above room temperature in the form of powder, bulk pellets, in 2-3 mu-m thick transparent pulsed laser deposited films of the Mn (<4 at. percent) doped ZnO. High-resolution transmission electron microscopy (HRTEM) and electron energy loss spectroscopy (EELS) spectra recorded from 2 to 200nm areas showed homogeneous

Life-cycle assessment of semiconductors

CERN Document Server

Boyd, Sarah B

2012-01-01

Life-Cycle Assessment of Semiconductors presents the first and thus far only available transparent and complete life cycle assessment of semiconductor devices. A lack of reliable semiconductor LCA data has been a major challenge to evaluation of the potential environmental benefits of information technologies (IT). The analysis and results presented in this book will allow a higher degree of confidence and certainty in decisions concerning the use of IT in efforts to reduce climate change and other environmental effects. Coverage includes but is not limited to semiconductor manufacturing trends by product type and geography, unique coverage of life-cycle assessment, with a focus on uncertainty and sensitivity analysis of energy and global warming missions for CMOS logic devices, life cycle assessment of flash memory and life cycle assessment of DRAM. The information and conclusions discussed here will be highly relevant and useful to individuals and institutions. The book also: Provides a detailed, complete a...

Application of nanomaterials in two-terminal resistive-switching memory devices

Directory of Open Access Journals (Sweden)

Jianyong Ouyang

2010-05-01

Full Text Available Nanometer materials have been attracting strong attention due to their interesting structure and properties. Many important practical applications have been demonstrated for nanometer materials based on their unique properties. This article provides a review on the fabrication, electrical characterization, and memory application of two-terminal resistive-switching devices using nanomaterials as the active components, including metal and semiconductor nanoparticles (NPs, nanotubes, nanowires, and graphenes. There are mainly two types of device architectures for the two-terminal devices with NPs. One has a triple-layer structure with a metal film sandwiched between two organic semiconductor layers, and the other has a single polymer film blended with NPs. These devices can be electrically switched between two states with significant different resistances, i.e. the ‘ON’ and ‘OFF’ states. These render the devices important application as two-terminal non-volatile memory devices. The electrical behavior of these devices can be affected by the materials in the active layer and the electrodes. Though the mechanism for the electrical switches has been in argument, it is generally believed that the resistive switches are related to charge storage on the NPs. Resistive switches were also observed on crossbars formed by nanotubes, nanowires, and graphene ribbons. The resistive switches are due to nanoelectromechanical behavior of the materials. The Coulombic interaction of transient charges on the nanomaterials affects the configurable gap of the crossbars, which results into significant change in current through the crossbars. These nanoelectromechanical devices can be used as fast-response and high-density memory devices as well. Dr. Jianyong Ouyang received his bachelor degree from the Tsinghua University in Beijing, China, and MSc from the Institute of Chemistry, Chinese Academy of Science. He received his PhD from the Institute for Molecular

All-polymer bistable resistive memory device based on nanoscale phase-separated PCBM-ferroelectric blends

KAUST Repository

Khan, Yasser; Bhansali, Unnat Sampatraj; Cha, Dong Kyu; Alshareef, Husam N.

2012-01-01

All polymer nonvolatile bistable memory devices are fabricated from blends of ferroelectric poly(vinylidenefluoride-trifluoroethylene (P(VDF-TrFE)) and n-type semiconducting [6,6]-phenyl-C61-butyric acid methyl ester (PCBM). The nanoscale phase

Soluble dendrimers europium(III) β-diketonate complex for organic memory devices

International Nuclear Information System (INIS)

Wang Binbin; Fang Junfeng; Li Bin; You Han; Ma Dongge; Hong Ziruo; Li Wenlian; Su Zhongmin

2008-01-01

We report the synthesis of a soluble dendrimers europium(III) complex, tris(dibenzoylmethanato)(1,3,5-tris[2-(2'-pyridyl) benzimidazoly]methylbenzene)-europium(III), and its application in organic electrical bistable memory device. Excellent stability that ensured more than 10 6 write-read-erase-reread cycles has been performed in ambient conditions without current-induced degradation. High-density, low-cost memory, good film-firming property, fascinating thermal and morphological stability allow the application of the dendrimers europium(III) complex as an active medium in non-volatile memory devices

Electrical switching phenomenon and memory effect in the semiconductor chalcogenide glass Ge0.10 As0.20 Te0.70

International Nuclear Information System (INIS)

Haro, M.; Marquez, E.; Villares, P.; Jimenez-Garay, R.

1987-01-01

Electrical switching phenomenon, as well as the memory effect in the semiconductor chalcogenide glass Ge 0.10 As 0.20 Te 0.70 has been studied. A device with a plano-punctual interelectrode configuration has been designed and built, so that the electrical stimuli may be applied correctly. This device permits adequate positioning of the upper electrode, as well as contact pressure regulation. The I-V characteristics in the OFF-state have been obtained, showing a marked non-linear character. Equally, a relation has been found between the threshold voltage and electrical resistance parameters, indicating that the electrical power giving rise to the phenomenon is constant. Finally, memory effects showing a sudden reduction in electrical resistance, as well as interelectrode filaments, have been observed. (author)

Photoresponse and photo-induced memory effect in the organic field-effect transistor based on AlOX nanoparticles at the interface of semiconductor/dielectric

Science.gov (United States)

Cheng, Yunfei; Wang, Wu

2017-10-01

In this work, the photoresponse and photo-induced memory effect were demonstrated in an organic field-effect transistor (OFET) with semiconductor pentacene and SiO2 as the active and gate dielectric layers, respectively. By inserting AlOX nanoparticles (NPs) at the interface of pentacene/SiO2, obvious enhancing photoresponse was obtained in the OFET with the maximum responsivity and photosensitivity of about 15 A/W and 100, respectively. Moreover, the stable photoinduced memory effect was achieved in the OFET, attributing to the photogenerated electrons captured by the interface traps of the AlOX NPs/SiO2.

A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

Science.gov (United States)

She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

2017-02-01

A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Crossbar memory array of organic bistable rectifying diodes for nonvolatile data storage

NARCIS (Netherlands)

Asadi, Kamal; Li, Mengyuan; Stingelin, Natalie; Blom, Paul W. M.; de Leeuw, Dago M.

2010-01-01

Cross-talk in memories using resistive switches in a cross-bar geometry can be prevented by integration of a rectifying diode. We present a functional cross bar memory array using a phase separated blend of a ferroelectric and a semiconducting polymer as storage medium. Each intersection acts

Optical memory

Science.gov (United States)

Mao, Samuel S; Zhang, Yanfeng

2013-07-02

Optical memory comprising: a semiconductor wire, a first electrode, a second electrode, a light source, a means for producing a first voltage at the first electrode, a means for producing a second voltage at the second electrode, and a means for determining the presence of an electrical voltage across the first electrode and the second electrode exceeding a predefined voltage. The first voltage, preferably less than 0 volts, different from said second voltage. The semiconductor wire is optically transparent and has a bandgap less than the energy produced by the light source. The light source is optically connected to the semiconductor wire. The first electrode and the second electrode are electrically insulated from each other and said semiconductor wire.

Two-dimensional multiferroics in monolayer group IV monochalcogenides

Science.gov (United States)

Wang, Hua; Qian, Xiaofeng

2017-03-01

Low-dimensional multiferroic materials hold great promises in miniaturized device applications such as nanoscale transducers, actuators, sensors, photovoltaics, and nonvolatile memories. Here, using first-principles theory we predict that two-dimensional (2D) monolayer group IV monochalcogenides including GeS, GeSe, SnS, and SnSe are a class of 2D semiconducting multiferroics with giant strongly-coupled in-plane spontaneous ferroelectric polarization and spontaneous ferroelastic lattice strain that are thermodynamically stable at room temperature and beyond, and can be effectively modulated by elastic strain engineering. Their optical absorption spectra exhibit strong in-plane anisotropy with visible-spectrum excitonic gaps and sizable exciton binding energies, rendering the unique characteristics of low-dimensional semiconductors. More importantly, the predicted low domain wall energy and small migration barrier together with the coupled multiferroic order and anisotropic electronic structures suggest their great potentials for tunable multiferroic functional devices by manipulating external electrical, mechanical, and optical field to control the internal responses, and enable the development of four device concepts including 2D ferroelectric memory, 2D ferroelastic memory, and 2D ferroelastoelectric nonvolatile photonic memory as well as 2D ferroelectric excitonic photovoltaics.

A Retina-Like Dual Band Organic Photosensor Array for Filter-Free Near-Infrared-to-Memory Operations.

Science.gov (United States)

Wang, Hanlin; Liu, Hongtao; Zhao, Qiang; Ni, Zhenjie; Zou, Ye; Yang, Jie; Wang, Lifeng; Sun, Yanqiu; Guo, Yunlong; Hu, Wenping; Liu, Yunqi

2017-08-01

Human eyes use retina photoreceptor cells to absorb and distinguish photons from different wavelengths to construct an image. Mimicry of such a process and extension of its spectral response into the near-infrared (NIR) is indispensable for night surveillance, retinal prosthetics, and medical imaging applications. Currently, NIR organic photosensors demand optical filters to reduce visible interference, thus making filter-free and anti-visible NIR imaging a challenging task. To solve this limitation, a filter-free and conformal, retina-inspired NIR organic photosensor is presented. Featuring an integration of photosensing and floating-gate memory modules, the device possesses an acute color distinguishing capability. In general, the retina-like photosensor transduces NIR (850 nm) into nonvolatile memory and acts as a dynamic photoswitch under green light (550 nm). In doing this, a filter-free but color-distinguishing photosensor is demonstrated that selectively converts NIR optical signals into nonvolatile memory. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Access to long-term optical memories using photon echoes retrieved from semiconductor spins

Science.gov (United States)

Langer, L.; Poltavtsev, S. V.; Yugova, I. A.; Salewski, M.; Yakovlev, D. R.; Karczewski, G.; Wojtowicz, T.; Akimov, I. A.; Bayer, M.

2014-11-01

The ability to store optical information is important for both classical and quantum communication. Achieving this in a comprehensive manner (converting the optical field into material excitation, storing this excitation, and releasing it after a controllable time delay) is greatly complicated by the many, often conflicting, properties of the material. More specifically, optical resonances in semiconductor quantum structures with high oscillator strength are inevitably characterized by short excitation lifetimes (and, therefore, short optical memory). Here, we present a new experimental approach to stimulated photon echoes by transferring the information contained in the optical field into a spin system, where it is decoupled from the optical vacuum field and may persist much longer. We demonstrate this for an n-doped CdTe/(Cd,Mg)Te quantum well, the storage time of which could be increased by more than three orders of magnitude, from the picosecond range up to tens of nanoseconds.

Crossover from Super- to Subdiffusive Motion and Memory Effects in Crystalline Organic Semiconductors

Science.gov (United States)

De Filippis, G.; Cataudella, V.; Mishchenko, A. S.; Nagaosa, N.; Fierro, A.; de Candia, A.

2015-02-01

The transport properties at finite temperature of crystalline organic semiconductors are investigated, within the Su-Schrieffer-Heeger model, by combining an exact diagonalization technique, Monte Carlo approaches, and a maximum entropy method. The temperature-dependent mobility data measured in single crystals of rubrene are successfully reproduced: a crossover from super- to subdiffusive motion occurs in the range 150 ≤T ≤200 K , where the mean free path becomes of the order of the lattice parameter and strong memory effects start to appear. We provide an effective model, which can successfully explain features of the absorption spectra at low frequencies. The observed response to slowly varying electric field is interpreted by means of a simple model where the interaction between the charge carrier and lattice polarization modes is simulated by a harmonic interaction between a fictitious particle and an electron embedded in a viscous fluid.

Material Engineering for Phase Change Memory

Science.gov (United States)

Cabrera, David M.

As semiconductor devices continue to scale downward, and portable consumer electronics become more prevalent there is a need to develop memory technology that will scale with devices and use less energy, while maintaining performance. One of the leading prototypical memories that is being investigated is phase change memory. Phase change memory (PCM) is a non-volatile memory composed of 1 transistor and 1 resistor. The resistive structure includes a memory material alloy which can change between amorphous and crystalline states repeatedly using current/voltage pulses of different lengths and magnitudes. The most widely studied PCM materials are chalcogenides - Germanium-Antimony-Tellerium (GST) with Ge2Sb2Te3 and Germanium-Tellerium (GeTe) being some of the most popular stochiometries. As these cells are scaled downward, the current/voltage needed to switch these materials becomes comparable to the voltage needed to sense the cell's state. The International Roadmap for Semiconductors aims to raise the threshold field of these devices from 66.6 V/mum to be at least 375 V/mum for the year 2024. These cells are also prone to resistance drift between states, leading to bit corruption and memory loss. Phase change material properties are known to influence PCM device performance such as crystallization temperature having an effect on data retention and litetime, while resistivity values in the amorphous and crystalline phases have an effect on the current/voltage needed to write/erase the cell. Addition of dopants is also known to modify the phase change material parameters. The materials G2S2T5, GeTe, with dopants - nitrogen, silicon, titanium, and aluminum oxide and undoped Gallium-Antimonide (GaSb) are studied for these desired characteristics. Thin films of these compositions are deposited via physical vapor deposition at IBM Watson Research Center. Crystallization temperatures are investigated using time resolved x-ray diffraction at Brookhaven National Laboratory

High-performance and low-power rewritable SiOx 1 kbit one diode-one resistor crossbar memory array.

Science.gov (United States)

Wang, Gunuk; Lauchner, Adam C; Lin, Jian; Natelson, Douglas; Palem, Krishna V; Tour, James M

2013-09-14

An entire 1-kilobit crossbar device based upon SiOx resistive memories with integrated diodes has been made. The SiOx -based one diode-one resistor device system has promise to satisfy the prerequisite conditions for next generation non-volatile memory applications. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Switching behavior of resistive change memory using oxide nanowires

Science.gov (United States)

Aono, Takashige; Sugawa, Kosuke; Shimizu, Tomohiro; Shingubara, Shoso; Takase, Kouichi

2018-06-01

Resistive change random access memory (ReRAM), which is expected to be the next-generation nonvolatile memory, often has wide switching voltage distributions due to many kinds of conductive filaments. In this study, we have tried to suppress the distribution through the structural restriction of the filament-forming area using NiO nanowires. The capacitor with Ni metal nanowires whose surface is oxidized showed good switching behaviors with narrow distributions. The knowledge gained from our study will be very helpful in producing practical ReRAM devices.

Reprogrammable logic in memristive crossbar for in-memory computing

Science.gov (United States)

Cheng, Long; Zhang, Mei-Yun; Li, Yi; Zhou, Ya-Xiong; Wang, Zhuo-Rui; Hu, Si-Yu; Long, Shi-Bing; Liu, Ming; Miao, Xiang-Shui

2017-12-01

Memristive stateful logic has emerged as a promising next-generation in-memory computing paradigm to address escalating computing-performance pressures in traditional von Neumann architecture. Here, we present a nonvolatile reprogrammable logic method that can process data between different rows and columns in a memristive crossbar array based on material implication (IMP) logic. Arbitrary Boolean logic can be executed with a reprogrammable cell containing four memristors in a crossbar array. In the fabricated Ti/HfO2/W memristive array, some fundamental functions, such as universal NAND logic and data transfer, were experimentally implemented. Moreover, using eight memristors in a 2  ×  4 array, a one-bit full adder was theoretically designed and verified by simulation to exhibit the feasibility of our method to accomplish complex computing tasks. In addition, some critical logic-related performances were further discussed, such as the flexibility of data processing, cascading problem and bit error rate. Such a method could be a step forward in developing IMP-based memristive nonvolatile logic for large-scale in-memory computing architecture.

In search of the next memory inside the circuitry from the oldest to the emerging non-volatile memories

CERN Document Server

Campardo, Giovanni

2017-01-01

This book provides students and practicing chip designers with an easy-to-follow yet thorough, introductory treatment of the most promising emerging memories under development in the industry. Focusing on the chip designer rather than the end user, this book offers expanded, up-to-date coverage of emerging memories circuit design. After an introduction on the old solid-state memories and the fundamental limitations soon to be encountered, the working principle and main technology issues of each of the considered technologies (PCRAM, MRAM, FeRAM, ReRAM) are reviewed and a range of topics related to design is explored: the array organization, sensing and writing circuitry, programming algorithms and error correction techniques are reviewed comparing the approach followed and the constraints for each of the technologies considered. Finally the issue of radiation effects on memory devices has been briefly treated. Additionally some considerations are entertained about how emerging memories can find a place in the...

Measurements of non-volatile aerosols with a VTDMA and their correlations with carbonaceous aerosols in Guangzhou, China

Science.gov (United States)

Cheung, Heidi H. Y.; Tan, Haobo; Xu, Hanbing; Li, Fei; Wu, Cheng; Yu, Jian Z.; Chan, Chak K.

2016-07-01

Simultaneous measurements of aerosol volatility and carbonaceous matters were conducted at a suburban site in Guangzhou, China, in February and March 2014 using a volatility tandem differential mobility analyzer (VTDMA) and an organic carbon/elemental carbon (OC / EC) analyzer. Low volatility (LV) particles, with a volatility shrink factor (VSF) at 300 °C exceeding 0.9, contributed 5 % of number concentrations of the 40 nm particles and 11-15 % of the 80-300 nm particles. They were composed of non-volatile material externally mixed with volatile material, and therefore did not evaporate significantly at 300 °C. Non-volatile material mixed internally with the volatile material was referred to as medium volatility (MV, 0.4 transported at low altitudes (below 1500 m) for over 40 h before arrival. Further comparison with the diurnal variations in the mass fractions of EC and the non-volatile OC in PM2.5 suggests that the non-volatile residuals may be related to both EC and non-volatile OC in the afternoon, during which the concentration of aged organics increased. A closure analysis of the total mass of LV and MV residuals and the mass of EC or the sum of EC and non-volatile OC was conducted. It suggests that non-volatile OC, in addition to EC, was one of the components of the non-volatile residuals measured by the VTDMA in this study.

A Survey of Phase Change Memory Systems

Institute of Scientific and Technical Information of China (English)

夏飞; 蒋德钧; 熊劲; 孙凝晖

2015-01-01

As the scaling of applications increases, the demand of main memory capacity increases in order to serve large working set. It is difficult for DRAM (dynamic random access memory) based memory system to satisfy the memory capacity requirement due to its limited scalability and high energy consumption. Compared to DRAM, PCM (phase change memory) has better scalability, lower energy leakage, and non-volatility. PCM memory systems have become a hot topic of academic and industrial research. However, PCM technology has the following three drawbacks: long write latency, limited write endurance, and high write energy, which raises challenges to its adoption in practice. This paper surveys architectural research work to optimize PCM memory systems. First, this paper introduces the background of PCM. Then, it surveys research efforts on PCM memory systems in performance optimization, lifetime improving, and energy saving in detail, respectively. This paper also compares and summarizes these techniques from multiple dimensions. Finally, it concludes these optimization techniques and discusses possible research directions of PCM memory systems in future.

Silicon-based thin films as bottom electrodes in chalcogenide nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Lee, Seung-Yun [IT Convergence and Components Laboratory, Electronics and Telecommunications Research Institute (ETRI), Yuseong-gu, Daejeon 305-350 (Korea, Republic of)], E-mail: seungyun@etri.re.kr; Yoon, Sung-Min; Choi, Kyu-Jeong; Lee, Nam-Yeal; Park, Young-Sam; Ryu, Sang-Ouk; Yu, Byoung-Gon; Kim, Sang-Hoon; Lee, Sang-Heung [IT Convergence and Components Laboratory, Electronics and Telecommunications Research Institute (ETRI), Yuseong-gu, Daejeon 305-350 (Korea, Republic of)

2007-10-31

The effect of the electrical resistivity of a silicon-germanium (SiGe) thin film on the phase transition in a GeSbTe (GST) chalcogenide alloy and the manufacturing aspect of the fabrication process of a chalcogenide memory device employing the SiGe film as bottom electrodes were investigated. While p-type SiGe bottom electrodes were formed using in situ doping techniques, n-type ones could be made in a different manner where phosphorus atoms diffused from highly doped silicon underlayers to undoped SiGe films. The p-n heterojunction did not form between the p-type GST and n-type SiGe layers, and the semiconduction type of the SiGe alloys did not influence the memory device switching. It was confirmed that an optimum resistivity value existed for memory operation in spite of proportionality of Joule heating to electrical resistivity. The very high resistivity of the SiGe film had no effect on the reduction of reset current, which might result from the resistance decrease of the SiGe alloy at high temperatures.

Nonvolatile flexible organic bistable devices fabricated utilizing CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole polymer layer

International Nuclear Information System (INIS)

Son, Dong-Ick; Kim, Ji-Hwan; Park, Dong-Hee; Choi, Won Kook; Li, Fushan; Ham, Jung Hun; Kim, Tae Whan

2008-01-01

The bistable effects of CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole (PVK) polymer layer by using flexible poly-vinylidene difluoride (PVDF) and polyethylene terephthalate (PET) substrates were investigated. Transmission electron microscopy (TEM) images revealed that CdSe/ZnS nanoparticles were formed inside the PVK polymer layer. Current-voltage (I-V) measurement on the Al/[CdSe/ZnS nanoparticles+ PVK]/ITO/PVDF and Al/[CdSe/ZnS nanoparticles+ PVK ]/ITO/PET structures at 300 K showed a nonvolatile electrical bistability behavior with a flat-band voltage shift due to the existence of the CdSe/ZnS nanoparticles, indicative of trapping, storing and emission of charges in the electronic states of the CdSe nanoparticles. A bistable behavior for the fabricated organic bistable device (OBD) structures is described on the basis of the I-V results. These results indicate that OBDs fabricated by embedding inorganic CdSe/ZnS nanoparticles in a conducting polymer matrix on flexible substrates are prospects for potential applications in flexible nonvolatile flash memory devices

Highly scalable 3-D NAND-NOR hybrid-type dual bit per cell flash memory devices with an additional cut-off gate

International Nuclear Information System (INIS)

Cho, Seongjae; Shim, Wonbo; Park, Ilhan; Kim, Yoon; Park, Byunggook

2010-01-01

In this work, a nonvolatile memory (NVM) device of novel structure in 3 dimensions is introduced, and its operation physics is validated. It is based on a pillar structure in which two identical storage nodes are located for dual-bit operation. The two storage nodes on neighboring pillars are controlled by using one common control gate so that the space between silicon pillars can be further reduced. For compatibility with conventional memory operations, an additional cut-off gate is constructed under the common control gate. This is considered as the ultimate form for a 3-D nonvolatile memory device based on a double-gate structure. The underlying physics is explained, and the operational schemes are validated in various aspects by using a numerical device simulation. Also, critical issues in device design for higher reliability are discussed.

Emerging materials and devices in spintronic integrated circuits for energy-smart mobile computing and connectivity

International Nuclear Information System (INIS)

Kang, S.H.; Lee, K.

2013-01-01

A spintronic integrated circuit (IC) is made of a combination of a semiconductor IC and a dense array of nanometer-scale magnetic tunnel junctions. This emerging field is of growing scientific and engineering interest, owing to its potential to bring disruptive device innovation to the world of electronics. This technology is currently being pursued not only for scalable non-volatile spin-transfer-torque magnetoresistive random access memory, but also for various forms of non-volatile logic (Spin-Logic). This paper reviews recent advances in spintronic IC. Key discoveries and breakthroughs in materials and devices are highlighted in light of the broader perspective of their application in low-energy mobile computing and connectivity systems, which have emerged as leading drivers for the prevailing electronics ecosystem

Charge retention in scaled SONOS nonvolatile semiconductor memory devices—Modeling and characterization

Science.gov (United States)

Hu, Yin; White, Marvin H.

1993-10-01

A new analytical model is developed to investigate the influence of the charge loss processes in the retention mode of the SONOS NVSM device. The model considers charge loss by the following processes: (1) electron back-tunneling from the nitride traps to the Si conduction band, (2) electron back-tunneling from the nitride traps to the Si/SiO 2 interface traps and (3) hole injection from the Si valence band to the nitride traps. An amphoteric trap charge distribution is used in this model. The new charge retention model predicts that process (1) determines the short term retention, while processes (2) and (3) determine the long term retention. Good agreement has been reached between the results of analytical calculations and the experimental retention data on both surface channel and buried channel SONOS devices.

Solution-processed flexible NiO resistive random access memory device

Science.gov (United States)

Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

2018-04-01

Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

Static memory devices

NARCIS (Netherlands)

2012-01-01

A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one

α-particle shielding of semiconductor device

International Nuclear Information System (INIS)

McKeown, P.J.A.; Perry, J.P.; Waddell, J.M.; Barker, K.D.

1981-01-01

Soft errors in semiconductor devices, e.g. random access memories, arising from the bombardment of the device by alpha particles produced by the disintegration of minute traces of uranium or thorium in the packaging materials are prevented by coating the active surface of the semiconductor chip with a thin layer, e.g. 20 to 100 microns of an organic polymeric material, this layer being of sufficient thickness to absorb the particles. Typically, the polymer is a poly-imide formed by u.v. electron-beam or thermal curing of liquid monomer applied to the chip surface. (author)

The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

Science.gov (United States)

Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

2004-06-01

The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

Uncorrelated multiple conductive filament nucleation and rupture in ultra-thin high-κ dielectric based resistive random access memory

KAUST Repository

Wu, Xing; Li, Kun; Raghavan, Nagarajan; Bosman, Michel; Wang, Qing-Xiao; Cha, Dong Kyu; Zhang, Xixiang; Pey, Kin-Leong

2011-01-01

Resistive switching in transition metal oxides could form the basis for next-generation non-volatile memory (NVM). It has been reported that the current in the high-conductivity state of several technologically relevant oxide materials flows through

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

International Nuclear Information System (INIS)

Che, Yongli; Zhang, Yating; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan; Cao, Xiaolong; Dai, Haitao; Yang, Junbo

2016-01-01

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV th  ∼ 15 V) and a long retention time (>10 5  s). The magnitude of ΔV th depended on both P/E voltages and the bias voltage (V DS ): ΔV th was a cubic function to V P/E and linearly depended on V DS . Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

Scandium doped Ge2Sb2Te5 for high-speed and low-power-consumption phase change memory

Science.gov (United States)

Wang, Yong; Zheng, Yonghui; Liu, Guangyu; Li, Tao; Guo, Tianqi; Cheng, Yan; Lv, Shilong; Song, Sannian; Ren, Kun; Song, Zhitang

2018-03-01

To bridge the gap of access time between memories and storage systems, the concept of storage class memory has been put forward based on emerging nonvolatile memory technologies. For all the nonvolatile memory candidates, the unpleasant tradeoff between operation speed and retention seems to be inevitable. To promote both the write speed and the retention of phase change memory (PCM), Sc doped Ge2Sb2Te5 (SGST) has been proposed as the storage medium. Octahedral Sc-Te motifs, acting as crystallization precursors to shorten the nucleation incubation period, are the possible reason for the high write speed of 6 ns in PCM cells, five-times faster than that of Ge2Sb2Te5 (GST) cells. Meanwhile, an enhanced 10-year data retention of 119 °C has been achieved. Benefiting from both the increased crystalline resistance and the inhibited formation of the hexagonal phase, the SGST cell has a 77% reduction in power consumption compared to the GST cell. Adhesion of the SGST/SiO2 interface has been strengthened, attributed to the reduced stress by forming smaller grains during crystallization, guaranteeing the reliability of the device. These improvements have made the SGST material a promising candidate for PCM application.

MoO3 trapping layers with CF4 plasma treatment in flash memory applications

International Nuclear Information System (INIS)

Kao, Chuyan Haur; Chen, Hsiang; Chen, Su-Zhien; Chen, Chian Yu; Lo, Kuang-Yu; Lin, Chun Han

2014-01-01

Highlights: • MoO 3 -based flash memories have been fabricated. • CF4 plasma treatment could enhance good memory performance. • Material analyses confirm that plasma treatment eliminated defects. • Fluorine atoms might fix the dangling bonds. - Abstract: In this research, we used MoO 3 with CF 4 plasma treatment as charge trapping layer in metal-oxide-high-k -oxide-Si-type memory. We analyzed material properties and electrical characteristics with multiple analyses. The plasma treatment could increase the trapping density, reduce the leakage current, expand band gap, and passivate the defect to enhance the memory performance. The MoO 3 charge trapping layer memory with suitable CF 4 plasma treatment is promising for future nonvolatile memory applications

Architecture and performance of radiation-hardened 64-bit SOS/MNOS memory

International Nuclear Information System (INIS)

Kliment, D.C.; Ronen, R.S.; Nielsen, R.L.; Seymour, R.N.; Splinter, M.R.

1976-01-01

This paper discusses the circuit architecture and performance of a nonvolatile 64-bit MNOS memory fabricated on silicon on sapphire (SOS). The circuit is a test vehicle designed to demonstrate the feasibility of a high-performance, high-density, radiation-hardened MNOS/SOS memory. The array is organized as 16 words by 4 bits and is fully decoded. It utilizes a two-(MNOS) transistor-per-bit cell and differential sensing scheme and is realized in PMOS static resistor load logic. The circuit was fabricated and tested as both a fast write random access memory (RAM) and an electrically alterable read only memory (EAROM) to demonstrate design and process flexibility. Discrete device parameters such as retention, circuit electrical characteristics, and tolerance to total dose and transient radiation are presented

Carrier concentration induced ferromagnetism in semiconductors

International Nuclear Information System (INIS)

Story, T.

2007-01-01

In semiconductor spintronics the key materials issue concerns ferromagnetic semiconductors that would, in particular, permit an integration (in a single multilayer heterostructure) of standard electronic functions of semiconductors with magnetic memory function. Although classical semiconductor materials, such as Si or GaAs, are nonmagnetic, upon substitutional incorporation of magnetic ions (typically of a few atomic percents of Mn 2+ ions) and very heavy doping with conducting carriers (at the level of 10 20 - 10 21 cm -3 ) a ferromagnetic transition can be induced in such diluted magnetic semiconductors (also known as semimagnetic semiconductors). In the lecture the spectacular experimental observations of carrier concentration induced ferromagnetism will be discussed for three model semiconductor crystals. p - Ga 1-x Mn x As currently the most actively studied and most perspective ferromagnetic semiconductor of III-V group, in which ferromagnetism appears due to Mn ions providing both local magnetic moments and acting as acceptor centers. p - Sn 1-x Mn x Te and p - Ge 1-x Mn x Te classical diluted magnetic semiconductors of IV-VI group, in which paramagnet-ferromagnet and ferromagnet-spin glass transitions are found for very high hole concentration. n - Eu 1-x Gd x Te mixed magnetic crystals, in which the substitution of Gd 3+ ions for Eu 2+ ions creates very high electron concentration and transforms antiferromagnetic EuTe (insulating compound) into ferromagnetic n-type semiconductor alloy. For each of these materials systems the key physical features will be discussed concerning: local magnetic moments formation, magnetic phase diagram as a function of magnetic ions and carrier concentration as well as Curie temperature and magnetic anisotropy engineering. Various theoretical models proposed to explain the effect of carrier concentration induced ferromagnetism in semiconductors will be briefly discussed involving mean field approaches based on Zener and RKKY

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

Energy Technology Data Exchange (ETDEWEB)

Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); Cao, Xiaolong [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); College of Mechanical and Electronic Engineering, Shandong University of Science and Technology, Qingdao 266590 (China); Dai, Haitao [Tianjin Key Laboratory of Low Dimensional Materials Physics and Preparing Technology, School of Science, Tianjin University, Tianjin 300072 (China); Yang, Junbo [Center of Material Science, National University of Defense Technology, Changsha 410073 (China)

2016-07-04

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th} was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

Enhanced non-volatile and updatable holography using a polymer composite system.

Science.gov (United States)

Wu, Pengfei; Sun, Sam Q; Baig, Sarfaraz; Wang, Michael R

2012-03-12

Updatable holography is considered as the ultimate technique for true 3D information recording and display. However, there is no practical solution to preserve the required features of both non-volatility and reversibility which conflict with each other when the reading has the same wavelength as the recording. We demonstrate a non-volatile and updatable holographic approach by exploiting new features of molecular transformations in a polymer recording system. In addition, by using a new composite recording film containing photo-reconfigurable liquid-crystal (LC) polymer, the holographic recording is enhanced due to the collective reorientation of LC molecules around the reconfigured polymer chains.

Charging and exciton-mediated decharging of metal nanoparticles in organic semiconductor matrices

International Nuclear Information System (INIS)

Ligorio, Giovanni; Vittorio Nardi, Marco; Christodoulou, Christos; Florea, Ileana; Ersen, Ovidiu; Monteiro, Nicolas-Crespo; Brinkmann, Martin; Koch, Norbert

2014-01-01

Gold nanoparticles (Au-NPs) were deposited on the surface of n- and p-type organic semiconductors to form defined model systems for charge storage based electrically addressable memory elements. We used ultraviolet photoelectron spectroscopy to study the electronic properties and found that the Au-NPs become positively charged because of photoelectron emission, evidenced by spectral shifts to higher binding energy. Upon illumination with light that can be absorbed by the organic semiconductors, dynamic charge neutrality of the Au-NPs could be re-established through electron transfer from excitons. The light-controlled charge state of the Au-NPs could add optical addressability to memory elements

Effect of ion implantation energy for the synthesis of Ge nanocrystals in SiN films with HfO2/SiO2 stack tunnel dielectrics for memory application

Directory of Open Access Journals (Sweden)

Gloux Florence

2011-01-01

Full Text Available Abstract Ge nanocrystals (Ge-NCs embedded in SiN dielectrics with HfO2/SiO2 stack tunnel dielectrics were synthesized by utilizing low-energy (≤5 keV ion implantation method followed by conventional thermal annealing at 800°C, the key variable being Ge+ ion implantation energy. Two different energies (3 and 5 keV have been chosen for the evolution of Ge-NCs, which have been found to possess significant changes in structural and chemical properties of the Ge+-implanted dielectric films, and well reflected in the charge storage properties of the Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si metal-insulator-semiconductor (MIS memory structures. No Ge-NC was detected with a lower implantation energy of 3 keV at a dose of 1.5 × 1016 cm-2, whereas a well-defined 2D-array of nearly spherical and well-separated Ge-NCs within the SiN matrix was observed for the higher-energy-implanted (5 keV sample for the same implanted dose. The MIS memory structures implanted with 5 keV exhibits better charge storage and retention characteristics compared to the low-energy-implanted sample, indicating that the charge storage is predominantly in Ge-NCs in the memory capacitor. A significant memory window of 3.95 V has been observed under the low operating voltage of ± 6 V with good retention properties, indicating the feasibility of these stack structures for low operating voltage, non-volatile memory devices.

Studies on nonvolatile resistance memory switching in ZnO thin films

Indian Academy of Sciences (India)

Administrator

(Kund et al 2005), phase change random access memory. (PRAM) (Lai 2003) and ..... 2008) and can be explained in terms of the aforemen- tioned filamentary ... Zhang S, Long S, Guan W, Liu Q, Wang Q and Liu M 2009 J. Phys. D: Appl. Phys.

Memory mass storage

CERN Document Server

Campardo, Giovanni; Iaculo, Massimo

2011-01-01

Covering all the fundamental storage technologies such as semiconductor, magnetic, optical and uncommon, this volume details their core characteristics. In addition, it includes an overview of the 'biological memory' of the human brain and its organization.

Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

International Nuclear Information System (INIS)

Avila-Nino, J.A.; Segura-Cardenas, E.; Sustaita, A.O.; Cruz-Cruz, I.; Lopez-Sandoval, R.; Reyes-Reyes, M.

2011-01-01

We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

Energy Technology Data Exchange (ETDEWEB)

Avila-Nino, J.A.; Segura-Cardenas, E. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Sustaita, A.O. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Cruz-Cruz, I. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Lopez-Sandoval, R. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Reyes-Reyes, M., E-mail: reyesm@iico.uaslp.mx [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico)

2011-03-25

We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

Materials and Physics Challenges for Spin Transfer Torque Magnetic Random Access Memories

Energy Technology Data Exchange (ETDEWEB)

Heinonen, O.

2014-10-05

Magnetic random access memories utilizing the spin transfer torque effect for writing information are a strong contender for non-volatile memories scalable to the 20 nm node, and perhaps beyond. I will here examine how these devices behave as the device size is scaled down from 70 nm size to 20 nm. As device sizes go below ~50 nm, the size becomes comparable to intrinsic magnetic length scales and the device behavior does not simply scale with size. This has implications for the device design and puts additional constraints on the materials in the device.

Flash memories economic principles of performance, cost and reliability optimization

CERN Document Server

Richter, Detlev

2014-01-01

The subject of this book is to introduce a model-based quantitative performance indicator methodology applicable for performance, cost and reliability optimization of non-volatile memories. The complex example of flash memories is used to introduce and apply the methodology. It has been developed by the author based on an industrial 2-bit to 4-bit per cell flash development project. For the first time, design and cost aspects of 3D integration of flash memory are treated in this book. Cell, array, performance and reliability effects of flash memories are introduced and analyzed. Key performance parameters are derived to handle the flash complexity. A performance and array memory model is developed and a set of performance indicators characterizing architecture, cost and durability is defined.   Flash memories are selected to apply the Performance Indicator Methodology to quantify design and technology innovation. A graphical representation based on trend lines is introduced to support a requirement based pr...

Process Qualification Strategy for Advances Embedded Non Volatile Memory Technology : The Philips' 0.18um Embedded Flash Case

NARCIS (Netherlands)

Tao, Guoqiao; Scarpa, Andrea; van Dijk, Kitty; Kuper, Fred G.

2003-01-01

A qualification strategy for advanced embedded non-volatile memory technology has been revealed. This strategy consists of: a thorough understanding of the requirements, extensive use and frequent update of the FMEA (failure mode effect analysis), a qualification plan with excellent coverage of all

A study on carbon nanotube bridge as a electromechanical memory device

Science.gov (United States)

Kang, Jeong Won; Ha Lee, Jun; Joo Lee, Hoong; Hwang, Ho Jung

2005-04-01

A nanoelectromechanical (NEM) nanotube random access memory (NRAM) device based on carbon nanotube (CNT) was investigated using atomistic simulations. For the CNT-based NEM memory, the mechanical properties of the CNT-bridge and van der Waals interactions between the CNT-bridge and substrate were very important. The critical amplitude of the CNT-bridge was 16% of the length of the CNT-bridge. As molecular dynamics time increased, the CNT-bridge went to the steady state under the electrostatic force with the damping of the potential and the kinetic energies of the CNT-bridge. The interatomic interaction between the CNT-bridge and substrate, value of the CNT-bridge slack, and damping rate of the CNT-bridge were very important for the operation of the NEM memory device as a nonvolatile memory.

Magnetization Dynamics in Two Novel Current-Driven Spintronic Memory Cell Structures

KAUST Repository

Velazquez-Rizo, Martin

2017-07-01

In this work, two new spintronic memory cell structures are proposed. The first cell uses the diffusion of polarized spins into ferromagnets with perpendicular anisotropy to tilt their magnetization followed by their dipolar coupling to a fixed magnet (Bhowmik et al., 2014). The possibility of setting the magnetization to both stable magnetization states in a controlled manner using a similar concept remains unknown, but the proposed structure poses to be a solution to this difficulty. The second cell proposed takes advantage of the multiple stable magnetic states that exist in ferromagnets with configurational anisotropy and also uses spin torques to manipulate its magnetization. It utilizes a square-shaped ferromagnet whose stable magnetization has preferred directions along the diagonals of the square, giving four stable magnetic states allowing to use the structure as a multi-bit memory cell. Both devices use spin currents generated in heavy metals by the Spin Hall effect present in these materials. Among the advantages of the structures proposed are their inherent non-volatility and the fact that there is no need for applying external magnetic fields during their operation, which drastically improves the energy efficiency of the devices. Computational simulations using the Object Oriented Micromagnetic Framework (OOMMF) software package were performed to study the dynamics of the magnetization process in both structures and predict their behavior. Besides, we fabricated a 4-terminal memory cell with configurational anisotropy similar to the device proposed, and found four stable resistive states on the structure, proving the feasibility of this technology for implementation of high-density, non-volatile memory cells.

PRISM -- A tool for modelling proton energy deposition in semiconductor materials

International Nuclear Information System (INIS)

Oldfield, M.K.; Underwood, C.I.

1996-01-01

This paper presents a description of, and test results from, a new PC based software simulation tool PRISM (Protons in Semiconductor Materials). The model describes proton energy deposition in complex 3D sensitive volumes of semiconductor materials. PRISM is suitable for simulating energy deposition in surface-barrier detectors and semiconductor memory devices, the latter being susceptible to Single-Event Upset (SEU) and Multiple-Bit Upset (MBU). The design methodology on which PRISM is based, together with the techniques used to simulate ion transport and energy deposition, are described. Preliminary test results used to analyze the PRISM model are presented

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

International Nuclear Information System (INIS)

Ando, K.; Yuasa, S.; Fujita, S.; Ito, J.; Yoda, H.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.

2014-01-01

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed

Effect of AlN layer on the bipolar resistive switching behavior in TiN thin film based ReRAM device for non-volatile memory application

Science.gov (United States)

Prakash, Ravi; Kaur, Davinder

2018-05-01

The effect of an additional AlN layer in the Cu/TiN/AlN/Pt stack configuration deposited using sputtering has been investigated. The Cu/TiN/AlN/Pt device shows a tristate resistive switching. Multilevel switching is facilitated by ionic and metallic filament formation, and the nature of the filaments formed is confirmed by performing a resistance vs. temperature measurement. Ohmic behaviour and trap controlled space charge limited current (SCLC) conduction mechanisms are confirmed as dominant conduction mechanism at low resistance state (LRS) and high resistance state (HRS). High resistance ratio (102) corresponding to HRS and LRS, good write/erase endurance (105) and non-volatile long retention (105s) are also observed. Higher thermal conductivity of the AlN layer is the main reasons for the enhancement of resistive switching performance in Cu/TiN/AlN/Pt cell. The above result suggests the feasibility of Cu/TiN/AlN/Pt devices for multilevel nonvolatile ReRAM application.

Microscale memory characteristics of virus-quantum dot hybrids

Science.gov (United States)

Portney, Nathaniel G.; Tseng, Ricky J.; Destito, Giuseppe; Strable, Erica; Yang, Yang; Manchester, Marianne; Finn, M. G.; Ozkan, Mihrimah

2007-05-01

An electrical multi stability effect was observed for a single layer device fabricated, comprising a hybrid virus-semiconducting quantum dot (CdSe /ZnS core/shell Qds) assembled onto icosahedral-mutant-virus template (CPMV-T184C). A substrate based bottom-up pathway was used to conjugate two different color emitting Qds for fluorescence visualization and to insert a charging/decharging factor. Pulsed wave measurements depicted distinct conductive states with repeatable and nonvolatile behavior as a functioning memory element.

Ferroelectric tunneling element and memory applications which utilize the tunneling element

Science.gov (United States)

Kalinin, Sergei V [Knoxville, TN; Christen, Hans M [Knoxville, TN; Baddorf, Arthur P [Knoxville, TN; Meunier, Vincent [Knoxville, TN; Lee, Ho Nyung [Oak Ridge, TN

2010-07-20

A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.

EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches

Energy Technology Data Exchange (ETDEWEB)

Mittal, Sparsh [ORNL; Vetter, Jeffrey S [ORNL

2014-01-01

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.

Bipolar one diode-one resistor integration for high-density resistive memory applications.

Science.gov (United States)

Li, Yingtao; Lv, Hangbing; Liu, Qi; Long, Shibing; Wang, Ming; Xie, Hongwei; Zhang, Kangwei; Huo, Zongliang; Liu, Ming

2013-06-07

Different from conventional unipolar-type 1D-1R RRAM devices, a bipolar-type 1D-1R memory device concept is proposed and successfully demonstrated by the integration of Ni/TiOx/Ti diode and Pt/HfO2/Cu bipolar RRAM cell to suppress the undesired sneak current in a cross-point array. The bipolar 1D-1R memory device not only achieves self-compliance resistive switching characteristics by the reverse bias current of the Ni/TiOx/Ti diode, but also exhibits excellent bipolar resistive switching characteristics such as uniform switching, satisfactory data retention, and excellent scalability, which give it high potentiality for high-density integrated nonvolatile memory applications.

Studies on nonvolatile resistance memory switching in ZnO thin films

Indian Academy of Sciences (India)

Six decades of research on ZnO has recently sprouted a new branch in the domain of resistive random access memories. Highly resistive and c-axis oriented ZnO thin films were grown by us using d.c. discharge assisted pulsed laser deposition on Pt/Ti/SiO2/Si substrates at room temperature. The resistive switching ...

Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

Science.gov (United States)

Seiler, David G.

1997-10-01

A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

Science.gov (United States)

Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

2017-12-01

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

Charged Semiconductor Defects Structure, Thermodynamics and Diffusion

CERN Document Server

Seebauer, Edmund G

2009-01-01

The technologically useful properties of a solid often depend upon the types and concentrations of the defects it contains. Not surprisingly, defects in semiconductors have been studied for many years, in many cases with a view towards controlling their behavior through various forms of "defect engineering." For example, in the bulk, charging significantly affects the total concentration of defects that are available to mediate phenomena such as solid-state diffusion. Surface defects play an important role in mediating surface mass transport during high temperature processing steps such as epitaxial film deposition, diffusional smoothing in reflow, and nanostructure formation in memory device fabrication. Charged Semiconductor Defects details the current state of knowledge regarding the properties of the ionized defects that can affect the behavior of advanced transistors, photo-active devices, catalysts, and sensors. Features: Group IV, III-V, and oxide semiconductors; Intrinsic and extrinsic defects; and, P...

Electric-field-controlled interface dipole modulation for Si-based memory devices.

Science.gov (United States)

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Nanographene charge trapping memory with a large memory window

International Nuclear Information System (INIS)

Meng, Jianling; Yang, Rong; Zhao, Jing; He, Congli; Wang, Guole; Shi, Dongxia; Zhang, Guangyu

2015-01-01

Nanographene is a promising alternative to metal nanoparticles or semiconductor nanocrystals for charge trapping memory. In general, a high density of nanographene is required in order to achieve high charge trapping capacity. Here, we demonstrate a strategy of fabrication for a high density of nanographene for charge trapping memory with a large memory window. The fabrication includes two steps: (1) direct growth of continuous nanographene film; and (2) isolation of the as-grown film into high-density nanographene by plasma etching. Compared with directly grown isolated nanographene islands, abundant defects and edges are formed in nanographene under argon or oxygen plasma etching, i.e. more isolated nanographene islands are obtained, which provides more charge trapping sites. As-fabricated nanographene charge trapping memory shows outstanding memory properties with a memory window as wide as ∼9 V at a relative low sweep voltage of ±8 V, program/erase speed of ∼1 ms and robust endurance of >1000 cycles. The high-density nanographene charge trapping memory provides an outstanding alternative for downscaling technology beyond the current flash memory. (paper)

Study of radiation effects on semiconductor devices

International Nuclear Information System (INIS)

Kuboyama, Satoshi; Shindou, Hiroyuki; Ikeda, Naomi; Iwata, Yoshiyuki; Murakami, Takeshi

2004-01-01

Fine structure of the recent semiconductor devices has made them more sensitive to the space radiation environment with trapped high-energy protons and heavy ions. A new failure mode caused by bulk damage had been reported on such devices with small structure, and its effect on commercial synchronous dynamic random access memory (SDRAMs) was analyzed from the irradiation test results performed at Heavy ion Medical Accelerator in Chiba (HIMAC). Single event upset (SEU) data of static random access memory (SRAMs) were also collected to establish the method of estimating the proton-induced SEU rate from the results of heavy ion irradiation tests. (authors)

WORM memory devices based on conformation change of a PVK derivative with a rigid spacer in side chain

International Nuclear Information System (INIS)

Liu Yuanhua; Li Najun; Xia Xuewei; Xu Qingfeng; Ge Jianfeng; Lu Jianmei

2010-01-01

A nonvolatile write-once-read-many-times (WORM) memory device based on poly((4-vinylbenzyl)-9H-carbazole) (PVCz) was fabricated by a simple and conventional process. The as-fabricated device was found to be at its OFF state and could be programmed irreversibly to the ON state with a low transition voltage of -1.7 V. The device exhibits a high ON/OFF current ratio of up to 10 6 , high stability in retention time up to 8 h and number of read cycles up to 10 8 under a read voltage of -1.0 V in both ON and OFF states. The results of X-ray diffraction (XRD) and fluorescence emission spectra in different states of PVCz indicate that the electrical bistable phenomenon is caused by the voltage-induced conformation change of the pendant carbazole groups. With high performance, low power consumption and low production cost, the device fabricated with PVCz has a potential application for nonvolatile memory.

Measurements of non-volatile aerosols with a VTDMA and their correlations with carbonaceous aerosols in Guangzhou, China

Directory of Open Access Journals (Sweden)

H. H. Y. Cheung

2016-07-01

Full Text Available Simultaneous measurements of aerosol volatility and carbonaceous matters were conducted at a suburban site in Guangzhou, China, in February and March 2014 using a volatility tandem differential mobility analyzer (VTDMA and an organic carbon/elemental carbon (OC ∕ EC analyzer. Low volatility (LV particles, with a volatility shrink factor (VSF at 300 °C exceeding 0.9, contributed 5 % of number concentrations of the 40 nm particles and 11–15 % of the 80–300 nm particles. They were composed of non-volatile material externally mixed with volatile material, and therefore did not evaporate significantly at 300 °C. Non-volatile material mixed internally with the volatile material was referred to as medium volatility (MV, 0.4  <  VSF  <  0.9 and high volatility (HV, VSF  <  0.4 particles. The MV and HV particles contributed 57–71 % of number concentration for the particles between 40 and 300 nm in size. The average EC and OC concentrations measured by the OC ∕ EC analyzer were 3.4 ± 3.0 and 9.0 ± 6.0 µg m−3, respectively. Non-volatile OC evaporating at 475 °C or above, together with EC, contributed 67 % of the total carbon mass. In spite of the daily maximum and minimum, the diurnal variations in the volume fractions of the volatile material, HV, MV and LV residuals were less than 15 % for the 80–300 nm particles. Back trajectory analysis also suggests that over 90 % of the air masses influencing the sampling site were well aged as they were transported at low altitudes (below 1500 m for over 40 h before arrival. Further comparison with the diurnal variations in the mass fractions of EC and the non-volatile OC in PM2.5 suggests that the non-volatile residuals may be related to both EC and non-volatile OC in the afternoon, during which the concentration of aged organics increased. A closure analysis of the total mass of LV and MV residuals and the mass of EC or the

Electrical properties of SrBi2Ta2O9 thin films deposited on Si (100) substrates by rf magnetron sputtering

International Nuclear Information System (INIS)

Roy, A.; Jha, G.; Dhar, A.; Ray, S.K.; Manna, I.

2008-01-01

Recently, metal-ferroelectric-semiconductor (MFS) structures have attracted much attention because of its potentials as nonvolatile memory device with nondestructive readout operation. In the present study ferroelectric SrBi 2 Ta 2 O 9 (SBT) thin films are grown on p-type (100) Si substrates by rf magnetron sputtering method at different deposition conditions. The crystallinity of the films is studied using grazing incidence X-ray diffraction (GIXRD) pattern. The spectra show the film are polycrystalline with dominant orientation along (115) plane. The capacitance-voltage (C-V) characteristics of Al/SBT/Si capacitors were measured at 100 kHz. The (C-V) characteristic of AI/SBT/Si capacitor post-annealed at 700-800 deg C shows a hysteresis nature with a clockwise rotation and the memory window of the hysteresis loop is 0.88 V when the gate voltage is ± 5 V. The interface trap density (D it ) calculated by using Hills method at room temperature and a value in the order of 10 11 -10 12 eV -1 cm -2 was found at mid gap region depending on the crystallization temperature. The surface morphology was investigated by atomic force microscope (AFM). The study showed the potential of SBT for application in metal- ferroelectric-silicon nonvolatile memory devices. (author)

Bulk heterojunction polymer memory devices with reduced graphene oxide as electrodes.

Science.gov (United States)

Liu, Juqing; Yin, Zongyou; Cao, Xiehong; Zhao, Fei; Lin, Anping; Xie, Linghai; Fan, Quli; Boey, Freddy; Zhang, Hua; Huang, Wei

2010-07-27

A unique device structure with a configuration of reduced graphene oxide (rGO) /P3HT:PCBM/Al has been designed for the polymer nonvolatile memory device. The current-voltage (I-V) characteristics of the fabricated device showed the electrical bistability with a write-once-read-many-times (WORM) memory effect. The memory device exhibits a high ON/OFF ratio (10(4)-10(5)) and low switching threshold voltage (0.5-1.2 V), which are dependent on the sheet resistance of rGO electrode. Our experimental results confirm that the carrier transport mechanisms in the OFF and ON states are dominated by the thermionic emission current and ohmic current, respectively. The polarization of PCBM domains and the localized internal electrical field formed among the adjacent domains are proposed to explain the electrical transition of the memory device.

Leakage current characteristics of the multiple metal alloy nanodot memory

International Nuclear Information System (INIS)

Lee, Gae Hun; Lee, Jung Min; Yang, Hyung Jun; Song, Yun Heub; Bea, Ji Chel; Tanaka, Tetsu

2010-01-01

The leakage current characteristics of a multiple metal alloy nanodot device for a nonvolatile random access memory using FePt materials are investigated. Several annealing conditions are evaluated and optimized to suppress the leakage current and to better the memory characterisctics. This work confirmed that the annealing condition of 700 .deg. C in a high vacuum ambience (under 1 x 10 -5 Pa) simultaneously provided good cell characteristics from a high dot density of over 1 x 10 13 /cm 2 and a low leakage current. In addition, a smaller nanodot diameter was found to give a lower leakage current for the multiple nanodot memory. Finally, for the proposed annealing condition, the quadruple FePt multiple nanodot memory with a 2-nm dot diameter provided good leakage current characteristics, showing a threshold voltage shift of under 5% at an initial retention stage of 1000 sec.

A graphene integrated highly transparent resistive switching memory device

Science.gov (United States)

Dugu, Sita; Pavunny, Shojan P.; Limbu, Tej B.; Weiner, Brad R.; Morell, Gerardo; Katiyar, Ram S.

2018-05-01

We demonstrate the hybrid fabrication process of a graphene integrated highly transparent resistive random-access memory (TRRAM) device. The indium tin oxide (ITO)/Al2O3/graphene nonvolatile memory device possesses a high transmittance of >82% in the visible region (370-700 nm) and exhibits stable and non-symmetrical bipolar switching characteristics with considerably low set and reset voltages (ITO/Al2O3/Pt device and studied its switching characteristics for comparison and a better understanding of the ITO/Al2O3/graphene device characteristics. The conduction mechanisms in high and low resistance states were analyzed, and the observed polarity dependent resistive switching is explained based on electro-migration of oxygen ions.

Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

KAUST Repository

Ghoneim, Mohamed T.; Zidan, Mohammed A.; Al-Nassar, Mohammed Y.; Hanna, Amir; Kosel, Jü rgen; Salama, Khaled N.; Hussain, Muhammad Mustafa

2015-01-01

A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational

Terrestrial neutron-induced soft errors in advanced memory devices

CERN Document Server

Nakamura, Takashi; Ibe, Eishi; Yahagi, Yasuo; Kameyama, Hideaki

2008-01-01

Terrestrial neutron-induced soft errors in semiconductor memory devices are currently a major concern in reliability issues. Understanding the mechanism and quantifying soft-error rates are primarily crucial for the design and quality assurance of semiconductor memory devices. This book covers the relevant up-to-date topics in terrestrial neutron-induced soft errors, and aims to provide succinct knowledge on neutron-induced soft errors to the readers by presenting several valuable and unique features. Sample Chapter(s). Chapter 1: Introduction (238 KB). Table A.30 mentioned in Appendix A.6 on

Organic electronic memory based on a ferroelectric polymer

Energy Technology Data Exchange (ETDEWEB)

Kalbitz, R; Fruebing, P; Gerhard, R [Department of Physics and Astronomy, University of Potsdam, Karl-Liebknecht Str., 24-25, 14476 Potsdam (Germany); Taylor, D M, E-mail: d.m.taylor@bangor.ac.uk [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom)

2011-06-23

Measurements of the capacitance of metal-insulator-semiconductor capacitors and the output characteristics of thin film transistors based on poly(3-hexylthiophene) as the active semiconductor and poly(vinylidenefluoride-trifluoroethylene) as the gate insulator show that ferroelectric polarisation in the insulator is stable but that its effect when poled by depletion voltages is partially neutralised by trapping of electrons at or near the semiconductor interface. Nevertheless, the combination of materials is capable of providing an adequate memory function.

Forced Ion Migration for Chalcogenide Phase Change Memory Device

Science.gov (United States)

Campbell, Kristy A (Inventor)

2013-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Nanocrystals manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications

Energy Technology Data Exchange (ETDEWEB)

Normand, P. E-mail: p.normand@imel.demokritos.gr; Kapetanakis, E.; Dimitrakis, P.; Skarlatos, D.; Beltsios, K.; Tsoukalas, D.; Bonafos, C.; Ben Assayag, G.; Cherkashin, N.; Claverie, A.; Berg, J.A. van den; Soncini, V.; Agarwal, A.; Ameen, M.; Perego, M.; Fanciulli, M

2004-02-01

An overview of recent developments regarding the fabrication and structure of thin silicon dioxide films with embedded nanocrystals through ultra-low-energy ion-beam-synthesis (ULE-IBS) is presented. Advances in fabrication, increased understanding of structure formation processes and ways to control them allow for the fabrication of reproducible and attractive silicon-nanocrystal memory devices for a wide-range of memory applications as herein demonstrated in the case of low-voltage EEPROM-like applications.

Nanocrystals manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications

International Nuclear Information System (INIS)

Normand, P.; Kapetanakis, E.; Dimitrakis, P.; Skarlatos, D.; Beltsios, K.; Tsoukalas, D.; Bonafos, C.; Ben Assayag, G.; Cherkashin, N.; Claverie, A.; Berg, J.A. van den; Soncini, V.; Agarwal, A.; Ameen, M.; Perego, M.; Fanciulli, M.

2004-01-01

An overview of recent developments regarding the fabrication and structure of thin silicon dioxide films with embedded nanocrystals through ultra-low-energy ion-beam-synthesis (ULE-IBS) is presented. Advances in fabrication, increased understanding of structure formation processes and ways to control them allow for the fabrication of reproducible and attractive silicon-nanocrystal memory devices for a wide-range of memory applications as herein demonstrated in the case of low-voltage EEPROM-like applications

Apparatus and methods for memory using in-plane polarization

Science.gov (United States)

Liu, Junwei; Chang, Kai; Ji, Shuai-Hua; Chen, Xi; Fu, Liang

2018-05-01

A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process is non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.

Giant enhancement in the ferroelectric field effect using a polarization gradient

Energy Technology Data Exchange (ETDEWEB)

Gu, Zongquan [Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104 (United States); Islam, Mohammad A. [Department of Materials Science and Engineering, Drexel University, Philadelphia, Pennsylvania 19104 (United States); Department of Physics, State University of New York at Oswego, Oswego, New York 13126 (United States); Spanier, Jonathan E., E-mail: spanier@drexel.edu [Department of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104 (United States); Department of Materials Science and Engineering, Drexel University, Philadelphia, Pennsylvania 19104 (United States); Department of Physics, Drexel University, Philadelphia, Pennsylvania 19104 (United States)

2015-10-19

Coupling of switchable ferroelectric polarization with the carrier transport in an adjacent semiconductor enables a robust, non-volatile manipulation of the conductance in a host of low-dimensional systems, including the two-dimensional electron liquid that forms at the LaAlO{sub 3} (LAO)-SrTiO{sub 3} (STO) interface. However, strength of the gate-channel coupling is relatively weak, limited in part by the electrostatic potential difference across a ferroelectric gate. Here, through application of phenomenological Landau-Ginzburg-Devonshire theory and self-consistent Poisson-Schrödinger model calculations, we show how compositional grading of PbZr{sub 1−x}Ti{sub x}O{sub 3} ferroelectric gates enables a more than twenty-five-fold increase in the LAO/STO channel conductance on/off ratios. Incorporation of polarization gradients in ferroelectric gates can enable breakthrough performance of ferroelectric non-volatile memories.

A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

Directory of Open Access Journals (Sweden)

Tharun Konduru

2015-01-01

Full Text Available A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone, acetonitrile (nitrile, ethyl acetate (ester, and ethanol (alcohol. The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm of methlypropyl sulfide and two concentrations (145 and 1452 ppm of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

Recent progress in tungsten oxides based memristors and their neuromorphological applications

Science.gov (United States)

Qu, Bo; Younis, Adnan; Chu, Dewei

2016-09-01

The advance in conventional silicon based semiconductor industry is now becoming indeterminacy as it still along the road of Moore's Law and concomitant problems associated with it are the emergence of a number of practical issues such as short channel effect. In terms of memory applications, it is generally believed that transistors based memory devices will approach to their scaling limits up to 2018. Therefore, one of the most prominent challenges today in semiconductor industry is the need of a new memory technology which is able to combine the best characterises of current devices. The resistive switching memories which are regarded as "memristors" thus gain great attentions thanks to their specific nonlinear electrical properties. More importantly, their behaviour resembles with the transmission characteristic of synapse in biology. Therefore, the research of synapses biomimetic devices based on memristor will certainly bring a great research prospect in studying synapse emulation as well as building artificial neural networks. Tungsten oxides (WO x ) exhibits many essential characteristics as a great candidate for memristive devices including: accredited endurance (over 105 cycles), stoichiometric flexibility, complimentary metal-oxide-semiconductor (CMOS) process compatibility and configurable properties including non-volatile rectification, memorization and learning functions. Herein, recent progress on Tungsten oxide based materials and its associating memory devices had been reviewed. The possible implementation of this material as a bio-inspired artificial synapse is also highlighted. The penultimate section summaries the current research progress for tungsten oxide based biological synapses and end up with several proposals that have been suggested for possible future developments.

Flexible and twistable non-volatile memory cell array with all-organic one diode-one resistor architecture.

Science.gov (United States)

Ji, Yongsung; Zeigler, David F; Lee, Dong Su; Choi, Hyejung; Jen, Alex K-Y; Ko, Heung Cho; Kim, Tae-Wook

2013-01-01

Flexible organic memory devices are one of the integral components for future flexible organic electronics. However, high-density all-organic memory cell arrays on malleable substrates without cross-talk have not been demonstrated because of difficulties in their fabrication and relatively poor performances to date. Here we demonstrate the first flexible all-organic 64-bit memory cell array possessing one diode-one resistor architectures. Our all-organic one diode-one resistor cell exhibits excellent rewritable switching characteristics, even during and after harsh physical stresses. The write-read-erase-read output sequence of the cells perfectly correspond to the external pulse signal regardless of substrate deformation. The one diode-one resistor cell array is clearly addressed at the specified cells and encoded letters based on the standard ASCII character code. Our study on integrated organic memory cell arrays suggests that the all-organic one diode-one resistor cell architecture is suitable for high-density flexible organic memory applications in the future.

Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

International Nuclear Information System (INIS)

Tang Zhen-Jie; Li Rong; Yin Jiang

2013-01-01

A composition-modulated (HfO 2 ) x (Al 2 O3) 1−x charge trapping layer is proposed for charge trap flash memory by controlling the Al atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated (HfO 2 ) x (Al 2 O 3 ) 1−x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode

Science.gov (United States)

Seung, Hyun-Min; Kwon, Kyoung-Cheol; Lee, Gon-Sub; Park, Jea-Gun

2014-10-01

Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 105 s with a memory margin of 9.2 × 105, program/erase endurance cycles of >102 with a memory margin of 8.4 × 105, and bending-fatigue-free cycles of ˜1 × 103 with a memory margin (Ion/Ioff) of 3.3 × 105.

Semiconductor ring lasers coupled by a single waveguide

Science.gov (United States)

Coomans, W.; Gelens, L.; Van der Sande, G.; Mezosi, G.; Sorel, M.; Danckaert, J.; Verschaffelt, G.

2012-06-01

We experimentally and theoretically study the characteristics of semiconductor ring lasers bidirectionally coupled by a single bus waveguide. This configuration has, e.g., been suggested for use as an optical memory and as an optical neural network motif. The main results are that the coupling can destabilize the state in which both rings lase in the same direction, and it brings to life a state with equal powers at both outputs. These are both undesirable for optical memory operation. Although the coupling between the rings is bidirectional, the destabilization occurs due to behavior similar to an optically injected laser system.

Scientific developments of liquid crystal-based optical memory: a review

Science.gov (United States)

Prakash, Jai; Chandran, Achu; Biradar, Ashok M.

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Semiconductor

International Nuclear Information System (INIS)

2000-01-01

This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

KAUST Repository

Caraveo-Frescas, Jesus Alfonso; Khan, M. A.; Alshareef, Husam N.

2014-01-01

Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm 2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

KAUST Repository

Caraveo-Frescas, Jesus Alfonso

2014-06-10

Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm 2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

Science.gov (United States)

Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

2017-11-01

A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

Supercritical fluid extraction of volatile and non-volatile compounds from Schinus molle L.

Directory of Open Access Journals (Sweden)

M. S. T. Barroso

2011-06-01

Full Text Available Schinus molle L., also known as pepper tree, has been reported to have antimicrobial, antifungal, anti-inflammatory, antispasmodic, antipyretic, antitumoural and cicatrizing properties. This work studies supercritical fluid extraction (SFE to obtain volatile and non-volatile compounds from the aerial parts of Schinus molle L. and the influence of the process on the composition of the extracts. Experiments were performed in a pilot-scale extractor with a capacity of 1 L at pressures of 9, 10, 12, 15 and 20 MPa at 323.15 K. The volatile compounds were obtained by CO2 supercritical extraction with moderate pressure (9 MPa, whereas the non-volatile compounds were extracted at higher pressure (12 to 20 MPa. The analysis of the essential oil was carried out by GC-MS and the main compounds identified were sabinene, limonene, D-germacrene, bicyclogermacrene, and spathulenol. For the non-volatile extracts, the total phenolic content was determined by the Folin-Ciocalteau method. Moreover, one of the goals of this study was to compare the experimental data with the simulated yields predicted by a mathematical model based on mass transfer. The model used requires three adjustable parameters to predict the experimental extraction yield curves.

Fatigue-free lead zirconate titanate-based capacitors for nonvolatile memories

International Nuclear Information System (INIS)

Shannigrahi, S. R.; Jang, Hyun M.

2001-01-01

The development of lead zirconate titanate (PZT)-based capacitors has been a long time goal of ferroelectric random access memories (FRAM). However, PZT-based perovskites with common platinum (Pt) electrodes have suffered from a significant reduction of the remanent polarization (P r ) after a certain number of read/write cycles (electrical fatigue). We now report the development of fatigue-free lanthanum-modified PZT capacitors using common Pt electrodes. The capacitors fabricated at 580 o C by applying a PZT seed layer exhibited fatigue-free behavior up to 6.5 x 10 10 switching cycles, a quite stable charge retention profile with time, and comparatively high P r values, all of which assure their suitability for practical FRAM applications. Copyright 2001 American Institute of Physics

Transparent Memory For Harsh Electronics

KAUST Repository

Ho, C. H.

2017-03-14

As a new class of non-volatile memory, resistive random access memory (RRAM) offers not only superior electronic characteristics, but also advanced functionalities, such as transparency and radiation hardness. However, the environmental tolerance of RRAM is material-dependent, and therefore the materials used must be chosen carefully in order to avoid instabilities and performance degradation caused by the detrimental effects arising from environmental gases and ionizing radiation. In this work, we demonstrate that AlN-based RRAM displays excellent performance and environmental stability, with no significant degradation to the resistance ratio over a 100-cycle endurance test. Moreover, transparent RRAM (TRRAM) based on AlN also performs reliably under four different harsh environmental conditions and 2 MeV proton irradiation fluences, ranging from 1011 to 1015 cm-2. These findings not only provide a guideline for TRRAM design, but also demonstrate the promising applicability of AlN TRRAM for future transparent harsh electronics.

Radioactive resistance of memory elements

International Nuclear Information System (INIS)

Loncar, B.; Stankovic, S.; Novakovic, D.; Osmokrovic, P.

1998-01-01

In this paper, the results of semiconductor memories radioactive resistance examination (EPROM and EEPROM) are presented. Performance of semiconductor memories is most important, when working under high risk condition where there is an influence of radiation. This research is particularly interesting for specific applications in military industry and space technology. Therefore, the analysis of the degradation mechanism of these components as well as the possibilities to increase their radiation resistivity have been considered by many authors. The aim of this work is the examination of the reliability of EPROM and EEPROM characteristics under radiation. Total dose results are presented for the JL 27C512D EPROM and ST 24C02 EEPROM. There is evidence that EPROM are more sensitive to y radiation than EEPROM. The results obtained are analyzed theoretically via the interaction of gamma radiation with oxide layer. (authors)

Facile fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) nanodot arrays for organic ferroelectric memory

International Nuclear Information System (INIS)

Fang, Huajing; Yan, Qingfeng; Geng, Chong; Li, Qiang; Chan, Ngai Yui; Au, Kit; Ng, Sheung Mei; Leung, Chi Wah; Wa Chan, Helen Lai; Dai, Jiyan; Yao, Jianjun; Guo, Dong

2016-01-01

Nano-patterned ferroelectric materials have attracted significant attention as the presence of two or more thermodynamically equivalent switchable polarization states can be employed in many applications such as non-volatile memory. In this work, a simple and effective approach for fabrication of highly ordered poly(vinylidene fluoride–trifluoroethylene) P(VDF-TrFE) nanodot arrays is demonstrated. By using a soft polydimethylsiloxane mold, we successfully transferred the 2D array pattern from the initial monolayer of colloidal polystyrene nanospheres to the imprinted P(VDF-TrFE) films via nanoimprinting. The existence of a preferred orientation of the copolymer chain after nanoimprinting was confirmed by Fourier transform infrared spectra. Local polarization switching behavior was measured by piezoresponse force microscopy, and each nanodot showed well-formed hysteresis curve and butterfly loop with a coercive field of ∼62.5 MV/m. To illustrate the potential application of these ordered P(VDF-TrFE) nanodot arrays, the writing and reading process as non-volatile memory was demonstrated at a relatively low voltage. As such, our results offer a facile and promising route to produce arrays of ferroelectric polymer nanodots with improved piezoelectric functionality

Facile fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) nanodot arrays for organic ferroelectric memory

Energy Technology Data Exchange (ETDEWEB)

Fang, Huajing [Department of Applied Physics, The Hong Kong Polytechnic University (PolyU) Hunghom, Kowloon (Hong Kong); Department of Chemistry, Tsinghua University, Beijing 100084 (China); Yan, Qingfeng, E-mail: yanqf@mail.tsinghua.edu.cn, E-mail: jiyan.dai@polyu.edu.hk; Geng, Chong; Li, Qiang [Department of Chemistry, Tsinghua University, Beijing 100084 (China); Chan, Ngai Yui; Au, Kit; Ng, Sheung Mei; Leung, Chi Wah; Wa Chan, Helen Lai; Dai, Jiyan, E-mail: yanqf@mail.tsinghua.edu.cn, E-mail: jiyan.dai@polyu.edu.hk [Department of Applied Physics, The Hong Kong Polytechnic University (PolyU) Hunghom, Kowloon (Hong Kong); Yao, Jianjun [Asylum Research, Oxford Instruments, Shanghai 200233 (China); Guo, Dong [Institute of Acoustics, Chinese Academy of Sciences, Beijing 100190 (China)

2016-01-07

Nano-patterned ferroelectric materials have attracted significant attention as the presence of two or more thermodynamically equivalent switchable polarization states can be employed in many applications such as non-volatile memory. In this work, a simple and effective approach for fabrication of highly ordered poly(vinylidene fluoride–trifluoroethylene) P(VDF-TrFE) nanodot arrays is demonstrated. By using a soft polydimethylsiloxane mold, we successfully transferred the 2D array pattern from the initial monolayer of colloidal polystyrene nanospheres to the imprinted P(VDF-TrFE) films via nanoimprinting. The existence of a preferred orientation of the copolymer chain after nanoimprinting was confirmed by Fourier transform infrared spectra. Local polarization switching behavior was measured by piezoresponse force microscopy, and each nanodot showed well-formed hysteresis curve and butterfly loop with a coercive field of ∼62.5 MV/m. To illustrate the potential application of these ordered P(VDF-TrFE) nanodot arrays, the writing and reading process as non-volatile memory was demonstrated at a relatively low voltage. As such, our results offer a facile and promising route to produce arrays of ferroelectric polymer nanodots with improved piezoelectric functionality.

Facile fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) nanodot arrays for organic ferroelectric memory

Science.gov (United States)

Fang, Huajing; Yan, Qingfeng; Geng, Chong; Chan, Ngai Yui; Au, Kit; Yao, Jianjun; Ng, Sheung Mei; Leung, Chi Wah; Li, Qiang; Guo, Dong; Wa Chan, Helen Lai; Dai, Jiyan

2016-01-01

Nano-patterned ferroelectric materials have attracted significant attention as the presence of two or more thermodynamically equivalent switchable polarization states can be employed in many applications such as non-volatile memory. In this work, a simple and effective approach for fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) P(VDF-TrFE) nanodot arrays is demonstrated. By using a soft polydimethylsiloxane mold, we successfully transferred the 2D array pattern from the initial monolayer of colloidal polystyrene nanospheres to the imprinted P(VDF-TrFE) films via nanoimprinting. The existence of a preferred orientation of the copolymer chain after nanoimprinting was confirmed by Fourier transform infrared spectra. Local polarization switching behavior was measured by piezoresponse force microscopy, and each nanodot showed well-formed hysteresis curve and butterfly loop with a coercive field of ˜62.5 MV/m. To illustrate the potential application of these ordered P(VDF-TrFE) nanodot arrays, the writing and reading process as non-volatile memory was demonstrated at a relatively low voltage. As such, our results offer a facile and promising route to produce arrays of ferroelectric polymer nanodots with improved piezoelectric functionality.

Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs

CERN Document Server

Cerjan, C J

2000-01-01

The research undertaken in this LDRD-funded project addressed the joint development of magnetic material-based nonvolatile, radiation-hard memory cells with Sandia National Laboratory. Specifically, the goal of this project was to demonstrate the intrinsic radiation-hardness of Giant Magneto-Resistive (GMR) materials by depositing representative alloy combinations upon radiation-hardened silicon-based integrated circuits. All of the stated goals of the project were achieved successfully. The necessary films were successfully deposited upon typical integrated circuits; the materials retained their magnetic field response at the highest radiation doses; and a patterning approach was developed that did not degrade the as-fabricated properties of the underlying circuitry. These results establish the feasibility of building radiation-hard magnetic memory cells.

A review of the semiconductor storage of television signals. Part 2: Applications 1975-1986

Science.gov (United States)

Riley, J. L.

1987-08-01

This is the second of two reports. In the first, the emerging semiconductor memory technology over the last two decades and some of the important operational characteristics of each ensuing generation of device are described together with the design philosophy for forming the devices into useful tools for the storage of television signals. The second of these reports describes some of the applications. These include improved television synchronizers, high quality PAL decoders, television noise reducers, film dirt concealment equipment and buffer storage for television picture processing equipment such as stills stores. The continuing developments in the technology promise still further increases of memory capacity and there is a proposal to build a mass semiconductor television picture sequence store, initially as a research tool.

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

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Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

2018-05-01

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

Fault-tolerant NAND-flash memory module for next-generation scientific instruments

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Lange, Tobias; Michel, Holger; Fiethe, Björn; Michalik, Harald; Walter, Dietmar

2015-10-01

Remote sensing instruments on today's space missions deliver a high amount of data which is typically evaluated on ground. Especially for deep space missions the telemetry downlink is very limited which creates the need for the scientific evaluation and thereby a reduction of data volume already on-board the spacecraft. A demanding example is the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter. To enable on-board offline processing for data reduction, the instrument has to be equipped with a high capacity memory module. The module is based on non-volatile NAND-Flash technology, which requires more advanced operation than volatile DRAM. Unlike classical mass memories, the module is integrated into the instrument and allows readback of data for processing. The architecture and safe operation of such kind of memory module is described in the following paper.

Light programmable organic transistor memory device based on hybrid dielectric

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Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Resistive Switching Characteristics in Electrochemically Synthesized ZnO Films

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Shuhan Jing

2015-04-01

Full Text Available The semiconductor industry has long been seeking a new kind of non-volatile memory technology with high-density, high-speed, and low-power consumption. This study demonstrated the electrochemical synthesis of ZnO films without adding any soft or hard templates. The effect of deposition temperatures on crystal structure, surface morphology and resistive switching characteristics were investigated. Our findings reveal that the crystallinity, surface morphology and resistive switching characteristics of ZnO thin films can be well tuned by controlling deposition temperature. A conducting filament based model is proposed to explain the switching mechanism in ZnO thin films.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications.

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Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-04-09

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 10 6 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

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Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.