Degradation Mechanisms for GaN and GaAs High Speed Transistors

Directory of Open Access Journals (Sweden)

Fan Ren

2012-11-01

Full Text Available We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs as well as Heterojunction Bipolar Transistors (HBTs in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate, and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

Science.gov (United States)

Cheney, David J.; Douglas, Erica A.; Liu, Lu; Lo, Chien-Fong; Gila, Brent P.; Ren, Fan; Pearton, Stephen J.

2012-01-01

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

Science.gov (United States)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

Optimization of ultra-low-power CMOS transistors

International Nuclear Information System (INIS)

Stockinger, M.

2000-01-01

Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

Gaining Insight Into Femtosecond-scale CMOS Effects using FPGAs

Science.gov (United States)

2015-03-24

current . PMOS devices degrade under negative bias (NBTI) and NMOS under positive bias (PBTI). In some cases partial recovery occurs when stress...statically biased; we hypothesize that these transistors might act as ― canaries ‖ for subtle degradation of the BTI type. Characterizing their switching...drain current depends on the threshold voltage [6], approximated by ( ) (1) Therefore, a measured increase in delay can be

NMOS contact resistance reduction with selenium implant into NiPt silicide

Science.gov (United States)

Rao, K. V.; Khaja, F. A.; Ni, C. N.; Muthukrishnan, S.; Darlark, A.; Lei, J.; Peidous, I.; Brand, A.; Henry, T.; Variam, N.; Erokhin, Y.

2012-11-01

A 25% reduction in NMOS contact resistance (Rc) was achieved by Selenium implantation into NiPt silicide film in VIISta Trident high-current single-wafer implanter. The Trident implanter is designed for shallow high-dose implants with high beam currents to maintain high throughput (for low CoO), with improved micro-uniformity and no energy contamination. The integration of Se implant was realized using a test chip dedicated to investigating silicide/junction related electrical properties and testable after silicidation. The silicide module processes were optimized, including the pre-clean (prior to RF PVD NiPt dep) and pre- and post-implant anneals. A 270°C soak anneal was used for RTP1, whereas a msec laser anneal was employed for RTP2 with sufficient process window (800-850°C), while maintaining excellent junction characteristics without Rs degradation.

Charge based DC compact modeling of bulk FinFET transistor

Science.gov (United States)

Cerdeira, A.; Garduño, I.; Tinoco, J.; Ritzenthaler, R.; Franco, J.; Togo, M.; Chiarella, T.; Claeys, C.

2013-09-01

Multiple-gate MOSFETs became an industrial reality in the last years. Due to a pragmatic trade-off between CMOS process baselines compatibility, improved performance compared to planar bulk architecture, and cost, bulk FinFETs emerged as the technological solution to provide downscaling for the 14/22 nm technological nodes. In this work, a charge based DC compact model based on the SDDG Model is demonstrated for this new generation of FinFET transistors and describes continuously the transistor characteristics in all operating regions. Validating the model against two bulk FinFET baselines (NMOS, PMOS, various gate lengths and EOT), an excellent agreement is found for transfer and output characteristics (linear and saturation regimes), transconductance/output conductance, and gm/IDS characteristics. Temperature dependence is also taken into account and validated (T range from 25 °C up to 175 °C).

Accelerating the life of transistors

International Nuclear Information System (INIS)

Qi Haochun; Lü Changzhi; Zhang Xiaoling; Xie Xuesong

2013-01-01

Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object, the test of accelerating life is conducted in constant temperature and humidity, and then the data are statistically analyzed with software developed by ourselves. According to degradations of such sensitive parameters as the reverse leakage current of transistors, the lifetime order of transistors is about more than 10 4 at 100 °C and 100% relative humidity (RH) conditions. By corrosion fracture of transistor outer leads and other failure modes, with the failure truncated testing, the average lifetime rank of transistors in different distributions is extrapolated about 10 3 . Failure mechanism analyses of degradation of electrical parameters, outer lead fracture and other reasons that affect transistor lifetime are conducted. The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation. (semiconductor devices)

Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

International Nuclear Information System (INIS)

Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Hsieh, Tien-Yu; Lin, Kun-Yao; Wu, Yi-Chun; Huang, Shih-Feng; Chiang, Cheng-Lung; Chen, Po-Lin; Lai, Tzu-Chieh; Lo, Chang-Cheng; Lien, Alan

2014-01-01

This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device. - Highlights: • There is abnormal V T shift induced by illuminated gate bias stress in a-Si:H thin film transistors. • Electron–hole pair is generated via trap-assisted photoexcitation. • Abnormal transconductance hump is induced by the leakage current from back channel. • Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate

The design of a new spiking neuron using dual work function silicon nanowire transistors

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2007-01-01

A new spike neuron cell is designed using vertically grown, undoped silicon nanowire transistors. This study presents an entire design cycle from designing and optimizing vertical nanowire transistors for minimal power dissipation to realizing a neuron cell and measuring its dynamic power consumption, performance and layout area. The design cycle starts with determining individual metal gate work functions for NMOS and PMOS transistors as a function of wire radius to produce a 300 mV threshold voltage. The wire radius and effective channel length are subsequently varied to find a common body geometry for both transistors that yields smaller than 1 pA OFF current while producing maximum drive currents. A spike neuron cell is subsequently built using these transistors to measure its transient performance, power dissipation and layout area. Post-layout simulation results indicate that the neuron consumes 0.397 μW to generate a +1 V and 1.12 μW to generate a -1 V output pulse for a fan-out of five synapses at 500 MHz; the power dissipation increases by approximately 3 nW for each additional synapse at the output for generating either pulse. The neuron circuit occupies approximately 0.27 μm 2

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

Science.gov (United States)

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Use of commercial VDMOSFETS in an electronic system subjected to radiation; Utilisation des VDMOSFETs commerciaux dans un systeme electronique soumis aux radiations

Energy Technology Data Exchange (ETDEWEB)

Picard, C.; Brisset, C.; Quittard, O.; Marceau, M.; Joffre, F. [CEA Saclay, Lab. d' Electronique et de Technologie de l' Informatique, LETI, 91 - Gif-sur-Yvette (France); Hoffmann, A.; Charles, J.P. [centre Lorrain d' Optique et Electronique des Solides, Supelec, 57 - Metz (France)

1999-07-01

This study explores the usefulness of pre-irradiation as a hardening technique for NMOS transistors. NMOS transistors have been exposed to Co-60 gamma radiation with a dose-rate of 10 krad(SiO{sub 2})/h. The pre-irradiation technique is based on 2 phenomena occurring when the polarization is negative or equals to 0: the weak shift and the saturation of the threshold voltage.

A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

CSIR Research Space (South Africa)

Reddy, Reeshen

2015-04-01

Full Text Available the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion...

Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

OpenAIRE

Amoroso, Salvatore Maria; Georgiev, Vihar P.; Gerrer, Louis; Towie, Ewan; Wang, Xingsheng; Riddet, Craig; Brown, Andrew Robert; Asenov, Asen

2014-01-01

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-dif...

Alpha particle induced soft errors in NMOS RAMs: a review

International Nuclear Information System (INIS)

Carter, P.M.; Wilkins, B.R.

1987-01-01

The paper aims to explain the alpha particle induced soft error phenomenon using the NMOS dynamic random access memory (RAM) as a model. It discusses some of the many techniques experimented with by manufacturers to overcome the problem, and gives a review of the literature covering most aspects of soft errors in dynamic RAMs. Finally, the soft error performance of current dynamic RAM and static RAM products from several manufacturers are compared. (author)

Design of a High Linearity Four-Quadrant Analog Multiplier in Wideband Frequency Range

Directory of Open Access Journals (Sweden)

Abdul kareem Mokif Obais

2017-05-01

Full Text Available In this paper, a voltage mode four quadrant analog multiplier in the wideband frequency rangeis designed using a wideband operational amplifier (OPAMP and squaring circuits. The wideband OPAMP is designed using 10 identical NMOS transistorsand operated with supply voltages of ±12V. Two NMOS transistors and two wideband OPAMP are utilized in the design of the proposed squaring circuit. All the NMOS transistors are based on 0.35µm NMOStechnology. The multiplier has input and output voltage ranges of ±10 V, high range of linearity from -10 V to +10 V, and cutoff frequency of about 5 GHz. The proposed multiplier is designed on PSpice in Orcad 16.6

A 32-bit NMOS microprocessor with a large register file

Science.gov (United States)

Sherburne, R. W., Jr.; Katevenis, M. G. H.; Patterson, D. A.; Sequin, C. H.

1984-10-01

Two scaled versions of a 32-bit NMOS reduced instruction set computer CPU, called RISC II, have been implemented on two different processing lines using the simple Mead and Conway layout rules with lambda values of 2 and 1.5 microns (corresponding to drawn gate lengths of 4 and 3 microns), respectively. The design utilizes a small set of simple instructions in conjunction with a large register file in order to provide high performance. This approach has resulted in two surprisingly powerful single-chip processors.

Electron density window for best frequency performance, lowest phase noise and slowest degradation of GaN heterostructure field-effect transistors

International Nuclear Information System (INIS)

Matulionis, Arvydas

2013-01-01

The problems in the realm of nitride heterostructure field-effect transistors (HFETs) are discussed in terms of a novel fluctuation–dissipation-based approach impelled by a recent demonstration of strong correlation of hot-electron fluctuations with frequency performance and degradation of the devices. The correlation has its genesis in the dissipation of the LO-mode heat accumulated by the non-equilibrium longitudinal optical phonons (hot phonons) confined in the channel that hosts the high-density hot-electron gas subjected to a high electric field. The LO-mode heat causes additional scattering of hot electrons and facilitates defect formation in a different manner than the conventional heat contained mainly in the acoustic phonon mode. We treat the heat dissipation problem in terms of the hot-phonon lifetime responsible for the conversion of the non-migrant hot phonons into migrant acoustic modes and other vibrations. The lifetime is measured over a wide range of electron density and supplied electric power. The optimal conditions for the dissipation of the LO-mode heat are associated with the plasmon-assisted disintegration of hot phonons. Signatures of plasmons are experimentally resolved in fluctuations, dissipation, hot-electron transport, transistor frequency performance, transistor phase noise and transistor reliability. In particular, a slower degradation and a faster operation of GaN-based HFETs take place inside the electron density window where the resonant plasmon-assisted ultrafast dissipation of the LO-mode heat comes into play. A novel heterostructure design for the possible improvement of HFET performance is proposed, implemented and tested. (invited review)

Impact of Process Technologies on ELDRS of Bipolar Transistors

International Nuclear Information System (INIS)

Lu Wu; Ren Diyuan; Guo Qi; Yu Xuefeng; Zheng Yuzhan

2010-01-01

Radiation effects under different dose rates and annealing behaviors of domestic bipolar transistors, with same manufacture technology, were investigated.These transistors include NPN transistors of various emitter area, and LPNP transistors with different doping concentrations in emitter. It is shown that different types of transistors have different radiation responses. The results of NPN transistors show that more degradation occurs at less emitter area. Yet, the results of LPNP transistors demonstrate that transistors with lightly doped emitter are more sensitive to radiation, compared with heavily doped emitter. Finally,the mechanisms of the difference between various radiation responses were analyzed. (authors)

Recent advances in understanding total-dose effects in bipolar transistors

International Nuclear Information System (INIS)

Schrimpf, R.D.

1996-01-01

Gain degradation in irradiated bipolar transistors can be a significant problem, particularly in linear integrated circuits. In many bipolar technologies, the degradation is greater for irradiation at low dose rates than it is for typical laboratory dose rates. Ionizing radiation causes the base current in bipolar transistors to increase, due to the presence of net positive charge in the oxides covering sensitive device areas and increases in surface recombination velocity. Understanding the mechanisms responsible for radiation-induced gain degradation in bipolar transistors is important in developing appropriate hardness assurance methods. This paper reviews recent modeling and experimental work, with the emphasis on low-dose-rate effects. A promising hardness assurance method based on irradiation at elevated temperatures is described

Atomic-Layer-Deposited SnO2 as Gate Electrode for Indium-Free Transparent Electronics

KAUST Repository

Alshammari, Fwzah Hamud

2017-08-04

Atomic-layer-deposited SnO2 is used as a gate electrode to replace indium tin oxide (ITO) in thin-film transistors and circuits for the first time. The SnO2 films deposited at 200 °C show low electrical resistivity of ≈3.1 × 10−3 Ω cm with ≈93% transparency in most of the visible range of the electromagnetic spectrum. Thin-film transistors fabricated with SnO2 gates show excellent transistor properties including saturation mobility of 15.3 cm2 V−1 s−1, a low subthreshold swing of ≈130 mV dec−1, a high on/off ratio of ≈109, and an excellent electrical stability under constant-voltage stressing conditions to the gate terminal. Moreover, the SnO2-gated thin-film transistors show excellent electrical characteristics when used in electronic circuits such as negative channel metal oxide semiconductor (NMOS) inverters and ring oscillators. The NMOS inverters exhibit a low propagation stage delay of ≈150 ns with high DC voltage gain of ≈382. A high oscillation frequency of ≈303 kHz is obtained from the output sinusoidal signal of the 11-stage NMOS inverter-based ring oscillators. These results show that SnO2 can effectively replace ITO in transparent electronics and sensor applications.

Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

CERN Document Server

Snoeys, W; Burns, M; Campbell, M; Cantatore, E; Carrer, N; Casagrande, L; Cavagnoli, A; Dachs, C; Di Liberto, S; Formenti, F; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Letheren, M F; Marchioro, A; Martinengo, P; Meddi, F; Mikulec, B; Morando, M; Morel, M; Noah, E; Paccagnella, A; Ropotar, I; Saladino, S; Sansen, Willy; Santopietro, F; Scarlassara, F; Segato, G F; Signe, P M; Soramel, F; Vannucci, Luigi; Vleugels, K

2000-01-01

A new pixel readout prototype has been developed at CERN for high- energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 mu m CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad-1.7 Mrad depending on the type of radiation. 10 keV X-rays, /sup 60/Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed. (20 refs).

Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study

Energy Technology Data Exchange (ETDEWEB)

Lu, Anh Khoa Augustin [Semiconductor Physics Laboratory, Department of Physics and Astronomy, University of Leuven, Celestijnenlaan 200 D, B-3001 Leuven (Belgium); IMEC, 75 Kapeldreef, B-3001 Leuven (Belgium); Pourtois, Geoffrey [IMEC, 75 Kapeldreef, B-3001 Leuven (Belgium); Department of Chemistry, Plasmant Research Group, University of Antwerp, B-2610 Wilrijk-Antwerp (Belgium); Agarwal, Tarun [IMEC, 75 Kapeldreef, B-3001 Leuven (Belgium); Department of Electrical Engineering, University of Leuven, Kasteelpark Arenberg 10, B-3001 Leuven (Belgium); Afzalian, Aryan [TSMC, Kapeldreef 75, B-3001 Leuven (Belgium); Radu, Iuliana P. [IMEC, 75 Kapeldreef, B-3001 Leuven (Belgium); Houssa, Michel [Semiconductor Physics Laboratory, Department of Physics and Astronomy, University of Leuven, Celestijnenlaan 200 D, B-3001 Leuven (Belgium)

2016-01-25

The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10 nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs.

Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study

International Nuclear Information System (INIS)

Lu, Anh Khoa Augustin; Pourtois, Geoffrey; Agarwal, Tarun; Afzalian, Aryan; Radu, Iuliana P.; Houssa, Michel

2016-01-01

The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10 nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs

Low Power Consumption Complementary Inverters with n-MoS2 and p-WSe2 Dichalcogenide Nanosheets on Glass for Logic and Light-Emitting Diode Circuits.

Science.gov (United States)

Jeon, Pyo Jin; Kim, Jin Sung; Lim, June Yeong; Cho, Youngsuk; Pezeshki, Atiye; Lee, Hee Sung; Yu, Sanghyuck; Min, Sung-Wook; Im, Seongil

2015-10-14

Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications.

Origin of degradation phenomenon under drain bias stress for oxide thin film transistors using IGZO and IGO channel layers.

Science.gov (United States)

Bak, Jun Yong; Kang, Youngho; Yang, Shinhyuk; Ryu, Ho-Jun; Hwang, Chi-Sun; Han, Seungwu; Yoon, Sung-Min

2015-01-20

Top-gate structured thin film transistors (TFTs) using In-Ga-Zn-O (IGZO) and In-Ga-O (IGO) channel compositions were investigated to reveal a feasible origin for degradation phenomenon under drain bias stress (DBS). DBS-driven instability in terms of V(TH) shift, deviation of the SS value, and increase in the on-state current were detected only for the IGZO-TFT, in contrast to the IGO-TFT, which did not demonstrate V(TH) shift. These behaviors were visually confirmed via nanoscale transmission electron microscopy and energy-dispersive x-ray spectroscopy observations. To understand the degradation mechanism, we performed ab initio molecular dynamic simulations on the liquid phases of IGZO and IGO. The diffusivities of Ga and In atoms were enhanced in IGZO, confirming the degradation mechanism to be increased atomic diffusion.

Total dose effects on elementary transistors of a comparator in bipolar technology

International Nuclear Information System (INIS)

Sarrabayrouse, G.; Guerre, F.X.

1995-01-01

In the present work we investigate elementary transistors behaviour of an Integrated Circuit using junction isolation bipolar technology. Polarization conditions and dose rate effects on the main elementary transistor types are analysed. Furthermore, the IC electronic function degradations are studied. Finally, a comparison between the function degradations and the elementary component ones is attempted. (author)

Radiation effect of doping and bias conditions on NPN bipolar junction transistors

International Nuclear Information System (INIS)

Xi Shanbin; Wang Yiyuan; Xu Fayue; Zhou Dong; Li Ming; Wang Fei; Wang Zhikuan; Yang Yonghui; Lu Wu

2011-01-01

In this paper,we investigate 60 Co γ-ray irradiation effects and annealing behaviors of NPN bipolar junction transistors of the same manufacturing technology but different doping concentrations. The transistors of different doping concentrations differ in responses of the radiation effect. More degradation was observed with the transistors of low concentration-doped NPN transistors than the high concentration-doped NPN transistors. The results also demonstrate that reverse-biased transistors are more sensitive to radiation than the forward-biased ones. Mechanisms of the radiation responses are analyzed. (authors)

Dose enhancement effects of X ray radiation in bipolar transistors

International Nuclear Information System (INIS)

Chen Panxun

1997-01-01

The author has presented behaviour degradation and dose enhancement effects of bipolar transistors in X ray irradiation environment. The relative dose enhancement factors of X ray radiation were measured in bipolar transistors by the experiment methods. The mechanism of bipolar device dose enhancement was investigated

Neutron Radiation Effect On 2N2222 And NTE 123 NPN Silicon Bipolar Junction Transistors

International Nuclear Information System (INIS)

Oo, Myo Min; Rashid, N K A Md; Hasbullah, N F; Karim, J Abdul; Zin, M R Mohamed

2013-01-01

This paper examines neutron radiation with PTS (Pneumatic Transfer System) effect on silicon NPN bipolar junction transistors (2N2222 and NTE 123) and analysis of the transistors in terms of electrical characterization such as current gain after neutron radiation. The key parameters are measured with Keithley 4200SCS. Experiment results show that the current gain degradation of the transistors is very sensitive to neutron radiation. The neutron radiation can cause displacement damage in the bulk layer of the transistor structure. The current degradation is believed to be governed by increasing recombination current between the base and emitter depletion region

Degradation pattern of black phosphorus multilayer field-effect transistors in ambient conditions: Strategy for contact resistance engineering in BP transistors

Science.gov (United States)

Lee, Byung Chul; Kim, Chul Min; Jang, Ho-Kyun; Lee, Jae Woo; Joo, Min-Kyu; Kim, Gyu-Tae

2017-10-01

Black phosphorus (BP) has been proposed as a future optoelectronic material owing to its direct bandgap with excellent electrical performances. However, oxygen (O2) and water (H2O) molecules in an ambient condition can create undesired bubbles on the surface of the BP, resulting in hampering its excellent intrinsic properties. Here, we report the electrical degradation pattern of a mechanically exfoliated BP field-effect transistor (FET) in terms of the channel and contact, separately. Various electrical parameters such as the threshold voltage (VTH), carrier mobility (μ), contact resistance (RCT) and channel resistance (RCH) are estimated by the Y function method (YFM) with respect to time (up to 2000 min). It is found that RCT reduces and then, increases with time; whereas, the behavior of RCH is vice versa in ambient conditions. We attribute these effects to oxygen doping at the contact and the surface oxidation effects on the surface of the BP, respectively.

Origin of Degradation Phenomenon under Drain Bias Stress for Oxide Thin Film Transistors using IGZO and IGO Channel Layers

OpenAIRE

Bak, Jun Yong; Kang, Youngho; Yang, Shinhyuk; Ryu, Ho-Jun; Hwang, Chi-Sun; Han, Seungwu; Yoon, Sung-Min

2015-01-01

Top-gate structured thin film transistors (TFTs) using In-Ga-Zn-O (IGZO) and In-Ga-O (IGO) channel compositions were investigated to reveal a feasible origin for degradation phenomenon under drain bias stress (DBS). DBS-driven instability in terms of VTH shift, deviation of the SS value, and increase in the on-state current were detected only for the IGZO-TFT, in contrast to the IGO-TFT, which did not demonstrate VTH shift. These behaviors were visually confirmed via nanoscale transmission el...

Degradation and lifetime estimation of n-MOS SLS ELA polycrystalline TFTs during hot carrier stressing: effect of channel width in the region Vth ≤ VGS,stress ≤ VDS,stress/2

International Nuclear Information System (INIS)

Kontogiannopoulos, G P; Farmakis, F V; Kouvatsos, D N; Papaioannou, G J; Voutsas, A T

2009-01-01

The voltage bias stress induced degradation of sequential lateral solidification (SLS) polysilicon thin film transistors (TFTs) is studied. The aim of this work is the investigation of the types of damage arising from the electrical stressing in the gate voltage range around V th ≤ V GS,stress ≤ V DS,stress /2 and for different drain-bias voltages. It is shown that the drain on-current variation (%) with stressing time for a defined gate voltage obeys a power–time-dependent law of the form At n . The parameters A and n of this law were determined in order to gain insight on degradation mechanisms in different stress regimes and to estimate the time to failure of our devices. Devices with different channel widths were compared, and their lifetime to failure was extracted. It was found that the magnitude of stress was lower for devices with narrower channel widths. By monitoring the threshold voltage variation and the percentage change of transconductance maximum in the linear regime of operation, it was verified that the threshold voltage degradation was mainly due to the contribution of G m,max to V th rather than severe carrier trapping

Degradation of AlGaN/GaN High Electron Mobility Transistors with Different AlGaN Layer Thicknesses under Strong Electric Field

International Nuclear Information System (INIS)

Ling, Yang; Yue, Hao; Xiao-Hua, Ma; Jing-Jing, Ma; Cheng, Zhu

2010-01-01

The degradation of AlGaN/GaN high electron mobility transistors (HEMTs) has a close relationship with a model of traps in AlGaN barriers as a result of high electric field. We mainly discuss the impacts of strong electrical field on the AlGaN barrier thickness of AlGaN/GaN HEMTs. It is found that the device with a thin AlGaN barrier layer is more easily degraded. We study the degradation of four parameters, i.e. the gate series resistance R Gate , channel resistance R channel , gate current I G,off at V GS = −5 and V DS = 0.1 V, and drain current I D,max at V GS = 2 and V DS = 5 V. In addition, the degradation mechanisms of the device electrical parameters are also investigated in detail. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

MOSFET Degradation Under RF Stress

NARCIS (Netherlands)

Sasse, G.T.; Kuper, F.G.; Schmitz, Jurriaan

2008-01-01

We report on the degradation of MOS transistors under RF stress. Hot-carrier degradation, negative-bias temperature instability, and gate dielectric breakdown are investigated. The findings are compared to established voltage- and field-driven models. The experimental results indicate that the

A transient-enhanced NMOS low dropout voltage regulator with parallel feedback compensation

International Nuclear Information System (INIS)

Wang Han; Tan Lin

2016-01-01

This paper presents a transient-enhanced NMOS low-dropout regulator (LDO) for portable applications with parallel feedback compensation. The parallel feedback structure adds a dynamic zero to get an adequate phase margin with a load current variation from 0 to 1 A. A class-AB error amplifier and a fast charging/discharging unit are adopted to enhance the transient performance. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 150 mV at a maximum 1 A load and I Q of 165 μA. Under the full range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 38 mV and 27 mV respectively. (paper)

Investigations on MGy ionizing dose effects in thin oxides of micro-electronic devices

Energy Technology Data Exchange (ETDEWEB)

Gaillardin, M.; Paillet, P.; Raine, M.; Martinez, M.; Marcandella, C.; Duhamel, O.; Richard, N.; Leray, J.L. [CEA, DAM, DIF, F-91297 Arpajon (France); Goiffon, V.; Corbiere, F.; Rolando, S.; Molina, R.; Magnan, P. [ISAE, Universite de Toulouse, 10 avenue Edouard Belin, BP 54032, 31055 Toulouse Cedex 4 (France); Girard, S.; Ouerdane, Y.; Boukenter, A. [Universite de Saint-Etienne, Laboratoire H. Curien, UMR-5516, 42000, Saint-Etienne (France)

2015-07-01

Total ionizing dose (TID) effects have been studied for a long time in micro-electronic components designed to operate in natural and artificial environments. In most cases, TID induces both charge trapping in the bulk of irradiated oxides and the buildup of interface traps located at semiconductor/dielectric interfaces. Such effects result from basic mechanisms driven by both the shape of the electric field which stands into the oxide and by fabrication process parameters inducing pre-existing traps in the oxide's bulk. From the pioneering studies based on 'thick' oxide technologies to the most recent ones dedicated to innovative technologies, most studies concluded that the impact of total ionizing dose effects reduces with the oxide thinning. This is specifically the case for the gate-oxide of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) for which it is generally considered that TID is not a major issue anymore at kGy dose ranges. TID effects are now mainly due to charge trapping in the field oxides such as Shallow Trench Isolation. This creates either parasitic conduction paths or Radiation-Induced Narrow Channel Effects (RINCE). Static current-voltage (I-V) electrical characteristics are then modified through a significant increase of the off-current of NMOS transistors or by shifting the whole I-V curves (of both NMOS and PMOS transistors). Based on these assumptions, no significant shift of I-V curves should be observed in modern bulk CMOS technologies. However, such phenomenon may not be directly extrapolated to higher TID ranges, typically of several MGy for which only few data are available in the literature. This paper presents evidences of large threshold voltage shifts measured at MGy dose levels despite the fact that transistors are designed in a submicron bulk technology which features a 7-nm thin gate-oxide on GO2 transistors dedicated to mixed analog/digital integrated circuits. Such electrical shifts are encountered

Investigations on MGy ionizing dose effects in thin oxides of micro-electronic devices

International Nuclear Information System (INIS)

Gaillardin, M.; Paillet, P.; Raine, M.; Martinez, M.; Marcandella, C.; Duhamel, O.; Richard, N.; Leray, J.L.; Goiffon, V.; Corbiere, F.; Rolando, S.; Molina, R.; Magnan, P.; Girard, S.; Ouerdane, Y.; Boukenter, A.

2015-01-01

Total ionizing dose (TID) effects have been studied for a long time in micro-electronic components designed to operate in natural and artificial environments. In most cases, TID induces both charge trapping in the bulk of irradiated oxides and the buildup of interface traps located at semiconductor/dielectric interfaces. Such effects result from basic mechanisms driven by both the shape of the electric field which stands into the oxide and by fabrication process parameters inducing pre-existing traps in the oxide's bulk. From the pioneering studies based on 'thick' oxide technologies to the most recent ones dedicated to innovative technologies, most studies concluded that the impact of total ionizing dose effects reduces with the oxide thinning. This is specifically the case for the gate-oxide of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) for which it is generally considered that TID is not a major issue anymore at kGy dose ranges. TID effects are now mainly due to charge trapping in the field oxides such as Shallow Trench Isolation. This creates either parasitic conduction paths or Radiation-Induced Narrow Channel Effects (RINCE). Static current-voltage (I-V) electrical characteristics are then modified through a significant increase of the off-current of NMOS transistors or by shifting the whole I-V curves (of both NMOS and PMOS transistors). Based on these assumptions, no significant shift of I-V curves should be observed in modern bulk CMOS technologies. However, such phenomenon may not be directly extrapolated to higher TID ranges, typically of several MGy for which only few data are available in the literature. This paper presents evidences of large threshold voltage shifts measured at MGy dose levels despite the fact that transistors are designed in a submicron bulk technology which features a 7-nm thin gate-oxide on GO2 transistors dedicated to mixed analog/digital integrated circuits. Such electrical shifts are encountered

High-electric-field-stress-induced degradation of SiN passivated AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Wen-Ping, Gu; Huan-Tao, Duan; Jin-Yu, Ni; Yue, Hao; Jin-Cheng, Zhang; Qian, Feng; Xiao-Hua, Ma

2009-01-01

AlGaN/GaN high electron mobility transistors (HEMTs) are fabricated by employing SiN passivation, this paper investigates the degradation due to the high-electric-field stress. After the stress, a recoverable degradation has been found, consisting of the decrease of saturation drain current I Dsat , maximal transconductance g m , and the positive shift of threshold voltage V TH at high drain-source voltage V DS . The high-electric-field stress degrades the electric characteristics of AlGaN/GaN HEMTs because the high field increases the electron trapping at the surface and in AlGaN barrier layer. The SiN passivation of AlGaN/GaN HEMTs decreases the surface trapping and 2DEG depletion a little during the high-electric-field stress. After the hot carrier stress with V DS = 20 V and V GS = 0 V applied to the device for 10 4 sec, the SiN passivation decreases the stress-induced degradation of I Dsat from 36% to 30%. Both on-state and pulse-state stresses produce comparative decrease of I Dsat , which shows that although the passivation is effective in suppressing electron trapping in surface states, it does not protect the device from high-electric-field degradation in nature. So passivation in conjunction with other technological solutions like cap layer, prepassivation surface treatments, or field-plate gate to weaken high-electric-field degradation should be adopted. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Multi-channel spintronic transistor design based on magnetoelectric barriers and spin-orbital effects

International Nuclear Information System (INIS)

Fujita, T; Jalil, M B A; Tan, S G

2008-01-01

We present a spin transistor design based on spin-orbital interactions in a two-dimensional electron gas, with magnetic barriers induced by a patterned ferromagnetic gate. The proposed device overcomes certain shortcomings of previous spin transistor designs such as long device length and degradation of conductance modulation for multi-channel transport. The robustness of our device for multi-channel transport is unique in spin transistor designs based on spin-orbit coupling. The device is more practical in fabrication and experimental respects compared to previously conceived single-mode spin transistors

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

Science.gov (United States)

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Effects of DC gate and drain bias stresses on the degradation of excimer laser crystallized polysilicon thin film transistors

International Nuclear Information System (INIS)

Kouvatsos, D N; Michalas, L; Voutsas, A T; Papaioannou, G J

2005-01-01

The effects of gate and drain bias stresses on thin film transistors fabricated in polysilicon films crystallized using the advanced sequential lateral solidification excimer laser annealing (SLS ELA) process, which yields very elongated polysilicon grains and allows the fabrication of TFTs without grain boundary barriers to current flow, are investigated as a function of the active layer thickness and of the TFT orientation relative to the grains. The application of hot carrier stress, with a condition of V GS = V DS /2, was determined to induce threshold voltage, subthreshold swing and transconductance degradation for TFTs in thicker polysilicon films and the associated stress-induced increase in the active layer trap density was evaluated. However, this device degradation was drastically reduced for TFTs fabricated in ultra-thin films. Furthermore, the application of the same stress condition to TFTs oriented vertically to the elongated grains resulted in similar threshold voltage shift but in substantially decreased subthreshold swing and transconductance degradation. The immunity of ultra-thin active layer devices to degradation under hot carrier stress clearly suggests the implementation of ultra thin SLS ELA polysilicon films for the fabrication of TFTs exhibiting not only high performance but, especially, the high reliability needed for integrated systems on panel

Electrical characterization of commercial NPN bipolar junction transistors under neutron and gamma irradiation

Directory of Open Access Journals (Sweden)

OO Myo Min

2014-01-01

Full Text Available Electronics components such as bipolar junction transistors, diodes, etc. which are used in deep space mission are required to be tolerant to extensive exposure to energetic neutrons and ionizing radiation. This paper examines neutron radiation with pneumatic transfer system of TRIGA Mark-II reactor at the Malaysian Nuclear Agency. The effects of the gamma radiation from Co-60 on silicon NPN bipolar junction transistors is also be examined. Analyses on irradiated transistors were performed in terms of the electrical characteristics such as current gain, collector current and base current. Experimental results showed that the current gain on the devices degraded significantly after neutron and gamma radiations. Neutron radiation can cause displacement damage in the bulk layer of the transistor structure and gamma radiation can induce ionizing damage in the oxide layer of emitter-base depletion layer. The current gain degradation is believed to be governed by the increasing recombination current in the base-emitter depletion region.

Micro-irradiation experiments in MOS transistors using synchrotron radiation

International Nuclear Information System (INIS)

Autran, J.L.; Masson, P.; Raynaud, C.; Freud, N.; Riekel, C.

1999-01-01

Spatially-resolved total-dose degradation has been performed in MOS transistors by focusing x-ray synchrotron radiation on the gate electrode with micrometer resolution. The influence of the resulting permanent degradation on device electrical properties has been analyzed using current-voltage and charge pumping measurements, in concert with optical characterization (hot-carrier luminescence) and one-dimensional device simulation. (authors)

Cryogenic Lifetime Studies of 130 nm and 65 nm CMOS Technologies for High-Energy Physics Experiments

Energy Technology Data Exchange (ETDEWEB)

Hoff, James R. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Deptuch, G. W. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Wu, Guoying [Southern Methodist Univ., Dallas, TX (United States); Gui, Ping [Southern Methodist Univ., Dallas, TX (United States)

2015-06-04

The Long Baseline Neutrino Facility intends to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This, then, requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm and 65 nm nMOS transistors operating at cryogenic temperatures are investigated. Our results show that both technologies achieve the lifetimes required by the experiment. Minimal design changes are necessary in the case of the 130 nm process and no changes whatsoever are necessary for the 65 nm process.

Modulation of the effective work function of a TiN metal gate for NMOS requisition with Al incorporation

International Nuclear Information System (INIS)

Han Kai; Ma Xueli; Yang Hong; Wang Wenwu

2013-01-01

The effect of Al incorporation on the effective work function (EWF) of TiN metal gate was systematically investigated. Metal—oxide—semiconductor (MOS) capacitors with W/TiN/Al/TiN gate stacks were used to fulfill this purpose. Different thickness ratios of Al to TiN and different post metal annealing (PMA) conditions were employed. Significant shift of work function towards to Si conduction band was observed, which was suitable for NMOS and the magnitude of shift depends on the processing conditions. (semiconductor technology)

Micro-irradiation experiments in MOS transistors using synchrotron radiation; Experiences de micro-irradiation de transistors MOS a l'aide d'un rayonnement synchrotron

Energy Technology Data Exchange (ETDEWEB)

Autran, J.L.; Masson, P.; Raynaud, C. [Institut National des Sciences Appliquees (INSA), 69 - Villeurbanne (France). Lab. de Physique de la Matiere; Masson, P. [Ecole Nationale Superieure d' Electronique et de Radio-Electricite, ENSERG/LPCS, 38 - Grenoble (France); Freud, N. [Institut National des Sciences Appliquees (INSA), CNDRI, 69 - Villeurbanne (France); Riekel, C. [European Synchrotron Radiation Facility ESRF, 38 - Grenoble (France)

1999-07-01

Spatially-resolved total-dose degradation has been performed in MOS transistors by focusing x-ray synchrotron radiation on the gate electrode with micrometer resolution. The influence of the resulting permanent degradation on device electrical properties has been analyzed using current-voltage and charge pumping measurements, in concert with optical characterization (hot-carrier luminescence) and one-dimensional device simulation. (authors)

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

Science.gov (United States)

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Transistor Effect in Improperly Connected Transistors.

Science.gov (United States)

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

Interface Engineering for Precise Threshold Voltage Control in Multilayer-Channel Thin Film Transistors

KAUST Repository

Park, Jihoon

2016-11-29

Multilayer channel structure is used to effectively manipulate the threshold voltage of zinc oxide transistors without degrading its field-effect mobility. Transistors operating in enhancement mode with good mobility are fabricated by optimizing the structure of the multilayer channel. The optimization is attributed to the formation of additional channel and suppression of the diffusion of absorbed water molecules and oxygen vacancies.

Interface Engineering for Precise Threshold Voltage Control in Multilayer-Channel Thin Film Transistors

KAUST Repository

Park, Jihoon; Alshammari, Fwzah Hamud; Wang, Zhenwei; Alshareef, Husam N.

2016-01-01

Multilayer channel structure is used to effectively manipulate the threshold voltage of zinc oxide transistors without degrading its field-effect mobility. Transistors operating in enhancement mode with good mobility are fabricated by optimizing the structure of the multilayer channel. The optimization is attributed to the formation of additional channel and suppression of the diffusion of absorbed water molecules and oxygen vacancies.

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

International Nuclear Information System (INIS)

Yan-Rong, Cao; Xiao-Hua, Ma; Yue, Hao; Shi-Gang, Hu

2010-01-01

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Source/drain electrodes contact effect on the stability of bottom-contact pentacene field-effect transistors

Directory of Open Access Journals (Sweden)

Xinge Yu

2012-06-01

Full Text Available Bottom-contact pentacene field-effect transistors were fabricated with a PMMA dielectric layer, and the air stability of the transistors was investigated. To characterize the device stability, the field-effect transistors were exposed to ambient conditions for 30 days and subsequently characterized. The degradation of electrical performance was traced to study the variation of field-effect mobility, saturation current and off-state current. By investigating the morphology variance of the pentacene film at the channel and source/drain (S/D contact regions by atomic force microscopy, it was clear that the morphology of the pentacene film adhered to the S/D degenerated dramatically. Moreover, by studying the variation of contact resistance in detail, it was found that the S/D contact effect was the main reason for the degradation in performance.

Characteristics of voltage regulators with serial NPN transistor in the fields of medium and high energy photons

International Nuclear Information System (INIS)

Vukic, V.; Osmokrovic, P.

2007-01-01

Variation of collector - emitter dropout voltage on serial transistors of voltage regulators LM2990T-5 and LT1086CT5 were used as the parameter for detection of examined devices' radiation hardness in X and ? radiation fields. Biased voltage regulators with serial super-β transistor in the medium dose rate X radiation field had significantly different response from devices with conventional serial NPN transistor. Although unbiased components suffered greater damage in most cases, complete device failure happened only among the biased components with serial super-β transistor in Bremsstrahlung field. Mechanisms of transistors degradation in ionizing radiation fields were analysed [sr

SOI Transistor measurement techniques using body contacted transistors

International Nuclear Information System (INIS)

Worley, E.R.; Williams, R.

1989-01-01

Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

Transistor Small Signal Analysis under Radiation Effects

International Nuclear Information System (INIS)

Sharshar, K.A.A.

2004-01-01

A Small signal transistor parameters dedicate the operation of bipolar transistor before and after exposed to gamma radiation (1 Mrad up to 5 Mrads) and electron beam(1 MeV, 25 mA) with the same doses as a radiation sources, the electrical parameters of the device are changed. The circuit Model has been discussed.Parameters, such as internal emitter resistance (re), internal base resistance, internal collector resistance (re), emitter base photocurrent (Ippe) and base collector photocurrent (Ippe). These parameters affect on the operation of the device in its applications, which work as an effective element, such as current gain (hFE≡β)degradation it's and effective parameter in the device operation. Also the leakage currents (IcBO) and (IEBO) are most important parameters, Which increased with radiation doses. Theoretical representation of the change in the equivalent circuit for NPN and PNP bipolar transistor were discussed, the input and output parameters of the two types were discussed due to the change in small signal input resistance of the two types. The emitter resistance(re) were changed by the effect of gamma and electron beam irradiation, which makes a change in the role of matching impedances between transistor stages. Also the transistor stability factors S(Ico), S(VBE) and S(β are detected to indicate the transistor operations after exposed to radiation fields. In low doses the gain stability is modified due to recombination of induced charge generated during device fabrication. Also the load resistance values are connected to compensate the effect

Transistor data book

International Nuclear Information System (INIS)

1988-03-01

It introduces how to use this book. It lists transistor data and index, which are Type No, Cross index, Germanium PNP low power transistors, silicon NPN low power transistors, Germanium PNP high power transistors, Switching transistors, transistor arrays, Miscellaneous transistors, types with U.S military specifications, direct replacement transistors, suggested replacement transistors, schematic drawings, outline drawings, device number keys and manufacturer's logos.

Simulation of 50-nm Gate Graphene Nanoribbon Transistors

Directory of Open Access Journals (Sweden)

Cedric Nanmeni Bondja

2016-01-01

Full Text Available An approach to simulate the steady-state and small-signal behavior of GNR MOSFETs (graphene nanoribbon metal-semiconductor-oxide field-effect transistor is presented. GNR material parameters and a method to account for the density of states of one-dimensional systems like GNRs are implemented in a commercial device simulator. This modified tool is used to calculate the current-voltage characteristics as well the cutoff frequency fT and the maximum frequency of oscillation fmax of GNR MOSFETs. Exemplarily, we consider 50-nm gate GNR MOSFETs with N = 7 armchair GNR channels and examine two transistor configurations. The first configuration is a simplified MOSFET structure with a single GNR channel as usually studied by other groups. Furthermore, and for the first time in the literature, we study in detail a transistor structure with multiple parallel GNR channels and interribbon gates. It is shown that the calculated fT of GNR MOSFETs is significantly lower than that of GFETs (FET with gapless large-area graphene channel with comparable gate length due to the mobility degradation in GNRs. On the other hand, GNR MOSFETs show much higher fmax compared to experimental GFETs due the semiconducting nature of the GNR channels and the resulting better saturation of the drain current. Finally, it is shown that the gate control in FETs with multiple parallel GNR channels is improved while the cutoff frequency is degraded compared to single-channel GNR MOSFETs due to parasitic capacitances of the interribbon gates.

Study on ionizing radiation effects of bipolar transistor with BPSG films

International Nuclear Information System (INIS)

Lu Man; Zhang Xiaoling; Xie Xuesong; Sun Jiangchao; Wang Pengpeng; Lu Changzhi; Zhang Yanxiu

2013-01-01

Background: Because of the damage induced by ionizing radiation, bipolar transistors in integrated voltage regulator could induce the current gain degradation and increase leakage current. This will bring serious problems to electronic system. Purpose: In order to ensure the reliability of the device work in the radiation environments, the device irradiation reinforcement technology is used. Methods: The characteristics of 60 Co γ irradiation and annealing at different temperatures in bipolar transistors and voltage regulators (JW117) with different passive films for SiO 2 +BPSG+SiO 2 and SiO 2 +SiN have been investigated. Results: The devices with BPSG film enhanced radiation tolerance significantly. Because BPSG films have better absorption for Na + in SiO 2 layer, the surface recombination rate of base region in a bipolar transistor and the excess base current have been reduced. It may be the main reason for BJT with BPSG film having a good radiation hardness. And annealing experiments at different temperatures after irradiation ensure the reliability of the devices with BPSG films. Conclusions: A method of improving the ionizing irradiation hardness of bipolar transistors is proposed. As well as the linear integrated circuits which containing bipolar transistors, an experimental basis for the anti-ionizing radiation effects of bipolar transistors is provided. (authors)

Bias temperature instability in tunnel field-effect transistors

Science.gov (United States)

Mizubayashi, Wataru; Mori, Takahiro; Fukuda, Koichi; Ishikawa, Yuki; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Liu, Yongxun; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Matsukawa, Takashi; Masahara, Meishoku; Endo, Kazuhiko

2017-04-01

We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms in TFETs are the same as those in metal-oxide-semiconductor FETs (MOSFETs). In TFETs, although traps are generated in high-k gate dielectrics by the bias stress and/or the interface state is degraded at the interfacial layer/channel interface, the threshold voltage (V th) shift due to BTI degradation is caused by the traps and/or the degradation of the interface state locating the band-to-band tunneling (BTBT) region near the source/gate edge. The BTI lifetime in n- and p-type TFETs is improved by applying a drain bias corresponding to the operation conditions.

Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

Directory of Open Access Journals (Sweden)

Noor Faizah Z.A.

2016-01-01

Full Text Available This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2 as dielectric and Tungsten Silicide (WSi2 and Titanium Silicide (TiSi2 as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil

2017-11-13

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor\\'s width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Organic transistors with high thermal stability for medical applications.

Science.gov (United States)

Kuribara, Kazunori; Wang, He; Uchiyama, Naoya; Fukuda, Kenjiro; Yokota, Tomoyuki; Zschieschang, Ute; Jaye, Cherno; Fischer, Daniel; Klauk, Hagen; Yamamoto, Tatsuya; Takimiya, Kazuo; Ikeda, Masaaki; Kuwabara, Hirokazu; Sekitani, Tsuyoshi; Loo, Yueh-Lin; Someya, Takao

2012-03-06

The excellent mechanical flexibility of organic electronic devices is expected to open up a range of new application opportunities in electronics, such as flexible displays, robotic sensors, and biological and medical electronic applications. However, one of the major remaining issues for organic devices is their instability, especially their thermal instability, because low melting temperatures and large thermal expansion coefficients of organic materials cause thermal degradation. Here we demonstrate the fabrication of flexible thin-film transistors with excellent thermal stability and their viability for biomedical sterilization processes. The organic thin-film transistors comprise a high-mobility organic semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene, and thin gate dielectrics comprising a 2-nm-thick self-assembled monolayer and a 4-nm-thick aluminium oxide layer. The transistors exhibit a mobility of 1.2 cm(2) V(-1)s(-1) within a 2 V operation and are stable even after exposure to conditions typically used for medical sterilization.

Impact of doped boron concentration in emitter on high- and low-dose-rate damage in lateral PNP transistors

International Nuclear Information System (INIS)

Zheng Yuzhan; Lu Wu; Ren Diyuan; Wang Yiyuan; Wang Zhikuan; Yang Yonghui

2010-01-01

The characteristics of radiation damage under a high or low dose rate in lateral PNP transistors with a heavily or lightly doped emitter is investigated. Experimental results show that as the total dose increases, the base current of transistors would increase and the current gain decreases. Furthermore, more degradation has been found in lightly-doped PNP transistors, and an abnormal effect is observed in heavily doped transistors. The role of radiation defects, especially the double effects of oxide trapped charge, is discussed in heavily or lightly doped transistors. Finally, through comparison between the high- and low-dose-rate response of the collector current in heavily doped lateral PNP transistors, the abnormal effect can be attributed to the annealing of the oxide trapped charge. The response of the collector current, in heavily doped PNP transistors under high- and low-dose-rate irradiation is described in detail. (semiconductor integrated circuits)

Impact of repeated uniaxial mechanical strain on flexible a-IGZO thin film transistors with symmetric and asymmetric structures

Science.gov (United States)

Liao, Po-Yung; Chang, Ting-Chang; Su, Wan-Ching; Chen, Bo-Wei; Chen, Li-Hui; Hsieh, Tien-Yu; Yang, Chung-Yi; Chang, Kuan-Chang; Zhang, Sheng-Dong; Huang, Yen-Yu; Chang, Hsi-Ming; Chiang, Shin-Chuan

2017-06-01

This letter investigates repeated uniaxial mechanical stress-induced degradation behavior in flexible amorphous In-Ga-Zn-O thin-film transistors (TFTs) of different geometric structures. Two types of via-contact structure TFTs are investigated: symmetrical and UI structure (TFTs with I- and U-shaped asymmetric electrodes). After repeated mechanical stress, I-V curves for the symmetrical structure show a significant negative threshold voltage (VT) shift, due to mechanical stress-induced oxygen vacancy generation. However, degradation in the UI structure TFTs after stress is a negative VT shift along with the parasitic transistor characteristic in the forward-operation mode, with this hump not evident in the reverse-operation mode. This asymmetrical degradation is clarified by the mechanical strain simulation of the UI TFTs.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

Science.gov (United States)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Reliability of planar silicon transistors exposed to 60Co γ rays

International Nuclear Information System (INIS)

Blin, A.; Le Ber, J.

1966-01-01

This report gives an account of results obtained during investigations on the reliability of silicon Planar Transistors, irradiated by the 60 Co γ rays. We consider in a first part the variation of the average values of the parameters of the lots under test. Then, a more complete statistical study is carried out (distribution of the values of the parameters within the lots; research of correlations, etc. ). It is clearly stated and shown that evaluation of the degradation of the gain of transistors depends on: the conditions of measurement (voltage, current), after irradiation; the polarisation of the elements during irradiation; the origin of manufacture of the lots under test (4 manufacturers). We show then the difficulties met to predict the behaviour of the transistors under radiation stress, and attempt is made to define practical rules for design engineers. (author) [fr

Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress

International Nuclear Information System (INIS)

Hsieh, Tien-Yu; Chang, Ting-Chang; Chen, Te-Chih; Tsai, Ming-Yen; Chen, Yu-Te

2013-01-01

This paper investigates the degradation mechanism of amorphous InGaZnO thin-film transistors under DC and AC gate bias stress. Comparing the degradation behavior at equal accumulated effective stress time, more pronounced threshold voltage shift under AC positive gate bias stress in comparison with DC stress indicates extra electron-trapping phenomenon that occurs in the duration of rising/falling time in pulse. Contrarily, illuminated AC negative gate bias stress exhibits much less threshold voltage shift than DC stress, suggesting that the photo-generated hole does not have sufficient time to drift to the interface of IGZO/gate insulator and causes hole-trapping under AC operation. Since the evolution of threshold voltage fits the stretched-exponential equation well, the different degradation tendencies under DC/AC stress can be attributed to the different electron- and hole-trapping efficiencies, and this is further verified by varying pulse waveform. - Highlights: ► Static and dynamic gate bias stresses are imposed on InGaZnO TFTs. ► Dynamic positive gate bias induces more pronounced threshold voltage shift. ► Static negative-bias illumination stress induces more severe threshold voltage shift. ► Evolution of threshold voltage fits the stretched-exponential equation well

Measurement of MOS current mismatch in the weak inversion region

International Nuclear Information System (INIS)

Forti, F.; Wright, M.E.

1994-01-01

The MOS transistor matching properties in the weak inversion region have not received, in the past, the attention that the mismatch in the strong inversion region has. The importance of weak inversion biased transistors in low power CMOS analog systems calls for more extensive data on the mismatch in this region of operation. The study presented in this paper was motivated by the need of controlling the threshold matching in a low power, low noise amplifier discriminator circuit used in a silicon radiation detector read-out, where both the transistor dimensions and the currents had to be kept to a minimum. The authors have measured the current matching properties of MOS transistors operated in the weak inversion region. They measured a total of about 1,400 PMOS and NMOS transistors produced in four different processes and report here the results in terms of mismatch dependence on current density, device dimensions, and substrate voltage, without using any specific model for the transistor

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

Science.gov (United States)

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Doped Organic Transistors.

Science.gov (United States)

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Dopant profile engineering of advanced Si MOSFET's using ion implantation

International Nuclear Information System (INIS)

Stolk, P.A.; Ponomarev, Y.V.; Schmitz, J.; Brandenburg, A.C.M.C. van; Roes, R.; Montree, A.H.; Woerlee, P.H.

1999-01-01

Ion implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET's. After defining the transistor configuration, SR profiles were formed by dopant implantation through the polycrystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation

Deformable Organic Nanowire Field-Effect Transistors.

Science.gov (United States)

Lee, Yeongjun; Oh, Jin Young; Kim, Taeho Roy; Gu, Xiaodan; Kim, Yeongin; Wang, Ging-Ji Nathan; Wu, Hung-Chin; Pfattner, Raphael; To, John W F; Katsumata, Toru; Son, Donghee; Kang, Jiheong; Matthews, James R; Niu, Weijun; He, Mingqian; Sinclair, Robert; Cui, Yi; Tok, Jeffery B-H; Lee, Tae-Woo; Bao, Zhenan

2018-02-01

Deformable electronic devices that are impervious to mechanical influence when mounted on surfaces of dynamically changing soft matters have great potential for next-generation implantable bioelectronic devices. Here, deformable field-effect transistors (FETs) composed of single organic nanowires (NWs) as the semiconductor are presented. The NWs are composed of fused thiophene diketopyrrolopyrrole based polymer semiconductor and high-molecular-weight polyethylene oxide as both the molecular binder and deformability enhancer. The obtained transistors show high field-effect mobility >8 cm 2 V -1 s -1 with poly(vinylidenefluoride-co-trifluoroethylene) polymer dielectric and can easily be deformed by applied strains (both 100% tensile and compressive strains). The electrical reliability and mechanical durability of the NWs can be significantly enhanced by forming serpentine-like structures of the NWs. Remarkably, the fully deformable NW FETs withstand 3D volume changes (>1700% and reverting back to original state) of a rubber balloon with constant current output, on the surface of which it is attached. The deformable transistors can robustly operate without noticeable degradation on a mechanically dynamic soft matter surface, e.g., a pulsating balloon (pulse rate: 40 min -1 (0.67 Hz) and 40% volume expansion) that mimics a beating heart, which underscores its potential for future biomedical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

Science.gov (United States)

Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

2018-05-01

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Science.gov (United States)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

The effects of gamma irradiation on neutron displacement sensitivity of lateral PNP bipolar transistors

International Nuclear Information System (INIS)

Wang, Chenhui; Chen, Wei; Liu, Yan; Jin, Xiaoming; Yang, Shanchao; Qi, Chao

2016-01-01

The effects of gamma irradiation on neutron displacement sensitivity of four types of lateral PNP bipolar transistors (LPNPs) with different neutral base widths, emitter widths and the doping concentrations of the epitaxial base region are studied. The physical mechanisms of the effects are explored by defect analysis using deep level transient spectroscopy (DLTS) techniques and numerical simulations of recombination process in the base region of the lateral PNP bipolar transistors, and are verified by the experiments on gate-controlled lateral PNP bipolar transistors (GCLPNPs) manufactured in the identical commercial bipolar process with different gate bias voltage. The results indicate that gamma irradiation increases neutron displacement damage sensitivity of lateral PNP bipolar transistors and the mechanism of this phenomenon is that positive charge induced by gamma irradiation enhances the recombination process in the defects induced by neutrons in the base region, leading to larger recombination component of base current and greater gain degradation.

The effects of gamma irradiation on neutron displacement sensitivity of lateral PNP bipolar transistors

Energy Technology Data Exchange (ETDEWEB)

Wang, Chenhui, E-mail: wangchenhui@nint.ac.cn; Chen, Wei; Liu, Yan; Jin, Xiaoming; Yang, Shanchao; Qi, Chao

2016-09-21

The effects of gamma irradiation on neutron displacement sensitivity of four types of lateral PNP bipolar transistors (LPNPs) with different neutral base widths, emitter widths and the doping concentrations of the epitaxial base region are studied. The physical mechanisms of the effects are explored by defect analysis using deep level transient spectroscopy (DLTS) techniques and numerical simulations of recombination process in the base region of the lateral PNP bipolar transistors, and are verified by the experiments on gate-controlled lateral PNP bipolar transistors (GCLPNPs) manufactured in the identical commercial bipolar process with different gate bias voltage. The results indicate that gamma irradiation increases neutron displacement damage sensitivity of lateral PNP bipolar transistors and the mechanism of this phenomenon is that positive charge induced by gamma irradiation enhances the recombination process in the defects induced by neutrons in the base region, leading to larger recombination component of base current and greater gain degradation.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

Science.gov (United States)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor

Unijunction transistors

International Nuclear Information System (INIS)

1981-01-01

The electrical characteristics of unijunction transistors can be modified by irradiation with electron beams in excess of 400 KeV and at a dose rate of 10 13 to 10 16 e/cm 2 . Examples are given of the effect of exposing the emitter-base junctions of transistors to such lattice defect causing radiation for a time sufficient to change the valley current of the transistor. (U.K.)

BUSFET -- A radiation-hardened SOI transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Energy Technology Data Exchange (ETDEWEB)

Liu, Xuhai; Kasemann, Daniel, E-mail: daniel.kasemann@iapp.de; Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Strasse 1, 01069 Dresden (Germany)

2015-03-09

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon S.; Hussain, Muhammad Mustafa

2017-01-01

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

BUSFET - A Novel Radiation-Hardened SOI Transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

Impact of process variations and long term degradation on 6T-SRAM cells

Directory of Open Access Journals (Sweden)

Th. Fischer

2007-06-01

Full Text Available In modern deep-submicron CMOS technologies voltage scaling can not keep up with the scaling of the dimensions of transistors. Therefore the electrical fields inside the transistors are not constant anymore, while scaling down the device area. The rising electrical fields bring up reliability problems, such as hot carrier injection. Also other long term degradation mechanisms like Negative Bias Temperature Instability (NBTI come into the focus of circuit design.

Along with process device parameter variations (threshold voltage, mobility, variations due to the degradation of devices form a big challenge for designers to build circuits that both yield high under the influence of process variations and remain functional with respect to long term device drift.

In this work we present the influence of long term degradation and process variations on the performance of SRAM core-cells and parametric yield of SRAM arrays. For different use cases we show the performance degradation depending on temperature and supply voltage.

The impact transconductance parameter and threshold voltage of MOSFET’s in static characteristics of CMOS inverter

Directory of Open Access Journals (Sweden)

Milaim Zabeli

2017-11-01

Full Text Available The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements.

A novel high voltage start up circuit for an integrated switched mode power supply

Energy Technology Data Exchange (ETDEWEB)

Hu Hao; Chen Xingbi, E-mail: huhao21@uestc.edu.c [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)

2010-09-15

A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions. (semiconductor devices)

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

International Nuclear Information System (INIS)

Jiang Yuxi; Li Jiao; Ran Feng; Cao Jialin; Yang Dianxiong

2009-01-01

Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented. (semiconductor devices)

Review of recent developments in amorphous oxide semiconductor thin-film transistor devices

International Nuclear Information System (INIS)

Park, Joon Seok; Maeng, Wan-Joo; Kim, Hyun-Suk; Park, Jin-Seong

2012-01-01

The present article is a review of the recent progress and major trends in the field of thin-film transistor (TFT) research involving the use of amorphous oxide semiconductors (AOS). First, an overview is provided on how electrical performance may be enhanced by the adoption of specific device structures and process schemes, the combination of various oxide semiconductor materials, and the appropriate selection of gate dielectrics and electrode metals in contact with the semiconductor. As metal oxide TFT devices are excellent candidates for switching or driving transistors in next generation active matrix liquid crystal displays (AMLCD) or active matrix organic light emitting diode (AMOLED) displays, the major parameters of interest in the electrical characteristics involve the field effect mobility (μ FE ), threshold voltage (V th ), and subthreshold swing (SS). A study of the stability of amorphous oxide TFT devices is presented next. Switching or driving transistors in AMLCD or AMOLED displays inevitably involves voltage bias or constant current stress upon prolonged operation, and in this regard many research groups have examined and proposed device degradation mechanisms under various stress conditions. The most recent studies involve stress experiments in the presence of visible light irradiating the semiconductor, and different degradation mechanisms have been proposed with respect to photon radiation. The last part of this review consists of a description of methods other than conventional vacuum deposition techniques regarding the formation of oxide semiconductor films, along with some potential application fields including flexible displays and information storage.

Low-frequency 1/f noise in MoS2 transistors: Relative contributions of the channel and contacts

Science.gov (United States)

Renteria, J.; Samnakay, R.; Rumyantsev, S. L.; Jiang, C.; Goli, P.; Shur, M. S.; Balandin, A. A.

2014-04-01

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS2 field-effect transistors revealing the relative contributions of the MoS2 channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS2 transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS2 transistors, are 2 × 1019 eV-1cm-3 and 2.5 × 1020 eV-1cm-3 for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS2 transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS2 and other van der Waals materials.

Degradation of SiGe devices by proton irradiation

Energy Technology Data Exchange (ETDEWEB)

Ohyama, Hidenori; Hayama, Kiyoteru [Kumamoto National Coll. of Technology, Nishigoshi (Japan); Vanhellemont, J; Takami, Yasukiyo; Sunaga, Hiromi; Nashiyama, Isamu; Uwatoko, Yoshiya; Poortmans, J; Caymax, M

1997-03-01

The degradation and recovery behavior of strained Si{sub 1-x}Ge{sub x} diodes and heterojunction bipolar transistors (HBTs) by irradiated by protons are studied. The degradation of device performance and the generation of lattice defects are reported as a function of fluence and germanium content and also compared extensively with previous results obtained on electron and neutron irradiated devices. In order to study the recovery behavior of the irradiated devices, isochronal annealing is performed. The radiation source dependence of the degradation is discussed taking into account the number of knock-on atoms and the nonionizing energy loss (NIEL). (author)

Exciton-polaron quenching in organic thin-film transistors studied by fluorescence lifetime imaging microscopy

DEFF Research Database (Denmark)

Jensen, Per Baunegaard With; Leißner, Till; Osadnik, Andreas

Organic semiconductors show great potential in electronic and optical applications. However, a major challenge is the degradation of the semiconductor materials that cause a reduction in device performance. Here, we present our investigations of Organic Thin Film Transistors (OTFT) based...... that correlates with the local charge density indicates a pronounced exciton quenching by the injected charges. Subsequent FLIM measurements on previously biased OTFT devices show a general decrease in fluorescence lifetime suggesting degradation of the organic semiconductor. This is correlated with the results...

Mechanisms of ionizing-radiation-induced gain degradation in lateral PNP BJTs

International Nuclear Information System (INIS)

Schmidt, D.M.; Wu, A.; Schrimpf, R.D.; Pease, R.L.; Combs, W.E.

1996-01-01

The physical mechanisms for gain degradation in laterals PNP bipolar transistors are examined experimentally and through simulation. The effect of increased surface recombination velocity at the base surface is moderated by positive oxide charge

Reduced Voltage Scaling in Clock Distribution Networks

Directory of Open Access Journals (Sweden)

Khader Mohammad

2009-01-01

Full Text Available We propose a novel circuit technique to generate a reduced voltage swing (RVS signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV devices and the programmability of the low voltage value.

Enhancement of Transistor-to-Transistor Variability Due to Total Dose Effects in 65-nm MOSFETs

CERN Document Server

Gerardin, S; Cornale, D; Ding, L; Mattiazzo, S; Paccagnella, A; Faccio, F; Michelis, S

2015-01-01

We studied device-to-device variations as a function of total dose in MOSFETs, using specially designed test structures and procedures aimed at maximizing matching between transistors. Degradation in nMOSFETs is less severe than in pMOSFETs and does not show any clear increase in sample-to-sample variability due to the exposure. At doses smaller than 1 Mrad( SiO2) variability in pMOSFETs is also practically unaffected, whereas at very high doses-in excess of tens of Mrad( SiO2)-variability in the on-current is enhanced in a way not correlated to pre-rad variability. The phenomenon is likely due to the impact of random dopant fluctuations on total ionizing dose effects.

Copper atomic-scale transistors.

Science.gov (United States)

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

Energy Technology Data Exchange (ETDEWEB)

Liao, Po-Yung [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chou, Cheng-Hsu; Chang, Jung-Fang [Product Technology Center, Chimei Innolux Corp., Tainan 741, Taiwan (China)

2016-03-31

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V{sub T}) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V{sub T} shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V{sub T} shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V{sub T} shift increases with decreasing frequency of the top gate pulses.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

International Nuclear Information System (INIS)

Liao, Po-Yung; Chang, Ting-Chang; Hsieh, Tien-Yu; Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo; Chou, Cheng-Hsu; Chang, Jung-Fang

2016-01-01

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V T ) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V T shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V T shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V T shift increases with decreasing frequency of the top gate pulses.

Superconducting transistor

International Nuclear Information System (INIS)

Gray, K.E.

1978-01-01

A three film superconducting tunneling device, analogous to a semiconductor transistor, is presented, including a theoretical description and experimental results showing a current gain of four. Much larger current gains are shown to be feasible. Such a development is particularly interesting because of its novelty and the striking analogies with the semiconductor junction transistor

Investigation of abrupt degradation of drain current caused by under-gate crack in AlGaN/GaN high electron mobility transistors during high temperature operation stress

Energy Technology Data Exchange (ETDEWEB)

Zeng, Chang; Liao, XueYang; Li, RuGuan; Wang, YuanSheng; Chen, Yiqiang, E-mail: yiqiang-chen@hotmail.com; Su, Wei; Liu, Yuan; Wang, Li Wei; Lai, Ping; Huang, Yun; En, YunFei [Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, The 5th Electronics Research Institute of the Ministry of Industry and Information Technology, 510610 Guangzhou (China)

2015-09-28

In this paper, we investigate the degradation mode and mechanism of AlGaN/GaN based high electron mobility transistors (HEMTs) during high temperature operation (HTO) stress. It demonstrates that there was abrupt degradation mode of drain current during HTO stress. The abrupt degradation is ascribed to the formation of crack under the gate which was the result of the brittle fracture of epilayer based on failure analysis. The origin of the mechanical damage under the gate is further investigated and discussed based on top-down scanning electron microscope, cross section transmission electron microscope and energy dispersive x-ray spectroscopy analysis, and stress simulation. Based on the coupled analysis of the failure physical feature and stress simulation considering the coefficient of thermal expansion (CTE) mismatch in different materials in gate metals/semiconductor system, the mechanical damage under the gate is related to mechanical stress induced by CTE mismatch in Au/Ti/Mo/GaN system and stress concentration caused by the localized structural damage at the drain side of the gate edge. These results indicate that mechanical stress induced by CTE mismatch of materials inside the device plays great important role on the reliability of AlGaN/GaN HEMTs during HTO stress.

Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

NARCIS (Netherlands)

Khan, M.A.; Kerkhoff, Hans G.

2014-01-01

In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

Low-frequency 1/f noise in MoS2 transistors: Relative contributions of the channel and contacts

International Nuclear Information System (INIS)

Renteria, J.; Jiang, C.; Samnakay, R.; Rumyantsev, S. L.; Goli, P.; Balandin, A. A.; Shur, M. S.

2014-01-01

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS 2 field-effect transistors revealing the relative contributions of the MoS 2 channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS 2 transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS 2 transistors, are 2 × 10 19  eV −1 cm −3 and 2.5 × 10 20  eV −1 cm −3 for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS 2 transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS 2 and other van der Waals materials

Ionizing/displacement synergistic effects induced by gamma and neutron irradiation in gate-controlled lateral PNP bipolar transistors

Energy Technology Data Exchange (ETDEWEB)

Wang, Chenhui, E-mail: wangchenhui@nint.ac.cn [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Chen, Wei; Yao, Zhibin; Jin, Xiaoming; Liu, Yan; Yang, Shanchao [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Wang, Zhikuan [State Key Laboratory of Analog Integrated Circuit, Chongqing 400060 (China)

2016-09-21

A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to do experimental validations and studies on the ionizing/displacement synergistic effects in the lateral PNP bipolar transistor. The individual and mixed irradiation experiments of gamma rays and neutrons are accomplished on the transistors. The common emitter current gain, gate sweep characteristics and sub-threshold sweep characteristics are measured after each exposure. The results indicate that under the sequential irradiation of gamma rays and neutrons, the response of the gate-controlled lateral PNP bipolar transistor does exhibit ionizing/displacement synergistic effects and base current degradation is more severe than the simple artificial sum of those under the individual gamma and neutron irradiation. Enough attention should be paid to this phenomenon in radiation damage evaluation. - Highlights: • A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to facilitate the analysis of ionizing/displacement synergistic effects induced by the mixed irradiation of gamma and neutron. • The difference between ionizing/displacement synergistic effects and the simple sum of TID and displacement effects is analyzed. • The physical mechanisms of synergistic effects are explained.

High-performance vertical organic transistors.

Science.gov (United States)

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Influence of X and gamma radiation and bias conditions on dropout voltage of voltage regulators serial transistors

International Nuclear Information System (INIS)

Vukic, V.; Osmokrovic, P.; Stankovic, S.; Kovacevic, M.

2005-01-01

Research topic presented in this paper is degradation of characteristics of low-dropout voltage regulator's serial transistor during exposure of device to the ionizing radiation. Voltage regulators were exposed to X and γ radiation in two modes: without bias conditions, and with bias conditions and load. Tested circuits are representatives of the first and the second generation of low-dropout voltage regulators, with lateral and vertical PNP serial transistor: LM2940 and L4940. Experimental results of output voltage and serial dropout voltage change in function of total ionizing dose, during the medium-dose-rate exposure, were presented. (author) [sr

Radiation resistance of wide-bandgap semiconductor power transistors

Energy Technology Data Exchange (ETDEWEB)

Hazdra, Pavel; Popelka, Stanislav [Department of Microelectronics, Czech Technical University in Prague (Czech Republic)

2017-04-15

Radiation resistance of state-of-the-art commercial wide-bandgap power transistors, 1700 V 4H-SiC power MOSFETs and 200 V GaN HEMTs, to the total ionization dose was investigated. Transistors were irradiated with 4.5 MeV electrons with doses up to 2000 kGy. Electrical characteristics and introduced defects were characterized by current-voltage (I-V), capacitance-voltage (C-V), and deep level transient spectroscopy (DLTS) measurements. Results show that already low doses of 4.5 MeV electrons (>1 kGy) cause a significant decrease in threshold voltage of SiC MOSFETs due to embedding of the positive charge into the gate oxide. On the other hand, other parameters like the ON-state resistance are nearly unchanged up to the dose of 20 kGy. At 200 kGy, the threshold voltage returns back close to its original value, however, the ON-state resistance increases and transconductance is lowered. This effect is caused by radiation defects introduced into the low-doped drift region which decrease electron concentration and mobility. GaN HEMTs exhibit significantly higher radiation resistance. They keep within the datasheet specification up to doses of 2000 kGy. Absence of dielectric layer beneath the gate and high concentration of carriers in the two dimensional electron gas channel are the reasons of higher radiation resistance of GaN HEMTs. Their degradation then occurs at much higher doses due to electron mobility degradation. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Silicon nanowire transistors

CERN Document Server

Bindal, Ahmet

2016-01-01

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

Science.gov (United States)

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

Logarithmic current-measuring transistor circuits

DEFF Research Database (Denmark)

Højberg, Kristian Søe

1967-01-01

Describes two transistorized circuits for the logarithmic measurement of small currents suitable for nuclear reactor instrumentation. The logarithmic element is applied in the feedback path of an amplifier, and only one dual transistor is used as logarithmic diode and temperature compensating...... transistor. A simple one-amplifier circuit is compared with a two-amplifier system. The circuits presented have been developed in connexion with an amplifier using a dual m.o.s. transistor input stage with diode-protected gates....

Shootthrough fault protection system for bipolar transistors in a voltage source transistor inverter

International Nuclear Information System (INIS)

Wirth, W.F.

1982-01-01

Faulted bipolar transistors in a voltage source transistor inverter are protected against shootthrough fault current, from the filter capacitor of the d-c voltage source which drives the inverter over the d-c bus, by interposing a small choke in series with the filter capacitor to limit the rate of rise of that fault current while at the same time causing the d-c bus voltage to instantly drop to essentially zero volts at the beginning of a shootthrough fault. In this way, the load lines of the faulted transistors are effectively shaped so that they do not enter the second breakdown area, thereby preventing second breakdown destruction of the transistors

A High-Voltage Level Tolerant Transistor Circuit

NARCIS (Netherlands)

Annema, Anne J.; Geelen, Godefridus Johannes Gertrudis Maria

2001-01-01

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1)

Diode, transistor & fet circuits manual

CERN Document Server

Marston, R M

2013-01-01

Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

Vertical organic transistors

International Nuclear Information System (INIS)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-01-01

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted. (topical review)

Vertical organic transistors.

Science.gov (United States)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

Measurement bias dependence of enhanced bipolar gain degradation at low dose rates

International Nuclear Information System (INIS)

Witczak, S.C.; Lacoe, R.C.; Mayer, D.C.; Fleetwood, D.M.

1998-03-01

Oxide trapped charge, field effects from emitter metallization, and high level injection phenomena moderate enhanced gain degradation of lateral pnp transistors at low dose rates. Hardness assurance tests at elevated irradiation temperatures require larger design margins for low power measurement biases

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

Energy Technology Data Exchange (ETDEWEB)

Erofeev, E. V., E-mail: erofeev@micran.ru [Tomsk State University of Control Systems and Radioelectronics, Research Institute of Electrical-Communication Systems (Russian Federation); Fedin, I. V.; Kutkov, I. V. [Research and Production Company “Micran” (Russian Federation); Yuryev, Yu. N. [National Research Tomsk Polytechnic University, Institute of Physics and Technology (Russian Federation)

2017-02-15

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

International Nuclear Information System (INIS)

Erofeev, E. V.; Fedin, I. V.; Kutkov, I. V.; Yuryev, Yu. N.

2017-01-01

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V_t_h = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V_t_h = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

On theory of single-molecule transistor

International Nuclear Information System (INIS)

Tran Tien Phuc

2009-01-01

The results of the study on single-molecule transistor are mainly investigated in this paper. The structure of constructed single-molecule transistor is similar to a conventional MOSFET. The conductive channel of the transistors is a single-molecule of halogenated benzene derivatives. The chemical simulation software CAChe was used to design and implement for the essential parameter of the molecules utilized as the conductive channel. The GUI of Matlab has been built to design its graphical interface, calculate and plot the output I-V characteristic curves for the transistor. The influence of temperature, length and width of the conductive channel, and gate voltage is considered. As a result, the simulated curves are similar to the traditional MOSFET's. The operating temperature range of the transistors is wider compared with silicon semiconductors. The supply voltage for transistors is only about 1 V. The size of transistors in this research is several nanometers.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

Science.gov (United States)

Tavel, B.; Duriez, B.; Gwoziecki, R.; Basso, M. T.; Julien, C.; Ortolland, C.; Laplanche, Y.; Fox, R.; Sabouret, E.; Detcheverry, C.; Boeuf, F.; Morin, P.; Barge, D.; Bidaud, M.; Biénacel, J.; Garnier, P.; Cooper, K.; Chapon, J. D.; Trouiller, Y.; Belledent, J.; Broekaart, M.; Gouraud, P.; Denais, M.; Huard, V.; Rochereau, K.; Difrenza, R.; Planes, N.; Marin, M.; Boret, S.; Gloria, D.; Vanbergue, S.; Abramowitz, P.; Vishnubhotla, L.; Reber, D.; Stolk, P.; Woo, M.; Arnaud, F.

2006-04-01

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with FT = 160 GHz for LP and 280 GHz for GP nMOS transistors.

Impact of semiconductor/metal interfaces on contact resistance and operating speed of organic thin film transistors

KAUST Repository

Wondmagegn, Wudyalew T.

2010-09-24

The contact resistance of field effect transistors based on pentacene and parylene has been investigated by experimental and numerical analysis. The device simulation was performed using finite element two-dimensional drift-diffusion simulation taking into account field-dependent mobility, interface/bulk trap states and fixed charge density at the organic/insulator interface. The width-normalized contact resistance extracted from simulation which included an interface dipole layer between the gold source/drain electrodes and pentacene was 91 kΩcm. However, contact resistance extracted from the simulation, without consideration of interface dipole was 52.4 kΩcm, which is about half of the experimentally extracted 108 kΩcm. This indicates that interface dipoles are critical effects which degrade performances of organic field effect transistors by increasing the contact resistance. Using numerical calculations and circuit simulations, we have predicted a 1 MHz switching frequency for a 1 μm channel length transistor without dipole interface between gold and pentacene. The transistor with dipole interface is predicted, via the same methods, to exhibit an operating frequency of less than 0.5 MHz. © 2010 Springer Science+Business Media LLC.

Impact of semiconductor/metal interfaces on contact resistance and operating speed of organic thin film transistors

KAUST Repository

Wondmagegn, Wudyalew T.; Satyala, Nikhil T.; Pieper, Ron J.; Quevedo-Ló pez, Manuel Angel Quevedo; Gowrisanker, Srinivas; Alshareef, Husam N.; Stiegler, Harvey J.; Gnade, Bruce E.

2010-01-01

The contact resistance of field effect transistors based on pentacene and parylene has been investigated by experimental and numerical analysis. The device simulation was performed using finite element two-dimensional drift-diffusion simulation taking into account field-dependent mobility, interface/bulk trap states and fixed charge density at the organic/insulator interface. The width-normalized contact resistance extracted from simulation which included an interface dipole layer between the gold source/drain electrodes and pentacene was 91 kΩcm. However, contact resistance extracted from the simulation, without consideration of interface dipole was 52.4 kΩcm, which is about half of the experimentally extracted 108 kΩcm. This indicates that interface dipoles are critical effects which degrade performances of organic field effect transistors by increasing the contact resistance. Using numerical calculations and circuit simulations, we have predicted a 1 MHz switching frequency for a 1 μm channel length transistor without dipole interface between gold and pentacene. The transistor with dipole interface is predicted, via the same methods, to exhibit an operating frequency of less than 0.5 MHz. © 2010 Springer Science+Business Media LLC.

Dosimetric properties of MOS transistors

International Nuclear Information System (INIS)

Frank, H.; Petr, I.

1977-01-01

The structure of MOS transistors is described and their characteristics given. The experiments performed and data in the literature show the following dosimetric properties of MOS transistors: while for low gamma doses the transistor response to exposure is linear, it shows saturation for higher doses (exceeding 10 3 Gy in tissue). The response is independent of the energy of radiation and of the dose rate (within 10 -2 to 10 5 Gy/s). The spontaneous reduction with time of the spatial charge captured by the oxide layer (fading) is small and acceptable from the point of view of dosimetry. Curves are given of isochronous annealing of the transistors following irradiation with 137 Cs and 18 MeV electrons for different voltages during irradiation. The curves show that in MOS transistors irradiated with high-energy electrons the effect of annealing is less than in transistors irradiated with 137 Cs. In view of the requirement of using higher temperatures (approx. 400 degC) for the complete ''erasing'' of the captured charge, unsealed systems must be used for dosimetric purposes. The effect was also studied of neutron radiation, proton radiation and electron radiation on the MOS transistor structure. For MOS transistor irradiation with 14 MeV neutrons from a neutron generator the response was 4% of that for gamma radiation at the same dose equivalent. The effect of proton radiation was studied as related to the changes in MOS transistor structure during space flights. The response curve shapes are similar to those of gamma radiation curves. The effect of electron radiation on the MOS structure was studied by many authors. The experiments show that for each thickness of the SiO 2 layer an electron energy exists at which the size of the charge captured in SiO 2 is the greatest. All data show that MOS transistors are promising for radiation dosimetry. The main advantage of MOS transistors as gamma dosemeters is the ease and speed of evaluation, low sensitivity to neutron

Double-gate junctionless transistor model including short-channel effects

International Nuclear Information System (INIS)

Paz, B C; Pavanello, M A; Ávila-Herrera, F; Cerdeira, A

2015-01-01

This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (V TH ), subthreshold slope (S) and drain induced barrier lowering. (paper)

Colour tuneable light-emitting transistor

Energy Technology Data Exchange (ETDEWEB)

Feldmeier, Eva J.; Melzer, Christian; Seggern, Heinz von [Electronic Materials Department, Institute of Materials Science, Technische Universitaet Darmstadt (Germany)

2010-07-01

In recent years the interest in ambipolar organic light-emitting field-effect transistors has increased steadily as the devices combine switching behaviour of transistors with light emission. Usually, small molecules and polymers with a band gap in the visible spectral range serve as semiconducting materials. Mandatory remain balanced injection and transport properties for both charge carrier types to provide full control of the spatial position of the recombination zone of electrons and holes in the transistor channel via the applied voltages. As will be presented here, the spatial control of the recombination zone opens new possibilities towards light-emitting devices with colour tuneable emission. In our contribution an organic light-emitting field-effect transistors is presented whose emission colour can be changed by the applied voltages. The organic top-contact field-effect transistor is based on a parallel layer stack of acenes serving as organic transport and emission layers. The transistor displays ambipolar characteristics with a narrow recombination zone within the transistor channel. During operation the recombination zone can be moved by a proper change in the drain and gate bias from one organic semiconductor layer to another one inducing a change in the emission colour. In the presented example the emission maxima can be switched from 530 nm to 580 nm.

Dosimetric properties of MOS transistors

International Nuclear Information System (INIS)

Peter, I.; Frank, G.

1977-01-01

The performance of MOS transistors as gamma detectors has been tested. The dosimeter sensitivity has proved to be independent on the doses ranging from 10 3 to 10 6 R, and gamma energy of 137 Cs, 60 Co - sources and 5 - 18 MeV electrons. Fading of the space charge trapped by the SiO 2 layer of the transistor has appeared to be neglegible at room temperature after 400 hrs. The isochronous annealing in the temperature range of 40-260 deg C had a more substantial effect on the space charge of the transistor irradiated with 18 MeV electrons than on the 137 Cs gamma-irradiated transistors. This proved a repeated use of γ-dosemeters. MOS transistors are concluded to be promising for gamma dosimetry [ru

Transistor-based particle detection systems and methods

Science.gov (United States)

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Electron irradiation of power transistors

International Nuclear Information System (INIS)

Hower, P.L.; Fiedor, R.J.

1982-01-01

A method for reducing storage time and gain parameters in a semiconductor transistor includes the step of subjecting the transistor to electron irradiation of a dosage determined from measurements of the parameters of a test batch of transistors. Reduction of carrier lifetime by proton bombardment and gold doping is mentioned as an alternative to electron irradiation. (author)

Compositional influence on the electrical performance of zinc indium tin oxide transparent thin-film transistors

International Nuclear Information System (INIS)

Marsal, A.; Carreras, P.; Puigdollers, J.; Voz, C.; Galindo, S.; Alcubilla, R.; Bertomeu, J.; Antony, A.

2014-01-01

In this work, zinc indium tin oxide layers with different compositions are used as the active layer of thin film transistors. This multicomponent transparent conductive oxide is gaining great interest due to its reduced content of the scarce indium element. Experimental data indicate that the incorporation of zinc promotes the creation of oxygen vacancies, which results in a higher free carrier density. In thin-film transistors this effect leads to a higher off current and threshold voltage values. The field-effect mobility is also strongly degraded, probably due to coulomb scattering by ionized defects. A post deposition annealing in air reduces the density of oxygen vacancies and improves the field-effect mobility by orders of magnitude. Finally, the electrical characteristics of the fabricated thin-film transistors have been analyzed to estimate the density of states in the gap of the active layers. These measurements reveal a clear peak located at 0.3 eV from the conduction band edge that could be attributed to oxygen vacancies. - Highlights: • Zinc promotes the creation of oxygen vacancies in zinc indium tin oxide transistors. • Post deposition annealing in air reduces the density of oxygen. • Density of states reveals a clear peak located at 0.3 eV from the conduction band

Low-frequency 1/f noise in MoS{sub 2} transistors: Relative contributions of the channel and contacts

Energy Technology Data Exchange (ETDEWEB)

Renteria, J.; Jiang, C. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Samnakay, R. [Materials Science and Engineering Program, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Rumyantsev, S. L. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States); Ioffe Physical-Technical Institute, St. Petersburg 194021 (Russian Federation); Goli, P.; Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California – Riverside, Riverside, California 92521 (United States); Shur, M. S. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States)

2014-04-14

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS{sub 2} field-effect transistors revealing the relative contributions of the MoS{sub 2} channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS{sub 2} transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS{sub 2} transistors, are 2 × 10{sup 19} eV{sup −1}cm{sup −3} and 2.5 × 10{sup 20} eV{sup −1}cm{sup −3} for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS{sub 2} transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS{sub 2} and other van der Waals materials.

Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

KAUST Repository

Li, Jingqi

2014-07-01

A vertical carbon nanotube field-effect transistor (CNTFET) based on silicon (Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube (SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage (Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

KAUST Repository

Li, Jingqi; Yue, Weisheng; Guo, Zaibing; Yang, Yang; Wang, Xianbin; Syed, Ahad A.; Zhang, Yafei

2014-01-01

A vertical carbon nanotube field-effect transistor (CNTFET) based on silicon (Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube (SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage (Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Energy Technology Data Exchange (ETDEWEB)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

2015-08-24

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

The point of practical use for the transistor circuit

International Nuclear Information System (INIS)

1996-01-01

This is comprised of eight chapters and goes as follows; what is transistor? the first step for use of transistor such as connection between power and signal source, static characteristic of transistor and equivalent circuit of transistor, design of easy small-signal amplifier circuit, design for amplification of electric power and countermeasure for prevention of trouble, transistor concerned interface, transistor circuit around micro computer, transistor in active use of FET and power circuit and transistor. It has an appendix on transistor and design of bias of FET circuits like small signal transistor circuit and FET circuit.

Silicon on insulator self-aligned transistors

Science.gov (United States)

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Physical limits of silicon transistors and circuits

International Nuclear Information System (INIS)

Keyes, Robert W

2005-01-01

A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates.

Science.gov (United States)

Tetzner, Kornelius; Bose, Indranil R; Bock, Karlheinz

2014-10-29

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

Anomalous dose rate effects in gamma irradiated SiGe heterojunction bipolar transistors

International Nuclear Information System (INIS)

Banerjee, G.; Niu, G.; Cressler, J.D.; Clark, S.D.; Palmer, M.J.; Ahlgren, D.C.

1999-01-01

Low dose rate (LDR) cobalt-60 (0.1 rad(Si)/s) gamma irradiated Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) were studied. Comparisons were made with devices irradiated with 300 rad(Si)/s gamma radiation to verify if LDR radiation is a serious radiation hardness assurance (RHA) issue. Almost no LDR degradation was observed in this technology up to 50 krad(Si). The assumption of the presence of two competing mechanisms is justified by experimental results. At low total dose (le20 krad), an anomalous base current decrease was observed which is attributed to self-annealing of deep-level traps to shallower levels. An increase in base current at larger total doses is attributed to radiation induced generation-recombination (G/R) center generation. Experiments on gate-assisted lateral PNP transistors and 2D numerical simulations using MEDICI were used to confirm these assertions

Effect of random inhomogeneities in the spatial distribution of radiation-induced defect clusters on carrier transport through the thin base of a heterojunction bipolar transistor upon neutron irradiation

Energy Technology Data Exchange (ETDEWEB)

Puzanov, A. S.; Obolenskiy, S. V., E-mail: obolensk@rf.unn.ru; Kozlov, V. A. [Lobachevsky State University of Nizhny Novgorod (NNSU) (Russian Federation)

2016-12-15

We analyze the electron transport through the thin base of a GaAs heterojunction bipolar transistor with regard to fluctuations in the spatial distribution of defect clusters induced by irradiation with a fissionspectrum fast neutron flux. We theoretically demonstrate that the homogeneous filling of the working region with radiation-induced defect clusters causes minimum degradation of the dc gain of the heterojunction bipolar transistor.

Break-before-make CMOS inverter for power-efficient delay implementation.

Science.gov (United States)

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Power transistor module for high current applications

International Nuclear Information System (INIS)

Cilyo, F.F.

1975-01-01

One of the parts needed for the control system of the 400-GeV accelerator at Fermilab was a power transistor with a safe operating area of 1800A at 50V, dc current gain of 100,000 and 20 kHz bandwidth. Since the commercially available discrete devices and power hybrid packages did not meet these requirements, a power transistor module was developed which performed satisfactorily. By connecting 13 power transistors in parallel, with due consideration for network and heat dissipation problems, and by driving these 13 with another power transistor, a super power transistor is made, having an equivalent current, power, and safe operating area capability of 13 transistors. For higher capabilities, additional modules can be conveniently added. (auth)

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates

Directory of Open Access Journals (Sweden)

Kornelius Tetzner

2014-10-01

Full Text Available In this work, the insulating properties of poly(4-vinylphenol (PVP and SU-8 (MicroChem, Westborough, MA, USA dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

Science.gov (United States)

Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

2014-01-01

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

Analysing organic transistors based on interface approximation

International Nuclear Information System (INIS)

Akiyama, Yuto; Mori, Takehiko

2014-01-01

Temperature-dependent characteristics of organic transistors are analysed thoroughly using interface approximation. In contrast to amorphous silicon transistors, it is characteristic of organic transistors that the accumulation layer is concentrated on the first monolayer, and it is appropriate to consider interface charge rather than band bending. On the basis of this model, observed characteristics of hexamethylenetetrathiafulvalene (HMTTF) and dibenzotetrathiafulvalene (DBTTF) transistors with various surface treatments are analysed, and the trap distribution is extracted. In turn, starting from a simple exponential distribution, we can reproduce the temperature-dependent transistor characteristics as well as the gate voltage dependence of the activation energy, so we can investigate various aspects of organic transistors self-consistently under the interface approximation. Small deviation from such an ideal transistor operation is discussed assuming the presence of an energetically discrete trap level, which leads to a hump in the transfer characteristics. The contact resistance is estimated by measuring the transfer characteristics up to the linear region

Doping effect on monolayer MoS2 for visible light dye degradation - A DFT study

Science.gov (United States)

Cheriyan, Silpa; Balamurgan, D.; Sriram, S.

2018-04-01

The electronic and optical properties of, Nitrogen (N), Cobalt (Co), and Co-N co-doped monolayers of MoS2 has been studied by using density functional theory (DFT) for visible light photocatalytic activity. From the calculations, it has been observed that the band gap of monolayer MoS2 has been reduced while doping. However, the band gaps of pristine and N doped MoS2 monolayers only falls in the visible region while for Co and Co-N co-doped systems, the band gap shifted to IR region. The optical calculation also confirms the results. The formation energy values of the doped system reaveal that MoS2 monolayer drops its stability while doping. To evaluate the photocatalytic response, band edge potentials of pristine and N-MoS2 are calculated, and the observed results show that compared to N-doped MoS2 monolayer, pure MoS2 is highly suitable for visible light photocatalytic dye degradation.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

International Nuclear Information System (INIS)

Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

2016-01-01

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

Energy Technology Data Exchange (ETDEWEB)

Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2016-08-30

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Distributed amplifier using Josephson vortex flow transistors

International Nuclear Information System (INIS)

McGinnis, D.P.; Beyer, J.B.; Nordman, J.E.

1986-01-01

A wide-band traveling wave amplifier using vortex flow transistors is proposed. A vortex flow transistor is a long Josephson junction used as a current controlled voltage source. The dual nature of this device to the field effect transistor is exploited. A circuit model of this device is proposed and a distributed amplifier utilizing 50 vortex flow transistors is predicted to have useful gain to 100 GHz

Photosensitive graphene transistors.

Science.gov (United States)

Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

2014-08-20

High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Degradation of Au–Ti contacts of SiGe HBTs during electromagnetic field stress

International Nuclear Information System (INIS)

Alaeddine, A; Genevois, C; Cuvilly, F; Daoud, K; Kadi, M

2011-01-01

This paper addresses electromagnetic field stress effects on SiGe heterojunction bipolar transistors (HBTs)' reliability issues, focusing on the relationship between the stress-induced current and device structure degradations. The origin of leakage currents and electrical parameter shifts in failed transistors has been studied by complementary failure analysis techniques. Characterization of the structure before and after ageing was performed by transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS). For the stressed samples, interface deformations of the titanium (Ti) thin film around all gold (Au) contacts have been clearly detected. These degradations include localized interface reaction between Au and Ti layers as well as their lateral atomic migration causing a significant reduction of Ti thickness. EDS analysis of the disordered region which is near the Si 3 N 4 interface has shown significant signals from Au. These observations could be attributed to the coupling between high current densities induced by stress and thermal effects due to local heating effects

Understanding mobility degeneration mechanism in organic thin-film transistors (OTFT)

Science.gov (United States)

Wang, Wei; Wang, Long; Xu, Guangwei; Gao, Nan; Wang, Lingfei; Ji, Zhuoyu; Lu, Congyan; Lu, Nianduan; Li, Ling; Liu, Miwng

2017-08-01

Mobility degradation at high gate bias is often observed in organic thin film transistors. We propose a mechanism for this confusing phenomenon, based on the percolation theory with the presence of disordered energy landscape with an exponential density of states. Within a simple model we show how the surface states at insulator/organic interface trap a portion of channel carriers, and result in decrease of mobility as well as source/drain current with gate voltage. Depending on the competition between the carrier accumulation and surface trapping effect, two different carrier density dependences of mobility are obtained, in excellent agreement with experiment data.

Gold nanoparticle-pentacene memory-transistors

OpenAIRE

Novembre , Christophe; Guerin , David; Lmimouni , Kamal; Gamrat , Christian; Vuillaume , Dominique

2008-01-01

We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off sta...

Numerical analysis of band tails in nanowires and their effects on the performance of tunneling field-effect transistors

Science.gov (United States)

Tanaka, Takahisa; Uchida, Ken

2018-06-01

Band tails in heavily doped semiconductors are one of the important parameters that determine transfer characteristics of tunneling field-effect transistors. In this study, doping concentration and doing profile dependences of band tails in heavily doped Si nanowires were analyzed by a nonequilibrium Green function method. From the calculated band tails, transfer characteristics of nanowire tunnel field-effect transistors were numerically analyzed by Wentzel–Kramer–Brillouin approximation with exponential barriers. The calculated transfer characteristics demonstrate that the band tails induced by dopants degrade the subthreshold slopes of Si nanowires from 5 to 56 mV/dec in the worst case. On the other hand, surface doping leads to a high drain current while maintaining a small subthreshold slope.

The Complete Semiconductor Transistor and Its Incomplete Forms

International Nuclear Information System (INIS)

Jie Binbin; Sah, C.-T.

2009-01-01

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

Evaluation of Enhanced Low Dose Rate Sensitivity in Discrete Bipolar Junction Transistors

Science.gov (United States)

Chen, Dakai; Ladbury Raymond; LaBel, Kenneth; Topper, Alyson; Ladbury, Raymond; Triggs, Brian; Kazmakites, Tony

2012-01-01

We evaluate the low dose rate sensitivity in several families of discrete bipolar transistors across device parameter, quality assurance level, and irradiation bias configuration. The 2N2222 showed the most significant low dose rate sensitivity, with low dose rate enhancement factor of 3.91 after 100 krad(Si). The 2N2907 also showed critical degradation levels. The devices irradiated at 10 mrad(Si)/s exceeded specifications after 40 and 50 krad(Si) for the 2N2222 and 2N2907 devices, respectively.

A study on the degradation mechanism of InGaZnO thin-film transistors under simultaneous gate and drain bias stresses based on the electronic trap characterization

International Nuclear Information System (INIS)

Jeong, Chan-Yong; Lee, Daeun; Song, Sang-Hun; Kwon, Hyuck-In; Kim, Jong In; Lee, Jong-Ho

2014-01-01

We discuss the device degradation mechanism of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses based on the electronic trap characterization results. The transfer curve exhibits an apparent negative shift as the stress time increases, and a formation of hump is observed in the transfer curve after stresses. A notable increase of the frequency dispersion is observed after stresses in both gate-to-drain capacitance–voltage (C GD –V G ) and gate-to-source capacitance–voltage (C GS –V G ) curves, which implies that the subgap states are generated by simultaneous gate and drain bias stresses, and the damaged location is not limited to the drain side of TFTs. The larger frequency dispersion is observed in C GD –V G  curves after stresses in a wider channel device, which implies that the heat is an important factor in the generation of the subgap states under simultaneous gate and drain bias stresses in a-IGZO TFTs. Based on the electronic trap characterization results, we conclude that the impact ionization near the drain side of the device is not a dominant mechanism causing the generation of subgap states and device degradation in a-IGZO TFTs under simultaneous gate and drain bias stresses. The generation of oxygen vacancy-related donor-like traps near the conduction band edge is considered as a possible mechanism causing the device degradation under simultaneous gate and drain bias stresses in a-IGZO TFTs. (paper)

SPICE modelling of the transient response of irradiated MOSFETs; Modelisation de la reponse transitoire de MOSFETs irradies avec SPICE

Energy Technology Data Exchange (ETDEWEB)

Pouget, V.; Lapuyade, H.; Lewis, D.; Deval, Y.; Fouillat, P. [Bordeaux-1 Univ., IXL, 33 - Talence (France); Sarger, L. [Bordeaux-1 Univ., CPMOH, 33 - Talence (France)

1999-07-01

A new SPICE model of irradiated MOSFET taking into account the real response of the 4 electrodes is proposed. The component that has been simulated is an NMOS transistor issued from the AMS BiCMOS 0.8 {mu}m technology. A comparison between SPICE-generated transients and PISCES device simulation demonstrates the accuracy benefits when used in complex electronic architectures. This model could be used when designing electronic circuits able to sustain hardening due to SEE (single event effect), it will be an efficient complement to the physical simulations.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

Science.gov (United States)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

International Nuclear Information System (INIS)

Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

2016-01-01

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

Ultrasensitive label-free detection of DNA hybridization by sapphire-based graphene field-effect transistor biosensor

Science.gov (United States)

Xu, Shicai; Jiang, Shouzhen; Zhang, Chao; Yue, Weiwei; Zou, Yan; Wang, Guiying; Liu, Huilan; Zhang, Xiumei; Li, Mingzhen; Zhu, Zhanshou; Wang, Jihua

2018-01-01

Graphene has attracted much attention in biosensing applications for its unique properties. Because of one-atom layer structure, every atom of graphene is exposed to the environment, making the electronic properties of graphene are very sensitive to charged analytes. Therefore, graphene is an ideal material for transistors in high-performance sensors. Chemical vapor deposition (CVD) method has been demonstrated the most successful method for fabricating large area graphene. However, the conventional CVD methods can only grow graphene on metallic substrate and the graphene has to be transferred to the insulating substrate for further device fabrication. The transfer process creates wrinkles, cracks, or tears on the graphene, which severely degrade electrical properties of graphene. These factors severely degrade the sensing performance of graphene. Here, we directly fabricated graphene on sapphire substrate by high temperature CVD without the use of metal catalysts. The sapphire-based graphene was patterned and make into a DNA biosensor in the configuration of field-effect transistor. The sensors show high performance and achieve the DNA detection sensitivity as low as 100 fM (10-13 M), which is at least 10 times lower than prior transferred CVD G-FET DNA sensors. The use of the sapphire-based G-FETs suggests a promising future for biosensing applications.

Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

DEFF Research Database (Denmark)

Igor, Mucha

1997-01-01

A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe degradat......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...... degradation of the performance of the circuit and without the need for a repeating programming. In this way the noise originating from any resistance previously used for the definition of the operating point is avoided completely and, moreover, by avoiding the input high-pass filter both the saturation...

A novel Tunneling Graphene Nano Ribbon Field Effect Transistor with dual material gate: Numerical studies

Science.gov (United States)

Ghoreishi, Seyed Saleh; Saghafi, Kamyar; Yousefi, Reza; Moravvej-farshi, Mohammad Kazem

2016-09-01

In this work, we present Dual Material Gate Tunneling Graphene Nano-Ribbon Field Effect Transistors (DMG-T-GNRFET) mainly to suppress the am-bipolar current with assumption that sub-threshold swing which is one of the important characteristics of tunneling transistors must not be degraded. In the proposed structure, dual material gates with different work functions are used. Our investigations are based on numerical simulations which self-consistently solves the 2D Poisson based on an atomistic mode-space approach and Schrodinger equations, within the Non-Equilibrium Green's (NEGF). The proposed device shows lower off-current and on-off ratio becomes 5order of magnitude greater than the conventional device. Also two different short channel effects: Drain Induced Barrier Shortening (DIBS) and hot-electron effect are improved in the proposed device compare to the main structure.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Ultra-high gain diffusion-driven organic transistor

Science.gov (United States)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

High-Performance Vertical Organic Electrochemical Transistors.

Science.gov (United States)

Donahue, Mary J; Williamson, Adam; Strakosas, Xenofon; Friedlein, Jacob T; McLeod, Robert R; Gleskova, Helena; Malliaras, George G

2018-02-01

Organic electrochemical transistors (OECTs) are promising transducers for biointerfacing due to their high transconductance, biocompatibility, and availability in a variety of form factors. Most OECTs reported to date, however, utilize rather large channels, limiting the transistor performance and resulting in a low transistor density. This is typically a consequence of limitations associated with traditional fabrication methods and with 2D substrates. Here, the fabrication and characterization of OECTs with vertically stacked contacts, which overcome these limitations, is reported. The resulting vertical transistors exhibit a reduced footprint, increased intrinsic transconductance of up to 57 mS, and a geometry-normalized transconductance of 814 S m -1 . The fabrication process is straightforward and compatible with sensitive organic materials, and allows exceptional control over the transistor channel length. This novel 3D fabrication method is particularly suited for applications where high density is needed, such as in implantable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electrical instability of a-Si:H/SiN thin film transistors : a study at room temperature and low voltage stress

NARCIS (Netherlands)

Merticaru, A.R.

2004-01-01

The thesis shows the results of four years of research into the electrical stability of a-Si:H/SiN TFTs. Various methods of investigation of a-Si:H/SiN TFTs have been carried out in this thesis towards understanding the causes of degradation that shortens the transistor lifetime and narrows the

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

Recent progress in photoactive organic field-effect transistors.

Science.gov (United States)

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

Recent progress in photoactive organic field-effect transistors

International Nuclear Information System (INIS)

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-01-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts. (review)

Programmable automated transistor test system

International Nuclear Information System (INIS)

Truong, L.V.; Sundberg, G.R.

1986-01-01

The paper describes a programmable automated transistor test system (PATTS) and its utilization to evaluate bipolar transistors and Darlingtons, and such MOSFET and special types as can be accommodated with the PATTS base-drive. An application of a pulsed power technique at low duty cycles in a non-destructive test is used to examine the dynamic switching characteristic curves of power transistors. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software. In addition a library of test data is established on disks, tapes, and hard copies for future reference

Universal power transistor base drive control unit

Science.gov (United States)

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Graphene field effect transistor without an energy gap.

Science.gov (United States)

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Low-background transistors for application in nuclear electronics

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

Investigations of silicon transistors were carried out to determine transistors with low value of base distributed resistance (R). Measurement results for R and current amplification coefficient β are presented for bipolar transistor several types. Correlations between R and β were studied. KT 399A, 2T640A and KT3117B transistors are found to be most adequate ones as a base for low-background amplifier development

Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures

International Nuclear Information System (INIS)

Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Chen, Te-Chih; Hsieh, Tien-Yu; Chen, Yu-Te; Tsai, Wu-Wei; Chiang, Wen-Jen; Yan, Jing-Yi

2013-01-01

This letter studies the hot-carrier effect in indium–gallium–zinc oxide (IGZO) thin film transistors with symmetric and asymmetric source/drain structures. The different degradation behaviors after hot-carrier stress in symmetric and asymmetric source/drain devices indicate that different mechanisms dominate the degradation. Since the C–V measurement is highly sensitive to trap states compared to the I–V characterization, C–V curves are utilized to analyze the hot-carrier stress-induced trap state generation. Furthermore, the asymmetric C–V measurements C GD (gate-to-drain capacitance) and C GS (gate-to-source capacitance) are used to analyze the trap state in channel location. The asymmetric source/drain structure under hot-carrier stress induces an asymmetric electrical field and causes different degradation behaviors. In this work, the on-current and subthreshold swing (S.S.) degrade under low electrical field, whereas an apparent V t shift occurs under large electrical field. The different degradation behaviors indicate that trap states are generated under a low electrical field and the channel-hot-electron (CHE) effect occurs under a large electrical field. - Highlights: ► Asymmetric structure thin film transistors improve kick-back effect. ► Asymmetric structures under hot-carrier stress induce different degradation. ► Hot-carrier stress leads to capacitance–voltage curve distortion. ► Extra trap states are generated during hot-carrier stress

A wideband CMOS inductorless low noise amplifier employing noise cancellation for digital TV tuner applications

International Nuclear Information System (INIS)

Zhang Jihong; Bai Xuefei; Huang Lu

2013-01-01

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2–15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point (IP1dB) is − 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5 × 0.35 mm 2 . (semiconductor integrated circuits)

Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeOx/Al2O3 gate dielectrics

International Nuclear Information System (INIS)

Wang, Xiaolei; Xiang, Jinjuan; Wang, Shengkai; Wang, Wenwu; Zhao, Chao; Ye, Tianchun; Xiong, Yuhua; Zhang, Jing

2016-01-01

Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal–oxide–semiconductor field-effect-transistors (MOSFETs) with GeO x /Al 2 O 3 gate stacks. It is found that the mobility increases with greater GeO x thickness (7.8–20.8 Å). The physical origin of this mobility dependence on GeO x thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeO x /Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeO x /Al 2 O 3 gate stacks are evaluated experimentally. The bulk charges in Al 2 O 3 and GeO x are found to be negligible. The density of the interfacial charge is  +3.2  ×  10 12 cm −2 at the GeO x /Ge interface and  −2.3  ×  10 12 cm −2 at the Al 2 O 3 /GeO x interface. The electric dipole at the Al 2 O 3 /GeO x interface is found to be  +0.15 V, which corresponds to an areal charge density of 1.9  ×  10 13 cm −2 . The origin of this mobility dependence on GeO x thickness is attributed to the RCS due to the electric dipole at the Al 2 O 3 /GeO x interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al 2 O 3 /GeO x interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement. (paper)

Planar-Processed Polymer Transistors.

Science.gov (United States)

Xu, Yong; Sun, Huabin; Shin, Eul-Yong; Lin, Yen-Fu; Li, Wenwu; Noh, Yong-Young

2016-10-01

Planar-processed polymer transistors are proposed where the effective charge injection and the split unipolar charge transport are all on the top surface of the polymer film, showing ideal device characteristics with unparalleled performance. This technique provides a great solution to the problem of fabrication limitations, the ambiguous operating principle, and the performance improvements in practical applications of conjugated-polymer transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Basic matrix algebra and transistor circuits

CERN Document Server

Zelinger, G

1963-01-01

Basic Matrix Algebra and Transistor Circuits deals with mastering the techniques of matrix algebra for application in transistors. This book attempts to unify fundamental subjects, such as matrix algebra, four-terminal network theory, transistor equivalent circuits, and pertinent design matters. Part I of this book focuses on basic matrix algebra of four-terminal networks, with descriptions of the different systems of matrices. This part also discusses both simple and complex network configurations and their associated transmission. This discussion is followed by the alternative methods of de

Graphene-based flexible and stretchable thin film transistors.

Science.gov (United States)

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

Science.gov (United States)

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

High Accuracy Transistor Compact Model Calibrations

Energy Technology Data Exchange (ETDEWEB)

Hembree, Charles E. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Mar, Alan [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Robertson, Perry J. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirements require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.

Ultrasmall transistor-based light sources

DEFF Research Database (Denmark)

With Jensen, Per Baunegaard; Tavares, Luciana; Kjelstrup-Hansen, Jakob

Dette projekt fokuserer på at udvikle transistor baserede nanofiber lyskilder med det overordnede mål at udvikle effektive og nano skalerede flerfarvede lyskilder integreret on-chip.......Dette projekt fokuserer på at udvikle transistor baserede nanofiber lyskilder med det overordnede mål at udvikle effektive og nano skalerede flerfarvede lyskilder integreret on-chip....

Impact of graphene polycrystallinity on the performance of graphene field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Jiménez, David; Chaves, Ferney [Departament d' Enginyeria Electrònica, Escola d' Enginyeria, Universitat Autònoma de Barcelona, 08193-Bellaterra (Spain); Cummings, Aron W.; Van Tuan, Dinh [ICN2, Institut Català de Nanociencia i Nanotecnologia, Campus UAB, 08193 Bellaterra (Barcelona) (Spain); Kotakoski, Jani [Faculty of Physics, University of Vienna, Boltzmanngasse 5, 1090 Wien (Austria); Department of Physics, University of Helsinki, P.O. Box 43, 00014 University of Helsinki (Finland); Roche, Stephan [ICN2, Institut Català de Nanociencia i Nanotecnologia, Campus UAB, 08193 Bellaterra (Barcelona) (Spain); ICREA, Institució Catalana de Recerca i Estudis Avançats, 08070 Barcelona (Spain)

2014-01-27

We have used a multi-scale physics-based model to predict how the grain size and different grain boundary morphologies of polycrystalline graphene will impact the performance metrics of graphene field-effect transistors. We show that polycrystallinity has a negative impact on the transconductance, which translates to a severe degradation of the maximum and cutoff frequencies. On the other hand, polycrystallinity has a positive impact on current saturation, and a negligible effect on the intrinsic gain. These results reveal the complex role played by graphene grain boundaries and can be used to guide the further development and optimization of graphene-based electronic devices.

Impact of graphene polycrystallinity on the performance of graphene field-effect transistors

International Nuclear Information System (INIS)

Jiménez, David; Chaves, Ferney; Cummings, Aron W.; Van Tuan, Dinh; Kotakoski, Jani; Roche, Stephan

2014-01-01

We have used a multi-scale physics-based model to predict how the grain size and different grain boundary morphologies of polycrystalline graphene will impact the performance metrics of graphene field-effect transistors. We show that polycrystallinity has a negative impact on the transconductance, which translates to a severe degradation of the maximum and cutoff frequencies. On the other hand, polycrystallinity has a positive impact on current saturation, and a negligible effect on the intrinsic gain. These results reveal the complex role played by graphene grain boundaries and can be used to guide the further development and optimization of graphene-based electronic devices

High temperature study of flexible silicon-on-insulator fin field-effect transistors

KAUST Repository

Diab, Amer El Hajj

2014-09-29

We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

Molecular materials for organic field-effect transistors

International Nuclear Information System (INIS)

Mori, T

2008-01-01

Organic field-effect transistors are important applications of thin films of molecular materials. A variety of materials have been explored for improving the performance of organic transistors. The materials are conventionally classified as p-channel and n-channel, but not only the performance but also even the carrier polarity is greatly dependent on the combinations of organic semiconductors and electrode materials. In this review, particular emphasis is laid on multi-sulfur compounds such as tetrathiafulvalenes and metal dithiolates. These compounds are components of highly conducting materials such as organic superconductors, but are also used in organic transistors. The charge-transfer complexes are used in organic transistors as active layers as well as electrodes. (topical review)

Multiple-channel detection of cellular activities by ion-sensitive transistors

Science.gov (United States)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

Photon-gated spin transistor

OpenAIRE

Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

2017-01-01

Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

Organic Thin-Film Transistor (OTFT-Based Sensors

Directory of Open Access Journals (Sweden)

Daniel Elkington

2014-04-01

Full Text Available Organic thin film transistors have been a popular research topic in recent decades and have found applications from flexible displays to disposable sensors. In this review, we present an overview of some notable articles reporting sensing applications for organic transistors with a focus on the most recent publications. In particular, we concentrate on three main types of organic transistor-based sensors: biosensors, pressure sensors and “e-nose”/vapour sensors.

Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeO x /Al2O3 gate dielectrics

Science.gov (United States)

Wang, Xiaolei; Xiang, Jinjuan; Wang, Shengkai; Wang, Wenwu; Zhao, Chao; Ye, Tianchun; Xiong, Yuhua; Zhang, Jing

2016-06-01

Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal-oxide-semiconductor field-effect-transistors (MOSFETs) with GeO x /Al2O3 gate stacks. It is found that the mobility increases with greater GeO x thickness (7.8-20.8 Å). The physical origin of this mobility dependence on GeO x thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeO x /Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeO x /Al2O3 gate stacks are evaluated experimentally. The bulk charges in Al2O3 and GeO x are found to be negligible. The density of the interfacial charge is  +3.2  ×  1012 cm-2 at the GeO x /Ge interface and  -2.3  ×  1012 cm-2 at the Al2O3/GeO x interface. The electric dipole at the Al2O3/GeO x interface is found to be  +0.15 V, which corresponds to an areal charge density of 1.9  ×  1013 cm-2. The origin of this mobility dependence on GeO x thickness is attributed to the RCS due to the electric dipole at the Al2O3/GeO x interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al2O3/GeO x interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement.

Capas de SiGe policristalino hidrogenado y su aplicación en transistores de película delgada

Directory of Open Access Journals (Sweden)

Rodríguez, A.

2004-04-01

Full Text Available The hydrogenation of polycrystalline SiGe layers, obtained by solid phase crystallization, by an electron ciclotron resonance hydrogen plasma and the influence of this hydrogenation process on the electrical characteristics of thin film transistors fabricated using this material as active layer have been studied. The hydrogenation processes were carried out at 150 and 250 ºC for several times, up to 11 hours. Infrared transmission spectra of these samples show only the absorption bands corresponding to Si-H bonds, indicating that hydrogen atoms are bonded mainly to silicon atoms. Ultraviolet reflectance measurements show that the surface damage caused by the plasma exposure increases as the Ge content of the film does. The transistors fabricated using polycrystalline SiGe films as active layer show a degradation phenomenon, consisting of a progressive decrease of the drain current at constant gate and drain bias. The degradation slows down as the hydrogenation time increases at constant temperature.

En este trabajo se ha caracterizado el proceso de hidrogenación en un plasma generado por resonancia ciclotrónica de electrones de capas de SiGe policristalino obtenidas mediante cristalización en fase sólida y el efecto de la hidrogenación en las características eléctricas de transistores de película delgada fabricados usando dicho material. Los procesos de hidrogenación se realizaron a 150 y 250 ºC, con duraciones de hasta 11 horas. Los espectros de transmitancia en infrarrojo muestran solamente las bandas de absorción características de los enlaces Si-H. Estas bandas indican que el hidrógeno se incorpora al material enlazándose principalmente con los átomos de silicio. Las medidas de reflectancia en el ultravioleta indican que se crea daño en la superficie de la muestra y que éste aumenta a medida que lo hace el contenido en Ge. Los transistores de película delgada con capa activa de SiGe policristalino muestran un fen

Doped organic transistors operating in the inversion and depletion regime

Science.gov (United States)

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Implementation of Self-Bias Transistor on Voting Logic

International Nuclear Information System (INIS)

Harzawardi Hasim; Syirrazie Che Soh

2014-01-01

Study in the eld of digital integrated circuit (IC) already become common to the modern industrial. Day by day we have been introduced with new gadget that was developed based on transistor. This paper will study the implementation of self-bias transistor on voting logic. The self-bias transistor will connected both on pull-up network and pull-down network. On previous research, study on comparison of total number of transistors, time propagation delay, and frequency between NAND and NOR gate of voting logic. It's show, with the same number of transistor, NAND gate achieve high frequency and low time propagation delay compare to NOR gate. We extend this analysis by comparing the total number of transistor, time propagation delay, frequency and power dissipation between common NAND gate with self-bias NAND gate. Extensive LTSpice simulations were performed using IBM 90 nm CMOS(Complementary Metal Oxide Semiconductor) process technology. The result show self-bias voting NAND gate consumes 54 % less power dissipation, 43% slow frequency and 43 % high time propagation delay compare to common voting NAND gate. (author)

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Science.gov (United States)

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Efficient simulation of power MOS transistors

NARCIS (Netherlands)

Ugryumova, M.; Schilders, W.H.A.

2011-01-01

In this report we present a few industrial problems related to modeling of MOS transistors. We suggest an efficient algorithm for computing output current at the top ports of power MOS transistors for given voltage excitations. The suggested algorithm exploits the connection between the resistor and

Thermal transistor utilizing gas-liquid transition

KAUST Repository

Komatsu, Teruhisa S.

2011-01-25

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter. © 2011 American Physical Society.

Water-gel for gating graphene transistors.

Science.gov (United States)

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Transistor reset preamplifier for high-rate high-resolution spectroscopy

International Nuclear Information System (INIS)

Landis, D.A.; Cork, C.P.; Madden, N.W.; Goulding, F.S.

1981-10-01

Pulsed transistor reset of high resolution charge sensitive preamplifiers used in cooled semiconductor spectrometers can sometimes have an advantage over pulsed light reset systems. Several versions of transistor reset spectrometers using both silicon and germanium detectors have been built. This paper discusses the advantages of the transistor reset system and illustrates several configurations of the packages used for the FET and reset transistor. It also describes the preamplifer circuit and shows the performance of the spectrometer at high rates

Protonic transistors from thin reflecting films

Energy Technology Data Exchange (ETDEWEB)

Ordinario, David D.; Phan, Long; Jocson, Jonah-Micah [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Nguyen, Tam [Department of Chemistry, University of California, Irvine, California 92697 (United States); Gorodetsky, Alon A., E-mail: alon.gorodetsky@uci.edu [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Department of Chemistry, University of California, Irvine, California 92697 (United States)

2015-01-01

Ionic transistors from organic and biological materials hold great promise for bioelectronics applications. Thus, much research effort has focused on optimizing the performance of these devices. Herein, we experimentally validate a straightforward strategy for enhancing the high to low current ratios of protein-based protonic transistors. Upon reducing the thickness of the transistors’ active layers, we increase their high to low current ratios 2-fold while leaving the other figures of merit unchanged. The measured ratio of 3.3 is comparable to the best values found for analogous devices. These findings underscore the importance of the active layer geometry for optimum protonic transistor functionality.

High mobility and quantum well transistors design and TCAD simulation

CERN Document Server

Hellings, Geert

2013-01-01

For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Qu...

Junction depth measurement using carrier illumination

International Nuclear Information System (INIS)

Borden, Peter

2001-01-01

Carrier Illumination [trade mark] (CI) is a new method recently developed to meet the need for a non-destructive, high throughput junction depth measurement on patterned wafers. A laser beam creates a quasi-static excess carrier profile in the semiconductor underlying the activated junction. The excess carrier profile is fairly constant below the junction, and drops rapidly in the junction, creating a steep index of refraction gradient at the junction edge. Interference with light reflected from this index gradient provides a signal that is analyzed to determine the junction depth. The paper summarizes evaluation of performance in full NMOS and PMOS process flows, on both bare and patterned wafers. The aims have been to validate (1) performance in the presence of underlying layers typically found at the source/drain (S/D) process steps and (2) measurement on patterned wafers. Correlation of CI measurements to SIMS and transistor drive current are shown. The data were obtained from NMOS structures using As S/D and LDD implants. Correlations to SRP, SIMS and sheet resistance are shown for PMOS structures using B 11 LDD implants. Gage capability measurements are also presented

Performance Enhancement of Power Transistors and Radiation effect

International Nuclear Information System (INIS)

Hassn, Th.A.A.

2012-01-01

The main objective of this scientific research is studying the characteristic of bipolar junction transistor device and its performance under radiation fields and temperature effect as a control element in many power circuits. In this work we present the results of experimental measurements and analytical simulation of gamma – radiation effects on the electrical characteristics and operation of power transistor types 2N3773, 2N3055(as complementary silicon power transistor are designed for general-purpose switching and amplifier applications), three samples of each type were irradiated by gamma radiation with doses, 1 K rad, 5 K rad, 10 K rad, 30 K rad, and 10 Mrad, the experimental data are utilized to establish an analytical relation between the total absorbed dose of gamma irradiation and corresponding to effective density of generated charge in the internal structure of transistor, the electrical parameters which can be measured to estimate the generated defects in the power transistor are current gain, collector current and collected emitter leakage current , these changes cause the circuit to case proper functioning. Collector current and transconductance of each device are calibrated as a function of irradiated dose. Also the threshold voltage and transistor gain can be affected and also calibrated as a function of dose. A silicon NPN power transistor type 2N3773 intended for general purpose applications, were used in this work. It was designed for medium current and high power circuits. Performance and characteristic were discusses under temperature and gamma radiation doses. Also the internal junction thermal system of the transistor represented in terms of a junction thermal resistance (Rjth). The thermal resistance changed by ΔRjth, due to the external intended, also due to the gamma doses intended. The final result from the model analysis reveals that the emitter-bias configuration is quite stable by resistance ratio RB/RE. Also the current

Progressive degradation in a-Si: H/SiN thin film transistors

NARCIS (Netherlands)

Merticaru, A.R.; Mouthaan, A.J.; Kuper, F.G.

2003-01-01

In this paper we present the study of gate-stress induced degradation in a-Si:H/SiN TFTs. The drain current transient during gate bias stress (forward or reverse bias) and subsequent relaxation cannot be fitted with the models existent in the literature but it shows to be described by a progressive

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Outlook and emerging semiconducting materials for ambipolar transistors.

Science.gov (United States)

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

Science.gov (United States)

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

International Nuclear Information System (INIS)

Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

1990-01-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

GaN transistors for efficient power conversion

CERN Document Server

Lidow, Alex; de Rooij, Michael; Reusch, David

2014-01-01

The first edition of GaN Transistors for Efficient Power Conversion was self-published by EPC in 2012, and is currently the only other book to discuss GaN transistor technology and specific applications for the technology. More than 1,200 copies of the first edition have been sold through Amazon or distributed to selected university professors, students and potential customers, and a simplified Chinese translation is also available. The second edition has expanded emphasis on applications for GaN transistors and design considerations. This textbook provides technical and application-focused i

Application of the Johnson criteria to graphene transistors

International Nuclear Information System (INIS)

Kelly, M J

2013-01-01

For 60 years, the Johnson criteria have guided the development of materials and the materials choices for field-effect and bipolar transistor technology. Intrinsic graphene is a semi-metal, precluding transistor applications, but only under lateral bias is a gap opened and transistor action possible. This first application of the Johnson criteria to biased graphene suggests that this material will struggle to ever achieve competitive commercial applications. (fast track communication)

Design method for a digitally trimmable MOS transistor structure

DEFF Research Database (Denmark)

Ning, Feng; Bruun, Erik

1996-01-01

A digitally trimmable MOS transistor is a MOS transistor consisting of a drain, a source, and a main gate as well as several subgates. The transconductance of the transistor is tunabledigitally by means of connecting subgates either to the main gate or to the source terminal. In this paper, a sys...

Selective epitaxial growth of monolithically integrated GaN-based light emitting diodes with AlGaN/GaN driving transistors

International Nuclear Information System (INIS)

Liu, Zhaojun; Ma, Jun; Huang, Tongde; Liu, Chao; May Lau, Kei

2014-01-01

In this Letter, we report selective epitaxial growth of monolithically integrated GaN-based light emitting diodes (LEDs) with AlGaN/GaN high-electron-mobility transistor (HEMT) drivers. A comparison of two integration schemes, selective epitaxial removal (SER), and selective epitaxial growth (SEG) was made. We found the SER resulted in serious degradation of the underlying LEDs in a HEMT-on-LED structure due to damage of the p-GaN surface. The problem was circumvented using the SEG that avoided plasma etching and minimized device degradation. The integrated HEMT-LEDs by SEG exhibited comparable characteristics as unintegrated devices and emitted modulated blue light by gate biasing

Electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous InGaZnO thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Her, Jim-Long [Division of Natural Science, Center for General Education, Chang Gung University, Taoyuan 333, Taiwan (China); Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Liu, Jiang-Hung; Wang, Hong-Jun; Chen, Ching-Hung [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Koyama, Keiichi [Graduate School of Science and Engineering, Kagoshima University, Kagoshima 890-0065 (Japan)

2014-10-31

In this article, we studied the structural properties and electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) applications. The a-IGZO TFT device featuring the GdTiO{sub 3} gate dielectric exhibited better electrical characteristics, including a small threshold voltage of 0.14 V, a large field-effect mobility of 32.3 cm{sup 2}/V-s, a high I{sub on}/I{sub off} current ratio of 4.2 × 10{sup 8}, and a low subthreshold swing of 213 mV/decade. Furthermore, the electrical instability of GdTiO{sub 3} a-IGZO TFTs was investigated under both positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS) conditions. The electron charge trapping in the gate dielectric dominates the PGBS degradation, while the oxygen vacancies control the NGBS degradation. - Highlights: • Indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) • Structural and electrical properties of the GdTiO{sub 3} film were studied. • a-IGZO TFT featuring GdTi{sub x}O{sub y} dielectric exhibited better electrical characteristics. • TFT instability investigated under positive and negative gate-bias stress conditions.

A nanoscale piezoelectric transformer for low-voltage transistors.

Science.gov (United States)

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Problems of noise modeling in the presence of total current branching in high electron mobility transistor and field-effect transistor channels

International Nuclear Information System (INIS)

Shiktorov, P; Starikov, E; Gružinskis, V; Varani, L; Sabatini, G; Marinchio, H; Reggiani, L

2009-01-01

In the framework of analytical and hydrodynamic models for the description of carrier transport and noise in high electron mobility transistor/field-effect transistor channels the main features of the intrinsic noise of transistors are investigated under continuous branching of the current between channel and gate. It is shown that the current-noise and voltage-noise spectra at the transistor terminals contain an excess noise related to thermal excitation of plasma wave modes in the dielectric layer between the channel and gate. It is found that the set of modes of excited plasma waves can be governed by the external embedding circuits, thus violating a universal description of noise in terms of Norton and Thevenin noise generators

Magnetic Vortex Based Transistor Operations

Science.gov (United States)

Kumar, D.; Barman, S.; Barman, A.

2014-01-01

Transistors constitute the backbone of modern day electronics. Since their advent, researchers have been seeking ways to make smaller and more efficient transistors. Here, we demonstrate a sustained amplification of magnetic vortex core gyration in coupled two and three vortices by controlling their relative core polarities. This amplification is mediated by a cascade of antivortex solitons travelling through the dynamic stray field. We further demonstrated that the amplification can be controlled by switching the polarity of the middle vortex in a three vortex sequence and the gain can be controlled by the input signal amplitude. An attempt to show fan–out operation yielded gain for one of the symmetrically placed branches which can be reversed by switching the core polarity of all the vortices in the network. The above observations promote the magnetic vortices as suitable candidates to work as stable bipolar junction transistors (BJT). PMID:24531235

Transistor challenges - A DRAM perspective

International Nuclear Information System (INIS)

Faul, Juergen W.; Henke, Dietmar

2005-01-01

Key challenges of the transistor scaling from a DRAM perspective will be reviewed. Both, array transistors as well as DRAM support devices face challenges that differ essentially from high performance logic device scaling. As a major difference, retention time and standby current requirements characterize special boundary conditions in the DRAM device design. Array device scaling is determined by a chip size driven aggressive node scaling. To continue scaling, major innovations need to be introduced into state-of-the-art planar array transistors. Alternatively, non planar device concepts will have to be evaluated. Support device design for DRAMs is driven by today's market demand for increased chip performances at little to no extra cost. Major innovations are required to continue that path. Besides this strive for performance increase, special limitations for 'on pitch' circuits at the array edge will come up due to the aggressive cell size scaling

Liquid crystals for organic transistors (Conference Presentation)

Science.gov (United States)

Hanna, Jun-ichi; Iino, Hiroaki

2016-09-01

Liquid crystals are a new type of organic semiconductors exhibiting molecular orientation in self-organizing manner, and have high potential for device applications. In fact, various device applications have been proposed so far, including photosensors, solar cells, light emitting diodes, field effect transistors, and so on.. However, device performance in those fabricated with liquid crystals is less than those of devices fabricated with conventional materials in spite of unique features of liquid crystals. Here we discuss how we can utilize the liquid crystallinity in organic transistors and how we can overcome conventional non-liquid crystalline organic transistor materials. Then, we demonstrate high performance organic transistors fabricated with a smectic E liquid crystal of Ph-BTBT-10, which show high mobility of over 10cm2/Vs and high thermal durability of over 200oC in OFETs fabricated with its spin-coated polycrystalline thin films.

A New Method for Negative Bias Temperature Instability Assessment in P-Channel Metal Oxide Semiconductor Transistors

Science.gov (United States)

Djezzar, Boualem; Tahi, Hakim; Benabdelmoumene, Abdelmadjid; Chenouf, Amel; Kribes, Youcef

2012-11-01

In this paper, we present a new method, named on the fly oxide trap (OTFOT), to extract the bias temperature instability (BTI) in MOS transistors. The OTFOT method is based on charge pumping technique (CP) at low and high frequencies. We emphasize on the theoretical-based concept, giving a clear insight on the easy-use of the OTFOT methodology and demonstrating its viability to characterize the negative BTI (NBTI). Using alternatively high and low frequencies, OTFOT method separates the interface-traps (ΔNit) and border-trap (ΔNbt) (switching oxide-trap) densities independently and also their contributions to the threshold voltage shift (ΔVth), without needing additional methods. The experimental results, from two experimental scenarios, showing the extraction of NBTI-induced shifts caused by interface- and oxide-trap increases are also presented. In the first scenario, all stresses are performed on the same transistor. It exhibits an artifact value of exponent n. In the second scenario, each voltage stress is applied only on one transistor. Its results show an average n of 0.16, 0.05, and 0.11 for NBTI-induced ΔNit, ΔNbt, ΔVth, respectively. Therefore, OTFOT method can contribute to further understand the behavior of the NBTI degradation, especially through the threshold voltage shift components such as ΔVit and ΔVot caused by interface-trap and border-trap, respectively.

Large magnetocurrents in double-barrier tunneling transistors

International Nuclear Information System (INIS)

Lee, J.H.; Jun, K.-I.; Shin, K.-H.; Park, S.Y.; Hong, J.K.; Rhie, K.; Lee, B.C.

2005-01-01

Magnetic tunneling transistors (MTT) with double tunneling barriers are fabricated. The structure of the transistor is AFM/FM/I/FM/I/FM/AFM, and ferromagnetic layers serve as the emitter, base and collector. This double-barrier tunneling transistor (DBTT) has an advantage of controlling the potential between the base and collector, compared to the Schottky-barrier-based base and collector of MTT. We found that the collector current density of DBTT is at least 10 3 times larger than that of conventional MTT, since tunneling through AlO x barrier provides much larger current density than that through Schottky barrier

Ambipolar organic tri-gate transistor for low-power complementary electronics

NARCIS (Netherlands)

Torricelli, F.; Ghittorelli, M.; Smits, E.C.P.; Roelofs, C.; Janssen, R.A.J.; Gelinck, G.H.; Kovács-Vajna, Z.M.; Cantatore, E.

2016-01-01

Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics

Stretchable transistors with buckled carbon nanotube films as conducting channels

Science.gov (United States)

Arnold, Michael S; Xu, Feng

2015-03-24

Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

Metal nanoparticle film-based room temperature Coulomb transistor.

Science.gov (United States)

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

Low-frequency noise in single electron tunneling transistor

DEFF Research Database (Denmark)

Tavkhelidze, A.N.; Mygind, Jesper

1998-01-01

The noise in current biased aluminium single electron tunneling (SET) transistors has been investigated in the frequency range of 5 mHz ..., we find the same input charge noise, typically QN = 5 × 10–4 e/Hz1/2 at 10 Hz, with and without the HF shielding. At lower frequencies, the noise is due to charge trapping, and the voltage noise pattern superimposed on the V(Vg) curve (voltage across transistor versus gate voltage) strongly depends...... when ramping the junction voltage. Dynamic trapping may limit the high frequency applications of the SET transistor. Also reported on are the effects of rf irradiation and the dependence of the SET transistor noise on bias voltage. ©1998 American Institute of Physics....

Uniformity of fully gravure printed organic field-effect transistors

International Nuclear Information System (INIS)

Hambsch, M.; Reuter, K.; Stanel, M.; Schmidt, G.; Kempa, H.; Fuegmann, U.; Hahn, U.; Huebler, A.C.

2010-01-01

Fully mass-printed organic field-effect transistors were made completely by means of gravure printing. Therefore a special printing layout was developed in order to avoid register problems in print direction. Upon using this layout, contact pads for source-drain electrodes of the transistors are printed together with the gate electrodes in one and the same printing run. More than 50,000 transistors have been produced and by random tests a yield of approximately 75% has been determined. The principle suitability of the gravure printed transistors for integrated circuits has been shown by the realization of ring oscillators.

Theory and application of dual-transistor charge separation analysis

International Nuclear Information System (INIS)

Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Sexton, F.W.; Shaneyfelt, M.R.

1989-01-01

The authors describe a dual-transistor charge separation method to evaluate the radiation response of MOS transistors. This method requires that n- and p-channel transistors with identically processed oxides be irradiated under identical conditions at the same oxide electric fields. Combining features of single-transistor midgap and mobility methods, the authors show how one may determine threshold voltage shifts due to oxide-trapped and interface-trapped charge from standard threshold voltage and mobility measurements. These measurements can be made at currents 2-5 orders of magnitude higher than those required for midgap, subthreshold slope, and charge-pumping methods. The dual-transistor method contains no adjustable parameters, and includes an internal self-consistency check. The accuracy of the method is verified by comparison to midgap, subthreshold slope, and charge-pumping methods for several MOS processes and technologies

Organic electrochemical transistors

KAUST Repository

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Ró isí n M.; Berggren, Magnus; Malliaras, George G.

2018-01-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume

Self-Consistent Study of Conjugated Aromatic Molecular Transistors

International Nuclear Information System (INIS)

Jing, Wang; Yun-Ye, Liang; Hao, Chen; Peng, Wang; Note, R.; Mizuseki, H.; Kawazoe, Y.

2010-01-01

We study the current through conjugated aromatic molecular transistors modulated by a transverse field. The self-consistent calculation is realized with density function theory through the standard quantum chemistry software Gaussian03 and the non-equilibrium Green's function formalism. The calculated I – V curves controlled by the transverse field present the characteristics of different organic molecular transistors, the transverse field effect of which is improved by the substitutions of nitrogen atoms or fluorine atoms. On the other hand, the asymmetry of molecular configurations to the axis connecting two sulfur atoms is in favor of realizing the transverse field modulation. Suitably designed conjugated aromatic molecular transistors possess different I – V characteristics, some of them are similar to those of metal-oxide-semiconductor field-effect transistors (MOSFET). Some of the calculated molecular devices may work as elements in graphene electronics. Our results present the richness and flexibility of molecular transistors, which describe the colorful prospect of next generation devices. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

The Smallest Transistor-Based Nonautonomous Chaotic Circuit

DEFF Research Database (Denmark)

Lindberg, Erik; Murali, K.; Tamasevicius, Arunas

2005-01-01

A nonautonomous chaotic circuit based on one transistor, two capacitors, and two resistors is described. The mechanism behind the chaotic performance is based on “disturbance of integration.” The forward part and the reverse part of the bipolar transistor are “fighting” about the charging...

High mobility polymer gated organic field effect transistor using zinc ...

Indian Academy of Sciences (India)

Organic thin film transistors were fabricated using evaporated zinc phthalocyanine as the active layer. Parylene film ... At room temperature, these transistors exhibit p-type conductivity with field-effect ... Keywords. Organic semiconductor; field effect transistor; phthalocyanine; high mobility. ... The evaporation rate was kept at ...

A transimpedance amplifier using a novel current mode feedback loop

CERN Document Server

Anghinolfi, Francis; Delagnes, E; Jarron, Pierre; Scharfetter, L H H

1995-01-01

We present a transimpedance amplifier stage based on a novel current mode feedback topology. This circuit employs NMOS and PMOS transistors exclusively and requires neither capacitor for stabilizing the transimpedance loop nor resistor for the transresistance feedback and transistor loading. This amplifier circuit is fully compatible with submicron digital CMOS processes. The active feedback network consists of two grounded-gate MOS devices which split the output current in both the feedback and output branches. The transresistance and the phase margin are adjustable through external DC signals. The measured rise time of the impulse response of the amplifier implemented in an industrial 0,7µm CMOS process is 18 ns for a transresistance of 180 k‡ and 30 ns for a transresistance of 560 k‡. The measured Equivalent Noise Charge (ENC) is 800 rms e¯ for an input capacitance of 20 pF with the transresistance adjusted to 560 k‡.

The use of 2N3055 transistor as photosensory in solarymeter

International Nuclear Information System (INIS)

Bintoro; Sastroamidjojo, M.S.A.

1981-01-01

The characteristics of 2N3055 type transistor used for solarymeters sensor. It can be seen that transistor sensor has more response time. The response to against arrival solar intensity is linear. It can be used for solarymeter sensor after calibrated with pyranometer reference, but not so sensitive for 500 nanometer wavelength. It can be concluded that 2N3055 transistor made by Motrola than the made by R.C.A. because the 2N3055 transistor is more wide and more accurate than the R.C.A. transistor. (author tr.)

N-type organic electrochemical transistors with stability in water

KAUST Repository

Giovannitti, Alexander

2016-10-07

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurements in water show no degradation when tested for 2 h under continuous cycling. This demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.

N-type organic electrochemical transistors with stability in water

KAUST Repository

Giovannitti, Alexander; Nielsen, Christian B.; Sbircea, Dan-Tiberiu; Inal, Sahika; Donahue, Mary; Niazi, Muhammad Rizwan; Hanifi, David A.; Amassian, Aram; Malliaras, George G.; Rivnay, Jonathan; McCulloch, Iain

2016-01-01

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurements in water show no degradation when tested for 2 h under continuous cycling. This demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.

Improvements in or relating to transistor circuits

International Nuclear Information System (INIS)

Richards, R.F.; Williamson, P.W.

1978-01-01

This invention relates to transistor circuits and in particular to integrated transistor circuits formed on a substrate of semi-conductor material such as silicon. The invention is concerned with providing integrated circuits in which malfunctions caused by the effects of ionising, e.g. nuclear, radiations are reduced. (author)

Enhanced transconductance in a double-gate graphene field-effect transistor

Science.gov (United States)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Modeling of charge transport in ion bipolar junction transistors.

Science.gov (United States)

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Metal nanoparticle film–based room temperature Coulomb transistor

Science.gov (United States)

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-01-01

Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

Large scale electromechanical transistor with application in mass sensing

Energy Technology Data Exchange (ETDEWEB)

Jin, Leisheng; Li, Lijie, E-mail: L.Li@swansea.ac.uk [Multidisciplinary Nanotechnology Centre, College of Engineering, Swansea University, Swansea SA2 8PP (United Kingdom)

2014-12-07

Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to be used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.

Tunneling field effect transistor technology

CERN Document Server

Chan, Mansun

2016-01-01

This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs.

Performance regeneration of InGaZnO transistors with ultra-thin channels

Energy Technology Data Exchange (ETDEWEB)

Zhang, Binglei; Li, He; Zhang, Xijian, E-mail: zhangxijian@sdu.edu.cn, E-mail: songam@sdu.edu.cn; Luo, Yi; Wang, Qingpu [School of Physics, Shandong University, Jinan 250100 (China); Song, Aimin, E-mail: zhangxijian@sdu.edu.cn, E-mail: songam@sdu.edu.cn [School of Physics, Shandong University, Jinan 250100 (China); School of Electrical and Electronic Engineering, University of Manchester, Manchester M13 9PL (United Kingdom)

2015-03-02

Thin-film transistors (TFTs) based on ultra-thin amorphous indium gallium zinc oxide (a-IGZO) semiconductors down to 4 nm were studied motivated by the increasing cost of indium. At and below 5 nm, it was found that the field-effect mobility was severely degraded, the threshold voltage increased, and the output characteristics became abnormal showing no saturated current. By encapsulating a layer of polymethyl methacrylate on the IGZO TFTs, the performance of the 5-nm-thick device was effectively recovered. The devices also showed much higher on/off ratios, improved hysteresis, and normal output characteristic curves as compared with devices not encapsulated. The stability of the encapsulated devices was also studied over a four month period.

Organic semiconductors for organic field-effect transistors

International Nuclear Information System (INIS)

Yamashita, Yoshiro

2009-01-01

The advantages of organic field-effect transistors (OFETs), such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed. (topical review)

Transistors using crystalline silicon devices on glass

Science.gov (United States)

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Organic semiconductors for organic field-effect transistors

Directory of Open Access Journals (Sweden)

Yoshiro Yamashita

2009-01-01

Full Text Available The advantages of organic field-effect transistors (OFETs, such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed.

Simulaci??n y modelado de transistores MOS de doble puerta

OpenAIRE

Cartujo Cassinello, Pedro

2000-01-01

En este trabajo se hace un estudio del transistor MOS de doble puerta analizando las posibles ventajas de esta nueva estructura frene al transistor convencional y el transistor MOS SOI de puerta simple. Para ello se ha analizado una secci??n transversal de un transistor MOS de doble puerta de canal N, con el fin de examinar detalladamente las peculiaridades de la distribuci??n de electrones con una amplia variedad de valores de todos los par??mentros tecnol??gicos y condiciones de operaci??n,...

Radiation effect on silicon transistors in mixed neutrons-gamma environment

Science.gov (United States)

Assaf, J.; Shweikani, R.; Ghazi, N.

2014-10-01

The effects of gamma and neutron irradiations on two different types of transistors, Junction Field Effect Transistor (JFET) and Bipolar Junction Transistor (BJT), were investigated. Irradiation was performed using a Syrian research reactor (RR) (Miniature Neutron Source Reactor (MNSR)) and a gamma source (Co-60 cell). For RR irradiation, MCNP code was used to calculate the absorbed dose received by the transistors. The experimental results showed an overall decrease in the gain factors of the transistors after irradiation, and the JFETs were more resistant to the effects of radiation than BJTs. The effect of RR irradiation was also greater than that of gamma source for the same dose, which could be because neutrons could cause more damage than gamma irradiation.

I2 basal stacking fault as a degradation mechanism in reverse gate-biased AlGaN/GaN HEMTs

Science.gov (United States)

Lang, A. C.; Hart, J. L.; Wen, J. G.; Miller, D. J.; Meyer, D. J.; Taheri, M. L.

2016-09-01

Here, we present the observation of a bias-induced, degradation-enhancing defect process in plasma-assisted molecular beam epitaxy grown reverse gate-biased AlGaN/GaN high electron mobility transistors (HEMTs), which is compatible with the current theoretical framework of HEMT degradation. Specifically, we utilize both conventional transmission electron microscopy and aberration-corrected transmission electron microscopy to analyze microstructural changes in not only high strained regions in degraded AlGaN/GaN HEMTs but also the extended gate-drain access region. We find a complex defect structure containing an I2 basal stacking fault and offer a potential mechanism for device degradation based on this defect structure. This work supports the reality of multiple failure mechanisms during device operation and identifies a defect potentially involved with device degradation.

Diffusion pipes at PNP switching transistors

International Nuclear Information System (INIS)

Sachelarie, D.; Postolache, C.; Gaiseanu, F.

1976-01-01

The appearance of the ''diffusion pipes'' greatly affects the fabrication of the PNP high-frequency/very-fast-switching transistors. A brief review of the principal problems connected to the presence of these ''pipes'' is made. A research program is presented which permitted the fabrication of the PNP switching transistors at ICCE-Bucharest, with transition frequency fsub(T) = 1.2 GHz and storage time tsub(s) = 4.5 ns. (author)

Integrated amplifying circuit with MOS transistors

Energy Technology Data Exchange (ETDEWEB)

Baylac, B; Merckel, G; Meunier, P

1974-01-25

The invention relates to a feedback-pass-band amplifier with MOS-transistors. The differential stage of conventional amplifiers is changed into an adding state, whereas the differential amplification stages are changed into amplifier inverter stages. All MOS transistors used in that amplifier are of similar configuration and are interdigitized, whereby the operating speed dispersion is reduced. This can be applied to obtaining a measurement channel for proportional chambers.

Programmable, automated transistor test system

Science.gov (United States)

Truong, L. V.; Sundburg, G. R.

1986-01-01

A programmable, automated transistor test system was built to supply experimental data on new and advanced power semiconductors. The data will be used for analytical models and by engineers in designing space and aircraft electric power systems. A pulsed power technique was used at low duty cycles in a nondestructive test to examine the dynamic switching characteristic curves of power transistors in the 500 to 1000 V, 10 to 100 A range. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software.

Subthreshold currents in CMOS transistors made on oxygen-implanted silicon

International Nuclear Information System (INIS)

Foster, D.J.

1983-01-01

Kinks have been observed in subthreshold current plots of mesa-shaped n-channel transistors made on oxygen-implanted silicon substrates. The kinks represent additional current flow and are due to overlapping fields from the gate electrode causing early corner inversion and to a Qsub(ss) side-wall effect. Subthreshold currents in n-channel transistors are dominated by the two effects which, as a consequence, reduce threshold voltages especially in narrow n-channel transistors. The subthreshold characteristics of p-channel transistors were not affected in the same way. (author)

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

Science.gov (United States)

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Vertically aligned carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi

2012-10-01

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been developed using pure semiconducting carbon nanotubes. The source and drain were vertically stacked, separated by a dielectric, and the carbon nanotubes were placed on the sidewall of the stack to bridge the source and drain. Both the effective gate dielectric and gate electrode were normal to the substrate surface. The channel length is determined by the dielectric thickness between source and drain electrodes, making it easier to fabricate sub-micrometer transistors without using time-consuming electron beam lithography. The transistor area is much smaller than the planar CNTFET due to the vertical arrangement of source and drain and the reduced channel area. © 2012 Elsevier Ltd. All rights reserved.

Transfer-free fabrication of graphene transistors

OpenAIRE

Wessely, P.J.; Wessely, F.; Birinci, E.; Schwalke, U.; Riedinger, B.

2012-01-01

The authors invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon, a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane-based growth process, monolayer graphene field-effect transistors and...

Single-event burnout of epitaxial bipolar transistors

Energy Technology Data Exchange (ETDEWEB)

Kuboyama, S.; Sugimoto, K.; Shugyo, S.; Matsuda, S. [National Space Development Agency of Japan, Tsukuba, Ibaraki (Japan); Hirao, T. [Japan Atomic Energy Research Inst., Takasaki, Gunma (Japan)

1998-12-01

Single-Event Burnout (SEB) of bipolar junction transistors (BJTs) has been observed nondestructively. It was revealed that all the NPN BJTs, including small signal transistors, with thinner epitaxial layers were inherently susceptible to the SEB phenomenon. It was demonstrated that several design parameters of BJTs were responsible for SEB susceptibility. Additionally, destructive and nondestructive modes of SEB were identified.

Group IV nanotube transistors for next generation ubiquitous computing

KAUST Repository

Fahad, Hossain M.

2014-06-04

Evolution in transistor technology from increasingly large power consuming single gate planar devices to energy efficient multiple gate non-planar ultra-narrow (< 20 nm) fins has enhanced the scaling trend to facilitate doubling performance. However, this performance gain happens at the expense of arraying multiple devices (fins) per operation bit, due to their ultra-narrow dimensions (width) originated limited number of charges to induce appreciable amount of drive current. Additionally arraying degrades device off-state leakage and increases short channel characteristics, resulting in reduced chip level energy-efficiency. In this paper, a novel nanotube device (NTFET) topology based on conventional group IV (Si, SiGe) channel materials is discussed. This device utilizes a core/shell dual gate strategy to capitalize on the volume-inversion properties of an ultra-thin (< 10 nm) group IV nanotube channel to minimize leakage and short channel effects while maximizing performance in an area-efficient manner. It is also shown that the NTFET is capable of providing a higher output drive performance per unit chip area than an array of gate-all-around nanowires, while maintaining the leakage and short channel characteristics similar to that of a single gate-all-around nanowire, the latter being the most superior in terms of electrostatic gate control. In the age of big data and the multitude of devices contributing to the internet of things, the NTFET offers a new transistor topology alternative with maximum benefits from performance-energy efficiency-functionality perspective. © (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Science.gov (United States)

Sengupta, Sarmista; Pandit, Soumya

2015-06-01

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

On the 50th Anniversary of the Transistor

DEFF Research Database (Denmark)

Stassen, Flemming

1997-01-01

This paper celebrates the 50th anniversary of the invention of the bipolar transistor in 1947. Combined with the inventions of integration and planar technology, the invention of the transistor marks the beginning of a period of unprecedented growth, the industrialization of electronics....

Organic electrochemical transistors

Science.gov (United States)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Organic electrochemical transistors

KAUST Repository

Rivnay, Jonathan

2018-01-16

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Magnetophoretic transistors in a tri-axial magnetic field.

Science.gov (United States)

Abedini-Nassab, Roozbeh; Joh, Daniel Y; Albarghouthi, Faris; Chilkoti, Ashutosh; Murdoch, David M; Yellen, Benjamin B

2016-10-18

The ability to direct and sort individual biological and non-biological particles into spatially addressable locations is fundamentally important to the emerging field of single cell biology. Towards this goal, we demonstrate a new class of magnetophoretic transistors, which can switch single magnetically labeled cells and magnetic beads between different paths in a microfluidic chamber. Compared with prior work on magnetophoretic transistors driven by a two-dimensional in-plane rotating field, the addition of a vertical magnetic field bias provides significant advantages in preventing the formation of particle clumps and in better replicating the operating principles of circuits in general. However, the three-dimensional driving field requires a complete redesign of the magnetic track geometry and switching electrodes. We have solved this problem by developing several types of transistor geometries which can switch particles between two different tracks by either presenting a local energy barrier or by repelling magnetic objects away from a given track, hereby denoted as "barrier" and "repulsion" transistors, respectively. For both types of transistors, we observe complete switching of magnetic objects with currents of ∼40 mA, which is consistent over a range of particle sizes (8-15 μm). The switching efficiency was also tested at various magnetic field strengths (50-90 Oe) and driving frequencies (0.1-0.6 Hz); however, we again found that the device performance only weakly depended on these parameters. These findings support the use of these novel transistor geometries to form circuit architectures in which cells can be placed in defined locations and retrieved on demand.

Simulation of a spintronic transistor: A study of its performance

International Nuclear Information System (INIS)

Pela, R.R.; Teles, L.K.

2009-01-01

We study theoretically the magnetic bipolar transistor, and compare its performance with common bipolar transistor. We present not only the simulation results for the characteristic curves, but also other relevant parameters related with its performance, such as: the current amplification factor, the open-loop gain, the hybrid parameters and the cutoff frequency. We noted that the spin-charge coupling introduces new phenomena that enrich the functionality characteristics of the magnetic bipolar transistor. Among other things, it has an adjustable band structure, which may be modified during the device operation; it exhibits the already known spin-voltaic effect. On the other hand, we observed that it is necessary a large g-factor to analyze the influence of the field B over the transistor. Nevertheless, we consider the magnetic bipolar transistor as a promising device for spintronic applications

Electrical pulse burnout of transistors in intense ionizing radiation

International Nuclear Information System (INIS)

Hartman, E.F.; Evans, D.C.

1975-01-01

Tests examining possible synergistic effects of electrical pulses and ionizing radiation on transistors were performed and energy/power thresholds for transistor burnout determined. The effect of ionizing radiation on burnout thresholds was found to be minimal, indicating that electrical pulse testing in the absence of radiation produces burnout-threshold results which are applicable to IEMP studies. The conditions of ionized transistor junctions and radiation induced current surges at semiconductor device terminals are inherent in IEMP studies of electrical circuits

The effect of various solvents on the back channel of solution-processed In-Ga-Zn-O thin-film transistors intended for biosensor applications

International Nuclear Information System (INIS)

Kim, Si Joon; Jung, Joohye; Yoon, Doo Hyun; Kim, Hyun Jae

2013-01-01

This study investigated the effects of exposing solution-processed In-Ga-Zn-O (IGZO) thin-film transistors (TFTs), intended for biosensor applications, to various solvents. Various solvents, such as the nonpolar solvent chlorobenzene and the polar solvents ethanol and deionized (DI) water, were dropped and adsorbed on exposed IGZO channel surfaces. All IGZO TFT devices exhibited a negative threshold voltage shift and a sub-threshold swing degradation, without an accompanying degradation in field-effect mobility. These variations depended on the dielectric constant of the solvents; with the exception of the IGZO TFT device exposed to DI water, they all gradually returned to their initial states.

Influence of 60Co gamma radiation on fluorine plasma treated enhancement-mode high-electron-mobility transistor

International Nuclear Information System (INIS)

Quan Si; Hao Yue; Ma Xiao-Hua; Yu Hui-You

2011-01-01

AlGaN/GaN depletion-mode high-electron-mobility transistor (D-HEMT) and fluorine (F) plasma treated enhancement-mode high-electron-mobility transistor (E-HEMT) are exposed to 60 Co gamma radiation with a dose of 1.6 Mrad (Si). No degradation is observed in the performance of D-HEMT. However, the maximum transconductance of E-HEMT is increased after radiation. The 2DEG density and the mobility are calculated from the results of capacitance-voltage measurement. The electron mobility decreases after fluorine plasma treatment and recovers after radiation. Conductance measurements in a frequency range from 10 kHz to 1 MHz are used to characterize the trapping effects in the devices. A new type of trap is observed in the F plasma treated E-HEMT compared with the D-HEMT, but the density of the trap decreases by radiation. Fitting of G p /ω data yields the trap densities D T = (1 − 3) × 10 12 cm −2 · eV −1 and D T = (0.2 − 0.8) × 10 12 cm −2 · eV −1 before and after radiation, respectively. The time constant is 0.5 ms-6 ms. With F plasma treatment, the trap is introduced by etch damage and degrades the electronic mobility. After 60 Co gamma radiation, the etch damage decreases and the electron mobility is improved. The gamma radiation can recover the etch damage caused by F plasma treatment. (interdisciplinary physics and related areas of science and technology)

Inexpensive Measuring System for the Characterization of Organic Transistors

Directory of Open Access Journals (Sweden)

Clara Pérez-Fuster

2018-01-01

Full Text Available A measuring module has been specifically designed for the electrical characterization of organic semiconductor devices such as organic field effect transistors (OFETs and organic electrochemical transistors (OECTs according to the IEEE 1620-2008 standard. This device has been tested with OFETs based on 6,13-bis(triisopropylsilylethinylpentacene (TIPS-pentacene. The measuring system has been constructed using a NI-PXIe-1073 chassis with integrated controller and two NI-PXI-4132 programmable high-precision source measure units (SMUs that offer a four-quadrant ± 100 V output, with resolution down to 10 pA. LabVIEW™ has been used to develop the appropriate program. Most of the main OFET parameters included in the IEEE 1620 standard can be measured by means of this device. Although nowadays expensive devices for the characterization of Si-based transistors are available, devices for the characterization of organic transistors are not yet widespread in the market. Fabrication of a specific and flexible module that can be used to characterize this type of transistors would provide a powerful tool to researchers.

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

Directory of Open Access Journals (Sweden)

Meng-Fang Lin

2015-01-01

Full Text Available The stable operation of transistors under a positive bias stress (PBS is achieved using Hf incorporated into InOx-based thin films processed at relatively low temperatures (150 to 250 °C. The mobilities of the Hf-InOx thin-film transistors (TFTs are higher than 8 cm2/Vs. The TFTs not only have negligible degradation in the mobility and a small shift in the threshold voltage under PBS for 60 h, but they are also thermally stable at 85 °C in air, without the need for a passivation layer. The Hf-InOx TFT can be stable even annealed at 150 °C for positive bias temperature stability (PBTS. A higher stability is achieved by annealing the TFTs at 250 °C, originating from a reduction in the trap density at the Hf-InOx/gate insulator interface. The knowledge obtained here will aid in the realization of stable TFTs processed at low temperatures.

Single-event burnout of epitaxial bipolar transistors

Energy Technology Data Exchange (ETDEWEB)

Kuboyama, Satoshi; Sugimoto, Kenji; Matsuda, Sumio [National Space Development Agency of Japan, Ysukuba, Ibaraki (Japan); Hirao, Toshio

1998-10-01

Single-event burnout (SEB) of bipolar junction transistors (BJTs) has been observed nondestructively. It was revealed that all the NPN BJTs including small signal transistors with thinner epitaxial layer were inherently susceptible to the SEB phenomenon. It was demonstrated that several design parameters of BJTs were responsible for SEB susceptibility. Additionally, destructive and nondestructive modes of SEB were identified. (author)

A Klein-tunneling transistor with ballistic graphene

Energy Technology Data Exchange (ETDEWEB)

Wilmart, Quentin; Fève, Gwendal; Berroir, Jean-Marc; Plaçais, Bernard [Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P et M Curie, Université D Diderot, 24, rue Lhomond, 75231 Paris Cedex 05 (France); Berrada, Salim; Hung Nguyen, V; Dollfus, Philippe [Institute of Fundamental Electronics, Univ. Paris-Sud, CNRS, Orsay (France); Torrin, David [Département de Physique, Ecole Polytechnique, 91128 Palaiseau (France)

2014-06-15

Today, the availability of high mobility graphene up to room temperature makes ballistic transport in nanodevices achievable. In particular, p-n-p transistors in the ballistic regime give access to Klein tunneling physics and allow the realization of devices exploiting the optics-like behavior of Dirac Fermions (DFs) as in the Veselago lens or the Fabry–Pérot cavity. Here we propose a Klein tunneling transistor based on the geometrical optics of DFs. We consider the case of a prismatic active region delimited by a triangular gate, where total internal reflection may occur, which leads to the tunable suppression of transistor transmission. We calculate the transmission and the current by means of scattering theory and the finite bias properties using non-equilibrium Green's function (NEGF) simulation. (letter)

Outlook and Emerging Semiconducting Materials for Ambipolar Transistors

NARCIS (Netherlands)

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great

Ambipolar charge transport in organic field-effect transistors

NARCIS (Netherlands)

Smits, E.C.P.; Anthopoulos, T.D.; Setayesh, S.; Veenendaal, van E.; Coehoorn, R.; Blom, P.W.M.; Boer, de B.; Leeuw, de D.M.

2006-01-01

A model describing charge transport in disordered ambipolar organic field-effect transistors is presented. The basis of this model is the variable-range hopping in an exponential density of states developed for disordered unipolar organic transistors. We show that the model can be used to calculate

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

Science.gov (United States)

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Low power fluorine plasma effects on electrical reliability of AlGaN/GaN high electron mobility transistor

International Nuclear Information System (INIS)

Yang Ling; Zhou Xiao-Wei; Ma Xiao-Hua; Lv Ling; Zhang Jin-Cheng; Hao Yue; Cao Yan-Rong

2017-01-01

The new electrical degradation phenomenon of the AlGaN/GaN high electron mobility transistor (HEMT) treated by low power fluorine plasma is discovered. The saturated current, on-resistance, threshold voltage, gate leakage and breakdown voltage show that each experiences a significant change in a short time stress, and then keeps unchangeable. The migration phenomenon of fluorine ions is further validated by the electron redistribution and breakdown voltage enhancement after off-state stress. These results suggest that the low power fluorine implant ion stays in an unstable state. It causes the electrical properties of AlGaN/GaN HEMT to present early degradation. A new migration and degradation mechanism of the low power fluorine implant ion under the off-stress electrical stress is proposed. The low power fluorine ions would drift at the beginning of the off-state stress, and then accumulate between gate and drain nearby the gate side. Due to the strong electronegativity of fluorine, the accumulation of the front fluorine ions would prevent the subsequent fluorine ions from drifting, thereby alleviating further the degradation of AlGaN/GaN HEMT electrical properties. (paper)

Very High Frequency Two-Port Characterization of Transistors

DEFF Research Database (Denmark)

Hertel, Jens Christian; Nour, Yasser; Jørgensen, Ivan Harald Holger

To properly use transistors in VHF converters, they need to be characterized under similar conditions. This research presents a two-port method, using a network analyzer (NWA) with a S-port setup. The method is a one-shot method, providing fast results of the off-state parasitics of the transistors....

High current transistor pulse generator

International Nuclear Information System (INIS)

Nesterov, V.; Cassel, R.

1991-05-01

A solid state pulse generator capable of delivering high current trapezoidally shaped pulses into an inductive load has been developed at SLAC. Energy stored in the capacitor bank of the pulse generator is switched to the load through a pair of Darlington transistors. A combination of diodes and Darlington transistors is used to obtain trapezoidal or triangular shaped current pulses into an inductive load and to recover the remaining energy in the same capacitor bank without reversing capacitor voltage. The transistors work in the switch mode, and the power losses are low. The rack mounted pulse generators presently used at SLAC contain a 660 microfarad storage capacitor bank and can deliver 400 amps at 800 volts into inductive loads up to 3 mH. The pulse generators are used in several different power systems, including pulse to pulse bipolar power supplies and in application with current pulses distributed into different inductive loads. The current amplitude and discharge time are controlled by the central computer system through a specially developed multichannel controller. Several years of operation with the pulse generators have proven their consistent performance and reliability. 8 figs

Simulación y modelado de transistores MOS de doble puerta

OpenAIRE

Cartujo Cassinello, Pedro

2013-01-01

En este trabajo se hace un estudio del transistor MOS de doble puerta analizando las posibles ventajas de esta nueva estructura frene al transistor convencional y el transistor MOS SOI de puerta simple. Para ello se ha analizado una sección transversal de un transistor MOS de doble puerta de canal N, con el fin de examinar detalladamente las peculiaridades de la distribución de electrones con una amplia variedad de valores de todos los parámentros tecnológicos y condiciones de operación, y se...

Transport Mechanisms in Organic Thin-Film Transistors

Science.gov (United States)

Fung, A. W. P.

1996-03-01

Recent success in fabricating field-effect transistors with polycrystalline α-sexithiophene (α-6T) has allowed us to study charge transport in this organic semiconductor. The appealing structural property that the oligomer chains are seated almost perpendicular to the substrate provides a model π-conjugated system which we find exhibits band transport at low temperatures. We observe a behavioral transition around 50K which is consistent with the metal-insulator transition in Holstein's small-polaron theory. The fact that we can observe intrinsic behavior means that the ambient-temperature mobility obtained in these transistors is optimal for α-6T. Agreement with the Holstein theory provides us with a prescription for rational design of materials for organic transistor applications. Work done in collaboration with L. Torsi, A. Dodabalapur, L. J. Rothberg and H. E. Katz.

A Klein-tunneling transistor with ballistic graphene

International Nuclear Information System (INIS)

Wilmart, Quentin; Fève, Gwendal; Berroir, Jean-Marc; Plaçais, Bernard; Berrada, Salim; Hung Nguyen, V; Dollfus, Philippe; Torrin, David

2014-01-01

Today, the availability of high mobility graphene up to room temperature makes ballistic transport in nanodevices achievable. In particular, p-n-p transistors in the ballistic regime give access to Klein tunneling physics and allow the realization of devices exploiting the optics-like behavior of Dirac Fermions (DFs) as in the Veselago lens or the Fabry–Pérot cavity. Here we propose a Klein tunneling transistor based on the geometrical optics of DFs. We consider the case of a prismatic active region delimited by a triangular gate, where total internal reflection may occur, which leads to the tunable suppression of transistor transmission. We calculate the transmission and the current by means of scattering theory and the finite bias properties using non-equilibrium Green's function (NEGF) simulation. (letter)

A spiking neuron circuit based on a carbon nanotube transistor

International Nuclear Information System (INIS)

Chen, C-L; Kim, K; Truong, Q; Shen, A; Li, Z; Chen, Y

2012-01-01

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions. (paper)

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

Science.gov (United States)

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Electric-stress reliability and current collapse of different thickness SiNx passivated AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Ling, Yang; Gui-Zhou, Hu; Yue, Hao; Xiao-Hua, Ma; Si, Quan; Li-Yuan, Yang; Shou-Gao, Jiang

2010-01-01

This paper investigates the impact of electrical degradation and current collapse on different thickness SiN x passivated AlGaN/GaN high electron mobility transistors. It finds that higher thickness SiN x passivation can significantly improve the high-electric-field reliability of a device. The degradation mechanism of the SiN x passivation layer under ON-state stress has also been discussed in detail. Under the ON-state stress, the strong electric-field led to degradation of SiN x passivation located in the gate-drain region. As the thickness of SiN x passivation increases, the density of the surface state will be increased to some extent. Meanwhile, it is found that the high NH 3 flow in the plasma enhanced chemical vapour deposition process could reduce the surface state and suppress the current collapse. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Tetracene-based organic light-emitting transistors: optoelectronic properties and electron injection mechanism

NARCIS (Netherlands)

Santato, C.; Capelli, R.; Loi, M.A.; Murgia, M.; Cicoira, F.; Roy, Arunesh; Stallinga, P; Zamboni, R.; Rost, C.; Karg, S.F.; Muccini, M.

2004-01-01

Optoelectronic properties of light-emitting field-effect transistors (LETs) fabricated on bottom-contact transistor structures using a tetracene film as charge-transport and light-emitting material are investigated. Electroluminescence generation and transistor current are correlated, and the bias

Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

International Nuclear Information System (INIS)

But, D. B.; Drexler, C.; Ganichev, S. D.; Sakhno, M. V.; Sizov, F. F.; Dyakonova, N.; Drachenko, O.; Gutin, A.; Knap, W.

2014-01-01

Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm 2 was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm 2 range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm 2 . The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ∼0.5 mW/cm 2 to ∼5 kW/cm 2 )

Failure rates for accelerated acceptance testing of silicon transistors

Science.gov (United States)

Toye, C. R.

1968-01-01

Extrapolation tables for the control of silicon transistor product reliability have been compiled. The tables are based on a version of the Arrhenius statistical relation and are intended to be used for low- and medium-power silicon transistors.

Electromechanical field effect transistors based on multilayer phosphorene nanoribbons

Energy Technology Data Exchange (ETDEWEB)

Jiang, Z.T., E-mail: jiangzhaotan@hotmail.com; Lv, Z.T.; Zhang, X.D.

2017-06-21

Based on the tight-binding Hamiltonian approach, we demonstrate that the electromechanical field effect transistors (FETs) can be realized by using the multilayer phosphorene nanoribbons (PNRs). The synergistic combination of the electric field and the external strains can establish the on–off switching since the electric field can shift or split the energy band, and the mechanical strains can widen or narrow the band widths. This kind of multilayer PNR FETs, much solider than the monolayer PNR one and more easily biased by different electric fields, has more transport channels consequently leading to the higher on–off current ratio or the higher sensitivity to the electric fields. Meanwhile, the strain-induced band-flattening will be beneficial for improving the flexibility in designing the electromechanical FETs. In addition, such electromechanical FETs can act as strain-controlled FETs or mechanical detectors for detecting the strains, indicating their potential applications in nano- and micro-electromechanical fields. - Highlights: • Electromechanical transistors are designed with multilayer phosphorene nanoribbons. • Electromechanical synergistic effect can establish the on–off switching more flexibly. • Multilayer transistors, solider and more easily biased, has more transport channels. • Electromechanical transistors can act as strain-controlled transistors or mechanical detectors.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

Science.gov (United States)

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Shikha Panwar

2014-01-01

Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

AlN/GaN heterostructures for normally-off transistors

Energy Technology Data Exchange (ETDEWEB)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.; Tereshenko, O. E. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation); Abgaryan, K. K.; Reviznikov, D. L. [Dorodnicyn Computing Centre of the Russian Academy of Sciences (Russian Federation); Zemlyakov, V. E.; Egorkin, V. I. [National Research University of Electronic Technology (MIET) (Russian Federation); Parnes, Ya. M.; Tikhomirov, V. G. [Joint Stock Company “Svetlana-Electronpribor” (Russian Federation); Prosvirin, I. P. [Russian Academy of Sciences, Boreskov Institute of Catalysis, Siberian Branch (Russian Federation)

2017-03-15

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

Science.gov (United States)

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Controlling the dimensionality of charge transport in organic thin-film transistors

Science.gov (United States)

Laiho, Ari; Herlogsson, Lars; Forchheimer, Robert; Crispin, Xavier; Berggren, Magnus

2011-01-01

Electrolyte-gated organic thin-film transistors (OTFTs) can offer a feasible platform for future flexible, large-area and low-cost electronic applications. These transistors can be divided into two groups on the basis of their operation mechanism: (i) field-effect transistors that switch fast but carry much less current than (ii) the electrochemical transistors which, on the contrary, switch slowly. An attractive approach would be to combine the benefits of the field-effect and the electrochemical transistors into one transistor that would both switch fast and carry high current densities. Here we report the development of a polyelectrolyte-gated OTFT based on conjugated polyelectrolytes, and we demonstrate that the OTFTs can be controllably operated either in the field-effect or the electrochemical regime. Moreover, we show that the extent of electrochemical doping can be restricted to a few monolayers of the conjugated polyelectrolyte film, which allows both high current densities and fast switching speeds at the same time. We propose an operation mechanism based on self-doping of the conjugated polyelectrolyte backbone by its ionic side groups. PMID:21876143

Nanometer size field effect transistors for terahertz detectors

International Nuclear Information System (INIS)

Knap, W; Rumyantsev, S; Coquillat, D; Dyakonova, N; Teppe, F; Vitiello, M S; Tredicucci, A; Blin, S; Shur, M; Nagatsuma, T

2013-01-01

Nanometer size field effect transistors can operate as efficient resonant or broadband terahertz detectors, mixers, phase shifters and frequency multipliers at frequencies far beyond their fundamental cut-off frequency. This work is an overview of some recent results concerning the application of nanometer scale field effect transistors for the detection of terahertz radiation. (paper)

Development and characterization of vertical double-gate MOS field-effect transistors

International Nuclear Information System (INIS)

Trellenkamp, S.

2004-07-01

Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)

Comparison of MOS capacitor and transistor postirradiation response

International Nuclear Information System (INIS)

McWhorter, P.J.; Fleetwood, D.M.; Pastorek, R.A.; Zimmerman, G.T.

1989-01-01

The postirradiation response of MOS capacitors and transistors fabricated on the same chip has been examined as a function of dose and anneal bias. A variety of analysis techniques are used to evaluate the postirradiation response of these structures, including low and high frequency capacitance-voltage techniques, subthreshold current-voltage techniques, and charge pumping. Though there are changes in the postirradiation energy spectrum of ΔD it , no clear evidence of defect transformation is observed on transistors or capacitors under any conditions examined. Postirradiation response at 80 degrees C is found to be similar in the two structures for low levels of damage (100 krad). For both structures, interface-trap densities continue to grow following irradiation under these conditions. In contrast, the postirradiation response of capacitors and transistors can differ qualitatively at higher levels of damage (1 Mrad), with interface-traps increasing postirradiation at 80 degrees C for transistors and annealing for capacitors. These results indicate that capacitor structures may not be suitable for hardness assurance studies that involve elevated temperature irradiations or postirradiation anneals

Switching Characteristics of Ferroelectric Transistor Inverters

Science.gov (United States)

Laws, Crystal; Mitchell, Coey; MacLeod, Todd C.; Ho, Fat D.

2010-01-01

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

Effect of initial material on the electrolytic parameters of field-effect transistors

International Nuclear Information System (INIS)

Antonov, A.V.; Sinitsyn, V.N.; Fursov, V.V.

1978-01-01

The effect of initial material parameters upon the main electric characteristics of field transistors at room and optimum (170 deg C) temperatures is studied. For that purpose, the values of parasitic resistances rsub(s), specific resistances rho and steepness S of field transistors, depending on temperature and electrical conditions were measured. The output volt-ampere characteristics of the transistors at room and optimum temperatures are given. An analysis of the results obtained permits to conclude that there is an unambiguous relationship between rho and rsub(s). Impact ionization is shown to occur for field transistors with lower rho at lower drain voltage. When manufacturing field transistors designed for operation at low temperatures, one should remember that a minimum rho may restrict maximum possible steepness. When designing field transistors with optimum noise characteristics, one should variate not only such material parameters as mobility and carrier density, but also select optimum geometry

Current-Induced Transistor Sensorics with Electrogenic Cells

Directory of Open Access Journals (Sweden)

Peter Fromherz

2016-04-01

Full Text Available The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned.

Technique of forecasting the working capacity of horizontal p-n-p transistor for a given radiation level; Metodika prognozirovaniya rabotosposobnosti gorizontal`nogo p-n-p tranzistora na zadannyj uroven` izlucheniya

Energy Technology Data Exchange (ETDEWEB)

Pershenkov, V S; Sevast` yanov, A V

1994-12-31

Methods of forecasting the degradation of horizontal p-n-p transistors under the effect of ionizing radiation based on the principles of invariant topological approach are presented. Results are presented and analysis of experimental investigations into the real test structures performed in the same process cycle as the integral circuit under development is given.

Planar transistors and impatt diodes with ion implantation

International Nuclear Information System (INIS)

Dorendorf, H.; Glawischnig, H.; Grasser, L.; Hammerschmitt, J.

1975-03-01

Low frequency planar npn and pnp transistors have been developed in which the base and emitter have been fabricated using ion implantation of boron and phosphorus by a drive-in diffusion. Electrical parameters of the transistors are comparable with conventionally produced transistors; the noise figure was improved and production tolerances were significantly reduced. Silicon-impatt diodes for the microwave range were also fabricated with implanted pn junctions and tested for their high frequency characteristics. These diodes, made in an improved upside down technology, delivered output power up to 40 mW (burn out power) at 30 GHz. Reverse leakage current and current carrying capability of these diodes were comparable to diffused structures. (orig.) 891 ORU 892 MB [de

Enchanced total dose damage in junction field effect transistors and related linear integrated circuits

International Nuclear Information System (INIS)

Flament, O.; Autran, J.L.; Roche, P.; Leray, J.L.; Musseau, O.

1996-01-01

Enhanced total dose damage of Junction Field-effect Transistors (JFETs) due to low dose rate and/or elevated temperature has been investigated for elementary p-channel structures fabricated on bulk and SOI substrates as well as for related linear integrated circuits. All these devices were fabricated with conventional junction isolation (field oxide). Large increases in damage have been revealed by performing high temperature and/or low dose rate irradiations. These results are consistent with previous studies concerning bipolar field oxides under low-field conditions. They suggest that the transport of radiation-induced holes through the oxide is the underlying mechanism. Such an enhanced degradation must be taken into account for low dose rate effects on linear integrated circuits

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

Science.gov (United States)

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Molecular thermal transistor: Dimension analysis and mechanism

Science.gov (United States)

Behnia, S.; Panahinia, R.

2018-04-01

Recently, large challenge has been spent to realize high efficient thermal transistors. Outstanding properties of DNA make it as an excellent nano material in future technologies. In this paper, we introduced a high efficient DNA based thermal transistor. The thermal transistor operates when the system shows an increase in the thermal flux despite of decreasing temperature gradient. This is what called as negative differential thermal resistance (NDTR). Based on multifractal analysis, we could distinguish regions with NDTR state from non-NDTR state. Moreover, Based on dimension spectrum of the system, it is detected that NDTR state is accompanied by ballistic transport regime. The generalized correlation sum (analogous to specific heat) shows that an irregular decrease in the specific heat induces an increase in the mean free path (mfp) of phonons. This leads to the occurrence of NDTR.

A III-V nanowire channel on silicon for high-performance vertical transistors.

Science.gov (United States)

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

p-i-n Homojunction in Organic Light-Emitting Transistors

NARCIS (Netherlands)

Bisri, Satria Zulkarnaen; Takenobu, Taishi; Sawabe, Kosuke; Tsuda, Satoshi; Yomogidao, Yohei; Yamao, Takeshi; Hotta, Shu; Adachi, Chihaya; Iwasa, Yoshihiro

2011-01-01

A new method for investigating light-emitting property in organic devices is demonstrated. We apply the ambipolar light-emitting transistors (LETS) to directly observe the recombination zone, and find a strong link between the transistor performance and the zone size. This finding unambiguously

The effect and mechanism of the bipolar junction transistor in different temperature

International Nuclear Information System (INIS)

Wang Dong; Lu Wu; Ren Diyuan; Li Aiwu; Kuang Zhibing

2007-01-01

The annealing-effect of bipolar junction transistor in different temperature is investigated. It is found that the anneal of the bipolar transistor is related to the annealing-temperature, and the annealing-effect of the different type transistor is dissimilar. The possible mechanism is discussed. (authors)

Development and Experimental Evaluation of an Automated Multi-Media Course on Transistors.

Science.gov (United States)

Whitted, J.H., Jr.; And Others

A completely automated multi-media self-study program for teaching a portion of electronic solid-state fundamentals was developed. The subject matter areas included were fundamental theory of transistors, transistor amplifier fundamentals, and simple mathematical analysis of transistors including equivalent circuits, parameters, and characteristic…

Field emission current from a junction field-effect transistor

International Nuclear Information System (INIS)

Monshipouri, Mahta; Abdi, Yaser

2015-01-01

Fabrication of a titanium dioxide/carbon nanotube (TiO 2 /CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO 2 nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO 2 /CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO 2 /CNT hetero-structure is also investigated, and well modeled

Radio frequency and linearity performance of transistors using high-purity semiconducting carbon nanotubes.

Science.gov (United States)

Wang, Chuan; Badmaev, Alexander; Jooyaie, Alborz; Bao, Mingqiang; Wang, Kang L; Galatsis, Kosmas; Zhou, Chongwu

2011-05-24

This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (f(t)) of 5 GHz and with maximum oscillation frequency (f(max)) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Label-free detection of DNA hybridization using transistors based on CVD grown graphene.

Science.gov (United States)

Chen, Tzu-Yin; Loan, Phan Thi Kim; Hsu, Chang-Lung; Lee, Yi-Hsien; Tse-Wei Wang, Jacob; Wei, Kung-Hwa; Lin, Cheng-Te; Li, Lain-Jong

2013-03-15

The high transconductance and low noise of graphene-based field-effect transistors based on large-area monolayer graphene produced by chemical vapor deposition are used for label-free electrical detection of DNA hybridization. The gate materials, buffer concentration and surface condition of graphene have been optimized to achieve the DNA detection sensitivity as low as 1 pM (10(-12) M), which is more sensitive than the existing report based on few-layer graphene. The graphene films obtained using conventional PMMA-assisted transfer technique exhibits PMMA residues, which degrade the sensing performance of graphene. We have demonstrated that the sensing performance of the graphene samples prepared by gold-transfer is largely enhanced (by 125%). Copyright © 2012 Elsevier B.V. All rights reserved.

Mesoscopic photon heat transistor

DEFF Research Database (Denmark)

Ojanen, T.; Jauho, Antti-Pekka

2008-01-01

We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir-Wingreen-Landauer-typ......We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir......-Wingreen-Landauer-type of conductance formula, which gives the photonic heat current through an arbitrary circuit element coupled to two dissipative reservoirs at finite temperatures. As an illustration we present an exact solution for the case when the intermediate circuit can be described as an electromagnetic resonator. We discuss...

Monolithic acoustic graphene transistors based on lithium niobate thin film

Science.gov (United States)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Calculation of comparators of analog-to-digital converters with account of electric regime of transistor operation and ionizing radiation effect; Raschet komparatov analogo-tsifrovykh preobrazovatelej s uchetom ehlektricheskogo rezhima raboty tranzistorov i vozdejstviya ioniziruyushchego izlucheniya

Energy Technology Data Exchange (ETDEWEB)

Ragozin, A Yu

1994-12-31

Zero shift voltage in comparators of analog-to-digital converters under gamma irradiation with regard to electric mode effect on bipolar transistor degradation is calculated. It is shown that the input range of comparators such weak units are represented by comparators of bipolar and lower grades.

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

Science.gov (United States)

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Dual-mode operation of 2D material-base hot electron transistors

KAUST Repository

Lan, Yann-Wen; Jr., Carlos M. Torres,; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R.; Lerner, Mitchell B.; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L.

2016-01-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (V-CB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (V-CB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Dual-mode operation of 2D material-base hot electron transistors

KAUST Repository

Lan, Yann-Wen

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (V-CB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (V-CB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Dual-mode operation of 2D material-base hot electron transistors.

Science.gov (United States)

Lan, Yann-Wen; Torres, Carlos M; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R; Lerner, Mitchell B; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

Science.gov (United States)

Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

2017-02-01

This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

Science.gov (United States)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Electrothermal Behavior of High-Frequency Silicon-On-Glass Transistors

NARCIS (Netherlands)

Nenadovic, N.

2004-01-01

In this thesis, research is focused on the investigation of electrothermal effects in high-speed silicon transistors. At high current levels the power dissipation in these devices can lead to heating of both the device itself and the adjacent devices. In advanced transistors these effects are

Controlling charge current through a DNA based molecular transistor

Energy Technology Data Exchange (ETDEWEB)

Behnia, S., E-mail: s.behnia@sci.uut.ac.ir; Fathizadeh, S.; Ziaei, J.

2017-01-05

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I–V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive. - Highlights: • Modeling a DNA based molecular transistor and studying its transport properties. • Choosing the appropriate DNA sequence using the quantum chaos tools. • Choosing the functional interval for voltages via the inverse participation ratio tool. • Detecting the rectifier and negative differential resistance behavior of DNA.

Field emission current from a junction field-effect transistor

Energy Technology Data Exchange (ETDEWEB)

Monshipouri, Mahta; Abdi, Yaser, E-mail: y.abdi@ut.ac.ir [University of Tehran, Nano-Physics Research Laboratory, Department of Physics (Iran, Islamic Republic of)

2015-04-15

Fabrication of a titanium dioxide/carbon nanotube (TiO{sub 2}/CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO{sub 2} nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO{sub 2}/CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO{sub 2}/CNT hetero-structure is also investigated, and well modeled.

Transport spectroscopy of coupled donors in silicon nano-transistors

Science.gov (United States)

Moraru, Daniel; Samanta, Arup; Anh, Le The; Mizuno, Takeshi; Mizuta, Hiroshi; Tabe, Michiharu

2014-01-01

The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed: dopant-atom-based transistors. So far, most studies report transport through dopants randomly located in the channel. However, for practical applications, it is critical to control the location of the donors with simple techniques. Here, we fabricate silicon transistors with selectively nanoscale-doped channels using nano-lithography and thermal-diffusion doping processes. Coupled phosphorus donors form a quantum dot with the ground state split into a number of levels practically equal to the number of coupled donors, when the number of donors is small. Tunneling-transport spectroscopy reveals fine features which can be correlated with the different numbers of donors inside the quantum dot, as also suggested by first-principles simulation results. PMID:25164032

Magnon transistor for all-magnon data processing.

Science.gov (United States)

Chumak, Andrii V; Serga, Alexander A; Hillebrands, Burkard

2014-08-21

An attractive direction in next-generation information processing is the development of systems employing particles or quasiparticles other than electrons--ideally with low dissipation--as information carriers. One such candidate is the magnon: the quasiparticle associated with the eigen-excitations of magnetic materials known as spin waves. The realization of single-chip all-magnon information systems demands the development of circuits in which magnon currents can be manipulated by magnons themselves. Using a magnonic crystal--an artificial magnetic material--to enhance nonlinear magnon-magnon interactions, we have succeeded in the realization of magnon-by-magnon control, and the development of a magnon transistor. We present a proof of concept three-terminal device fabricated from an electrically insulating magnetic material. We demonstrate that the density of magnons flowing from the transistor's source to its drain can be decreased three orders of magnitude by the injection of magnons into the transistor's gate.

Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters

Directory of Open Access Journals (Sweden)

Vytautas Bleizgys

2011-03-01

Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian

Transistor-based filter for inhibiting load noise from entering a power supply

Science.gov (United States)

Taubman, Matthew S

2013-07-02

A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

The dual role of multiple-transistor charge sharing collection in single-event transients

International Nuclear Information System (INIS)

Guo Yang; Chen Jian-Jun; He Yi-Bai; Liang Bin; Liu Bi-Wei

2013-01-01

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients (SETs) due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal—oxide semiconductor field-effect transistor (PMOS FET), but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies. (condensed matter: structural, mechanical, and thermal properties)

Transistor analogs of emergent iono-neuronal dynamics.

Science.gov (United States)

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

On the choice of a head element for low-noise bipolar transistor amplifier

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

The measurement results of equivalent noise charge (ENC) for KT382 transistor depending on detector capacity, formation duration and collector current are given. It is shown that the measurement results for this transistor in good agreement with calculations according to the noise model, time-consuming ENC measurements can be replaced by preliminary transistor rejection according to the distributed base resistance, current gain and simple calculations. In applications in the field of nuclear electronics the KT382 transistor enables to attain the same noise parameters as NE578, NE021 transistors (Japan) and it can be recommended for using as a head element of amplifiers

Transistor regenerative spectrometer for 14N nuclear quadrupole resonance study

International Nuclear Information System (INIS)

Anferov, V.P.; Mikhal'kov, V.M.

1981-01-01

Improvement of the Robinson transducer for investigations of nuclear quadrupole resonance (NQR) in 14 N is described. Amplifier of the suggested transducer is made using p-n field effect transistor and small-noise SHF bipolar transistor. Such a circuit permits to obtain optimal relation between input resistance, low-frequency noises and transconductance which provides uniform gain of the transducer in the frequency range of 0.6-12 MHz and permits to construct a transistor spectrometer of NQR not yielding to a lamp spectrometer in sensitivity [ru

Junctionless Cooper pair transistor

Energy Technology Data Exchange (ETDEWEB)

Arutyunov, K. Yu., E-mail: konstantin.yu.arutyunov@jyu.fi [National Research University Higher School of Economics , Moscow Institute of Electronics and Mathematics, 101000 Moscow (Russian Federation); P.L. Kapitza Institute for Physical Problems RAS , Moscow 119334 (Russian Federation); Lehtinen, J.S. [VTT Technical Research Centre of Finland Ltd., Centre for Metrology MIKES, P.O. Box 1000, FI-02044 VTT (Finland)

2017-02-15

Highlights: • Junctionless Cooper pair box. • Quantum phase slips. • Coulomb blockade and gate modulation of the Coulomb gap. - Abstract: Quantum phase slip (QPS) is the topological singularity of the complex order parameter of a quasi-one-dimensional superconductor: momentary zeroing of the modulus and simultaneous 'slip' of the phase by ±2π. The QPS event(s) are the dynamic equivalent of tunneling through a conventional Josephson junction containing static in space and time weak link(s). Here we demonstrate the operation of a superconducting single electron transistor (Cooper pair transistor) without any tunnel junctions. Instead a pair of thin superconducting titanium wires in QPS regime was used. The current–voltage characteristics demonstrate the clear Coulomb blockade with magnitude of the Coulomb gap modulated by the gate potential. The Coulomb blockade disappears above the critical temperature, and at low temperatures can be suppressed by strong magnetic field.

Imperceptible and Ultraflexible p-Type Transistors and Macroelectronics Based on Carbon Nanotubes.

Science.gov (United States)

Cao, Xuan; Cao, Yu; Zhou, Chongwu

2016-01-26

Flexible thin-film transistors based on semiconducting single-wall carbon nanotubes are promising for flexible digital circuits, artificial skins, radio frequency devices, active-matrix-based displays, and sensors due to the outstanding electrical properties and intrinsic mechanical strength of carbon nanotubes. Nevertheless, previous research effort only led to nanotube thin-film transistors with the smallest bending radius down to 1 mm. In this paper, we have realized the full potential of carbon nanotubes by making ultraflexible and imperceptible p-type transistors and circuits with a bending radius down to 40 μm. In addition, the resulted transistors show mobility up to 12.04 cm(2) V(-1) S(-1), high on-off ratio (∼10(6)), ultralight weight (transistors and circuits have great potential to work as indispensable components for ultraflexible complementary electronics.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

Science.gov (United States)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-08-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Optimizing switching frequency of the soliton transistor by numerical simulation

Energy Technology Data Exchange (ETDEWEB)

Izadyar, S., E-mail: S_izadyar@yahoo.co [Department of Electronics, Khaje Nasir Toosi University of Technology, Shariati Ave., Tehran (Iran, Islamic Republic of); Niazzadeh, M.; Raissi, F. [Department of Electronics, Khaje Nasir Toosi University of Technology, Shariati Ave., Tehran (Iran, Islamic Republic of)

2009-10-15

In this paper, by numerical simulations we have examined different ways to increase the soliton transistor's switching frequency. Speed of the solitons in a soliton transistor depends on various parameters such as the loss of the junction, the applied bias current, and the transmission line characteristics. Three different ways have been examined; (i) decreasing the size of the transistor without losing transistor effect. (ii) Decreasing the amount of loss of the junction to increase the soliton speed. (iii) Optimizing the bias current to obtain maximum possible speed. We have obtained the shortest possible length to have at least one working soliton inside the transistor. The dimension of the soliton can be decreased by changing the inductance of the transmission line, causing a further decrease in the size of the transistor, however, a trade off between the size and the inductance is needed to obtain the optimum switching speed. Decreasing the amount of loss can be accomplished by increasing the characteristic tunneling resistance of the device, however, a trade off is again needed to make soliton and antisoliton annihilation possible. By increasing the bias current, the forces acting the solitons increases and so does their speed. Due to nonuniform application of bias current a self induced magnetic field is created which can result in creation of unwanted solitons. Optimum bias current application can result in larger bias currents and larger soliton speed. Simulations have provided us with such an arrangement of bias current paths.

Optimizing switching frequency of the soliton transistor by numerical simulation

International Nuclear Information System (INIS)

Izadyar, S.; Niazzadeh, M.; Raissi, F.

2009-01-01

In this paper, by numerical simulations we have examined different ways to increase the soliton transistor's switching frequency. Speed of the solitons in a soliton transistor depends on various parameters such as the loss of the junction, the applied bias current, and the transmission line characteristics. Three different ways have been examined; (i) decreasing the size of the transistor without losing transistor effect. (ii) Decreasing the amount of loss of the junction to increase the soliton speed. (iii) Optimizing the bias current to obtain maximum possible speed. We have obtained the shortest possible length to have at least one working soliton inside the transistor. The dimension of the soliton can be decreased by changing the inductance of the transmission line, causing a further decrease in the size of the transistor, however, a trade off between the size and the inductance is needed to obtain the optimum switching speed. Decreasing the amount of loss can be accomplished by increasing the characteristic tunneling resistance of the device, however, a trade off is again needed to make soliton and antisoliton annihilation possible. By increasing the bias current, the forces acting the solitons increases and so does their speed. Due to nonuniform application of bias current a self induced magnetic field is created which can result in creation of unwanted solitons. Optimum bias current application can result in larger bias currents and larger soliton speed. Simulations have provided us with such an arrangement of bias current paths.

Beta irradiation as a method of the static MOS RAM memories processing and circuit design verification

International Nuclear Information System (INIS)

Wislowski, J.; Jagusztyn, M.

1985-01-01

1K NMOS RAM's in plastic packages were investigated after beta irradiation up to 100 Gy (Si) total dose. The memory samples differed as regards processing details and circuit design. Radioisotope beta sources were used for irradiation as the most safe and least expensive. A new version of the model of radiation-induced functional degradation of MOS RAM's has been proposed. 19 refs., 8 figs., 5 tabs. (author)

Evolution of the MOS transistor - From conception to VLSI

International Nuclear Information System (INIS)

Sah, C.T.

1988-01-01

Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

Fundamentals of bias temperature instability in MOS transistors characterization methods, process and materials impact, DC and AC modeling

CERN Document Server

2016-01-01

This book aims to cover different aspects of Bias Temperature Instability (BTI). BTI remains as an important reliability concern for CMOS transistors and circuits. Development of BTI resilient technology relies on utilizing artefact-free stress and measurement methods and suitable physics-based models for accurate determination of degradation at end-of-life, and understanding the gate insulator process impact on BTI. This book discusses different ultra-fast characterization techniques for recovery artefact free BTI measurements. It also covers different direct measurements techniques to access pre-existing and newly generated gate insulator traps responsible for BTI. The book provides a consistent physical framework for NBTI and PBTI respectively for p- and n- channel MOSFETs, consisting of trap generation and trapping. A physics-based compact model is presented to estimate measured BTI degradation in planar Si MOSFETs having differently processed SiON and HKMG gate insulators, in planar SiGe MOSFETs and also...

Transistorized PWM inverter-induction motor drive system

Science.gov (United States)

Peak, S. C.; Plunkett, A. B.

1982-01-01

This paper describes the development of a transistorized PWM inverter-induction motor traction drive system. A vehicle performance analysis was performed to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of inverter and motor specifications. The inverter was a transistorized three-phase bridge using General Electric power Darlington transistors. The description of the design and development of this inverter is the principal object of this paper. The high-speed induction motor is a design which is optimized for use with an inverter power source. The primary feedback control is a torque angle control with voltage and torque outer loop controls. A current-controlled PWM technique is used to control the motor voltage. The drive has a constant torque output with PWM operation to base motor speed and a constant horsepower output with square wave operation to maximum speed. The drive system was dynamometer tested and the results are presented.

Oscillation of Critical Current by Gate Voltage in Cooper Pair Transistor

International Nuclear Information System (INIS)

Kim, N.; Cheong, Y.; Song, W.

2010-01-01

We measured the critical current of a Cooper pair transistor consisting of two Josephson junctions and a gate electrode. The Cooper pair transistors were fabricated by using electron-beam lithography and double-angle evaporation technique. The Gate voltage dependence of critical current was measured by observing voltage jumps at various gate voltages while sweeping bias current. The observed oscillation was 2e-periodic, which shows the Cooper pair transistor had low level of quasiparticle poisoning.

Fundamentals of RF and microwave transistor amplifiers

CERN Document Server

Bahl, Inder J

2009-01-01

A Comprehensive and Up-to-Date Treatment of RF and Microwave Transistor Amplifiers This book provides state-of-the-art coverage of RF and microwave transistor amplifiers, including low-noise, narrowband, broadband, linear, high-power, high-efficiency, and high-voltage. Topics covered include modeling, analysis, design, packaging, and thermal and fabrication considerations. Through a unique integration of theory and practice, readers will learn to solve amplifier-related design problems ranging from matching networks to biasing and stability. More than 240 problems are included to help read

Transistor and integrated circuit manufacture

Energy Technology Data Exchange (ETDEWEB)

Colman, D

1978-09-27

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

Going ballistic: Graphene hot electron transistors

Science.gov (United States)

Vaziri, S.; Smith, A. D.; Östling, M.; Lupina, G.; Dabrowski, J.; Lippert, G.; Mehr, W.; Driussi, F.; Venica, S.; Di Lecce, V.; Gnudi, A.; König, M.; Ruhl, G.; Belete, M.; Lemme, M. C.

2015-12-01

This paper reviews the experimental and theoretical state of the art in ballistic hot electron transistors that utilize two-dimensional base contacts made from graphene, i.e. graphene base transistors (GBTs). Early performance predictions that indicated potential for THz operation still hold true today, even with improved models that take non-idealities into account. Experimental results clearly demonstrate the basic functionality, with on/off current switching over several orders of magnitude, but further developments are required to exploit the full potential of the GBT device family. In particular, interfaces between graphene and semiconductors or dielectrics are far from perfect and thus limit experimental device integrity, reliability and performance.

Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.

Science.gov (United States)

Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2017-10-25

Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2  area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

Science.gov (United States)

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Effects on focused ion beam irradiation on MOS transistors

International Nuclear Information System (INIS)

Campbell, A.N.; Peterson, K.A.; Fleetwood, D.M.; Soden, J.M.

1997-01-01

The effects of irradiation from a focused ion beam (FIB) system on MOS transistors are reported systematically for the first time. Three MOS transistor technologies, with 0.5, 1, and 3 μm minimum feature sizes and with gate oxide thicknesses ranging from 11 to 50 nm, were analyzed. Significant shifts in transistor parameters (such as threshold voltage, transconductance, and mobility) were observed following irradiation with a 30 keV Ga + focused ion beam with ion doses varying by over 5 orders of magnitude. The apparent damage mechanism (which involved the creation of interface traps, oxide trapped charge, or both) and extent of damage were different for each of the three technologies investigated

Light programmable organic transistor memory device based on hybrid dielectric

Science.gov (United States)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

International Nuclear Information System (INIS)

Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang; Zhao, Juan; Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S.

2015-01-01

Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10 4 and a field-effect mobility of 5 cm 2 V −1 s −1 under elongation and demonstrate invariant performance over 1000 stretching cycles

Transistor and integrated circuit manufacture

International Nuclear Information System (INIS)

Colman, D.

1978-01-01

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

Method for double-sided processing of thin film transistors

Science.gov (United States)

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Fully printed metabolite sensor using organic electrochemical transistor

Science.gov (United States)

Scheiblin, Gaëtan; Aliane, Abdelkader; Coppard, Romain; Owens, Róisín. M.; Mailley, Pascal; Malliaras, George G.

2015-08-01

As conducting polymer based devices, organic electrochemical transistors (OECTs) are suited for printing process. The convenience of the screen-printing techniques allowed us to design and fabricate OECTs with a selected design and using different gate material. Depending on the material used, we were able to tune the transistor for different biological application. Ag/AgCl gate provided transistor with good transconductance, and electrochemical sensitivity to pH was provided by polyaniline ink. Finally, we validate the enzymatic sensing of glucose and lactate with a Poly(3,4-ethylene dioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS) gate often used due to its biocompatible properties. The screen-printing process allowed us to fabricate a large amount of devices in a short period of time, using only commercially available grades of ink, showing by this way the possible transfer to industrial purpose.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

Science.gov (United States)

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Transport and performance of a gate all around InAs nanowire transistor

International Nuclear Information System (INIS)

Alam, Khairul

2009-01-01

The transport physics and performance metrics of a gate all around an InAs nanowire transistor are studied using a three-dimensional quantum simulation. The transistor action of an InAs nanowire transistor occurs by modulating the transmission coefficient of the device. This action is different from a conventional metal-oxide-semiconductor field effect transistor, where the transistor action occurs by modulating the charge in the channel. The device has 82% tunneling current in the off-state and 81% thermal current in the on-state. The two current components become equal at a gate bias at which an approximate source-channel flat-band condition is achieved. Prior to this gate bias, the tunneling current dominates and the thermal current dominates beyond it. The device has an on/off current ratio of 7.84 × 10 5 and an inverse subthreshold slope of 63 mV dec −1 . The transistor operates in the quantum capacitance limit with a normalized transconductance value of 14.43 mS µm −1 , an intrinsic switching delay of 90.1675 fs, and an intrinsic unity current gain frequency of 6.8697 THz

Worst-Case Bias During Total Dose Irradiation of SOI Transistors

International Nuclear Information System (INIS)

Ferlet-Cavrois, V.; Colladant, T.; Paillet, P.; Leray, J.-L; Musseau, O.; Schwank, James R.; Shaneyfelt, Marty R.; Pelloie, J.L.; Du Port de Poncharra, J.

2000-01-01

The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide

Static Characteristics of the Ferroelectric Transistor Inverter

Science.gov (United States)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Pulse GaAs field transistor amplifier with subnanosecond time transient

International Nuclear Information System (INIS)

Sidnev, A.N.

1987-01-01

Pulse amplifier on fast field effect GaAs transistors with Schottky barrier is described. The amplifier contains four cascades, the first three of which are made on combined transistors on the common-drain circuit. The last cascade is made on high-power field effect GaAs transistor for coordination with 50 ohm load. The amplifier operates within the range of input signals from 0.5 up to 100 mV with repetition frequency up to 16 Hz, The gain of the amplifier is ≅ 20 dB. The setting time at output pulses amplitude up to 1 V constitutes ∼ 0.2 ns

Investigations of Tunneling for Field Effect Transistors

OpenAIRE

Matheu, Peter

2012-01-01

Over 40 years of scaling dimensions for new and continuing product cycles has introduced new challenges for transistor design. As the end of the technology roadmap for semiconductors approaches, new device structures are being investigated as possible replacements for traditional metal-oxide-semiconductor field effect transistors (MOSFETs). Band-to-band tunneling (BTBT) in semiconductors, often viewed as an adverse effect of short channel lengths in MOSFETs, has been discussed as a promising ...

Organic tunnel field effect transistors

KAUST Repository

Tietze, Max Lutz; Lussem, Bjorn; Liu, Shiyi

2017-01-01

Various examples are provided for organic tunnel field effect transistors (OTFET), and methods thereof. In one example, an OTFET includes a first intrinsic layer (i-layer) of organic semiconductor material disposed over a gate insulating layer

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

Science.gov (United States)

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-frequency self-aligned graphene transistors with transferred gate stacks

Science.gov (United States)

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Progresses in organic field-effect transistors and molecular electronics

Institute of Scientific and Technical Information of China (English)

Wu Weiping; Xu Wei; Hu Wenping; Liu Yunqi; Zhu Daoben

2006-01-01

In the past years,organic semiconductors have been extensively investigated as electronic materials for organic field-effect transistors (OFETs).In this review,we briefly summarize the current status of organic field-effect transistors including materials design,device physics,molecular electronics and the applications of carbon nanotubes in molecular electronics.Future prospects and investigations required to improve the OFET performance are also involved.

A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

Science.gov (United States)

She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

2017-02-01

A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

International Nuclear Information System (INIS)

Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

2014-01-01

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

Science.gov (United States)

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Oxygen effect on the electrical characteristics of pentacene transistors

International Nuclear Information System (INIS)

Hu Yan; Dong Guifang; Hu Yuanchuan; Wang Liduo; Qiu Yong

2006-01-01

The effect of oxygen on the electrical characteristics of organic thin film transistors with pentacene as the active layer has been investigated. The saturation currents and mobilities of the transistors increase as the ambient oxygen concentration decreases, which is ascribed to the formation of a charge transfer complex between pentacene and O 2 . The deposition rate of the pentacene layer affects this phenomenon. The transistor with the pentacene layer deposited at a rate of 15 nm min -1 shows higher sensitivity to oxygen concentration than the device with the pentacene layer deposited at 30 nm min -1 . We suggest that when deposited at a lower rate the pentacene film is less compact, leading to easier entrance of oxygen into the charge accumulation region

Hot carrier degradation and a new lifetime prediction model in ultra-deep sub-micron pMOSFET

International Nuclear Information System (INIS)

Lei Xiao-Yi; Liu Hong-Xia; Zhang Kai; Zhang Yue; Zheng Xue-Feng; Ma Xiao-Hua; Hao Yue

2013-01-01

The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal—oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time (t), channel width (W), channel length (L), and stress voltage (V d ) is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Research of the voltage and current stabilization processes by using the silicon field-effect transistor

International Nuclear Information System (INIS)

Karimov, A.V.; Yodgorova, D.M.; Kamanov, B.M.; Giyasova, F.A.; Yakudov, A.A.

2012-01-01

The silicon field-effect transistors were investigated to use in circuits for stabilization of current and voltage. As in gallium arsenide field-effect transistors, in silicon field-effect transistors with p-n-junction a new mechanism of saturation of the drain current is experimentally found out due to both transverse and longitudinal compression of channel by additional resistance between the source and the gate of the transistor. The criteria for evaluating the coefficients of stabilization of transient current suppressors and voltage stabilizator based on the field-effect transistor are considered. (authors)

Organic field-effect transistors using single crystals

International Nuclear Information System (INIS)

Hasegawa, Tatsuo; Takeya, Jun

2009-01-01

Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for 'plastic electronics'. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs), the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20-40 cm 2 Vs -1 , achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR) measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps. (topical review)

Circuit and method for controlling the threshold voltage of transistors.

NARCIS (Netherlands)

2008-01-01

A control unit, for controlling a threshold voltage of a circuit unit having transistor devices, includes a reference circuit and a measuring unit. The measuring unit is configured to measure a threshold voltage of at least one sensing transistor of the circuit unit, and to measure a threshold

Large-area WSe2 electric double layer transistors on a plastic substrate

KAUST Repository

Funahashi, Kazuma; Pu, Jiang; Li, Ming Yang; Li, Lain-Jong; Iwasa, Yoshihiro; Takenobu, Taishi

2015-01-01

Due to the requirements for large-area, uniform films, currently transition metal dichalcogenides (TMDC) cannot be used in flexible transistor industrial applications. In this study, we first transferred chemically grown large-area WSe2 monolayer films from the as-grown sapphire substrates to the flexible plastic substrates. We also fabricated electric double layer transistors using the WSe2 films on the plastic substrates. These transistors exhibited ambipolar operation and an ON/OFF current ratio of ∼104, demonstrating chemically grown WSe2 transistors on plastic substrates for the first time. This achievement can be an important first step for the next-generation TMDC based flexible devices. © 2015 The Japan Society of Applied Physics.

Large-area WSe2 electric double layer transistors on a plastic substrate

KAUST Repository

Funahashi, Kazuma

2015-04-27

Due to the requirements for large-area, uniform films, currently transition metal dichalcogenides (TMDC) cannot be used in flexible transistor industrial applications. In this study, we first transferred chemically grown large-area WSe2 monolayer films from the as-grown sapphire substrates to the flexible plastic substrates. We also fabricated electric double layer transistors using the WSe2 films on the plastic substrates. These transistors exhibited ambipolar operation and an ON/OFF current ratio of ∼104, demonstrating chemically grown WSe2 transistors on plastic substrates for the first time. This achievement can be an important first step for the next-generation TMDC based flexible devices. © 2015 The Japan Society of Applied Physics.

NMOS-Based Integrated Modular Bypass for Use in Solar Systems (NIMBUS: Intelligent Bypass for Reducing Partial Shading Power Loss in Solar Panel Applications

Directory of Open Access Journals (Sweden)

Pieter Bauwens

2016-06-01

Full Text Available NMOS-based Integrated Modular Bypass for Use in Solar systems (NIMBUS is designed as a replacement for the traditional bypass diode, used in common solar panels. Because of the series connection between the individual solar cells, the power output of a photovoltaic (PV panel will drop disproportionally under partial shading. Currently, this is solved by dividing the PV panel into substrings, each with a diode bypass placed in parallel. This allows an alternative current path. However, the diodes still have a significant voltage drop (about 350 mV, and due to the fairly large currents in a panel, the diodes are dissipating power that we would rather see at the output of the panel. The NIMBUS chip, being a low-voltage-drop switch, aims to replace these diodes and, thus, reduce that power loss. NIMBUS is a smart bypass: a completely stand-alone system that detects the failing of one or more cells and activates when necessary. It is designed for a 100-mV voltage drop under a 5-A load current. When two or more NIMBUS chips are placed in parallel, an internal synchronization circuit ensures proper operation to provide for larger load currents. This paper will elaborate on the operation, design and implementation of the NIMBUS chip, as well as on the first measurements.

The total dose effects on the 1/f noise of deep submicron CMOS transistors

International Nuclear Information System (INIS)

Hu Rongbin; Wang Yuxin; Lu Wu

2014-01-01

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

A high-speed low-noise transimpedance amplifier in a 0.25 μm CMOS technology

International Nuclear Information System (INIS)

Anelli, Giovanni; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

2003-01-01

We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 kΩ, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO 2 ) without any degradation in the performance

A high-speed low-noise transimpedance amplifier in a 0.25 {mu}m CMOS technology

Energy Technology Data Exchange (ETDEWEB)

Anelli, Giovanni E-mail: giovanni.anelli@cern.ch; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

2003-10-11

We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 k{omega}, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO{sub 2}) without any degradation in the performance.

Morphological and crystalline characterization of pulsed laser deposited pentacene thin films for organic transistor applications

Science.gov (United States)

Pereira, Antonio; Bonhommeau, Sébastien; Sirotkin, Sergey; Desplanche, Sarah; Kaba, Mamadouba; Constantinescu, Catalin; Diallo, Abdou Karim; Talaga, David; Penuelas, Jose; Videlot-Ackermann, Christine; Alloncle, Anne-Patricia; Delaporte, Philippe; Rodriguez, Vincent

2017-10-01

We show that high-quality pentacene (P5) thin films of high crystallinity and low surface roughness can be produced by pulsed laser deposition (PLD) without inducing chemical degradation of the molecules. By using Raman spectroscopy and X-ray diffraction measurements, we also demonstrate that the deposition of P5 on Au layers result in highly disordered P5 thin films. While the P5 molecules arrange within the well-documented 1.54-nm thin-film phase on high-purity fused silica substrates, this ordering is indeed destroyed upon introducing an Au interlayer. This observation may be one explanation for the low electrical performances measured in P5-based organic thin film transistors (OTFTs) deposited by laser-induced forward transfer (LIFT).

Schottky barrier diode embedded AlGaN/GaN switching transistor

International Nuclear Information System (INIS)

Park, Bong-Ryeol; Lee, Jung-Yeon; Lee, Jae-Gil; Lee, Dong-Myung; Cha, Ho-Young; Kim, Moon-Kyung

2013-01-01

We developed a Schottky barrier diode (SBD) embedded AlGaN/GaN switching transistor to allow negative current flow during off-state condition. An SBD was embedded in a recessed normally-off AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistor (MOSHFET). The fabricated device exhibited normally-off characteristics with a gate threshold voltage of 2.8 V, a diode turn-on voltage of 1.2 V, and a breakdown voltage of 849 V for the anode-to-drain distance of 8 µm. An on-resistance of 2.66 mΩcm 2 was achieved at a gate voltage of 16 V in the forward transistor mode. Eliminating the need for an external diode, the SBD embedded switching transistor has advantages of significant reduction in parasitic inductance and chip area. (paper)

Transistor design considerations for low-noise preamplifiers

International Nuclear Information System (INIS)

Fair, R.B.

1976-01-01

A review is presented of design considerations for GaAs Schottky-barrier FETs and other types of transistors in low-noise amplifiers for capacitive sources which are used in nuclear radiation detectors and high speed fiber-optic communication systems. Ultimate limits on performance are evaluated in terms of the g/sub m//C/sub i/ ratio and the gate leakage current to minimize the noise sources. Si bipolar transistors and the future prospects of GaAs, Si and InAs MISFETs are discussed, and performance is compared to FETs currently being used in low-noise preamplifiers

Progressive failure site generation in AlGaN/GaN high electron mobility transistors under OFF-state stress: Weibull statistics and temperature dependence

International Nuclear Information System (INIS)

Sun, Huarui; Bajo, Miguel Montes; Uren, Michael J.; Kuball, Martin

2015-01-01

Gate leakage degradation of AlGaN/GaN high electron mobility transistors under OFF-state stress is investigated using a combination of electrical, optical, and surface morphology characterizations. The generation of leakage “hot spots” at the edge of the gate is found to be strongly temperature accelerated. The time for the formation of each failure site follows a Weibull distribution with a shape parameter in the range of 0.7–0.9 from room temperature up to 120 °C. The average leakage per failure site is only weakly temperature dependent. The stress-induced structural degradation at the leakage sites exhibits a temperature dependence in the surface morphology, which is consistent with a surface defect generation process involving temperature-associated changes in the breakdown sites

Noise characteristics of single-walled carbon nanotube network transistors

International Nuclear Information System (INIS)

Kim, Un Jeong; Kim, Kang Hyun; Kim, Kyu Tae; Min, Yo-Sep; Park, Wanjun

2008-01-01

The noise characteristics of randomly networked single-walled carbon nanotubes grown directly by plasma enhanced chemical vapor deposition (PECVD) are studied with field effect transistors (FETs). Due to the geometrical complexity of nanotube networks in the channel area and the large number of tube-tube/tube-metal junctions, the inverse frequency, 1/f, dependence of the noise shows a similar level to that of a single single-walled carbon nanotube transistor. Detailed analysis is performed with the parameters of number of mobile carriers and mobility in the different environment. This shows that the change in the number of mobile carriers resulting in the mobility change due to adsorption and desorption of gas molecules (mostly oxygen molecules) to the tube surface is a key factor in the 1/f noise level for carbon nanotube network transistors

Design Optimization of Transistors Used for Neural Recording

Directory of Open Access Journals (Sweden)

Eric Basham

2012-01-01

Full Text Available Neurons cultured directly over open-gate field-effect transistors result in a hybrid device, the neuron-FET. Neuron-FET amplifier circuits reported in the literature employ the neuron-FET transducer as a current-mode device in conjunction with a transimpedance amplifier. In this configuration, the transducer does not provide any signal gain, and characterization of the transducer out of the amplification circuit is required. Furthermore, the circuit requires a complex biasing scheme that must be retuned to compensate for drift. Here we present an alternative strategy based on the gm/Id design approach to optimize a single-stage common-source amplifier design. The gm/Id design approach facilitates in circuit characterization of the neuron-FET and provides insight into approaches to improving the transistor process design for application as a neuron-FET transducer. Simulation data for a test case demonstrates optimization of the transistor design and significant increase in gain over a current mode implementation.

Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang [Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Zhao, Juan [School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China); Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S., E-mail: michael.arnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States)

2015-08-03

Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10{sup 4} and a field-effect mobility of 5 cm{sup 2} V{sup −1} s{sup −1} under elongation and demonstrate invariant performance over 1000 stretching cycles.

Effect of Disorder on the Conductance of Spin Field Effect Transistors (SPINFET)

OpenAIRE

Cahay, M.; Bandyopadhyay, S.

2003-01-01

We show that the conductance of Spin Field Effect Transistors (SPINFET) [Datta and Das, Appl. Phys. Lett., Vol. 56, 665 (1990)] is affected by a single (non-magnetic) impurity in the transistor's channel. The extreme sensitivity of the amplitude and phase of the transistor's conductance oscillations to the location of a single impurity in the channel is reminiscent of the phenomenon of universal conductance fluctuations in mesoscopic samples and is extremely problematic as far as device imple...

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

Energy Technology Data Exchange (ETDEWEB)

Curry, M. J. [Department of Physics and Astronomy, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); England, T. D.; Bishop, N. C.; Ten-Eyck, G.; Wendt, J. R.; Pluym, T.; Lilly, M. P.; Carroll, M. S. [Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); Carr, S. M. [Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States)

2015-05-18

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10–100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

International Nuclear Information System (INIS)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-01-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f_t/f_m_a_x of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f_t/f_m_a_x of 48/60 GHz.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

Energy Technology Data Exchange (ETDEWEB)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J. [Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375 (United States)

2016-08-08

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.

Graphene-graphite oxide field-effect transistors.

Science.gov (United States)

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa; Fahad, Hossain M.; Smith, Casey E.; Rojas, Jhonathan Prieto

2015-01-01

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa

2015-12-29

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

High-mobility pyrene-based semiconductor for organic thin-film transistors.

Science.gov (United States)

Cho, Hyunduck; Lee, Sunyoung; Cho, Nam Sung; Jabbour, Ghassan E; Kwak, Jeonghun; Hwang, Do-Hoon; Lee, Changhee

2013-05-01

Numerous conjugated oligoacenes and polythiophenes are being heavily studied in the search for high-mobility organic semiconductors. Although many researchers have designed fused aromatic compounds as organic semiconductors for organic thin-film transistors (OTFTs), pyrene-based organic semiconductors with high mobilities and on-off current ratios have not yet been reported. Here, we introduce a new pyrene-based p-type organic semiconductor showing liquid crystal behavior. The thin film characteristics of this material are investigated by varying the substrate temperature during the deposition and the gate dielectric condition using the surface modification with a self-assembled monolayer, and systematically studied in correlation with the performances of transistor devices with this compound. OTFT fabricated under the optimum deposition conditions of this compound, namely, 1,6-bis(5'-octyl-2,2'-bithiophen-5-yl)pyrene (BOBTP) shows a high-performance transistor behavior with a field-effect mobility of 2.1 cm(2) V(-1) s(-1) and an on-off current ratio of 7.6 × 10(6) and enhanced long-term stability compared to the pentacene thin-film transistor.

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Polarization sensitive detection of 100 GHz radiation by high mobility field-effect transistors

International Nuclear Information System (INIS)

Sakowicz, M.; Lusakowski, J.; Karpierz, K.; Grynberg, M.; Knap, W.; Gwarek, W.

2008-01-01

Detection of 100 GHz electromagnetic radiation by a GaAs/AlGaAs high electron mobility field-effect transistor was investigated at 300 K as a function of the angle α between the direction of linear polarization of the radiation and the symmetry axis of the transistor. The angular dependence of the detected signal was found to be A 0 cos 2 (α-α 0 )+C with A 0 , α 0 , and C dependent on the electrical polarization of the transistor gate. This dependence is interpreted as due to excitation of two crossed phase-shifted oscillators. A response of the transistor chip (including bonding wires and the substrate) to 100 GHz radiation was numerically simulated. Results of calculations confirmed experimentally observed dependencies and showed that the two oscillators result from an interplay of 100 GHz currents defined by the transistor impedance together with bonding wires and substrate related modes

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

Science.gov (United States)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

GaN transistors on Si for switching and high-frequency applications

Science.gov (United States)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

High operational and environmental stability of high-mobility conjugated polymer field-effect transistors through the use of molecular additives

KAUST Repository

Nikolka, Mark; Nasrallah, Iyad; Rose, Bradley Daniel; Ravva, Mahesh Kumar; Broch, Katharina; Sadhanala, Aditya; Harkin, David; Charmet, Jerome; Hurhangee, Michael; Brown, Adam; Illig, Steffen; Too, Patrick; Jongman, Jan; McCulloch, Iain; Bredas, Jean-Luc; Sirringhaus, Henning

2016-01-01

Due to their low-temperature processing properties and inherent mechanical flexibility, conjugated polymer field-effect transistors (FETs) are promising candidates for enabling flexible electronic circuits and displays. Much progress has been made on materials performance; however, there remain significant concerns about operational and environmental stability, particularly in the context of applications that require a very high level of threshold voltage stability, such as active-matrix addressing of organic light-emitting diode displays. Here, we investigate the physical mechanisms behind operational and environmental degradation of high-mobility, p-type polymer FETs and demonstrate an effective route to improve device stability. We show that water incorporated in nanometre-sized voids within the polymer microstructure is the key factor in charge trapping and device degradation. By inserting molecular additives that displace water from these voids, it is possible to increase the stability as well as uniformity to a high level sufficient for demanding industrial applications.

High operational and environmental stability of high-mobility conjugated polymer field-effect transistors through the use of molecular additives

KAUST Repository

Nikolka, Mark

2016-12-12

Due to their low-temperature processing properties and inherent mechanical flexibility, conjugated polymer field-effect transistors (FETs) are promising candidates for enabling flexible electronic circuits and displays. Much progress has been made on materials performance; however, there remain significant concerns about operational and environmental stability, particularly in the context of applications that require a very high level of threshold voltage stability, such as active-matrix addressing of organic light-emitting diode displays. Here, we investigate the physical mechanisms behind operational and environmental degradation of high-mobility, p-type polymer FETs and demonstrate an effective route to improve device stability. We show that water incorporated in nanometre-sized voids within the polymer microstructure is the key factor in charge trapping and device degradation. By inserting molecular additives that displace water from these voids, it is possible to increase the stability as well as uniformity to a high level sufficient for demanding industrial applications.

Organic field-effect transistors using single crystals

Directory of Open Access Journals (Sweden)

Tatsuo Hasegawa and Jun Takeya

2009-01-01

Full Text Available Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for 'plastic electronics'. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs, the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20–40 cm2 Vs−1, achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps.

A pattern recognition approach to transistor array parameter variance

Science.gov (United States)

da F. Costa, Luciano; Silva, Filipi N.; Comin, Cesar H.

2018-06-01

The properties of semiconductor devices, including bipolar junction transistors (BJTs), are known to vary substantially in terms of their parameters. In this work, an experimental approach, including pattern recognition concepts and methods such as principal component analysis (PCA) and linear discriminant analysis (LDA), was used to experimentally investigate the variation among BJTs belonging to integrated circuits known as transistor arrays. It was shown that a good deal of the devices variance can be captured using only two PCA axes. It was also verified that, though substantially small variation of parameters is observed for BJT from the same array, larger variation arises between BJTs from distinct arrays, suggesting the consideration of device characteristics in more critical analog designs. As a consequence of its supervised nature, LDA was able to provide a substantial separation of the BJT into clusters, corresponding to each transistor array. In addition, the LDA mapping into two dimensions revealed a clear relationship between the considered measurements. Interestingly, a specific mapping suggested by the PCA, involving the total harmonic distortion variation expressed in terms of the average voltage gain, yielded an even better separation between the transistor array clusters. All in all, this work yielded interesting results from both semiconductor engineering and pattern recognition perspectives.

Combinatorial study of zinc tin oxide thin-film transistors

Science.gov (United States)

McDowell, M. G.; Sanderson, R. J.; Hill, I. G.

2008-01-01

Groups of thin-film transistors using a zinc tin oxide semiconductor layer have been fabricated via a combinatorial rf sputtering technique. The ZnO :SnO2 ratio of the film varies as a function of position on the sample, from pure ZnO to SnO2, allowing for a study of zinc tin oxide transistor performance as a function of channel stoichiometry. The devices were found to have mobilities ranging from 2to12cm2/Vs, with two peaks in mobility in devices at ZnO fractions of 0.80±0.03 and 0.25±0.05, and on/off ratios as high as 107. Transistors composed predominantly of SnO2 were found to exhibit light sensitivity which affected both the on/off ratios and threshold voltages of these devices.

Graphene Field Effect Transistor for Radiation Detection

Science.gov (United States)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

Proton migration mechanism for the instability of organic field-effect transistors

NARCIS (Netherlands)

Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.

2009-01-01

During prolonged application of a gate bias, organic field-effect transistors show an instability involving a gradual shift of the threshold voltage toward the applied gate bias voltage. We propose a model for this instability in p-type transistors with a silicon-dioxide gate dielectric, based on

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

International Nuclear Information System (INIS)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng; Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu

2014-01-01

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

Energy Technology Data Exchange (ETDEWEB)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng, E-mail: swffrog@seu.edu.cn [National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China); Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu [CSMC Technologies Corporation, Wuxi 214061 (China)

2014-04-14

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

Science.gov (United States)

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Hybrid light emitting transistors (Presentation Recording)

Science.gov (United States)

Muhieddine, Khalid; Ullah, Mujeeb; Namdas, Ebinazar B.; Burn, Paul L.

2015-10-01

Organic light-emitting diodes (OLEDs) are well studied and established in current display applications. Light-emitting transistors (LETs) have been developed to further simplify the necessary circuitry for these applications, combining the switching capabilities of a transistor with the light emitting capabilities of an OLED. Such devices have been studied using mono- and bilayer geometries and a variety of polymers [1], small organic molecules [2] and single crystals [3] within the active layers. Current devices can often suffer from low carrier mobilities and most operate in p-type mode due to a lack of suitable n-type organic charge carrier materials. Hybrid light-emitting transistors (HLETs) are a logical step to improve device performance by harnessing the charge carrier capabilities of inorganic semiconductors [4]. We present state of the art, all solution processed hybrid light-emitting transistors using a non-planar contact geometry [1, 5]. We will discuss HLETs comprised of an inorganic electron transport layer prepared from a sol-gel of zinc tin oxide and several organic emissive materials. The mobility of the devices is found between 1-5 cm2/Vs and they had on/off ratios of ~105. Combined with optical brightness and efficiencies of the order of 103 cd/m2 and 10-3-10-1 %, respectively, these devices are moving towards the performance required for application in displays. [1] M. Ullah, K. Tandy, S. D. Yambem, M. Aljada, P. L. Burn, P. Meredith, E. B. Namdas., Adv. Mater. 2013, 25, 53, 6213 [2] R. Capelli, S. Toffanin, G. Generali, H. Usta, A. Facchetti, M. Muccini, Nature Materials 2010, 9, 496 [3] T. Takenobu, S. Z. Bisri, T. Takahashi, M. Yahiro, C. Adachi, Y. Iwasa, Phys. Rev. Lett. 2008, 100, 066601 [4] H. Nakanotani, M. Yahiro, C. Adachi, K. Yano, Appl. Phys. Lett. 2007, 90, 262104 [5] K. Muhieddine, M. Ullah, B. N. Pal, P. Burn E. B. Namdas, Adv. Mater. 2014, 26,37, 6410

Radiation induced deep level defects in bipolar junction transistors under various bias conditions

International Nuclear Information System (INIS)

Liu, Chaoming; Yang, Jianqun; Li, Xingji; Ma, Guoliang; Xiao, Liyi; Bollmann, Joachim

2015-01-01

Bipolar junction transistor (BJT) is sensitive to ionization and displacement radiation effects in space. In this paper, 35 MeV Si ions were used as irradiation source to research the radiation damage on NPN and PNP bipolar transistors. The changing of electrical parameters of transistors was in situ measured with increasing irradiation fluence of 35 MeV Si ions. Using deep level transient spectroscopy (DLTS), defects in the bipolar junction transistors under various bias conditions are measured after irradiation. Based on the in situ electrical measurement and DLTS spectra, it is clearly that the bias conditions can affect the concentration of deep level defects, and the radiation damage induced by heavy ions.

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

Science.gov (United States)

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Validation of Nonlinear Bipolar Transistor Model by Small-Signal Measurements

DEFF Research Database (Denmark)

Vidkjær, Jens; Porra, V.; Zhu, J.

1992-01-01

A new method for the validity analysis of nonlinear transistor models is presented based on DC-and small-signal S-parameter measurements and realistic consideration of the measurement and de-embedding errors and singularities of the small-signal equivalent circuit. As an example, some analysis...... results for an extended Gummel Poon model are presented in the case of a UHF bipolar power transistor....

Principles of an atomtronic transistor

International Nuclear Information System (INIS)

Caliga, Seth C; Anderson, Dana Z; Straatsma, Cameron J E; Zozulya, Alex A

2016-01-01

A semiclassical formalism is used to investigate the transistor-like behavior of ultracold atoms in a triple-well potential. Atom current flows from the source well, held at fixed chemical potential and temperature, into an empty drain well. In steady-state, the gate well located between the source and drain is shown to acquire a well-defined chemical potential and temperature, which are controlled by the relative height of the barriers separating the three wells. It is shown that the gate chemical potential can exceed that of the source and have a lower temperature. In electronics terminology, the source–gate junction can be reverse-biased. As a result, the device exhibits regimes of negative resistance and transresistance, indicating the presence of gain. Given an external current input to the gate, transistor-like behavior is characterized both in terms of the current gain, which can be greater than unity, and the power output of the device. (paper)

Direct observation of single-charge-detection capability of nanowire field-effect transistors.

Science.gov (United States)

Salfi, J; Savelyev, I G; Blumin, M; Nair, S V; Ruda, H E

2010-10-01

A single localized charge can quench the luminescence of a semiconductor nanowire, but relatively little is known about the effect of single charges on the conductance of the nanowire. In one-dimensional nanostructures embedded in a material with a low dielectric permittivity, the Coulomb interaction and excitonic binding energy are much larger than the corresponding values when embedded in a material with the same dielectric permittivity. The stronger Coulomb interaction is also predicted to limit the carrier mobility in nanowires. Here, we experimentally isolate and study the effect of individual localized electrons on carrier transport in InAs nanowire field-effect transistors, and extract the equivalent charge sensitivity. In the low carrier density regime, the electrostatic potential produced by one electron can create an insulating weak link in an otherwise conducting nanowire field-effect transistor, modulating its conductance by as much as 4,200% at 31 K. The equivalent charge sensitivity, 4 × 10(-5) e Hz(-1/2) at 25 K and 6 × 10(-5) e Hz(-1/2) at 198 K, is orders of magnitude better than conventional field-effect transistors and nanoelectromechanical systems, and is just a factor of 20-30 away from the record sensitivity for state-of-the-art single-electron transistors operating below 4 K (ref. 8). This work demonstrates the feasibility of nanowire-based single-electron memories and illustrates a physical process of potential relevance for high performance chemical sensors. The charge-state-detection capability we demonstrate also makes the nanowire field-effect transistor a promising host system for impurities (which may be introduced intentionally or unintentionally) with potentially long spin lifetimes, because such transistors offer more sensitive spin-to-charge conversion readout than schemes based on conventional field-effect transistors.

Printable, Degradable, and Biocompatible Ion Gels from a Renewable ABA Triblock Polyester and a Low Toxicity Ionic Liquid

Energy Technology Data Exchange (ETDEWEB)

Tang, Boxin; Schneiderman, Deborah K.; Bidoky, Fazel Zare; Frisbie, C.Daniel; Lodge, Timothy P. (UMM)

2017-09-15

We have designed printable, biocompatible, and degradable ion gels by combining a novel ABA triblock aliphatic polyester, poly(ε-decalactone)-b-poly(dl-lactide)-b-poly(ε-decalactone), and a low toxicity ionic liquid, 1-butyl-1-methylpyrrolidinium bistrifluoromethanesulfonylimide ([P14][TFSI]). Due to the favorable compatibility between amorphous poly(dl-lactide) and [P14][TFSI] and the insolubility of the poly(ε-decalactone), the triblock polymer forms self-assembled micellar cross-links similar to thermoplastic elastomers, which ensures similar processing conditions and mechanical robustness during the fabrication of printed electrolyte-gated organic transistor devices. Additionally, the ester backbone in the polymer structure enables efficient hydrolytic degradation of these ion gels compared to those made previously using carbon-backbone polymers.

Large signal S-parameters: modeling and radiation effects in microwave power transistors

International Nuclear Information System (INIS)

Graham, E.D. Jr.; Chaffin, R.J.; Gwyn, C.W.

1973-01-01

Microwave power transistors are usually characterized by measuring the source and load impedances, efficiency, and power output at a specified frequency and bias condition in a tuned circuit. These measurements provide limited data for circuit design and yield essentially no information concerning broadbanding possibilities. Recently, a method using large signal S-parameters has been developed which provides a rapid and repeatable means for measuring microwave power transistor parameters. These large signal S-parameters have been successfully used to design rf power amplifiers. Attempts at modeling rf power transistors have in the past been restricted to a modified Ebers-Moll procedure with numerous adjustable model parameters. The modified Ebers-Moll model is further complicated by inclusion of package parasitics. In the present paper an exact one-dimensional device analysis code has been used to model the performance of the transistor chip. This code has been integrated into the SCEPTRE circuit analysis code such that chip, package and circuit performance can be coupled together in the analysis. Using []his computational tool, rf transistor performance has been examined with particular attention given to the theoretical validity of large-signal S-parameters and the effects of nuclear radiation on device parameters. (auth)

High-Current Gain Two-Dimensional MoS 2 -Base Hot-Electron Transistors

KAUST Repository

Torres, Carlos M.

2015-12-09

The vertical transport of nonequilibrium charge carriers through semiconductor heterostructures has led to milestones in electronics with the development of the hot-electron transistor. Recently, significant advances have been made with atomically sharp heterostructures implementing various two-dimensional materials. Although graphene-base hot-electron transistors show great promise for electronic switching at high frequencies, they are limited by their low current gain. Here we show that, by choosing MoS2 and HfO2 for the filter barrier interface and using a noncrystalline semiconductor such as ITO for the collector, we can achieve an unprecedentedly high-current gain (α ∼ 0.95) in our hot-electron transistors operating at room temperature. Furthermore, the current gain can be tuned over 2 orders of magnitude with the collector-base voltage albeit this feature currently presents a drawback in the transistor performance metrics such as poor output resistance and poor intrinsic voltage gain. We anticipate our transistors will pave the way toward the realization of novel flexible 2D material-based high-density, low-energy, and high-frequency hot-carrier electronic applications. © 2015 American Chemical Society.

High-Current Gain Two-Dimensional MoS 2 -Base Hot-Electron Transistors

KAUST Repository

Torres, Carlos M.; Lan, Yann Wen; Zeng, Caifu; Chen, Jyun Hong; Kou, Xufeng; Navabi, Aryan; Tang, Jianshi; Montazeri, Mohammad; Adleman, James R.; Lerner, Mitchell B.; Zhong, Yuan Liang; Li, Lain-Jong; Chen, Chii Dong; Wang, Kang L.

2015-01-01

The vertical transport of nonequilibrium charge carriers through semiconductor heterostructures has led to milestones in electronics with the development of the hot-electron transistor. Recently, significant advances have been made with atomically sharp heterostructures implementing various two-dimensional materials. Although graphene-base hot-electron transistors show great promise for electronic switching at high frequencies, they are limited by their low current gain. Here we show that, by choosing MoS2 and HfO2 for the filter barrier interface and using a noncrystalline semiconductor such as ITO for the collector, we can achieve an unprecedentedly high-current gain (α ∼ 0.95) in our hot-electron transistors operating at room temperature. Furthermore, the current gain can be tuned over 2 orders of magnitude with the collector-base voltage albeit this feature currently presents a drawback in the transistor performance metrics such as poor output resistance and poor intrinsic voltage gain. We anticipate our transistors will pave the way toward the realization of novel flexible 2D material-based high-density, low-energy, and high-frequency hot-carrier electronic applications. © 2015 American Chemical Society.

Laser-Printed Organic Thin-Film Transistors

KAUST Repository

Diemer, Peter J.; Harper, Angela F.; Niazi, Muhammad Rizwan; Petty, Anthony J.; Anthony, John E.; Amassian, Aram; Jurchescu, Oana D.

2017-01-01

their incorporation in large-scale manufacturing processes. Here, the first ever organic thin-film transistor fabricated with an electrophotographic laser printing process using a standard office laser printer is reported. This completely solvent-free additive

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

Science.gov (United States)

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Fabrication and characterization of V-gate AlGaN/GaN high-electron-mobility transistors

International Nuclear Information System (INIS)

Zhang Kai; Cao Meng-Yi; Chen Yong-He; Yang Li-Yuan; Wang Chong; Ma Xiao-Hua; Hao Yue

2013-01-01

V-gate GaN high-electron-mobility transistors (HEMTs) are fabricated and investigated systematically. A V-shaped recess geometry is obtained using an improved Si 3 N 4 recess etching technology. Compared with standard HEMTs, the fabricated V-gate HEMTs exhibit a 17% higher peak extrinsic transconductance due to a narrowed gate foot. Moreover, both the gate leakage and current dispersion are dramatically suppressed simultaneously, although a slight degradation of frequency response is observed. Based on a two-dimensional electric field simulation using Silvaco “ATLAS” for both standard HEMTs and V-gate HEMTs, the relaxation in peak electric field at the gate edge is identified as the predominant factor leading to the superior performance of V-gate HEMTs. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

High-performance radio frequency transistors based on diameter-separated semiconducting carbon nanotubes

Energy Technology Data Exchange (ETDEWEB)

Cao, Yu; Che, Yuchi; Zhou, Chongwu, E-mail: chongwuz@usc.edu [Department of Electrical Engineering, University of Southern California, Los Angeles, California 90089 (United States); Seo, Jung-Woo T.; Hersam, Mark C. [Department of Materials Science and Engineering and Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States); Gui, Hui [Department of Chemical Engineering and Materials Science, University of Southern California, Los Angeles, California 90089 (United States)

2016-06-06

In this paper, we report the high-performance radio-frequency transistors based on the single-walled semiconducting carbon nanotubes with a refined average diameter of ∼1.6 nm. These diameter-separated carbon nanotube transistors show excellent transconductance of 55 μS/μm and desirable drain current saturation with an output resistance of ∼100 KΩ μm. An exceptional radio-frequency performance is also achieved with current gain and power gain cut-off frequencies of 23 GHz and 20 GHz (extrinsic) and 65 GHz and 35 GHz (intrinsic), respectively. These radio-frequency metrics are among the highest reported for the carbon nanotube thin-film transistors. This study provides demonstration of radio frequency transistors based on carbon nanotubes with tailored diameter distributions, which will guide the future application of carbon nanotubes in radio-frequency electronics.

Self-standing chitosan films as dielectrics in organic thin-film transistors

Directory of Open Access Journals (Sweden)

J. Morgado

2013-12-01

Full Text Available Organic thin film transistors, using self-standing 50 µm thick chitosan films as dielectric, are fabricated using sublimed pentacene or two conjugated polymers deposited by spin coating as semiconductors. Field-effect mobilities are found to be similar to values obtained with other dielectrics and, in the case of pentacene, a value (0.13 cm2/(V•s comparable to high performing transistors was determined. In spite of the low On/Off ratios (a maximum value of 600 was obtained for the pentacene-based transistors, these are promising results for the area of sustainable organic electronics in general and for biocompatible electronics in particular.

Strained silicon/silicon germanium heterojunction n-channel metal oxide semiconductor field effect transistors

International Nuclear Information System (INIS)

Olsen, Sarah H.

2002-01-01

Investigations into the performance of strained silicon/silicon-germanium (Si/SiGe) n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) have been carried out. Theoretical predictions suggest that use of a strained Si/SiGe material system with advanced material properties compared with conventional silicon allows enhanced MOSFET device performance. This study has therefore investigated the practical feasibility of obtaining superior electrical performance using a Si/SiGe material system. The MOSFET devices consisted of a strained Si surface channel and were fabricated on relaxed SiGe material using a reduced thermal budget process in order to preserve the strain. Two batches of strained Si/SiGe devices fabricated on material grown by differing methods have been analysed and both showed good transistor action. A correlation of electrical and physical device data established that the electrical device behaviour was closely related to the SiGe material quality, which differed depending on growth technique. The cross-wafer variation in the electrical performance of the strained Si/SiGe devices was found to be a function of material quality, thus the viability of Si/SiGe MOSFET technology for commercial applications has been addressed. Of particular importance was the finding that large-scale 'cross-hatching' roughness associated with relaxed SiGe alloys led to degradation in the small-scale roughness at the gate oxide interface, which affects electrical device performance. The fabrication of strained Si MOSFET devices on high quality SiGe material thus enabled significant performance gains to be realised compared with conventional Si control devices. In contrast, the performance of devices fabricated on material with severe cross-hatching roughness was found to be diminished by the nanoscale oxide interface roughness. The effect of device processing on SiGe material with differing as-grown roughness has been carried out and compared with the reactions

All-Metallic Vertical Transistors Based on Stacked Dirac Materials

OpenAIRE

Wang, Yangyang; Ni, Zeyuan; Liu, Qihang; Quhe, Ruge; Zheng, Jiaxin; Ye, Meng; Yu, Dapeng; Shi, Junjie; Yang, Jinbo; Lu, Jing

2014-01-01

It is an ongoing pursuit to use metal as a channel material in a field effect transistor. All metallic transistor can be fabricated from pristine semimetallic Dirac materials (such as graphene, silicene, and germanene), but the on/off current ratio is very low. In a vertical heterostructure composed by two Dirac materials, the Dirac cones of the two materials survive the weak interlayer van der Waals interaction based on density functional theory method, and electron transport from the Dirac ...

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

Science.gov (United States)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Electric double layer transistors with ferroelectric BaTiO3 channels

NARCIS (Netherlands)

Ito, M.; Matsubara, Y.; Kozuka, Y.; Takahashi, K. S.; Kagawa, F.; Ye, J. T.; Iwasa, Y.; Ueno, K.; Tokura, Y.; Kawasaki, M.

2014-01-01

We report the surface conduction of a BaTiO3 thin film using electric double layer transistor (EDLT) structure. A transistor operation was observed at 220 K with an on/off ratio exceeding 10(5), demonstrating that ionic liquid gating is effective to induce carriers at the surface of ferroelectric

E-Learning System for Design and Construction of Amplifier Using Transistors

Science.gov (United States)

Takemura, Atsushi

2014-01-01

This paper proposes a novel e-Learning system for the comprehensive understanding of electronic circuits with transistors. The proposed e-Learning system allows users to learn a wide range of topics, encompassing circuit theories, design, construction, and measurement. Given the fact that the amplifiers with transistors are an integral part of…

Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

DEFF Research Database (Denmark)

Mucha, Igor

1999-01-01

current memory cells were designed using a CMOS process with threshold voltages V-T0n = \\V-T0p\\ = 0.9 V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than +/-18 mu......A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultralow supply voltage operation also in CMOS processes with high threshold voltages....... This paper presents the theoretical basis for the design of "floating-gate'' switched current memory cells by giving a detailed description and analysis of the most important impacts degrading the performance of the cells. To support the theoretical assumptions circuits based on "floating-gate'' switched...

Suppression of photo-bias induced instability for amorphous indium tungsten oxide thin film transistors with bi-layer structure

Energy Technology Data Exchange (ETDEWEB)

Liu, Po-Tsun, E-mail: ptliu@mail.nctu.edu.tw; Chang, Chih-Hsiang; Chang, Chih-Jui [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (China)

2016-06-27

This study investigates the instability induced by bias temperature illumination stress (NBTIS) for an amorphous indium-tungsten-oxide thin film transistor (a-IWO TFT) with SiO{sub 2} backchannel passivation layer (BPL). It is found that this electrical degradation phenomenon can be attributed to the generation of defect states during the BPL process, which deteriorates the photo-bias stability of a-IWO TFTs. A method proposed by adding an oxygen-rich a-IWO thin film upon the a-IWO active channel layer could effectively suppress the plasma damage to channel layer during BPL deposition process. The bi-layer a-IWO TFT structure with an oxygen-rich back channel exhibits superior electrical reliability of device under NBTIS.

Impact of rounded electrode corners on breakdown characteristics of AlGaN/GaN high-electron mobility transistors

Science.gov (United States)

Yamazaki, Taisei; Asubar, Joel T.; Tokuda, Hirokuni; Kuzuhara, Masaaki

2018-05-01

We investigated the impact of rounded electrode corners on the breakdown characteristics of AlGaN/GaN high-electron mobility transistors. For standard reference devices, catastrophic breakdown occurred predominantly near the sharp electrode corners. By introducing a rounded-electrode architecture, premature breakdown at the corners was mitigated. Moreover, the rate of breakdown voltage (V BR) degradation with an increasing gate width (W G) was significantly lower for devices with rounded corners. When W G was increased from 100 µm to 10 mm, the V BR of the reference device dropped drastically, from 1,200 to 300 V, whereas that of the rounded-electrode device only decreased to a respectable value of 730 V.

Design of ternary clocked adiabatic static random access memory

International Nuclear Information System (INIS)

Wang Pengjun; Mei Fengna

2011-01-01

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions. (semiconductor integrated circuits)

Tracing of border trap behavior by noise analysis in microelectronics

International Nuclear Information System (INIS)

Sharshar, K.A.A.; Shaalan, A.A.M.; Gomaa, E.I.

2008-01-01

The present state of art of this work is to study the electrical defects of the silicon- silicon dioxide interface created by gamma rays (Co 60 ) in submicron MOS devices used in telecommunication systems. We focus our investigation on a particular class of trapped charge located near the interface characterized as the border traps. The expected physical location and chemical structure of the traps were discussed. The low frequency 1/f noise measurement is used in the estimation of border trap densities before and after irradiation; the results are reported for n-MOS transistor exposed to doses (0.3, 0.5, 1 and 10 Mrad). The border trap population in the irradiated samples increased from 7.6*10 10 up to 1.03*10 11 eV -1 Cm -2

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

Science.gov (United States)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

Design of ternary clocked adiabatic static random access memory

Science.gov (United States)

Pengjun, Wang; Fengna, Mei

2011-10-01

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.

LHCb: Radiation hard programmable delay line for LHCb Calorimeter Upgrade

CERN Multimedia

Mauricio Ferre, J; Vilasís Cardona, X; Picatoste Olloqui, E; Machefert, F; Lefrançois, J; Duarte, O

2013-01-01

This poster describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with a 4ps jitter and 18ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35um technology.

Improving positive and negative bias illumination stress stability in parylene passivated IGZO transistors

Energy Technology Data Exchange (ETDEWEB)

Kiazadeh, Asal [Department of Materials Science, i3N/CENIMAT, Faculty of Science and Technology, Universidade NOVA de Lisboa and CEMOP/UNINOVA, Campus de Caparica, 2829-516 Caparica (Portugal); Universidade do Algarve, FCT, 8000-139 Faro (Portugal); Gomes, Henrique L. [Universidade do Algarve, FCT, 8000-139 Faro (Portugal); IT-Instituto de Telecomunicações, Av. Rovisco, Pais, 1, 1049-001 Lisboa (Portugal); Barquinha, Pedro; Martins, Jorge; Rovisco, Ana; Pinto, Joana V.; Martins, Rodrigo; Fortunato, Elvira [Department of Materials Science, i3N/CENIMAT, Faculty of Science and Technology, Universidade NOVA de Lisboa and CEMOP/UNINOVA, Campus de Caparica, 2829-516 Caparica (Portugal)

2016-08-01

The impact of a parylene top-coating layer on the illumination and bias stress instabilities of indium-gallium-zinc oxide thin-film transistors (TFTs) is presented and discussed. The parylene coating substantially reduces the threshold voltage shift caused by continuous application of a gate bias and light exposure. The operational stability improves by 75%, and the light induced instability is reduced by 35%. The operational stability is quantified by fitting the threshold voltage shift with a stretched exponential model. Storage time as long as 7 months does not cause any measurable degradation on the electrical performance. It is proposed that parylene plays not only the role of an encapsulation layer but also of a defect passivation on the top semiconductor surface. It is also reported that depletion-mode TFTs are less sensitive to light induced instabilities. This is attributed to a defect neutralization process in the presence of free electrons.

Molecular doping for control of gate bias stress in organic thin film transistors

Energy Technology Data Exchange (ETDEWEB)

Hein, Moritz P., E-mail: hein@iapp.de; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K. [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Zakhidov, Alexander A. [Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany); Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany)

2014-01-06

The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

Molecular doping for control of gate bias stress in organic thin film transistors

International Nuclear Information System (INIS)

Hein, Moritz P.; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K.; Zakhidov, Alexander A.; Leo, Karl

2014-01-01

The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface

Reliability of AlGaN/GaN high electron mobility transistors on low dislocation density bulk GaN substrate: Implications of surface step edges

Energy Technology Data Exchange (ETDEWEB)

Killat, N., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk; Montes Bajo, M.; Kuball, M., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk [Center for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Paskova, T. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Materials Science and Engineering Department, North Carolina State University, Raleigh, North Carolina 27695 (United States); Evans, K. R. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Leach, J. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Li, X.; Özgür, Ü.; Morkoç, H. [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Chabak, K. D.; Crespo, A.; Gillespie, J. K.; Fitch, R.; Kossler, M.; Walker, D. E.; Trejo, M.; Via, G. D.; Blevins, J. D. [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)

2013-11-04

To enable gaining insight into degradation mechanisms of AlGaN/GaN high electron mobility transistors, devices grown on a low-dislocation-density bulk-GaN substrate were studied. Gate leakage current and electroluminescence (EL) monitoring revealed a progressive appearance of EL spots during off-state stress which signify the generation of gate current leakage paths. Atomic force microscopy evidenced the formation of semiconductor surface pits at the failure location, which corresponds to the interaction region of the gate contact edge and the edges of surface steps.

Reevaluating the worst-case radiation response of MOS transistors

Science.gov (United States)

Fleetwood, D. M.

Predicting worst-case response of a semiconductor device to ionizing radiation is a formidable challenge. As processes change and MOS gate insulators become thinner in advanced VLSI and VHSIC technologies, failure mechanisms must be constantly re-examined. Results are presented of a recent study in which more than 100 MOS transistors were monitored for up to 300 days after Co-60 exposure. Based on these results, a reevaluation of worst-case n-channel transistor response (most positive threshold voltage shift) in low-dose-rate and postirradiation environments is required in many cases. It is shown for Sandia hardened n-channel transistors with a 32 nm gate oxide, that switching from zero-volt bias, held during the entire radiation period, to positive bias during anneal clearly leads to a more positive threshold voltage shift (and thus the slowest circuit response) after Co-60 exposure than the standard case of maintaining positive bias during irradiation and anneal. It is concluded that irradiating these kinds of transistors with zero-volt bias, and annealing with positive bias, leads to worst-case postirradiation response. For commercial devices (with few interface states at doses of interest), on the other hand, device response only improves postirradiation, and worst-case response (in terms of device leakage) is for devices irradiated under positive bias and annealed with zero-volts bias.

Lateral power transistors in integrated circuits

CERN Document Server

Erlbacher, Tobias

2014-01-01

This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

Controllable film densification and interface flatness for high-performance amorphous indium oxide based thin film transistors

Energy Technology Data Exchange (ETDEWEB)

Ou-Yang, Wei, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Kizu, Takio; Gao, Xu; Lin, Meng-Fang; Tsukagoshi, Kazuhito, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp [International Center for Materials Nanoarchitectronics (WPI-MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nabatame, Toshihide [MANA Foundry and MANA Advanced Device Materials Group, National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

2014-10-20

To avoid the problem of air sensitive and wet-etched Zn and/or Ga contained amorphous oxide transistors, we propose an alternative amorphous semiconductor of indium silicon tungsten oxide as the channel material for thin film transistors. In this study, we employ the material to reveal the relation between the active thin film and the transistor performance with aid of x-ray reflectivity study. By adjusting the pre-annealing temperature, we find that the film densification and interface flatness between the film and gate insulator are crucial for achieving controllable high-performance transistors. The material and findings in the study are believed helpful for realizing controllable high-performance stable transistors.

Fermilab main accelerator quadrupole transistorized regulators for improved tune stability

International Nuclear Information System (INIS)

Yarema, R.J.; Pfeffer, H.

1977-01-01

During early operation of the Fermilab Main Accelerator, tune fluctuations, caused by the SCR-controlled power supplies in the quad bus, limited the beam aperature at low energies. To correct this problem, two transistorized power supplies were built in 1975 to regulate and filter the main ring quad magnet current during injection and beam acceleration through the rf transistion region. There is one power supply in series with each quad bus. Each supply uses 320 parallel power transistors and is rated at 300A, 120V. Since the voltage and current capabilities of the transistorized supplies are limited, the supplies are turned-off at about 25GeV. A real-time computer system initiates turn-on of the SCR-controlled power supplies and regulation takeover by the SCR-controlled supplies, at the appropriate times

Nanophotonic quantum computer based on atomic quantum transistor

International Nuclear Information System (INIS)

Andrianov, S N; Moiseev, S A

2015-01-01

We propose a scheme of a quantum computer based on nanophotonic elements: two buses in the form of nanowaveguide resonators, two nanosized units of multiatom multiqubit quantum memory and a set of nanoprocessors in the form of photonic quantum transistors, each containing a pair of nanowaveguide ring resonators coupled via a quantum dot. The operation modes of nanoprocessor photonic quantum transistors are theoretically studied and the execution of main logical operations by means of them is demonstrated. We also discuss the prospects of the proposed nanophotonic quantum computer for operating in high-speed optical fibre networks. (quantum computations)

Nanophotonic quantum computer based on atomic quantum transistor

Energy Technology Data Exchange (ETDEWEB)

Andrianov, S N [Institute of Advanced Research, Academy of Sciences of the Republic of Tatarstan, Kazan (Russian Federation); Moiseev, S A [Kazan E. K. Zavoisky Physical-Technical Institute, Kazan Scientific Center, Russian Academy of Sciences, Kazan (Russian Federation)

2015-10-31

We propose a scheme of a quantum computer based on nanophotonic elements: two buses in the form of nanowaveguide resonators, two nanosized units of multiatom multiqubit quantum memory and a set of nanoprocessors in the form of photonic quantum transistors, each containing a pair of nanowaveguide ring resonators coupled via a quantum dot. The operation modes of nanoprocessor photonic quantum transistors are theoretically studied and the execution of main logical operations by means of them is demonstrated. We also discuss the prospects of the proposed nanophotonic quantum computer for operating in high-speed optical fibre networks. (quantum computations)

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

Science.gov (United States)

Wang, Ching-Hua; Incorvia, Jean Anne C; McClellan, Connor J; Yu, Andrew C; Mleczko, Michal J; Pop, Eric; Wong, H-S Philip

2018-05-09

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Heavy metal removal from water/wastewater by nanosized metal oxides: A review

International Nuclear Information System (INIS)

Hua, Ming; Zhang, Shujuan; Pan, Bingcai; Zhang, Weiming; Lv, Lu; Zhang, Quanxing

2012-01-01

Nanosized metal oxides (NMOs), including nanosized ferric oxides, manganese oxides, aluminum oxides, titanium oxides, magnesium oxides and cerium oxides, provide high surface area and specific affinity for heavy metal adsorption from aqueous systems. To date, it has become a hot topic to develop new technologies to synthesize NMOs, to evaluate their removal of heavy metals under varying experimental conditions, to reveal the underlying mechanism responsible for metal removal based on modern analytical techniques (XAS, ATR-FT-IR, NMR, etc.) or mathematical models, and to develop metal oxide-based materials of better applicability for practical use (such as granular oxides or composite materials). The present review mainly focuses on NMOs’ preparation, their physicochemical properties, adsorption characteristics and mechanism, as well as their application in heavy metal removal. In addition, porous host supported NMOs are particularly concerned because of their great advantages for practical application as compared to the original NMOs. Also, some magnetic NMOs were included due to their unique separation performance.

Pseudo-diode based on protonic/electronic hybrid oxide transistor

Science.gov (United States)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

Controlled ion-beam transformation of silicon bipolar microwave power transistor's characteristics

International Nuclear Information System (INIS)

Solodukha, V.A.; Snitovskij, Yu.P.

2015-01-01

In this article, a method for changing the silicon bipolar microwave power transistor's characteristics in a direct and deliberate manner by modifying the chemical composition at the molybdenum - silicon boundary, the electro-physical properties of molybdenum - silicon contacts, and the electrophysical characteristics of transistor structure areas by the phosphorus ions irradiation of generated ohmic molybdenum - silicon contacts to the transistor emitters is proposed for the first time. The possibilities of this method are investigated and confirmed experimentally. (authors)

Full-zone spectral envelope function formalism for the optimization of line and point tunnel field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Verreck, Devin, E-mail: devin.verreck@imec.be; Groeseneken, Guido [imec, Kapeldreef 75, 3001 Leuven (Belgium); Department of Electrical Engineering, KU Leuven, 3001 Leuven (Belgium); Verhulst, Anne S.; Mocuta, Anda; Collaert, Nadine; Thean, Aaron [imec, Kapeldreef 75, 3001 Leuven (Belgium); Van de Put, Maarten; Magnus, Wim [imec, Kapeldreef 75, 3001 Leuven (Belgium); Department of Physics, Universiteit Antwerpen, 2020 Antwerpen (Belgium); Sorée, Bart [imec, Kapeldreef 75, 3001 Leuven (Belgium); Department of Physics, Universiteit Antwerpen, 2020 Antwerpen (Belgium); Department of Electrical Engineering, KU Leuven, 3001 Leuven (Belgium)

2015-10-07

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In{sub 0.53}Ga{sub 0.47}As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET.

Controlling the mode of operation of organic transistors through side-chain engineering

KAUST Repository

Giovannitti, Alexander

2016-10-11

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors.

Controlling the mode of operation of organic transistors through side-chain engineering

Science.gov (United States)

Giovannitti, Alexander; Sbircea, Dan-Tiberiu; Inal, Sahika; Nielsen, Christian B.; Bandiello, Enrico; Hanifi, David A.; Sessolo, Michele; Malliaras, George G.; McCulloch, Iain; Rivnay, Jonathan

2016-01-01

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors. PMID:27790983

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

Science.gov (United States)

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Improving the performance of X-ray proportional counters by using field transistor preamplifiers

International Nuclear Information System (INIS)

Kalinina, N.I.; Mel'ttser, L.V.; Pan'kin, V.V.

1972-01-01

The possibility of using low-noise field-effect transistors with the n-channel in preamplifiers for x-ray proportional counters constitutes the object of this article. The operation of the preamplifier assembled according to the scheme of the voltage amplifier and charge-sensitive preamplifier has been studied. The use of the field-effect transistor with the n-channel in preamplifiers for proportional counters allows to improve significantly the energy resolution and operation at reduced voltage and at high loads. Notably good results have been obtained when constructing the circuit of the premplifier with the field-effect transistor on the charge-sensitive principle. The use of home-produced field-effect transistors makes it possible to construct detectors of roentgen radiometric instruments to measure light element content with proportional counters at reduced voltage

Growth-substrate induced performance degradation in chemically synthesized monolayer MoS{sub 2} field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Amani, Matin; Chin, Matthew L.; Mazzoni, Alexander L.; Burke, Robert A.; Dubey, Madan, E-mail: madan.dubey.civ@mail.mil [Sensors and Electron Devices Directorate, US Army Research Laboratory, Adelphi, Maryland 20723 (United States); Najmaei, Sina; Ajayan, Pulickel M.; Lou, Jun [Department of Materials Science and Nanoengineering, Rice University, Houston, Texas 77005 (United States)

2014-05-19

We report on the electronic transport properties of single-layer thick chemical vapor deposition (CVD) grown molybdenum disulfide (MoS{sub 2}) field-effect transistors (FETs) on Si/SiO{sub 2} substrates. MoS{sub 2} has been extensively investigated for the past two years as a potential semiconductor analogue to graphene. To date, MoS{sub 2} samples prepared via mechanical exfoliation have demonstrated field-effect mobility values which are significantly higher than that of CVD-grown MoS{sub 2}. In this study, we will show that the intrinsic electronic performance of CVD-grown MoS{sub 2} is equal or superior to that of exfoliated material and has been possibly masked by a combination of interfacial contamination on the growth substrate and residual tensile strain resulting from the high-temperature growth process. We are able to quantify this strain in the as-grown material using pre- and post-transfer metrology and microscopy of the same crystals. Moreover, temperature-dependent electrical measurements made on as-grown and transferred MoS{sub 2} devices following an identical fabrication process demonstrate the improvement in field-effect mobility.

Remaining Useful Life Estimation of Insulated Gate Biploar Transistors (IGBTs Based on a Novel Volterra k-Nearest Neighbor Optimally Pruned Extreme Learning Machine (VKOPP Model Using Degradation Data

Directory of Open Access Journals (Sweden)

Zhen Liu

2017-11-01

Full Text Available The insulated gate bipolar transistor (IGBT is a kind of excellent performance switching device used widely in power electronic systems. How to estimate the remaining useful life (RUL of an IGBT to ensure the safety and reliability of the power electronics system is currently a challenging issue in the field of IGBT reliability. The aim of this paper is to develop a prognostic technique for estimating IGBTs’ RUL. There is a need for an efficient prognostic algorithm that is able to support in-situ decision-making. In this paper, a novel prediction model with a complete structure based on optimally pruned extreme learning machine (OPELM and Volterra series is proposed to track the IGBT’s degradation trace and estimate its RUL; we refer to this model as Volterra k-nearest neighbor OPELM prediction (VKOPP model. This model uses the minimum entropy rate method and Volterra series to reconstruct phase space for IGBTs’ ageing samples, and a new weight update algorithm, which can effectively reduce the influence of the outliers and noises, is utilized to establish the VKOPP network; then a combination of the k-nearest neighbor method (KNN and least squares estimation (LSE method is used to calculate the output weights of OPELM and predict the RUL of the IGBT. The prognostic results show that the proposed approach can predict the RUL of IGBT modules with small error and achieve higher prediction precision and lower time cost than some classic prediction approaches.

Flexible Textile-Based Organic Transistors Using Graphene/Ag Nanoparticle Electrode

Science.gov (United States)

Kim, Youn; Kwon, Yeon Ju; Lee, Kang Eun; Oh, Youngseok; Um, Moon-Kwang; Seong, Dong Gi; Lee, Jea Uk

2016-01-01

Highly flexible and electrically-conductive multifunctional textiles are desirable for use in wearable electronic applications. In this study, we fabricated multifunctional textile composites by vacuum filtration and wet-transfer of graphene oxide films on a flexible polyethylene terephthalate (PET) textile in association with embedding Ag nanoparticles (AgNPs) to improve the electrical conductivity. A flexible organic transistor can be developed by direct transfer of a dielectric/semiconducting double layer on the graphene/AgNP textile composite, where the textile composite was used as both flexible substrate and conductive gate electrode. The thermal treatment of a textile-based transistor enhanced the electrical performance (mobility = 7.2 cm2·V−1·s−1, on/off current ratio = 4 × 105, and threshold voltage = −1.1 V) due to the improvement of interfacial properties between the conductive textile electrode and the ion-gel dielectric layer. Furthermore, the textile transistors exhibited highly stable device performance under extended bending conditions (with a bending radius down to 3 mm and repeated tests over 1000 cycles). We believe that our simple methods for the fabrication of graphene/AgNP textile composite for use in textile-type transistors can potentially be applied to the development of flexible large-area electronic clothes. PMID:28335276

Investigation on the electrical characteristics of a pentacene thin-film transistor and its reliability under positive drain bias stress

International Nuclear Information System (INIS)

Fan, Ching-Lin; Chiu, Ping-Cheng; Lin, Yu-Zuo; Yang, Tsung-Hsien; Chiang, Chin-Yuan

2011-01-01

This study systematically investigates the effects of pentacene deposition rates and channel lengths on the electrical characteristics of pentacene-based organic thin-film transistors (OTFTs), and the performance degradation of OTFTs under the positive drain bias stress. With a slower deposition rate of the pentacene channel layer, the larger grain size is formed, and it improves the performance of pentacene-based OTFTs. As the channel length decreases, the threshold voltage (V TH ) shifts toward the positive direction and the field-effect mobility (µ FE ) decreases, which are due to the drain-induced barrier lowering effect and the lower mobility in the active channel near the region of source/drain electrodes, respectively. In addition, we also propose a mechanism to present the channel length dependence on the field-effect mobility. Results also show that the pentacene-based OTFTs, which are under positive drain bias stress, exhibit greater performance degradation than those under negative drain bias stress. The greater performance degradation, the decreasing I ON and the larger V TH shift are due to the greater trap state density (N trap ) created in the bulk channel by the large lateral electrical field and the carriers injected into the gate insulator by the large vertical electrical field, respectively

Celebrating 65th Anniversary of the Transistor

Directory of Open Access Journals (Sweden)

Goce L. Arsov

2013-12-01

Full Text Available The paper is dedicated to the 65th anniversary of the invention of the revolutionary electronic component that actually changed our way of life—the transistor. It recounts the key historical moments leading up to the invention of the first semiconductor active component in 1947. The meaning of the blend “transistor” is explained using the memorandum issued by Bell Telephone Laboratories. Certain problems appeared in the engineering phase of the transistor development and the new components obtained as a result of this research are reviewed. The impact of this invention on the development of power electronics is being emphasized. Finally, the possibility that the most important invention of the 20th century has been conceived not once but twice is discussed.

Quantum engineering of transistors based on 2D materials heterostructures

Science.gov (United States)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Nanowire transistors physics of devices and materials in one dimension

CERN Document Server

Colinge, Jean-Pierre

2016-01-01

From quantum mechanical concepts to practical circuit applications, this book presents a self-contained and up-to-date account of the physics and technology of nanowire semiconductor devices. It includes a unified account of the critical ideas central to low-dimensional physics and transistor physics which equips readers with a common framework and language to accelerate scientific and technological developments across the two fields. Detailed descriptions of novel quantum mechanical effects such as quantum current oscillations, the metal-to-semiconductor transition and the transition from classical transistor to single-electron transistor operation are described in detail, in addition to real-world applications in the fields of nanoelectronics, biomedical sensing techniques, and advanced semiconductor research. Including numerous illustrations to help readers understand these phenomena, this is an essential resource for researchers and professional engineers working on semiconductor devices and materials in ...

Carbon nanotubes field-effect transistor for rapid detection of DHA

International Nuclear Information System (INIS)

Nguyen Thi Thuy; Nguyen Duc Chien; Mai Anh Tuan

2012-01-01

This paper presents the development of DNA sensor based on a network carbon nanotubes field effect transistor (CNTFETs) for Escherichia coli bacteria detection. The DNA sequences were immobilized on single-walled carbon nanotubes of transistor CNTFETs by using absorption. The hybridization of the DNA probe sequences and complementary DNA strands was detected by electrical conductance change from the electron doping by DNA hybridization directly on the carbon nanotubes leading to the change in the metal-CNTs barrier energy through the modulation of the electrode work function of carbon nanotubes field effect transistor. The results showed that the response time of DNA sensor was approximately 1 min and the sensitivity of DNA sensor was at 0.565 μA/nM; the detection limit of the sensor was about 1 pM of E. coli bacteria sample. (author)

Quantum engineering of transistors based on 2D materials heterostructures.

Science.gov (United States)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application.

Science.gov (United States)

Liang, Xuelei; Xia, Jiye; Dong, Guodong; Tian, Boyuan; Peng, Lianmao

2016-12-01

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

P-type Cu2O/SnO bilayer thin film transistors processed at low temperatures

KAUST Repository

Al-Jawhari, Hala A.

2013-10-09

P-type Cu2O/SnO bilayer thin film transistors (TFTs) with tunable performance were fabricated using room temperature sputtered copper and tin oxides. Using Cu2O film as capping layer on top of a SnO film to control its stoichiometry, we have optimized the performance of the resulting bilayer transistor. A transistor with 10 nm/15 nm Cu2O to SnO thickness ratio (25 nm total thickness) showed the best performance using a maximum process temperature of 170 C. The bilayer transistor exhibited p-type behavior with field-effect mobility, on-to-off current ratio, and threshold voltage of 0.66 cm2 V-1 s-1, 1.5×10 2, and -5.2 V, respectively. The advantages of the bilayer structure relative to single layer transistor are discussed. © 2013 American Chemical Society.

Carbon Based Transistors and Nanoelectronic Devices

Science.gov (United States)

Rouhi, Nima

Carbon based materials (carbon nanotube and graphene) has been extensively researched during the past decade as one of the promising materials to be used in high performance device technology. In long term it is thought that they may replace digital and/or analog electronic devices, due to their size, near-ballistic transport, and high stability. However, a more realistic point of insertion into market may be the printed nanoelectronic circuits and sensors. These applications include printed circuits for flexible electronics and displays, large-scale bendable electrical contacts, bio-membranes and bio sensors, RFID tags, etc. In order to obtain high performance thin film transistors (as the basic building block of electronic circuits) one should be able to manufacture dense arrays of all semiconducting nanotubes. Besides, graphene synthesize and transfer technology is in its infancy and there is plenty of room to improve the current techniques. To realize the performance of nanotube and graphene films in such systems, we need to economically fabricate large-scale devices based on these materials. Following that the performance control over such devices should also be considered for future design variations for broad range of applications. Here we have first investigated carbon nanotube ink as the base material for our devices. The primary ink used consisted of both metallic and semiconducting nanotubes which resulted in networks suitable for moderate-resistivity electrical connections (such as interconnects) and rfmatching circuits. Next, purified all-semiconducting nanotube ink was used to fabricate waferscale, high performance (high mobility, and high on/off ratio) thin film transistors for printed electronic applications. The parameters affecting device performance were studied in detail to establish a roadmap for the future of purified nanotube ink printed thin film transistors. The trade of between mobility and on/off ratio of such devices was studied and the

Optomechanical transistor with mechanical gain

Science.gov (United States)

Zhang, X. Z.; Tian, Lin; Li, Yong

2018-04-01

We study an optomechanical transistor, where an input field can be transferred and amplified unidirectionally in a cyclic three-mode optomechanical system. In this system, the mechanical resonator is coupled simultaneously to two cavity modes. We show that it only requires a finite mechanical gain to achieve the nonreciprocal amplification. Here the nonreciprocity is caused by the phase difference between the linearized optomechanical couplings that breaks the time-reversal symmetry of this system. The amplification arises from the mechanical gain, which provides an effective phonon bath that pumps the mechanical mode coherently. This effect is analogous to the stimulated emission of atoms, where the probe field can be amplified when its frequency is in resonance with that of the anti-Stokes transition. We show that by choosing optimal parameters, this optomechanical transistor can reach perfect unidirectionality accompanied with strong amplification. In addition, the presence of the mechanical gain can result in ultralong delay in the phase of the probe field, which provides an alternative to controlling light transport in optomechanical systems.

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

Science.gov (United States)

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

Science.gov (United States)

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Liquid–Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

KAUST Repository

Zhang, Yu

2017-10-17

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

Science.gov (United States)

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Concept of rewritable organic ferroelectric random access memory in two lateral transistors-in-one cell architecture

International Nuclear Information System (INIS)

Kim, Min-Hoi; Lee, Gyu Jeong; Keum, Chang-Min; Lee, Sin-Doo

2014-01-01

We propose a concept of rewritable ferroelectric random access memory (RAM) with two lateral organic transistors-in-one cell architecture. Lateral integration of a paraelectric organic field-effect transistor (OFET), being a selection transistor, and a ferroelectric OFET as a memory transistor is realized using a paraelectric depolarizing layer (PDL) which is patterned on a ferroelectric insulator by transfer-printing. For the selection transistor, the key roles of the PDL are to reduce the dipolar strength and the surface roughness of the gate insulator, leading to the low memory on–off ratio and the high switching on–off current ratio. A new driving scheme preventing the crosstalk between adjacent memory cells is also demonstrated for the rewritable operation of the ferroelectric RAM. (paper)

Laser-Printed Organic Thin-Film Transistors

KAUST Repository

Diemer, Peter J.

2017-09-20

Solution deposition of organic optoelectronic materials enables fast roll-to-roll manufacturing of photonic and electronic devices on any type of substrate and at low cost. But controlling the film microstructure when it crystallizes from solution can be challenging. This represents a major limitation of this technology, since the microstructure, in turn, governs the charge transport properties of the material. Further, the solvents typically used are hazardous, which precludes their incorporation in large-scale manufacturing processes. Here, the first ever organic thin-film transistor fabricated with an electrophotographic laser printing process using a standard office laser printer is reported. This completely solvent-free additive manufacturing method allows for simultaneous deposition, purification, and patterning of the organic semiconductor layer. Laser-printed transistors using triisopropylsilylethynyl pentacene as the semiconductor layer are realized on flexible substrates and characterized, making this a successful first demonstration of the potential of laser printing of organic semiconductors.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity

International Nuclear Information System (INIS)

Li Jinjin; Zhu Kadi

2011-01-01

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity.

Science.gov (United States)

Li, Jin-Jin; Zhu, Ka-Di

2011-02-04

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

Improved electrical stability of CdS thin film transistors through Hydrogen-based thermal treatments

KAUST Repository

Salas Villaseñor, Ana L.

2014-06-01

Thin film transistors (TFTs) with a bottom-gate configuration were fabricated using a photolithography process with chemically bath deposited (CBD) cadmium sulfide (CdS) films as the active channel. Thermal annealing in hydrogen was used to improve electrical stability and performance of the resulting CdS TFTs. Hydrogen thermal treatments results in significant V T instability (V T shift) improvement while increasing the I on/I off ratio without degrading carrier mobility. It is demonstrated that after annealing V T shift and I on/I off improves from 10 V to 4.6 V and from 105 to 10 9, respectively. Carrier mobility remains in the order of 14.5 cm2 V s-1. The reduced V T shift and performance is attributed to a reduction in oxygen species in the CdS after hydrogen annealing, as evaluated by Fourier transform infrared spectroscopy (FTIR). © 2014 IOP Publishing Ltd.

Improved electrical stability of CdS thin film transistors through Hydrogen-based thermal treatments

KAUST Repository

Salas Villaseñ or, Ana L.; Mejia, Israel I.; Sotelo-Lerma, Mé rida; Guo, Zaibing; Alshareef, Husam N.; Quevedo-Ló pez, Manuel Angel Quevedo

2014-01-01

Thin film transistors (TFTs) with a bottom-gate configuration were fabricated using a photolithography process with chemically bath deposited (CBD) cadmium sulfide (CdS) films as the active channel. Thermal annealing in hydrogen was used to improve electrical stability and performance of the resulting CdS TFTs. Hydrogen thermal treatments results in significant V T instability (V T shift) improvement while increasing the I on/I off ratio without degrading carrier mobility. It is demonstrated that after annealing V T shift and I on/I off improves from 10 V to 4.6 V and from 105 to 10 9, respectively. Carrier mobility remains in the order of 14.5 cm2 V s-1. The reduced V T shift and performance is attributed to a reduction in oxygen species in the CdS after hydrogen annealing, as evaluated by Fourier transform infrared spectroscopy (FTIR). © 2014 IOP Publishing Ltd.

Oxide Semiconductor-Based Flexible Organic/Inorganic Hybrid Thin-Film Transistors Fabricated on Polydimethylsiloxane Elastomer.

Science.gov (United States)

Jung, Soon-Won; Choi, Jeong-Seon; Park, Jung Ho; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lim, Sang Chul; Lee, Sang Seok; Chu, Hye Yong

2016-03-01

We demonstrate flexible organic/inorganic hybrid thin-film transistors (TFTs) on a polydimethysilox- ane (PDMS) elastomer substrate. The active channel and gate insulator of the hybrid TFT are composed of In-Ga-Zn-O (IGZO) and blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF- TrFE)] with poly(methyl methacrylate) (PMMA), respectively. It has been confirmed that the fabri- cated TFT display excellent characteristics: the recorded field-effect mobility, sub-threshold voltage swing, and I(on)/I(off) ratio were approximately 0.35 cm2 V(-1) s(-1), 1.5 V/decade, and 10(4), respectively. These characteristics did not experience any degradation at a bending radius of 15 mm. These results correspond to the first demonstration of a hybrid-type TFT using an organic gate insulator/oxide semiconducting active channel structure fabricated on PDMS elastomer, and demonstrate the feasibility of a promising device in a flexible electronic system.

Vertically aligned carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi; Zhao, Chao; Wang, Qingxiao; Zhang, Qiang; Wang, Zhihong; Zhang, Xixiang; Abutaha, Anas I.; Alshareef, Husam N.

2012-01-01

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been developed using pure semiconducting carbon nanotubes. The source and drain were vertically stacked, separated by a dielectric, and the carbon nanotubes were placed

VO2-based radiative thermal transistor with a semi-transparent base

Science.gov (United States)

Prod'homme, Hugo; Ordonez-Miranda, Jose; Ezzahri, Younès; Drévillon, Jérémie; Joulain, Karl

2018-05-01

We study a radiative thermal transistor analogous to an electronic one made of a VO2 base placed between two silica semi-infinite plates playing the roles of the transistor collector and emitter. The fact that VO2 exhibits an insulator to metal transition is exploited to modulate and/or amplify heat fluxes between the emitter and the collector, by applying a thermal current on the VO2 base. We extend the work of precedent studies considering the case where the base can be semi-transparent so that heat can be exchanged directly between the collector and the emitter. Both near and far field cases are considered leading to 4 typical regimes resulting from the fact that the emitter-base and base-collector separation distances can be larger or smaller than the thermal wavelength for a VO2 layer opaque or semi-transparent. Thermal currents variations with the base temperatures are calculated and analyzed. It is found that the transistor can operate in an amplification mode as already stated in [1] or in a switching mode as seen in [2]. An optimum configuration for the base thickness and separation distance maximizing the thermal transistor modulation factor is found.