A PMSM current controller system on FPGA platform | Ahmadian ...

African Journals Online (AJOL)

Journal of Fundamental and Applied Sciences ... Proposed system architecture and computational blocks are described and system level and RTL simulation results are presented. Simulation results show that the total computation cycle time of implemented system on Altera Cyclone II FPGA is 456ns. Keywords: PMSM ...

Non-Linear Detection for Joint Space-Frequency Block Coding and Spatial Multiplexing in OFDM-MIMO Systems

DEFF Research Database (Denmark)

Rahman, Imadur Mohamed; Marchetti, Nicola; Fitzek, Frank

2005-01-01

(SIC) receiver where the detection is done on subcarrier by sub-carrier basis based on both Zero Forcing (ZF) and Minimum Mean Square Error (MMSE) nulling criterion for the system. In terms of Frame Error Rate (FER), MMSE based SIC receiver performs better than all other receivers compared......In this work, we have analyzed a joint spatial diversity and multiplexing transmission structure for MIMO-OFDM system, where Orthogonal Space-Frequency Block Coding (OSFBC) is used across all spatial multiplexing branches. We have derived a BLAST-like non-linear Successive Interference Cancellation...... in this paper. We have found that a linear two-stage receiver for the proposed system [1] performs very close to the non-linear receiver studied in this work. Finally, we compared the system performance in spatially correlated scenario. It is found that higher amount of spatial correlation at the transmitter...

FPGA Implementation of Heart Rate Monitoring System.

Science.gov (United States)

Panigrahy, D; Rakshit, M; Sahu, P K

2016-03-01

This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

A demonstration of a Time Multiplexed Trigger for the CMS experiment

Energy Technology Data Exchange (ETDEWEB)

Frazier, R; Newbold, D [University of Bristol, H.H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Fayer, S; Hall, G; Hunt, C; Iles, G; Rose, A [Imperial College London, Blackett Laboratory, Prince Consort Road, London SW7 2BW (United Kingdom)

2012-01-15

A novel approach to first-level hardware triggering in the LHC experiments has been studied and a prototype system built. Calorimeter trigger primitive data ( {approx} 5 Tb/s) are re-organised and time-multiplexed so that a single processing node (FPGA) may access the data corresponding to the entire detector for a given bunch crossing. This provides maximal flexibility in the construction of new trigger algorithms, which will be an important factor in ensuring adequate trigger performance at the very high levels of background expected at the upgraded LHC. A test system that incorporates all the key technologies for a final system and demonstrates the time-multiplexing and algorithm performance is presented.

Readout Unit-FPGA version for link multipexers, DAQ and VELO trigger

CERN Document Server

Müller, H; Guirao, A; Bal, F

2003-01-01

The FPGA-based Readout Unit (RU) was designed as entry stage to the readout networks of the LHCb data acquisition and L1-VELO topology trigger systems. The RU performs subevent building from up to 16 custom S-link inputs towards a commercial readout network via a PCI interface card. For output to custom links, as required in datalink multiplexer applications, an output S-link transmitter interface is alternatively available. Baseline readout networks for the RU are intelligent Gbit-ethernet NIC cards for the DAQ system and SCI shared memory network for the L1-VELO system. Any new protocols, like 10Gbit ethernet or Infiniband may be adopted as far as proper PCI interfaces and Linux device drivers will become available. The two baseline RU modes of operation are: 1.) link-multiplexer with N*Slink to single-Slink 2.) eventbuilder interface with quad Slink-to-PCI network interface.

High-speed real-time OFDM transmission based on FPGA

Science.gov (United States)

Xiao, Xin; Li, Fan; Yu, Jianjun

2016-02-01

In this paper, we review our recent research progresses on real-time orthogonal frequency division multiplexing (OFDM) transmission based on FPGA. We successfully demonstrated four-channel wavelength-division multiplexing (WDM) 256.51Gb/s 16-ary quadrature amplitude modulation (16QAM)-OFDM signal transmission system for short-reach optical amplifier free inter-connection with real-time reception. Four optical carriers are modulated by four different 16QAM-OFDM signals via 10G-class direct modulation lasers (DMLs). We achieved highest capacity real-time reception optical OFDM signal transmission over 2.4-km SMF with the bit-error ratio (BER) under soft-decision forward error correction (SD-FEC) limitation of 2.4×10-2. In order to achieve higher spectrum efficiency (SE), we demonstrate 4-channel high level QAM-OFDM transmission over 20-km SMF-28 with real-time reception. 58.72-Gb/s 256QAM-OFDM and 56.4-Gb/s 128QAM-OFDM signal transmission within 25-GHz grid is achieved with the BER under 2.4×10-2 and real-time reception.

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

Directory of Open Access Journals (Sweden)

Srilata Raman

1996-01-01

Full Text Available In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.

SEU mitigation exploratory tests in a ITER related FPGA

International Nuclear Information System (INIS)

Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, José G.; Teixeira, Isabel C.; Teixeira, João P.; Sousa, Jorge; Gonçalves, Bruno

2017-01-01

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

SEU mitigation exploratory tests in a ITER related FPGA

Energy Technology Data Exchange (ETDEWEB)

Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

2017-05-15

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

FPGA Implementation of a SAR Two-dimensional Autofocus Approach

Directory of Open Access Journals (Sweden)

Guo Jiangzhe

2016-08-01

Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

FPGA design

CERN Document Server

Simpson, Philip

2010-01-01

This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

Evaluation of radiation tolerance of TMR designs in SRAM-based FPGA.

CERN Document Server

Shibin, Konstantin

2016-01-01

During the Summer Student program in CERN I was working in the CMS Muon Drift Tube group, building a setup for evaluating the radiation tolerance of the drift tube signal encoding hardware (Time-to-Digital Converter, TDC) implemented in SRAM-based FPGA using Triple Modular Redundancy (TMR). While commercially available SRAM-based FPGAs have more computational power, are more advanced in general than flash-based FPGAs and are the most suitable technology for implementing the TDC logic (also taking into account the performance requirements), in the context of operation inside an environment with high levels of ionizing radiation (such as inside CMS DT detector) they are more susceptible to configuration memory bit flips – Single Event Upsets (SEUs) - due to lower required energy for a memory bit being flipped. The effect of a SEU inside the configuration memory might change the functionality of the underlying building blocks of FPGA and if the respective blocks were involved in implementing the desired custom...

Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

Science.gov (United States)

Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

2018-02-01

In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

FPGA programming using FX3

CERN Document Server

Calleja, Stefano

2014-01-01

An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

Science.gov (United States)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed

Interfacing Hardware Accelerators to a Time-Division Multiplexing Network-on-Chip

DEFF Research Database (Denmark)

Pezzarossa, Luca; Sørensen, Rasmus Bo; Schoeberl, Martin

2015-01-01

This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors in ...... implementation. The design evaluation is carried out using the open source T-CREST multi-core platform implemented on an Altera Cyclone IV FPGA. The size of the proposed design, including a floating-point accelerator, is about two-thirds of a processor....

Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

Science.gov (United States)

Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

2004-06-01

Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

ULTRASOUND GUIDED ILIOINGUINAL AND ILIOHYPOGASTRIC NERVE BLOCK FOR INGUINAL HERNIA REPAIR IN ARTHROGRYPOSIS MULTIPLEX CONGENITA

Directory of Open Access Journals (Sweden)

Paul O.

2015-06-01

Full Text Available Arthrogryposis multiplex congenita (AMC refers to a syndrome of unknown etiology with multiple congenital contractures in one or more joints with a concomitant inability of passive extension and flexion . The overall prevalence of arthrogryposis is one in 3000 live births . The extensive contractures , tense skin , minimal muscle mass and subcutaneous tissue pose challenges in anaesthetic management. We report a seven year old boy (15 kg , known case of AMC with congenital talipes equino varus (CTEV and bilateral hip dislocation posted for right sided herniot omy and orchidopexy. We planned to combine general anaesthesia without muscle relaxants and regional nerve block. The child was induced with propofol and Classic LMA Size 2 was inserted. An ilioinguinal and i liohypogastric nerve block was given under ultrasound guidance using 0.2% ropivacaine. Pateint remained hemodynamically stable during surgery with minimal anaesthetic requirement and no anlgesics. Analgesia lasted for 8 hours postoperatively. Combining narcosis with regional anaesthesia leads to a reduced demand for anaesthetics , stable circulatory conditions , maintenance of spontaneous breathing , prevention of stress and sufficient postoperative analgesia

Adaptive Hardware Cryptography Engine Based on FPGA

International Nuclear Information System (INIS)

Afify, M.A.A.

2011-01-01

In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

The FPGA Pixel Array Detector

International Nuclear Information System (INIS)

Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

2013-01-01

A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

Directory of Open Access Journals (Sweden)

Peter Irgens

2017-04-01

Full Text Available We present an field programmable gate arrays (FPGA based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

Test results of an ITER relevant FPGA when irradiated with neutrons

Energy Technology Data Exchange (ETDEWEB)

Batista, Antonio J. N.; Santos, Bruno; Fernandes, Ana; Goncalves, Bruno [Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Leong, Carlos; Teixeira, Joao P. [Instituto de Engenharia de Sistemas e Computadores - Investigacao e Desenvolvimento, 1000-029 Lisboa, (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, Jose G. [Centro de Ciencias e Tecnologias Nucleares, Instituto Superior Tecnico, Universidade de Lisboa, 2695-066 Bobadela, (Portugal)

2015-07-01

The data acquisition and control instrumentation cubicles room of the ITER tokamak will be irradiated with neutrons during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I and C products - Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in state elements of the FPGA. The SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. Novel SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. The results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories. (authors)

Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGA

Directory of Open Access Journals (Sweden)

SKLYAROV, V.

2014-05-01

Full Text Available This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations. Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.

Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-05-23

The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

Implementation of FPGA-Based Diverse Protection System

International Nuclear Information System (INIS)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

2015-01-01

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

Implementation of FPGA-Based Diverse Protection System

Energy Technology Data Exchange (ETDEWEB)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

2015-10-15

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

Tethered Forth system for FPGA applications

Science.gov (United States)

Goździkowski, Paweł; Zabołotny, Wojciech M.

2013-10-01

This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

Design and Performance of the Multiplexed SQUID/TES Array at Ninety Gigahertz

Science.gov (United States)

Stanchfield, Sara; Ade, Peter; Aguirre, James; Brevik, Justus A.; Cho, Hsiao-Mei; Datta, Rahul; Devlin, Mark; Dicker, Simon R.; Dober, Bradley; Duff, Shannon M.; Egan, Dennis; Ford, Pam; Hilton, Gene; Hubmayr, Johannes; Irwin, Kent; Knowles, Kenda; Marganian, Paul; Mason, Brian Scott; Mates, John A. B.; McMahon, Jeff; Mello, Melinda; Mroczkowski, Tony; Romero, Charles; Sievers, Jonathon; Tucker, Carole; Vale, Leila R.; Vissers, Michael; White, Steven; Whitehead, Mark; Ullom, Joel; Young, Alexander

2018-01-01

We present the array performance and astronomical images from early science results from MUSTANG-2, a 90 GHz feedhorn-coupled, microwave SQUID-multiplexed TES bolometer array operating on the Robert C. Byrd Green Bank Telescope (GBT). MUSTANG-2 was installed on the GBT on December 2, 2016 and immediately began commissioning efforts, followed by science observations, which are expected to conclude June 2017. The feedhorn and waveguide-probe-coupled detector technology is a mature technology, which has been used on instrument including the South Pole Telescope, the Atacama Cosmology Telescope, and the Atacama B-mode Search telescope. The microwave SQUID readout system developed for MUSTANG-2 currently reads out 66 detectors with a single coaxial cable and will eventually allow thousands of detectors to be multiplexed. This microwave SQUID multiplexer combines the proven abilities of millimeterwave TES detectors with the multiplexing capabilities of KIDs with no degradation in noise performance of the detectors. Each multiplexing device is read out using warm electronics consisting of a commercially available ROACH board, a DAC/ADC card, and an Intermediate Frequency mixer circuit. The hardware was originally developed by the UC Berkeley Collaboration for Astronomy Signal Processing and Electronic Research (CASPER) group, whose primary goal is to develop scalable FPGA-based hardware with the flexibility to be used in a wide range of radio signal processing applications. MUSTANG-2 is the first on-sky instrument to use microwave SQUID multiplexing and is available as a shared-risk/PI instrument on the GBT. In MUSTANG-2's first season 7 separate proposals were awarded a total of 230 hours of telescope time.

Qualification of FPGA-Based Safety-Related PRM System

International Nuclear Information System (INIS)

Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

2011-01-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

A FPGA Implementation of the CAR-FAC Cochlear Model

Directory of Open Access Journals (Sweden)

Ying Xu

2018-04-01

Full Text Available This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC cochlear model. The CAR part simulates the basilar membrane's (BM response to sound. The FAC part models the outer hair cell (OHC, the inner hair cell (IHC, and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

A FPGA Implementation of the CAR-FAC Cochlear Model.

Science.gov (United States)

Xu, Ying; Thakur, Chetan S; Singh, Ram K; Hamilton, Tara Julia; Wang, Runchun M; van Schaik, André

2018-01-01

This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

Flexible experimental FPGA based platform

DEFF Research Database (Denmark)

Andersen, Karsten Holm; Nymand, Morten

2016-01-01

This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

Autonomous Lawnmower using FPGA implementation.

Science.gov (United States)

Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

2016-11-01

Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

Natrium: Use of FPGA embedded processors for real-time data compression

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

2011-12-15

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Natrium: Use of FPGA embedded processors for real-time data compression

International Nuclear Information System (INIS)

Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2011-01-01

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

FPGA based, modular, configurable controller with fast synchronous optical network

Energy Technology Data Exchange (ETDEWEB)

Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

2006-07-01

The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

FPGA based, modular, configurable controller with fast synchronous optical network

International Nuclear Information System (INIS)

Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S.

2006-01-01

The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

Prototype data terminal-multiplexer/demultiplexer

Science.gov (United States)

Leck, D. E.; Goodwin, J. E.

1972-01-01

The design and operation of a quad redundant data terminal and a multiplexer/demultiplexer (MDU) is described. The most unique feature is the design of the quad redundant data terminal. This is one of the few designs where the unit is fail/op, fail/op, fail/safe. Laboratory tests confirm that the unit will operate satisfactorily with the failure of three out of four channels. Although the design utilizes state-of-the-art technology, the waveform error checks, the voting techniques, and the parity bit checks are believed to be used in unique configurations. Correct word selection routines are also novel. The MDU design, while not redundant, utilizes, the latest state-of-the-art advantages of light coupler and interested amplifiers. Much of the technology employed was an evolution of prior NASA contracts related to the Addressable Time Division Data System. A good example of the earlier technology development was the development of a low level analog multiplexer, a high level analog multiplexer, and a digital multiplexer. A list of all drawings is included for reference and all schematic, block and timing diagrams are incorporated.

Efficient FPGA Implementation of a STBC-OFDM Combiner for an IEEE 802.16 Software Radio Receiver

DEFF Research Database (Denmark)

Cattoni, Andrea Fabio; Le Moullec, Yannick; Sacchi, Claudio

2014-01-01

In this paper, an efficient FPGA implementation of a 4x4 Space-Time Block Coding (STBC) combiner for MIMO-OFDM software radio receivers is considered. The proposed combiner is based on a low-complexity algorithm which reduces the interference due to the Quasi-Orthogonality of the STBC decoding...

Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection

Directory of Open Access Journals (Sweden)

BHUVANESWARI, M. C.

2013-11-01

Full Text Available FPGAs are increasingly being used to implement data path intensive algorithms for signal processing and image processing applications. In High Level Synthesis of Data Flow Graphs targeted at FPGAs, the effect of interconnect resources such as multiplexers must be considered since they contribute significantly to the area and switching power. We propose a binding framework for behavioral synthesis of Data Flow Graphs (DFGs onto FPGA targets with power reduction as the main criterion. The technique uses a multi-objective GA, NSGA II for design space exploration to identify schedules that have the potential to yield low-power bindings from a population of non-dominated solutions. A greedy constructive binding technique reported in the literature is adapted for interconnect minimization. The binding is further subjected to a perturbation process by altering the register and multiplexer assignments. Results obtained on standard DFG benchmarks indicate that our technique yields better power aware bindings than the constructive binding approach with little or no area overhead.

FPGA Design and Implementation of a Rangefinder

Directory of Open Access Journals (Sweden)

ALBU Răzvan-Daniel

2017-10-01

Full Text Available In this paper we will present the design and implementation of an ultrasonic non-contact rangefinder with FPGA. This rangefinder can be used in numerous applications, ranging from hardly accessible spaces to electromagnetically polluted environments. The experimental implementations proved to be accurate, portable, and easy to operate. Attributable to their programmable nature, FPGAs are an ideal fit for many dissimilar markets. Even though FPGAs used to be designated for lower speed and complexity designs in the past, today’s FPGAs effortlessly push the 500 MHz performance barricade. Since they bring features, such as embedded processors, DSP blocks, clocking, and high-speed serial at lower prices, FPGAs are a convincing alternative for almost any type of design.

Protection and Control with FPGA technology

Energy Technology Data Exchange (ETDEWEB)

Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-03-15

To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

Protection and Control with FPGA technology

International Nuclear Information System (INIS)

Sohn, K. Y.; Yi, W. J.; Koo, I. S.

2012-01-01

To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

FPGA-based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

Science.gov (United States)

Perkuszewski, Karol; Pozniak, Krzysztof T.; Jalmuzna, Wojciech; Koprek, Waldemar; Szewinski, Jaroslaw; Romaniuk, Ryszard S.; Simrock, Stefan

2006-10-01

The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented.

FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

International Nuclear Information System (INIS)

Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S.

2006-01-01

The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

Energy Technology Data Exchange (ETDEWEB)

Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems; Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

2006-07-01

The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

Directory of Open Access Journals (Sweden)

P. Fiala

2015-09-01

Full Text Available This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.

Irradiation test of FPGA for BES III

International Nuclear Information System (INIS)

Chen Yixin; Liang Hao; Xue Jundong; Liu Baoying; Liu Qiang; Yu Xiaoqi; Zhou Yongzhao; Hou Long

2005-01-01

The irradiation effect of FPGA, applied in Front-end Electronics for experiments of High-Energy Physics, is a serious problem. The performance of FPGA, used in the front-end card of Muon Counters of BES III project, needs to be evaluated under irradiation. SEUs on Altera ACEX 1K FPGA, observed in the experiment under the irradiation of γ ray, 14 and 2.5 MeV neutrons, was investigated. The authors calculated involved cross-section and provided reasonable analysis and evaluation for the result of the experiment. The conclusion about feasibility of applying ACEX 1K FPGA in the front-end card of the readout system of Muon Counters for BES III was given. (authors)

Development of FPGA-Based Control Board

Energy Technology Data Exchange (ETDEWEB)

Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

2009-10-15

It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

Exploration of Heterogeneous FPGA Architectures

Directory of Open Access Journals (Sweden)

Umer Farooq

2011-01-01

mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

Implementation of T-box/T/sup -1/-box based AES design on latest xilinx fpga

International Nuclear Information System (INIS)

Kundi, D.E.; Aziz, A.

2015-01-01

This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption. (author)

Study on FPGA SEU Mitigation for the Readout Electronics of DAMPE BGO Calorimeter in Space

Science.gov (United States)

Shen, Zhongtao; Feng, Changqing; Gao, Shanshan; Zhang, Deliang; Jiang, Di; Liu, Shubin; An, Qi

2015-06-01

The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of the Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based field-programmable gate array (FPGA), of which the design-level flip-flops and embedded block random access memories (RAM) are single event upset (SEU) sensitive in the harsh space environment. To comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

The MCD circuit based on FPGA

International Nuclear Information System (INIS)

Vu Quoc Trong

2003-01-01

Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

Real-time FPGA architectures for computer vision

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2000-03-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

High-Throughput Block Optical DNA Sequence Identification.

Science.gov (United States)

Sagar, Dodderi Manjunatha; Korshoj, Lee Erik; Hanson, Katrina Bethany; Chowdhury, Partha Pratim; Otoupal, Peter Britton; Chatterjee, Anushree; Nagpal, Prashant

2018-01-01

Optical techniques for molecular diagnostics or DNA sequencing generally rely on small molecule fluorescent labels, which utilize light with a wavelength of several hundred nanometers for detection. Developing a label-free optical DNA sequencing technique will require nanoscale focusing of light, a high-throughput and multiplexed identification method, and a data compression technique to rapidly identify sequences and analyze genomic heterogeneity for big datasets. Such a method should identify characteristic molecular vibrations using optical spectroscopy, especially in the "fingerprinting region" from ≈400-1400 cm -1 . Here, surface-enhanced Raman spectroscopy is used to demonstrate label-free identification of DNA nucleobases with multiplexed 3D plasmonic nanofocusing. While nanometer-scale mode volumes prevent identification of single nucleobases within a DNA sequence, the block optical technique can identify A, T, G, and C content in DNA k-mers. The content of each nucleotide in a DNA block can be a unique and high-throughput method for identifying sequences, genes, and other biomarkers as an alternative to single-letter sequencing. Additionally, coupling two complementary vibrational spectroscopy techniques (infrared and Raman) can improve block characterization. These results pave the way for developing a novel, high-throughput block optical sequencing method with lossy genomic data compression using k-mer identification from multiplexed optical data acquisition. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FPGA based computation of average neutron flux and e-folding period for start-up range of reactors

International Nuclear Information System (INIS)

Ram, Rajit; Borkar, S.P.; Dixit, M.Y.; Das, Debashis

2013-01-01

Pulse processing instrumentation channels used for reactor applications, play a vital role to ensure nuclear safety in startup range of reactor operation and also during fuel loading and first approach to criticality. These channels are intended for continuous run time computation of equivalent reactor core neutron flux and e-folding period. This paper focuses only the computational part of these instrumentation channels which is implemented in single FPGA using 32-bit floating point arithmetic engine. The computations of average count rate, log of average count rate, log rate and reactor period are done in VHDL using digital circuit realization approach. The computation of average count rate is done using fully adaptive window size moving average method, while Taylor series expansion for logarithms is implemented in FPGA to compute log of count rate, log rate and reactor e-folding period. This paper describes the block diagrams of digital logic realization in FPGA and advantage of fully adaptive window size moving average technique over conventional fixed size moving average technique for pulse processing of reactor instrumentations. (author)

From OO to FPGA :

Energy Technology Data Exchange (ETDEWEB)

Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

2012-09-01

Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

Development of FPGA-based safety-related I and C systems

Energy Technology Data Exchange (ETDEWEB)

Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

2006-07-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

FPGA fabric specific optimization for RLT design

International Nuclear Information System (INIS)

Perwaiz, A.; Khan, S.A.

2010-01-01

This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

Realise of PWM-generating based on FPGA

International Nuclear Information System (INIS)

Su Rongfeng; Xu Ruinian; Huang Maomao

2012-01-01

The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

Energy Technology Data Exchange (ETDEWEB)

Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

2013-05-15

In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

Online data reduction with FPGA-based track reconstruction for the Belle II DEPFET pixel detector

Energy Technology Data Exchange (ETDEWEB)

Deschamps, Bruno; Wessel, Christian; Marinas, Carlos; Dingfelder, Jochen [Physikalisches Institut, Universitaet Bonn (Germany)

2016-07-01

The innermost two layers of the Belle II vertex detector at the KEK facility in Tsukuba, Japan, will be covered by high-granularity DEPFET pixel sensors (PXD). The large number of pixels leads to a maximum data rate of 256 Gbps, which has to be significantly reduced by the Data Acquisition System (DATCON). For the data reduction the hit information of the surrounding Silicon strip Vertex Detector (SVD) is utilized to define so-called Regions of Interest (ROI). Only hit information of the pixels located inside these ROIs are saved. The ROIs for the PXD are computed by reconstructing track segments from SVD data and extrapolation to the PXD. The goal is to achieve a data reduction of at least a factor of 10 with this ROI selection. All the necessary processing stages, the receiving, decoding and multiplexing of SVD data on 48 optical fibers, the track reconstruction and the definition of the ROIs, will be performed by the presented system. The planned hardware design is based on a distributed set of Advanced Mezzanine Cards (AMC) each equipped with a Field Programmable Gate Array (FPGA) and 4 optical transceivers. In this talk, the status and plans for the DATCON prototype and the FPGA-based tracking algorithm are introduced as well as the plans for their test in the upcoming test beam at DESY.

FPGA Acceleration by Dynamically-Loaded Hardware Libraries

DEFF Research Database (Denmark)

Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

Development of FPGA-based safety-related instrumentation and control systems

Energy Technology Data Exchange (ETDEWEB)

Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

2004-07-01

Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

Fault tolerance based on serial communication of FPGA

International Nuclear Information System (INIS)

Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

2012-01-01

There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

Random number generators for large-scale parallel Monte Carlo simulations on FPGA

Science.gov (United States)

Lin, Y.; Wang, F.; Liu, B.

2018-05-01

Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

Computer vision camera with embedded FPGA processing

Science.gov (United States)

Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

2000-03-01

Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

Algorithmic strategies for FPGA-based vision

OpenAIRE

Lim, Yoong Kang

2016-01-01

As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

A Hardware Framework for on-Chip FPGA Acceleration

DEFF Research Database (Denmark)

Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

2016-01-01

In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

Prototyping Advanced Control Systems on FPGA

Directory of Open Access Journals (Sweden)

Simard Stéphane

2009-01-01

Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

FPGA Implementation of the stepwise shutdown system

International Nuclear Information System (INIS)

Lotjonen, L.

2012-01-01

This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

FPGA Implementation of the stepwise shutdown system

Energy Technology Data Exchange (ETDEWEB)

Lotjonen, L.

2012-07-01

This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

Adaptive Multi-Layered Space-Time Block Coded Systems in Wireless Environments

KAUST Repository

Al-Ghadhban, Samir

2014-01-01

© 2014, Springer Science+Business Media New York. Multi-layered space-time block coded systems (MLSTBC) strike a balance between spatial multiplexing and transmit diversity. In this paper, we analyze the block error rate performance of MLSTBC

Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

International Nuclear Information System (INIS)

Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa

2015-01-01

This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket

A software radio platform based on ARM and FPGA

Directory of Open Access Journals (Sweden)

Yang Xin.

2016-01-01

Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

A FPGA-based architecture for real-time image matching

Science.gov (United States)

Wang, Jianhui; Zhong, Sheng; Xu, Wenhui; Zhang, Weijun; Cao, Zhiguo

2013-10-01

Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

Logic qualification of FPGA-based safety-related I and C systems

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

2009-01-01

We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

FPGA-Based Sonar Processing

National Research Council Canada - National Science Library

Graham, Paul; Nelson, Brent

1998-01-01

This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

FPGA based Control of a Production Cell System

NARCIS (Netherlands)

Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

Commercial FPGA based multipurpose controller: implementation perspective

International Nuclear Information System (INIS)

Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

2012-01-01

This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

FPGA remote update for nuclear environments

Energy Technology Data Exchange (ETDEWEB)

Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

2015-07-01

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

Embedded system in FPGA-based LLRF controller for FLASH

Science.gov (United States)

Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

2006-10-01

FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

Fpga As A Part Of Ms Windows Control Environment

Directory of Open Access Journals (Sweden)

Krzysztof Kołek

2007-01-01

Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

Long-distance configuration of FPGA based on serial communication

International Nuclear Information System (INIS)

Liu Xiang; Song Kezhu; Zhang Sifeng

2010-01-01

To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

Automatic generation of application specific FPGA multicore accelerators

DEFF Research Database (Denmark)

Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

2014-01-01

High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

An alarm multiplexer communication system

International Nuclear Information System (INIS)

Herrera, G.V.

1986-01-01

A low cost Alarm Multiplexer Communication System (AMCS) has been developed to perform the security sensor monitoring and control functions and to provide remote relay control capability for integrated security systems. AMCS has a distributed multiplexer/repeater architecture with up to four dual communication loops and dual control computers that guarantee total system operation under any single point failure condition. Each AMCS can control up to 4096 sensors and 2048 remote relays. AMCS reports alarm status information to and is controlled by either one or two Host computers. This allows for independent operation of primary and backup security command centers. AMCS communicates with the Host computers over an asynchronous serial communication link and has a message protocol which allows AMCS to fully recover from lost messages or large blocks of data communication errors. This paper describes the AMCS theory of operation, AMCS fault modes, and AMCS system design methodology. Also, cost and timing information is presented. AMCS is being used and considered for several DOE and DOD facilities

Flexible, fpga-based electronics for modular robots

DEFF Research Database (Denmark)

Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

2008-01-01

In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

FPGA based Smart Wireless MIMO Control System

International Nuclear Information System (INIS)

Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

2013-01-01

In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

Verification of FPGA-based NPP I and C systems. General approach and techniques

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

2011-01-01

This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

FPGA communications based on Gigabit Ethernet

International Nuclear Information System (INIS)

Doolittle, L.R.; Serrano, C.

2012-01-01

The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

Burst-Mode Asynchronous Controllers on FPGA

Directory of Open Access Journals (Sweden)

Duarte L. Oliveira

2008-01-01

Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

High-frequency, three-phase current controller implementation in an FPGA

Energy Technology Data Exchange (ETDEWEB)

Hartmann, M.; Round, S. D.; Kolar, J. W.

2008-07-01

Three phase rectifiers with switching frequencies of 500 kHz or more require high speed current controllers. At such high switching frequencies analog controllers as well as high speed digital signal processing (DSP) systems have limited performance. In this paper, two high speed current controller implementations using two different field-programmable gate arrays (FPGA) - one for switching frequencies up to 1 MHz and one for switching frequencies beyond 1 MHz - are presented to overcome this performance limitation. Starting with the digital system design all the blocks of the signal chain, containing analog-to-digital (A/D) interface, digital controller implementation using HW-multipliers and implementation of a novel high speed, high resolution pulse width modulation (PWM) are discussed and compared. Final measurements verify the performance of the controllers. (author)

Simulation Performance of Multiple-Input Multiple-Output Systems Employing Single-Carrier Modulation and Orthogonal Frequency Division Multiplexing

National Research Council Canada - National Science Library

Saglam, Halil D

2004-01-01

...) systems utilizing Alamouti-based space-time block coding (STBC) technique. The MIMO communication systems using STBC technique employing both single-carrier modulation and orthogonal frequency division multiplexing (OFDM...

FPGA Mezzanine Cards for CERN’s Accelerator Control System

CERN Document Server

Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

2009-01-01

Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

A low-power wave union TDC implemented in FPGA

International Nuclear Information System (INIS)

Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

2011-01-01

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

L1 track finding for a time multiplexed trigger

Energy Technology Data Exchange (ETDEWEB)

Cieri, D., E-mail: davide.cieri@bristol.ac.uk [University of Bristol, Bristol (United Kingdom); Rutherford Appleton Laboratory, Didcot (United Kingdom); Brooke, J.; Grimes, M. [University of Bristol, Bristol (United Kingdom); Newbold, D. [University of Bristol, Bristol (United Kingdom); Rutherford Appleton Laboratory, Didcot (United Kingdom); Harder, K.; Shepherd-Themistocleous, C.; Tomalin, I. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Vichoudis, P. [CERN, Geneva (Switzerland); Reid, I. [Brunel University, London (United Kingdom); Iles, G.; Hall, G.; James, T.; Pesaresi, M.; Rose, A.; Tapper, A.; Uchida, K. [Imperial College, London (United Kingdom)

2016-07-11

At the HL-LHC, proton bunches will cross each other every 25 ns, producing an average of 140 pp-collisions per bunch crossing. To operate in such an environment, the CMS experiment will need a L1 hardware trigger able to identify interesting events within a latency of 12.5 μs. The future L1 trigger will make use also of data coming from the silicon tracker to control the trigger rate. The architecture that will be used in future to process tracker data is still under discussion. One interesting proposal makes use of the Time Multiplexed Trigger concept, already implemented in the CMS calorimeter trigger for the Phase I trigger upgrade. The proposed track finding algorithm is based on the Hough Transform method. The algorithm has been tested using simulated pp-collision data. Results show a very good tracking efficiency. The algorithm will be demonstrated in hardware in the coming months using the MP7, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s.

L1 Track Finding for a Time Multiplexed Trigger

CERN Document Server

AUTHOR|(CDS)2090481; Grimes, M.; Newbold, D.; Harder, K.; Shepherd-Themistocleous, C.; Tomalin, I.; Vichoudis, P.; Reid, I.; Iles, G.; Hall, G.; James, T.; Pesaresi, M.; Rose, A.; Tapper, A.; Uchida, K.

2016-01-01

At the HL-LHC, proton bunches will cross each other every 25 ns, producing an average of 140 p p-collisions per bunch crossing. To operate in such an environment, the CMS experiment will need a L1 hardware trigger able to identify interesting events within a latency of 12.5 us. The future L1 trigger will make use also of data coming from the silicon tracker to control the trigger rate. The architecture that will be used in future to process tracker data is still under discussion. One interesting proposal makes use of the Time Multiplexed Trigger concept, already implemented in the CMS calorimeter trigger for the Phase I trigger upgrade. The proposed track finding algorithm is based on the Hough Transform method. The algorithm has been tested using simulated pp-collision data. Results show a very good tracking efficiency. The algorithm will be demonstrated in hardware in the coming months using the MP7, which is a uTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s.

An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

Science.gov (United States)

Gregory, Kyle J.; Hill, Joanne E. (Editor); Black, J. Kevin; Baumgartner, Wayne H.; Jahoda, Keith

2016-01-01

A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

FAS: Using FPGA to Accelerate and Secure SDN Software Switches

Directory of Open Access Journals (Sweden)

Wenwen Fu

2018-01-01

Full Text Available Software-Defined Networking (SDN promises the vision of more flexible and manageable networks but requires certain level of programmability in the data plane to accommodate different forwarding abstractions. SDN software switches running on commodity multicore platforms are programmable and are with low deployment cost. However, the performance of SDN software switches is not satisfactory due to the complex forwarding operations on packets. Moreover, this may hinder the performance of real-time security on software switch. In this paper, we analyze the forwarding procedure and identify the performance bottleneck of SDN software switches. An FPGA-based mechanism for accelerating and securing SDN switches, named FAS (FPGA-Accelerated SDN software switch, is proposed to take advantage of the reconfigurability and high-performance advantages of FPGA. FAS improves the performance as well as the capacity against malicious traffic attacks of SDN software switches by offloading some functional modules. We validate FAS on an FPGA-based network processing platform. Experiment results demonstrate that the forwarding rate of FAS can be 44% higher than the original SDN software switch. In addition, FAS provides new opportunity to enhance the security of SDN software switches by allowing the deployment of bump-in-the-wire security modules (such as packet detectors and filters in FPGA.

CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

CERN Document Server

Zhu, Yu

2010-01-01

Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

FPGA cluster for high-performance AO real-time control system

Science.gov (United States)

Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

2006-06-01

Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

FPGA-based trigger system for the Fermilab SeaQuest experimentz

Energy Technology Data Exchange (ETDEWEB)

Shiu, Shiuan-Hal, E-mail: shshiu@phys.sinica.edu.tw [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Department of Physics, National Central University, No. 300, Jhongda Rd., Jhongli District, Taoyuan City 32001, Taiwan (China); Wu, Jinyuan [Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); McClellan, Randall Evan [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Gilman, Ron [Rutgers, The State University of New Jersey, 136 Frelinghuysen Rd., Piscataway, NJ 08854 (United States); Nakano, Kenichi [Department of Physics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 (Japan); Peng, Jen-Chieh [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Wang, Su-Yin [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); Department of Physics, National Kaohsiung Normal University, No. 62, Shenjhong Rd.,Yanchao Township, Kaohsiung County 824, Taiwan (China)

2015-12-01

The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ{sup +} and μ{sup −} produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

Energy efficiency analysis and implementation of AES on an FPGA

Science.gov (United States)

Kenney, David

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

Spatial and color clustering on an FPGA-based computer system

Science.gov (United States)

Leeser, Miriam E.; Kitaryeva, Natalya V.; Crisman, Jill D.

1998-10-01

We are mapping an image clustering algorithm onto an FPGA- based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

FPGA development board for applications in cosmic rays physics

International Nuclear Information System (INIS)

Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

2013-01-01

The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

Energy Technology Data Exchange (ETDEWEB)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

2011-08-15

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

2011-01-01

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

2011-01-01

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

Directory of Open Access Journals (Sweden)

B. Lakshmi

2010-09-01

Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

Der ATLAS LVL2-Trigger mit FPGA-Prozessoren : Entwicklung, Aufbau und Funktionsnachweis des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS

CERN Document Server

Singpiel, Holger

2000-01-01

This thesis describes the conception and implementation of the hybrid FPGA/CPU based processing system ATLANTIS as trigger processor for the proposed ATLAS experiment at CERN. CompactPCI provides the close coupling of a multi FPGA system and a standard CPU. The system is scalable in computing power and flexible in use due to its partitioning into dedicated FPGA boards for computation, I/O tasks and a private communication. Main focus of the research activities based on the usage of the ATLANTIS system are two areas in the second level trigger (LVL2). First, the acceleration of time critical B physics trigger algorithms is the major aim. The execution of the full scan TRT algorithm on ATLANTIS, which has been used as a demonstrator, results in a speedup of 5.6 compared to a standard CPU. Next, the ATLANTIS system is used as a hardware platform for research work in conjunction with the ATLAS readout systems. For further studies a permanent installation of the ATLANTIS system in the LVL2 application testbed is f...

B-DCGAN:Evaluation of Binarized DCGAN for FPGA

OpenAIRE

Terada, Hideo; Shouno, Hayaru

2018-01-01

We are trying to implement deep neural networks in the edge computing environment for real-world applications such as the IoT(Internet of Things), the FinTech etc., for the purpose of utilizing the significant achievement of Deep Learning in recent years. Especially, we now focus algorithm implementation on FPGA, because FPGA is one of the promising devices for low-cost and low-power implementation of the edge computer. In this work, we introduce Binary-DCGAN(B-DCGAN) - Deep Convolutional GAN...

Photoelectric radar servo control system based on ARM+FPGA

Science.gov (United States)

Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

2016-01-01

In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

Directory of Open Access Journals (Sweden)

Tomyslav Sledevič

2013-05-01

Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

Functional Multiplex PageRank

Science.gov (United States)

Iacovacci, Jacopo; Rahmede, Christoph; Arenas, Alex; Bianconi, Ginestra

2016-10-01

Recently it has been recognized that many complex social, technological and biological networks have a multilayer nature and can be described by multiplex networks. Multiplex networks are formed by a set of nodes connected by links having different connotations forming the different layers of the multiplex. Characterizing the centrality of the nodes in a multiplex network is a challenging task since the centrality of the node naturally depends on the importance associated to links of a certain type. Here we propose to assign to each node of a multiplex network a centrality called Functional Multiplex PageRank that is a function of the weights given to every different pattern of connections (multilinks) existent in the multiplex network between any two nodes. Since multilinks distinguish all the possible ways in which the links in different layers can overlap, the Functional Multiplex PageRank can describe important non-linear effects when large relevance or small relevance is assigned to multilinks with overlap. Here we apply the Functional Page Rank to the multiplex airport networks, to the neuronal network of the nematode C. elegans, and to social collaboration and citation networks between scientists. This analysis reveals important differences existing between the most central nodes of these networks, and the correlations between their so-called pattern to success.

Multiplex PageRank.

Directory of Open Access Journals (Sweden)

Arda Halu

Full Text Available Many complex systems can be described as multiplex networks in which the same nodes can interact with one another in different layers, thus forming a set of interacting and co-evolving networks. Examples of such multiplex systems are social networks where people are involved in different types of relationships and interact through various forms of communication media. The ranking of nodes in multiplex networks is one of the most pressing and challenging tasks that research on complex networks is currently facing. When pairs of nodes can be connected through multiple links and in multiple layers, the ranking of nodes should necessarily reflect the importance of nodes in one layer as well as their importance in other interdependent layers. In this paper, we draw on the idea of biased random walks to define the Multiplex PageRank centrality measure in which the effects of the interplay between networks on the centrality of nodes are directly taken into account. In particular, depending on the intensity of the interaction between layers, we define the Additive, Multiplicative, Combined, and Neutral versions of Multiplex PageRank, and show how each version reflects the extent to which the importance of a node in one layer affects the importance the node can gain in another layer. We discuss these measures and apply them to an online multiplex social network. Findings indicate that taking the multiplex nature of the network into account helps uncover the emergence of rankings of nodes that differ from the rankings obtained from one single layer. Results provide support in favor of the salience of multiplex centrality measures, like Multiplex PageRank, for assessing the prominence of nodes embedded in multiple interacting networks, and for shedding a new light on structural properties that would otherwise remain undetected if each of the interacting networks were analyzed in isolation.

Multiplex PageRank.

Science.gov (United States)

Halu, Arda; Mondragón, Raúl J; Panzarasa, Pietro; Bianconi, Ginestra

2013-01-01

Many complex systems can be described as multiplex networks in which the same nodes can interact with one another in different layers, thus forming a set of interacting and co-evolving networks. Examples of such multiplex systems are social networks where people are involved in different types of relationships and interact through various forms of communication media. The ranking of nodes in multiplex networks is one of the most pressing and challenging tasks that research on complex networks is currently facing. When pairs of nodes can be connected through multiple links and in multiple layers, the ranking of nodes should necessarily reflect the importance of nodes in one layer as well as their importance in other interdependent layers. In this paper, we draw on the idea of biased random walks to define the Multiplex PageRank centrality measure in which the effects of the interplay between networks on the centrality of nodes are directly taken into account. In particular, depending on the intensity of the interaction between layers, we define the Additive, Multiplicative, Combined, and Neutral versions of Multiplex PageRank, and show how each version reflects the extent to which the importance of a node in one layer affects the importance the node can gain in another layer. We discuss these measures and apply them to an online multiplex social network. Findings indicate that taking the multiplex nature of the network into account helps uncover the emergence of rankings of nodes that differ from the rankings obtained from one single layer. Results provide support in favor of the salience of multiplex centrality measures, like Multiplex PageRank, for assessing the prominence of nodes embedded in multiple interacting networks, and for shedding a new light on structural properties that would otherwise remain undetected if each of the interacting networks were analyzed in isolation.

FPGA implementation of a ZigBee wireless network control interface to transmit biomedical signals

International Nuclear Information System (INIS)

López, M A Gómez; Goy, C B; Bolognini, P C; Herrera, M C

2011-01-01

In recent years, cardiac hemodynamic monitors have incorporated new technologies based on wireless sensor networks which can implement different types of communication protocols. More precisely, a digital conductance catheter system recently developed adds a wireless ZigBee module (IEEE 802.15.4 standards) to transmit cardiac signals (ECG, intraventricular pressure and volume) which would allow the physicians to evaluate the patient's cardiac status in a noninvasively way. The aim of this paper is to describe a control interface, implemented in a FPGA device, to manage a ZigBee wireless network. ZigBee technology is used due to its excellent performance including simplicity, low-power consumption, short-range transmission and low cost. FPGA internal memory stores 8-bit signals with which the control interface prepares the information packets. These data were send to the ZigBee END DEVICE module that receives and transmits wirelessly to the external COORDINATOR module. Using an USB port, the COORDINATOR sends the signals to a personal computer for displaying. Each functional block of control interface was assessed by means of temporal diagrams. Three biological signals, organized in packets and converted to RS232 serial protocol, were successfully transmitted and displayed in a PC screen. For this purpose, a custom-made graphical software was designed using LabView.

FPGA implementation of a ZigBee wireless network control interface to transmit biomedical signals

Science.gov (United States)

Gómez López, M. A.; Goy, C. B.; Bolognini, P. C.; Herrera, M. C.

2011-12-01

In recent years, cardiac hemodynamic monitors have incorporated new technologies based on wireless sensor networks which can implement different types of communication protocols. More precisely, a digital conductance catheter system recently developed adds a wireless ZigBee module (IEEE 802.15.4 standards) to transmit cardiac signals (ECG, intraventricular pressure and volume) which would allow the physicians to evaluate the patient's cardiac status in a noninvasively way. The aim of this paper is to describe a control interface, implemented in a FPGA device, to manage a ZigBee wireless network. ZigBee technology is used due to its excellent performance including simplicity, low-power consumption, short-range transmission and low cost. FPGA internal memory stores 8-bit signals with which the control interface prepares the information packets. These data were send to the ZigBee END DEVICE module that receives and transmits wirelessly to the external COORDINATOR module. Using an USB port, the COORDINATOR sends the signals to a personal computer for displaying. Each functional block of control interface was assessed by means of temporal diagrams. Three biological signals, organized in packets and converted to RS232 serial protocol, were sucessfully transmitted and displayed in a PC screen. For this purpose, a custom-made graphical software was designed using LabView.

An FPGA-based silicon neuronal network with selectable excitability silicon neurons

Directory of Open Access Journals (Sweden)

Jing eLi

2012-12-01

Full Text Available This paper presents a digital silicon neuronal network which simulates the nerve system in creatures and has the ability to execute intelligent tasks, such as associative memory. Two essential elements, the mathematical-structure-based digital spiking silicon neuron (DSSN and the transmitter release based silicon synapse, allow the network to show rich dynamic behaviors and are computationally efficient for hardware implementation. We adopt mixed pipeline and parallel structure and shift operations to design a sufficient large and complex network without excessive hardware resource cost. The network with $256$ full-connected neurons is built on a Digilent Atlys board equipped with a Xilinx Spartan-6 LX45 FPGA. Besides, a memory control block and USB control block are designed to accomplish the task of data communication between the network and the host PC. This paper also describes the mechanism of associative memory performed in the silicon neuronal network. The network is capable of retrieving stored patterns if the inputs contain enough information of them. The retrieving probability increases with the similarity between the input and the stored pattern increasing. Synchronization of neurons is observed when the successful stored pattern retrieval occurs.

An FPGA-based torus communication network

Energy Technology Data Exchange (ETDEWEB)

Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

2011-02-15

We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

An FPGA-based torus communication network

International Nuclear Information System (INIS)

Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

2011-02-01

We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

Analogue multiplexer

International Nuclear Information System (INIS)

Gorshkov, V.A.; Kuznetsov, A.N.

1980-01-01

In systems of signal recording from several parallel spectrometric channels one can considerably reduce the total apparatus volume using a special unit - an analog multiplexer. A description of the multiplexer in the CAMAC system on the base of fast linear gating circuits which allows one analog-to-code converter to attend four spectrometric channels is given. On the example of the 4-channel spectrometer the logics of interaction of the multiple with analog-to-digital coxernver and signal recorder is shown. Electrical and functional multiplexer flow-sheets are given and its main characteristics are presented

FPGA based VME boards for Indus-2 timing control system

International Nuclear Information System (INIS)

Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

2009-01-01

FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

International Nuclear Information System (INIS)

HOFF, L.T.

2005-01-01

The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

Uranus: a rapid prototyping tool for FPGA embedded computer vision

Science.gov (United States)

Rosales-Hernández, Victor; Castillo-Jimenez, Liz; Viveros-Velez, Gilberto; Zuñiga-Grajeda, Virgilio; Treviño Torres, Abel; Arias-Estrada, M.

2007-01-01

The starting point for all successful system development is the simulation. Performing high level simulation of a system can help to identify, insolate and fix design problems. This work presents Uranus, a software tool for simulation and evaluation of image processing algorithms with support to migrate them to an FPGA environment for algorithm acceleration and embedded processes purposes. The tool includes an integrated library of previous coded operators in software and provides the necessary support to read and display image sequences as well as video files. The user can use the previous compiled soft-operators in a high level process chain, and code his own operators. Additional to the prototyping tool, Uranus offers FPGA-based hardware architecture with the same organization as the software prototyping part. The hardware architecture contains a library of FPGA IP cores for image processing that are connected with a PowerPC based system. The Uranus environment is intended for rapid prototyping of machine vision and the migration to FPGA accelerator platform, and it is distributed for academic purposes.

A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

Directory of Open Access Journals (Sweden)

Stamen Gadzhanov

2013-04-01

Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

Simultaneous Perturbation Particle Swarm Optimization and Its FPGA Implementation

OpenAIRE

Maeda, Yutaka; Matsushita, Naoto

2009-01-01

In this paper, we presented hardware implementation of the particle swarm optimization algorithm which is combination of the ordinary particle swarm optimization and the simultaneous perturbation method. FPGA is used to realize the system. This algorithm utilizes local information of objective function effectively without lack of advantage of the original particle swarm optimization. Moreover, the FPGA implementation gives higher operation speed effectively using parallelism of the particle s...

An FPGA-Based Electronic Cochlea

Directory of Open Access Journals (Sweden)

M. P. Leong

2003-06-01

Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

Directory of Open Access Journals (Sweden)

Kevin R. Townsend

2015-01-01

Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

Development of a multi-purpose logic module with the FPGA

International Nuclear Information System (INIS)

Nanbu, K.; Ishikawa, T.; Shimizu, H.

2008-01-01

We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

CERN Document Server

Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

2018-01-01

The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

International Nuclear Information System (INIS)

Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

Energy Technology Data Exchange (ETDEWEB)

Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

DEFF Research Database (Denmark)

Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

2017-01-01

and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER......In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...

Development of an FPGA-Based Motion Control IC for Caving Machine

Directory of Open Access Journals (Sweden)

Chiu-Keng Lai

2014-03-01

Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

International Nuclear Information System (INIS)

Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

2016-01-01

Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

The integration of FPGA TDC inside White Rabbit node

International Nuclear Information System (INIS)

Li, H.; Xue, T.; Gong, G.; Li, J.

2017-01-01

White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

The integration of FPGA TDC inside White Rabbit node

Science.gov (United States)

Li, H.; Xue, T.; Gong, G.; Li, J.

2017-04-01

White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-04-20

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

A natural-color mapping for single-band night-time image based on FPGA

Science.gov (United States)

Wang, Yilun; Qian, Yunsheng

2018-01-01

A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-04-20

The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

NARCIS (Netherlands)

Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen

2014-01-01

In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic

Soft error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter

International Nuclear Information System (INIS)

Wirthlin, M J; Harding, A; Takai, H

2014-01-01

This paper summarizes the radiation testing performed on the Xilinx Kintex-7 FPGA in an effort to determine if the Kintex-7 can be used within the ATLAS Liquid Argon (LAr) Calorimeter. The Kintex-7 device was tested with wide-spectrum neutrons, protons, heavy-ions, and mixed high-energy hadron environments. The results of these tests were used to estimate the configuration ram and block ram upset rate within the ATLAS LAr. These estimations suggest that the configuration memory will upset at a rate of 1.1 × 10 −10 upsets/bit/s and the bram memory will upset at a rate of 9.06 × 10 −11 upsets/bit/s. For the Kintex 7K325 device, this translates to 6.85 × 10 −3 upsets/device/s for configuration memory and 1.49 × 10 −3 for block memory

Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

International Nuclear Information System (INIS)

Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

2014-01-01

The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

Carry-chain propagation delay impacts on resolution of FPGA-based TDC

International Nuclear Information System (INIS)

Dong Lei; Yang Junfeng; Song Kezhu

2014-01-01

The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG

Science.gov (United States)

2014-06-01

is normalized to π. The proposed burst-mode architecture is written in VHDL and verified using Modelsim. The VHDL design is implemented on a Xilinx...Document Number: SET 2014-0043 412TW-PA-14298 FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG June 2014 Final Report Test...To) 9/11 -- 8/14 4. TITLE AND SUBTITLE FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG 5a. CONTRACT NUMBER: W900KK-11-C-0032 5b

Development of a multiplexed readout with high position resolution for positron emission tomography

Energy Technology Data Exchange (ETDEWEB)

Lee, Sangwon; Choi, Yong [Molecular Imaging Research & Education (MiRe) Laboratory, Department of Electronic Engineering, Sogang University, Seoul 04107 (Korea, Republic of); Kang, Jihoon [Department of Biomedical Engineering, Chonnam National University, Yeosu 550-749 (Korea, Republic of); Jung, Jin Ho [Molecular Imaging Research & Education (MiRe) Laboratory, Department of Electronic Engineering, Sogang University, Seoul 04107 (Korea, Republic of)

2017-04-01

Detector signals for positron emission tomography (PET) are commonly multiplexed to reduce the number of digital processing channels so that the system can remain cost effective while also maintaining imaging performance. In this work, a multiplexed readout combining Anger position estimation algorithm and position decoder circuit (PDC) was developed to reduce the number of readout channels by a factor of 24, 96-to-4. The data acquisition module consisted of a TDC (50 ps resolution), 4-channel ADCs (12 bit, 105 MHz sampling rate), 2 GB SDRAM and USB3.0. The performance of the multiplexed readout was assessed with a high-resolution PET detector block composed of 2×3 detector modules, each consisting of an 8×8 array of 1.52×1.52×6 mm{sup 3} LYSO, a 4×4 array of 3×3 mm{sup 2} silicon photomultiplier (SiPM) and 13.4×13.4 mm{sup 2} light guide with 0.7 mm thickness. The acquired flood histogram showed that all 384 crystals could be resolved. The average energy resolution at 511 keV was 13.7±1.6% full-width-at-half-maximum (FWHM) and the peak-to-valley ratios of the flood histogram on the horizontal and vertical lines were 18.8±0.8 and 22.8±1.3, respectively. The coincidence resolving time of a pair of detector blocks was 6.2 ns FWHM. The reconstructed phantom image showed that rods down to a diameter of 1.6 mm could be resolved. The results of this study indicate that the multiplexed readout would be useful in developing a PET with a spatial resolution less than the pixel size of the photosensor, such as a SiPM array.

An FPGA-based heterogeneous image fusion system design method

Science.gov (United States)

Song, Le; Lin, Yu-chi; Chen, Yan-hua; Zhao, Mei-rong

2011-08-01

Taking the advantages of FPGA's low cost and compact structure, an FPGA-based heterogeneous image fusion platform is established in this study. Altera's Cyclone IV series FPGA is adopted as the core processor of the platform, and the visible light CCD camera and infrared thermal imager are used as the image-capturing device in order to obtain dualchannel heterogeneous video images. Tailor-made image fusion algorithms such as gray-scale weighted averaging, maximum selection and minimum selection methods are analyzed and compared. VHDL language and the synchronous design method are utilized to perform a reliable RTL-level description. Altera's Quartus II 9.0 software is applied to simulate and implement the algorithm modules. The contrast experiments of various fusion algorithms show that, preferably image quality of the heterogeneous image fusion can be obtained on top of the proposed system. The applied range of the different fusion algorithms is also discussed.

An FPGA-based track finder for the L1 trigger of the CMS experiment at the HL-LHC

CERN Document Server

Cieri, Davide; Harder, Kristian; Manolopoulos, Konstantinos; Shepherd-Themistocleous, Claire; Tomalin, Ian; Aggleton, Robin; Ball, Fionn; Brooke, Jim; Clement, Emyr; Newbold, Dave; Paramesvaran, Sudarshan; Hobson, Peter; Morton, Alexander Davide; Reid, Ivan; Hall, Geoff; Iles, Gregory; James, Thomas Owen; Matsushita, Takashi; Pesaresi, Mark; Rose, Andrew William; Shtipliyski, Antoni; Summers, Sioni; Tapper, Alex; Uchida, Kirika; Vichoudis, Paschalis; Ardila-Perez, Luis; Balzer, Matthias; Caselle, Michele; Sander, Oliver; Schuh, Thomas; Weber, Marc

2017-01-01

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial component of this upgrade will be the ability to reconstruct within a few microseconds all charged particle tracks with transverse momentum above 3 GeV, so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform followed by a track fitting based on the linear regression technique. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying latency constraints. T...

Analysis of subsystems in wavelength-division-multiplexing networks

DEFF Research Database (Denmark)

Liu, Fenghai

2001-01-01

Wavelength division multiplexing (WDM) technology together with optical amplification has created a new era for optical communication. Transmission capacity is greatly increased by adding more and more wavelength channels into a single fiber, as well as by increasing the line rate of each channel...... in semiconductor optical amplifiers (SOAs), and dispersion managed fiber sections. New subsystems are also proposed in the thesis: a modular 2×2 multiwavelength cross-connect using wavelength switching blocks, a wavelength converter based on cross phase modulation in a semiconductor modulator, a wavelength...

Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

International Nuclear Information System (INIS)

Suetoe, J.; Hegyesi, G.

2012-01-01

Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

International Nuclear Information System (INIS)

Shanjie, Xiao; Tatjana, Jevremovic

2010-01-01

The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

Science.gov (United States)

Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

2016-01-01

It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

Multifunctional data acquisition system based on USB and FPGA

International Nuclear Information System (INIS)

Huang Tuchen; Gong Hui; Shao Beibei

2013-01-01

A multifunctional data acquisition system based on USB and FPGA was developed. The system has four analog inputs digitalized by fast ADC. Based on flexibility of FPGA, different functions can be implemented such as waveform sampling, pulse counting, multi-channel pulse height analysis, and charge division readout process. The hardware communicates with host PC via USB interface. The Labview based user soft ware initializes the hardware, configures the running parameters, reads and processes the data as well as displays the result online. (authors)

Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

Directory of Open Access Journals (Sweden)

He Chen

2011-12-01

Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

Multiplex gas chromatography

Science.gov (United States)

Valentin, Jose R.

1990-01-01

The principles of the multiplex gas chromatography (GC) technique, which is a possible candidate for chemical analysis of planetary atmospheres, are discussed. Particular attention is given to the chemical modulators developed by present investigators for multiplex GC, namely, the thermal-desorption, thermal-decomposition, and catalytic modulators, as well as to mechanical modulators. The basic technique of multiplex GC using chemical modulators and a mechanical modulator is demonstrated. It is shown that, with the chemical modulators, only one gas stream consisting of the carrier in combination with the components is being analyzed, resulting in a simplified instrument that requires relatively few consumables. The mechanical modulator demonstrated a direct application of multiplex GC for the analysis of gases in atmosphere of Titan at very low pressures.

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Directory of Open Access Journals (Sweden)

Swapnil Mhaske

2017-01-01

Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

A parallel FPGA implementation for real-time 2D pixel clustering for the ATLAS Fast Tracker Processor

International Nuclear Information System (INIS)

Sotiropoulou, C L; Gkaitatzis, S; Kordas, K; Nikolaidis, S; Petridou, C; Annovi, A; Beretta, M; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of

The RTE inversion on FPGA aboard the solar orbiter PHI instrument

Science.gov (United States)

Cobos Carrascosa, J. P.; Aparicio del Moral, B.; Ramos Mas, J. L.; Balaguer, M.; López Jiménez, A. C.; del Toro Iniesta, J. C.

2016-07-01

In this work we propose a multiprocessor architecture to reach high performance in floating point operations by using radiation tolerant FPGA devices, and under narrow time and power constraints. This architecture is used in the PHI instrument that carries out the scientific analysis aboard the ESA's Solar Orbiter mission. The proposed architecture, in a SIMD flavor, is aimed to be an accelerator within the Data Processing Unit (it is composed by a main Leon processor and two FPGAs) for carrying out the RTE inversion on board the spacecraft using a relatively slow FPGA device - Xilinx XQR4VSX55-. The proposed architecture squeezes the FPGA resources in order to reach the computational requirements and improves the ground-based system performance based on commercial CPUs regarding time and power consumption. In this work we demonstrate the feasibility of using this FPGA devices embedded in the SO/PHI instrument. With that goal in mind, we perform tests to evaluate the scientific results and to measure the processing time and power consumption for carrying out the RTE inversion.

Rapid-X - An FPGA Development Toolset Using a Custom Simulink Library for MTCA.4 Modules

Science.gov (United States)

Prędki, Paweł; Heuer, Michael; Butkowski, Łukasz; Przygoda, Konrad; Schlarb, Holger; Napieralski, Andrzej

2015-06-01

The recent introduction of advanced hardware architectures such as the Micro Telecommunications Computing Architecture (MTCA) caused a change in the approach to implementation of control schemes in many fields. The development has been moving away from traditional programming languages ( C/C++), to hardware description languages (VHDL, Verilog), which are used in FPGA development. With MATLAB/Simulink it is possible to describe complex systems with block diagrams and simulate their behavior. Those diagrams are then used by the HDL experts to implement exactly the required functionality in hardware. Both the porting of existing applications and adaptation of new ones require a lot of development time from them. To solve this, Xilinx System Generator, a toolbox for MATLAB/Simulink, allows rapid prototyping of those block diagrams using hardware modelling. It is still up to the firmware developer to merge this structure with the hardware-dependent HDL project. This prevents the application engineer from quickly verifying the proposed schemes in real hardware. The framework described in this article overcomes these challenges, offering a hardware-independent library of components that can be used in Simulink/System Generator models. The components are subsequently translated into VHDL entities and integrated with a pre-prepared VHDL project template. Furthermore, the entire implementation process is run in the background, giving the user an almost one-click path from control scheme modelling and simulation to bit-file generation. This approach allows the application engineers to quickly develop new schemes and test them in real hardware environment. The applications may range from simple data logging or signal generation ones to very advanced controllers. Taking advantage of the Simulink simulation capabilities and user-friendly hardware implementation routines, the framework significantly decreases the development time of FPGA-based applications.

Three-dimensional design methodologies for tree-based FPGA architecture

CERN Document Server

Pangracious, Vinod; Mehrez, Habib

2015-01-01

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

Motion camera based on a custom vision sensor and an FPGA architecture

Science.gov (United States)

Arias-Estrada, Miguel

1998-09-01

A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

Design and demonstration of a multitechnology FPGA for photonic information processing

Science.gov (United States)

Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

2003-11-01

We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

Directory of Open Access Journals (Sweden)

Bhattacharyya Shuvra S

2003-01-01

Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

FPGA Vision Data Architecture

Science.gov (United States)

Morfopoulos, Arin C.; Pham, Thang D.

2013-01-01

JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

Consideration for wavelength multiplexing versus time multiplexing in optical transport network

DEFF Research Database (Denmark)

Limal, Emmanuel; Stubkjær, Kristian Elmholdt

1999-01-01

We compare optical wavelength multiplexing and time multiplexing techniquesfor optical transport network by studying the space switch sizes of OXCs andtheir interfaces as a function of the fraction of add/drop traffic....

Multicasting based optical inverse multiplexing in elastic optical network.

Science.gov (United States)

Guo, Bingli; Xu, Yingying; Zhu, Paikun; Zhong, Yucheng; Chen, Yuanxiang; Li, Juhao; Chen, Zhangyuan; He, Yongqi

2014-06-16

Optical multicasting based inverse multiplexing (IM) is introduced in spectrum allocation of elastic optical network to resolve the spectrum fragmentation problem, where superchannels could be split and fit into several discrete spectrum blocks in the intermediate node. We experimentally demonstrate it with a 1-to-7 optical superchannel multicasting module and selecting/coupling components. Also, simulation results show that, comparing with several emerging spectrum defragmentation solutions (e.g., spectrum conversion, split spectrum), IM could reduce blocking performance significantly but without adding too much system complexity as split spectrum. On the other hand, service fairness for traffic with different granularity of these schemes is investigated for the first time and it shows that IM performs better than spectrum conversion and almost as well as split spectrum, especially for smaller size traffic under light traffic intensity.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

Millar James

2006-01-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

James Millar

2006-10-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

Programovatelná hradlová pole - FPGA

Czech Academy of Sciences Publication Activity Database

Daněk, Martin

2006-01-01

Roč. 12, č. 2 (2006), s. 9-13 ISSN 1210-9592 R&D Projects: GA ČR GA102/04/2137 Institutional research plan: CEZ:AV0Z10750506 Keywords : FPGA architecture * physical design * design flow Subject RIV: JC - Computer Hardware ; Software

An FPGA based track finder for the L1 trigger of the CMS experiment at the High Luminosity LHC

CERN Document Server

Tomalin, Ian; Ball, Fionn Amhairghen; Balzer, Matthias Norbert; Boudoul, Gaelle; Brooke, James John; Caselle, Michele; Calligaris, Luigi; Cieri, Davide; Clement, Emyr John; Dutta, Suchandra; Hall, Geoffrey; Harder, Kristian; Hobson, Peter; Iles, Gregory Michiel; James, Thomas Owen; Manolopoulos, Konstantinos; Matsushita, Takashi; Morton, Alexander; Newbold, David; Paramesvaran, Sudarshan; Pesaresi, Mark Franco; Pozzobon, Nicola; Reid, Ivan; Rose, A. W; Sander, Oliver; Shepherd-Themistocleous, Claire; Shtipliyski, Antoni; Schuh, Thomas; Skinnari, Louise; Summers, Sioni Paris; Tapper, Alexander; Thea, Alessandro; Uchida, Kirika; Vichoudis, Paschalis; Viret, Sebastien; Weber, M; Aggleton, Robin Cameron

2017-12-14

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial requirement of this upgrade is to provide the ability to reconstruct all charged particle tracks with transverse momentum above 2-3 GeV within 4$\\mu$s so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform, followed by a combinatorial Kalman Filter. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system functionality, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle acceptance at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying the latency requirement. ...

Implementation of a feed-forward artificial neural network in VHDL on FPGA

NARCIS (Netherlands)

Dondon, P.; Carvalho, J.; Gardere, R.; Lahalle, P.; Tsenov, G.; Mladenov, V.M.; Reljin, B.; Stankovic, S.

2014-01-01

Describing an Artificial Neural Network (ANN) using VHDL allows a further implementation of such a system on FPGA. Indeed, the principal point of using FPGA for ANNs is flexibility that gives it an advantage toward other systems like ASICS which are entirely dedicated to one unique architecture and

Extracting information from multiplex networks

Science.gov (United States)

Iacovacci, Jacopo; Bianconi, Ginestra

2016-06-01

Multiplex networks are generalized network structures that are able to describe networks in which the same set of nodes are connected by links that have different connotations. Multiplex networks are ubiquitous since they describe social, financial, engineering, and biological networks as well. Extending our ability to analyze complex networks to multiplex network structures increases greatly the level of information that is possible to extract from big data. For these reasons, characterizing the centrality of nodes in multiplex networks and finding new ways to solve challenging inference problems defined on multiplex networks are fundamental questions of network science. In this paper, we discuss the relevance of the Multiplex PageRank algorithm for measuring the centrality of nodes in multilayer networks and we characterize the utility of the recently introduced indicator function Θ ˜ S for describing their mesoscale organization and community structure. As working examples for studying these measures, we consider three multiplex network datasets coming for social science.

Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

International Nuclear Information System (INIS)

Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

2010-10-01

The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

Diversity for security: case assessment for FPGA-based safety-critical systems

Directory of Open Access Journals (Sweden)

Kharchenko Vyacheslav

2016-01-01

Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

Science.gov (United States)

Rais, Muhammad H.; Qasim, Syed M.

2010-06-01

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

FPGA prototyping by Verilog examples Xilinx Spartan-3 version

CERN Document Server

Chu, Pong P

2008-01-01

FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II)

CERN Document Server

Ajuha, S; Costa de Paiva, Thiago; Das, Souvik; Eusebi, Ricardo; Finotti Ferreira, Vitor; Hahn, Kristian; Hu, Zhen; Jindariani, Sergo; Konigsberg, Jacobo; Liu, Tiehui Ted; Low, Jia Fu; Okumura, Yasuyuki; Olsen, Jamieson; Arruda Ramalho, Lucas; Rossin, Roberto; Ristori, Luciano; Akira Shinoda, Ailton; Tran, Nhan; Trovato, Marco; Ulmer, Keith; Vaz, Mario; Wen, Xianshan; Wu, Jin-Yuan; Xu, Zijun; Yin, Han; Zorzetti, Silvia

2017-01-01

The Pulsar II is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this technical memo we describe the Pulsar II hardware and its performance, such as the performance test results with full mesh backplanes from di↵erent vendors, how the backplane is used for the development of low-latency time-multiplexed data transfer schemes and how the inter-shelf and intra-shelf synchronization works.

A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II)

Energy Technology Data Exchange (ETDEWEB)

Ajuha, S. [Univ. of Sao Paulo (Brazil); et al.

2017-06-29

The Pulsar II is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this technical memo we describe the Pulsar II hardware and its performance, such as the performance test results with full mesh backplanes from different vendors, how the backplane is used for the development of low-latency time-multiplexed data transfer schemes and how the inter-shelf and intra-shelf synchronization works.

Shared protection based virtual network mapping in space division multiplexing optical networks

Science.gov (United States)

Zhang, Huibin; Wang, Wei; Zhao, Yongli; Zhang, Jie

2018-05-01

Space Division Multiplexing (SDM) has been introduced to improve the capacity of optical networks. In SDM optical networks, there are multiple cores/modes in each fiber link, and spectrum resources are multiplexed in both frequency and core/modes dimensions. Enabled by network virtualization technology, one SDM optical network substrate can be shared by several virtual networks operators. Similar with point-to-point connection services, virtual networks (VN) also need certain survivability to guard against network failures. Based on customers' heterogeneous requirements on the survivability of their virtual networks, this paper studies the shared protection based VN mapping problem and proposes a Minimum Free Frequency Slots (MFFS) mapping algorithm to improve spectrum efficiency. Simulation results show that the proposed algorithm can optimize SDM optical networks significantly in terms of blocking probability and spectrum utilization.

High-Performance Linear Algebra Processor using FPGA

National Research Council Canada - National Science Library

Johnson, J

2004-01-01

With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

Science.gov (United States)

Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

2016-01-01

It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

FPGA Flash Memory High Speed Data Acquisition

Science.gov (United States)

Gonzalez, April

2013-01-01

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

On the speed of response of an FPGA-based shutdown system in CANDU nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

She Jingke, E-mail: jshe2@uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada); Jiang Jin, E-mail: jjiang@eng.uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada)

2011-06-15

Highlights: > Design and implementation of an FPGA-based CANDU SDS1. > Hardware-in-the-loop simulation for performance evaluation involved with an NPP simulator. > Comparison of the response time between FPGA-based trip channel and software-based PLC. - Abstract: Several issues in an FPGA based implementation of shutdown systems in CANDU nuclear power plants have been investigated in this paper. A particular attention is on the response time of an FPGA implementation of safety shutdown systems in comparison with operating system based software solutions as in existing CANDU plants. The trip decision logic under 'steam generator (SG) level low' condition has been examined in detail. The design and implementation of this logic on an FPGA platform have been carried out. The functionality tests are performed in a hardware-in-the-loop (HIL) environment by connecting the FPGA based system to an NPP simulator, and replacing one channel of Shutdown System Number 1 (SDS1) in the simulator by the FPGA implementation. The response time of the designed system is also measured through multiple tests under different conditions, and statistical data analysis has been performed. The results of the response time tests are compared against those of a software-based implementation of the same trip logic.

Spatial Multiplexing of Atom-Photon Entanglement Sources using Feedforward Control and Switching Networks.

Science.gov (United States)

Tian, Long; Xu, Zhongxiao; Chen, Lirong; Ge, Wei; Yuan, Haoxiang; Wen, Yafei; Wang, Shengzhi; Li, Shujing; Wang, Hai

2017-09-29

The light-matter quantum interface that can create quantum correlations or entanglement between a photon and one atomic collective excitation is a fundamental building block for a quantum repeater. The intrinsic limit is that the probability of preparing such nonclassical atom-photon correlations has to be kept low in order to suppress multiexcitation. To enhance this probability without introducing multiexcitation errors, a promising scheme is to apply multimode memories to the interface. Significant progress has been made in temporal, spectral, and spatial multiplexing memories, but the enhanced probability for generating the entangled atom-photon pair has not been experimentally realized. Here, by using six spin-wave-photon entanglement sources, a switching network, and feedforward control, we build a multiplexed light-matter interface and then demonstrate a ∼sixfold (∼fourfold) probability increase in generating entangled atom-photon (photon-photon) pairs. The measured compositive Bell parameter for the multiplexed interface is 2.49±0.03 combined with a memory lifetime of up to ∼51  μs.

Moessbauer spectrometric data acquisition based on FPGA

International Nuclear Information System (INIS)

Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

2008-01-01

FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

Development, verification and validation of an FPGA-based core heat removal protection system for a PWR

Energy Technology Data Exchange (ETDEWEB)

Wu, Yichun, E-mail: ycwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China); Shui, Xuanxuan, E-mail: 807001564@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Cai, Yuanfeng, E-mail: 1056303902@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Zhou, Junyi, E-mail: 1032133755@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Wu, Zhiqiang, E-mail: npic_wu@126.com [State Key Laboratory of Reactor System Design Technology, Nuclear Power Institute of China, Chengdu 610041 (China); Zheng, Jianxiang, E-mail: zwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China)

2016-05-15

Highlights: • An example on life cycle development process and V&V on FPGA-based I&C is presented. • Software standards and guidelines are used in FPGA-based NPP I&C system logic V&V. • Diversified FPGA design and verification languages and tools are utilized. • An NPP operation principle simulator is used to simulate operation scenarios. - Abstract: To reach high confidence and ensure reliability of nuclear FPGA-based safety system, life cycle processes of discipline specification and implementation of design as well as regulations verification and validation (V&V) are needed. A specific example on how to conduct life cycle development process and V&V on FPGA-based core heat removal (CHR) protection system for CPR1000 pressure water reactor (PWR) is presented in this paper. Using the existing standards and guidelines for life cycle development and V&V, a simplified FPGA-based CHR protection system for PWR has been designed, implemented, verified and validated. Diversified verification and simulation languages and tools are used by the independent design team and the V&V team. In the system acceptance testing V&V phase, a CPR1000 NPP operation principle simulator (OPS) model is utilized to simulate normal and abnormal operation scenarios, and provide input data to the under-test FPGA-based CHR protection system and a verified C code CHR function module. The evaluation results are applied to validate the under-test FPGA-based CHR protection system. The OPS model operation outputs also provide reasonable references for the tests. Using an OPS model in the system acceptance testing V&V is cost-effective and high-efficient. A dedicated OPS, as a commercial-off-the-shelf (COTS) item, would contribute as an important tool in the V&V process of NPP I&C systems, including FPGA-based and microprocessor-based systems.

Baseband Transceiver Design of a High Definition Radio FM System Using Joint Theoretical Analysis and FPGA Implementation

Directory of Open Access Journals (Sweden)

Chien-Sheng Chen

2014-01-01

Full Text Available Advances in wireless communications have enabled various technologies for wireless digital communication. In the field of digital radio broadcasting, several specifications have been proposed, such as Eureka-147 and digital radio mondiale (DRM. These systems require a new spectrum assignment, which incurs heavy cost due to the depletion of the available spectrum. Therefore, the in-band on-channel (IBOC system has been developed to work in the same band with the conventional analog radio and to provide digital broadcasting services. This paper discusses the function and algorithm of the high definition (HD radio frequency modulation (FM digital radio broadcasting system. Content includes data format allocation, constellation mapping, orthogonal frequency division multiplexing (OFDM modulation of the transmitter, timing synchronization, OFDM demodulation, integer and fraction carrier frequency (integer carrier frequency offset (ICFO and fractional CFO (FCFO estimation, and channel estimation of the receiver. When we implement this system to the field programmable gate array (FPGA based on a hardware platform, both theoretical and practical aspects have been considered to accommodate the available hardware resources.

Optimization on fixed low latency implementation of the GBT core in FPGA

Science.gov (United States)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-07-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Optimization on fixed low latency implementation of the GBT core in FPGA

International Nuclear Information System (INIS)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-01-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

A configurable FPGA FEC unit for Tb/s optical communication

DEFF Research Database (Denmark)

Andersen, Jakob Dahl; Larsen, Knud J.; Bering Bøgh, Christian

2017-01-01

Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency...... within the resources of the FPGA. A proof-of-concept lab experiment at 40 Gb/s was conducted and pre-FEC — post-FEC performance validated with simulated results....

Development of γ dose rate monitor based on FPGA and single-chip microcomputer

International Nuclear Information System (INIS)

He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

2009-01-01

A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

Directory of Open Access Journals (Sweden)

Y. Hou

2016-06-01

Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

Application-specific mesh-based heterogeneous FPGA architectures

CERN Document Server

Parvez, Husain

2011-01-01

This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

Energy Technology Data Exchange (ETDEWEB)

Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

2010-10-15

The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

International Nuclear Information System (INIS)

Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

2016-01-01

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

Using FPGA coprocessor for ATLAS level 2 trigger application

International Nuclear Information System (INIS)

Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

2006-01-01

Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

DEFF Research Database (Denmark)

Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

2012-01-01

This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

Compact FPGA hardware architecture for public key encryption in embedded devices.

Science.gov (United States)

Rodríguez-Flores, Luis; Morales-Sandoval, Miguel; Cumplido, René; Feregrino-Uribe, Claudia; Algredo-Badillo, Ignacio

2018-01-01

Security is a crucial requirement in the envisioned applications of the Internet of Things (IoT), where most of the underlying computing platforms are embedded systems with reduced computing capabilities and energy constraints. In this paper we present the design and evaluation of a scalable low-area FPGA hardware architecture that serves as a building block to accelerate the costly operations of exponentiation and multiplication in [Formula: see text], commonly required in security protocols relying on public key encryption, such as in key agreement, authentication and digital signature. The proposed design can process operands of different size using the same datapath, which exhibits a significant reduction in area without loss of efficiency if compared to representative state of the art designs. For example, our design uses 96% less standard logic than a similar design optimized for performance, and 46% less resources than other design optimized for area. Even using fewer area resources, our design still performs better than its embedded software counterparts (190x and 697x).

A single FPGA-based portable ultrasound imaging system for point-of-care applications.

Science.gov (United States)

Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

2012-07-01

We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

High-definition video display based on the FPGA and THS8200

Science.gov (United States)

Qian, Jia; Sui, Xiubao

2014-11-01

This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

Guide to FPGA Implementation of Arithmetic Functions

CERN Document Server

Deschamps, Jean-Pierre; Cantó, Enrique

2012-01-01

This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

An Improved Rotary Interpolation Based on FPGA

Directory of Open Access Journals (Sweden)

Mingyu Gao

2014-08-01

Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

FPGA-based digital convolution for wireless applications

CERN Document Server

Guan, Lei

2017-01-01

This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

CERN Document Server

Palchaudhuri, Ayan

2016-01-01

This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

Note: Design of FPGA based system identification module with application to atomic force microscopy

Science.gov (United States)

Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

2018-05-01

The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking

OpenAIRE

Basil M Hamed; Mohammed S. El-Moghany

2012-01-01

The cell has optimum operating point to be able to get maximum power. To obtain Maximum Power from photovoltaic array, photovoltaic power system usually requires Maximum Power Point Tracking (MPPT) controller. This paper provides a small power photovoltaic control system based on fuzzy control with FPGA technology design and implementation for MPPT. The system composed of photovoltaic module, buck converter and the fuzzy logic controller implemented on FPGA for controlling on/off time of MOSF...

FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

Directory of Open Access Journals (Sweden)

Mohammed Bahoura

2016-02-01

Full Text Available In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA using Xilinx System Generator (XSG and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

A scalable FPGA-based digitizing platform for radiation data acquisition

International Nuclear Information System (INIS)

Schiffer, Randolph T.; Flaska, Marek; Pozzi, Sara A.; Carney, Sean; Wentzloff, David D.

2011-01-01

Regulating the proliferation of nuclear materials has become an important issue in our society. In order to detect the radiation given off by nuclear materials, systems implementing detectors connected to data processing modules have been developed. We have implemented a scalable, portable detection platform with a data processing module about the size of an external DVD drive. The data processing component of our system utilizes real-time data handling and has the potential for growth and behavior modifications through custom FPGA code editing. The size of our system is dynamic, so additional input channels can be implemented if necessary. This paper presents a scalable, portable detection system capable of transmitting streaming data from its inputs to a PC or laptop. The system also performs tail/total integral pulse shape discrimination (PSD) in real time on the FPGA to filter the data and selectively transmit pulses to a PC. The data arrives at the inputs of the data capturing module, is processed in real time by the onboard FPGA and is then transferred to a PC or laptop via a PCIe cord in discrete packets. The maximum transfer rate from the FPGA to the PC is 2000 MB/s. The Detection for Nuclear Non-Proliferation Group at University of Michigan will use the detection platform to achieve pre-processing of radiation data in real time. Such pre-processing includes PSD, pulse height distributions and particle times of arrival.

An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

Directory of Open Access Journals (Sweden)

Lai Chiu-Keng

2016-01-01

Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

Design and FPGA Implementation of a new hyperchaotic system

International Nuclear Information System (INIS)

Wang Guangyi; Bao Xulei; Wang Zhonglin

2008-01-01

In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic Nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array (FPGA) technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup. (general)

Multichannel analyzer embedded in FPGA; Analizador multicanal embebido en FPGA

Energy Technology Data Exchange (ETDEWEB)

Garcia D, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98060 Zacatecas, Zac. (Mexico); Ordaz G, O. O. [Universidad de Cordoba, Departamento de Arquitectura de Computadores, Electronica y Tecnologia Electronica, Campus de Rabanales, Ctra. N-IVa Km 396, 14071 Cordoba (Spain); Bravo M, I., E-mail: angelogarciad@hotmail.com [Universidad de Alcala de Henares, Departamento de Electronica, Campus Universitario, Carretera Madrid-Barcelona Km 33.600, 28801 Alcala de Henares, Madrid (Spain)

2017-10-15

Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

Multiplexed Engineering in Biology.

Science.gov (United States)

Rogers, Jameson K; Church, George M

2016-03-01

Biotechnology is the manufacturing technology of the future. However, engineering biology is complex, and many possible genetic designs must be evaluated to find cells that produce high levels of a desired drug or chemical. Recent advances have enabled the design and construction of billions of genetic variants per day, but evaluation capacity remains limited to thousands of variants per day. Here we evaluate biological engineering through the lens of the design–build–test cycle framework and highlight the role that multiplexing has had in transforming the design and build steps. We describe a multiplexed solution to the ‘test’ step that is enabled by new research. Achieving a multiplexed test step will permit a fully multiplexed engineering cycle and boost the throughput of biobased product development by up to a millionfold.

Silicon Chip-to-Chip Mode-Division Multiplexing

DEFF Research Database (Denmark)

Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

2018-01-01

A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

High performance parallel backprojection on FPGA

Energy Technology Data Exchange (ETDEWEB)

Pfanner, Florian; Knaup, Michael; Kachelriess, Marc [Erlangen-Nuernberg Univ., Erlangen (Germany). Inst. of Medical Physics (IMP)

2011-07-01

Reconstruction of tomographic images, i.e., images from a Computed Tomography scanner, is a very time consuming issue. The most calculation power is needed for the backprojection step. A closer inspection shows that the algorithm for backprojection is easy to parallelize. FPGAs are able to execute many operations in the same time, so a highly parallel algorithm is a requirement for a powerful acceleration. For data flow rate maximization, we realized the backprojection in a pipelined structure with data throughput of one clock cycle. Due the hardware limitations of the FPGA, it is not possible to reconstruct the image as a whole. So it is necessary to split up the image and reconstruct these parts separately. Despite that, a reconstruction of 512 projections into a 5122 image is calculated within 13 ms on a Virtex 5 FPGA. To save hardware resources we use fixed point arithmetic with an accuracy of 23 bit for calculation. A comparison of the result image and an image, calculated with floating point arithmetic on CPU, shows that there are no differences between these images. (orig.)

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

International Nuclear Information System (INIS)

Quinn, Heather M.; Graham, Paul S.; Morgan, Keith S.; Caffrey, Michael P.

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

A novel FPGA-based bunch purity monitor system at the APS storage ring

International Nuclear Information System (INIS)

Norum, W.E.

2008-01-01

Bunch purity is an important source quality factor for the magnetic resonance experiments at the Advanced Photon Source. Conventional bunch-purity monitors utilizing time-to-amplitude converters are subject to dead time. We present a novel design based on a single field- programmable gate array (FPGA) that continuously processes pulses at the full speed of the detector and front-end electronics. The FPGA provides 7778 single-channel analyzers (six per rf bucket). The starting time and width of each single-channel analyzer window can be set to a resolution of 178 ps. A detector pulse arriving inside the window of a single-channel analyzer is recorded in an associated 32-bit counter. The analyzer makes no contribution to the system dead time. Two channels for each rf bucket count pulses originating from the electrons in the bucket. The other four channels on the early and late side of the bucket provide estimates of the background. A single-chip microcontroller attached to the FPGA acts as an EPICS IOC to make the information in the FPGA available to the EPICS clients.

Multiplex measuring systems in physics

International Nuclear Information System (INIS)

Soroko, L.M.

1980-01-01

The principles of operation of multiplex devices used in different spheres of physics are discussed. The ''multiplex'' notion means that the data output of the device is an integral image of the functional dependence under investigation, but not its readings as in usual instruments. The analysis of the present state of developments of the multiplex systems in optics, nuclear magnetic resonance spectroscopy, in time-of-flight spectrometers for slow and fast neutrons, as well as elementary particle detectors, is given. The construction algorithms for the digital codes are presented, the history of development of the multiplex measuring principle is given [ru

A low delay transmission method of multi-channel video based on FPGA

Science.gov (United States)

Fu, Weijian; Wei, Baozhi; Li, Xiaobin; Wang, Quan; Hu, Xiaofei

2018-03-01

In order to guarantee the fluency of multi-channel video transmission in video monitoring scenarios, we designed a kind of video format conversion method based on FPGA and its DMA scheduling for video data, reduces the overall video transmission delay.In order to sace the time in the conversion process, the parallel ability of FPGA is used to video format conversion. In order to improve the direct memory access (DMA) writing transmission rate of PCIe bus, a DMA scheduling method based on asynchronous command buffer is proposed. The experimental results show that this paper designs a low delay transmission method based on FPGA, which increases the DMA writing transmission rate by 34% compared with the existing method, and then the video overall delay is reduced to 23.6ms.

Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

Directory of Open Access Journals (Sweden)

Burhan Khurshid

2015-05-01

Full Text Available Modern Field Programmable Gate Arrays (FPGA are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC primarily because of the low Non-recurring Engineering (NRE costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources.

FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES

Directory of Open Access Journals (Sweden)

M. Santhi

2010-03-01

Full Text Available In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

Energy Technology Data Exchange (ETDEWEB)

Yoo, Junbeom; Lee, Jonghoon [Konkuk Univ., Seoul (Korea, Republic of); Lee, Jangsoo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2013-08-15

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

International Nuclear Information System (INIS)

Yoo, Junbeom; Lee, Jonghoon; Lee, Jangsoo

2013-01-01

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea

A RESEARCH ON SEAMLESS PLATFORM CHANGE OF REACTOR PROTECTION SYSTEM FROM PLC TO FPGA

Directory of Open Access Journals (Sweden)

JUNBEOM YOO

2013-08-01

Full Text Available The PLC (Programmable Logic Controller has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems. Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array. Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

Directory of Open Access Journals (Sweden)

Burgess Shane C

2008-04-01

Full Text Available Abstract Background This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences. Results This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

International Nuclear Information System (INIS)

Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

2016-01-01

As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

Data acquisition system for charge-division mechanism based on FPGA

International Nuclear Information System (INIS)

Yang Litao; Li Dongcang; Yang Lei; Wu Huaiyi; Qi Zhong

2010-01-01

Design a system of Peak value acquisition, data processing and data output for 4 channels nuclear signal at the same time by FPGA that base on the basic principle of position information readout for particle through Charger-division Mechanism. In view of the randomness of nuclear signal, so insert asynchronous FIFO in the system, which greatly improve the sampling rate of system. In the article has produced the conjunctive relation and inner circuit structure and give out simulation. From here, you can see the great power of FPGA which used in nuclear data acquisition and processing system. (authors)

LDPC decoder with a limited-precision FPGA-based floating-point multiplication coprocessor

Science.gov (United States)

Moberly, Raymond; O'Sullivan, Michael; Waheed, Khurram

2007-09-01

Implementing the sum-product algorithm, in an FPGA with an embedded processor, invites us to consider a tradeoff between computational precision and computational speed. The algorithm, known outside of the signal processing community as Pearl's belief propagation, is used for iterative soft-decision decoding of LDPC codes. We determined the feasibility of a coprocessor that will perform product computations. Our FPGA-based coprocessor (design) performs computer algebra with significantly less precision than the standard (e.g. integer, floating-point) operations of general purpose processors. Using synthesis, targeting a 3,168 LUT Xilinx FPGA, we show that key components of a decoder are feasible and that the full single-precision decoder could be constructed using a larger part. Soft-decision decoding by the iterative belief propagation algorithm is impacted both positively and negatively by a reduction in the precision of the computation. Reducing precision reduces the coding gain, but the limited-precision computation can operate faster. A proposed solution offers custom logic to perform computations with less precision, yet uses the floating-point format to interface with the software. Simulation results show the achievable coding gain. Synthesis results help theorize the the full capacity and performance of an FPGA-based coprocessor.

Control de acceso usando FPGA y RFID

Directory of Open Access Journals (Sweden)

Dora Luz Almanza Ojeda

2012-10-01

Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

Adaptive Multi-Layered Space-Time Block Coded Systems in Wireless Environments

KAUST Repository

Al-Ghadhban, Samir

2014-12-23

© 2014, Springer Science+Business Media New York. Multi-layered space-time block coded systems (MLSTBC) strike a balance between spatial multiplexing and transmit diversity. In this paper, we analyze the block error rate performance of MLSTBC. In addition, we propose an adaptive MLSTBC schemes that are capable of accommodating the channel signal-to-noise ratio variation of wireless systems by near instantaneously adapting the uplink transmission configuration. The main results demonstrate that significant effective throughput improvements can be achieved while maintaining a certain target bit error rate.

Integrated photonics : compact multiplexing

NARCIS (Netherlands)

Pile, D.; Chen, H.; Uden, van R.G.H.; Okonkwo, C.M.; Koonen, A.M.J.

2015-01-01

Spatial multiplexers (SMUXs) for mode division multiplexing often involve multiple strategies for mode-selective excitation and the minimization of insertion and other losses. Haoshuo Chen, Roy van Uden, Chigo Okonkwo and Ton Koonen, working at the COBRA Institute at the Eindhoven University of

The implementing of high resolution time measuring circuit based on FPGA

International Nuclear Information System (INIS)

Zhang Ji; Zeng Yun; Wang Zheng; Li Quiju; Lu Jifang; Wu Jinyuan

2011-01-01

It presents the implementing of TDC based on FPGA. The fine timing function part is accomplished through the time interpolators that are composed of the carry chain of intrinsic adders in FPGA. This architecture dates back to the latest technology-WUTDC (Wave Union TDC) that is developed to sub-divide the ultra-wide bins and improve the measure resolution. The board and the online test have been proved that the linearity of converters is satisfying and the time resolution is better than 40 ps. (authors)

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

International Nuclear Information System (INIS)

Ren, Y J; Zhu, J G; Yang, X Y; Ye, S H

2006-01-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

Science.gov (United States)

Ren, Y. J.; Zhu, J. G.; Yang, X. Y.; Ye, S. H.

2006-10-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent.

Dynamic Optically Multiplexed Imaging

Science.gov (United States)

2015-07-29

Dynamic Optically Multiplexed Imaging Yaron Rachlin, Vinay Shah, R. Hamilton Shepard, and Tina Shih Lincoln Laboratory, Massachusetts Institute of...V. Shah, and T. Shih “Design Architectures for Optically Multiplexed Imaging,” in submission 9 R. Gupta , P. Indyk, E. Price, and Y. Rachlin

Polarization-multiplexing ghost imaging

Science.gov (United States)

Dongfeng, Shi; Jiamin, Zhang; Jian, Huang; Yingjian, Wang; Kee, Yuan; Kaifa, Cao; Chenbo, Xie; Dong, Liu; Wenyue, Zhu

2018-03-01

A novel technique for polarization-multiplexing ghost imaging is proposed to simultaneously obtain multiple polarimetric information by a single detector. Here, polarization-division multiplexing speckles are employed for object illumination. The light reflected from the objects is detected by a single-pixel detector. An iterative reconstruction method is used to restore the fused image containing the different polarimetric information by using the weighted sum of the multiplexed speckles based on the correlation coefficients obtained from the detected intensities. Next, clear images of the different polarimetric information are recovered by demultiplexing the fused image. The results clearly demonstrate that the proposed method is effective.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

DEFF Research Database (Denmark)

Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

2015-01-01

standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

Timing measurements of some tracking algorithms and suitability of FPGA's to improve the execution speed

CERN Document Server

Khomich, A; Kugel, A; Männer, R; Müller, M; Baines, J T M

2003-01-01

Some of track reconstruction algorithms which are common to all B-physics channels and standard RoI processing have been tested for execution time and assessed for suitability for speed-up by using FPGA coprocessor. The studies presented in this note were performed in the C/C++ framework, CTrig, which was the fullest set of algorithms available at the time of study For investigation of possible speed-up of algorithms most time consuming parts of TRT-LUT was implemented in VHDL for running in FPGA coprocessor board MPRACE. MPRACE (Reconfigurable Accelerator / Computing Engine) is an FPGA-Coprocessor based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim. Timing measurements results for a TRT Full Scan algorithm executed on the MPRACE are presented here as well. The measurement results show a speed-up factor of ~2 for this algorithm.

An FPGA bridge preserving traffing quality of service for on-chip network-based systems

NARCIS (Netherlands)

Nejad, A.B.; Escudero Martinez, M.; Goossens, K.G.W.

2011-01-01

FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into

A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

Science.gov (United States)

Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

2015-10-01

Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

Science.gov (United States)

Du, Hongtao; Qi, Hairong; Szu, Harold H.

2005-03-01

Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

Science.gov (United States)

2015-12-01

shelf (COTS) field- programmable gate array (FPGA) at the optimized factor levels established from the DOE and varying the programmed signal. This...signature using APREL’s EM-ISight automated system is hypothesized to be a novel way to accomplish this task. Research Questions The research...a field programmable gate array (FPGA) is the circuit board utilized for testing the inherent electromagnetic signature. Every device produces an

Desain Protokol Suara Sebagai Pengendali Dalam Smart Home Menggunakan FPGA

Directory of Open Access Journals (Sweden)

Barlian Henryranu Prasetio

2017-05-01

Smart home is a system that uses computers and information technology to control home-like equipment such as windows and lights. The system can be a simple control system to a complex system. Computer / microcontroller based on internet/ethernet network equipped with intelligent system and automation system so as to make home to work automatically. Many computer devices / microcontrollers that can be implemented as a controller in the smart home. Smart home control system in this study using Xilinx xpartan-3e that controls the equipment in the house through LAN (Local Area Networking. This control system communicates using broadcast voice on the local network. The Controller System is designed to be able to transmit a voice signal packet from the microphone input and then send it using the ethernet protocol in the home local network using the FPGA. The FPGA is programmed to transmit and encode data packets, converting digital data into analog data to be able to control the equipment in the home. From the simulation test results using ISIM, it is seen that the system works in realtime. Keywords: smart home, voice, fpga, control

An FPGA-Based People Detection System

Directory of Open Access Journals (Sweden)

James J. Clark

2005-05-01

Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

Superconducting cavity driving with FPGA controller

Energy Technology Data Exchange (ETDEWEB)

Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

2006-07-01

The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

Superconducting cavity driving with FPGA controller

International Nuclear Information System (INIS)

Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.; Brand, A.; Chase, B.; Carcagno, R.; Cancelo, G.; Koeth, T.W.

2006-01-01

The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Science.gov (United States)

Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

2014-01-01

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

A FPGA embedded web server for remote monitoring and control of smart sensors networks.

Science.gov (United States)

Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

2013-12-27

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Directory of Open Access Journals (Sweden)

Eduardo Magdaleno

2013-12-01

Full Text Available This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI. The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A. Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

Intermediate Frequency Digital Receiver Based on Multi-FPGA System

Directory of Open Access Journals (Sweden)

Chengchang Zhang

2016-01-01

Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods

Directory of Open Access Journals (Sweden)

Bakos Jason D

2010-04-01

Full Text Available Abstract Background Likelihood (ML-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. Results We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10× speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Conclusions Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs 1.

Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration

DEFF Research Database (Denmark)

Nannarelli, Alberto; Re, M.; Cardarilli, Gian Carlo

2017-01-01

Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over-clocking th......Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over...

FPGA Realization of Memory 10 Viterbi Decoder

DEFF Research Database (Denmark)

Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

1997-01-01

sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

Development of FPGA-based digital signal processing system for radiation spectroscopy

International Nuclear Information System (INIS)

Lee, Pil Soo; Lee, Chun Sik; Lee, Ju Hahn

2013-01-01

We have developed an FPGA-based digital signal processing system that performs both online digital signal filtering and pulse-shape analysis for both particle and gamma-ray spectroscopy. Such functionalities were made possible by a state-of-the-art programmable logic device and system architectures employed. The system performance as measured, for example, in the system dead time and accuracy for pulse-height and rise-time determination, was evaluated with standard alpha- and gamma-ray sources using a CsI(Tl) scintillation detector. It is resulted that the present system has shown its potential application to various radiation-related fields such as particle identification, radiography, and radiation imaging. - Highlights: ► An FPGA-based digital processing system was developed for radiation spectroscopy. ► Our digital system has a 14-bit resolution and a 100-MHz sampling rate. ► The FPGA implements the online digital filtering and pulse-shape analysis. ► The pileup rejection is implemented in trigger logic before digital filtering process. ► Our digital system was verified in alpha-gamma measurements using a CsI detector

A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA

OpenAIRE

Zhang, Xinyu; Das, Srinjoy; Neopane, Ojash; Kreutz-Delgado, Ken

2017-01-01

In recent years deep learning algorithms have shown extremely high performance on machine learning tasks such as image classification and speech recognition. In support of such applications, various FPGA accelerator architectures have been proposed for convolutional neural networks (CNNs) that enable high performance for classification tasks at lower power than CPU and GPU processors. However, to date, there has been little research on the use of FPGA implementations of deconvolutional neural...

On-chip mode division multiplexing technologies

DEFF Research Database (Denmark)

Ding, Yunhong; Frellsen, Louise Floor; Guan, Xiaowei

2016-01-01

Space division multiplexing (SDM) is currently widely investigated in order to provide enhanced capacity thanks to the utilization of space as a new degree of multiplexing freedom in both optical fiber communication and on-chip interconnects. Basic components allowing the processing of spatial...... photonic integrated circuit mode (de) multiplexer for few-mode fibers (FMFs)....

Design of CMOS imaging system based on FPGA

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

FPGA-based network data transmission scheme for CSNS

International Nuclear Information System (INIS)

Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

2012-01-01

This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method.

Science.gov (United States)

Zhang, Chen; Liang, Tianzhu; Mok, Philip K T; Yu, Weichuan

2017-07-01

In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, "feature-motion decorrelation" still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these methods is the high computational complexity. Even the graphics processing unit (GPU)-based program requires a long time to finish the analysis. In this paper, we propose field-programmable gate array (FPGA)-based implementations of both methods for further acceleration. The capability of FPGAs on handling different image processing components in these methods is discussed. A fast and memory-saving image warping approach is proposed. The algorithms are reformulated to build a highly efficient pipeline on FPGA. The final implementations on a Xilinx Virtex-7 FPGA are at least 13 times faster than the GPU implementation on the NVIDIA graphic card (GeForce GTX 580).

Design and Implementation of Radar Cross-Section Models on a Virtex-6 FPGA

Directory of Open Access Journals (Sweden)

B. U. V. Prashanth

2014-01-01

Full Text Available The simulation of radar cross-section (RCS models in FPGA is illustrated. The models adopted are the Swerling ones. Radar cross-section (RCS which is also termed as echo area gives the amount of scattered power from a target towards the radar. This paper elucidates the simulation of RCS to represent the specified targets under different conditions, namely, aspect angle and frequency. This model is used for the performance evaluation of radar. RCS models have been developed for various targets like simple objects to complex objects like aircrafts, missiles, tanks, and so forth. First, the model was developed in MATLAB real time simulation environment and after successful verification, the same was implemented in FPGA. Xilinx ISE software was used for VHDL coding. This simulation model was used for the testing of a radar system. The results were compared with MATLAB simulations and FPGA based timing diagrams and RTL synthesis. The paper illustrates the simulation of various target radar cross-section (RCS models. These models are simulated in MATLAB and in FPGA, with the aim of implementing them efficiently on a radar system. This method can be generalized to apply to objects of arbitrary geometry for the two configurations of transmitter and receiver in the same as well as different locations.

Automated Metabolic P System Placement in FPGA

Directory of Open Access Journals (Sweden)

Kulakovskis Darius

2016-07-01

Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

Embedded Active Vision System Based on an FPGA Architecture

Directory of Open Access Journals (Sweden)

Chalimbaud Pierre

2007-01-01

Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

Embedded Active Vision System Based on an FPGA Architecture

Directory of Open Access Journals (Sweden)

Pierre Chalimbaud

2006-12-01

Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

Steatocystoma multiplex hos 39-årig kvinde

DEFF Research Database (Denmark)

Duffy, Jonas Raymond; Siersen, Hans Erik; Bonde, Christian T

2011-01-01

-coloured cystic lesions on the chest, abdomen, axillae and back. The patient's clinical presentations and history were compatible with steatocystoma multiplex. Various treatment options for steatocystoma multiplex and steatocystoma multiplex suppurativum have been published and include oral antibiotics...

Efficient and side-channel resistant authenticated encryption of FPGA bitstreams

DEFF Research Database (Denmark)

Bogdanov, Andrey; Moradi, Amir; Yalcin, Tolga

2013-01-01

AE modes of operation with the same countermeasure. We conclude that the deployment of dedicated AE schemes such as ALE significantly facilitates the real-world efficiency and security of FPGA bitstream protection in practice: Not only our solution enables authenticated encryption for bitstream...... on low-cost FPGAs but it also aims to mitigate physical attacks which have been lately shown to undermine the security of the bitstream protection mechanisms in the field.......State-of-the-art solutions for FPGA bitstream protection rely on encryption and authentication of the bitstream to both ensure its confidentiality, thwarting unauthorized copying and reverse engineering, and prevent its unauthorized modification, maintaining a root of trust in the field. Adequate...

Signal compression in radar using FPGA

OpenAIRE

Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

2010-01-01

We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

Explaining HIV Risk Multiplexity: A Social Network Analysis.

Science.gov (United States)

Felsher, Marisa; Koku, Emmanuel

2018-04-21

Risk multiplexity (i.e., overlap in drug-use, needle exchange and sexual relations) is a known risk factor for HIV. However, little is known about predictors of multiplexity. This study uses egocentric data from the Colorado Springs study to examine how individual, behavioral and social network factors influence engagement in multiplex risk behavior. Analyses revealed that compared to Whites, Hispanics were significantly more likely to engage in risk multiplexity and Blacks less so. Respondents who were similar to each other (e.g., in terms of race) had significantly higher odds of being in risk multiplex relationships, and respondents' risk perceptions and network size were significantly associated with engaging in multiplex risk behaviors. Findings from interaction analysis showed the effect of knowing someone with HIV on the odds of multiplexity depends partly on whether respondents' know their HIV status. Findings suggest that demographics, HIV behaviors and network factors impact engagement in multiplex risk behaviors, highlighting the need for multi-level interventions aimed at reducing HIV risk behavior.

The current state of FPGA technology in the nuclear domain

Energy Technology Data Exchange (ETDEWEB)

Ranta, J.

2012-07-01

Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

The current state of FPGA technology in the nuclear domain

International Nuclear Information System (INIS)

Ranta, J.

2012-01-01

Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

Percolation in real multiplex networks

Science.gov (United States)

Bianconi, Ginestra; Radicchi, Filippo

2016-12-01

We present an exact mathematical framework able to describe site-percolation transitions in real multiplex networks. Specifically, we consider the average percolation diagram valid over an infinite number of random configurations where nodes are present in the system with given probability. The approach relies on the locally treelike ansatz, so that it is expected to accurately reproduce the true percolation diagram of sparse multiplex networks with negligible number of short loops. The performance of our theory is tested in social, biological, and transportation multiplex graphs. When compared against previously introduced methods, we observe improvements in the prediction of the percolation diagrams in all networks analyzed. Results from our method confirm previous claims about the robustness of real multiplex networks, in the sense that the average connectedness of the system does not exhibit any significant abrupt change as its individual components are randomly destroyed.

Fpga based L-band pulse doppler radar design and implementation

Science.gov (United States)

Savci, Kubilay

As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed

Single Event Effects in FPGA Devices 2015-2016

Science.gov (United States)

Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

2016-01-01

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

FPGA-Based Embedded Motion Estimation Sensor

Directory of Open Access Journals (Sweden)

Zhaoyi Wei

2008-01-01

Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

Modular high power diode lasers with flexible 3D multiplexing arrangement optimized for automated manufacturing

Science.gov (United States)

Könning, Tobias; Bayer, Andreas; Plappert, Nora; Faßbender, Wilhelm; Dürsch, Sascha; Küster, Matthias; Hubrich, Ralf; Wolf, Paul; Köhler, Bernd; Biesenbach, Jens

2018-02-01

A novel 3-dimensional arrangement of mirrors is used to re-arrange beams from 1-D and 2-D high power diode laser arrays. The approach allows for a variety of stacking geometries, depending on individual requirements. While basic building blocks, including collimating optics, always remain the same, most adaptations can be realized by simple rearrangement of a few optical components. Due to fully automated alignment processes, the required changes can be realized in software by changing coordinates, rather than requiring customized mechanical components. This approach minimizes development costs due to its flexibility, while reducing overall product cost by using similar building blocks for a variety of products and utilizing a high grade of automation. The modules can be operated with industrial grade water, lowering overall system and maintenance cost. Stackable macro coolers are used as the smallest building block of the system. Each cooler can hold up to five diode laser bars. Micro optical components, collimating the beam, are mounted directly to the cooler. All optical assembly steps are fully automated. Initially, the beams from all laser bars propagate in the same direction. Key to the concept is an arrangement of deflectors, which re-arrange the beams into a 2-D array of the desired shape and high fill factor. Standard multiplexing techniques like polarization- or wavelengths-multiplexing have been implemented as well. A variety of fiber coupled modules ranging from a few hundred watts of optical output power to multiple kilowatts of power, as well as customized laser spot geometries like uniform line sources, have been realized.

Design of the device of auto-measuring radon continuously based on FPGA

International Nuclear Information System (INIS)

Wang Yan; Shen Zhengqin; Chen Qiong

2004-01-01

This paper introduces the design of the device of auto-measuring radon continuously. The core of the system is the design of controlling system by FPGA, which consists of preset module, electrical calendar module and driving module. The system can automatically measure the consistence of the radon and the separating out rate of it. The information data is displayed by LCD. The high speed micro printer is used to print the measuring result. It adopts FPGA to design the measuring system of the device, which can improve the precision and stability of the system. (authors)

Embedded algorithms within an FPGA-based system to process nonlinear time series data

Science.gov (United States)

Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

2008-03-01

This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better

Design of optical axis jitter control system for multi beam lasers based on FPGA

Science.gov (United States)

Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

2018-02-01

A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

Spatial analysis of various multiplex cinema types

Directory of Open Access Journals (Sweden)

Young-Seo Park

2016-03-01

Full Text Available This study identifies the spatial characteristics and relationships of each used space according to the multiplex type. In this study, multiplexes are classified according to screen rooms and circulation systems, and each used space is quantitatively analyzed. The multiplex type based on screen rooms and moving line systems influences the relationship and characteristics of each used space in various ways. In particular, the structure of the used space of multiplexes has a significant effect on profit generation and audience convenience.

Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Directory of Open Access Journals (Sweden)

Chiung-Wei Huang

2018-01-01

Full Text Available We propose a prototype of field programmable gate array (FPGA implementation for optimal pixel adjustment process (OPAP algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC to an FPGA board using RS232 interface for hardware processing. We firstly embed k-bit secret message into each pixel of the cover image by the last-significant-bit (LSB substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.

An FPGA-based reconfigurable DDC algorithm

Science.gov (United States)

Juszczyk, B.; Kasprowicz, G.

2016-09-01

This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

THESEUS: A wavelength division multiplexed/microwave subcarrier multiplexed optical network, its ATM switch applications and device requirements

Science.gov (United States)

Xin, Wei

1997-10-01

A Terabit Hybrid Electro-optical /underline[Se]lf- routing Ultrafast Switch (THESEUS) has been proposed. It is a self-routing wavelength division multiplexed (WDM) / microwave subcarrier multiplexed (SCM) asynchronous transfer mode (ATM) switch for the multirate ATM networks. It has potential to be extended to a large ATM switch as 1000 x 1000 without internal blocking. Among the advantages of the hybrid implementation are flexibility in service upgrade, relaxed tolerances on optical filtering, protocol simplification and less processing overhead. For a small ATM switch, the subcarrier can be used as output buffers to solve output contention. A mathematical analysis was conducted to evaluate different buffer configurations. A testbed has been successfully constructed. Multirate binary data streams have been switched through the testbed and error free reception ([<]10-9 bit error rate) has been achieved. A simple, intuitive theoretical model has been developed to describe the heterodyne optical beat interference. A new concept of interference time and interference length has been introduced. An experimental confirmation has been conducted. The experimental results match the model very well. It shows that a large portion of optical bandwidth is wasted due to the beat interference. Based on the model, several improvement approaches have been proposed. The photo-generated carrier lifetime of silicon germanium has been measured using time-resolved reflectivity measurement. Via oxygen ion implantation, the carrier lifetime has been reduced to as short as 1 ps, corresponding to 1 THz of photodetector bandwidth. It has also been shown that copper dopants act as recombination centers in the silicon germanium.

Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

International Nuclear Information System (INIS)

Messai, A.; Mellit, A.; Massi Pavan, A.; Guessoum, A.; Mekki, H.

2011-01-01

Research highlights: → FL-MPPT controller is implemented on FPGA. → Results obtained with ModelSim show a satisfactory performance. → Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

Energy Technology Data Exchange (ETDEWEB)

Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mellit, A., E-mail: a.mellit@yahoo.co.u [Department of Electronics, Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Massi Pavan, A. [Department of Materials and Natural Resources, University of Trieste, Via A. Valerio, 2 - 34127 Trieste (Italy); Guessoum, A. [Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mekki, H. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria)

2011-07-15

Research highlights: {yields} FL-MPPT controller is implemented on FPGA. {yields} Results obtained with ModelSim show a satisfactory performance. {yields} Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

VHDL, FPGA and the master trigger controller of BES

International Nuclear Information System (INIS)

Guo Yanan; Wang Jufang; Zhao Dixin

1996-01-01

A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

Performance enhancement of multi-core fiber transmission using real-time FPGA based pre-emphasis

DEFF Research Database (Denmark)

Hasanuzzaman, G. K.M.; Spolitis, Sandis; Salgals, T.

2017-01-01

We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA.......We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA....

A novel IPTV program multiplex access system to EPON

Science.gov (United States)

Xu, Xian; Liu, Deming; He, Wei; Lu, Xi

2007-11-01

With the rapid development of high speed networks, such as Ethernet Passive Optical Network (EPON), traffic patterns in access networks have evolved from traditional text-oriented service to the mixed text-, voice- and video- based services, leading to so called "Triple Play". For supporting IPTV service in EPON access network infrastructure, in this article we propose a novel IPTV program multiplex access system to EPON, which enables multiple IPTV program source servers to seamlessly access to IPTV service access port of optical line terminal (OLT) in EPON. There are two multiplex schemes, namely static multiplex scheme and dynamic multiplex scheme, in implementing the program multiplexing. Static multiplex scheme is to multiplex all the IPTV programs and forward them to the OLT, regardless of the need of end-users. While dynamic multiplex scheme can dynamically multiplex and forward IPTV programs according to what the end-users actually demand and those watched by no end-user would not be multiplexed. By comparing these two schemes, a reduced traffic of EPON can be achieved by using dynamic multiplex scheme, especially when most end-users are watching the same few IPTV programs. Both schemes are implemented in our system, with their hardware and software designs described.

Bilevel alarm monitoring multiplexer

International Nuclear Information System (INIS)

Johnson, C.S.

1977-06-01

This report describes the operation of the Bilevel Alarm Monitoring Multiplexer used in the Adaptive Intrusion Data System (AIDS) to transfer and control alarm signals being sent to the Nova 2 computer, the Memory Controlled Data Processor, and its own integral Display Panel. The multiplexer can handle 48 alarm channels and format the alarms into binary formats compatible with the destination of the alarm data

Acceleration of Cherenkov angle reconstruction with the new Intel Xeon/FPGA compute platform for the particle identification in the LHCb Upgrade

Science.gov (United States)

Faerber, Christian

2017-10-01

The LHCb experiment at the LHC will upgrade its detector by 2018/2019 to a ‘triggerless’ readout scheme, where all the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to readout the detector at 40 MHz. This increases the data bandwidth from the detector down to the Event Filter farm to 40 TBit/s, which also has to be processed to select the interesting proton-proton collision for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered for use inside the new Event Filter farm. In the high performance computing sector more and more FPGA compute accelerators are used to improve the compute performance and reduce the power consumption (e.g. in the Microsoft Catapult project and Bing search engine). Also for the LHCb upgrade the usage of an experimental FPGA accelerated computing platform in the Event Building or in the Event Filter farm is being considered and therefore tested. This platform from Intel hosts a general CPU and a high performance FPGA linked via a high speed link which is for this platform a QPI link. On the FPGA an accelerator is implemented. The used system is a two socket platform from Intel with a Xeon CPU and an FPGA. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. As a first step, a computing intensive algorithm to reconstruct Cherenkov angles for the LHCb RICH particle identification was successfully ported in Verilog to the Intel Xeon/FPGA platform and accelerated by a factor of 35. The same algorithm was ported to the Intel Xeon/FPGA platform with OpenCL. The implementation work and the performance will be compared. Also another FPGA accelerator the Nallatech 385 PCIe accelerator with the same Stratix V FPGA were tested for performance. The results show that the Intel

Frequency multiplexing for readout of spin qubits

Energy Technology Data Exchange (ETDEWEB)

Hornibrook, J. M.; Colless, J. I.; Mahoney, A. C.; Croot, X. G.; Blanvillain, S.; Reilly, D. J., E-mail: david.reilly@sydney.edu.au [ARC Centre of Excellence for Engineered Quantum Systems, School of Physics, University of Sydney, Sydney, NSW 2006 (Australia); Lu, H.; Gossard, A. C. [Materials Department, University of California, Santa Barbara, California 93106 (United States)

2014-03-10

We demonstrate a low loss, chip-level frequency multiplexing scheme for readout of scaled-up spin qubit devices. By integrating separate bias tees and resonator circuits on-chip for each readout channel, we realise dispersive gate-sensing in combination with charge detection based on two radio frequency quantum point contacts. We apply this approach to perform multiplexed readout of a double quantum dot in the few-electron regime and further demonstrate operation of a 10-channel multiplexing device. Limitations for scaling spin qubit readout to large numbers of multiplexed channels are discussed.

Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

Science.gov (United States)

Xia, Fei; Jin, Guoqing

2014-06-01

PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

Parallel Hough Transform-Based Straight Line Detection and Its FPGA Implementation in Embedded Vision

Directory of Open Access Journals (Sweden)

Nam Ling

2013-07-01

Full Text Available Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

Science.gov (United States)

Zhu, Yuhua; Zhu, Dan; Wang, Jianing

2012-09-01

As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

Parallel Hough Transform-based straight line detection and its FPGA implementation in embedded vision.

Science.gov (United States)

Lu, Xiaofeng; Song, Li; Shen, Sumin; He, Kang; Yu, Songyu; Ling, Nam

2013-07-17

Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA) provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT) and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

National Research Council Canada - National Science Library

Bardouleau, Graham; Kulp, James

2005-01-01

In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

Preliminary study of visual effect of multiplex hologram

Science.gov (United States)

Fu, Huaiping; Xiong, Bingheng; Yang, Hong; Zhang, Xueguo

2004-06-01

The process of any movement of real object can be recorded and displayed by a multiplex holographic stereogram. An embossing multiplex holographic stereogram and a multiplex rainbow holographic stereogram have been made by us, the multiplex rainbow holographic stereogram reconstructs the dynamic 2D line drawing of speech organs, the embossing multiplex holographic stereogram reconstructs the process of an old man drinking water. In this paper, we studied the visual result of an embossing multiplex holographic stereogram made with 80 films of 2-D pictures. Forty-eight persons of aged from 13 to 67 were asked to see the hologram and then to answer some questions about the feeling of viewing. The results indicate that this kind of holograms could be accepted by human visual sense organ without any problem. This paper also discusses visual effect of the multiplex holography stereograms base on visual perceptual psychology. It is open out that the planar multiplex holograms can be recorded and present the movement of real animal and object. Not only have the human visual perceptual constancy for shape, just as that size, color, etc... but also have visual perceptual constancy for binocular parallax.

Small Microprocessor for ASIC or FPGA Implementation

Science.gov (United States)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

FPGA Implementation of Computer Vision Algorithm

OpenAIRE

Zhou, Zhonghua

2014-01-01

Computer vision algorithms, which play an significant role in vision processing, is widely applied in many aspects such as geology survey, traffic management and medical care, etc.. Most of the situations require the process to be real-timed, in other words, as fast as possible. Field Programmable Gate Arrays (FPGAs) have a advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms. The...

17 bit 4.35 mW 1 kHz Delta Sigma ADC and 256-to-1 multiplexer for remote handling instrumentation equipment

Energy Technology Data Exchange (ETDEWEB)

Verbeeck, Jens, E-mail: jens.verbeeck@esat.kuleuven.be [KU Leuven, Department ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KH Kempen University College, IBW-RELIC, Kleinhoefstraat 4, 2440 Geel (Belgium); Van Uffelen, Marco [Fusion for Energy, c/Josep, n° 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Steyaert, Michiel [KU Leuven, Department ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, Department ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KH Kempen University College, IBW-RELIC, Kleinhoefstraat 4, 2440 Geel (Belgium)

2013-10-15

Highlights: ► We present a radiation hard 17 bit-1 kHz 4.35 mW Delta Sigma ADC. ► A radiation tolerant 256-to-1 multiplexer is shown. ► We propose a generic radiation tolerant ASIC for use in an instrumentation link. ► The ASIC can interface more than hundred pressure or resistive sensors. ► All building blocks have a simulated radiation tolerance of more than 1 MGy. -- Abstract: A radiation tolerant Delta-Sigma Analog-to-Digital Converter (ADC) and multiplexer is presented. The design features a 1.5 V, 17 bit ADC consuming 4.35 mW at a sample frequency of 1 MHz. The ADC features a bandwidth of 1 kHz and utilizes a Correlated Double Sampling technique (CDS) to remove offset and 1/f noise. The circuit maintains its 17 bit resolution upon a simulated radiation dose exceeding 1 MGy and varying temperatures between 0 °C and 85 °C. Next a multiplexer is presented. It can multiplex 256 channels at a clock frequency of 128 MHz or has a data throughput of 256 MSample/s. In addition the bit period of the multiplexer varies less then 1.5% due to the influence of temperature or radiation, which proves the temperature and radiation tolerance.

Demonstration of hybrid orbital angular momentum multiplexing and time-division multiplexing passive optical network.

Science.gov (United States)

Wang, Andong; Zhu, Long; Liu, Jun; Du, Cheng; Mo, Qi; Wang, Jian

2015-11-16

Mode-division multiplexing passive optical network (MDM-PON) is a promising scheme for next-generation access networks to further increase fiber transmission capacity. In this paper, we demonstrate the proof-of-concept experiment of hybrid mode-division multiplexing (MDM) and time-division multiplexing (TDM) PON architecture by exploiting orbital angular momentum (OAM) modes. Bidirectional transmissions with 2.5-Gbaud 4-level pulse amplitude modulation (PAM-4) downstream and 2-Gbaud on-off keying (OOK) upstream are demonstrated in the experiment. The observed optical signal-to-noise ratio (OSNR) penalties for downstream and upstream transmissions at a bit-error rate (BER) of 2 × 10(-3) are less than 2.0 dB and 3.0 dB, respectively.

Direct Measurement of Power Dissipated by Monte Carlo Simulations on CPU and FPGA Platforms

OpenAIRE

Albicocco, Pietro; Papini, Davide; Nannarelli, Alberto

2012-01-01

In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which is a popular algorithm used in financial computations. The Hall effect probe measurements complement the measurements performed on the core of the FPGA by a built-in Xilinxpower monitoring system.

Using Simulated Partial Dynamic Run-Time Reconfiguration to Share Embedded FPGA Compute and Power Resources across a Swarm of Unpiloted Airborne Vehicles

Directory of Open Access Journals (Sweden)

Kearney David

2007-01-01

Full Text Available We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGA's resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarm based on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Directory of Open Access Journals (Sweden)

Hasitha Muthumala Waidyasooriya

2017-01-01

Full Text Available Finite difference time domain (FDTD method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a “C-like” programming language called OpenCL (open computing language. As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

8-channel, FPGA based, DSP integrated cavity simulator and controller for VUV-FEL. SIMCON 3.0 Ver. 3.0. rev. 1, 06.2005 - Hardware manual

International Nuclear Information System (INIS)

Pozniak, K.T.; Czarski, T.; Koprek, W.; Giergusiewicz, W.; Romaniuk, R.S.

2005-01-01

The note describes integrated, eight channel system of hardware controller and simulator of the resonant superconducting, narrowband niobium cavity, originally considered for the TTF and TESLA in DESY, Hamburg (now tested for the VUV FEL and developed for X-Ray FEL). The controller bases on a programmable circuit Xilinx VirtexII V4000. The solution uses DSP EMBEDDED BOARD module positioned on a Modular LLRF Control Platform. The algorithm and FPGA circuit configuration was done in the VHDL language. The internal hardware multiplication components, present in Virtex II chips, were used, to improve the floating point calculation efficiency. The implementation was achieved of a device working in the real time, according to the demands of the LLRF control system for the TESLA Test Facility (now associated with the VUV FEL machine). The device under consideration will be referred to as superconducting cavity (SCCav) SIMCON throughout this work. The manual describes hardware features of SIMCON, ver. 3.0 in modular solution. The following components are described here in detail: functional layer, parameter programming, foundations of control of particular blocks and monitoring of the real time processes. This note is accompanied by the one describing the multichannel DOOCS interface for the described hardware system. The interface was prepared in DOOCS for Solaris and in Windows. The hardware and software of 8-channel SIMCON was tested in CHECIA and ACC1 module of VUV FEL linac. The measurements results are presented. While giving all necessary technical details required to understand the work of the integrated hardware controller and simulator and to enable its practical copying, this document is a unity with other TESLA technical notes published by the same team on the subject. Thus, some modeling and other subjects were omitted, as they were addressed in detail in the quoted references. Keywords: Super conducting cavity, cavity simulator, CAVITIES CONTROLLER, SIMCON

Signal multiplexing scheme for LINAC

International Nuclear Information System (INIS)

Sujo, C.I.; Mohan, Shyam; Joshi, Gopal; Singh, S.K.; Karande, Jitendra

2004-01-01

For the proper operation of the LINAC some signals, RF (radio frequency) as well as LF (low frequency) have to be available at the Master Control Station (MCS). These signals are needed to control, calibrate and characterize the RF fields in the resonators. This can be achieved by proper multiplexing of various signals locally and then routing the selected signals to the MCS. A multiplexing scheme has been designed and implemented, which will allow the signals from the selected cavity to the MCS. High isolation between channels and low insertion loss for a given signal are important issues while selecting the multiplexing scheme. (author)

Real-time digital simulation of power electronics systems with Neutral Point Piloted multilevel inverter using FPGA

Energy Technology Data Exchange (ETDEWEB)

Rakotozafy, Mamianja [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France); Poure, Philippe [Laboratoire d' Instrumentation Electronique de Nancy (LIEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Saadate, Shahrokh [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Bordas, Cedric; Leclere, Loic [CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France)

2011-02-15

Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital simulators.As an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (author)

A FPGA-based signal processing unit for a GEM array detector

International Nuclear Information System (INIS)

Yen, W.W.; Chou, H.P.

2013-06-01

in the present study, a signal processing unit for a GEM one-dimensional array detector is presented to measure the trajectory of photoelectrons produced by cosmic X-rays. The present GEM array detector system has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies. The prototype of the processing unit is implemented using commercial field programmable gate array circuit boards. The FPGA based system is linked to a personal computer for testing and data analysis. Tests using simulated signals indicated that the FPGA-based signal processing unit has a good linearity and is flexible for parameter adjustment for various experimental conditions (authors)

Implementation of the 2-D Wavelet Transform into FPGA for Image

Science.gov (United States)

León, M.; Barba, L.; Vargas, L.; Torres, C. O.

2011-01-01

This paper presents a hardware system implementation of the of discrete wavelet transform algoritm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

Implementation of the 2-D Wavelet Transform into FPGA for Image

Energy Technology Data Exchange (ETDEWEB)

Leon, M; Barba, L; Vargas, L; Torres, C O, E-mail: madeleineleon@unicesar.edu.co [Laboratorio de Optica e Informatica, Universidad Popular del Cesar, Sede balneario Hurtado, Valledupar, Cesar (Colombia)

2011-01-01

This paper presents a hardware system implementation of the of discrete wavelet transform algorithm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

Thermally multiplexed polymerase chain reaction.

Science.gov (United States)

Phaneuf, Christopher R; Pak, Nikita; Saunders, D Curtis; Holst, Gregory L; Birjiniuk, Joav; Nagpal, Nikita; Culpepper, Stephen; Popler, Emily; Shane, Andi L; Jerris, Robert; Forest, Craig R

2015-07-01

Amplification of multiple unique genetic targets using the polymerase chain reaction (PCR) is commonly required in molecular biology laboratories. Such reactions are typically performed either serially or by multiplex PCR. Serial reactions are time consuming, and multiplex PCR, while powerful and widely used, can be prone to amplification bias, PCR drift, and primer-primer interactions. We present a new thermocycling method, termed thermal multiplexing, in which a single heat source is uniformly distributed and selectively modulated for independent temperature control of an array of PCR reactions. Thermal multiplexing allows amplification of multiple targets simultaneously-each reaction segregated and performed at optimal conditions. We demonstrate the method using a microfluidic system consisting of an infrared laser thermocycler, a polymer microchip featuring 1 μl, oil-encapsulated reactions, and closed-loop pulse-width modulation control. Heat transfer modeling is used to characterize thermal performance limitations of the system. We validate the model and perform two reactions simultaneously with widely varying annealing temperatures (48 °C and 68 °C), demonstrating excellent amplification. In addition, to demonstrate microfluidic infrared PCR using clinical specimens, we successfully amplified and detected both influenza A and B from human nasopharyngeal swabs. Thermal multiplexing is scalable and applicable to challenges such as pathogen detection where patients presenting non-specific symptoms need to be efficiently screened across a viral or bacterial panel.

Signal compression in radar using FPGA

Directory of Open Access Journals (Sweden)

Enrique Escamilla Hemández

2010-01-01

Full Text Available El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array. El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR. El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde nos centramos en obtener una mejor atenuación para los valores de lóbulos laterales. La arquitectura propuesta explota los recursos de computación paralela de los dispositivos FPGA para alcanzar una mejor velocidad de cómputo. Las investigaciones experimentales han demostrado que los mejores resultados para el funcionamiento de la compresión del pulso se han obtenido usando las funciones atómicas, mejorando el funcionamiento del sistema del radar en presencia de ruido, y consiguiendo una pequeña degradación en la resolución de rango. La puesta en práctica del tratamiento de señales en el sistema de radar en tiempo real se discute y se justifica la eficiencia de la arquitectura de hardware propuesta.

Wire Position Monitoring with FPGA based Electronics

International Nuclear Information System (INIS)

Eddy, N.; Lysenko, O.

2009-01-01

This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

fpga controller design and simulation of a portable dough mixing

African Journals Online (AJOL)

modelled and simulated with Matlab/Simulink. Synthesizable VHDL ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ... and (b) to simulate the control process in a virtual environment, using.

Real-time distortion correction for visual inspection systems based on FPGA

Science.gov (United States)

Liang, Danhua; Zhang, Zhaoxia; Chen, Xiaodong; Yu, Daoyin

2008-03-01

Visual inspection is a kind of new technology based on the research of computer vision, which focuses on the measurement of the object's geometry and location. It can be widely used in online measurement, and other real-time measurement process. Because of the defects of the traditional visual inspection, a new visual detection mode -all-digital intelligent acquisition and transmission is presented. The image processing, including filtering, image compression, binarization, edge detection and distortion correction, can be completed in the programmable devices -FPGA. As the wide-field angle lens is adopted in the system, the output images have serious distortion. Limited by the calculating speed of computer, software can only correct the distortion of static images but not the distortion of dynamic images. To reach the real-time need, we design a distortion correction system based on FPGA. The method of hardware distortion correction is that the spatial correction data are calculated first under software circumstance, then converted into the address of hardware storage and stored in the hardware look-up table, through which data can be read out to correct gray level. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified.

N queens on an fpga: mathematics,programming, or both?

NARCIS (Netherlands)

Kuper, Jan; Wester, Rinse

2014-01-01

This paper presents a design methodology for deriving an FPGA implementation directly from a mathematical specification, thus avoiding the switch in semantic perspective as is present in widely applied methods which include an imperative implementation as an intermediate step. The first step in the

Effective and efficient FPGA synthesis through general functional decomposition

NARCIS (Netherlands)

Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.

2003-01-01

In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom–up general functional decomposition and theory of information relationship measures that we

FPGA-based implementation of sorting networks in MMC applications

DEFF Research Database (Denmark)

Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

2016-01-01

, and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

Implementació d'una Cache per a un processador MIPS d'una FPGA

OpenAIRE

Riera Villanueva, Marc

2013-01-01

[CATALÀ] Primer s'explicarà breument l'arquitectura d'un MIPS, la jerarquia de memòria i el funcionament de la cache. Posteriorment s'explicarà com s'ha dissenyat i implementat una jerarquia de memòria per a un MIPS implementat en VHDL en una FPGA. [ANGLÈS] First, the MIPS architecture, memory hierarchy and the functioning of the cache will be explained briefly. Then, the design and implementation of a memory hierarchy for a MIPS processor implemented in VHDL on an FPGA will be explained....

Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

National Research Council Canada - National Science Library

Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

2005-01-01

.... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

International Nuclear Information System (INIS)

Anderson, Harold D.; Williams, John T.

2009-01-01

The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Based on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens

FPGA implementation of a hybrid on-line process monitoring in PC based real-time systems

Directory of Open Access Journals (Sweden)

Jovanović Bojan

2011-01-01

Full Text Available This paper presents one way of FPGA implementation of hybrid (hardware-software based on-line process monitoring in Real-Time systems (RTS. The reasons for RTS monitoring are presented at the beginning. The summary of different RTS monitoring approaches along with its advantages and drawbacks are also exposed. Finally, monitoring module is described in details. Also, FPGA implementation results and some useful monitoring system applications are mentioned.

Laguerre Gaussian beam multiplexing through turbulence

CSIR Research Space (South Africa)

Trichili, A

2014-08-17

Full Text Available We analyze the effect of atmospheric turbulence on the propagation of multiplexed Laguerre Gaussian modes. We present a method to multiplex Laguerre Gaussian modes using digital holograms and decompose the resulting field after encountering a...

FPGA Implementation of a Simple 3D Graphics Pipeline

Directory of Open Access Journals (Sweden)

Vladimir Kasik

2015-01-01

Full Text Available Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing.

SEU mitigation technique by Dynamic Reconfiguration method in FPGA based DSP application

International Nuclear Information System (INIS)

Dey, Madhusudan; Singh, Abhishek; Roy, Amitava

2012-01-01

Field Programmable Gate Array (FPGA), an SRAM based configurable devices meant for implementation of any digital circuits is susceptible to malfunction in the harsh radiation environment. It causes the corruption of the configuration memory of FPGA and the digital circuits starts malfunctioning. There is a need to restore the system as early as possible. This paper discusses about one such technique named dynamic partial reconfiguration (DPR) method. This paper also touches upon the signal processing by DPR method. The framework consisting of ADC, DAC and ICAP controllers designed using dedicated state machines to study the best possible downtime also for verifying the performance of digital filters for signal processing

Integration of multi-interface conversion channel using FPGA for modular photonic network

Science.gov (United States)

Janicki, Tomasz; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

2010-09-01

The article discusses the integration of different types of interfaces with FPGA circuits using a reconfigurable communication platform. The solution has been implemented in practice in a single node of a distributed measurement system. Construction of communication platform has been presented with its selected hardware modules, described in VHDL and implemented in FPGA circuits. The graphical user interface (GUI) has been described that allows a user to control the operation of the system. In the final part of the article selected practical solutions have been introduced. The whole measurement system resides on multi-gigabit optical network. The optical network construction is highly modular, reconfigurable and scalable.

Implementation of FPGA based PID Controller for DC Motor Speed Control System

Directory of Open Access Journals (Sweden)

Savita SONOLI

2010-03-01

Full Text Available In this paper, the implementation of software module using ‘VHDL’ for Xilinx FPGA (XC3S400 based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.2i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed.

Analysis of blocking probability for OFDM-based variable bandwidth optical network

Science.gov (United States)

Gong, Lei; Zhang, Jie; Zhao, Yongli; Lin, Xuefeng; Wu, Yuyao; Gu, Wanyi

2011-12-01

Orthogonal Frequency Division Multiplexing (OFDM) has recently been proposed as a modulation technique. For optical networks, because of its good spectral efficiency, flexibility, and tolerance to impairments, optical OFDM is much more flexible compared to traditional WDM systems, enabling elastic bandwidth transmissions, and optical networking is the future trend of development. In OFDM-based optical network the research of blocking rate has very important significance for network assessment. Current research for WDM network is basically based on a fixed bandwidth, in order to accommodate the future business and the fast-changing development of optical network, our study is based on variable bandwidth OFDM-based optical networks. We apply the mathematical analysis and theoretical derivation, based on the existing theory and algorithms, research blocking probability of the variable bandwidth of optical network, and then we will build a model for blocking probability.

An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

International Nuclear Information System (INIS)

Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah; Choi, Jong Gyun

2014-01-01

NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity

An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

Energy Technology Data Exchange (ETDEWEB)

Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun [KAERI, Daejeon (Korea, Republic of)

2014-08-15

NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity.

Advanced combinational microfluidic multiplexer for fuel cell reactors

International Nuclear Information System (INIS)

Lee, D W; Kim, Y; Cho, Y-H; Doh, I

2013-01-01

An advanced combinational microfluidic multiplexer capable to address multiple fluidic channels for fuel cell reactors is proposed. Using only 4 control lines and two different levels of control pressures, the proposed multiplexer addresses up to 19 fluidic channels, at least two times larger than the previous microfluidic multiplexers. The present multiplexer providing high control efficiency and simple structure for channel addressing would be used in the application areas of the integrated microfluidic systems such as fuel cell reactors and dynamic pressure generators

An Intelligent FPGA Based Anti-Sweating System for Bed Sore Prevention in a Clinical Environment

Directory of Open Access Journals (Sweden)

K. S. Jaichandar

2011-01-01

Full Text Available Bed sores, a common problem among immobile patients occur as a result of continuous sweating due to increase in skin to bed surface temperature in patients lying on same posture for prolonged period. If left untreated, the skin can break open and become infected. Currently adopted methods for bed sores prevention include: use of two hourly flip chat for repositioning patient or use of air fluidized beds. However, the setbacks of these preventive measures include either use of costly equipment or wastage of human resources. This paper introduces an intelligent low cost FPGA based anti-sweating system for bed sores prevention in a clinical environment. The developed system consists of bed surface implanted temperature sensors interfaced with an FPGA chip for sensing the temperature change in patient’s skin to bed surface. Based on the temperature change, the FPGA chip select the - mode (heater/cooler and speed of the fan module. Furthermore, an alarm module was implemented to alert the nurse to reposition the patient only if patient’s skin to bed surface temperature exceeds a predefined threshold thereby saving human resources. By integrating the whole system into a single FPGA chip, we were able to build a low cost compact system without sacrificing processing power and flexibility.

A Signature-Based Power Model for MPSoC on FPGA

Directory of Open Access Journals (Sweden)

Roberta Piscitelli

2012-01-01

Full Text Available This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

Embedded System Implementation on FPGA System With μCLinux OS

International Nuclear Information System (INIS)

Amin, Ahmad Fairuz Muhd; Aris, Ishak; Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah

2011-01-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Embedded System Implementation on FPGA System With μCLinux OS

Science.gov (United States)

Fairuz Muhd Amin, Ahmad; Aris, Ishak; Syamsul Azmir Raja Abdullah, Raja; Kalos Zakiah Sahbudin, Ratna

2011-02-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Embedded System Implementation on FPGA System With {mu}CLinux OS

Energy Technology Data Exchange (ETDEWEB)

Amin, Ahmad Fairuz Muhd [Institute of Advanced Technology, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Aris, Ishak [Department of Electrical and Electronic Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia); Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah, E-mail: gs20613@mutiara.upm.edu.my, E-mail: ishak@eng.upm.edu.my, E-mail: rsa@eng.upm.edu.my [Department of Computer and Communication Systems Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia)

2011-02-15

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), {mu}Clinux. In this paper, an example of web server is explained and demonstrated

Research on acceleration method of reactor physics based on FPGA platforms

International Nuclear Information System (INIS)

Li, C.; Yu, G.; Wang, K.

2013-01-01

The physical designs of the new concept reactors which have complex structure, various materials and neutronic energy spectrum, have greatly improved the requirements to the calculation methods and the corresponding computing hardware. Along with the widely used parallel algorithm, heterogeneous platforms architecture has been introduced into numerical computations in reactor physics. Because of the natural parallel characteristics, the CPU-FPGA architecture is often used to accelerate numerical computation. This paper studies the application and features of this kind of heterogeneous platforms used in numerical calculation of reactor physics through practical examples. After the designed neutron diffusion module based on CPU-FPGA architecture achieves a 11.2 speed up factor, it is proved to be feasible to apply this kind of heterogeneous platform into reactor physics. (authors)

Modified SURF Algorithm Implementation on FPGA For Real-Time Object Tracking

Directory of Open Access Journals (Sweden)

Tomyslav Sledevič

2013-05-01

Full Text Available The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84×84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640×480 pixel camera.Article in Lithuanian

Analysis of Thermal Stability of Different Counter on 28nm FPGA

DEFF Research Database (Denmark)

Gupta, Daizy; Yadav, Amit; Hussain, Dil muhammed Akbar

2016-01-01

In this paper we are presenting the power analysis for thermal awareness of different counters. The technique we are using to do the analysis is based on 28 nm FPGA tech-nique. In this work during implementation on FPGA, we are going to analyze thermal stability of different counters in temperatu...... range of 10oC, 30oC, 60oC, 90oC, 120oC. There is 90.36% reduction in leakage power of divide by 2 counter when we scale down the temperature from 120oC to 10oC and 49.61% reduction in leakage power of LFSR up counter when we scale down the temperature from 120oC to 10oC....

Spacewire Routers Implemented with FPGA Technology

Science.gov (United States)

Habinc, Sandi; Isomaki, Marko

2011-08-01

Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

Science.gov (United States)

Yokoyama, Yoshiaki; Kim, Minseok; Arai, Hiroyuki

At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.

Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

International Nuclear Information System (INIS)

Jalmuzna, W.

2006-02-01

The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

Energy Technology Data Exchange (ETDEWEB)

Jalmuzna, W.

2006-02-15

The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

Multiplexed image storage by electromagnetically induced transparency in a solid

Science.gov (United States)

Heinze, G.; Rentzsch, N.; Halfmann, T.

2012-11-01

We report on frequency- and angle-multiplexed image storage by electromagnetically induced transparency (EIT) in a Pr3+:Y2SiO5 crystal. Frequency multiplexing by EIT relies on simultaneous storage of light pulses in atomic coherences, driven in different frequency ensembles of the inhomogeneously broadened solid medium. Angular multiplexing by EIT relies on phase matching of the driving laser beams, which permits simultaneous storage of light pulses propagating under different angles into the crystal. We apply the multiplexing techniques to increase the storage capacity of the EIT-driven optical memory, in particular to implement multiplexed storage of larger two-dimensional amounts of data (images). We demonstrate selective storage and readout of images by frequency-multiplexed EIT and angular-multiplexed EIT, as well as the potential to combine both multiplexing approaches towards further enhanced storage capacities.

Design issues on using FPGA-based I and C systems in nuclear reactors

Energy Technology Data Exchange (ETDEWEB)

Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

2015-07-01

The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

Frequency-domain readout multiplexing of transition-edge sensor arrays

Energy Technology Data Exchange (ETDEWEB)

Lanting, T.M. [Physics Department, University of California, Berkeley, CA 94720 (United States)]. E-mail: tlanting@berkeley.edu; Arnold, K. [Physics Department, University of California, Berkeley, CA 94720 (United States); Cho, Hsiao-Mei [Physics Department, University of California, Berkeley, CA 94720 (United States); Clarke, John [Physics Department, University of California, Berkeley, CA 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Dobbs, Matt [Physics Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Holzapfel, William [Physics Department, University of California, Berkeley, CA 94720 (United States); Lee, Adrian T. [Physics Department, University of California, Berkeley, CA 94720 (United States); Physics Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Lueker, M. [Physics Department, University of California, Berkeley, CA 94720 (United States); Richards, P.L. [Physics Department, University of California, Berkeley, CA 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Space Sciences Laboratory, University of California, Berkeley, CA 94720 (United States); Smith, A.D. [Northrop-Grumman, Redondo Beach, CA 94278 (United States); Spieler, H.G. [Physics Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

2006-04-15

We have demonstrated frequency-domain readout multiplexing of eight channels for superconducting transition-edge sensor bolometer arrays. The multiplexed readout noise is 6.5 pA/{radical}Hz, well below the bolometer dark noise of 15-20 pA/{radical}Hz. We measure an upper limit on crosstalk of 0.004 between channels adjacent in frequency which meets our design requirement of 0.01. We have observed vibration insensitivity in our frequency-domain multiplexed transition-edge sensors, making this system very attractive for telescope and satellite observations. We also discuss extensions to our multiplexed readout. In particular, we are developing a SQUID flux-locked loop that is entirely cold and collaborating on digital multiplexer technology in order to scale up the number of multiplexed channels.

Realization of manchester encoding and decoding and fast-speed communication for digital power supply based on FPGA

International Nuclear Information System (INIS)

Chen Huanguang; Xu Ruinian; Shen Tianjian; Li Deming

2008-01-01

A design and simulation to realize the process of Manchester encoding and decoding, to realize the process of SPI communication between FPGA and DSP, using Altera company's Quartus II IDE on FPGA is presented in this paper. And the application on the digital power supply controller with Manchester communication by optical fiber is introduced. (authors)

Immunization of Epidemics in Multiplex Networks

Science.gov (United States)

Zhao, Dawei; Wang, Lianhai; Li, Shudong; Wang, Zhen; Wang, Lin; Gao, Bo

2014-01-01

Up to now, immunization of disease propagation has attracted great attention in both theoretical and experimental researches. However, vast majority of existing achievements are limited to the simple assumption of single layer networked population, which seems obviously inconsistent with recent development of complex network theory: each node could possess multiple roles in different topology connections. Inspired by this fact, we here propose the immunization strategies on multiplex networks, including multiplex node-based random (targeted) immunization and layer node-based random (targeted) immunization. With the theory of generating function, theoretical analysis is developed to calculate the immunization threshold, which is regarded as the most critical index for the effectiveness of addressed immunization strategies. Interestingly, both types of random immunization strategies show more efficiency in controlling disease spreading on multiplex Erdös-Rényi (ER) random networks; while targeted immunization strategies provide better protection on multiplex scale-free (SF) networks. PMID:25401755

Immunization of epidemics in multiplex networks.

Science.gov (United States)

Zhao, Dawei; Wang, Lianhai; Li, Shudong; Wang, Zhen; Wang, Lin; Gao, Bo

2014-01-01

Up to now, immunization of disease propagation has attracted great attention in both theoretical and experimental researches. However, vast majority of existing achievements are limited to the simple assumption of single layer networked population, which seems obviously inconsistent with recent development of complex network theory: each node could possess multiple roles in different topology connections. Inspired by this fact, we here propose the immunization strategies on multiplex networks, including multiplex node-based random (targeted) immunization and layer node-based random (targeted) immunization. With the theory of generating function, theoretical analysis is developed to calculate the immunization threshold, which is regarded as the most critical index for the effectiveness of addressed immunization strategies. Interestingly, both types of random immunization strategies show more efficiency in controlling disease spreading on multiplex Erdös-Rényi (ER) random networks; while targeted immunization strategies provide better protection on multiplex scale-free (SF) networks.

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

Directory of Open Access Journals (Sweden)

Alisson C. D. de Souza

2014-09-01

Full Text Available This paper proposes a parallel fixed point radial basis function (RBF artificial neural network (ANN, implemented in a field programmable gate array (FPGA trained online with a least mean square (LMS algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx, with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

TESLA cavity modeling and digital implementation in FPGA technology for control system development

International Nuclear Information System (INIS)

Czarski, T.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.

2006-01-01

The electromechanical model of the TESLA cavity has been implemented in FPGA technology for real-time testing of the control system. The model includes Lorentz force detuning and beam loading effects. Step operation and vector stimulus operation modes are applied for the evaluation of a FPGA cavity simulator operated by a digital controller. The performance of the cavity hardware model is verified by comparing with a software model of the cavity implemented in the MATLAB system. The numerical aspects are considered for an optimal DSP calculation. Some experimental results are presented for different cavity operational conditions. (orig.)

Design and implementation of a programming circuit in radiation-hardened FPGA

International Nuclear Information System (INIS)

Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

2011-01-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

A low-cost, FPGA-based servo controller with lock-in amplifier

International Nuclear Information System (INIS)

Yang, G; Barry, J F; Shuman, E S; Steinecker, M H; DeMille, D

2012-01-01

We describe the design and implementation of a low-cost, FPGA-based servo controller with an integrated waveform synthesizer and lock-in amplifier. This system has been designed with the specific application of laser frequency locking in mind but should be adaptable to a variety of other purposes as well. The system incorporates an onboard waveform synthesizer, a lock-in amplifier, two channels of proportional-integral (PI) servo control, and a ramp generator on a single FPGA chip. The system is based on an inexpensive, off-the-shelf FPGA evaluation board with a wide variety of available accessories, allowing the system to interface with standard laser controllers and detectors while minimizing the use of custom hardware and electronics. Gains, filter constants, and other relevant parameters are adjustable via onboard knobs and switches. These parameters and other information are displayed to the user via an integrated LCD, allowing full operation of the device without an accompanying computer. We demonstrate the performance of the system in a test setup, in which the frequency of a tunable external-cavity diode laser (ECDL) is locked to a resonant optical transmission peak of a Fabry-Perot cavity. In this setup, we achieve a total servo-loop bandwidth of ∼ 7 kHz and achieve locking of the ECDL to the cavity with a full-width-at-half-maximum (FWHM) linewidth of ∼ 200 kHz.

Design and implementation of a programming circuit in radiation-hardened FPGA

Science.gov (United States)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Junction Temperature Aware Energy Efficient Router Design on FPGA

DEFF Research Database (Denmark)

Thind, Vandana; Sharma, Shivani; Minwer, M H

2015-01-01

Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

Energy Technology Data Exchange (ETDEWEB)

Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of)

2014-10-15

Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases.

A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

International Nuclear Information System (INIS)

Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom

2014-01-01

Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases

Hyperchaotic Chameleon: Fractional Order FPGA Implementation

Directory of Open Access Journals (Sweden)

Karthikeyan Rajagopal

2017-01-01

Full Text Available There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA implementations of the systems with their power and resource utilization are presented.

Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Jain, Vishal; Sharma, Rashmi

2017-01-01

In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three.......33%, 86%, 90.67%, 65.33%, 52%, and 48.67% reduction in IO power dissipation of FIR Filter design on CSG324 package of Artix-7 FPGA family....

Implementación de un procesador MIPS en una FPGA

OpenAIRE

Guillen Fandos, David

2012-01-01

L'objectiu del projecte és el disseny i implementació d'un computador al voltant d'un processador MIPS. Aquest computador ha de funcionar a una placa de demostració Terasic DE2-115, que disposa d'una FPGA Altera Cyclone IV.

Immunization of epidemics in multiplex networks.

Directory of Open Access Journals (Sweden)

Dawei Zhao

Full Text Available Up to now, immunization of disease propagation has attracted great attention in both theoretical and experimental researches. However, vast majority of existing achievements are limited to the simple assumption of single layer networked population, which seems obviously inconsistent with recent development of complex network theory: each node could possess multiple roles in different topology connections. Inspired by this fact, we here propose the immunization strategies on multiplex networks, including multiplex node-based random (targeted immunization and layer node-based random (targeted immunization. With the theory of generating function, theoretical analysis is developed to calculate the immunization threshold, which is regarded as the most critical index for the effectiveness of addressed immunization strategies. Interestingly, both types of random immunization strategies show more efficiency in controlling disease spreading on multiplex Erdös-Rényi (ER random networks; while targeted immunization strategies provide better protection on multiplex scale-free (SF networks.

Optimizing diffusion in multiplexes by maximizing layer dissimilarity

Science.gov (United States)

Serrano, Alfredo B.; Gómez-Gardeñes, Jesús; Andrade, Roberto F. S.

2017-05-01

Diffusion in a multiplex depends on the specific link distribution between the nodes in each layer, but also on the set of the intralayer and interlayer diffusion coefficients. In this work we investigate, in a quantitative way, the efficiency of multiplex diffusion as a function of the topological similarity among multiplex layers. This similarity is measured by the distance between layers, taken among the pairs of layers. Results are presented for a simple two-layer multiplex, where one of the layers is held fixed, while the other one can be rewired in a controlled way in order to increase or decrease the interlayer distance. The results indicate that, for fixed values of all intra- and interlayer diffusion coefficients, a large interlayer distance generally enhances the global multiplex diffusion, providing a topological mechanism to control the global diffusive process. For some sets of networks, we develop an algorithm to identify the most sensitive nodes in the rewirable layer, so that changes in a small set of connections produce a drastic enhancement of the global diffusion of the whole multiplex system.

Available number of multiplexed holograms based on signal-to-noise ratio analysis in reflection-type holographic memory using three-dimensional speckle-shift multiplexing.

Science.gov (United States)

Nishizaki, Tatsuya; Matoba, Osamu; Nitta, Kouichi

2014-09-01

The recording properties of three-dimensional speckle-shift multiplexing in reflection-type holographic memory are analyzed numerically. Three-dimensional recording can increase the number of multiplexed holograms by suppressing the cross-talk noise from adjacent holograms by using depth-direction multiplexing rather than in-plane multiplexing. Numerical results indicate that the number of multiplexed holograms in three-layer recording can be increased by 1.44 times as large as that of a single-layer recording when an acceptable signal-to-noise ratio is set to be 2 when NA=0.43 and the thickness of the recording medium is 0.5 mm.

Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

DEFF Research Database (Denmark)

Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

2016-01-01

Multiplier is used for multiplication of a signal and a constant in digital signal processing (DSP). 28nm technology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and XPower Analyzer. Vedic multiplier gain speed improvements by parallelizing the generation...... Programmable Gate Array (FPGA) in order to reduce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy...... efficient Vedic multiplier.There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively....

Strain measurement using multiplexed fiber optic sensors

International Nuclear Information System (INIS)

Kwon, Il Bum; Kim, Chi Yeop; Yoon, Dong Jin; Lee, Seung Seok

2003-01-01

FBG(Fiber Bragg grating) sensor, which is one of the fiber optic sensors for the application of smart structures, can not only measure one specific point but also multiple points by multiplexing techniques. We have proposed a novel multiplexing technique of FBG sensor by the intensity modulation of light source. This technique is applicable to WDM(Wavelength Division Multiplexing) technique and number of sensors in this system can be increased by using this technique with WDM technique.

A Sea-of-Gates Style FPGA Placement Algorithm

Directory of Open Access Journals (Sweden)

Kalapi Roy

1996-01-01

Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

Anti Theft Mechanism Through Face recognition Using FPGA

Science.gov (United States)

Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

2012-11-01

The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

Science.gov (United States)

Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

2017-06-01

A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

Application of the Information Encryption Technology in the Industrial Control Network Based on FPGA

Directory of Open Access Journals (Sweden)

Guo Yao-Hua

2014-07-01

Full Text Available With the rapid development of information technology industry, Information encryption is an effective means of information security. Data encryption system based on FPGA in the field of industry is elaborated in this paper, and the data acquisition module, the basic principle of 3DES algorithm, its implementation in FPGA and PMC bus interface module are introduced. Based on the function simulation, test and analysis of the design results, this scheme has the characteristics of high reliability, fast algorithm and less hardware resources, and it can be widely used in industrial networks.

An FPGA-based bolometer for the MAST-U Super-X divertor

Energy Technology Data Exchange (ETDEWEB)

Lovell, Jack, E-mail: jack.lovell@durham.ac.uk [Durham University, South Road, Durham DH1 3LE (United Kingdom); Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Naylor, Graham; Field, Anthony [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Drewelow, Peter [MPI für Plasmaphysik, Greifswald (Germany); Sharples, Ray [Durham University, South Road, Durham DH1 3LE (United Kingdom); Collaboration: EUROfusion Consortium, JET, Culham Science Centre, Abingdon OX14 3DB (United Kingdom)

2016-11-15

A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

V&V Plan for FPGA-based ESF-CCS Using System Engineering Approach.

Science.gov (United States)

Maerani, Restu; Mayaka, Joyce; El Akrat, Mohamed; Cheon, Jung Jae

2018-02-01

Instrumentation and Control (I&C) systems play an important role in maintaining the safety of Nuclear Power Plant (NPP) operation. However, most current I&C safety systems are based on Programmable Logic Controller (PLC) hardware, which is difficult to verify and validate, and is susceptible to software common cause failure. Therefore, a plan for the replacement of the PLC-based safety systems, such as the Engineered Safety Feature - Component Control System (ESF-CCS), with Field Programmable Gate Arrays (FPGA) is needed. By using a systems engineering approach, which ensures traceability in every phase of the life cycle, from system requirements, design implementation to verification and validation, the system development is guaranteed to be in line with the regulatory requirements. The Verification process will ensure that the customer and stakeholder’s needs are satisfied in a high quality, trustworthy, cost efficient and schedule compliant manner throughout a system’s entire life cycle. The benefit of the V&V plan is to ensure that the FPGA based ESF-CCS is correctly built, and to ensure that the measurement of performance indicators has positive feedback that “do we do the right thing” during the re-engineering process of the FPGA based ESF-CCS.

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Directory of Open Access Journals (Sweden)

Paolo Meloni

2012-01-01

Full Text Available Application Specific Instruction-set Processors (ASIPs expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

Specification of requirements for the implementation of ASICs and FPGA in instrumentation and control systems important to safety in German NPPs

International Nuclear Information System (INIS)

Schnurer, G.

2007-01-01

This paper gives an overview concerning the design as well as the verification and validation of Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGA) in German NPPs which are applied to carry out I and C functions. The qualification procedures dealt with restricted on ASICs without any microcontroller core. Dependent on the different safety categories, recommendations concerning the qualification level and procedures are elaborated which have to be achieved for ASICs and FPGA. Important aspects within the framework of the expert judgement for upgrading of safety relevant I and C by ASICs and FPGA are dealt with. These aspects are of general character and are mainly focused on suitability test procedures and robustness requirements of ASICs and FPGA

Optical network and FPGA/DSP based control system for free electron laser

International Nuclear Information System (INIS)

Romaniuk, R.S.; Pozniak, K.T.; Czarski, T.; Czuba, K.; Giergusiewicz, W.; Kasprowicz, G.; Koprek, W.

2005-01-01

The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to

Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Rehman, M. Atiqur; Hussain, Dil muhammed Akbar

2016-01-01

, SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA......nm FPGA....

A signature-based power model for MPSoC on FPGA

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2012-01-01

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used

A high-level power model for MPSoC on FPGA

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2012-01-01

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the

Controlador empotrado en FPGA para Sistema Inteligente de Transporte

Directory of Open Access Journals (Sweden)

Alejandro José Cabrera Sarmiento

2011-11-01

Full Text Available 1024x768 Normal 0 21 false false false ES X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} En el presente trabajo se expone la concepción, desarrollo e implementación de un controlador empotrado en un FPGA de Xilinx para ser utilizado en un Sistema Inteligente de Transporte (SIT. La estructura hardware del controlador está basada en la utilización de diversos módulos de propiedad intelectual del sistema de procesamiento MicroBlaze y el soporte de software está basado en la utilización del sistema operativo Petalinux. El controlador empotrado dispone de interfaces Ethernet, USB, UART, SPI e I2C para la comunicación con los diferentes niveles jerárquicos del SIT. Ha sido implementado sobre una placa de desarrollo basada en un FPGA Spartan3E de 1.200 k compuertas, ocupando un 59% de sus recursos configurables. El resto de los recursos disponibles en el FPGA permite, además de la posible actualización del controlador, la implementación hardware de algoritmos que requieren una alta velocidad de procesamiento.

Multirate Digital Filters Based on FPGA and Its Applications

International Nuclear Information System (INIS)

Sharaf El-Din, R.M.A.

2013-01-01

Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

Directory of Open Access Journals (Sweden)

Manuel Saldaña

2012-01-01

Full Text Available Partial reconfiguration (PR is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.

FPGA based phase detection technique for electron density measurement in SST-1 tokamak

International Nuclear Information System (INIS)

Pramila; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

2016-01-01

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

FPGA based phase detection technique for electron density measurement in SST-1 tokamak

Energy Technology Data Exchange (ETDEWEB)

Pramila, E-mail: pramila@ipr.res.in; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

2016-11-15

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

FPGA based fast synchronous serial multi-wire links synchronization

Science.gov (United States)

Pozniak, Krzysztof T.

2013-10-01

The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

A New FPGA Architecture of FAST and BRIEF Algorithm for On-Board Corner Detection and Matching.

Science.gov (United States)

Huang, Jingjin; Zhou, Guoqing; Zhou, Xiang; Zhang, Rongting

2018-03-28

Although some researchers have proposed the Field Programmable Gate Array (FPGA) architectures of Feature From Accelerated Segment Test (FAST) and Binary Robust Independent Elementary Features (BRIEF) algorithm, there is no consideration of image data storage in these traditional architectures that will result in no image data that can be reused by the follow-up algorithms. This paper proposes a new FPGA architecture that considers the reuse of sub-image data. In the proposed architecture, a remainder-based method is firstly designed for reading the sub-image, a FAST detector and a BRIEF descriptor are combined for corner detection and matching. Six pairs of satellite images with different textures, which are located in the Mentougou district, Beijing, China, are used to evaluate the performance of the proposed architecture. The Modelsim simulation results found that: (i) the proposed architecture is effective for sub-image reading from DDR3 at a minimum cost; (ii) the FPGA implementation is corrected and efficient for corner detection and matching, such as the average value of matching rate of natural areas and artificial areas are approximately 67% and 83%, respectively, which are close to PC's and the processing speed by FPGA is approximately 31 and 2.5 times faster than those by PC processing and by GPU processing, respectively.

FPGA based algorithms for data reduction at Belle II

Energy Technology Data Exchange (ETDEWEB)

Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

2011-07-01

Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

Optimizing latency in Xilinx FPGA implementations of the GBT

CERN Document Server

Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

2010-01-01

The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

FPGA Dynamic Power Minimization through Placement and Routing Constraints

Directory of Open Access Journals (Sweden)

Deepak Agarwal

2006-08-01

Full Text Available Field-programmable gate arrays (FPGAs are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.

Clock Gating Based Energy Efficient and Thermal Aware Design for Vedic Equation Solver on 28nm and 40nm FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Pandey, Sujeet; Sharma, Shivani

2016-01-01

In this paper, we are integrating clock gating in design of energy efficient equation solver circuits based on Vedic mathematics. Clock gating is one of the best energy efficient techniques. The Sutra 'SunyamSamyasamuccaye' says thatif sum of numerator and sum of denominator is same then we can e......, 94.54% for 1800MHz, and 94.02% for 2.2GHz, when we use gated clock instead of un gated one on 40nm FPGA and temperature is 329.85K. Power consumption in 28nm FPGA is less than 40nm FPGA....

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

Science.gov (United States)

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

Fault injection as a test method for an FPGA in charge of data readout for a large tracking detector

CERN Document Server

Roed, K; Richter, M; Fehlker, D; Helstrup, H; Alme, J; Ullaland, K

2011-01-01

This paper describes how fault injection has been implemented as a test method for an FPGA in an existing hardware configuration setup. As this FPGA is in charge of data readout for a large tracking detector, the reliability of this FPGA is of high importance. Due to the complexity of the readout electronics, irradiation testing is technically difficult at this stage of the system commissioning. The work presented in this paper is therefore motivated by introducing fault injection as an alternative method to characterize failures caused by SEUs. It is a method to study the effect that a configuration upset may have on the operation of the FPGA. The target platform consists of two independent modules for data acquisition and detector control functionality. Fault injection to test the response of the data acquisition module is made possible by implementing the solution as part of the detector control functionality. Correct implementation is validated by a simple shift register design. Our results demonstrate th...

Multichannel analyzer embedded in FPGA

International Nuclear Information System (INIS)

Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

2017-10-01

Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

An improved real time superresolution FPGA system

Science.gov (United States)

Lakshmi Narasimha, Pramod; Mudigoudar, Basavaraj; Yue, Zhanfeng; Topiwala, Pankaj

2009-05-01

In numerous computer vision applications, enhancing the quality and resolution of captured video can be critical. Acquired video is often grainy and low quality due to motion, transmission bottlenecks, etc. Postprocessing can enhance it. Superresolution greatly decreases camera jitter to deliver a smooth, stabilized, high quality video. In this paper, we extend previous work on a real-time superresolution application implemented in ASIC/FPGA hardware. A gradient based technique is used to register the frames at the sub-pixel level. Once we get the high resolution grid, we use an improved regularization technique in which the image is iteratively modified by applying back-projection to get a sharp and undistorted image. The algorithm was first tested in software and migrated to hardware, to achieve 320x240 -> 1280x960, about 30 fps, a stunning superresolution by 16X in total pixels. Various input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as in FPGA hardware, which gives us a fine balance between the number of bits and performance. The proposed system is robust and highly efficient. We have shown the performance improvement of the hardware superresolution over the software version (C code).

FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

Science.gov (United States)

Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

2016-05-01

This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

Real Time Implementation of a DC Motor Speed Control by Fuzzy Logic Controller and PI Controller Using FPGA

Directory of Open Access Journals (Sweden)

G. Sakthivel

2010-10-01

Full Text Available Fuzzy logic control has met with growing interest in many motor control applications due to its non-linearity, handling features and independence of plant modelling. The hardware implementation of fuzzy logic controller (FLC on FPGA is very important because of the increasing number of fuzzy applications requiring highly parallel and high speed fuzzy processing. Implementation of a fuzzy logic controller and conventional PI controller on an FPGA using VHDL for DC motor speed control is presented in this paper. The proposed scheme is to improve tracking performance of D.C. motor as compared to the conventional (PI control strategy .This paper describes the hardware implementation of two inputs (error and change in error, one output fuzzy logic controller based on PI controller and conventional PI controller using VHDL. Real time implementation FLC and conventional PI controller is made on Spartan-3A DSP FPGA (XC3SD1800A FPGA for the speed control of DC motor. It is observed that fuzzy logic based controllers give better responses than the conventional PI controller for the speed control of dc motor.

FPGA implementation of image dehazing algorithm for real time applications

Science.gov (United States)

Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

2017-09-01

Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

General method of synthesis by PLIC/FPGA digital devices to ...

African Journals Online (AJOL)

A general method is proposed to synthesize digital devices in order to perform discrete orthogonal transformations (DOT) on programmable logic integrated circuits (PLIC) of FPGA class. The basic and the most "slow" operation during DOT performance is the operation of multiplying by a constant factor (constant) - OMC.

Using an FPGA for Fast Bit Accurate SoC Simulation

NARCIS (Netherlands)

Wolkotte, P.T.; Holzenspies, P.K.F.; Smit, Gerardus Johannes Maria

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit

A high-level power model for MPSoC on FPGA

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2011-01-01

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, e.g., commonly-used instruction-set

Test of Gb Ethernet with FPGA for HADES upgrade

Energy Technology Data Exchange (ETDEWEB)

Gilardi, C. [II. Physikalisches Inst., Giessen Univ. (Germany)

2007-07-01

Within the HADES experiment, we are investigating a trigger upgrade in order to run heavier systems (Au + Au). We investigate Gigabit Ethernet transfers with Xilinx Virtex II FPGA on the commercial board Celoxica RC300E. We implement the transfer protocols (UDP, ICMP, ARP) with Handel-C. First results of bandwidth and latency will be presented. (orig.)

Real-time particle image velocimetry based on FPGA technology;Velocimetria PIV en tiempo real basada en logica programable FPGA

Energy Technology Data Exchange (ETDEWEB)

Iriarte Munoz, Jose Miguel [Universidad Nacional de Cuyo, Instituto Balseiro, Centro Atomico Bariloche (Argentina)

2008-07-01

Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach.;La velocimetria por imagenes de particulas (PIV), basada en plano laser, es una potente herramienta de medicion en dinamica de fluidos, capaz de medir sin grandes errores, un campo de velocidades distribuido en liquidos, gases y flujo multifase.Los altos requerimientos computacionales de los algoritmos PIV dificultan su empleo en tiempo-real.En este trabajo presentamos el diseno de una plataforma basada en tecnologia FPGA para capturar video y procesar en tiempo real el algoritmo de correlacion cruzada bidimensional.Mostramos resultados de un primer abordaje de la captura de imagenes y procesamiento de un campo fisico de velocidades en tiempo real.

Design of a dedicated processor for AC motor control implemented in a low cost FPGA

DEFF Research Database (Denmark)

Jakobsen, Uffe; Matzen, Torben N.

2008-01-01

of drives. Furthermore the softcore processor is designed with a system for plug in of external logic. Doing so shortens development time, since functionality is simply added to or removed from the softcore. The designer can then choose between resource usage on the FPGA and execution speed in more degrees....... The approach is tested for two different motor types, synchronousand hybrid switched reluctance motors, using a Spartan 3E FPGA. The impact of having ADC-communication in VHDL versus in assembler is also presented....

FPGA implementation of self organizing map with digital phase locked loops.

Science.gov (United States)

Hikawa, Hiroomi

2005-01-01

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.

Cavity enhanced eigenmode multiplexing for volume holographic data storage

Science.gov (United States)

Miller, Bo E.; Takashima, Yuzuru

2017-08-01

Previously, we proposed and experimentally demonstrated enhanced recording speeds by using a resonant optical cavity to semi-passively increase the reference beam power while recording image bearing holograms. In addition to enhancing the reference beam power the cavity supports the orthogonal reference beam families of its eigenmodes, which can be used as a degree of freedom to multiplex data pages and increase storage densities for volume Holographic Data Storage Systems (HDSS). While keeping the increased recording speed of a cavity enhanced reference arm, image bearing holograms are multiplexed by orthogonal phase code multiplexing via Hermite-Gaussian eigenmodes in a Fe:LiNbO3 medium with a 532 nm laser at two Bragg angles for expedited recording of four multiplexed holograms. We experimentally confirmed write rates are enhanced by an average factor of 1.1, and page crosstalk is about 2.5%. This hybrid multiplexing opens up a pathway to increase storage density while minimizing modifications to current angular multiplexing HDSS.

Signal compression in radar using FPGA

OpenAIRE

Enrique Escamilla Hemández; Víctor Kravchenko; Volodymyr Ponomaryov; Gonzalo Duchen Sánchez; David Hernández Sánchez

2010-01-01

El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array). El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR). El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde n...

Re-Form: FPGA-Powered True Codesign Flow for High-Performance Computing In The Post-Moore Era

Energy Technology Data Exchange (ETDEWEB)

Cappello, Franck; Yoshii, Kazutomo; Finkel, Hal; Cong, Jason

2016-11-14

Multicore scaling will end soon because of practical power limits. Dark silicon is becoming a major issue even more than the end of Moore’s law. In the post-Moore era, the energy efficiency of computing will be a major concern. FPGAs could be a key to maximizing the energy efficiency. In this paper we address severe challenges in the adoption of FPGA in HPC and describe “Re-form,” an FPGA-powered codesign flow.

Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

DEFF Research Database (Denmark)

Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

2012-01-01

Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...

An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC

Directory of Open Access Journals (Sweden)

Bo Peng

2016-01-01

Full Text Available As a modified-gravity proposal to handle the dark matter problem on galactic scales, Modified Newtonian Dynamics (MOND has shown a great success. However, the N-body MOND simulation is quite challenged by its computation complexity, which appeals to acceleration of the simulation calculation. In this paper, we present a highly integrated accelerating solution for N-body MOND simulations. By using the FPGA-SoC, which integrates both FPGA and SoC (system on chip in one chip, our solution exhibits potentials for better performance, higher integration, and lower power consumption. To handle the calculation bottleneck of potential summation, on one hand, we develop a strategy to simplify the pipeline, in which the square calculation task is conducted by the DSP48E1 of Xilinx 7 series FPGAs, so as to reduce the logic resource utilization of each pipeline; on the other hand, advantages of particle-mesh scheme are taken to overcome the bottleneck on bandwidth. Our experiment results show that 2 more pipelines can be integrated in Zynq-7020 FPGA-SoC with the simplified pipeline, and the bandwidth requirement is reduced significantly. Furthermore, our accelerating solution has a full range of advantages over different processors. Compared with GPU, our work is about 10 times better in performance per watt and 50% better in performance per cost.

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

Directory of Open Access Journals (Sweden)

Ramu Seva

2017-11-01

Full Text Available The high performance of FPGA (Field Programmable Gate Array in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

CERN Document Server

Pozniak, Krzysztof T

2004-01-01

The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

A New FPGA Architecture of FAST and BRIEF Algorithm for On-Board Corner Detection and Matching

Directory of Open Access Journals (Sweden)

Jingjin Huang

2018-03-01

Full Text Available Although some researchers have proposed the Field Programmable Gate Array (FPGA architectures of Feature From Accelerated Segment Test (FAST and Binary Robust Independent Elementary Features (BRIEF algorithm, there is no consideration of image data storage in these traditional architectures that will result in no image data that can be reused by the follow-up algorithms. This paper proposes a new FPGA architecture that considers the reuse of sub-image data. In the proposed architecture, a remainder-based method is firstly designed for reading the sub-image, a FAST detector and a BRIEF descriptor are combined for corner detection and matching. Six pairs of satellite images with different textures, which are located in the Mentougou district, Beijing, China, are used to evaluate the performance of the proposed architecture. The Modelsim simulation results found that: (i the proposed architecture is effective for sub-image reading from DDR3 at a minimum cost; (ii the FPGA implementation is corrected and efficient for corner detection and matching, such as the average value of matching rate of natural areas and artificial areas are approximately 67% and 83%, respectively, which are close to PC’s and the processing speed by FPGA is approximately 31 and 2.5 times faster than those by PC processing and by GPU processing, respectively.

A Correctness Verification Technique for Commercial FPGA Synthesis Tools

International Nuclear Information System (INIS)

Kim, Eui Sub; Yoo, Jun Beom; Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo

2014-01-01

Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

A Correctness Verification Technique for Commercial FPGA Synthesis Tools

Energy Technology Data Exchange (ETDEWEB)

Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2014-10-15

Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-06-01

Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

FPGA based mixed-signal circuit novel testing techniques

International Nuclear Information System (INIS)

Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

2013-01-01

Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

DEFF Research Database (Denmark)

Singh, Ritu; Kalia, Kartik; Minver, M. H.

2016-01-01

Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile...

GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

International Nuclear Information System (INIS)

Mitra, Jubin; Khan, Shuaib A.; Nayak, Tapan K.; Marin, Manoel Barros; Baron, Sophie; Kluge, Alex; Cachemiche, Jean-Pierre; Hachon, Frédéric; Rethore, Frédéric; David, Erno; Kiss, Tivadar

2016-01-01

The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA

UNIX veida mikrokodola operētājsistēma FPGA procesoram

OpenAIRE

Liepkalns, Ansis

2012-01-01

Risinājumos, kuros izmanto programmējamo loģisko mezglu masīvu (FPGA) procesorus, programmatūras pieejamība ir svarīga, lai samazinātu galaprodukta iegūšanai nepieciešamo laiku. Plašu programmatūras atbalstu ir ieguvušas UNIX veida operētājsistēmas. To kombinācija ar FPGA procesoriem spēj nodrošināt vēlamo izstrādes ātrumu. Lai apmierinātu kvalitātes prasības, tiek piedāvāts izmantot mikrokodola operētājsistēmu. Darbā tiek apskatīta sistēmas mikroshēmā izveide darbībai ar „Minix 3“ mikrokodol...

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Directory of Open Access Journals (Sweden)

Y. H. Lee

2016-01-01

Full Text Available Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration

DEFF Research Database (Denmark)

Cardarilli, Gian Carlo; Di Carlo, Leonardo; Nannarelli, Alberto

2016-01-01

Hardware acceleration is often used to address the need for speed and computing power in embedded systems. FPGAs always represented a good solution for HW acceleration and, recently, new SoC platforms extended the flexibility of the FPGAs by combining on a single chip both high-performance CPUs...... and FPGA fabric. The aim of this work is the implementation of hardware accelerators for these new SoCs. The innovative feature of these accelerators is the on-the-fly reconfiguration of the hardware to dynamically adapt the accelerator’s functionalities to the current CPU workload. The realization...... of the accelerators preliminarily requires also the profiling of both the SW (ARM CPU + NEON Units) and HW (FPGA) performance, an evaluation of the partial reconfiguration times and the development of an applicationspecific IP-cores library. This paper focuses on the profiling aspect of both the SW and HW...

Comparing an FPGA to a Cell for an Image Processing Application

Science.gov (United States)

Rakvic, Ryan N.; Ngo, Hau; Broussard, Randy P.; Ives, Robert W.

2010-12-01

Modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs), have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. On the other hand, PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high performance. In this research project, our aim is to study the differences in performance of a modern image processing algorithm on these two hardware platforms. In particular, Iris Recognition Systems have recently become an attractive identification method because of their extremely high accuracy. Iris matching, a repeatedly executed portion of a modern iris recognition algorithm, is parallelized on an FPGA system and a Cell processor. We demonstrate a 2.5 times speedup of the parallelized algorithm on the FPGA system when compared to a Cell processor-based version.

Comparing an FPGA to a Cell for an Image Processing Application

Directory of Open Access Journals (Sweden)

Robert W. Ives

2010-01-01

Full Text Available Modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs, have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. On the other hand, PlayStation3 (PS3 game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high performance. In this research project, our aim is to study the differences in performance of a modern image processing algorithm on these two hardware platforms. In particular, Iris Recognition Systems have recently become an attractive identification method because of their extremely high accuracy. Iris matching, a repeatedly executed portion of a modern iris recognition algorithm, is parallelized on an FPGA system and a Cell processor. We demonstrate a 2.5 times speedup of the parallelized algorithm on the FPGA system when compared to a Cell processor-based version.

Helicity multiplexed broadband metasurface holograms.

Science.gov (United States)

Wen, Dandan; Yue, Fuyong; Li, Guixin; Zheng, Guoxing; Chan, Kinlong; Chen, Shumei; Chen, Ming; Li, King Fai; Wong, Polis Wing Han; Cheah, Kok Wai; Pun, Edwin Yue Bun; Zhang, Shuang; Chen, Xianzhong

2015-09-10

Metasurfaces are engineered interfaces that contain a thin layer of plasmonic or dielectric nanostructures capable of manipulating light in a desirable manner. Advances in metasurfaces have led to various practical applications ranging from lensing to holography. Metasurface holograms that can be switched by the polarization state of incident light have been demonstrated for achieving polarization multiplexed functionalities. However, practical application of these devices has been limited by their capability for achieving high efficiency and high image quality. Here we experimentally demonstrate a helicity multiplexed metasurface hologram with high efficiency and good image fidelity over a broad range of frequencies. The metasurface hologram features the combination of two sets of hologram patterns operating with opposite incident helicities. Two symmetrically distributed off-axis images are interchangeable by controlling the helicity of the input light. The demonstrated helicity multiplexed metasurface hologram with its high performance opens avenues for future applications with functionality switchable optical devices.

User Multiplexing in Relay Enhanced LTE-Advanced Networks

DEFF Research Database (Denmark)

Teyeb, Oumer Mohammed; Frederiksen, Frank; Redana, Simone

2010-01-01

is radio relaying. This uses relay nodes that act as surrogate base stations for mobile users whose radio links with the base stations are not experiencing good enough conditions. In the downlink, the data that is destined for the relayed users may first have to be multiplexed by the base station, sent...... over the wireless backhaul link towards the relay node, and de-multiplexed and forwarded to the individual users by the relay node. The reverse process also has to be undertaken in the uplink. In this paper, we present a novel multiplexing scheme which is able to adapt the addressing and bitmapping...... of user identification to the actual number of users being served by the relay nodes, and thus greatly reduce the multiplexing overhead....

Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

National Research Council Canada - National Science Library

Nixon, Patrick

2002-01-01

This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA

Directory of Open Access Journals (Sweden)

Beau Tippetts

2014-01-01

Full Text Available A variety of platforms, such as micro-unmanned vehicles, are limited in the amount of computational hardware they can support due to weight and power constraints. An efficient stereo vision algorithm implemented on an FPGA would be able to minimize payload and power consumption in microunmanned vehicles, while providing 3D information and still leaving computational resources available for other processing tasks. This work presents a hardware design of the efficient profile shape matching stereo vision algorithm. Hardware resource usage is presented for the targeted micro-UV platform, Helio-copter, that uses the Xilinx Virtex 4 FX60 FPGA. Less than a fifth of the resources on this FGPA were used to produce dense disparity maps for image sizes up to 450 × 375, with the ability to scale up easily by increasing BRAM usage. A comparison is given of accuracy, speed performance, and resource usage of a census transform-based stereo vision FPGA implementation by Jin et al. Results show that the profile shape matching algorithm is an efficient real-time stereo vision algorithm for hardware implementation for resource limited systems such as microunmanned vehicles.

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments.

Science.gov (United States)

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J; Madison, Kirk W

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

Development of An Embedded FPGA-Based Data Acquisition System Dedicated to Zero Power Reactor Noise Experiments

Directory of Open Access Journals (Sweden)

Arkani Mohammad

2014-08-01

Full Text Available An embedded time interval data acquisition system (DAS is developed for zero power reactor (ZPR noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA. The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments

Science.gov (United States)

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J.; Madison, Kirk W.

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

Multiple routes transmitted epidemics on multiplex networks

International Nuclear Information System (INIS)

Zhao, Dawei; Li, Lixiang; Peng, Haipeng; Luo, Qun; Yang, Yixian

2014-01-01

This letter investigates the multiple routes transmitted epidemic process on multiplex networks. We propose detailed theoretical analysis that allows us to accurately calculate the epidemic threshold and outbreak size. It is found that the epidemic can spread across the multiplex network even if all the network layers are well below their respective epidemic thresholds. Strong positive degree–degree correlation of nodes in multiplex network could lead to a much lower epidemic threshold and a relatively smaller outbreak size. However, the average similarity of neighbors from different layers of nodes has no obvious effect on the epidemic threshold and outbreak size. -- Highlights: •We studies multiple routes transmitted epidemic process on multiplex networks. •SIR model and bond percolation theory are used to analyze the epidemic processes. •We derive equations to accurately calculate the epidemic threshold and outbreak size. •ASN has no effect on the epidemic threshold and outbreak size. •Strong positive DDC leads to a lower epidemic threshold and a smaller outbreak size.

Multiple routes transmitted epidemics on multiplex networks

Energy Technology Data Exchange (ETDEWEB)

Zhao, Dawei [Information Security Center, State Key Laboratory of Networking and Switching Technology, Beijing University of Posts and Telecommunications, P.O. Box 145, Beijing 100876 (China); National Engineering Laboratory for Disaster Backup and Recovery, Beijing University of Posts and Telecommunications, Beijing 100876 (China); Shandong Provincial Key Laboratory of Computer Network, Shandong Computer Science Center, Jinan 250014 (China); Li, Lixiang [Information Security Center, State Key Laboratory of Networking and Switching Technology, Beijing University of Posts and Telecommunications, P.O. Box 145, Beijing 100876 (China); National Engineering Laboratory for Disaster Backup and Recovery, Beijing University of Posts and Telecommunications, Beijing 100876 (China); Peng, Haipeng, E-mail: penghaipeng@bupt.edu.cn [Information Security Center, State Key Laboratory of Networking and Switching Technology, Beijing University of Posts and Telecommunications, P.O. Box 145, Beijing 100876 (China); National Engineering Laboratory for Disaster Backup and Recovery, Beijing University of Posts and Telecommunications, Beijing 100876 (China); Luo, Qun; Yang, Yixian [Information Security Center, State Key Laboratory of Networking and Switching Technology, Beijing University of Posts and Telecommunications, P.O. Box 145, Beijing 100876 (China); National Engineering Laboratory for Disaster Backup and Recovery, Beijing University of Posts and Telecommunications, Beijing 100876 (China)

2014-02-01

This letter investigates the multiple routes transmitted epidemic process on multiplex networks. We propose detailed theoretical analysis that allows us to accurately calculate the epidemic threshold and outbreak size. It is found that the epidemic can spread across the multiplex network even if all the network layers are well below their respective epidemic thresholds. Strong positive degree–degree correlation of nodes in multiplex network could lead to a much lower epidemic threshold and a relatively smaller outbreak size. However, the average similarity of neighbors from different layers of nodes has no obvious effect on the epidemic threshold and outbreak size. -- Highlights: •We studies multiple routes transmitted epidemic process on multiplex networks. •SIR model and bond percolation theory are used to analyze the epidemic processes. •We derive equations to accurately calculate the epidemic threshold and outbreak size. •ASN has no effect on the epidemic threshold and outbreak size. •Strong positive DDC leads to a lower epidemic threshold and a smaller outbreak size.

An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots

Directory of Open Access Journals (Sweden)

Jones Y. Mori

2012-01-01

Full Text Available This work presents the development of an integrated hardware/software sensor system for moving object detection and distance calculation, based on background subtraction algorithm. The sensor comprises a catadioptric system composed by a camera and a convex mirror that reflects the environment to the camera from all directions, obtaining a panoramic view. The sensor is used as an omnidirectional vision system, allowing for localization and navigation tasks of mobile robots. Several image processing operations such as filtering, segmentation and morphology have been included in the processing architecture. For achieving distance measurement, an algorithm to determine the center of mass of a detected object was implemented. The overall architecture has been mapped onto a commercial low-cost FPGA device, using a hardware/software co-design approach, which comprises a Nios II embedded microprocessor and specific image processing blocks, which have been implemented in hardware. The background subtraction algorithm was also used to calibrate the system, allowing for accurate results. Synthesis results show that the system can achieve a throughput of 26.6 processed frames per second and the performance analysis pointed out that the overall architecture achieves a speedup factor of 13.78 in comparison with a PC-based solution running on the real-time operating system xPC Target.

Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement

Science.gov (United States)

Pałka, M.; Strzempek, P.; Korcyl, G.; Bednarski, T.; Niedźwiecki, Sz.; Białas, P.; Czerwiński, E.; Dulski, K.; Gajos, A.; Głowacz, B.; Gorgol, M.; Jasińska, B.; Kamińska, D.; Kajetanowicz, M.; Kowalski, P.; Kozik, T.; Krzemień, W.; Kubicz, E.; Mohhamed, M.; Raczyński, L.; Rudy, Z.; Rundel, O.; Salabura, P.; Sharma, N. G.; Silarski, M.; Smyrski, J.; Strzelecki, A.; Wieczorek, A.; Wiślicki, W.; Zieliński, M.; Zgardzińska, B.; Moskal, P.

2017-08-01

In this article it is presented an FPGA based Multi-Voltage Threshold (MVT) system which allows of sampling fast signals (1-2 ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of 20 ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10%. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of σ(TOF) ≈ 68 ps is by factor of two better with respect to the current TOF-PET systems.

Design of time interval generator based on hybrid counting method

International Nuclear Information System (INIS)

Yao, Yuan; Wang, Zhaoqi; Lu, Houbing; Chen, Lian; Jin, Ge

2016-01-01

Time Interval Generators (TIGs) are frequently used for the characterizations or timing operations of instruments in particle physics experiments. Though some “off-the-shelf” TIGs can be employed, the necessity of a custom test system or control system makes the TIGs, being implemented in a programmable device desirable. Nowadays, the feasibility of using Field Programmable Gate Arrays (FPGAs) to implement particle physics instrumentation has been validated in the design of Time-to-Digital Converters (TDCs) for precise time measurement. The FPGA-TDC technique is based on the architectures of Tapped Delay Line (TDL), whose delay cells are down to few tens of picosecond. In this case, FPGA-based TIGs with high delay step are preferable allowing the implementation of customized particle physics instrumentations and other utilities on the same FPGA device. A hybrid counting method for designing TIGs with both high resolution and wide range is presented in this paper. The combination of two different counting methods realizing an integratable TIG is described in detail. A specially designed multiplexer for tap selection is emphatically introduced. The special structure of the multiplexer is devised for minimizing the different additional delays caused by the unpredictable routings from different taps to the output. A Kintex-7 FPGA is used for the hybrid counting-based implementation of a TIG, providing a resolution up to 11 ps and an interval range up to 8 s.

Design of time interval generator based on hybrid counting method

Energy Technology Data Exchange (ETDEWEB)

Yao, Yuan [State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, Anhui 230026 (China); Institute of Plasma Physics, Chinese Academy of Sciences, Hefei 230031 (China); Wang, Zhaoqi [State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, Anhui 230026 (China); Lu, Houbing [State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, Anhui 230026 (China); Hefei Electronic Engineering Institute, Hefei 230037 (China); Chen, Lian [State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, Anhui 230026 (China); Jin, Ge, E-mail: goldjin@ustc.edu.cn [State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, Anhui 230026 (China)

2016-10-01

Time Interval Generators (TIGs) are frequently used for the characterizations or timing operations of instruments in particle physics experiments. Though some “off-the-shelf” TIGs can be employed, the necessity of a custom test system or control system makes the TIGs, being implemented in a programmable device desirable. Nowadays, the feasibility of using Field Programmable Gate Arrays (FPGAs) to implement particle physics instrumentation has been validated in the design of Time-to-Digital Converters (TDCs) for precise time measurement. The FPGA-TDC technique is based on the architectures of Tapped Delay Line (TDL), whose delay cells are down to few tens of picosecond. In this case, FPGA-based TIGs with high delay step are preferable allowing the implementation of customized particle physics instrumentations and other utilities on the same FPGA device. A hybrid counting method for designing TIGs with both high resolution and wide range is presented in this paper. The combination of two different counting methods realizing an integratable TIG is described in detail. A specially designed multiplexer for tap selection is emphatically introduced. The special structure of the multiplexer is devised for minimizing the different additional delays caused by the unpredictable routings from different taps to the output. A Kintex-7 FPGA is used for the hybrid counting-based implementation of a TIG, providing a resolution up to 11 ps and an interval range up to 8 s.

FPGA platform for MEMS Disc Resonance Gyroscope (DRG) control

Science.gov (United States)

Keymeulen, Didier; Peay, Chris; Foor, David; Trung, Tran; Bakhshi, Alireza; Withington, Phil; Yee, Karl; Terrile, Rich

2008-04-01

Inertial navigation systems based upon optical gyroscopes tend to be expensive, large, power consumptive, and are not long lived. Micro-Electromechanical Systems (MEMS) based gyros do not have these shortcomings; however, until recently, the performance of MEMS based gyros had been below navigation grade. Boeing and JPL have been cooperating since 1997 to develop high performance MEMS gyroscopes for miniature, low power space Inertial Reference Unit applications. The efforts resulted in demonstration of a Post Resonator Gyroscope (PRG). This experience led to the more compact Disc Resonator Gyroscope (DRG) for further reduced size and power with potentially increased performance. Currently, the mass, volume and power of the DRG are dominated by the size of the electronics. This paper will detail the FPGA based digital electronics architecture and its implementation for the DRG which will allow reduction of size and power and will increase performance through a reduction in electronics noise. Using the digital control based on FPGA, we can program and modify in real-time the control loop to adapt to the specificity of each particular gyro and the change of the mechanical characteristic of the gyro during its life time.

FPGA-based architecture for motion recovering in real-time

Science.gov (United States)

Arias-Estrada, Miguel; Maya-Rueda, Selene E.; Torres-Huitzil, Cesar

2002-03-01

A key problem in the computer vision field is the measurement of object motion in a scene. The main goal is to compute an approximation of the 3D motion from the analysis of an image sequence. Once computed, this information can be used as a basis to reach higher level goals in different applications. Motion estimation algorithms pose a significant computational load for the sequential processors limiting its use in practical applications. In this work we propose a hardware architecture for motion estimation in real time based on FPGA technology. The technique used for motion estimation is Optical Flow due to its accuracy, and the density of velocity estimation, however other techniques are being explored. The architecture is composed of parallel modules working in a pipeline scheme to reach high throughput rates near gigaflops. The modules are organized in a regular structure to provide a high degree of flexibility to cover different applications. Some results will be presented and the real-time performance will be discussed and analyzed. The architecture is prototyped in an FPGA board with a Virtex device interfaced to a digital imager.

Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

Czech Academy of Sciences Publication Activity Database

Pohl, Zdeněk; Tichý, Milan; Kadlec, Jiří

2008-01-01

Roč. 2008, č. 2008 (2008), s. 1-11 ISSN 1687-6172 R&D Projects: GA MŠk(CZ) 1M0567 EU Projects: European Commission(XE) 027611 - AETHER Program:FP6 Institutional research plan: CEZ:AV0Z10750506 Keywords : DSP * Least-squares lattice * order estimation * exponential forgetting factor estimation * FPGA implementation * scheduling * dynamic reconfiguration * microblaze Subject RIV: IN - Informatics, Computer Science Impact factor: 1.055, year: 2008 http://library.utia.cas.cz/separaty/2008/ZS/pohl-tichy-kadlec-implementation%20of%20the%20least-squares%20lattice%20with%20order%20and%20forgetting%20factor%20estimation%20for%20fpga.pdf

Radiation tolerance and mitigation strategies for FPGA:s in the ATLAS TileCal Demonstrator

CERN Document Server

Akerstedt, H; The ATLAS collaboration

2013-01-01

During 2014, demonstrator electronics will be installed in a Tile calorimeter "drawer" to get long term experience with the inherently redundant electronics proposed for a full upgrade scheduled for 2022. The new system, being FPGA-based, uses dense programmable logic which must be proven to be sufficently radiation tolerant. It must be protected against radiation induced single event upsets that corrupt memory and logic functions. Radiation induced errors need to be found and compensated for in time, to minimize data loss but also to avoid permanent damage. Strategies for detecting and correcting radiation induced errors in the Kintex-7 FPGA:s of the demonstrator are evaluated and discussed.

Multiplex Biosensing Based on Highly Sensitive Magnetic Nanolabel Quantification: Rapid Detection of Botulinum Neurotoxins A, B, and E in Liquids.

Science.gov (United States)

Orlov, Alexey V; Znoyko, Sergey L; Cherkasov, Vladimir R; Nikitin, Maxim P; Nikitin, Petr I

2016-11-01

We present a multiplex quantitative lateral flow (LF) assay for simultaneous on-site detection of botulinum neurotoxin (BoNT) types A, B, and E in complex matrixes, which is innovative by virtually no sacrifice in performance while transition from the single-plex assays and by characteristics on the level of laboratory quantitative methods. The novel approach to easy multiplexing is realized via joining an on-demand set of single-plex LF strips, which employ magnetic nanolabels, into a miniature cylinder cartridge that mimics LF strip during all assay stages. The cartridge is read out by an original portable multichannel reader based on the magnetic particle quantification technique. The developed reader offers the unmatched 60 zmol detection limit and 7-order linear dynamic range for volumetric registration of magnetic labels inside a cartridge of several millimeters in diameter regardless of its optical transparency. Each of the test strips, developed here as building blocks for the multiplex assay, can be used "as is" for autonomous quantitative single-plex detection with the same measuring setup, exhibiting the limits of detection (LOD) of 0.22, 0.11, and 0.32 ng/mL for BoNT-A, -B, and -E, respectively. The proposed multiplex assay has demonstrated the remarkably similar LOD values of 0.20, 0.12, 0.35 ng/mL under the same conditions. The multiplex assay performance was successfully validated by BoNT detection in milk and apple and orange juices. The developed methods can be extended to other proteins and used for rapid multianalyte tests for point-of-care in vitro diagnostics, food analysis, biosafety and environmental monitoring, forensics, and security, etc.

Superconducting cavity driving with FPGA controller

International Nuclear Information System (INIS)

Czarski, Tomasz; Koprek, Waldemar; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

2006-01-01

A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

Directory of Open Access Journals (Sweden)

E.A. Ramadan

2014-09-01

Full Text Available This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions.

Bridging FPGA and GPU technologies for AO real-time control

Science.gov (United States)

Perret, Denis; Lainé, Maxime; Bernard, Julien; Gratadour, Damien; Sevin, Arnaud

2016-07-01

Our team has developed a common environment for high performance simulations and real-time control of AO systems based on the use of Graphics Processors Units in the context of the COMPASS project. Such a solution, based on the ability of the real time core in the simulation to provide adequate computing performance, limits the cost of developing AO RTC systems and makes them more scalable. A code developed and validated in the context of the simulation may be injected directly into the system and tested on sky. Furthermore, the use of relatively low cost components also offers significant advantages for the system hardware platform. However, the use of GPUs in an AO loop comes with drawbacks: the traditional way of offloading computation from CPU to GPUs - involving multiple copies and unacceptable overhead in kernel launching - is not well suited in a real time context. This last application requires the implementation of a solution enabling direct memory access (DMA) to the GPU memory from a third party device, bypassing the operating system. This allows this device to communicate directly with the real-time core of the simulation feeding it with the WFS camera pixel stream. We show that DMA between a custom FPGA-based frame-grabber and a computation unit (GPU, FPGA, or Coprocessor such as Xeon-phi) across PCIe allows us to get latencies compatible with what will be needed on ELTs. As a fine-grained synchronization mechanism is not yet made available by GPU vendors, we propose the use of memory polling to avoid interrupts handling and involvement of a CPU. Network and Vision protocols are handled by the FPGA-based Network Interface Card (NIC). We present the results we obtained on a complete AO loop using camera and deformable mirror simulators.

A novel integrated renewable energy system modelling approach, allowing fast FPGA controller prototyping

DEFF Research Database (Denmark)

Teodorescu, Remus; Ruiz, Alberto Parera; Cirstea, Marcian

2008-01-01

The paper describes a new holistic approach to the modeling of integrated renewable energy systems. The method is using the DK5 modeling/design environment from Celoxica and is based on the new Handel-C programming language. The goal of the work carried out was to achieve a combined model...... containing a Xilinx Spartan II FPGA and was successfully experimentally tested. This approach enables the design and fast hardware implementation of efficient controllers for Distributed Energy Resource (DER) hybrid systems....... of a photovoltaic energy system and a wind power system, which would allow an optimized holistic digital control system design, followed by rapid prototyping of the controller into a single Field Programmable Gate Array (FPGA). Initially, the system was simulated using Matlab / Simulink, to create a reference...

Miniaturized high-temperature superconducting multiplexer with cascaded quadruplet structure

Science.gov (United States)

Xu, Zhang; Jingping, Liu; Shaolin, Yan; Lan, Fang; Bo, Zhang; Xinjie, Zhao

2015-06-01

In this paper, compact high temperature superconducting (HTS) multiplexers are presented for satellite communication applications. The first multiplexer consists of an input coupling node and three high-order bandpass filters, which is named triplexer. The node is realized by a loop microstrip line instead of conventional T-junction to eliminate the redundant susceptance due to combination of three filters. There are two eight-pole band-pass filters and one ten-pole band-pass filter with cascaded quadruplet structure for realizing high isolation. Moreover, the triplexer is extended to a multiplexer with six channels so as to verify the expansibility of the suggested approach. The triplexer is fabricated using double-sided YBa2Cu3O7 thin films on a 38 × 25 mm2 LaAlO3 substrate. The experimental results, when compared with those ones from the T-junction multiplexer, show that our multiplexer has lower insertion loss, smaller sizes and higher isolation between any two channels. Also, good agreement has been achieved between simulations and measurements, which illustrate the effectiveness of our methods for the design of high performance HTS multiplexers.

Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System

Directory of Open Access Journals (Sweden)

Oliver TimothyF

2007-01-01

Full Text Available A method of constructing prerouted FPGA cores, which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing systems, is presented. Two major challenges are considered: how to manage the wires crossing a core's borders; and how to maintain an acceptable level of flexibility for system construction with only a minimum of overhead. In order to maintain FPGA computing performance, it is crucial to thoroughly analyze the issues at the lowest level of device detail in order to ensure that computing circuit encapsulation is as efficient as possible. We present the first methodology that allows a core to scale its interface bandwidth to the maximum available in a routing channel. Cores can be constructed independently from the rest of the system using a framework that is independent of the method used to place and route primitive components within the core. We use an abstract FPGA model and CAD tools that mirror those used in industry. An academic design flow has been modified to include a wire policy and an interface constraints framework that tightly constrains the use of the wires that cross a core's boundaries. Using this tool set we investigate the effect of prerouting on overall system optimality. Abutting cores are instantly connected by colocation of interface wires. Eliminating run-time routing drastically reduces the time taken to construct a system using a set of cores.

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

Energy Technology Data Exchange (ETDEWEB)

Cardinali, M., E-mail: cardinal@kph.uni-mainz.de [Institut für Kernphysik, Johannes Gutenberg-University Mainz, Mainz (Germany); Helmholtz Institut Mainz, Mainz (Germany); Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt (Germany); Dodokhov, V.Kh. [Joint Institute for Nuclear Research, Dubna (Russian Federation); Britting, A. [Friedrich Alexander-University of Erlangen-Nuremberg, Erlangen (Germany); and others

2014-12-01

The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R and D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype. - Highlights: • Frontend electronics for Cherenkov detectors have been developed. • FPGA-TDCs have been used for high precision timing. • Time over threshold has been utilised for walk correction. • Single photo-electron timing resolution less than 100 ps has been achieved.

Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

DEFF Research Database (Denmark)

Saini, Rishita; Bansal, Neha; Bansal, Meenakshi

2015-01-01

Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient...

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

Science.gov (United States)

2008-07-01

Cruickshank, J. E. Gaffney and R. D. Melbourne, Australia : ACM, 1992. Proceedings of the 14th International Conference on Software Engineering. pp. 327-337... Ridge Compiler Collection Stone Ridge Technology 48 A.3 FPGA Architecture Survey Company Niche 3P plus 1 Technology Coarse-grain configurable IP

FPGA-based real time implementation of MPPT-controller for photovoltaic systems

Energy Technology Data Exchange (ETDEWEB)

Mellit, A.; Rezzouk, H.; Medjahed, B. [Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200 Djelfa (Algeria)

2011-05-15

In this paper an FPGA-based implementation of a real time perturb and observe (P and O) algorithm for tracking the Maximum Power Point (MPP) of a photovoltaic (PV) generator is presented. The P and O algorithm has been designed using the very high-speed description language (VHDL) and implemented on Xilinx Virtex-II-Pro(xc2v1000-4fg456) - Field Programmable Gate Array (FPGA). The algorithm and the hardware have been simulated and tested by conditioning the power produced by the PV-modules installed on the rooftop of the ''Hall of Technology Laboratory'' at Jijel University. The main advantages of the developed MPPT are low cost, good velocity, acceptable reliability, and easy implementation. However, its main disadvantage is related to the fact that for fast changes in irradiance it may fail to track the maximum power point. The efficiency of the implemented P and O controller is about 96%. (author)

Study on Method of Ultrasonic Gas Temperature Measure Based on FPGA

Energy Technology Data Exchange (ETDEWEB)

Wen, S H; Xu, F R [Institute of Electrical Engineering, Yanshan University, Qinhuangdao, 066004 (China)

2006-10-15

It is always a problem to measure instantaneous temperature of high-temperature and high-pressure gas. There is difficulty for the conventional method of measuring temperature to measure quickly and exactly, and the measuring precision is low, the ability of anti-jamming is bad, etc. So the article introduces a method of measuring burning gas temperature using ultrasonic based on Field-Programmable Gate Array (FPGA). The mathematic model of measuring temperature is built with the relation of velocity of ultrasonic transmitting and gas Kelvin in the ideal gas. The temperature can be figured out by measuring the difference of ultrasonic frequency {delta}f. FPGA is introduced and a high-precision data acquisition system based on digital phase-shift technology is designed. The feasibility of proposed above is confirmed more by measuring pressure of burning gas timely. Experimental result demonstrates that the error is less than 12.. and the precision is heightened to 0.8%.

ALICE high-level trigger readout and FPGA processing in Run 2

Energy Technology Data Exchange (ETDEWEB)

Engel, Heiko; Kebschull, Udo [IRI, Goethe-Universitaet Frankfurt (Germany); Collaboration: ALICE-Collaboration

2016-07-01

The ALICE experiment uses the optical Detector Data Link (DDL) protocol to connect the detectors to the computing clusters of Data Acquisition (DAQ) and High-Level Trigger (HLT). The interfaces between the clusters and the optical links are realized with FPGA boards. HLT has replaced all of its interface boards with the Common Read-Out Receiver Card (C-RORC) for Run 2. This enables the read-out of detectors at higher link rates and allows to extend the data pre-processing capabilities, like online cluster finding, already in the FPGA. The C-RORC is integrated transparently into the existing HLT data transport framework and the cluster monitoring and management infrastructure. The board is in use since the start of LHC Run 2 and all ALICE data from and to HLT as well as all data from the TPC and the TRD is handled by C-RORCs. This contribution gives an overview on the firmware and software status of the C-RORC in the HLT.

An FPGA Implementation of Secured Steganography Communication System

Directory of Open Access Journals (Sweden)

Ahlam Fadhil Mahmood

2013-04-01

Full Text Available     Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.        In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.      This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secures data transmission applications

An FPGA Implementation of Secured Steganography Communication System

Directory of Open Access Journals (Sweden)

Ahlam Mahmood

2014-04-01

Full Text Available Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.  In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.  This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secure data transmission applications

Interlaboratory study of DNA extraction from multiple ground samples, multiplex real-time PCR, and multiplex qualitative PCR for individual kernel detection system of genetically modified maize.

Science.gov (United States)

Akiyama, Hiroshi; Sakata, Kozue; Makiyma, Daiki; Nakamura, Kosuke; Teshima, Reiko; Nakashima, Akie; Ogawa, Asako; Yamagishi, Toru; Futo, Satoshi; Oguchi, Taichi; Mano, Junichi; Kitta, Kazumi

2011-01-01

In many countries, the labeling of grains, feed, and foodstuff is mandatory if the genetically modified (GM) organism content exceeds a certain level of approved GM varieties. We previously developed an individual kernel detection system consisting of grinding individual kernels, DNA extraction from the individually ground kernels, GM detection using multiplex real-time PCR, and GM event detection using multiplex qualitative PCR to analyze the precise commingling level and varieties of GM maize in real sample grains. We performed the interlaboratory study of the DNA extraction with multiple ground samples, multiplex real-time PCR detection, and multiplex qualitative PCR detection to evaluate its applicability, practicality, and ruggedness for the individual kernel detection system of GM maize. DNA extraction with multiple ground samples, multiplex real-time PCR, and multiplex qualitative PCR were evaluated by five laboratories in Japan, and all results from these laboratories were consistent with the expected results in terms of the commingling level and event analysis. Thus, the DNA extraction with multiple ground samples, multiplex real-time PCR, and multiplex qualitative PCR for the individual kernel detection system is applicable and practicable in a laboratory to regulate the commingling level of GM maize grain for GM samples, including stacked GM maize.

SQUID readout multiplexers for transition-edge sensor arrays

Energy Technology Data Exchange (ETDEWEB)

Lee, Adrian T. [Physics Department, University of California, Berkeley, CA 94720 (United States) and Physics Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)]. E-mail: atl@physics.berkeley.edu

2006-04-15

Two classes of SQUID multiplexer are being developed for large arrays of cryogenic sensors, distinguished by their operation in either the time domain or frequency domain. Several systems optimized for use with Transition-Edge Sensors (TES) are reaching a high level of maturity, and will be deployed on funded astrophysics experiments in the next several years. A useful technical figure of merit is the product of the number of detectors multplexed multipled by the bandwidth of the detectors, which can be termed the 'total signal bandwidth' of a multiplexer system. This figure of merit is comparable within a factor of two for the mature systems. Several new concepts for increasing the total bandwidth are being developed in the broad class of frequency domain multiplexers. Another notable area of progress is in the level of integration of muliplexer and detector array. The time domain system for SCUBA-II is a sophisticated bump-bonded sandwich structure, and the Jena/MPI group is integrating detectors and a time domain multiplexer on one substrate. Finally, the Kinetic Inductance Detectors (KID)/HEMT (non-SQUID) detector/multiplexer system, will be discussed briefly.

Using of FPGA coprocessor for improving the execution speed of the pattern recognition algorithm for ATLAS - high energy physics experiment

CERN Document Server

Hinkelbein, C; Kugel, A; Männer, R; Miiller, M

2004-01-01

Pattern recognition algorithms are used in experimental High Energy physics for getting parameters (features) of particles tracks in detectors. It is particularly important to have fast algorithms in trigger system. This paper investigates the suitability of using FPGA coprocessor for speedup of the TRT-LUT algorithm - one of the feature extraction algorithms for second level trigger for ATLAS experiment (CERN). Two realization of the same algorithm have been compared: C++ realization tested on a computer equipped with dual Xeon 2.4 GHz CPU, 64-bit, 66MHz PCI bus, 1024Mb DDR RAM main memories with Red Hat Linux 7.1 and hybrid C++ - VHDL realisation tested on same PC equipped in addition by MPRACE board (FPGA-Coprocessor board based on Xilinx Virtex-II FPGA and made as 64-bit, 66 MHz PCI card developed at the University of Mannheim). Usage of the FPGA coprocessor can give some reasonable speedup in contrast to general purpose processor only for those algorithms (or parts of algorithms), for which there is a po...

Design of area array CCD image acquisition and display system based on FPGA

Science.gov (United States)

Li, Lei; Zhang, Ning; Li, Tianting; Pan, Yue; Dai, Yuming

2014-09-01

With the development of science and technology, CCD(Charge-coupled Device) has been widely applied in various fields and plays an important role in the modern sensing system, therefore researching a real-time image acquisition and display plan based on CCD device has great significance. This paper introduces an image data acquisition and display system of area array CCD based on FPGA. Several key technical challenges and problems of the system have also been analyzed and followed solutions put forward .The FPGA works as the core processing unit in the system that controls the integral time sequence .The ICX285AL area array CCD image sensor produced by SONY Corporation has been used in the system. The FPGA works to complete the driver of the area array CCD, then analog front end (AFE) processes the signal of the CCD image, including amplification, filtering, noise elimination, CDS correlation double sampling, etc. AD9945 produced by ADI Corporation to convert analog signal to digital signal. Developed Camera Link high-speed data transmission circuit, and completed the PC-end software design of the image acquisition, and realized the real-time display of images. The result through practical testing indicates that the system in the image acquisition and control is stable and reliable, and the indicators meet the actual project requirements.

A fast improved fat tree encoder for wave union TDC in an FPGA

International Nuclear Information System (INIS)

Shen Qi; Zhao Lei; Liu Shubin; Qi Binxiang; Hu Xueye; An Qi; Liao Shengkai; Peng Chengzhi

2013-01-01

Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs. (authors)

Multiplexing schemes for an achromatic programmable diffractive lens

Energy Technology Data Exchange (ETDEWEB)

Millan, M S; Perez-Cabre, E; Oton, J [Technical University of Catalonia, Dep. Optics and Optometry, Terrassa-Barcelona, 08222 (Spain)], E-mail: millan@oo.upc.edu

2008-11-01

A multiplexed programmable diffractive lens, displayed on a pixelated liquid crystal device under broadband illumination, is proposed to compensate for the severe chromatic aberration that affects diffractive elements. The proposed lens is based on multiplexing a set of sublenses with a common focal length for different wavelengths. We consider different types of integration of the optical information (spatial only, temporal only and hybrid spatial-temporal) combined with a proper selection of the spectral bandwidth. The properties and limits of the achromatic programmable multiplexed lens are described. Experimental results are presented and discussed.

Multiplexing schemes for an achromatic programmable diffractive lens

International Nuclear Information System (INIS)

Millan, M S; Perez-Cabre, E; Oton, J

2008-01-01

A multiplexed programmable diffractive lens, displayed on a pixelated liquid crystal device under broadband illumination, is proposed to compensate for the severe chromatic aberration that affects diffractive elements. The proposed lens is based on multiplexing a set of sublenses with a common focal length for different wavelengths. We consider different types of integration of the optical information (spatial only, temporal only and hybrid spatial-temporal) combined with a proper selection of the spectral bandwidth. The properties and limits of the achromatic programmable multiplexed lens are described. Experimental results are presented and discussed.

VHDL resolved function based inner communication bus for FPGA

Science.gov (United States)

Pozniak, Krzysztof T.

2017-08-01

This article discusses a method of building an internal, universal and parametric bus. The solution was designed for a variety of FPGA families and popular VHDL compilers. The algorithm of automatic configuration of address space and methods of receiving and sending addressed data are discussed. The basic solution realized in VHDL language in a behavioral form and chosen examples of practical use of the internal bus are presented in detail.

Eigenmode multiplexing with SLM for volume holographic data storage

Science.gov (United States)

Chen, Guanghao; Miller, Bo E.; Takashima, Yuzuru

2017-08-01

The cavity supports the orthogonal reference beam families as its eigenmodes while enhancing the reference beam power. Such orthogonal eigenmodes are used as additional degree of freedom to multiplex data pages, consequently increase storage densities for volume Holographic Data Storage Systems (HDSS) when the maximum number of multiplexed data page is limited by geometrical factor. Image bearing holograms are multiplexed by orthogonal phase code multiplexing via Hermite-Gaussian eigenmodes in a Fe:LiNbO3 medium with a 532 nm laser at multiple Bragg angles by using Liquid Crystal on Silicon (LCOS) spatial light modulators (SLMs) in reference arms. Total of nine holograms are recorded with three angular and three eigenmode.

Trinary Encoder, Decoder, Multiplexer and Demultiplexer Using Savart Plate and Spatial Light Modulator

Science.gov (United States)

Ghosh, Amal K.; Singha Roy, Souradip; Mandal, Sudipta; Basuray, Amitabha

Optoelectronic processors have already been developed with the strong potentiality of optics in information and data processing. Encoder, Decoder, Multiplexers and Demultiplexers are the most important components in modern system designs and in communications. We have implemented the same using trinary logic gates with signed magnitude defined as Modified Trinary Number (MTN). The Spatial Light Modulator (SLM) based optoelectronic circuit is suitable for high speed data processing and communications using photon as carrier. We also presented here a possible method of implementing the same using light with photon as carrier of information. The importance of the method is that all the basic gates needed may be fabricated based on basic building block.

Reconfigurable Parallel Computer Architectures for Space Applications

Science.gov (United States)

2012-08-07

63 B-1. Dependency diagram of the hardware blocks implemented with VHDL .................. 64 C-1. The...distribution is unlimited. The CU has been fully implemented in a FPGA using VHDL . The CU hardware design is depicted in Figure 12. It consists of a main...the hardware design implemented in the FPGA using VHDL . The block diagram shows the dependency of all the VHDL blocks included in the design. Each

FPGA-based fully digital fast power switch fault detection and compensation for three-phase shunt active filters

Energy Technology Data Exchange (ETDEWEB)

Karimi, S.; Saadate, S. [Groupe de Recherche en Electrotechnique et Electronique de Nancy, GREEN-UHP, CNRS UMR 7037 (France); Poure, P. [Laboratoire d' Instrumentation Electronique de Nancy, LIEN, EA 3440, France Nancy Universite - Universite Henri Poincare de Nancy I, BP 239, 54506 Vandoeuvre les Nancy cedex (France)

2008-11-15

This paper discusses the design, implementation, experimental validation and performances of a fully digital fast power switch fault detection and compensation for three-phase shunt active power filters. The approach introduced in this paper minimizes the time interval between the fault occurrence and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 {mu}s by using simultaneously a ''time criterion'' and a ''voltage criterion''. In order to attain this fast detection time a FPGA (Field Programmable Gate Array) is used. The other feature introduced in this approach is that the control scheme used to compensate the current load harmonics and fault tolerant scheme are both programmed in only one FPGA. ''FPGA in the loop'' prototyping results and fully experimental results based on a real active power filter verify satisfactory performances of the proposed method. (author)

Design and development of FPGA based TCP/IP module for real time computers in nuclear power plants

International Nuclear Information System (INIS)

Balasri, G. Janani; Santhana Raj, A.; Gour, Aditya; Murali, N.; Manikandan, J.

2013-01-01

An VME (Virtual Module Europa) bus based Real Time Computer's (RTC's) are being developed for Prototype Fast Breeder Reactor (PFBR) which is in an advanced stage of construction at Kalpakkam, where the RTC's have to communicate to the central process computer on the data collected from the field instrument and receive data from the central process computer. A Distributed Digital Control System (DDSC) architecture has been designed for this communication which is based on Transfer Communication Protocol/Internet Protocol (TCP/IP) over Ethernet. Currently the RTC's uses 'Wiznet Module', a bought out chip which implements the TCP/IP stack in hardware. This project concentrates on the design and development of Field Programmable Gate Array (FPGA) based TCP/IP module that runs on Microblaze, a 32-bit softcore processor, to take care of the communication as that of Wiznet module. Advantage of switching over to FPGA based system are its reconfigurability, desired number of sockets, and the design is stable even if the FPGA's get obsolete. (author)

Artificial Neural Network as the FPGA Trigger in the Cyclone V based Front-End for a Detection of Neutrino-Origin Showers

Energy Technology Data Exchange (ETDEWEB)

Szadkowski, Zbigniew; Glas, Dariusz [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149 (Poland); Pytel, Krzysztof [University of Lodz, Department of Physics and Applied Informatics, Faculty of Informatics, 90-236 Lodz (Poland)

2015-07-01

Neutrinos play a fundamental role in the understanding of the origin of ultra-high-energy cosmic rays. They interact through charged and neutral currents in the atmosphere generating extensive air showers. However, their a very low rate of events potentially generated by neutrinos is a significant challenge for a detection technique and requires both sophisticated algorithms and high-resolution hardware. A trigger based on a artificial neural network was implemented into the Cyclone{sup R} V E FPGA 5CEFA9F31I7 - the heart of the prototype Front-End boards developed for tests of new algorithms in the Pierre Auger surface detectors. Showers for muon and tau neutrino initiating particles on various altitudes, angles and energies were simulated in CORSICA and Offline platforms giving pattern of ADC traces in Auger water Cherenkov detectors. The 3-layer 12-8-1 neural network was taught in MATLAB by simulated ADC traces according the Levenberg-Marquardt algorithm. Results show that a probability of a ADC traces generation is very low due to a small neutrino cross-section. Nevertheless, ADC traces, if occur, for 1-10 EeV showers are relatively short and can be analyzed by 16-point input algorithm. We optimized the coefficients from MATLAB to get a maximal range of potentially registered events and for fixed-point FPGA processing to minimize calculation errors. New sophisticated triggers implemented in Cyclone{sup R} V E FPGAs with large amount of DSP blocks, embedded memory running with 120 - 160 MHz sampling may support a discovery of neutrino events in the Pierre Auger Observatory. (authors)

A low power flash-FPGA based brain implant micro-system of PID control.

Science.gov (United States)

Lijuan Xia; Fattah, Nabeel; Soltan, Ahmed; Jackson, Andrew; Chester, Graeme; Degenaar, Patrick

2017-07-01

In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Das, Bhagwan; Kaur, Amanpreet

2017-01-01

that will energy efficient as well as faster than traditional design. Three different FPGA and SOC are taken under consideration and our design is implemented on these four ICs and we find the most energy efficient architecture and also find the architecture that will deliver highest performance among these four...... FPGA then we conclude that Zynq 7000 All programmable SOC is power hungry architecture and Kintex ultrascale architecture is the most energy efficient architecture that dissipates 20.86% less power than Zynq 700 All programmable SOC. For performance evaluation, we have taken benchmark C code of FIR...... provide by Xilinx. We transform that C code into HDL using Vivado HLS 2016.2 before power analysis on Vivado 2016.2. Ultrascale FPGA is generally used for packet processing in 100G networking and heterogeneous wireless infrastructure....

The FPGA realization of the general cellular automata based cryptographic hash functions: Performance and effectiveness

Directory of Open Access Journals (Sweden)

P. G. Klyucharev

2014-01-01

Full Text Available In the paper the author considers hardware implementation of the GRACE-H family general cellular automata based cryptographic hash functions. VHDL is used as a language and Altera FPGA as a platform for hardware implementation. Performance and effectiveness of the FPGA implementations of GRACE-H hash functions were compared with Keccak (SHA-3, SHA-256, BLAKE, Groestl, JH, Skein hash functions. According to the performed tests, performance of the hardware implementation of GRACE-H family hash functions significantly (up to 12 times exceeded performance of the hardware implementation of previously known hash functions, and effectiveness of that hardware implementation was also better (up to 4 times.

Social contagions on correlated multiplex networks

Science.gov (United States)

Wang, Wei; Cai, Meng; Zheng, Muhua

2018-06-01

The existence of interlayer degree correlations has been disclosed by abundant multiplex network analysis. However, how they impose on the dynamics of social contagions are remain largely unknown. In this paper, we propose a non-Markovian social contagion model in multiplex networks with inter-layer degree correlations to delineate the behavior spreading, and develop an edge-based compartmental (EBC) theory to describe the model. We find that multiplex networks promote the final behavior adoption size. Remarkably, it can be observed that the growth pattern of the final behavior adoption size, versus the behavioral information transmission probability, changes from discontinuous to continuous once decreasing the behavior adoption threshold in one layer. We finally unravel that the inter-layer degree correlations play a role on the final behavior adoption size but have no effects on the growth pattern, which is coincidence with our prediction by using the suggested theory.

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Science.gov (United States)

Asaad, Sameh W.; Kapur, Mohit

2016-03-15

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Evaluation of multiplex ligation-dependent probe amplification analysis versus multiplex polymerase chain reaction assays in the detection of dystrophin gene rearrangements in an Iranian population subset

Directory of Open Access Journals (Sweden)

Nayereh Nouri

2014-01-01

Full Text Available Background: The Duchenne muscular dystrophy (DMD gene is located in the short arm of the X chromosome (Xp21. It spans 2.4 Mb of the human genomic DNA and is composed of 79 exons. Mutations in the Dystrophin gene result in DMD and Becker muscular dystrophy. In this study, the efficiency of multiplex ligation-dependent probe amplification (MLPA over multiplex polymerase chain reaction (PCR assays in an Iranian population was investigated. Materials and Methods: Multiplex PCR assays and MLPA analysis were carried out in 74 patients affected with DMD. Results: Multiplex PCR detected deletions in 51% of the patients with DMD. MLPA analysis could determine all the deletions detected by the multiplex PCR. Additionally, MLPA was able to identify one more deletion and duplication in patients without detectable mutations by multiplex PCR. Moreover, MLPA precisely determined the exact size of the deletions. Conclusion: Although MLPA analysis is more sensitive for detection of deletions and duplications in the dystrophin gene, multiplex PCR might be used for the initial analysis of the boys affected with DMD in the Iranian population as it was able to detect 95% of the rearrangements in patients with DMD.

Moving through a multiplex holographic scene

Science.gov (United States)

Mrongovius, Martina

2013-02-01

This paper explores how movement can be used as a compositional element in installations of multiplex holograms. My holographic images are created from montages of hand-held video and photo-sequences. These spatially dynamic compositions are visually complex but anchored to landmarks and hints of the capturing process - such as the appearance of the photographer's shadow - to establish a sense of connection to the holographic scene. Moving around in front of the hologram, the viewer animates the holographic scene. A perception of motion then results from the viewer's bodily awareness of physical motion and the visual reading of dynamics within the scene or movement of perspective through a virtual suggestion of space. By linking and transforming the physical motion of the viewer with the visual animation, the viewer's bodily awareness - including proprioception, balance and orientation - play into the holographic composition. How multiplex holography can be a tool for exploring coupled, cross-referenced and transformed perceptions of movement is demonstrated with a number of holographic image installations. Through this process I expanded my creative composition practice to consider how dynamic and spatial scenes can be conveyed through the fragmented view of a multiplex hologram. This body of work was developed through an installation art practice and was the basis of my recently completed doctoral thesis: 'The Emergent Holographic Scene — compositions of movement and affect using multiplex holographic images'.

Embedded active vision system based on an FPGA architecture

OpenAIRE

Chalimbaud , Pierre; Berry , François

2006-01-01

International audience; In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision) is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks,...

Radiometric and signal-to-noise ratio properties of multiplex dispersive spectrometry

International Nuclear Information System (INIS)

Barducci, Alessandro; Guzzi, Donatella; Lastri, Cinzia; Nardino, Vanni; Marcoionni, Paolo; Pippi, Ivan

2010-01-01

Recent theoretical investigations have shown important radiometric disadvantages of interferential multiplexing in Fourier transform spectrometry that apparently can be applied even to coded aperture spectrometers. We have reexamined the methods of noninterferential multiplexing in order to assess their signal-to-noise ratio (SNR) performance, relying on a theoretical modeling of the multiplexed signals. We are able to show that quite similar SNR and radiometric disadvantages affect multiplex dispersive spectrometry. The effect of noise on spectral estimations is discussed.

An FPGA based control unit for synchronization of laser Thomson scattering measurements to plasma events on MAST

International Nuclear Information System (INIS)

Naylor, G.A.

2010-01-01

The power and flexibility of modern Field Programmable Gate Arrays (FPGAs) is now being recognised in many areas of instrumentation and control . The high performance of modern ADCs and the high throughput of FPGAs allow the emulation of many specialised analogue instruments. The functions of heterodyne detection, phase measurements, spectrum analyzers, phase sensitive detectors, counters, etc. can be achieved in relatively simple hardware using an FPGA. The complex filtering functions can be efficiently performed digitally in the FPGA, without recourse to a separate DSP chip. This paper describes the use of a custom off the shelf FPGA board with a collection of custom interface boards to produce a powerful custom trigger system. This has been developed for agile triggering of YAG lasers on MAST. This unit allows various analogue inputs including magnetics data to be processed in real-time and allow Thomson scattering data to be collected at accurate times with respect to randomly occurring MHD phenomena such as neoclassical tearing modes (NTMs). The FPGA allows a 'System On a Chip' architecture in order to perform fast filtering in logic coupled to a dedicated soft processor for real-time fixed latency operations and a second soft processor to handle external communications with the control system for system configuration and reporting of status/archived data. The use of such a generic structure in order to provide a common approach, with reduced software development times, for diverse diagnostic situations will be discussed.

FPGA-Based HD Camera System for the Micropositioning of Biomedical Micro-Objects Using a Contactless Micro-Conveyor

Directory of Open Access Journals (Sweden)

Elmar Yusifli

2017-03-01

Full Text Available With recent advancements, micro-object contactless conveyers are becoming an essential part of the biomedical sector. They help avoid any infection and damage that can occur due to external contact. In this context, a smart micro-conveyor is devised. It is a Field Programmable Gate Array (FPGA-based system that employs a smart surface for conveyance along with an OmniVision complementary metal-oxide-semiconductor (CMOS HD camera for micro-object position detection and tracking. A specific FPGA-based hardware design and VHSIC (Very High Speed Integrated Circuit Hardware Description Language (VHDL implementation are realized. It is done without employing any Nios processor or System on a Programmable Chip (SOPC builder based Central Processing Unit (CPU core. It keeps the system efficient in terms of resource utilization and power consumption. The micro-object positioning status is captured with an embedded FPGA-based camera driver and it is communicated to the Image Processing, Decision Making and Command (IPDC module. The IPDC is programmed in C++ and can run on a Personal Computer (PC or on any appropriate embedded system. The IPDC decisions are sent back to the FPGA, which pilots the smart surface accordingly. In this way, an automated closed-loop system is employed to convey the micro-object towards a desired location. The devised system architecture and implementation principle is described. Its functionality is also verified. Results have confirmed the proper functionality of the developed system, along with its outperformance compared to other solutions.

Topology-optimized silicon photonic wire mode (de)multiplexer

DEFF Research Database (Denmark)

Frellsen, Louise Floor; Frandsen, Lars Hagedorn; Ding, Yunhong

2015-01-01

We have designed and for the first time experimentally verified a topology optimized mode (de)multiplexer, which demultiplexes the fundamental and the first order mode of a double mode photonic wire to two separate single mode waveguides (and multiplexes vice versa). The device has a footprint...