A chiral-based magnetic memory device without a permanent magnet.

Science.gov (United States)

Ben Dor, Oren; Yochelis, Shira; Mathew, Shinto P; Naaman, Ron; Paltiel, Yossi

2013-01-01

Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices.

Electric-field-controlled interface dipole modulation for Si-based memory devices.

Science.gov (United States)

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

Science.gov (United States)

Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

2017-12-01

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

Fast, Capacious Disk Memory Device

Science.gov (United States)

Muller, Ronald M.

1990-01-01

Device for recording digital data on, and playing back data from, memory disks has high recording or playback rate and utilizes available recording area more fully. Two disks, each with own reading/writing head, used to record data at same time. Head on disk A operates on one of tracks numbered from outside in; head on disk B operates on track of same number in sequence from inside out. Underlying concept of device applicable to magnetic or optical disks.

A stacked memory device on logic 3D technology for ultra-high-density data storage

International Nuclear Information System (INIS)

Kim, Jiyoung; Hong, Augustin J; Kim, Sung Min; Shin, Kyeong-Sik; Song, Emil B; Hwang, Yongha; Xiu, Faxian; Galatsis, Kosmas; Chui, Chi On; Candler, Rob N; Wang, Kang L; Choi, Siyoung; Moon, Joo-Tae

2011-01-01

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

A stacked memory device on logic 3D technology for ultra-high-density data storage

Energy Technology Data Exchange (ETDEWEB)

Kim, Jiyoung; Hong, Augustin J; Kim, Sung Min; Shin, Kyeong-Sik; Song, Emil B; Hwang, Yongha; Xiu, Faxian; Galatsis, Kosmas; Chui, Chi On; Candler, Rob N; Wang, Kang L [Device Research Laboratory, Department of Electrical Engineering, University of California, Los Angeles, CA 90095 (United States); Choi, Siyoung; Moon, Joo-Tae, E-mail: hbt100@ee.ucla.edu [Advanced Technology Development Team and Process Development Team, Memory R and D Center, Samsung Electronics Co. Ltd (Korea, Republic of)

2011-06-24

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

Bulk heterojunction polymer memory devices with reduced graphene oxide as electrodes.

Science.gov (United States)

Liu, Juqing; Yin, Zongyou; Cao, Xiehong; Zhao, Fei; Lin, Anping; Xie, Linghai; Fan, Quli; Boey, Freddy; Zhang, Hua; Huang, Wei

2010-07-27

A unique device structure with a configuration of reduced graphene oxide (rGO) /P3HT:PCBM/Al has been designed for the polymer nonvolatile memory device. The current-voltage (I-V) characteristics of the fabricated device showed the electrical bistability with a write-once-read-many-times (WORM) memory effect. The memory device exhibits a high ON/OFF ratio (10(4)-10(5)) and low switching threshold voltage (0.5-1.2 V), which are dependent on the sheet resistance of rGO electrode. Our experimental results confirm that the carrier transport mechanisms in the OFF and ON states are dominated by the thermionic emission current and ohmic current, respectively. The polarization of PCBM domains and the localized internal electrical field formed among the adjacent domains are proposed to explain the electrical transition of the memory device.

Characterizations of MoTiO5 flash memory devices with post-annealing

International Nuclear Information System (INIS)

Kao, Chyuan Haur; Chen, Hsiang; Chen, Su Zhien; Chen, Yu Jie; Chu, Yu Cheng

2014-01-01

In this study, high-K MoTiO 5 dielectrics were applied as charge trapping layers in fabricated metal-oxide-high-K MoTiO 5 -oxide-Si-type memory devices. Among the applied MoTiO 5 trapping layer treatment conditions, annealing at 900 °C yielded devices that exhibited superior memory performance, such as a larger memory window and faster programming/erasing speed. Multiple material analyses, namely X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy, confirmed that annealing at 900 °C can improve the material quality as a result of crystallization. The fabricated MoTiO 5 -based memory devices show potential for future commercial memory device applications. - Highlights: • MoTiO5-based flash memories have been fabricated. • MoTiO5 trapping layers could be formed by co-sputtering. • MoTiO5 layers with annealing exhibited a good memory performance. • Multiple material analyses confirm that annealing enhanced crystallization

Demonstration of Ultra-Fast Switching in Nano metallic Resistive Switching Memory Devices

International Nuclear Information System (INIS)

Yang, Y.

2016-01-01

Interdependency of switching voltage and time creates a dilemma/obstacle for most resistive switching memories, which indicates low switching voltage and ultra-fast switching time cannot be simultaneously achieved. In this paper, an ultra-fast (sub-100 ns) yet low switching voltage resistive switching memory device (“nano metallic ReRAM”) was demonstrated. Experimental switching voltage is found independent of pulse width (intrinsic device property) when the pulse is long but shows abrupt time dependence (“cliff”) as pulse width approaches characteristic RC time of memory device (extrinsic device property). Both experiment and simulation show that the onset of cliff behavior is dependent on physical device size and parasitic resistance, which is expected to diminish as technology nodes shrink down. We believe this study provides solid evidence that nano metallic resistive switching memory can be reliably operated at low voltage and ultra-fast regime, thus beneficial to future memory technology.

Solution-processed flexible NiO resistive random access memory device

Science.gov (United States)

Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

2018-04-01

Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

Resistively heated shape memory polymer device

Energy Technology Data Exchange (ETDEWEB)

Marion, III, John E.; Bearinger, Jane P.; Wilson, Thomas S.; Maitland, Duncan J.

2017-09-05

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

Resistively heated shape memory polymer device

Energy Technology Data Exchange (ETDEWEB)

Marion, III, John E.; Bearinger, Jane P.; Wilson, Thomas S.; Maitland, Duncan J.

2016-10-25

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

A graphene integrated highly transparent resistive switching memory device

Science.gov (United States)

Dugu, Sita; Pavunny, Shojan P.; Limbu, Tej B.; Weiner, Brad R.; Morell, Gerardo; Katiyar, Ram S.

2018-05-01

We demonstrate the hybrid fabrication process of a graphene integrated highly transparent resistive random-access memory (TRRAM) device. The indium tin oxide (ITO)/Al2O3/graphene nonvolatile memory device possesses a high transmittance of >82% in the visible region (370-700 nm) and exhibits stable and non-symmetrical bipolar switching characteristics with considerably low set and reset voltages (ITO/Al2O3/Pt device and studied its switching characteristics for comparison and a better understanding of the ITO/Al2O3/graphene device characteristics. The conduction mechanisms in high and low resistance states were analyzed, and the observed polarity dependent resistive switching is explained based on electro-migration of oxygen ions.

Impacts of Co doping on ZnO transparent switching memory device characteristics

Energy Technology Data Exchange (ETDEWEB)

Simanjuntak, Firman Mangasa; Wei, Kung-Hwa [Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Prasad, Om Kumar [Department of Electrical Engineering and Computer Science, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Panda, Debashis [Department of Electronics Engineering, National Institute of Science and Technology, Berhampur, Odisha 761008 (India); Lin, Chun-An; Tsai, Tsung-Ling; Tseng, Tseung-Yuen, E-mail: tseng@cc.nctu.edu.tw [Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan (China)

2016-05-02

The resistive switching characteristics of indium tin oxide (ITO)/Zn{sub 1−x}Co{sub x}O/ITO transparent resistive memory devices were investigated. An appropriate amount of cobalt dopant in ZnO resistive layer demonstrated sufficient memory window and switching stability. In contrast, pure ZnO devices demonstrated a poor memory window, and using an excessive dopant concentration led to switching instability. To achieve suitable memory performance, relying only on controlling defect concentrations is insufficient; the grain growth orientation of the resistive layer must also be considered. Stable endurance with an ON/OFF ratio of more than one order of magnitude during 5000 cycles confirmed that the Co-doped ZnO device is a suitable candidate for resistive random access memory application. Additionally, fully transparent devices with a high transmittance of up to 90% at wavelength of 550 nm have been fabricated.

Organic nonvolatile memory devices with charge trapping multilayer graphene film

International Nuclear Information System (INIS)

Ji, Yongsung; Choe, Minhyeok; Cho, Byungjin; Song, Sunghoon; Yoon, Jongwon; Ko, Heung Cho; Lee, Takhee

2012-01-01

We fabricated an array-type organic nonvolatile memory device with multilayer graphene (MLG) film embedded in polyimide (PI) layers. The memory devices showed a high ON/OFF ratio (over 10 6 ) and a long retention time (over 10 4 s). The switching of the Al/PI/MLG/PI/Al memory devices was due to the presence of the MLG film inserted into the PI layers. The double-log current–voltage characteristics could be explained by the space-charge-limited current conduction based on a charge-trap model. A conductive atomic force microscopy found that the conduction paths in the low-resistance ON state were distributed in a highly localized area, which was associated with a carbon-rich filamentary switching mechanism. (paper)

Ferroelectric-gate field effect transistor memories device physics and applications

CERN Document Server

Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

2016-01-01

This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices

Directory of Open Access Journals (Sweden)

Fu-Chien Chiu

2013-01-01

Full Text Available Bipolar resistance switching characteristics are demonstrated in Pt/ZnO/Pt nonvolatile memory devices. A negative differential resistance or snapback characteristic can be observed when the memory device switches from a high resistance state to a low resistance state due to the formation of filamentary conducting path. The dependence of pulse width and temperature on set/reset voltages was examined in this work. The exponentially decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1 s. Hence, to switch the ZnO memory devices, a minimum set/reset voltage is required. The set voltage decreases linearly with the temperature whereas the reset voltage is nearly temperature-independent. In addition, the ac cycling endurance can be over 106 switching cycles, whereas, the dependence of HRS/LRS resistance distribution indicates that a significant memory window closure may take place after about 102  dc switching cycles.

Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

International Nuclear Information System (INIS)

Cho, Ikjun; Cho, Jinhan; Kim, Beom Joon; Cho, Jeong Ho; Ryu, Sook Won

2014-01-01

Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-Au NPs ) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-Au NP ) n films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO 2 gate dielectric layer. For a single Au NP layer (i.e. PAD/TOA-Au NP ) 1 ) with a number density of 1.82 × 10 12 cm −2 , the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four Au NP layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔV th ) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 10 6 ) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate. (paper)

Three-terminal resistive switching memory in a transparent vertical-configuration device

International Nuclear Information System (INIS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies

Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure

International Nuclear Information System (INIS)

Kim, Tae-Wook; Choi, Hyejung; Oh, Seung-Hwan; Jo, Minseok; Wang, Gunuk; Cho, Byungjin; Kim, Dong-Yu; Hwang, Hyunsang; Lee, Takhee

2009-01-01

The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 μm 2 to 200 x 200 nm 2 . From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I ON /I OFF ∼10 4 ), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10 000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

Metal-free, single-polymer device exhibits resistive memory effect

KAUST Repository

Bhansali, Unnat Sampatraj; Khan, Yasser; Cha, Dong Kyu; Almadhoun, Mahmoud N.; Li, Ruipeng; Chen, Long; Amassian, Aram; Odeh, Ihab N.; Alshareef, Husam N.

2013-01-01

All-polymer, write-once-read-many times resistive memory devices have been fabricated on flexible substrates using a single polymer, poly(3,4- ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS). Spin-cast or inkjet-printed films of solvent-modified PEDOT:PSS are used as electrodes, while the unmodified or as-is PEDOT:PSS is used as the semiconducting active layer. The all-polymer devices exhibit an irreversible but stable transition from a low resistance state (ON) to a high resistance state (OFF) at low voltages caused by an electric-field-induced morphological rearrangement of PEDOT and PSS at the electrode interface. However, in the metal-PEDOT:PSS-metal devices, we have shown a metal filament formation switching the device from an initial high resistance state (OFF) to the low resistance state (ON). The all-PEDOT:PSS memory device has low write voltages (<3 V), high ON/OFF ratio (>10 3), good retention characteristics (>10 000 s), and stability in ambient storage (>3 months). © 2013 American Chemical Society.

Metal-free, single-polymer device exhibits resistive memory effect

KAUST Repository

Bhansali, Unnat Sampatraj

2013-12-23

All-polymer, write-once-read-many times resistive memory devices have been fabricated on flexible substrates using a single polymer, poly(3,4- ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS). Spin-cast or inkjet-printed films of solvent-modified PEDOT:PSS are used as electrodes, while the unmodified or as-is PEDOT:PSS is used as the semiconducting active layer. The all-polymer devices exhibit an irreversible but stable transition from a low resistance state (ON) to a high resistance state (OFF) at low voltages caused by an electric-field-induced morphological rearrangement of PEDOT and PSS at the electrode interface. However, in the metal-PEDOT:PSS-metal devices, we have shown a metal filament formation switching the device from an initial high resistance state (OFF) to the low resistance state (ON). The all-PEDOT:PSS memory device has low write voltages (<3 V), high ON/OFF ratio (>10 3), good retention characteristics (>10 000 s), and stability in ambient storage (>3 months). © 2013 American Chemical Society.

Terrestrial neutron-induced soft errors in advanced memory devices

CERN Document Server

Nakamura, Takashi; Ibe, Eishi; Yahagi, Yasuo; Kameyama, Hideaki

2008-01-01

Terrestrial neutron-induced soft errors in semiconductor memory devices are currently a major concern in reliability issues. Understanding the mechanism and quantifying soft-error rates are primarily crucial for the design and quality assurance of semiconductor memory devices. This book covers the relevant up-to-date topics in terrestrial neutron-induced soft errors, and aims to provide succinct knowledge on neutron-induced soft errors to the readers by presenting several valuable and unique features. Sample Chapter(s). Chapter 1: Introduction (238 KB). Table A.30 mentioned in Appendix A.6 on

Memory-assisted measurement-device-independent quantum key distribution

Science.gov (United States)

Panayi, Christiana; Razavi, Mohsen; Ma, Xiongfeng; Lütkenhaus, Norbert

2014-04-01

A protocol with the potential of beating the existing distance records for conventional quantum key distribution (QKD) systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of measurement-device-independent QKD, which only requires optical source equipment at the user's end. For certain memories with short access times, our scheme allows a higher repetition rate than that of quantum repeaters with single-mode memories, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is potentially possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations.

Memory-assisted measurement-device-independent quantum key distribution

International Nuclear Information System (INIS)

Panayi, Christiana; Razavi, Mohsen; Ma, Xiongfeng; Lütkenhaus, Norbert

2014-01-01

A protocol with the potential of beating the existing distance records for conventional quantum key distribution (QKD) systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of measurement-device-independent QKD, which only requires optical source equipment at the user's end. For certain memories with short access times, our scheme allows a higher repetition rate than that of quantum repeaters with single-mode memories, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is potentially possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations. (paper)

Guide wire extension for shape memory polymer occlusion removal devices

Science.gov (United States)

Maitland, Duncan J [Pleasant Hill, CA; Small, IV, Ward; Hartman, Jonathan [Sacramento, CA

2009-11-03

A flexible extension for a shape memory polymer occlusion removal device. A shape memory polymer instrument is transported through a vessel via a catheter. A flexible elongated unit is operatively connected to the distal end of the shape memory polymer instrument to enhance maneuverability through tortuous paths en route to the occlusion.

Combating Memory Corruption Attacks On Scada Devices

Science.gov (United States)

Bellettini, Carlo; Rrushi, Julian

Memory corruption attacks on SCADA devices can cause significant disruptions to control systems and the industrial processes they operate. However, despite the presence of numerous memory corruption vulnerabilities, few, if any, techniques have been proposed for addressing the vulnerabilities or for combating memory corruption attacks. This paper describes a technique for defending against memory corruption attacks by enforcing logical boundaries between potentially hostile data and safe data in protected processes. The technique encrypts all input data using random keys; the encrypted data is stored in main memory and is decrypted according to the principle of least privilege just before it is processed by the CPU. The defensive technique affects the precision with which attackers can corrupt control data and pure data, protecting against code injection and arc injection attacks, and alleviating problems posed by the incomparability of mitigation techniques. An experimental evaluation involving the popular Modbus protocol demonstrates the feasibility and efficiency of the defensive technique.

Soluble dendrimers europium(III) β-diketonate complex for organic memory devices

International Nuclear Information System (INIS)

Wang Binbin; Fang Junfeng; Li Bin; You Han; Ma Dongge; Hong Ziruo; Li Wenlian; Su Zhongmin

2008-01-01

We report the synthesis of a soluble dendrimers europium(III) complex, tris(dibenzoylmethanato)(1,3,5-tris[2-(2'-pyridyl) benzimidazoly]methylbenzene)-europium(III), and its application in organic electrical bistable memory device. Excellent stability that ensured more than 10 6 write-read-erase-reread cycles has been performed in ambient conditions without current-induced degradation. High-density, low-cost memory, good film-firming property, fascinating thermal and morphological stability allow the application of the dendrimers europium(III) complex as an active medium in non-volatile memory devices

Memory operation devices based on light-illumination ambipolar carbon-nanotube thin-film-transistors

International Nuclear Information System (INIS)

Aïssa, B.; Nedil, M.; Kroeger, J.; Haddad, T.; Rosei, F.

2015-01-01

We report the memory operation behavior of a light illumination ambipolar single-walled carbon nanotube thin film field-effect transistors devices. In addition to the high electronic-performance, such an on/off transistor-switching ratio of 10 4 and an on-conductance of 18 μS, these memory devices have shown a high retention time of both hole and electron-trapping modes, reaching 2.8 × 10 4  s at room temperature. The memory characteristics confirm that light illumination and electrical field can act as an independent programming/erasing operation method. This could be a fundamental step toward achieving high performance and stable operating nanoelectronic memory devices

Hybrid superconducting-magnetic memory device using competing order parameters.

Science.gov (United States)

Baek, Burm; Rippard, William H; Benz, Samuel P; Russek, Stephen E; Dresselhaus, Paul D

2014-05-28

In a hybrid superconducting-magnetic device, two order parameters compete, with one type of order suppressing the other. Recent interest in ultra-low-power, high-density cryogenic memories has spurred new efforts to simultaneously exploit superconducting and magnetic properties so as to create novel switching elements having these two competing orders. Here we describe a reconfigurable two-layer magnetic spin valve integrated within a Josephson junction. Our measurements separate the suppression in the superconducting coupling due to the exchange field in the magnetic layers, which causes depairing of the supercurrent, from the suppression due to the stray magnetic field. The exchange field suppression of the superconducting order parameter is a tunable and switchable behaviour that is also scalable to nanometer device dimensions. These devices demonstrate non-volatile, size-independent switching of Josephson coupling, in magnitude as well as phase, and they may enable practical nanoscale superconducting memory devices.

A new DRAM-type memory devices based on polymethacrylate containing pendant 2-methylbenzothiazole

International Nuclear Information System (INIS)

Wang Dong; Li Hua; Li Najun; Zhao Ying; Zhou Qianhao; Xu Qingfeng; Lu Jianmei; Wang Lihua

2012-01-01

Graphical abstract: The devices fabricated with 75 nm and 45 nm thick pBVMA films were both found to exhibit DRAM type memory behaviors, which may indicate that the Al nanoparticles had no penetration into the thin film during the vacuum-deposition process. Highlights: ► The side-functional moieties of pBVMA regularly arranged in film state. ► The device exhibits volatile memory behavior with an ON/OFF current ratio up to 10 5 . ► The film thickness has nothing to do with the device's memory behavior. ► Physical theoretical models and molecular simulation supported the memory mechanism. - Abstract: A polymethacrylate containing pendant 2-methylbenzothiazole (pBVMA) with good thermal stability was synthesized by free radical polymerization. The devices based on pBVMA possess a sandwich structure comprising bottom indium-tin oxide (ITO) electrode and top Al electrode. The as-fabricated device exhibits the dynamic random access memory (DRAM) behavior with an ON/OFF current ratio up to 10 5 and can endure 10 8 read cycles under −1 V pulse voltage. The effect of the film thickness on the device performance was investigated and the devices fabricated with 75 nm and 45 nm thick pBVMA films were both found to exhibit DRAM type memory behaviors, which may indicate that the Al nanoparticles had no penetration into the thin film during the vacuum-deposition process. The molecular simulation and physical theoretical models were analyzed and the mechanism of the DRAM performance may be attributed to the weak electron withdrawing ability of the molecule.

Charge Carrier Transport Mechanism Based on Stable Low Voltage Organic Bistable Memory Device.

Science.gov (United States)

Ramana, V V; Moodley, M K; Kumar, A B V Kiran; Kannan, V

2015-05-01

A solution processed two terminal organic bistable memory device was fabricated utilizing films of polymethyl methacrylate PMMA/ZnO/PMMA on top of ITO coated glass. Electrical characterization of the device structure showed that the two terminal device exhibited favorable switching characteristics with an ON/OFF ratio greater than 1 x 10(4) when the voltage was swept between - 2 V and +3 V. The device maintained its state after removal of the bias voltage. The device did not show degradation after a 1-h retention test at 120 degrees C. The memory functionality was consistent even after fifty cycles of operation. The charge transport switching mechanism is discussed on the basis of carrier transport mechanism and our analysis of the data shows that the charge carrier trans- port mechanism of the device during the writing process can be explained by thermionic emission (TE) and space-charge-limited-current (SCLC) mechanism models while erasing process could be explained by the FN tunneling mechanism. This demonstration provides a class of memory devices with the potential for low-cost, low-power consumption applications, such as a digital memory cell.

Silicon nano crystal-based non-volatile memory devices

International Nuclear Information System (INIS)

Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

2006-01-01

In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

Discovering Authentication Credentials in Volatile Memory of Android Mobile Devices

OpenAIRE

Apostolopoulos , Dimitris; Marinakis , Giannis; Ntantogian , Christoforos; Xenakis , Christos

2013-01-01

Part 5: Adoption Issues in e/m-Services; International audience; This paper investigates whether authentication credentials in the volatile memory of Android mobile devices can be discovered using freely available tools. The experiments that we carried out for each application included two different sets: In the first set, our goal was to check if we could recover our own submitted credentials from the memory dump of the mobile device. In the second set of experiments, the goal was to find pa...

New memory devices based on the proton transfer process

Science.gov (United States)

Wierzbowska, Małgorzata

2016-01-01

Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices.

Memory operation devices based on light-illumination ambipolar carbon-nanotube thin-film-transistors

Energy Technology Data Exchange (ETDEWEB)

Aïssa, B., E-mail: aissab@emt.inrs.ca [Qatar Environment and Energy Research Institute (QEERI), Qatar Foundation, P.O. Box 5825, Doha (Qatar); Centre Energie, Matériaux et Télécommunications, INRS, 1650, Boulevard Lionel-Boulet Varennes, Quebec J3X 1S2 (Canada); Nedil, M. [Telebec Wireless Underground Communication Laboratory, UQAT, 675, 1ère Avenue, Val d' Or, Quebec J9P 1Y3 (Canada); Kroeger, J. [NanoIntegris & Raymor Nanotech, Raymor Industries Inc., 3765 La Vérendrye, Boisbriand, Quebec J7H 1R8 (Canada); Haddad, T. [Department of Mechanical Engineering, McGill University, Montreal, Quebec H3A 0B8 (Canada); Rosei, F. [Centre Energie, Matériaux et Télécommunications, INRS, 1650, Boulevard Lionel-Boulet Varennes, Quebec J3X 1S2 (Canada)

2015-09-28

We report the memory operation behavior of a light illumination ambipolar single-walled carbon nanotube thin film field-effect transistors devices. In addition to the high electronic-performance, such an on/off transistor-switching ratio of 10{sup 4} and an on-conductance of 18 μS, these memory devices have shown a high retention time of both hole and electron-trapping modes, reaching 2.8 × 10{sup 4} s at room temperature. The memory characteristics confirm that light illumination and electrical field can act as an independent programming/erasing operation method. This could be a fundamental step toward achieving high performance and stable operating nanoelectronic memory devices.

Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

KAUST Repository

Caraveo-Frescas, Jesus Alfonso; Khan, M. A.; Alshareef, Husam N.

2014-01-01

Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm 2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

KAUST Repository

Caraveo-Frescas, Jesus Alfonso

2014-06-10

Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm 2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

Light programmable organic transistor memory device based on hybrid dielectric

Science.gov (United States)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Configurable Resistive Switching between Memory and Threshold Characteristics for Protein-Based Devices

KAUST Repository

Wang, Hong

2015-05-01

The employ of natural biomaterials as the basic building blocks of electronic devices is of growing interest for biocompatible and green electronics. Here, resistive switching (RS) devices based on naturally silk protein with configurable functionality are demonstrated. The RS type of the devices can be effectively and exactly controlled by controlling the compliance current in the set process. Memory RS can be triggered by a higher compliance current, while threshold RS can be triggered by a lower compliance current. Furthermore, two types of memory devices, working in random access and WORM modes, can be achieved with the RS effect. The results suggest that silk protein possesses the potential for sustainable electronics and data storage. In addition, this finding would provide important guidelines for the performance optimization of biomaterials based memory devices and the study of the underlying mechanism behind the RS effect arising from biomaterials. Resistive switching (RS) devices with configurable functionality based on protein are successfully achieved. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

New memory devices based on the proton transfer process

International Nuclear Information System (INIS)

Wierzbowska, Małgorzata

2016-01-01

Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing  information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices. (paper)

Electronic memory devices based on the chalcone with negative electrostatic potential regions

International Nuclear Information System (INIS)

Yan, Bao-Long; Sun, Ru; Ge, Jian-Feng; Wang, Dong; Li, Hua; Lu, Jian-Mei

2013-01-01

The molecular electrostatic potential (ESP) properties were used for the explanation of organic electric memory ability. Several chalcone compounds, owning a negative ESP region locates at the oxygen atom, were selected in this paper to validate the selection of compounds for organic memory materials. The synthesis, characterization, fabrication of the organic memory devices and the electrical properties for them were reported, and they were shown as WORM (write once read many times) type memory devices. The molecular geometries were optimized by the addition of a changeable electric field in the x direction inside the molecules using FF-DFT (Finite Field-Density Functionary Theory) method. The relationship between ESP of the molecules under different electric field and the property was discussed, and the mechanisms associated with the memory effect were also elucidated from DFT calculation results. - Highlights: • The molecular electrostatic potential (ESP) properties were used. • The chalcone compounds were used for the WORM type device. • The molecular geometries were optimized by the addition of a changeable electric field in the x direction. • The structure–property relationship was discussed

A study on carbon nanotube bridge as a electromechanical memory device

Science.gov (United States)

Kang, Jeong Won; Ha Lee, Jun; Joo Lee, Hoong; Hwang, Ho Jung

2005-04-01

A nanoelectromechanical (NEM) nanotube random access memory (NRAM) device based on carbon nanotube (CNT) was investigated using atomistic simulations. For the CNT-based NEM memory, the mechanical properties of the CNT-bridge and van der Waals interactions between the CNT-bridge and substrate were very important. The critical amplitude of the CNT-bridge was 16% of the length of the CNT-bridge. As molecular dynamics time increased, the CNT-bridge went to the steady state under the electrostatic force with the damping of the potential and the kinetic energies of the CNT-bridge. The interatomic interaction between the CNT-bridge and substrate, value of the CNT-bridge slack, and damping rate of the CNT-bridge were very important for the operation of the NEM memory device as a nonvolatile memory.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Science.gov (United States)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Non-Hebbian learning implementation in light-controlled resistive memory devices.

Science.gov (United States)

Ungureanu, Mariana; Stoliar, Pablo; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E

2012-01-01

Non-Hebbian learning is often encountered in different bio-organisms. In these processes, the strength of a synapse connecting two neurons is controlled not only by the signals exchanged between the neurons, but also by an additional factor external to the synaptic structure. Here we show the implementation of non-Hebbian learning in a single solid-state resistive memory device. The output of our device is controlled not only by the applied voltages, but also by the illumination conditions under which it operates. We demonstrate that our metal/oxide/semiconductor device learns more efficiently at higher applied voltages but also when light, an external parameter, is present during the information writing steps. Conversely, memory erasing is more efficiently at higher applied voltages and in the dark. Translating neuronal activity into simple solid-state devices could provide a deeper understanding of complex brain processes and give insight into non-binary computing possibilities.

RFID and Memory Devices Fabricated Integrally on Substrates

Science.gov (United States)

Schramm, Harry F.

2004-01-01

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for

Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

International Nuclear Information System (INIS)

Avila-Nino, J.A.; Segura-Cardenas, E.; Sustaita, A.O.; Cruz-Cruz, I.; Lopez-Sandoval, R.; Reyes-Reyes, M.

2011-01-01

We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

Energy Technology Data Exchange (ETDEWEB)

Avila-Nino, J.A.; Segura-Cardenas, E. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Sustaita, A.O. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Cruz-Cruz, I. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Lopez-Sandoval, R. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Reyes-Reyes, M., E-mail: reyesm@iico.uaslp.mx [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico)

2011-03-25

We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS2 quantum dot-polymethylmethacrylate nanocomposites

International Nuclear Information System (INIS)

Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan; Kim, Sang Wook

2014-01-01

Nonvolatile memory devices based on CuInS 2 (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10 −10 was maintained for 8 × 10 3 cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10 6 cycles converged to 2.40 × 10 −10 , indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams

Nonvolatile rewritable memory device based on solution-processable graphene/poly(3-hexylthiophene) nanocomposite

Energy Technology Data Exchange (ETDEWEB)

Zhang, Li, E-mail: lizhang9@zzu.edu.cn [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China); Li, Ye; Shi, Jun [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China); Shi, Gaoquan [Department of Chemistry, Tsinghua University, Beijing 100084 (China); Cao, Shaokui, E-mail: Caoshaokui@zzu.edu.cn [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China)

2013-11-01

An electrically bistable device utilizing a nanocomposite of hexadecylamine-functionalized graphene oxide (HDAGO) with poly(3-hexylthiophene) (P3HT) is demonstrated. The device has an ITO/P3HT-HDAGO/Al sandwich structure, in which the composite film of P3HT-HDAGO was prepared by simple solution phase mixing of the exfoliated HDAGO monolayers with P3HT matrix and a spin-coating method. The memory device exhibits typical bistable electrical switching behavior and a nonvolatile rewritable memory effect, with a turn-on voltage of about 1.5 V and an ON/OFF-state current ratio of 10{sup 5}. Under ambient conditions, both the ON and OFF states are stable under a constant voltage stress or a continuous pulse voltage stress at a read voltage of 1 V. The conduction mechanism is deduced from the modeling of the nature of currents in both states, and the electrical switching behavior can be attributed to the electric-field-induced charge transfer between P3HT and HDAGO nanosheets. - Highlights: • Nonvolatile rewritable memory effect in P3HT–graphene composite is demonstrated. • The memory device was fabricated through a simple solution processing technique. • The device shows a remarkable electrical bistable behavior and excellent stability. • Memory mechanism is deduced from the modeling of the currents in both states.

Nonvolatile rewritable memory device based on solution-processable graphene/poly(3-hexylthiophene) nanocomposite

International Nuclear Information System (INIS)

Zhang, Li; Li, Ye; Shi, Jun; Shi, Gaoquan; Cao, Shaokui

2013-01-01

An electrically bistable device utilizing a nanocomposite of hexadecylamine-functionalized graphene oxide (HDAGO) with poly(3-hexylthiophene) (P3HT) is demonstrated. The device has an ITO/P3HT-HDAGO/Al sandwich structure, in which the composite film of P3HT-HDAGO was prepared by simple solution phase mixing of the exfoliated HDAGO monolayers with P3HT matrix and a spin-coating method. The memory device exhibits typical bistable electrical switching behavior and a nonvolatile rewritable memory effect, with a turn-on voltage of about 1.5 V and an ON/OFF-state current ratio of 10 5 . Under ambient conditions, both the ON and OFF states are stable under a constant voltage stress or a continuous pulse voltage stress at a read voltage of 1 V. The conduction mechanism is deduced from the modeling of the nature of currents in both states, and the electrical switching behavior can be attributed to the electric-field-induced charge transfer between P3HT and HDAGO nanosheets. - Highlights: • Nonvolatile rewritable memory effect in P3HT–graphene composite is demonstrated. • The memory device was fabricated through a simple solution processing technique. • The device shows a remarkable electrical bistable behavior and excellent stability. • Memory mechanism is deduced from the modeling of the currents in both states

Electrical studies of Ge4Sb1Te5 devices for memory applications

Science.gov (United States)

Sangeetha, B. G.; Shylashree, N.

2018-05-01

In this paper, the Ge4Sb1Te5 thin film device preparation and electrical studies for memory devices were carried out. The device was deposited using vapor-evaporation technique. RESET to SET state switching was shown using current-voltage characterization. The current-voltage characterization shows the switching between SET to RESET state and it was found that it requires a low energy for transition. Switching between amorphous to crystalline nature was studied using resistance-voltage characteristics. The endurance showed the effective use of this composition for memory device.

Atomic-layer deposited IrO2 nanodots for charge-trap flash-memory devices

International Nuclear Information System (INIS)

Choi, Sangmoo; Cha, Young-Kwan; Seo, Bum-Seok; Park, Sangjin; Park, Ju-Hee; Shin, Sangmin; Seol, Kwang Soo; Park, Jong-Bong; Jung, Young-Soo; Park, Youngsoo; Park, Yoondong; Yoo, In-Kyeong; Choi, Suk-Ho

2007-01-01

Charge-trap flash- (CTF) memory structures have been fabricated by employing IrO 2 nanodots (NDs) grown by atomic-layer deposition. A band of isolated IrO 2 NDs of about 3 nm lying almost parallel to Si/SiO 2 interface is confirmed by transmission electron microscopy and x-ray photoelectron spectroscopy. The memory device with IrO 2 NDs shows much larger capacitance-voltage (C-V) hysteresis and memory window compared with the control sample without IrO 2 NDs. After annealing at 800 deg. C for 20 min, the ND device shows almost no change in the width of C-V hysteresis and the ND distribution. These results indicate that the IrO 2 NDs embedded in SiO 2 can be utilized as thermally stable, discrete charge traps, promising for metal oxide-ND-based CTF memory devices

Application of nanomaterials in two-terminal resistive-switching memory devices

Directory of Open Access Journals (Sweden)

Jianyong Ouyang

2010-05-01

Full Text Available Nanometer materials have been attracting strong attention due to their interesting structure and properties. Many important practical applications have been demonstrated for nanometer materials based on their unique properties. This article provides a review on the fabrication, electrical characterization, and memory application of two-terminal resistive-switching devices using nanomaterials as the active components, including metal and semiconductor nanoparticles (NPs, nanotubes, nanowires, and graphenes. There are mainly two types of device architectures for the two-terminal devices with NPs. One has a triple-layer structure with a metal film sandwiched between two organic semiconductor layers, and the other has a single polymer film blended with NPs. These devices can be electrically switched between two states with significant different resistances, i.e. the ‘ON’ and ‘OFF’ states. These render the devices important application as two-terminal non-volatile memory devices. The electrical behavior of these devices can be affected by the materials in the active layer and the electrodes. Though the mechanism for the electrical switches has been in argument, it is generally believed that the resistive switches are related to charge storage on the NPs. Resistive switches were also observed on crossbars formed by nanotubes, nanowires, and graphene ribbons. The resistive switches are due to nanoelectromechanical behavior of the materials. The Coulombic interaction of transient charges on the nanomaterials affects the configurable gap of the crossbars, which results into significant change in current through the crossbars. These nanoelectromechanical devices can be used as fast-response and high-density memory devices as well. Dr. Jianyong Ouyang received his bachelor degree from the Tsinghua University in Beijing, China, and MSc from the Institute of Chemistry, Chinese Academy of Science. He received his PhD from the Institute for Molecular

Observation of long term potentiation in papain-based memory devices

KAUST Repository

Bag, A.; Hota, Mrinal Kanti; Mallik, Sandipan B.; Maì ti, Chinmay Kumar

2014-01-01

Biological synaptic behavior in terms of long term potentiation has been observed in papain-based (plant protein) memory devices (memristors) for the first time. Improvement in long term potentiation depends on pulse amplitude and width (duration). Continuous/repetitive dc voltage sweep leads to an increase in memristor conductivity leading to a long term memory in the 'learning' processes.

Observation of long term potentiation in papain-based memory devices

KAUST Repository

Bag, A.

2014-06-01

Biological synaptic behavior in terms of long term potentiation has been observed in papain-based (plant protein) memory devices (memristors) for the first time. Improvement in long term potentiation depends on pulse amplitude and width (duration). Continuous/repetitive dc voltage sweep leads to an increase in memristor conductivity leading to a long term memory in the \\'learning\\' processes.

Application of graphene oxide-poly (vinyl alcohol) polymer nanocomposite for memory devices

Science.gov (United States)

Kaushal, Jyoti; Kaur, Ravneet; Sharma, Jadab; Tripathi, S. K.

2018-05-01

Significant attention has been gained by polymer nanocomposites because of their possible demands in future electronic memory devices. In the present work, device based on Graphene Oxide (GO) and polyvinyl alcohol (PVA) has been made and examined for the memory device application. The prepared Graphene oxide (GO) and GO-PVA nanocomposite (NC) has been characterized by X-ray Diffraction (XRD). GO nanosheets show the diffraction peak at 2θ = 11.60° and the interlayer spacing of 0.761 nm. The XRD of GO-PVA NC shows the diffraction peak at 2θ =18.56°. The fabricated device shows bipolar switching behavior having ON/OFF current ratio ˜102. The Write-Read-Erase-Read (WRER) cycles test shows that the Al/GO-PVA/Ag device has good stability and repeatability.

Novel nano materials for high performance logic and memory devices

Science.gov (United States)

Das, Saptarshi

After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

Germanium nanoparticles grown at different deposition times for memory device applications

International Nuclear Information System (INIS)

Mederos, M.; Mestanza, S.N.M.; Lang, R.; Doi, I.; Diniz, J.A.

2016-01-01

In the present work, circular Metal-Oxide-Semiconductor capacitors with 200 μm of diameter and germanium (Ge) nanoparticles (NPs) embedded in the gate oxide are studied for memory applications. Optimal process parameters are investigated for Ge NPs growing by low pressure chemical vapor deposition at different deposition times. Photoluminescence measurements showed room-temperature size-dependent green-red region bands attributed to quantum confinement effects present in the NPs. High-frequency capacitance versus voltage measurements demonstrated the memory effects on the MOS structures due to the presence of Ge NPs in the gate oxide acting as discrete floating gates. Current versus voltage measurements confirmed the Fowler-Nordheim tunneling as the programming mechanism of the devices. - Highlights: • Ge nanoparticles with high density and uniforms sizes were obtained by LPCVD. • Room-temperature size-dependent bands of photoluminescence were observed. • MOS capacitors with Ge nanoparticles embedded in the oxide were fabricated. • Ge nanoparticles are the main responsible for the memory properties in the devices. • Fowler-Nordheim tunneling is the conduction mechanism observed on the devices.

Germanium nanoparticles grown at different deposition times for memory device applications

Energy Technology Data Exchange (ETDEWEB)

Mederos, M., E-mail: melissa.mederos@gmail.com [Center for Semiconductor Components and Nanotechnology (CCSNano), University of Campinas (Unicamp), Rua João Pandia Calógeras 90, Campinas, CEP: 13083-870, São Paulo (Brazil); Mestanza, S.N.M. [Federal University of ABC (UFABC), Rua Santa Adélia 166, Bangu, Santo André, CEP: 09210-170, São Paulo (Brazil); Lang, R. [Institute of Science and Technology, Federal University of São Paulo (UNIFESP), Rua Talim, 330, São José dos Campos, CEP: 12231-280, São Paulo (Brazil); Doi, I.; Diniz, J.A. [Center for Semiconductor Components and Nanotechnology (CCSNano), University of Campinas (Unicamp), Rua João Pandia Calógeras 90, Campinas, CEP: 13083-870, São Paulo (Brazil); School of Electrical and Computer Engineering, University of Campinas (Unicamp), Av. Albert Einstein 400, Campinas, CEP: 13083-852, São Paulo (Brazil)

2016-07-29

In the present work, circular Metal-Oxide-Semiconductor capacitors with 200 μm of diameter and germanium (Ge) nanoparticles (NPs) embedded in the gate oxide are studied for memory applications. Optimal process parameters are investigated for Ge NPs growing by low pressure chemical vapor deposition at different deposition times. Photoluminescence measurements showed room-temperature size-dependent green-red region bands attributed to quantum confinement effects present in the NPs. High-frequency capacitance versus voltage measurements demonstrated the memory effects on the MOS structures due to the presence of Ge NPs in the gate oxide acting as discrete floating gates. Current versus voltage measurements confirmed the Fowler-Nordheim tunneling as the programming mechanism of the devices. - Highlights: • Ge nanoparticles with high density and uniforms sizes were obtained by LPCVD. • Room-temperature size-dependent bands of photoluminescence were observed. • MOS capacitors with Ge nanoparticles embedded in the oxide were fabricated. • Ge nanoparticles are the main responsible for the memory properties in the devices. • Fowler-Nordheim tunneling is the conduction mechanism observed on the devices.

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

Science.gov (United States)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Resistive switching effect of N-doped MoS2-PVP nanocomposites films for nonvolatile memory devices

Science.gov (United States)

Wu, Zijin; Wang, Tongtong; Sun, Changqi; Liu, Peitao; Xia, Baorui; Zhang, Jingyan; Liu, Yonggang; Gao, Daqiang

2017-12-01

Resistive memory technology is very promising in the field of semiconductor memory devices. According to Liu et al, MoS2-PVP nanocomposite can be used as an active layer material for resistive memory devices due to its bipolar resistive switching behavior. Recent studies have also indicated that the doping of N element can reduce the band gap of MoS2 nanosheets, which is conducive to improving the conductivity of the material. Therefore, in this paper, we prepared N-doped MoS2 nanosheets and then fabricated N-doped MoS2-PVP nanocomposite films by spin coating. Finally, the resistive memory [C. Tan et al., Chem. Soc. Rev. 44, 2615 (2015)], device with ITO/N-doped MoS2-PVP/Pt structure was fabricated. Study on the I-V characteristics shows that the device has excellent resistance switching effect. It is worth mentioning that our device possesses a threshold voltage of 0.75 V, which is much better than 3.5 V reported previously for the undoped counterparts. The above research shows that N-doped MoS2-PVP nanocomposite films can be used as the active layer of resistive switching memory devices, and will make the devices have better performance.

Flexible All-Inorganic Perovskite CsPbBr3 Nonvolatile Memory Device.

Science.gov (United States)

Liu, Dongjue; Lin, Qiqi; Zang, Zhigang; Wang, Ming; Wangyang, Peihua; Tang, Xiaosheng; Zhou, Miao; Hu, Wei

2017-02-22

All-inorganic perovskite CsPbX 3 (X = Cl, Br, or I) is widely used in a variety of photoelectric devices such as solar cells, light-emitting diodes, lasers, and photodetectors. However, studies to understand the flexible CsPbX 3 electrical application are relatively scarce, mainly due to the limitations of the low-temperature fabricating process. In this study, all-inorganic perovskite CsPbBr 3 films were successfully fabricated at 75 °C through a two-step method. The highly crystallized films were first employed as a resistive switching layer in the Al/CsPbBr 3 /PEDOT:PSS/ITO/PET structure for flexible nonvolatile memory application. The resistive switching operations and endurance performance demonstrated the as-prepared flexible resistive random access memory devices possess reproducible and reliable memory characteristics. Electrical reliability and mechanical stability of the nonvolatile device were further tested by the robust current-voltage curves under different bending angles and consecutive flexing cycles. Moreover, a model of the formation and rupture of filaments through the CsPbBr 3 layer was proposed to explain the resistive switching effect. It is believed that this study will offer a new setting to understand and design all-inorganic perovskite materials for future stable flexible electronic devices.

Anomalous Threshold Voltage Variability of Nitride Based Charge Storage Nonvolatile Memory Devices

Directory of Open Access Journals (Sweden)

Meng Chuan Lee

2013-01-01

Full Text Available Conventional technology scaling is implemented to meet the insatiable demand of high memory density and low cost per bit of charge storage nonvolatile memory (NVM devices. In this study, effect of technology scaling to anomalous threshold voltage ( variability is investigated thoroughly on postcycled and baked nitride based charge storage NVM devices. After long annealing bake of high temperature, cell’s variability of each subsequent bake increases within stable distribution and found exacerbate by technology scaling. Apparent activation energy of this anomalous variability was derived through Arrhenius plots. Apparent activation energy (Eaa of this anomalous variability is 0.67 eV at sub-40 nm devices which is a reduction of approximately 2 times from 110 nm devices. Technology scaling clearly aggravates this anomalous variability, and this poses reliability challenges to applications that demand strict control, for example, reference cells that govern fundamental program, erase, and verify operations of NVM devices. Based on critical evidence, this anomalous variability is attributed to lateral displacement of trapped charges in nitride storage layer. Reliability implications of this study are elucidated. Moreover, potential mitigation methods are proposed to complement technology scaling to prolong the front-runner role of nitride based charge storage NVM in semiconductor flash memory market.

Microwave oven fabricated hybrid memristor devices for non-volatile memory storage

International Nuclear Information System (INIS)

Verrelli, E; Gray, R J; O’Neill, M; Kemp, N T; Kelly, S M

2014-01-01

Novel hybrid non-volatile memories made using an ultra-fast microwave heating method are reported for the first time. The devices, consisting of aligned ZnO nanorods embedded in poly (methyl methacrylate), require no forming step and exhibit reliable and reproducible bipolar resistive switching at low voltages and with low power usage. We attribute these properties to a combination of the high aspect ratio of the nanorods and the polymeric hybrid structure of the device. The extremely easy, fast and low-cost solution based method of fabrication makes possible the simple and quick production of cheap memory cells. (paper)

All-spin logic operations: Memory device and reconfigurable computing

Science.gov (United States)

Patra, Moumita; Maiti, Santanu K.

2018-02-01

Exploiting spin degree of freedom of electron a new proposal is given to characterize spin-based logical operations using a quantum interferometer that can be utilized as a programmable spin logic device (PSLD). The ON and OFF states of both inputs and outputs are described by spin state only, circumventing spin-to-charge conversion at every stage as often used in conventional devices with the inclusion of extra hardware that can eventually diminish the efficiency. All possible logic functions can be engineered from a single device without redesigning the circuit which certainly offers the opportunities of designing new generation spintronic devices. Moreover, we also discuss the utilization of the present model as a memory device and suitable computing operations with proposed experimental setups.

Numerical analysis of a polysilicon-based resistive memory device

KAUST Repository

Berco, Dan; Chand, Umesh

2018-01-01

This study investigates a conductive bridge resistive memory device based on a Cu top electrode, 10-nm polysilicon resistive switching layer and a TiN bottom electrode, by numerical analysis for $$10^{3}$$103 programming and erase simulation cycles

Spatial memory in nonhuman primates implanted with the subdural pharmacotherapy device.

Science.gov (United States)

Ludvig, Nandor; Tang, Hai M; Baptiste, Shirn L; Stefanov, Dimitre G; Kral, John G

2015-06-01

This study investigated the possible influence of the Subdural Pharmacotherapy Device (SPD) on spatial memory in 3 adult, male bonnet macaques (Macaca radiata). The device was implanted in and above the subdural/subarachnoid space and cranium overlaying the right parietal/frontal cortex: a circuitry involved in spatial memory processing. A large test chamber, equipped with four baited and four non-baited food-ports at different locations, was used: reaches into empty food ports were counted as spatial memory errors. In this study of within-subject design, before SPD implantation (control) the animals made mean 373.3 ± 114.9 (mean ± SEM) errors in the first spatial memory test session. This value dropped to 47.7 ± 18.4 by the 8th session. After SPD implantation and alternating cycles of transmeningeal saline delivery and local cerebrospinal fluid (CSF) drainage in the implanted cortex the spatial memory error count, with the same port locations, was 33.0 ± 12.2 during the first spatial memory test session, further decreasing to 5.7 ± 3.5 by the 8th post-implantation session (Pmemory performance, which in fact included at least one completely error-free session per animal over time. The study showed that complication-free implantation and use of the SPD over the parietal and frontal cortices for months leave spatial memory processes intact in nonhuman primates. Copyright © 2015 Elsevier B.V. All rights reserved.

Negative effect of Au nanoparticles on an IGZO TFT-based nonvolatile memory device

Energy Technology Data Exchange (ETDEWEB)

Lim, Myunghoon; Yoo, Gwangwe; Lee, Jongtaek; Jeong, Seokwon; Roh, Yonghan; Park, Jinhong; Kwon, Namyong [Sungkyunkwan University, Suwon (Korea, Republic of); Jung, Wooshik [Stanford University, Stanford, CA (United States)

2014-02-15

In this letter, the electrical characteristics of nonvolatile memory devices based on back gate type indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are investigated in terms of the Au nanoparticles (NPs) employed in the floating gate-stack of the device. The size of the Au NPs is controlled using a by 500 .deg. C annealing process after the Au thin-film deposition. The size and the roughness of the Au NPs were observed by using scanning electron microscopy, atomic force microscopy, and transmission electron microscopy. In order to analyze the electrical properties according to Au NP size, we measured the current-voltage (I{sub D}-V{sub G}) characteristics of the nonvolatile memory devices fabricated without Au NPs and with Au NPs of various sizes. The size of the Au NP increased, so did the surface roughness of the gate. This resulted in increased carrier scattering, which subsequently degraded the on-current of the memory device. In addition, inter-diffusion between the Au and the α-IGZO through the non-uniform Al{sub 2}O{sub 3} tunneling layer seemed to further degrade the device performance.

Interfacial behavior of resistive switching in ITO–PVK–Al WORM memory devices

International Nuclear Information System (INIS)

Whitcher, T J; Woon, K L; Wong, W S; Chanlek, N; Nakajima, H; Saisopa, T; Songsiriritthigul, P

2016-01-01

Understanding the mechanism of resistive switching in a memory device is fundamental in order to improve device performance. The mechanism of current switching in a basic organic write-once read-many (WORM) memory device is investigated by determining the energy level alignments of indium tin oxide (ITO), poly(9-vinylcarbazole) (PVK) and aluminum (Al) using x-ray and ultraviolet photoelectron spectroscopy, current–voltage characterization and Auger depth profiling. The current switching mechanism was determined to be controlled by the interface between the ITO and the PVK. The electric field applied across the device causes the ITO from the uneven surface of the anode to form metallic filaments through the PVK, causing a shorting effect within the device leading to increased conduction. This was found to be independent of the PVK thickness, although the switch-on voltage was non-linearly dependent on the thickness. The formation of these filaments also caused the destruction of the interfacial dipole at the PVK–Al interface. (paper)

Interfacial behavior of resistive switching in ITO-PVK-Al WORM memory devices

Science.gov (United States)

Whitcher, T. J.; Woon, K. L.; Wong, W. S.; Chanlek, N.; Nakajima, H.; Saisopa, T.; Songsiriritthigul, P.

2016-02-01

Understanding the mechanism of resistive switching in a memory device is fundamental in order to improve device performance. The mechanism of current switching in a basic organic write-once read-many (WORM) memory device is investigated by determining the energy level alignments of indium tin oxide (ITO), poly(9-vinylcarbazole) (PVK) and aluminum (Al) using x-ray and ultraviolet photoelectron spectroscopy, current-voltage characterization and Auger depth profiling. The current switching mechanism was determined to be controlled by the interface between the ITO and the PVK. The electric field applied across the device causes the ITO from the uneven surface of the anode to form metallic filaments through the PVK, causing a shorting effect within the device leading to increased conduction. This was found to be independent of the PVK thickness, although the switch-on voltage was non-linearly dependent on the thickness. The formation of these filaments also caused the destruction of the interfacial dipole at the PVK-Al interface.

Modeling of strain effects on the device behaviors of ferroelectric memory field-effect transistors

International Nuclear Information System (INIS)

Yang, Feng; Hu, Guangda; Wu, Weibing; Yang, Changhong; Wu, Haitao; Tang, Minghua

2013-01-01

The influence of strains on the channel current–gate voltage behaviors and memory windows of ferroelectric memory field-effect transistors (FeMFETs) were studied using an improved model based on the Landau–Devonshire theory. ‘Channel potential–gate voltage’ ferroelectric polarization and silicon surface potential diagrams were constructed for strained single-domain BaTiO 3 FeMFETs. The compressive strains can increase (or decrease) the amplitude of transistor currents and enlarge memory windows. However, tensile strains only decrease the maximum value of transistor currents and compress memory windows. Mismatch strains were found to have a significant influence on the electrical behaviors of the devices, therefore, they must be considered in FeMFET device designing. (fast track communication)

Camera memory study for large space telescope. [charge coupled devices

Science.gov (United States)

Hoffman, C. P.; Brewer, J. E.; Brager, E. A.; Farnsworth, D. L.

1975-01-01

Specifications were developed for a memory system to be used as the storage media for camera detectors on the large space telescope (LST) satellite. Detectors with limited internal storage time such as intensities charge coupled devices and silicon intensified targets are implied. The general characteristics are reported of different approaches to the memory system with comparisons made within the guidelines set forth for the LST application. Priority ordering of comparisons is on the basis of cost, reliability, power, and physical characteristics. Specific rationales are provided for the rejection of unsuitable memory technologies. A recommended technology was selected and used to establish specifications for a breadboard memory. Procurement scheduling is provided for delivery of system breadboards in 1976, prototypes in 1978, and space qualified units in 1980.

Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

International Nuclear Information System (INIS)

Wang Guangli; Chen Yubin; Shi Yi; Pu Lin; Pan Lijia; Zhang Rong; Zheng Youdou

2010-01-01

A novel two-step method is employed, for the first time, to fabricate nonvolatile memory devices that have metal nanocrystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concern for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method. (semiconductor devices)

Fabrication of poly(methyl methacrylate)-MoS{sub 2}/graphene heterostructure for memory device application

Energy Technology Data Exchange (ETDEWEB)

Shinde, Sachin M.; Tanemura, Masaki [Department of Frontier Materials, Nagoya Institute of Technology, Gokiso-cho, Showa-ku, Nagoya 466-8555 (Japan); Kalita, Golap, E-mail: kalita.golap@nitech.ac.jp [Department of Frontier Materials, Nagoya Institute of Technology, Gokiso-cho, Showa-ku, Nagoya 466-8555 (Japan); Center for Fostering Young and Innovative Researchers, Nagoya Institute of Technology, Gokiso-cho, Showa-ku, Nagoya 466-8555 (Japan)

2014-12-07

Combination of two dimensional graphene and semi-conducting molybdenum disulfide (MoS{sub 2}) is of great interest for various electronic device applications. Here, we demonstrate fabrication of a hybridized structure with the chemical vapor deposited graphene and MoS{sub 2} crystals to configure a memory device. Elongated hexagonal and rhombus shaped MoS{sub 2} crystals are synthesized by sulfurization of thermally evaporated molybdenum oxide (MoO{sub 3}) thin film. Scanning transmission electron microscope studies reveal atomic level structure of the synthesized high quality MoS{sub 2} crystals. In the prospect of a memory device fabrication, poly(methyl methacrylate) (PMMA) is used as an insulating dielectric material as well as a supporting layer to transfer the MoS{sub 2} crystals. In the fabricated device, PMMA-MoS{sub 2} and graphene layers act as the functional and electrode materials, respectively. Distinctive bistable electrical switching and nonvolatile rewritable memory effect is observed in the fabricated PMMA-MoS{sub 2}/graphene heterostructure. The developed material system and demonstrated memory device fabrication can be significant for next generation data storage applications.

Ferroelectric Thin Films Basic Properties and Device Physics for Memory Applications

CERN Document Server

Okuyama, Masanori

2005-01-01

Ferroelectric thin films continue to attract much attention due to their developing, diverse applications in memory devices, FeRAM, infrared sensors, piezoelectric sensors and actuators. This book, aimed at students, researchers and developers, gives detailed information about the basic properties of these materials and the associated device physics. All authors are acknowledged experts in the field.

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

International Nuclear Information System (INIS)

Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

2005-01-01

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device

International Nuclear Information System (INIS)

Seo, Kyungah; Park, Sangsu; Lee, Kwanghee; Lee, Byounghun; Hwang, Hyunsang; Kim, Insung; Jung, Seungjae; Jo, Minseok; Park, Jubong; Shin, Jungho; Biju, Kuyyadi P; Kong, Jaemin

2011-01-01

We demonstrated analog memory, synaptic plasticity, and a spike-timing-dependent plasticity (STDP) function with a nanoscale titanium oxide bilayer resistive switching device with a simple fabrication process and good yield uniformity. We confirmed the multilevel conductance and analog memory characteristics as well as the uniformity and separated states for the accuracy of conductance change. Finally, STDP and a biological triple model were analyzed to demonstrate the potential of titanium oxide bilayer resistive switching device as synapses in neuromorphic devices. By developing a simple resistive switching device that can emulate a synaptic function, the unique characteristics of synapses in the brain, e.g. combined memory and computing in one synapse and adaptation to the outside environment, were successfully demonstrated in a solid state device.

Characterization of gold nanoparticle pentacene memory device with polymer dielectric layer

International Nuclear Information System (INIS)

Kim, Hyung-Jun; Jung, Sung Mok; Kim, Yo-Han; Kim, Bong-Jin; Ha, Sanghyub; Kim, Yong-Sang; Yoon, Tae-Sik; Lee, Hyun Ho

2011-01-01

We report on the electrical behavior of gold nanoparticles (Au NPs) intervened metal-pentacene-insulator-semiconductor structures. The structure adopts polyvinyl alcohol (PVA) and pentacene as gate insulator and semiconductor, respectively. On the PVA (250 nm) film which was spin-coated and UV cross-linked, 3-aminopropyl triethoxysilane was functionalized for self assembling of the Au NPs monolayer. The devices exhibited clockwise hysteresis in their capacitance-voltage characteristics, with a memory window depending on the range of the voltage sweep. A relatively large memory window of about 4.7 V, which was deduced from control devices, was achieved with voltage sweep of (-/+)7 V. Formation of the monolayered Au NPs was confirmed by field effect scanning electron microscopy and atomic force microscopy.

Resistive switching characteristics of HfO2-based memory devices on flexible plastics.

Science.gov (United States)

Han, Yong; Cho, Kyoungah; Park, Sukhyung; Kim, Sangsig

2014-11-01

In this study, we examine the characteristics of HfO2-based resistive switching random access memory (ReRAM) devices on flexible plastics. The Pt/HfO2/Au ReRAM devices exhibit the unipolar resistive switching behaviors caused by the conducting filaments. From the Auger depth profiles of the HfO2 thin film, it is confirmed that the relatively lower oxygen content in the interface of the bottom electrode is responsible for the resistive switching by oxygen vacancies. And the unipolar resistive switching behaviors are analyzed from the C-V characteristics in which negative and positive capacitances are measured in the low-resistance state and the high-resistance state, respectively. The devices have a high on/off ratio of 10(4) and the excellent retention properties even after a continuous bending test of two thousand cycles. The correlation between the device size and the memory characteristics is investigated as well. A relatively smaller-sized device having a higher on/off ratio operates at a higher voltage than a relatively larger-sized device.

Realization of transient memory-loss with NiO-based resistive switching device

Science.gov (United States)

Hu, S. G.; Liu, Y.; Chen, T. P.; Liu, Z.; Yu, Q.; Deng, L. J.; Yin, Y.; Hosaka, Sumio

2012-11-01

A resistive switching device based on a nickel-rich nickel oxide thin film, which exhibits inherent learning and memory-loss abilities, is reported in this work. The conductance of the device gradually increases and finally saturates with the number of voltage pulses (or voltage sweepings), which is analogous to the behavior of the short-term and long-term memory in the human brain. Furthermore, the number of the voltage pulses (or sweeping cycles) required to achieve a given conductance state increases with the interval between two consecutive voltage pulses (or sweeping cycles), which is attributed to the heat diffusion in the material of the conductive filaments formed in the nickel oxide thin film. The phenomenon resembles the behavior of the human brain, i.e., forgetting starts immediately after an impression, a larger interval of the impressions leads to more memory loss, thus the memorization needs more impressions to enhance.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

Science.gov (United States)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-07-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices.

Evidence of Filamentary Switching in Oxide-based Memory Devices via Weak Programming and Retention Failure Analysis

Science.gov (United States)

Younis, Adnan; Chu, Dewei; Li, Sean

2015-09-01

Further progress in high-performance microelectronic devices relies on the development of novel materials and device architectures. However, the components and designs that are currently in use have reached their physical limits. Intensive research efforts, ranging from device fabrication to performance evaluation, are required to surmount these limitations. In this paper, we demonstrate that the superior bipolar resistive switching characteristics of a CeO2:Gd-based memory device can be manipulated by means of UV radiation, serving as a new degree of freedom. Furthermore, the metal oxide-based (CeO2:Gd) memory device was found to possess electrical and neuromorphic multifunctionalities. To investigate the underlying switching mechanism of the device, its plasticity behaviour was studied by imposing weak programming conditions. In addition, a short-term to long-term memory transition analogous to the forgetting process in the human brain, which is regarded as a key biological synaptic function for information processing and data storage, was realized. Based on a careful examination of the device’s retention behaviour at elevated temperatures, the filamentary nature of switching in such devices can be understood from a new perspective.

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures

Science.gov (United States)

Abhijith, T.; Kumar, T. V. Arun; Reddy, V. S.

2017-03-01

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO3) between two tris-(8-hydroxyquinoline)aluminum (Alq3) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 103 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO3 layer thickness and its location in the Alq3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

High-performance flexible resistive memory devices based on Al2O3:GeOx composite

Science.gov (United States)

Behera, Bhagaban; Maity, Sarmistha; Katiyar, Ajit K.; Das, Samaresh

2018-05-01

In this study a resistive switching random access memory device using Al2O3:GeOx composite thin films on flexible substrate is presented. A bipolar switching characteristic was observed for the co-sputter deposited Al2O3:GeOx composite thin films. Al/Al2O3:GeOx/ITO/PET memory device shows excellent ON/OFF ratio (∼104) and endurance (>500 cycles). GeOx nanocrystals embedded in the Al2O3 matrix have been found to play a significant role in enhancing the switching characteristics by facilitating oxygen vacancy formation. Mechanical endurance was retained even after several bending. The conduction mechanism of the device was qualitatively discussed by considering Ohmic and SCLC conduction. This flexible device is a potential candidate for next-generation electronics device.

Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices

Science.gov (United States)

Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

2016-01-01

Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr07377d

Device and methods for writing and erasing analog information in small memory units via voltage pulses

Science.gov (United States)

El Gabaly Marquez, Farid; Talin, Albert Alec

2018-04-17

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

Feasibility study of molecular memory device based on DNA using methylation to store information

Energy Technology Data Exchange (ETDEWEB)

Jiang, Liming; Al-Dirini, Feras [Department of Electrical and Electronic Engineering, The University of Melbourne, Parkville 3010 (Australia); Center for Neural Engineering (CfNE), The University of Melbourne, Carlton 3053 (Australia); National ICT Australia, The University of Melbourne, Parkville 3010 (Australia); Qiu, Wanzhi; Skafidas, Efstratios, E-mail: sskaf@unimelb.edu.au [Department of Electrical and Electronic Engineering, The University of Melbourne, Parkville 3010 (Australia); Center for Neural Engineering (CfNE), The University of Melbourne, Carlton 3053 (Australia); Hossain, Faruque M. [Center for Neural Engineering (CfNE), The University of Melbourne, Carlton 3053 (Australia); Evans, Robin [Department of Electrical and Electronic Engineering, The University of Melbourne, Parkville 3010 (Australia)

2016-07-14

DNA, because of its robustness and dense information storage capability, has been proposed as a potential candidate for next-generation storage media. However, encoding information into the DNA sequence requires molecular synthesis technology, which to date is costly and prone to synthesis errors. Reading the DNA strand information is also complex. Ideally, DNA storage will provide methods for modifying stored information. Here, we conduct a feasibility study investigating the use of the DNA 5-methylcytosine (5mC) methylation state as a molecular memory to store information. We propose a new 1-bit memory device and study, based on the density functional theory and non-equilibrium Green's function method, the feasibility of electrically reading the information. Our results show that changes to methylation states lead to changes in the peak of negative differential resistance which can be used to interrogate memory state. Our work demonstrates a new memory concept based on methylation state which can be beneficial in the design of next generation DNA based molecular electronic memory devices.

Feasibility study of molecular memory device based on DNA using methylation to store information

International Nuclear Information System (INIS)

Jiang, Liming; Al-Dirini, Feras; Qiu, Wanzhi; Skafidas, Efstratios; Hossain, Faruque M.; Evans, Robin

2016-01-01

DNA, because of its robustness and dense information storage capability, has been proposed as a potential candidate for next-generation storage media. However, encoding information into the DNA sequence requires molecular synthesis technology, which to date is costly and prone to synthesis errors. Reading the DNA strand information is also complex. Ideally, DNA storage will provide methods for modifying stored information. Here, we conduct a feasibility study investigating the use of the DNA 5-methylcytosine (5mC) methylation state as a molecular memory to store information. We propose a new 1-bit memory device and study, based on the density functional theory and non-equilibrium Green's function method, the feasibility of electrically reading the information. Our results show that changes to methylation states lead to changes in the peak of negative differential resistance which can be used to interrogate memory state. Our work demonstrates a new memory concept based on methylation state which can be beneficial in the design of next generation DNA based molecular electronic memory devices.

Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

KAUST Repository

Semple, James; Wyatt-Moon, Gwenhivir; Georgiadou, Dimitra G.; McLachlan, Martyn A.; Anthopoulos, Thomas D.

2017-01-01

Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

KAUST Repository

Semple, James

2017-01-02

Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

Science.gov (United States)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

A study of selenium nanoparticles as charge storage element for flexible semi-transparent memory devices

Science.gov (United States)

Alotaibi, Sattam; Nama Manjunatha, Krishna; Paul, Shashi

2017-12-01

Flexible Semi-Transparent electronic memory would be useful in coming years for integrated flexible transparent electronic devices. However, attaining such flexibility and semi-transparency leads to the boundaries in material composition. Thus, impeding processing speed and device performance. In this work, we present the use of inorganic stable selenium nanoparticles (Se-NPs) as a storage element and hydrogenated amorphous carbon (a-C:H) as an insulating layer in two terminal non-volatile physically flexible and semi-transparent capacitive memory devices (2T-NMDs). Furthermore, a-C:H films can be deposited at very low temperature (industrial technique called Plasma Enhanced Chemical Vapour Deposition (PECVD) which is available in many existing fabrication labs. Self-assembled Se-NPs has several unique features including deposition at room temperature by simple vacuum thermal evaporation process without the need for further optimisation. This facilitates the fabrication of memory on a flexible substrate. Moreover, the memory behaviour of the Se-NPs was found to be more distinct than those of the semiconductor and metal nanostructures due to higher work function compared to the commonly used semiconductor and metal species. The memory behaviour was observed from the hysteresis of current-voltage (I-V) measurements while the two distinguishable electrical conductivity states (;0; and "1") were studied by current-time (I-t) measurements.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

Science.gov (United States)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-01-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

Growth of Si nanocrystals on alumina and integration in memory devices

Science.gov (United States)

Baron, T.; Fernandes, A.; Damlencourt, J. F.; De Salvo, B.; Martin, F.; Mazen, F.; Haukka, S.

2003-06-01

We present a detailed study of the growth of Si quantum dots (Si QDs) by low pressure chemical vapor deposition on alumina dielectric deposited by atomic layer deposition. The Si QDs density is very high, 1012 cm-2, for a mean diameter between 5 and 10 nm. Al2O3/Si QD stacks have been integrated in memory devices as granular floating gate. The devices demonstrate good charge storage and data retention characteristics.

Zinc Cadmium Selenide Cladded Quantum Dot Based Electroluminescent and Nonvolatile Memory Devices

Science.gov (United States)

Al-Amody, Fuad H.

This dissertation presents electroluminescent (EL) and nonvolatile memory devices fabricated using pseudomorphic ZnCdSe-based cladded quantum dots (QDs). These dots were grown using our own in-school built novel reactor. The EL device was fabricated on a substrate of ITO (indium tin oxide) coated glass with the quantum dots sandwiched between anode and cathode contacts with a small barrier layer on top of the QDs. The importance of these cladded dots is to increase the quantum yield of device. This device is unique as they utilize quantum dots that are pseudomorphic (nearly lattice-matched core and the shell of the dot). In the case of floating quantum dot gate nonvolatile memory, cladded ZnCdSe quantum dots are deposited on single crystalline gate insulator (ZnMgS/ZnMgSe), which is grown using metal-organic chemical vapor deposition (MOCVD). The control gate dielectric layer of the nonvolatile memory is Si3N4 or SiO2 and is grown using plasma enhanced chemical vapor deposition (PECVD). The cladded dots are grown using an improved methodology of photo-assisted microwave plasma metal-organic chemical vapor deposition (PMP-MOCVD) enhanced reactor. The cladding composition of the core and shell of the dots was engineered by the help of ultraviolet light which changed the incorporation of zinc (and hence composition of ZnCdSe). This makes ZnxCd1--xSe-ZnyCd1--y Se QDs to have a low composition of zinc in the core than the cladding (x

Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

International Nuclear Information System (INIS)

Sung, Sihyun; Kim, Tae Whan

2017-01-01

Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10 3 and 1.4 × 10 3 , respectively. The retention times of the devices before and after bending remained same 1 × 10 4 s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

Energy Technology Data Exchange (ETDEWEB)

Sung, Sihyun; Kim, Tae Whan, E-mail: twk@hanyang.ac.kr

2017-07-31

Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10{sup 3} and 1.4 × 10{sup 3}, respectively. The retention times of the devices before and after bending remained same 1 × 10{sup 4} s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Science.gov (United States)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Memory device sensitivity trends in aircraft's environment

International Nuclear Information System (INIS)

Bouchet, T.; Fourtine, S.; Calvet, M.C.

1999-01-01

The authors present the SEU (single event upset) sensitivity of 31 SRAM (static random access memory) and 8 DRAM (dynamic random access memory) according to their technologies. 2 methods have been used to compute the SEU rate: the NCS (neutron cross section) method and the BGR (burst generation rate) method, the physics data required by both methods have been either found in scientific literature or directly measured. The use of new technologies implies a quicker time response through a dramatic reduction of chip size and of the amount of energy representing 1 bit. The reduction of size makes less particles are likely to interact with the chip but the reduction of the critical charge implies that these interactions are more likely to damage the chip. The SEU sensitivity is then parted between these 2 opposed trends. Results show that for technologies beyond 0,18 μm these 2 trends balance roughly. Nevertheless the feedback experience shows that the number of errors is increasing. This is due to the fact that avionics requires more and more memory to perform numerical functions, the number of bits is increasing so is the risk of errors. As far as SEU is concerned, RAM devices are less and less sensitive comparatively for 1 bit, and DRAM seem to be less sensitive than SRAM. (A.C.)

Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications

International Nuclear Information System (INIS)

Linn, E; Ferch, S; Waser, R; Menzel, S

2013-01-01

Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications. (paper)

The influence of Ti doping and annealing on Ce_2Ti_2O_7 flash memory devices

International Nuclear Information System (INIS)

Kao, Chyuan Haur; Chen, Su Zhien; Luo, Yang; Chiu, Wang Ting; Chiu, Shih Wei; Chen, I Chien; Lin, Chan-Yu; Chen, Hsiang

2017-01-01

Highlights: • Ce_2Ti_2O_7 flash memories have been fabricated. • Material quality can be improved by annealing. • The memory performance can be enhanced by Ti doping. • Ti doping and annealing can reinforce crystallization. - Abstract: In this research, a CeO_2 film with Ti doping was used as a trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type memory devices. Since incorporation of Ti atoms into the film could fix dangling bonds and defects, the Ce_2Ti_2O_7 trapping layer with annealing treatment could have a larger memory window and a faster programming/erasing speed. To confirm the origin, multiple material analyses indicate that annealing at an appropriate temperature and Ti doping could enhance crystallization. The Ce_2Ti_2O_7-based memory device is promising for future industrial flash memory applications.

Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device

Directory of Open Access Journals (Sweden)

W. J. Liu

2016-01-01

Full Text Available We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

Application of complex programmable logic devices in memory radiation effects test system

International Nuclear Information System (INIS)

Li Yonghong; He Chaohui; Yang Hailiang; He Baoping

2005-01-01

The application of the complex programmable logic device (CPLD) in electronics is emphatically discussed. The method of using software MAX + plus II and CPLD are introduced. A new test system for memory radiation effects is established by using CPLD devices-EPM7128C84-15. The old test system's function are realized and, moreover, a number of small scale integrated circuits are reduced and the test system's reliability is improved. (authors)

Effect of hydrogen ion beam treatment on Si nanocrystal/SiO_2 superlattice-based memory devices

International Nuclear Information System (INIS)

Fu, Sheng-Wen; Chen, Hui-Ju; Wu, Hsuan-Ta; Chuang, Bing-Ru; Shih, Chuan-Feng

2016-01-01

Graphical abstract: - Highlights: • Memory window and retention properties are improved employing HIBAS technique. • The O/Si ratio and radiative recombination are changed by HIBAS. • Memory properties are affected not only by Si NCs and O/Si ratio but also the RDCs. • The mechanism of hydrogen ion beam alters the memory properties is investigated. - Abstract: This study presents a novel route for synthesizing silicon-rich oxide (SRO)/SiO_2 superlattice-based memory devices with an improved memory window and retention properties. The SiO_2 and SRO superlattices are deposited by reactive sputtering. Specifically, the hydrogen ion beam is used to irradiate the SRO layer immediately after its deposition in the vacuum chamber. The use of the hydrogen ion beam was determined to increase oxygen content and the density of the Si nanocrystals. The memory window increased from 16 to 25.6 V, and the leakage current decreased significantly by two orders, to under ±20 V, for the hydrogen ion beam-prepared devices. This study investigates the mechanism into how hydrogen ion beam treatment alters SRO films and influences memory properties.

Unusual magnetic behavior in a chiral-based magnetic memory device

Energy Technology Data Exchange (ETDEWEB)

Ben-Dor, Oren; Yochelis, Shira [Department of Applied Physics, Center of Nanoscience and Nanotechnology, Hebrew University, Jerusalem 91904 (Israel); Felner, Israel, E-mail: Israel.felner@mail.huij.ac.il [“Racah” Institute of Physics, Hebrew University, Jerusalem 91904 (Israel); Paltiel, Yossi [Department of Applied Physics, Center of Nanoscience and Nanotechnology, Hebrew University, Jerusalem 91904 (Israel)

2016-01-15

In recent years chiral molecules were found to act as efficient spin filters. Using a multilayer structure with chiral molecules magnetic memory was realized. Observed rare magnetic phenomena in a chiral-based magnetic memory device was reported by O-Ben Dor et. al in Nature Commun, 4, 2256 (2013). This multi-layered device is built from α-helix L-polyalanine (AHPA-L) adsorbed on gold, Al{sub 2}O{sub 3} (7 nm) and Ni (30 nm) layers. It was shown that certain temperature range the FC branch crosses the magnetic peak (at 55 K) observed in the ZFC curve thus ZFC>FC. We show here that in another similar multi-layered material, at low applied field, the ZFC curve lies above the FC one up to 70 K. The two features have the same origin and the crucial necessary components to exhibit them are: AHPA-L and 30 nm Ni layered thick. Similar effects were also reported in sulfur doped amorphous carbon. A comparison between the two systems and the ingredients for these peculiar observations is discussed. - Highlights: • The highlights of the present manuscript is the peculiar magnetic behavior observed in a multilayer structure with chiral molecules, magnetic memory. • It is shown that certain temperature range the FC branch crosses the magnetic peak (at 55 K) observed in the ZFC curve thus ZFC>FC. • Similar effects were also reported in sulfur doped amorphous carbon.

Effect of vacuum annealing on evaporated pentacene thin films for memory device applications

International Nuclear Information System (INIS)

Gayathri, A.G.; Joseph, C.M.

2016-01-01

Graphical abstract: Switching of ITO/pentacene/Al thin films for different annealing temperatures. - Highlights: • Memory device performance in pentacene improved considerably with annealing. • ON/OFF ratio of the pentacene device increases due to annealing. • Threshold voltage reduces from 2.55 V to 1.35 V due to annealing. • Structure of pentacene thin films is also dependent on annealing temperature. - Abstract: Thin films of pentacene were deposited thermally onto glass substrates and annealed at 323 K, 373 K, 423 K, 473 K and 523 K in high vacuum. Effect of annealing on the morphological and structural properties of these films was studied. X-ray diffraction patterns confirmed the crystalline nature of the films. Electrical studies for the use as write once read many (WORM) memory devices were done for the vacuum deposited pentacene thin films on indium tin oxide coated glass. Due to annealing, a sharp increase in the ON/OFF ratio of current and a decrease in threshold voltage were observed at around 373 K. This device showed a stable switching with an ON/OFF current ratio as high as 10 9 and a switching threshold voltage of 1.35 V. The performance of the device degraded above 423 K due to the changes in the crystallinity of the film.

Effect of vacuum annealing on evaporated pentacene thin films for memory device applications

Energy Technology Data Exchange (ETDEWEB)

Gayathri, A.G., E-mail: gaythri305@yahoo.com; Joseph, C.M., E-mail: cmjoseph@rediffmail.com

2016-09-15

Graphical abstract: Switching of ITO/pentacene/Al thin films for different annealing temperatures. - Highlights: • Memory device performance in pentacene improved considerably with annealing. • ON/OFF ratio of the pentacene device increases due to annealing. • Threshold voltage reduces from 2.55 V to 1.35 V due to annealing. • Structure of pentacene thin films is also dependent on annealing temperature. - Abstract: Thin films of pentacene were deposited thermally onto glass substrates and annealed at 323 K, 373 K, 423 K, 473 K and 523 K in high vacuum. Effect of annealing on the morphological and structural properties of these films was studied. X-ray diffraction patterns confirmed the crystalline nature of the films. Electrical studies for the use as write once read many (WORM) memory devices were done for the vacuum deposited pentacene thin films on indium tin oxide coated glass. Due to annealing, a sharp increase in the ON/OFF ratio of current and a decrease in threshold voltage were observed at around 373 K. This device showed a stable switching with an ON/OFF current ratio as high as 10{sup 9} and a switching threshold voltage of 1.35 V. The performance of the device degraded above 423 K due to the changes in the crystallinity of the film.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

Science.gov (United States)

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

Chemical insight into origin of forming-free resistive random-access memory devices

KAUST Repository

Wu, X.; Fang, Z.; Li, K.; Bosman, M.; Raghavan, N.; Li, X.; Yu, H. Y.; Singh, N.; Lo, G. Q.; Zhang, Xixiang; Pey, K. L.

2011-01-01

We demonstrate the realization of a forming-step free resistive random access memory (RRAM) device using a HfOx/TiOx/HfOx/TiOxmultilayer structure, as a replacement for the conventional HfOx-based single layer structure. High-resolution transmission

Migration of interfacial oxygen ions modulated resistive switching in oxide-based memory devices

Science.gov (United States)

Chen, C.; Gao, S.; Zeng, F.; Tang, G. S.; Li, S. Z.; Song, C.; Fu, H. D.; Pan, F.

2013-07-01

Oxides-based resistive switching memory induced by oxygen ions migration is attractive for future nonvolatile memories. Numerous works had focused their attentions on the sandwiched oxide materials for depressing the characteristic variations, but the comprehensive studies of the dependence of electrodes on the migration behavior of oxygen ions are overshadowed. Here, we investigated the interaction of various metals (Ni, Co, Al, Ti, Zr, and Hf) with oxygen atoms at the metal/Ta2O5 interface under electric stress and explored the effect of top electrode on the characteristic variations of Ta2O5-based memory device. It is demonstrated that chemically inert electrodes (Ni and Co) lead to the scattering switching characteristics and destructive gas bubbles, while the highly chemically active metals (Hf and Zr) formed a thick and dense interfacial intermediate oxide layer at the metal/Ta2O5 interface, which also degraded the resistive switching behavior. The relatively chemically active metals (Al and Ti) can absorb oxygen ions from the Ta2O5 film and avoid forming the problematic interfacial layer, which is benefit to the formation of oxygen vacancies composed conduction filaments in Ta2O5 film thus exhibit the minimum variations of switching characteristics. The clarification of oxygen ions migration behavior at the interface can lead further optimization of resistive switching performance in Ta2O5-based memory device and guide the rule of electrode selection for other oxide-based resistive switching memories.

Defect engineering: reduction effect of hydrogen atom impurities in HfO2-based resistive-switching memory devices

International Nuclear Information System (INIS)

Kim, Seonghyun; Park, Jubong; Jung, Seungjae; Lee, Wootae; Shin, Jungho; Hwang, Hyunsang; Lee, Daeseok; Woo, Jiyong; Choi, Godeuni

2012-01-01

In this study, we propose a new and effective methodology for improving the resistive-switching performance of memory devices by high-pressure hydrogen annealing under ambient conditions. The reduction effect results in the uniform creation of oxygen vacancies that in turn enable forming-free operation and afford uniform switching characteristics. In addition, H + and mobile hydroxyl (OH − ) ions are generated, and these induce fast switching operation due to the higher mobility compared to oxygen ions. Defect engineering, specifically, the introduction of hydrogen atom impurities, improves the device performance for metal–oxide-based resistive-switching random access memory devices. (paper)

Phase-change materials for non-volatile memory devices: from technological challenges to materials science issues

Science.gov (United States)

Noé, Pierre; Vallée, Christophe; Hippert, Françoise; Fillot, Frédéric; Raty, Jean-Yves

2018-01-01

Chalcogenide phase-change materials (PCMs), such as Ge-Sb-Te alloys, have shown outstanding properties, which has led to their successful use for a long time in optical memories (DVDs) and, recently, in non-volatile resistive memories. The latter, known as PCM memories or phase-change random access memories (PCRAMs), are the most promising candidates among emerging non-volatile memory (NVM) technologies to replace the current FLASH memories at CMOS technology nodes under 28 nm. Chalcogenide PCMs exhibit fast and reversible phase transformations between crystalline and amorphous states with very different transport and optical properties leading to a unique set of features for PCRAMs, such as fast programming, good cyclability, high scalability, multi-level storage capability, and good data retention. Nevertheless, PCM memory technology has to overcome several challenges to definitively invade the NVM market. In this review paper, we examine the main technological challenges that PCM memory technology must face and we illustrate how new memory architecture, innovative deposition methods, and PCM composition optimization can contribute to further improvements of this technology. In particular, we examine how to lower the programming currents and increase data retention. Scaling down PCM memories for large-scale integration means the incorporation of the PCM into more and more confined structures and raises materials science issues in order to understand interface and size effects on crystallization. Other materials science issues are related to the stability and ageing of the amorphous state of PCMs. The stability of the amorphous phase, which determines data retention in memory devices, can be increased by doping the PCM. Ageing of the amorphous phase leads to a large increase of the resistivity with time (resistance drift), which has up to now hindered the development of ultra-high multi-level storage devices. A review of the current understanding of all these

Empirical study of the metal-nitride-oxide-semiconductor device characteristics deduced from a microscopic model of memory traps

International Nuclear Information System (INIS)

Ngai, K.L.; Hsia, Y.

1982-01-01

A graded-nitride gate dielectric metal-nitride-oxide-semiconductor (MNOS) memory transistor exhibiting superior device characteristics is presented and analyzed based on a qualitative microscopic model of the memory traps. The model is further reviewed to interpret some generic properties of the MNOS memory transistors including memory window, erase-write speed, and the retention-endurance characteristic features

Investigations on the effects of electrode materials on the device characteristics of ferroelectric memory thin film transistors fabricated on flexible substrates

Science.gov (United States)

Yang, Ji-Hee; Yun, Da-Jeong; Seo, Gi-Ho; Kim, Seong-Min; Yoon, Myung-Han; Yoon, Sung-Min

2018-03-01

For flexible memory device applications, we propose memory thin-film transistors using an organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator and an amorphous In-Ga-Zn-O (a-IGZO) active channel. The effects of electrode materials and their deposition methods on the characteristics of memory devices exploiting the ferroelectric field effect were investigated for the proposed ferroelectric memory thin-film transistors (Fe-MTFTs) at flat and bending states. It was found that the plasma-induced sputtering deposition and mechanical brittleness of the indium-tin oxide (ITO) markedly degraded the ferroelectric-field-effect-driven memory window and bending characteristics of the Fe-MTFTs. The replacement of ITO electrodes with metal aluminum (Al) electrodes prepared by plasma-free thermal evaporation greatly enhanced the memory device characteristics even under bending conditions owing to their mechanical ductility. Furthermore, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) was introduced to achieve robust bending performance under extreme mechanical stress. The Fe-MTFTs using PEDOT:PSS source/drain electrodes were successfully fabricated and showed the potential for use as flexible memory devices. The suitable choice of electrode materials employed for the Fe-MTFTs is concluded to be one of the most important control parameters for highly functional flexible Fe-MTFTs.

InAs quantum dots as charge storing elements for applications in flash memory devices

Energy Technology Data Exchange (ETDEWEB)

Islam, Sk Masiul; Biswas, Pranab [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Banerji, P., E-mail: pallab@matsc.iitkgp.ernet.in [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Chakraborty, S. [Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064 (India)

2015-08-15

Graphical abstract: - Highlights: • Catalyst-free growth of InAs quantum dots was carried out on high-k ZrO{sub 2}. • Memory device with InAs quantum dots as charge storage nodes are fabricated. • Superior memory window, low leakage and reasonably good retention were observed. • Carrier transport phenomena are explained in both program and erase operations. - Abstract: InAs quantum dots (QDs) were grown by metal organic chemical vapor deposition technique to use them as charge storage nodes. Uniform QDs were formed with average diameter 5 nm and height 5–10 nm with a density of 2 × 10{sup 11} cm{sup −2}. The QDs were grown on high-k dielectric layer (ZrO{sub 2}), which was deposited onto ultra-thin GaP passivated p-GaAs (1 0 0) substrate. A charge storage device with the structure Metal/ZrO{sub 2}/InAs QDs/ZrO{sub 2}/(GaP)GaAs/Metal was fabricated. The devices containing InAs QDs exhibit superior memory window, low leakage current density along with reasonably good charge retention. A suitable electronic band diagram corresponding to programming and erasing operations was proposed to explain the operation.

Towards an Artificial Phonological Loop: An Assistive Device for Working Memory and Attentional Control

Directory of Open Access Journals (Sweden)

D. Bogen

2006-01-01

Full Text Available We describe the initial development of an artificial phonological loop (APL, a new technology to assist individuals with impairment of the working memory system. The phonological loop, along with the visuospatial sketchpad, is one of the two slave short-term memory subsystems that comprise working memory, a cognitive function closely associated with the control of attention. In the phonological loop, phonological (speech information lasting for 1–2 second is maintained active by repetitive, subvocal (silent speech rehearsal. Deficits in working memory, specifically in the phonological loop, occur in many disorders, including attention-deficit disorder and Alzheimer’s disease. In these disorders, it appears that the ability for phonological rehearsal is intact, but the regulation or triggering of the rehearsal process is inadequate, thus causing the contents of working memory to be lost. The purpose, then, of the APL is to facilitate the phonological loop by artificially extending the duration of phonological rehearsals. The APL mimics the natural phonological loop by providing audible vocal echoes to take the place of subvocal rehearsals. In this system, the user talks to him/herself in short (1–2 second phrases; the device records these phrases, stores them in electronic memory, and then repeats— i.e., echoes—the phrases multiple times over an extended period. Two versions of this device have been developed: the Echo-APL and the Rearticulation-APL. In the Echo-APL, only echoing is involved. In the Rearticulation-APL, however, the user re-vocalizes (rearticulates the phrase in response to an audible cue. The device repeats the cue until it detects (hears the re-vocalization. Future research and development of the APL will require extensive testing and careful evaluation of possible echo-schedules: the predefined program controlling inter-echo time intervals and echo-amplitude (echo loudness. The APL essentially exteriorizes the silent

Memory Device and Nanofabrication Techniques Using Electrically Configurable Materials

Science.gov (United States)

Ascenso Simões, Bruno

Development of novel nanofabrication techniques and single-walled carbon nanotubes field configurable transistor (SWCNT-FCT) memory devices using electrically configurable materials is presented. A novel lithographic technique, electric lithography (EL), that uses electric field for pattern generation has been demonstrated. It can be used for patterning of biomolecules on a polymer surface and patterning of resist as well. Using electrical resist composed of a polymer having Boc protected amine group and iodonium salt, Boc group on the surface of polymer was modified to free amine by applying an electric field. On the modified surface of the polymer, Streptavidin pattern was fabricated with a sub-micron scale. Also patterning of polymer resin composed of epoxy monomers and diaryl iodonium salt by EL has been demonstrated. Reaction mechanism for electric resist configuration is believed to be induced by an acid generation via electrochemical reduction in the resist. We show a novel field configurable transistor (FCT) based on single-walled carbon nanotube network field-effect transistors in which poly (ethylene glycol) crosslinked by electron-beam is incorporated into the gate. The device conductance can be configured to arbitrary states reversibly and repeatedly by applying external gate voltages. Raman spectroscopy revealed that evolution of the ratio of D- to G-band intensity in the SWCNTs of the FCT progressively increases as the device is configured to lower conductance states. Electron transport studies at low temperatures showed a strong temperature dependence of the resistance. Band gap widening of CNTs up to ˜ 4 eV has been observed by examining the differential conductance-gate voltage-bias voltage relationship. The switching mechanism of the FCT is attributed a structural transformation of CNTs via reversible hydrogenation and dehydrogenations induced by gate voltages, which tunes the CNT bandgap continuously and reversibly to non-volatile analog values

Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

Science.gov (United States)

Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

2016-04-01

The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

Shape memory polymer medical device

Science.gov (United States)

Maitland, Duncan [Pleasant Hill, CA; Benett, William J [Livermore, CA; Bearinger, Jane P [Livermore, CA; Wilson, Thomas S [San Leandro, CA; Small, IV, Ward; Schumann, Daniel L [Concord, CA; Jensen, Wayne A [Livermore, CA; Ortega, Jason M [Pacifica, CA; Marion, III, John E.; Loge, Jeffrey M [Stockton, CA

2010-06-29

A system for removing matter from a conduit. The system includes the steps of passing a transport vehicle and a shape memory polymer material through the conduit, transmitting energy to the shape memory polymer material for moving the shape memory polymer material from a first shape to a second and different shape, and withdrawing the transport vehicle and the shape memory polymer material through the conduit carrying the matter.

An ultrafast programmable electrical tester for enabling time-resolved, sub-nanosecond switching dynamics and programming of nanoscale memory devices

Science.gov (United States)

Shukla, Krishna Dayal; Saxena, Nishant; Manivannan, Anbarasu

2017-12-01

Recent advancements in commercialization of high-speed non-volatile electronic memories including phase change memory (PCM) have shown potential not only for advanced data storage but also for novel computing concepts. However, an in-depth understanding on ultrafast electrical switching dynamics is a key challenge for defining the ultimate speed of nanoscale memory devices that demands for an unconventional electrical setup, specifically capable of handling extremely fast electrical pulses. In the present work, an ultrafast programmable electrical tester (PET) setup has been developed exceptionally for unravelling time-resolved electrical switching dynamics and programming characteristics of nanoscale memory devices at the picosecond (ps) time scale. This setup consists of novel high-frequency contact-boards carefully designed to capture extremely fast switching transient characteristics within 200 ± 25 ps using time-resolved current-voltage measurements. All the instruments in the system are synchronized using LabVIEW, which helps to achieve various programming characteristics such as voltage-dependent transient parameters, read/write operations, and endurance test of memory devices systematically using short voltage pulses having pulse parameters varied from 1 ns rise/fall time and 1.5 ns pulse width (full width half maximum). Furthermore, the setup has successfully demonstrated strikingly one order faster switching characteristics of Ag5In5Sb60Te30 (AIST) PCM devices within 250 ps. Hence, this novel electrical setup would be immensely helpful for realizing the ultimate speed limits of various high-speed memory technologies for future computing.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

Science.gov (United States)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Magnetic Shape Memory Alloys as smart materials for micro-positioning devices

Directory of Open Access Journals (Sweden)

A. Hubert

2012-10-01

Full Text Available In the field of microrobotics, actuators based on smart materials are predominant because of very good precision, integration capabilities and high compactness. This paper presents the main characteristics of Magnetic Shape Memory Alloys as new candidates for the design of micromechatronic devices. The thermo-magneto-mechanical energy conversion process is first presented followed by the adequate modeling procedure required to design actuators. Finally, some actuators prototypes realized at the Femto-ST institute are presented, including a push-pull bidirectional actuator. Some results on the control and performances of these devices conclude the paper.

Wearable Intrinsically Soft, Stretchable, Flexible Devices for Memories and Computing.

Science.gov (United States)

Rajan, Krishna; Garofalo, Erik; Chiolerio, Alessandro

2018-01-27

A recent trend in the development of high mass consumption electron devices is towards electronic textiles (e-textiles), smart wearable devices, smart clothes, and flexible or printable electronics. Intrinsically soft, stretchable, flexible, Wearable Memories and Computing devices (WMCs) bring us closer to sci-fi scenarios, where future electronic systems are totally integrated in our everyday outfits and help us in achieving a higher comfort level, interacting for us with other digital devices such as smartphones and domotics, or with analog devices, such as our brain/peripheral nervous system. WMC will enable each of us to contribute to open and big data systems as individual nodes, providing real-time information about physical and environmental parameters (including air pollution monitoring, sound and light pollution, chemical or radioactive fallout alert, network availability, and so on). Furthermore, WMC could be directly connected to human brain and enable extremely fast operation and unprecedented interface complexity, directly mapping the continuous states available to biological systems. This review focuses on recent advances in nanotechnology and materials science and pays particular attention to any result and promising technology to enable intrinsically soft, stretchable, flexible WMC.

Scalability of voltage-controlled filamentary and nanometallic resistance memory devices.

Science.gov (United States)

Lu, Yang; Lee, Jong Ho; Chen, I-Wei

2017-08-31

Much effort has been devoted to device and materials engineering to realize nanoscale resistance random access memory (RRAM) for practical applications, but a rational physical basis to be relied on to design scalable devices spanning many length scales is still lacking. In particular, there is no clear criterion for switching control in those RRAM devices in which resistance changes are limited to localized nanoscale filaments that experience concentrated heat, electric current and field. Here, we demonstrate voltage-controlled resistance switching, always at a constant characteristic critical voltage, for macro and nanodevices in both filamentary RRAM and nanometallic RRAM, and the latter switches uniformly and does not require a forming process. As a result, area-scalability can be achieved under a device-area-proportional current compliance for the low resistance state of the filamentary RRAM, and for both the low and high resistance states of the nanometallic RRAM. This finding will help design area-scalable RRAM at the nanoscale. It also establishes an analogy between RRAM and synapses, in which signal transmission is also voltage-controlled.

Numerical analysis of a polysilicon-based resistive memory device

KAUST Repository

Berco, Dan

2018-03-08

This study investigates a conductive bridge resistive memory device based on a Cu top electrode, 10-nm polysilicon resistive switching layer and a TiN bottom electrode, by numerical analysis for $$10^{3}$$103 programming and erase simulation cycles. The low and high resistive state values in each cycle are calculated, and the analysis shows that the structure has excellent retention reliability properties. The presented Cu species density plot indicates that Cu insertion occurs almost exclusively along grain boundaries resulting in a confined isomorphic conductive filament that maintains its overall shape and electric properties during cycling. The superior reliability of this structure may thus be attributed to the relatively low amount of Cu migrating into the RSL during initial formation. In addition, the results show a good match and help to confirm experimental measurements done over a previously demonstrated device.

Rare-Earth Ions in Niobium-Based Devices as a Quantum Memory: Magneto-Optical Effects on Room Temperature Electrical Transport

Science.gov (United States)

2016-09-01

heterostructure can be used to implement cryogenic memory for superconducting digital computing. Our concept involves embedding rare-earth ions in...rare-earth neodymium by ion implantation in thin films of niobium and niobium-based heterostructure devices. We model the ion implantation process...the films and devices so they can properly designed and optimized for utility as quantum memory. We find that the magnetic field has a strong effect

Systematic Development Strategy for Smart Devices Based on Shape-Memory Polymers

Directory of Open Access Journals (Sweden)

Andrés Díaz Lantada

2017-10-01

Full Text Available Shape-memory polymers are outstanding “smart” materials, which can perform important geometrical changes, when activated by several types of external stimuli, and which can be applied to several emerging engineering fields, from aerospace applications, to the development of biomedical devices. The fact that several shape-memory polymers can be structured in an additive way is an especially noteworthy advantage, as the development of advanced actuators with complex geometries for improved performance can be achieved, if adequate design and manufacturing considerations are taken into consideration. Present study presents a review of challenges and good practices, leading to a straightforward methodology (or integration of strategies, for the development of “smart” actuators based on shape-memory polymers. The combination of computer-aided design, computer-aided engineering and additive manufacturing technologies is analyzed and applied to the complete development of interesting shape-memory polymer-based actuators. Aspects such as geometrical design and optimization, development of the activation system, selection of the adequate materials and related manufacturing technologies, training of the shape-memory effect, final integration and testing are considered, as key processes of the methodology. Current trends, including the use of low-cost 3D and 4D printing, and main challenges, including process eco-efficiency and biocompatibility, are also discussed and their impact on the proposed methodology is considered.

All-polymer bistable resistive memory device based on nanoscale phase-separated PCBM-ferroelectric blends

KAUST Repository

Khan, Yasser; Bhansali, Unnat Sampatraj; Cha, Dong Kyu; Alshareef, Husam N.

2012-01-01

All polymer nonvolatile bistable memory devices are fabricated from blends of ferroelectric poly(vinylidenefluoride-trifluoroethylene (P(VDF-TrFE)) and n-type semiconducting [6,6]-phenyl-C61-butyric acid methyl ester (PCBM). The nanoscale phase

Selected Advances in Nanoelectronic Devices Logic, Memory and RF

CERN Document Server

Joodaki, Mojtaba

2013-01-01

Nanoelectronics, as a true successor of microelectronics, is certainly a major technology boomer in the 21st century. This has been shown by its several applications and also by its enormous potential to influence all areas of electronics, computers, information technology, aerospace defense, and consumer goods. Although the current semiconductor technology is projected to reach its physical limit in about a decade, nanoscience and nanotechnology promise breakthroughs for the future. The present books provides an in-depth review of the latest advances in the technology of nanoelectronic devices and their developments over the past decades. Moreover, it introduces new concepts for the realization of future nanoelectronic devices. The main focus of the book is on three fundamental branches of semiconductor products or applications: logic, memory, and RF and communication. By pointing out to the key technical challenges, important aspects and characteristics of various designs are used to illustrate mechanisms t...

Anisotropic sensor and memory device with a ferromagnetic tunnel barrier as the only magnetic element.

Science.gov (United States)

Lόpez-Mir, L; Frontera, C; Aramberri, H; Bouzehouane, K; Cisneros-Fernández, J; Bozzo, B; Balcells, L; Martínez, B

2018-01-16

Multiple spin functionalities are probed on Pt/La 2 Co 0.8 Mn 1.2 O 6 /Nb:SrTiO 3 , a device composed by a ferromagnetic insulating barrier sandwiched between non-magnetic electrodes. Uniquely, La 2 Co 0.8 Mn 1.2 O 6 thin films present strong perpendicular magnetic anisotropy of magnetocrystalline origin, property of major interest for spintronics. The junction has an estimated spin-filtering efficiency of 99.7% and tunneling anisotropic magnetoresistance (TAMR) values up to 30% at low temperatures. This remarkable angular dependence of the magnetoresistance is associated with the magnetic anisotropy whose origin lies in the large spin-orbit interaction of Co 2+ which is additionally tuned by the strain of the crystal lattice. Furthermore, we found that the junction can operate as an electrically readable magnetic memory device. The findings of this work demonstrate that a single ferromagnetic insulating barrier with strong magnetocrystalline anisotropy is sufficient for realizing sensor and memory functionalities in a tunneling device based on TAMR.

Multistate storage nonvolatile memory device based on ferroelectricity and resistive switching effects of SrBi2Ta2O9 films

Science.gov (United States)

Song, Zhiwei; Li, Gang; Xiong, Ying; Cheng, Chuanpin; Zhang, Wanli; Tang, Minghua; Li, Zheng; He, Jiangheng

2018-05-01

A memory device with a Pt/SrBi2Ta2O9(SBT)/Pt(111) structure was shown to have excellent combined ferroelectricity and resistive switching properties, leading to higher multistate storage memory capacity in contrast to ferroelectric memory devices. In this device, SBT polycrystalline thin films with significant (115) orientation were fabricated on Pt(111)/Ti/SiO2/Si(100) substrates using CVD (chemical vapor deposition) method. Measurement results of the electric properties exhibit reproducible and reliable ferroelectricity switching behavior and bipolar resistive switching effects (BRS) without an electroforming process. The ON/OFF ratio of the resistive switching was found to be about 103. Switching mechanisms for the low resistance state (LRS) and high resistance state (HRS) currents are likely attributed to the Ohmic and space charge-limited current (SCLC) behavior, respectively. Moreover, the ferroelectricity and resistive switching effects were found to be mutually independent, and the four logic states were obtained by controlling the periodic sweeping voltage. This work holds great promise for nonvolatile multistate memory devices with high capacity and low cost.

Novel spintronics devices for memory and logic: prospects and challenges for room temperature all spin computing

Science.gov (United States)

Wang, Jian-Ping

An energy efficient memory and logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new materials and physics. Magnetoresistive based devices have been a promising candidate for future integrated magnetic computation because of its unique non-volatility and functionalities. The application of perpendicular magnetic anisotropy for potential STT-RAM application was demonstrated and later has been intensively investigated by both academia and industry groups, but there is no clear path way how scaling will eventually work for both memory and logic applications. One of main reasons is that there is no demonstrated material stack candidate that could lead to a scaling scheme down to sub 10 nm. Another challenge for the usage of magnetoresistive based devices for logic application is its available switching speed and writing energy. Although a good progress has been made to demonstrate the fast switching of a thermally stable magnetic tunnel junction (MTJ) down to 165 ps, it is still several times slower than its CMOS counterpart. In this talk, I will review the recent progress by my research group and my C-SPIN colleagues, then discuss the opportunities, challenges and some potential path ways for magnetoresitive based devices for memory and logic applications and their integration for room temperature all spin computing system.

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

Directory of Open Access Journals (Sweden)

Oliver Sander

2012-01-01

Full Text Available SRAM-based fingerprinting uses deviations in power-up behaviour caused by the CMOS fabrication process to identify distinct devices. This method is a promising technique for unique identification of physical devices. In the case of SRAM-based hardware reconfigurable devices such as FPGAs, the integrated SRAM cells are often initialized automatically at power-up, sweeping potential identification data. We demonstrate an approach to utilize unused parts of configuration memory space for device identification. Based on a total of over 200,000 measurements on nine Xilinx Virtex-5 FPGAs, we show that the retrieved values have promising properties with respect to consistency on one device, variety between different devices, and stability considering temperature variation and aging.

Parasitic resistive switching uncovered from complementary resistive switching in single active-layer oxide memory device

Science.gov (United States)

Zhu, Lisha; Hu, Wei; Gao, Chao; Guo, Yongcai

2017-12-01

This paper reports the reversible transition processes between the bipolar and complementary resistive switching (CRS) characteristics on the binary metal-oxide resistive memory devices of Pt/HfO x /TiN and Pt/TaO x /TiN by applying the appropriate bias voltages. More interestingly, by controlling the amplitude of the negative bias, the parasitic resistive switching effect exhibiting repeatable switching behavior is uncovered from the CRS behavior. The electrical observation of the parasitic resistive switching effect can be explained by the controlled size of the conductive filament. This work confirms the transformation and interrelationship among the bipolar, parasitic, and CRS effects, and thus provides new insight into the understanding of the physical mechanism of the binary metal-oxide resistive switching memory devices.

Effect of Ag nanoparticles on resistive switching of polyfluorene-based organic non-volatile memory devices

International Nuclear Information System (INIS)

Kim, Tae-Wook; Oh, Seung-Hwan; Choi, Hye-Jung; Wang, Gun-Uk; Kim, Dong-Yu; Hwang, Hyun-Sang; Lee, Tak-Hee

2010-01-01

The effects of Ag nanoparticles on the switching behavior of polyfluorene-based organic nonvolatile memory devices were investigated. Polyfluorene-derivatives (WPF-oxy-F) with and without Ag nanoparticles were synthesized, and the presence of Ag nanoparticles in Ag-WPF-oxy-F was identified by transmission electron microscopy and X-ray photoelectron spectroscopy analyses. The Ag-nanoparticles did not significantly affect the basic switching performances, such as the current-voltage characteristics, the distribution of on/off resistance, and the retention. The pulse switching time of Ag-WPF-oxy-F was faster than that of WPF-oxy-F. Ag-WPF-oxy-F memory devices showed an area dependence in the high resistance state, implying that formation of a Ag metallic channel for current conduction.

Highly scalable 3-D NAND-NOR hybrid-type dual bit per cell flash memory devices with an additional cut-off gate

International Nuclear Information System (INIS)

Cho, Seongjae; Shim, Wonbo; Park, Ilhan; Kim, Yoon; Park, Byunggook

2010-01-01

In this work, a nonvolatile memory (NVM) device of novel structure in 3 dimensions is introduced, and its operation physics is validated. It is based on a pillar structure in which two identical storage nodes are located for dual-bit operation. The two storage nodes on neighboring pillars are controlled by using one common control gate so that the space between silicon pillars can be further reduced. For compatibility with conventional memory operations, an additional cut-off gate is constructed under the common control gate. This is considered as the ultimate form for a 3-D nonvolatile memory device based on a double-gate structure. The underlying physics is explained, and the operational schemes are validated in various aspects by using a numerical device simulation. Also, critical issues in device design for higher reliability are discussed.

Magnetic Resonance Flow Velocity and Temperature Mapping of a Shape Memory Polymer Foam Device

Energy Technology Data Exchange (ETDEWEB)

Small IV, W; Gjersing, E; Herberg, J L; Wilson, T S; Maitland, D J

2008-10-29

Interventional medical devices based on thermally responsive shape memory polymer (SMP) are under development to treat stroke victims. The goals of these catheter-delivered devices include re-establishing blood flow in occluded arteries and preventing aneurysm rupture. Because these devices alter the hemodynamics and dissipate thermal energy during the therapeutic procedure, a first step in the device development process is to investigate fluid velocity and temperature changes following device deployment. A laser-heated SMP foam device was deployed in a simplified in vitro vascular model. Magnetic resonance imaging (MRI) techniques were used to assess the fluid dynamics and thermal changes associated with device deployment. Spatial maps of the steady-state fluid velocity and temperature change inside and outside the laser-heated SMP foam device were acquired. Though non-physiological conditions were used in this initial study, the utility of MRI in the development of a thermally-activated SMP foam device has been demonstrated.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

Science.gov (United States)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

KAUST Repository

Nayak, Pradipta K.

2012-06-22

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin filmtransistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectrictransistors, which is very promising for low-power non-volatile memory applications.

The influence of Ti doping and annealing on Ce{sub 2}Ti{sub 2}O{sub 7} flash memory devices

Energy Technology Data Exchange (ETDEWEB)

Kao, Chyuan Haur [Department of Electronic Engineering, Chang Gung University, No. 259, Wenhua 1st Rd., Guishan Dist., Taoyuan City 33302, Taiwan, ROC (China); Kidney Research Center, Department of Nephrology, Chang Gung Memorial Hospital, Chang Gung University, College of Medicine, Taoyuan, Taiwan, ROC (China); Department of Electronic Engineering, Ming Chi University of Technology, Taiwan, ROC (China); Chen, Su Zhien [Department of Electronic Engineering, Chang Gung University, No. 259, Wenhua 1st Rd., Guishan Dist., Taoyuan City 33302, Taiwan, ROC (China); Kidney Research Center, Department of Nephrology, Chang Gung Memorial Hospital, Chang Gung University, College of Medicine, Taoyuan, Taiwan, ROC (China); Luo, Yang; Chiu, Wang Ting; Chiu, Shih Wei; Chen, I Chien [Department of Applied Materials and Optoelectronic Engineering, National Chi Nan University, No. 1, University Rd., Puli, Nantou Country 54561, Taiwan, ROC (China); Lin, Chan-Yu [Kidney Research Center, Department of Nephrology, Chang Gung Memorial Hospital, Chang Gung University, College of Medicine, Taoyuan, Taiwan, ROC (China); Chen, Hsiang, E-mail: hchen@ncnu.edu.tw [Department of Applied Materials and Optoelectronic Engineering, National Chi Nan University, No. 1, University Rd., Puli, Nantou Country 54561, Taiwan, ROC (China)

2017-02-28

Highlights: • Ce{sub 2}Ti{sub 2}O{sub 7} flash memories have been fabricated. • Material quality can be improved by annealing. • The memory performance can be enhanced by Ti doping. • Ti doping and annealing can reinforce crystallization. - Abstract: In this research, a CeO{sub 2} film with Ti doping was used as a trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type memory devices. Since incorporation of Ti atoms into the film could fix dangling bonds and defects, the Ce{sub 2}Ti{sub 2}O{sub 7} trapping layer with annealing treatment could have a larger memory window and a faster programming/erasing speed. To confirm the origin, multiple material analyses indicate that annealing at an appropriate temperature and Ti doping could enhance crystallization. The Ce{sub 2}Ti{sub 2}O{sub 7}-based memory device is promising for future industrial flash memory applications.

A bio-inspired memory device based on interfacing Physarum polycephalum with an organic semiconductor

Energy Technology Data Exchange (ETDEWEB)

Romeo, Agostino; Dimonte, Alice; Tarabella, Giuseppe; D’Angelo, Pasquale, E-mail: dangelo@imem.cnr.it, E-mail: iannotta@imem.cnr.it; Erokhin, Victor; Iannotta, Salvatore, E-mail: dangelo@imem.cnr.it, E-mail: iannotta@imem.cnr.it [IMEM-CNR, Institute of Materials for Electronics and Magnetism-National Research Council, Parma 43124 (Italy)

2015-01-01

The development of devices able to detect and record ion fluxes is a crucial point in order to understand the mechanisms that regulate communication and life of organisms. Here, we take advantage of the combined electronic and ionic conduction properties of a conducting polymer to develop a hybrid organic/living device with a three-terminal configuration, using the Physarum polycephalum Cell (PPC) slime mould as a living bio-electrolyte. An over-oxidation process induces a conductivity switch in the polymer, due to the ionic flux taking place at the PPC/polymer interface. This behaviour endows a current-depending memory effect to the device.

Nonvolatile organic write-once-read-many-times memory devices based on hexadecafluoro-copper-phthalocyanine

Science.gov (United States)

Wang, Lidan; Su, Zisheng; Wang, Cheng

2012-05-01

Nonvolatile organic write-once-read-many-times memory device was demonstrated based on hexadecafluoro-copper-phthalocyanine (F16CuPc) single layer sandwiched between indium tin oxide (ITO) anode and Al cathode. The as fabricated device remains in ON state and it can be tuned to OFF state by applying a reverse bias. The ON/OFF current ratio of the device can reach up to 2.3 × 103. Simultaneously, the device shows long-term storage stability and long retention time in air. The ON/OFF transition is attributed to the formation and destruction of the interfacial dipole layer in the ITO/F16CuPc interface, and such a mechanism is different from previously reported ones.

Multiferroic Memories

Directory of Open Access Journals (Sweden)

Amritendu Roy

2012-01-01

Full Text Available Multiferroism implies simultaneous presence of more than one ferroic characteristics such as coexistence of ferroelectric and magnetic ordering. This phenomenon has led to the development of various kinds of materials and conceptions of many novel applications such as development of a memory device utilizing the multifunctionality of the multiferroic materials leading to a multistate memory device with electrical writing and nondestructive magnetic reading operations. Though, interdependence of electrical- and magnetic-order parameters makes it difficult to accomplish the above and thus rendering the device to only two switchable states, recent research has shown that such problems can be circumvented by novel device designs such as formation of tunnel junction or by use of exchange bias. In this paper, we review the operational aspects of multiferroic memories as well as the materials used for these applications along with the designs that hold promise for the future memory devices.

Microwave impedance imaging on semiconductor memory devices

Science.gov (United States)

Kundhikanjana, Worasom; Lai, Keji; Yang, Yongliang; Kelly, Michael; Shen, Zhi-Xun

2011-03-01

Microwave impedance microscopy (MIM) maps out the real and imaginary components of the tip-sample impedance, from which the local conductivity and dielectric constant distribution can be derived. The stray field contribution is minimized in our shielded cantilever design, enabling quantitative analysis of nano-materials and device structures. We demonstrate here that the MIM can spatially resolve the conductivity variation in a dynamic random access memory (DRAM) sample. With DC or low-frequency AC bias applied to the tip, contrast between n-doped and p-doped regions in the dC/dV images is observed, and p-n junctions are highlighted in the dR/dV images. The results can be directly compared with data taken by scanning capacitance microscope (SCM), which uses unshielded cantilevers and resonant electronics, and the MIM reveals more information of the local dopant concentration than SCM.

Radiation Damage in Electronic Memory Devices

OpenAIRE

Fetahović, Irfan; Pejović, Milić; Vujisić, Miloš

2013-01-01

This paper investigates the behavior of semiconductor memories exposed to radiation in order to establish their applicability in a radiation environment. The experimental procedure has been used to test radiation hardness of commercial semiconductor memories. Different types of memory chips have been exposed to indirect ionizing radiation by changing radiation dose intensity. The effect of direct ionizing radiation on semiconductor memory behavior has been analyzed by using Monte Carlo simula...

Organic ferroelectric memory devices with inkjet-printed polymer electrodes on flexible substrates

KAUST Repository

Bhansali, Unnat Sampatraj

2013-05-01

Drop-on-demand piezoelectric inkjet-printing technique has been used to fabricate a functional cross-bar array of all-organic ferroelectric memory devices. The polymer-ferroelectric-polymer device consists of a ferroelectric copolymer P(VDF-TrFE) film sandwiched between inkjet-patterned, continuous, orthogonal lines of PEDOT:PSS polymer as the bottom and top electrodes. These devices exhibit well-saturated hysteresis curves with a maximum remnant polarization (Pr) = 6.7 μC/cm2, coercive field (E c) = 55 MV/m and a peak capacitance density of 45 nF/cm2. Our polarization fatigue measurements show that these devices retain ∼100% and 45% of their initial Pr values after 103 and 10 5 stress cycles, respectively. The overall performance and polarization retention characteristics of these ferroelectric capacitors with inkjet-printed polymer electrodes are comparable to metal and spin-cast polymer electrodes suggesting their potential use in large-area flexible electronics. © 2013 Elsevier Ltd. All rights reserved.

The future of memory

Science.gov (United States)

Marinella, M.

In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

Management of long-term and reversible hysteroscopic sterilization: a novel device with nickel-titanium shape memory alloy

Science.gov (United States)

2014-01-01

Background Female sterilization is the second most commonly used method of contraception in the United States. Female sterilization can now be performed through laparoscopic, abdominal, or hysteroscopic approaches. The hysteroscopic sterilization may be a safer option than sterilization through laparoscopy or laparotomy because it avoids invading the abdominal cavity and undergoing general anaesthesia. Hysteroscopic sterilization mainly includes chemical agents and mechanical devices. Common issues related to the toxicity of the chemical agents used have raised concerns regarding this kind of contraception. The difficulty of the transcervical insertion of such mechanical devices into the fallopian tubes has increased the high incidence of device displacement or dislodgment. At present, Essure® is the only commercially available hysteroscopic sterilization device being used clinically. The system is irreversible and is not effective immediately. Presentation of the hypothesis Our new hysteroscopic sterility system consists of nickel-titanium (NiTi) shape memory alloy and a waterproof membrane. The NiTi alloy is covered with two coatings to avoid toxic Ni release and to prevent stimulation of epithelial tissue growth around the oviducts. Because of the shape memory effect of the NiTi alloy, the device works like an umbrella: it stays collapsed at low temperature before placement and opens by the force of shape memory activated by the body temperature after it is inserted hysteroscopically into the interstitial tubal lumen. The rim of the open device will incise into interstitial myometrium during the process of unfolding. Once the device is fixed, it blocks the tube completely. When the patient no longer wishes for sterilization, the device can be closed by perfusing liquid with low temperature into the uterine cavity, followed by prospective hysteroscopic removal. After the device removal, the fallopian tube will revert to its physiological functions. Testing the

Organic nonvolatile resistive memory devices based on thermally deposited Au nanoparticle

Science.gov (United States)

Jin, Zhiwen; Liu, Guo; Wang, Jizheng

2013-05-01

Uniform Au nanoparticles (NPs) are formed by thermally depositing nominal 2-nm thick Au film on a 10-nm thick polyimide film formed on a Al electrode, and then covered by a thin polymer semiconductor film, which acts as an energy barrier for electrons to be injected from the other Al electrode (on top of polymer film) into the Au NPs, which are energetically electron traps in such a resistive random access memory (RRAM) device. The Au NPs based RRAM device exhibits estimated retention time of 104 s, cycle times of more than 100, and ON-OFF ratio of 102 to 103. The carrier transport properties are also analyzed by fitting the measured I-V curves with several conduction models.

Transparent and flexible write-once-read-many (WORM) memory device based on egg albumen

International Nuclear Information System (INIS)

Qu, Bo; Lin, Qianru; Wan, Tao; Du, Haiwei; Chen, Nan; Lin, Xi; Chu, Dewei

2017-01-01

Egg albumen, as an important protein resource in nature, is an interesting dielectric material exhibiting many fascinating properties for the development of environmentally friendly electronic devices. Taking advantage of their extraordinary transparency and flexibility, this paper presents an innovative preparation approach for albumen thin film based write-once-read-many-times (WORM) memory devices in a simple, cost-effective manner. The fabricated device shows superior data retention properties including non-volatile character (over 10 5 s) and promising great read durability (10 6 times). Furthermore, our results suggested that the electric-field-induced trap-controlled space charge limited current (SCLC) conduction is responsible for the observed resistance switching effect. The present study may likely reveal another pathway towards complete see-through electrical devices. (paper)

Transparent and flexible write-once-read-many (WORM) memory device based on egg albumen

Science.gov (United States)

Qu, Bo; Lin, Qianru; Wan, Tao; Du, Haiwei; Chen, Nan; Lin, Xi; Chu, Dewei

2017-08-01

Egg albumen, as an important protein resource in nature, is an interesting dielectric material exhibiting many fascinating properties for the development of environmentally friendly electronic devices. Taking advantage of their extraordinary transparency and flexibility, this paper presents an innovative preparation approach for albumen thin film based write-once-read-many-times (WORM) memory devices in a simple, cost-effective manner. The fabricated device shows superior data retention properties including non-volatile character (over 105 s) and promising great read durability (106 times). Furthermore, our results suggested that the electric-field-induced trap-controlled space charge limited current (SCLC) conduction is responsible for the observed resistance switching effect. The present study may likely reveal another pathway towards complete see-through electrical devices.

A bio-inspired memory device based on interfacing Physarum polycephalum with an organic semiconductor

Directory of Open Access Journals (Sweden)

Agostino Romeo

2015-01-01

Full Text Available The development of devices able to detect and record ion fluxes is a crucial point in order to understand the mechanisms that regulate communication and life of organisms. Here, we take advantage of the combined electronic and ionic conduction properties of a conducting polymer to develop a hybrid organic/living device with a three-terminal configuration, using the Physarum polycephalum Cell (PPC slime mould as a living bio-electrolyte. An over-oxidation process induces a conductivity switch in the polymer, due to the ionic flux taking place at the PPC/polymer interface. This behaviour endows a current-depending memory effect to the device.

Resistive switching effect in the planar structure of all-printed, flexible and rewritable memory device based on advanced 2D nanocomposite of graphene quantum dots and white graphene flakes

International Nuclear Information System (INIS)

Rehman, Muhammad Muqeet; Siddiqui, Ghayas Uddin; Kim, Sowon; Choi, Kyung Hyun

2017-01-01

Pursuit of the most appropriate materials and fabrication methods is essential for developing a reliable, rewritable and flexible memory device. In this study, we have proposed an advanced 2D nanocomposite of white graphene (hBN) flakes embedded with graphene quantum dots (GQDs) as the functional layer of a flexible memory device owing to their unique electrical, chemical and mechanical properties. Unlike the typical sandwich type structure of a memory device, we developed a cost effective planar structure, to simplify device fabrication and prevent sneak current. The entire device fabrication was carried out using printing technology followed by encapsulation in an atomically thin layer of aluminum oxide (Al 2 O 3 ) for protection against environmental humidity. The proposed memory device exhibited attractive bipolar switching characteristics of high switching ratio, large electrical endurance and enhanced lifetime, without any crosstalk between adjacent memory cells. The as-fabricated device showed excellent durability for several bending cycles at various bending diameters without any degradation in bistable resistive states. The memory mechanism was deduced to be conductive filamentary; this was validated by illustrating the temperature dependence of bistable resistive states. Our obtained results pave the way for the execution of promising 2D material based next generation flexible and non-volatile memory (NVM) applications. (paper)

Impact of AlO x layer on resistive switching characteristics and device-to-device uniformity of bilayered HfO x -based resistive random access memory devices

Science.gov (United States)

Chuang, Kai-Chi; Chung, Hao-Tung; Chu, Chi-Yan; Luo, Jun-Dao; Li, Wei-Shuo; Li, Yi-Shao; Cheng, Huang-Chung

2018-06-01

An AlO x layer was deposited on HfO x , and bilayered dielectric films were found to confine the formation locations of conductive filaments (CFs) during the forming process and then improve device-to-device uniformity. In addition, the Ti interposing layer was also adopted to facilitate the formation of oxygen vacancies. As a result, the resistive random access memory (RRAM) device with TiN/Ti/AlO x (1 nm)/HfO x (6 nm)/TiN stack layers demonstrated excellent device-to-device uniformity although it achieved slightly larger resistive switching characteristics, which were forming voltage (V Forming) of 2.08 V, set voltage (V Set) of 1.96 V, and reset voltage (V Reset) of ‑1.02 V, than the device with TiN/Ti/HfO x (6 nm)/TiN stack layers. However, the device with a thicker 2-nm-thick AlO x layer showed worse uniformity than the 1-nm-thick one. It was attributed to the increased oxygen atomic percentage in the bilayered dielectric films of the 2-nm-thick one. The difference in oxygen content showed that there would be less oxygen vacancies to form CFs. Therefore, the random growth of CFs would become severe and the device-to-device uniformity would degrade.

Radiation Damage in Electronic Memory Devices

Directory of Open Access Journals (Sweden)

Irfan Fetahović

2013-01-01

Full Text Available This paper investigates the behavior of semiconductor memories exposed to radiation in order to establish their applicability in a radiation environment. The experimental procedure has been used to test radiation hardness of commercial semiconductor memories. Different types of memory chips have been exposed to indirect ionizing radiation by changing radiation dose intensity. The effect of direct ionizing radiation on semiconductor memory behavior has been analyzed by using Monte Carlo simulation method. Obtained results show that gamma radiation causes decrease in threshold voltage, being proportional to the absorbed dose of radiation. Monte Carlo simulations of radiation interaction with material proved to be significant and can be a good estimation tool in probing semiconductor memory behavior in radiation environment.

Memory hierarchy using row-based compression

Science.gov (United States)

Loh, Gabriel H.; O'Connor, James M.

2016-10-25

A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

Influence of Thermal Annealing Treatment on Bipolar Switching Properties of Vanadium Oxide Thin-Film Resistance Random-Access Memory Devices

Science.gov (United States)

Chen, Kai-Huang; Cheng, Chien-Min; Kao, Ming-Cheng; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Wu, Sean; Su, Feng-Yi

2017-04-01

The bipolar switching properties and electrical conduction mechanism of vanadium oxide thin-film resistive random-access memory (RRAM) devices obtained using a rapid thermal annealing (RTA) process have been investigated in high-resistive status/low-resistive status (HRS/LRS) and are discussed herein. In addition, the resistance switching properties and quality improvement of the vanadium oxide thin-film RRAM devices were measured by x-ray diffraction (XRD) analysis, x-ray photoelectron spectrometry (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM), and current-voltage ( I- V) measurements. The activation energy of the hopping conduction mechanism in the devices was investigated based on Arrhenius plots in HRS and LRS. The hopping conduction distance and activation energy barrier were obtained as 12 nm and 45 meV, respectively. The thermal annealing process is recognized as a candidate method for fabrication of thin-film RRAM devices, being compatible with integrated circuit technology for nonvolatile memory devices.

WORM memory devices based on conformation change of a PVK derivative with a rigid spacer in side chain

International Nuclear Information System (INIS)

Liu Yuanhua; Li Najun; Xia Xuewei; Xu Qingfeng; Ge Jianfeng; Lu Jianmei

2010-01-01

A nonvolatile write-once-read-many-times (WORM) memory device based on poly((4-vinylbenzyl)-9H-carbazole) (PVCz) was fabricated by a simple and conventional process. The as-fabricated device was found to be at its OFF state and could be programmed irreversibly to the ON state with a low transition voltage of -1.7 V. The device exhibits a high ON/OFF current ratio of up to 10 6 , high stability in retention time up to 8 h and number of read cycles up to 10 8 under a read voltage of -1.0 V in both ON and OFF states. The results of X-ray diffraction (XRD) and fluorescence emission spectra in different states of PVCz indicate that the electrical bistable phenomenon is caused by the voltage-induced conformation change of the pendant carbazole groups. With high performance, low power consumption and low production cost, the device fabricated with PVCz has a potential application for nonvolatile memory.

Study of nanoimprint lithography (NIL) for HVM of memory devices

Science.gov (United States)

Kono, Takuya; Hatano, Masayuki; Tokue, Hiroshi; Kobayashi, Kei; Suzuki, Masato; Fukuhara, Kazuya; Asano, Masafumi; Nakasugi, Tetsuro; Choi, Eun Hyuk; Jung, Wooyung

2017-03-01

A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.

Chemical insight into origin of forming-free resistive random-access memory devices

KAUST Repository

Wu, X.

2011-09-29

We demonstrate the realization of a forming-step free resistive random access memory (RRAM) device using a HfOx/TiOx/HfOx/TiOxmultilayer structure, as a replacement for the conventional HfOx-based single layer structure. High-resolution transmission electron microscopy (HRTEM), along with electron energy loss spectroscopy(EELS)analysis has been carried out to identify the distribution and the role played by Ti in the RRAM stack. Our results show that Ti out-diffusion into the HfOx layer is the chemical cause of forming-free behavior. Moreover, the capability of Ti to change its ionic state in HfOx eases the reduction-oxidation (redox) reaction, thus lead to the RRAM devices performance improvements.

Electrical switching and memory phenomena observed in redox-gradient dendrimer sandwich devices

OpenAIRE

Li, JianChang; Blackstock, Silas C.; Szulczewski, Greg J.

2005-01-01

We report on the fabrication of dendrimer sandwich devices with electrical switching and memory properties. The storage media is consisted of a redox-gradient dendrimer layer sandwiched in organic barrier thin films. The dendrimer layer acts as potential well where redox-state changes and consequent electrical transitions of the embedded dendrimer molecules are expected to be effectively triggered and retained, respectively. Experimental results indicated that electrical switching could be re...

Nanoscale observations of the operational failure for phase-change-type nonvolatile memory devices using Ge2Sb2Te5 chalcogenide thin films

International Nuclear Information System (INIS)

Yoon, Sung-Min; Choi, Kyu-Jeong; Lee, Nam-Yeal; Lee, Seung-Yun; Park, Young-Sam; Yu, Byoung-Gon

2007-01-01

In this study, a phase-change memory device was fabricated and the origin of device failure mode was examined using transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS). Ge 2 Sb 2 Te 5 (GST) was used as the active phase-change material in the memory device and the active pore size was designed to be 0.5 μm. After the programming signals of more than 2x10 6 cycles were repeatedly applied to the device, the high-resistance memory state (reset) could not be rewritten and the cell resistance was fixed at the low-resistance state (set). Based on TEM and EDS studies, Sb excess and Ge deficiency in the device operating region had a strong effect on device reliability, especially under endurance-demanding conditions. An abnormal segregation and oxidation of Ge also was observed in the region between the device operating and inactive peripheral regions. To guarantee an data endurability of more than 1x10 10 cycles of PRAM, it is very important to develop phase-change materials with more stable compositions and to reduce the current required for programming

Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

International Nuclear Information System (INIS)

Son, Dang Ngoc; Van Duy, Nguyen; Jung, Sungwook; Yi, Junsin

2010-01-01

Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiN x films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application

Electrostatically telescoping nanotube nonvolatile memory device

International Nuclear Information System (INIS)

Kang, Jeong Won; Jiang Qing

2007-01-01

We propose a nonvolatile memory based on carbon nanotubes (CNTs) serving as the key building blocks for molecular-scale computers and investigate the dynamic operations of a double-walled CNT memory element by classical molecular dynamics simulations. The localized potential energy wells achieved from both the interwall van der Waals energy and CNT-metal binding energy make the bistability of the CNT positions and the electrostatic attractive forces induced by the voltage differences lead to the reversibility of this CNT memory. The material for the electrodes should be carefully chosen to achieve the nonvolatility of this memory. The kinetic energy of the CNT shuttle experiences several rebounds induced by the collisions of the CNT onto the metal electrodes, and this is critically important to the performance of such an electrostatically telescoping CNT memory because the collision time is sufficiently long to cause a delay of the state transition

Role of potential fluctuations in phase-change GST memory devices

Energy Technology Data Exchange (ETDEWEB)

Agarwal, Satish C. [Department of Physics, Indian Institute of Technology, Kanpur 208016 (India)

2012-10-15

The long range potential fluctuations (LRPFs) arising from the defects and heterogeneities in disordered semiconductors are important for understanding their atomic and electronic properties. Here, they are measured in Ge{sub X}Sb{sub Y}Te{sub 1-X-Y} (GST) chalcogenide glasses used in rewritable phase change memory (PCM) devices. It is found that the most commonly used composition Ge{sub 2}Sb{sub 2}Te{sub 5} has the smallest LRPF amongst its nearby compositions. This finding may be useful in the search for better PCM materials. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

The effectiveness of music as a mnemonic device on recognition memory for people with multiple sclerosis.

Science.gov (United States)

Moore, Kimberly Sena; Peterson, David A; O'Shea, Geoffrey; McIntosh, Gerald C; Thaut, Michael H

2008-01-01

Research shows that people with multiple sclerosis exhibit learning and memory difficulties and that music can be used successfully as a mnemonic device to aid in learning and memory. However, there is currently no research investigating the effectiveness of music mnemonics as a compensatory learning strategy for people with multiple sclerosis. Participants with clinically definitive multiple sclerosis (N = 38) were given a verbal learning and memory test. Results from a recognition memory task were analyzed that compared learning through music (n = 20) versus learning through speech (n = 18). Preliminary baseline neuropsychological data were collected that measured executive functioning skills, learning and memory abilities, sustained attention, and level of disability. An independent samples t test showed no significant difference between groups on baseline neuropsychological functioning or on recognition task measures. Correlation analyses suggest that music mnemonics may facilitate learning for people who are less impaired by the disease. Implications for future research are discussed.

PIYAS-Proceeding to Intelligent Service Oriented Memory Allocation for Flash Based Data Centric Sensor Devices in Wireless Sensor Networks

Directory of Open Access Journals (Sweden)

Sanam Shahla Rizvi

2009-12-01

Full Text Available Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS. This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

Science.gov (United States)

Rizvi, Sanam Shahla; Chung, Tae-Sun

2010-01-01

Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

Preparation and characterization of Sb2Se3 devices for memory applications

Science.gov (United States)

Shylashree, N.; Uma B., V.; Dhanush, S.; Abachi, Sagar; Nisarga, A.; Aashith, K.; Sangeetha B., G.

2018-05-01

In this paper, A phase change material of Sb2Se3 was proposed for non volatile memory application. The thin film device preparation and characterization were carried out. The deposition method used was vapor evaporation technique and a thickness of 180nm was deposited. The switching between the SET and RESET state is shown by the I-V characterization. The change of phase was studied using R-V characterization. Different fundamental modes were also identified using Raman spectroscopy.

Enhanced oxygen vacancy diffusion in Ta2O5 resistive memory devices due to infinitely adaptive crystal structure

Science.gov (United States)

Jiang, Hao; Stewart, Derek A.

2016-04-01

Metal oxide resistive memory devices based on Ta2O5 have demonstrated high switching speed, long endurance, and low set voltage. However, the physical origin of this improved performance is still unclear. Ta2O5 is an important archetype of a class of materials that possess an adaptive crystal structure that can respond easily to the presence of defects. Using first principles nudged elastic band calculations, we show that this adaptive crystal structure leads to low energy barriers for in-plane diffusion of oxygen vacancies in λ phase Ta2O5. Identified diffusion paths are associated with collective motion of neighboring atoms. The overall vacancy diffusion is anisotropic with higher diffusion barriers found for oxygen vacancy movement between Ta-O planes. Coupled with the fact that oxygen vacancy formation energy in Ta2O5 is relatively small, our calculated low diffusion barriers can help explain the low set voltage in Ta2O5 based resistive memory devices. Our work shows that other oxides with adaptive crystal structures could serve as potential candidates for resistive random access memory devices. We also discuss some general characteristics for ideal resistive RAM oxides that could be used in future computational material searches.

Fabrication of ultrahigh density metal-cell-metal crossbar memory devices with only two cycles of lithography and dry-etch procedures

KAUST Repository

Zong, Baoyu; Goh, J. Y.; Guo, Zaibing; Luo, Ping; Wang, Chenchen; Qiu, Jinjun; Ho, Pin; Chen, Yunjie; Zhang, Mingsheng; Han, Guchang

2013-01-01

A novel approach to the fabrication of metal-cell-metal trilayer memory devices was demonstrated by using only two cycles of lithography and dry-etch procedures. The fabricated ultrahigh density crossbar devices can be scaled down to ≤70 nm in half

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

KAUST Repository

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, Husam N.

2012-01-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

Directory of Open Access Journals (Sweden)

Shojan P. Pavunny

2014-03-01

Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

Energy Technology Data Exchange (ETDEWEB)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P. [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Chakraborty, S. [Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064 (India); Mukherjee, Rabibrata [Department of Chemical Engineering, Indian Institute of Technology, Kharagpur 721302 (India)

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

Application of phase-change materials in memory taxonomy.

Science.gov (United States)

Wang, Lei; Tu, Liang; Wen, Jing

2017-01-01

Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects.

All-printed paper memory

KAUST Repository

Lien, Derhsien

2014-08-26

We report the memory device on paper by means of an all-printing approach. Using a sequence of inkjet and screen-printing techniques, a simple metal-insulator-metal device structure is fabricated on paper as a resistive random access memory with a potential to reach gigabyte capacities on an A4 paper. The printed-paper-based memory devices (PPMDs) exhibit reproducible switching endurance, reliable retention, tunable memory window, and the capability to operate under extreme bending conditions. In addition, the PBMD can be labeled on electronics or living objects for multifunctional, wearable, on-skin, and biocompatible applications. The disposability and the high-security data storage of the paper-based memory are also demonstrated to show the ease of data handling, which are not achievable for regular silicon-based electronic devices. We envision that the PPMDs manufactured by this cost-effective and time-efficient all-printing approach would be a key electronic component to fully activate a paper-based circuit and can be directly implemented in medical biosensors, multifunctional devices, and self-powered systems. © 2014 American Chemical Society.

Self-formed conductive nanofilaments in (Bi, Mn)Ox for ultralow-power memory devices

KAUST Repository

Kang, Chen Fang

2015-04-01

Resistive random access memory (RRAM) is one of the most promising candidates as a next generation nonvolatile memory (NVM), owing to its superior scalability, low power consumption and high speed. From the materials science point of view, to explore optimal RRAM materials is still essential for practical application. In this work, a new material (Bi, Mn)Ox (BMO) is investigated and several key performance characteristics of Pt/BMO/Pt structured device, including switching performance, retention and endurance, are examined in details. Furthermore, it has been confirmed by high-resolution transmission electron microscopy that the underlying switching mechanism is attributed to formation and disruption of metallic conducting nanofilaments (CNFs). More importantly, the power dissipation for each CNF is as low as 3.8/20fJ for set/reset process, and a realization of cross-bar structure memory cell is demonstrated to prove the downscaling ability of proposed RRAM. These distinctive properties have important implications for understanding switching mechanisms and implementing ultralow power-dissipation RRAM based on BMO. •Self-formed conductive nanofilaments in BMO show ultralow-power memory feature.•The feature of 10nm in diameter and an average 20-30nm spacing of CNFs suggests the compatibility with the current CMOS technologies.•Power dissipation for each CNF is as low as 3.8/20fJ for set/reset process•A realization of cross-bar structure memory cell is demonstrated to prove the downscaling ability of proposed RRAM. © 2015 Elsevier Ltd.

Short-term memory to long-term memory transition in a nanoscale memristor.

Science.gov (United States)

Chang, Ting; Jo, Sung-Hyun; Lu, Wei

2011-09-27

"Memory" is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses (i.e., the stimulation rate) plays a crucial role in determining the effectiveness of the transition. The memory enhancement and transition of the memristor device was explained from the microscopic picture of impurity redistribution and can be qualitatively described by the same equations governing biological memories. © 2011 American Chemical Society

MBE-grown Si and Si1−xGex quantum dots embedded within epitaxial Gd2O3 on Si(111) substrate for floating gate memory device

International Nuclear Information System (INIS)

Manna, S; Aluguri, R; Katiyar, A; Ray, S K; Das, S; Laha, A; Osten, H J

2013-01-01

Si and Si 1−x Ge x quantum dots embedded within epitaxial Gd 2 O 3 grown by molecular beam epitaxy have been studied for application in floating gate memory devices. The effect of interface traps and the role of quantum dots on the memory properties have been studied using frequency-dependent capacitance–voltage and conductance–voltage measurements. Multilayer quantum dot memory comprising four and five layers of Si quantum dots exhibits a superior memory window to that of single-layer quantum dot memory devices. It has also been observed that single-layer Si 1−x Ge x quantum dots show better memory characteristics than single-layer Si quantum dots. (paper)

Control rod selecting and driving device

International Nuclear Information System (INIS)

Isobe, Hideo.

1981-01-01

Purpose: To simultaneously drive a predetermined number of control rods in a predetermined mode by the control of addresses for predetermined number of control rods and read or write of driving codified data to and from the memory by way of a memory controller. Constitution: The system comprises a control rod information selection device for selecting predetermined control rods from a plurality of control rods disposed in a reactor and outputting information for driving them in a predetermined mode, a control rod information output device for codifying the information outputted from the above device and outputting the addresses to the predetermined control rods and driving mode coded data, and a driving device for driving said predetermined control rods in a predetermined mode in accordance with the codified data outputted from the above device, said control rod infromation output device comprising a memory device capable of storing a predetermined number of the codified data and a memory control device for storing the predetermined number of data into the above memory device at a predetermined timing while successively outputting the thus stored predetermined number of data at a predetermined timing. (Seki, T.)

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures

Science.gov (United States)

Lee, Myoung-Jae; Lee, Chang Bum; Lee, Dongsoo; Lee, Seung Ryul; Chang, Man; Hur, Ji Hyun; Kim, Young-Bae; Kim, Chang-Jung; Seo, David H.; Seo, Sunae; Chung, U.-In; Yoo, In-Kyeong; Kim, Kinam

2011-08-01

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Organic ferroelectric opto-electronic memories

NARCIS (Netherlands)

Asadi, K.; Li, M.; Blom, P.W.M.; Kemerink, M.; Leeuw, D.M. de

2011-01-01

Memory is a prerequisite for many electronic devices. Organic non-volatile memory devices based on ferroelectricity are a promising approach towards the development of a low-cost memory technology based on a simple cross-bar array. In this review article we discuss the latest developments in this

In-chip optical CD measurements for non-volatile memory devices

Science.gov (United States)

Vasconi, Mauro; Kremer, Stephanie; Polli, M.; Severgnini, Ermes; Trovati, Silvia S.

2006-03-01

A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks, mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight of the overall lithographic process window and a quantitative method to evaluate process equipment performance along time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered layers in terms of designed CD, pitch, stack and orientation.

Organic bistable light-emitting devices

Science.gov (United States)

Ma, Liping; Liu, Jie; Pyo, Seungmoon; Yang, Yang

2002-01-01

An organic bistable device, with a unique trilayer structure consisting of organic/metal/organic sandwiched between two outmost metal electrodes, has been invented. [Y. Yang, L. P. Ma, and J. Liu, U.S. Patent Pending, U.S. 01/17206 (2001)]. When the device is biased with voltages beyond a critical value (for example 3 V), the device suddenly switches from a high-impedance state to a low-impedance state, with a difference in injection current of more than 6 orders of magnitude. When the device is switched to the low-impedance state, it remains in that state even when the power is off. (This is called "nonvolatile" phenomenon in memory devices.) The high-impedance state can be recovered by applying a reverse bias; therefore, this bistable device is ideal for memory applications. In order to increase the data read-out rate of this type of memory device, a regular polymer light-emitting diode has been integrated with the organic bistable device, such that it can be read out optically. These features make the organic bistable light-emitting device a promising candidate for several applications, such as digital memories, opto-electronic books, and recordable papers.

Transparent and flexible resistive switching memory devices with a very high ON/OFF ratio using gold nanoparticles embedded in a silk protein matrix

Science.gov (United States)

Gogurla, Narendar; Mondal, Suvra P.; Sinha, Arun K.; Katiyar, Ajit K.; Banerjee, Writam; Kundu, Subhas C.; Ray, Samit K.

2013-08-01

The growing demand for biomaterials for electrical and optical devices is motivated by the need to make building blocks for the next generation of printable bio-electronic devices. In this study, transparent and flexible resistive memory devices with a very high ON/OFF ratio incorporating gold nanoparticles into the Bombyx mori silk protein fibroin biopolymer are demonstrated. The novel electronic memory effect is based on filamentary switching, which leads to the occurrence of bistable states with an ON/OFF ratio larger than six orders of magnitude. The mechanism of this process is attributed to the formation of conductive filaments through silk fibroin and gold nanoparticles in the nanocomposite. The proposed hybrid bio-inorganic devices show promise for use in future flexible and transparent nanoelectronic systems.

Transparent and flexible resistive switching memory devices with a very high ON/OFF ratio using gold nanoparticles embedded in a silk protein matrix

International Nuclear Information System (INIS)

Gogurla, Narendar; Mondal, Suvra P; Sinha, Arun K; Katiyar, Ajit K; Banerjee, Writam; Ray, Samit K; Kundu, Subhas C

2013-01-01

The growing demand for biomaterials for electrical and optical devices is motivated by the need to make building blocks for the next generation of printable bio-electronic devices. In this study, transparent and flexible resistive memory devices with a very high ON/OFF ratio incorporating gold nanoparticles into the Bombyx mori silk protein fibroin biopolymer are demonstrated. The novel electronic memory effect is based on filamentary switching, which leads to the occurrence of bistable states with an ON/OFF ratio larger than six orders of magnitude. The mechanism of this process is attributed to the formation of conductive filaments through silk fibroin and gold nanoparticles in the nanocomposite. The proposed hybrid bio-inorganic devices show promise for use in future flexible and transparent nanoelectronic systems. (paper)

Nanoscale chemical state analysis of resistance random access memory device reacting with Ti

Science.gov (United States)

Shima, Hisashi; Nakano, Takashi; Akinaga, Hiro

2010-05-01

The thermal stability of the resistance random access memory material in the reducing atmosphere at the elevated temperature was improved by the addition of Ti. The unipolar resistance switching before and after the postdeposition annealing (PDA) process at 400 °C was confirmed in Pt/CoO/Ti(5 nm)/Pt device, while the severe degradation of the initial resistance occurs in the Pt/CoO/Pt and Pt/CoO/Ti(50 nm)/Pt devices. By investigating the chemical bonding states of Co, O, and Ti using electron energy loss spectroscopy combined with transmission electron microscopy, it was revealed that excess Ti induces the formation of metallic Co, while the thermal stability was improved by trace Ti. Moreover, it was indicated that the filamentary conduction path can be thermally induced after PDA in the oxide layer by analyzing electrical properties of the degraded devices. The adjustment of the reducing elements is quite essential in order to participate in their profits.

Accessing memory

Science.gov (United States)

Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganthan, Parthasarathy

2017-09-26

A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

Finite temperature simulation studies of spin-flop magnetic random access memory devices

International Nuclear Information System (INIS)

Chui, S.T.; Chang, C.-R.

2006-01-01

Spin-flop structures are currently being developed for magnetic random access memory devices. We report simulation studies of this system. We found the switching involves an intermediate edge-pinned domain state, similar to that observed in the single layer case. This switching scenario is quite different from that based on the coherent rotation picture. A significant temperature dependence of the switching field is observed. Our result suggests that the interplane coupling and thus the switching field has to be above a finite threshold for the spin-flop switching to be better than conventional switching methods

All-printed paper memory

KAUST Repository

He, Jr-Hau; Lin, Chun-Ho; Lien, Der-Hsien

2016-01-01

All-printed paper-based substrate memory devices are described. In an embodiment, a paper-based memory device is prepared by coating one or more areas of a paper substrate with a conductor material such as a carbon paste, to form a first electrode

All-printed paper memory

KAUST Repository

He, Jr-Hau

2016-08-11

All-printed paper-based substrate memory devices are described. In an embodiment, a paper-based memory device is prepared by coating one or more areas of a paper substrate with a conductor material such as a carbon paste, to form a first electrode of a memory, depositing a layer of insulator material, such as titanium dioxide, over one or more areas of the conductor material, and depositing a layer of metal over one or more areas of the insulator material to form a second electrode of the memory. In an embodiment, the device can further include diodes printed between the insulator material and the second electrode, and the first electrode and the second electrodes can be formed as a crossbar structure to provide a WORM memory. The various layers and the diodes can be printed onto the paper substrate by, for example, an ink jet printer.

Josephson Thermal Memory

Science.gov (United States)

Guarcello, Claudio; Solinas, Paolo; Braggio, Alessandro; Di Ventra, Massimiliano; Giazotto, Francesco

2018-01-01

We propose a superconducting thermal memory device that exploits the thermal hysteresis in a flux-controlled temperature-biased superconducting quantum-interference device (SQUID). This system reveals a flux-controllable temperature bistability, which can be used to define two well-distinguishable thermal logic states. We discuss a suitable writing-reading procedure for these memory states. The time of the memory writing operation is expected to be on the order of approximately 0.2 ns for a Nb-based SQUID in thermal contact with a phonon bath at 4.2 K. We suggest a noninvasive readout scheme for the memory states based on the measurement of the effective resonance frequency of a tank circuit inductively coupled to the SQUID. The proposed device paves the way for a practical implementation of thermal logic and computation. The advantage of this proposal is that it represents also an example of harvesting thermal energy in superconducting circuits.

System and method for programmable bank selection for banked memory subsystems

Energy Technology Data Exchange (ETDEWEB)

Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton on Hudson, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E. (Irvington, NY); Hoenicke, Dirk (Seebruck-Seeon, DE); Ohmacht, Martin (Yorktown Heights, NY); Salapura, Valentina (Chappaqua, NY); Sugavanam, Krishnan (Mahopac, NY)

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Exponential increase in the on-off ratio of conductance in organic memory devices by controlling the surface morphology of the devices

Science.gov (United States)

Vyas, Giriraj; Dagar, Parveen; Sahu, Satyajit

2018-05-01

We have shown an exponential increase in the ratio of conductance in the on and off states of switching devices by controlling the surface morphology of the thin films for the device by depositing at different rotational speeds. The pinholes which are preferred topography on the surface at higher rotational speed give rise to higher on-off ratio of current from the devices fabricated at the speed. The lower rotational speed contributes to higher thickness of the film and hence no switching. For thicker films, the domain is formed due to phase segregation between the two components in the film, which also indicates that the film is far from thermal equilibrium. At higher speed, there is very little scope of segregation when the film is drying up. Hence, there are only few pinholes on the surface of the film which are shallow. So, the filamentary mechanism of switching in memory devices can be firmly established by varying the speed of thin film deposition which leads to phase segregation of the materials. Thus, the formation of filament can be regulated by controlling the thickness and the surface morphology.

Single-event phenomena on recent semiconductor devices. Charge-type multiple-bit upsets in high integrated memories

International Nuclear Information System (INIS)

Makihara, Akiko; Shindou, Hiroyuki; Nemoto, Norio; Kuboyama, Satoshi; Matsuda, Sumio; Ohshima, Takeshi; Hirao, Toshio; Itoh, Hisayoshi

2001-01-01

High integrated memories are used in solid state data recorder (SSDR) of the satellite for accumulating observation data. Single event upset phenomena which turn over an accumulated data in the memory cells are caused by heavy ion incidence. Studies on single-bit upset and multiple-bit upset phenomena in the high integrated memory cells are in progress recently. 16 Mbit DRAM (Dynamic Random Access Memories) and 64 Mbit DRAM are irradiated by heavy ion species, such as iodine, bromine and nickel, in comparison with the irradiation damage in the cosmic environment. Data written on the memory devices are read out after the irradiation. The memory cells in three kinds of states, all of charged state, all of discharged state, and an alternative state of charge and discharge, are irradiated for sorting out error modes caused by heavy ion incidence. The soft error in a single memory cells is known as a turn over from charged state to discharged state. Electrons in electron-hole pair generated by heavy ion incidence are captured in a diffusion region between capacitor electrodes of semiconductor. The charged states in the capacitor electrodes before the irradiation are neutralized and changed to the discharged states. According to high integration of the memories, many of the cells are affected by a single ion incidence. The multiple-bit upsets, however, are generated in the memory cells of discharged state before the irradiation, also. The charge-type multiple-bit upsets is considered as that error data are written on the DRAM during refresh cycle of a sense-up circuit and a pre-charge circuit which control the DRAM. (M. Suetake)

Synaptic plasticity and memory functions achieved in a WO3−x-based nanoionics device by using the principle of atomic switch operation

International Nuclear Information System (INIS)

Yang, Rui; Terabe, Kazuya; Yao, Yiping; Tsuruoka, Tohru; Hasegawa, Tsuyoshi; Gimzewski, James K; Aono, Masakazu

2013-01-01

A compact neuromorphic nanodevice with inherent learning and memory properties emulating those of biological synapses is the key to developing artificial neural networks rivaling their biological counterparts. Experimental results showed that memorization with a wide time scale from volatile to permanent can be achieved in a WO 3−x -based nanoionics device and can be precisely and cumulatively controlled by adjusting the device’s resistance state and input pulse parameters such as the amplitude, interval, and number. This control is analogous to biological synaptic plasticity including short-term plasticity, long-term potentiation, transition from short-term memory to long-term memory, forgetting processes for short- and long-term memory, learning speed, and learning history. A compact WO 3−x -based nanoionics device with a simple stacked layer structure should thus be a promising candidate for use as an inorganic synapse in artificial neural networks due to its striking resemblance to the biological synapse. (paper)

Electrical bistabilities and memory mechanisms of nonvolatile organic bistable devices based on exfoliated muscovite-type mica nanoparticle/poly(methylmethacrylate) nanocomposites

Science.gov (United States)

Lim, Won Gyu; Lee, Dea Uk; Na, Han Gil; Kim, Hyoun Woo; Kim, Tae Whan

2018-02-01

Organic bistable devices (OBDs) with exfoliated mica nanoparticles (NPs) embedded into an insulating poly(methylmethacrylate) (PMMA) layer were fabricated by using a spin-coating method. Current-voltage (I-V) curves for the Al/PMMA/exfoliated mica NP/PMMA/indium-tin-oxide/glass devices at 300 K showed a clockwise current hysteresis behavior due to the existence of the exfoliated muscovite-type mica NPs, which is an essential feature for bistable devices. Write-read-erase-read data showed that the OBDs had rewritable nonvolatile memories and an endurance number of ON/OFF switching for the OBDs of 102 cycles. An ON/OFF ratio of 1 × 103 was maintained for retention times larger than 1 × 104 s. The memory mechanisms of the fabricated OBDs were described by using the trapping and the tunneling processes within a PMMA active layer containing exfoliated muscovite-type mica NPs on the basis of the energy band diagram and the I-V curves.

Fabrication of ultrahigh density metal-cell-metal crossbar memory devices with only two cycles of lithography and dry-etch procedures

KAUST Repository

Zong, Baoyu

2013-05-20

A novel approach to the fabrication of metal-cell-metal trilayer memory devices was demonstrated by using only two cycles of lithography and dry-etch procedures. The fabricated ultrahigh density crossbar devices can be scaled down to ≤70 nm in half-pitch without alignment issues. Depending on the different dry-etch mechanisms in transferring high and low density nanopatterns, suitable dry-etch angles and methods are studied for the transfer of high density nanopatterns. Some novel process methods have also been developed to eliminate the sidewall and other conversion obstacles for obtaining high density of uniform metallic nanopatterns. With these methods, ultrahigh density trilayer crossbar devices (∼2 × 1010 bit cm-2-kilobit electronic memory), which are composed of built-in practical magnetoresistive nanocells, have been achieved. This scalable process that we have developed provides the relevant industries with a cheap means to commercially fabricate three-dimensional high density metal-cell-metal nanodevices. © 2013 IOP Publishing Ltd.

Configurable memory system and method for providing atomic counting operations in a memory device

Science.gov (United States)

Bellofatto, Ralph E.; Gara, Alan G.; Giampapa, Mark E.; Ohmacht, Martin

2010-09-14

A memory system and method for providing atomic memory-based counter operations to operating systems and applications that make most efficient use of counter-backing memory and virtual and physical address space, while simplifying operating system memory management, and enabling the counter-backing memory to be used for purposes other than counter-backing storage when desired. The encoding and address decoding enabled by the invention provides all this functionality through a combination of software and hardware.

Electrical bistabilities and memory stabilities of nonvolatile bistable devices fabricated utilizing C60 molecules embedded in a polymethyl methacrylate layer

International Nuclear Information System (INIS)

Cho, Sung Hwan; Lee, Dong Ik; Jung, Jae Hun; Kim, Tae Whan

2009-01-01

Current-voltage (I-V) measurements on Al/fullerene (C 60 ) molecules embedded in polymethyl methacrylate/Al devices at 300 K showed a current bistability due to the existence of the C 60 molecules. The on/off ratio of the current bistability for the memory devices was as large as 10 3 . The retention time of the devices was above 2.5 x 10 4 s at room temperature, and cycling endurance tests on these devices indicated that the ON and OFF currents showed no degradation until 50 000 cycles. Carrier transport mechanisms for the nonvolatile bistable devices are described on the basis of the I-V experimental and fitting results.

Oxygen-doped zirconium nitride based transparent resistive random access memory devices fabricated by radio frequency sputtering method

International Nuclear Information System (INIS)

Kim, Hee-Dong; Yun, Min Ju; Kim, Kyeong Heon; Kim, Sungho

2016-01-01

In this work, we present a feasibility of bipolar resistive switching (RS) characteristics for Oxygen-doped zirconium nitride (O-doped ZrN_x) films, produced by sputtering method, which shows a high optical transmittance of approximately 78% in the visible region as well as near ultra-violet region. In addition, in a RS test, the device has a large current ratio of 5 × 10"3 in positive bias region and 5 × 10"5 in negative bias region. Then, to evaluate an ability of data storage for the proposed memory devices, we measured a retention time for 10"4 s at room temperature (RT) and 85 °C as well. As a result, the set and reset states were stably maintained with a current ratio of ∼10"2 at 85 °C to ∼10"3 at RT. This result means that the transparent memory by controlling the working pressure during sputtering process to deposit the ZrN_x films could be a milestone for future see-through electronic devices. - Highlights: • The resistive switching characteristics of the transparent O-doped ZrN_x-based RRAM cells have investigated. • Oxygen doping concentration within ZrN_x is optimized using working pressure of sputter. • Long retention time were observed.

Realization of synaptic learning and memory functions in Y2O3 based memristive device fabricated by dual ion beam sputtering

Science.gov (United States)

Das, Mangal; Kumar, Amitesh; Singh, Rohit; Than Htay, Myo; Mukherjee, Shaibal

2018-02-01

Single synaptic device with inherent learning and memory functions is demonstrated based on a forming-free amorphous Y2O3 (yttria) memristor fabricated by dual ion beam sputtering system. Synaptic functions such as nonlinear transmission characteristics, long-term plasticity, short-term plasticity and ‘learning behavior (LB)’ are achieved using a single synaptic device based on cost-effective metal-insulator-semiconductor (MIS) structure. An ‘LB’ function is demonstrated, for the first time in the literature, for a yttria based memristor, which bears a resemblance to certain memory functions of biological systems. The realization of key synaptic functions in a cost-effective MIS structure would promote much cheaper synapse for artificial neural network.

Process control device

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Kobayashi, Hiroshi.

1994-01-01

A process control device comprises a memory device for memorizing a plant operation target, a plant state or a state of equipments related with each other as control data, a read-only memory device for storing programs, a plant instrumentation control device or other process control devices, an input/output device for performing input/output with an operator, and a processing device which conducts processing in accordance with the program and sends a control demand or a display demand to the input/output device. The program reads out control data relative to a predetermined operation target, compares and verify them with actual values to read out control data to be a practice premise condition which is further to be a practice premise condition if necessary, thereby automatically controlling the plant or requiring or displaying input. Practice presuming conditions for the operation target can be examined succesively in accordance with the program without constituting complicated logical figures and AND/OR graphs. (N.H.)

Calculation of neutron-induced single-event upset cross sections for semiconductor memory devices

International Nuclear Information System (INIS)

Ikeuchi, Taketo; Watanabe, Yukinobu; Nakashima, Hideki; Sun, Weili

2001-01-01

Neutron-induced single-event upset (SEU) cross sections for semiconductor memory devices are calculated by the Burst Generation Rate (BGR) method using LA150 data and QMD calculation in the neutron energy range between 20 MeV and 10 GeV. The calculated results are compared with the measured SEU cross sections for energies up to 160 MeV, and the validity of the calculation method and the nuclear data used is verified. The kind of reaction products and the neutron energy range that have the most effect on SEU are discussed. (author)

Fast Initialization of Bubble-Memory Systems

Science.gov (United States)

Looney, K. T.; Nichols, C. D.; Hayes, P. J.

1986-01-01

Improved scheme several orders of magnitude faster than normal initialization scheme. State-of-the-art commercial bubble-memory device used. Hardware interface designed connects controlling microprocessor to bubblememory circuitry. System software written to exercise various functions of bubble-memory system in comparison made between normal and fast techniques. Future implementations of approach utilize E2PROM (electrically-erasable programable read-only memory) to provide greater system flexibility. Fastinitialization technique applicable to all bubble-memory devices.

Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture.

Science.gov (United States)

Zhu, Bowen; Wang, Hong; Liu, Yaqing; Qi, Dianpeng; Liu, Zhiyuan; Wang, Hua; Yu, Jiancan; Sherburne, Matthew; Wang, Zhaohui; Chen, Xiaodong

2016-02-24

Skin-inspired haptic-memory devices, which can retain pressure information after the removel of external pressure by virtue of the nonvolatile nature of the memory devices, are achieved. The rise of haptic-memory devices will allow for mimicry of human sensory memory, opening new avenues for the design of next-generation high-performance sensing devices and systems. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Memristor as Multi-Bit Memory: Feasibility Analysis

Directory of Open Access Journals (Sweden)

O. Bass

2015-06-01

Full Text Available The use of emerging memristor materials for advanced electrical devices such as multi-valued logic is expected to outperform today's binary logic digital technologies. We show here an example for such non-binary device with the design of a multi-bit memory. While conventional memory cells can store only 1 bit, memristors-based multi-bit cells can store more information within single device thus increasing the information storage density. Such devices can potentially utilize the non-linear resistance of memristor materials for efficient information storage. We analyze the performance of such memory devices based on their expected variations in order to determine the viability of memristor-based multi-bit memory. A design of read/write scheme and a simple model for this cell, lay grounds for full integration of memristor multi-bit memory cell.

A 3D Printed Implantable Device for Voiding the Bladder Using Shape Memory Alloy (SMA) Actuators.

Science.gov (United States)

Hassani, Faezeh Arab; Peh, Wendy Yen Xian; Gammad, Gil Gerald Lasam; Mogan, Roshini Priya; Ng, Tze Kiat; Kuo, Tricia Li Chuen; Ng, Lay Guat; Luu, Percy; Yen, Shih-Cheng; Lee, Chengkuo

2017-11-01

Underactive bladder or detrusor underactivity (DU) is defined as a reduction of contraction strength or duration of the bladder wall. Despite the serious healthcare implications of DU, there are limited solutions for affected individuals. A flexible 3D printed implantable device driven by shape memory alloys (SMA) actuators is presented here for the first time to physically contract the bladder to restore voluntary control of the bladder for individuals suffering from DU. This approach is used initially in benchtop experiments with a rubber balloon acting as a model for the rat bladder to verify its potential for voiding, and that the operating temperatures are safe for the eventual implantation of the device in a rat. The device is then implanted and tested on an anesthetized rat, and a voiding volume of more than 8% is successfully achieved for the SMA-based device without any surgical intervention or drug injection to relax the external sphincter.

Memory properties of a Ge nanoring MOS device fabricated by pulsed laser deposition.

Science.gov (United States)

Ma, Xiying

2008-07-09

The non-volatile charge-storage properties of memory devices with MOS structure based on Ge nanorings have been studied. The two-dimensional Ge nanorings were prepared on a p-Si(100) matrix by means of pulsed laser deposition (PLD) using the droplet technique combined with rapid annealing. Complete planar nanorings with well-defined sharp inner and outer edges were formed via an elastic self-transformation droplet process, which is probably driven by the lateral strain of the Ge/Si layers and the surface tension in the presence of Ar gas. The low leakage current was attributed to the small roughness and the few interface states in the planar Ge nanorings, and also to the effect of Coulomb blockade preventing injection. A significant threshold-voltage shift of 2.5 V was observed when an operating voltage of 8 V was implemented on the device.

Parallel database search and prime factorization with magnonic holographic memory devices

Energy Technology Data Exchange (ETDEWEB)

Khitun, Alexander [Electrical and Computer Engineering Department, University of California - Riverside, Riverside, California 92521 (United States)

2015-12-28

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploit wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.

Parallel database search and prime factorization with magnonic holographic memory devices

Science.gov (United States)

Khitun, Alexander

2015-12-01

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploit wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.

Parallel database search and prime factorization with magnonic holographic memory devices

International Nuclear Information System (INIS)

Khitun, Alexander

2015-01-01

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploit wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed

Nanometer-scale temperature imaging for independent observation of Joule and Peltier effects in phase change memory devices.

Science.gov (United States)

Grosse, Kyle L; Pop, Eric; King, William P

2014-09-01

This paper reports a technique for independent observation of nanometer-scale Joule heating and thermoelectric effects, using atomic force microscopy (AFM) based measurements of nanometer-scale temperature fields. When electrical current flows through nanoscale devices and contacts the temperature distribution is governed by both Joule and thermoelectric effects. When the device is driven by an electrical current that is both periodic and bipolar, the temperature rise due to the Joule effect is at a different harmonic than the temperature rise due to the Peltier effect. An AFM tip scanning over the device can simultaneously measure all of the relevant harmonic responses, such that the Joule effect and the Peltier effect can be independently measured. Here we demonstrate the efficacy of the technique by measuring Joule and Peltier effects in phase change memory devices. By comparing the observed temperature responses of these working devices, we measure the device thermopower, which is in the range of 30 ± 3 to 250 ± 10 μV K(-1). This technique could facilitate improved measurements of thermoelectric phenomena and properties at the nanometer-scale.

Nanometer-scale temperature imaging for independent observation of Joule and Peltier effects in phase change memory devices

Energy Technology Data Exchange (ETDEWEB)

Grosse, Kyle L. [Department of Mechanical Science and Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801 (United States); Pop, Eric [Department of Electrical Engineering, Stanford University, Stanford, California 94305 (United States); King, William P., E-mail: wpk@illinois.edu [Department of Mechanical Science and Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801 (United States); Departments of Electrical and Computer Engineering and Materials Science and Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801 (United States)

2014-09-15

This paper reports a technique for independent observation of nanometer-scale Joule heating and thermoelectric effects, using atomic force microscopy (AFM) based measurements of nanometer-scale temperature fields. When electrical current flows through nanoscale devices and contacts the temperature distribution is governed by both Joule and thermoelectric effects. When the device is driven by an electrical current that is both periodic and bipolar, the temperature rise due to the Joule effect is at a different harmonic than the temperature rise due to the Peltier effect. An AFM tip scanning over the device can simultaneously measure all of the relevant harmonic responses, such that the Joule effect and the Peltier effect can be independently measured. Here we demonstrate the efficacy of the technique by measuring Joule and Peltier effects in phase change memory devices. By comparing the observed temperature responses of these working devices, we measure the device thermopower, which is in the range of 30 ± 3 to 250 ± 10 μV K{sup −1}. This technique could facilitate improved measurements of thermoelectric phenomena and properties at the nanometer-scale.

System of programming units for the K556RT4 and K556RT5 fixed programmed memory devices

International Nuclear Information System (INIS)

Bobkov, S.G.; Ermolin, Yu.V.; Kantserov, V.A.; Strigin, V.B.

1983-01-01

The programming system of constant programmable memory devices K556RT4 and K556RT5 that consist of two units (a programming device and an electrothermotraining unit) is described. The modules are made in the KAMAK standard. The programming device takes up 2 normal places, while the electrothermotraining block takes up 1 place. As information recording is done using a computer the time for programming is reduced and the possibility of errors is limited as compared with the manual method. The computer introduces the whole word to be recorded, not the separate parts, in the programming device. The transition to a new digit of a given word in the programming device is done automatically. This reduces the expense of computer time and accelerates the programming of microdiagrams

Memory behaviour in a radiation environment

International Nuclear Information System (INIS)

Brucker, G.J.; Thurlow, L.

1979-01-01

Memory devices are often required for storage of data which must not be altered during a nuclear burst. If the properties of non-alterability and low power consumption during a standby mode of operation are combined, then the choice is narrowed down to static C-MOS bulk or silicon-on-sapphire (SOS) memories. Previous investigations have indicated that the SOS devices will achieve the maximum non-scrambling dose rate. However, it is interesting to determine the limitations of bulk as well as SOS devices for those programs where circumvention and refreshing of the memory is allowed. This article will present the results of an investigation of the characteristics of these memory types in a transient environment. (author)

Oxygen-doped zirconium nitride based transparent resistive random access memory devices fabricated by radio frequency sputtering method

Energy Technology Data Exchange (ETDEWEB)

Kim, Hee-Dong, E-mail: khd0708@sejong.ac.kr [Department of Electrical Engineering, Sejong University, Neungdong-ro 209, Gwangjin-gu, Seoul 143-747 (Korea, Republic of); Yun, Min Ju [Department of Electrical Engineering, Sejong University, Neungdong-ro 209, Gwangjin-gu, Seoul 143-747 (Korea, Republic of); Kim, Kyeong Heon [School of Electrical Engineering, Korea University, Anam-dong, Sungbuk-gu, Seoul 163-701 (Korea, Republic of); Kim, Sungho, E-mail: sungho85.kim@sejong.ac.kr [Department of Electrical Engineering, Sejong University, Neungdong-ro 209, Gwangjin-gu, Seoul 143-747 (Korea, Republic of)

2016-08-05

In this work, we present a feasibility of bipolar resistive switching (RS) characteristics for Oxygen-doped zirconium nitride (O-doped ZrN{sub x}) films, produced by sputtering method, which shows a high optical transmittance of approximately 78% in the visible region as well as near ultra-violet region. In addition, in a RS test, the device has a large current ratio of 5 × 10{sup 3} in positive bias region and 5 × 10{sup 5} in negative bias region. Then, to evaluate an ability of data storage for the proposed memory devices, we measured a retention time for 10{sup 4} s at room temperature (RT) and 85 °C as well. As a result, the set and reset states were stably maintained with a current ratio of ∼10{sup 2} at 85 °C to ∼10{sup 3} at RT. This result means that the transparent memory by controlling the working pressure during sputtering process to deposit the ZrN{sub x} films could be a milestone for future see-through electronic devices. - Highlights: • The resistive switching characteristics of the transparent O-doped ZrN{sub x}-based RRAM cells have investigated. • Oxygen doping concentration within ZrN{sub x} is optimized using working pressure of sputter. • Long retention time were observed.

All-polymer bistable resistive memory device based on nanoscale phase-separated PCBM-ferroelectric blends

KAUST Repository

Khan, Yasser

2012-11-21

All polymer nonvolatile bistable memory devices are fabricated from blends of ferroelectric poly(vinylidenefluoride-trifluoroethylene (P(VDF-TrFE)) and n-type semiconducting [6,6]-phenyl-C61-butyric acid methyl ester (PCBM). The nanoscale phase separated films consist of PCBM domains that extend from bottom to top electrode, surrounded by a ferroelectric P(VDF-TrFE) matrix. Highly conducting poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) polymer electrodes are used to engineer band offsets at the interfaces. The devices display resistive switching behavior due to modulation of this injection barrier. With careful optimization of the solvent and processing conditions, it is possible to spin cast very smooth blend films (Rrms ≈ 7.94 nm) and with good reproducibility. The devices exhibit high Ion/I off ratios (≈3 × 103), low read voltages (≈5 V), excellent dielectric response at high frequencies (Ïμr ≈ 8.3 at 1 MHz), and excellent retention characteristics up to 10 000 s. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Metallic spintronic devices

CERN Document Server

Wang, Xiaobin

2014-01-01

Metallic Spintronic Devices provides a balanced view of the present state of the art of metallic spintronic devices, addressing both mainstream and emerging applications from magnetic tunneling junction sensors and spin torque oscillators to spin torque memory and logic. Featuring contributions from well-known and respected industrial and academic experts, this cutting-edge work not only presents the latest research and developments but also: Describes spintronic applications in current and future magnetic recording devicesDiscusses spin-transfer torque magnetoresistive random-access memory (STT-MRAM) device architectures and modelingExplores prospects of STT-MRAM scaling, such as detailed multilevel cell structure analysisInvestigates spintronic device write and read optimization in light of spintronic memristive effectsConsiders spintronic research directions based on yttrium iron garnet thin films, including spin pumping, magnetic proximity, spin hall, and spin Seebeck effectsProposes unique solutions for ...

A complementary switching mechanism for organic memory devices to regulate the conductance of binary states

Science.gov (United States)

Vyas, Giriraj; Dagar, Parveen; Sahu, Satyajit

2016-06-01

We have fabricated an organic non-volatile memory device wherein the ON/OFF current ratio has been controlled by varying the concentration of a small organic molecule, 2,3-Dichloro-5,6-dicyano-p-benzoquinone (DDQ), in an insulating matrix of a polymer Poly(4-vinylphenol) (PVP). A maximum ON-OFF ratio of 106 is obtained when the concentration of DDQ is half or 10 wt. % of PVP. In this process, the switching direction for the devices has also been altered, indicating the disparity in conduction mechanism. Conduction due to metal filament formation through the active material and the voltage dependent conformational change of the organic molecule seem to be the motivation behind the gradual change in the switching direction.

Low-cost fabrication and polar-dependent switching uniformity of memory devices using alumina interfacial layer and Ag nanoparticle monolayer

Directory of Open Access Journals (Sweden)

Peng Xia

2017-11-01

Full Text Available A facile and low-cost process was developed for fabricating write-once-read-many-times (WORM Cu/Ag NPs/Alumina/Al memory devices, where the alumina passivation layer formed naturally in air at room temperature, whereas the Ag nanoparticle monolayer was in situ prepared through thermal annealing of a 4.5 nm Ag film in air at 150°C. The devices exhibit irreversible transition from initial high resistance (OFF state to low resistance (ON state, with ON/OFF ratio of 107, indicating the introduction of Ag nanoparticle monolayer greatly improves ON/OFF ratio by four orders of magnitude. The uniformity of threshold voltages exhibits a polar-dependent behavior, and a narrow range of threshold voltages of 0.40 V among individual devices was achieved upon the forward voltage. The memory device can be regarded as two switching units connected in series. The uniform alumina interfacial layer and the non-uniform distribution of local electric fields originated from Ag nanoparticles might be responsible for excellent switching uniformity. Since silver ions in active layer can act as fast ion conductor, a plausible mechanism relating to the formation of filaments sequentially among the two switching units connected in series is suggested for the polar-dependent switching behavior. Furthermore, we demonstrate both alumina layer and Ag NPs monolayer play essential roles in improving switching parameters based on comparative experiments.

Low-cost fabrication and polar-dependent switching uniformity of memory devices using alumina interfacial layer and Ag nanoparticle monolayer

Science.gov (United States)

Xia, Peng; Li, Luman; Wang, Pengfei; Gan, Ying; Xu, Wei

2017-11-01

A facile and low-cost process was developed for fabricating write-once-read-many-times (WORM) Cu/Ag NPs/Alumina/Al memory devices, where the alumina passivation layer formed naturally in air at room temperature, whereas the Ag nanoparticle monolayer was in situ prepared through thermal annealing of a 4.5 nm Ag film in air at 150°C. The devices exhibit irreversible transition from initial high resistance (OFF) state to low resistance (ON) state, with ON/OFF ratio of 107, indicating the introduction of Ag nanoparticle monolayer greatly improves ON/OFF ratio by four orders of magnitude. The uniformity of threshold voltages exhibits a polar-dependent behavior, and a narrow range of threshold voltages of 0.40 V among individual devices was achieved upon the forward voltage. The memory device can be regarded as two switching units connected in series. The uniform alumina interfacial layer and the non-uniform distribution of local electric fields originated from Ag nanoparticles might be responsible for excellent switching uniformity. Since silver ions in active layer can act as fast ion conductor, a plausible mechanism relating to the formation of filaments sequentially among the two switching units connected in series is suggested for the polar-dependent switching behavior. Furthermore, we demonstrate both alumina layer and Ag NPs monolayer play essential roles in improving switching parameters based on comparative experiments.

Near-field NanoThermoMechanical memory

International Nuclear Information System (INIS)

Elzouka, Mahmoud; Ndao, Sidy

2014-01-01

In this letter, we introduce the concept of NanoThermoMechanical Memory. Unlike electronic memory, a NanoThermoMechanical memory device uses heat instead of electricity to record, store, and recover data. Memory function is achieved through the coupling of near-field thermal radiation and thermal expansion resulting in negative differential thermal resistance and thermal latching. Here, we demonstrate theoretically via numerical modeling the concept of near-field thermal radiation enabled negative differential thermal resistance that achieves bistable states. Design and implementation of a practical silicon based NanoThermoMechanical memory device are proposed along with a study of its dynamic response under write/read cycles. With more than 50% of the world's energy losses being in the form of heat along with the ever increasing need to develop computer technologies which can operate in harsh environments (e.g., very high temperatures), NanoThermoMechanical memory and logic devices may hold the answer

In-memory interconnect protocol configuration registers

Energy Technology Data Exchange (ETDEWEB)

Cheng, Kevin Y.; Roberts, David A.

2017-09-19

Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

In-memory interconnect protocol configuration registers

Science.gov (United States)

Cheng, Kevin Y.; Roberts, David A.

2017-09-19

Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

Associative Memory Acceptors.

Science.gov (United States)

Card, Roger

The properties of an associative memory are examined in this paper from the viewpoint of automata theory. A device called an associative memory acceptor is studied under real-time operation. The family "L" of languages accepted by real-time associative memory acceptors is shown to properly contain the family of languages accepted by one-tape,…

Carbon nanomaterials for non-volatile memories

Science.gov (United States)

Ahn, Ethan C.; Wong, H.-S. Philip; Pop, Eric

2018-03-01

Carbon can create various low-dimensional nanostructures with remarkable electronic, optical, mechanical and thermal properties. These features make carbon nanomaterials especially interesting for next-generation memory and storage devices, such as resistive random access memory, phase-change memory, spin-transfer-torque magnetic random access memory and ferroelectric random access memory. Non-volatile memories greatly benefit from the use of carbon nanomaterials in terms of bit density and energy efficiency. In this Review, we discuss sp2-hybridized carbon-based low-dimensional nanostructures, such as fullerene, carbon nanotubes and graphene, in the context of non-volatile memory devices and architectures. Applications of carbon nanomaterials as memory electrodes, interfacial engineering layers, resistive-switching media, and scalable, high-performance memory selectors are investigated. Finally, we compare the different memory technologies in terms of writing energy and time, and highlight major challenges in the manufacturing, integration and understanding of the physical mechanisms and material properties.

Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

International Nuclear Information System (INIS)

Lin, Chun-Cheng; Tang, Jian-Fu; Su, Hsiu-Hsien; Hong, Cheng-Shong; Huang, Chih-Yu; Chu, Sheng-Yuan

2016-01-01

The multi-step resistive switching (RS) behavior of a unipolar Pt/Li 0.06 Zn 0.94 O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li + ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

Poly (vinylidene fluoride-trifluoroethylene/barium titanate nanocomposite for ferroelectric nonvolatile memory devices

Directory of Open Access Journals (Sweden)

Uvais Valiyaneerilakkal

2013-04-01

Full Text Available The effect of barium titanate (BaTiO3 nanoparticles (particle size <100nm on the ferroelectric properties of poly (vinylidenefluoride-trifluoroethylene P(VDF-TrFE copolymer has been studied. Different concentrations of nanoparticles were added to P(VDF-TrFE using probe sonication, and uniform thin films were made. Polarisation - Electric field (P-E hysteresis analysis shows an increase in remnant polarization (Pr and decrease in coercive voltage (Vc. Piezo-response force microscopy analysis shows the switching capability of the polymer composite. The topography and surface roughness was studied using atomic force microscopy. It has been observed that this nanocomposite can be used for the fabrication of non-volatile ferroelectric memory devices.

Optically controlled multiple switching operations of DNA biopolymer devices

International Nuclear Information System (INIS)

Hung, Chao-You; Tu, Waan-Ting; Lin, Yi-Tzu; Fruk, Ljiljana; Hung, Yu-Chueh

2015-01-01

We present optically tunable operations of deoxyribonucleic acid (DNA) biopolymer devices, where a single high-resistance state, write-once read-many-times memory state, write-read-erase memory state, and single low-resistance state can be achieved by controlling UV irradiation time. The device is a simple sandwich structure with a spin-coated DNA biopolymer layer sandwiched by two electrodes. Upon irradiation, the electrical properties of the device are adjusted owing to a phototriggered synthesis of silver nanoparticles in DNA biopolymer, giving rise to multiple switching scenarios. This technique, distinct from the strategy of doping of pre-formed nanoparticles, enables a post-film fabrication process for achieving optically controlled memory device operations, which provides a more versatile platform to fabricate organic memory and optoelectronic devices

Optically controlled multiple switching operations of DNA biopolymer devices

Energy Technology Data Exchange (ETDEWEB)

Hung, Chao-You; Tu, Waan-Ting; Lin, Yi-Tzu [Institute of Photonics Technologies, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Fruk, Ljiljana [Department of Chemical Engineering and Biotechnology, University of Cambridge, Pembroke Street, Cambridge CB2 3RA (United Kingdom); Hung, Yu-Chueh, E-mail: ychung@ee.nthu.edu.tw [Institute of Photonics Technologies, National Tsing Hua University, Hsinchu 30013, Taiwan (China); Department of Electrical Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (China)

2015-12-21

We present optically tunable operations of deoxyribonucleic acid (DNA) biopolymer devices, where a single high-resistance state, write-once read-many-times memory state, write-read-erase memory state, and single low-resistance state can be achieved by controlling UV irradiation time. The device is a simple sandwich structure with a spin-coated DNA biopolymer layer sandwiched by two electrodes. Upon irradiation, the electrical properties of the device are adjusted owing to a phototriggered synthesis of silver nanoparticles in DNA biopolymer, giving rise to multiple switching scenarios. This technique, distinct from the strategy of doping of pre-formed nanoparticles, enables a post-film fabrication process for achieving optically controlled memory device operations, which provides a more versatile platform to fabricate organic memory and optoelectronic devices.

Architectures for a quantum random access memory

OpenAIRE

Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

2008-01-01

A random access memory, or RAM, is a device that, when interrogated, returns the content of a memory location in a memory array. A quantum RAM, or qRAM, allows one to access superpositions of memory sites, which may contain either quantum or classical information. RAMs and qRAMs with n-bit addresses can access 2^n memory sites. Any design for a RAM or qRAM then requires O(2^n) two-bit logic gates. At first sight this requirement might seem to make large scale quantum versions of such devices ...

Fabrication of Nano-Crossbar Resistive Switching Memory Based on the Copper-Tantalum Pentoxide-Platinum Device Structure

Science.gov (United States)

Olga Gneri, Paula; Jardim, Marcos

Resistive switching memory has been of interest lately not only for its simple metal-insulator-metal (MIM) structure but also for its promising ease of scalability an integration into current CMOS technologies like the Field Programmable Gate Arrays and other non-volatile memory applications. There are several resistive switching MIM combinations but under this scope of research, attention will be paid to the bipolar resistive switching characteristics and fabrication of Tantalum Pentaoxide sandwiched between platinum and copper. By changing the polarity of the voltage bias, this metal-insulator-metal (MIM) device can be switched between a high resistive state (OFF) and low resistive state (ON). The change in states is induced by an electrochemical metallization process, which causes a formation or dissolution of Cu metal filamentary paths in the Tantalum Pentaoxide insulator. There is very little thorough experimental information about the Cu-Ta 2O5-Pt switching characteristics when scaled to nanometer dimensions. In this light, the MIM structure was fabricated in a two-dimensional crossbar format. Also, with the limited available resources, a multi-spacer technique was formulated to localize the active device area in this MIM configuration to less than 20nm. This step is important in understanding the switching characteristics and reliability of this structure when scaled to nanometer dimensions.

Overview of emerging nonvolatile memory technologies.

Science.gov (United States)

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

Overview of emerging nonvolatile memory technologies

Science.gov (United States)

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

Units for designing multidetector system for spectrometric data storage on the base of the 16Kx24 bit memory device

International Nuclear Information System (INIS)

Vagov, V.A.; Korobchenko, M.L.; Sirotin, A.P.

1985-01-01

Main units of the system for spectrometric data accumulation on the base of the 16Kx24 bit memory device are considered. Input units: counter unit and unit for organization of analysis are described. The applied method for multiplexing data removed into the counter unit permits to essentially reduce hardware loading. Application of some special functions in the unit for analysis organization simplifies data accumulation control to a large extent. The unit for analysis organization allows application of the memory with an address field up to 64K

Physically Transient Memory on a Rapidly Dissoluble Paper for Security Application

Science.gov (United States)

Bae, Hagyoul; Lee, Byung-Hyun; Lee, Dongil; Seol, Myeong-Lok; Kim, Daewon; Han, Jin-Woo; Kim, Choong-Ki; Jeon, Seung-Bae; Ahn, Daechul; Park, Sang-Jae; Park, Jun-Young; Choi, Yang-Kyu

2016-12-01

We report the transient memory device by means of a water soluble SSG (solid sodium with glycerine) paper. This material has a hydroscopic property hence it can be soluble in water. In terms of physical security of memory devices, prompt abrogation of a memory device which stored a large number of data is crucial when it is stolen because all of things have identified information in the memory device. By utilizing the SSG paper as a substrate, we fabricated a disposable resistive random access memory (RRAM) which has good data retention of longer than 106 seconds and cycling endurance of 300 cycles. This memory device is dissolved within 10 seconds thus it can never be recovered or replicated. By employing direct printing but not lithography technology to aim low cost and disposable applications, the memory capacity tends to be limited less than kilo-bits. However, unlike high memory capacity demand for consumer electronics, the proposed device is targeting for security applications. With this regards, the sub-kilobit memory capacity should find the applications such as one-time usable personal identification, authentication code storage, cryptography key, and smart delivery tag. This aspect is attractive for security and protection system against unauthorized accessibility.

Current-driven domain wall motion based memory devices: Application to a ratchet ferromagnetic strip

Science.gov (United States)

Sánchez-Tejerina, Luis; Martínez, Eduardo; Raposo, Víctor; Alejos, Óscar

2018-04-01

Ratchet memories, where perpendicular magnetocristalline anisotropy is tailored so as to precisely control the magnetic transitions, has been recently proven to be a feasible device to store and manipulate data bits. For such devices, it has been shown that the current-driven regime of domain walls can improve their performances with respect to the field-driven one. However, the relaxing time required by the traveling domain walls constitutes a certain drawback if the former regime is considered, since it results in longer device latencies. In order to speed up the bit shifting procedure, it is demonstrated here that the application of a current of inverse polarity during the DW relaxing time may reduce such latencies. The reverse current must be sufficiently high as to drive the DW to the equilibrium position faster than the anisotropy slope itself, but with an amplitude sufficiently low as to avoid DW backward shifting. Alternatively, it is possible to use such a reverse current to increase the proper range of operation for a given relaxing time, i.e., the pair of values of the current amplitude and pulse time that ensures single DW jumps for a certain latency time.

Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

Energy Technology Data Exchange (ETDEWEB)

Lin, Chun-Cheng [Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (China); Department of Mathematic and Physical Sciences, R.O.C. Air Force Academy, Kaohsiung 820, Taiwan (China); Tang, Jian-Fu; Su, Hsiu-Hsien [Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (China); Hong, Cheng-Shong; Huang, Chih-Yu [Department of Electronic Engineering, National Kaohsiung Normal University, Kaohsiung 802, Taiwan (China); Chu, Sheng-Yuan, E-mail: chusy@mail.ncku.edu.tw [Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (China); Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan 701, Taiwan (China)

2016-06-28

The multi-step resistive switching (RS) behavior of a unipolar Pt/Li{sub 0.06}Zn{sub 0.94}O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li{sup +} ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

Protecting Cryptographic Memory against Tampering Attack

DEFF Research Database (Denmark)

Mukherjee, Pratyay

In this dissertation we investigate the question of protecting cryptographic devices from tampering attacks. Traditional theoretical analysis of cryptographic devices is based on black-box models which do not take into account the attacks on the implementations, known as physical attacks. In prac......In this dissertation we investigate the question of protecting cryptographic devices from tampering attacks. Traditional theoretical analysis of cryptographic devices is based on black-box models which do not take into account the attacks on the implementations, known as physical attacks....... In practice such attacks can be executed easily, e.g. by heating the device, as substantiated by numerous works in the past decade. Tampering attacks are a class of such physical attacks where the attacker can change the memory/computation, gains additional (non-black-box) knowledge by interacting...... with the faulty device and then tries to break the security. Prior works show that generically approaching such problem is notoriously difficult. So, in this dissertation we attempt to solve an easier question, known as memory-tampering, where the attacker is allowed tamper only with the memory of the device...

Design exploration of emerging nano-scale non-volatile memory

CERN Document Server

Yu, Hao

2014-01-01

This book presents the latest techniques for characterization, modeling and design for nano-scale non-volatile memory (NVM) devices.  Coverage focuses on fundamental NVM device fabrication and characterization, internal state identification of memristic dynamics with physics modeling, NVM circuit design, and hybrid NVM memory system design-space optimization. The authors discuss design methodologies for nano-scale NVM devices from a circuits/systems perspective, including the general foundations for the fundamental memristic dynamics in NVM devices.  Coverage includes physical modeling, as well as the development of a platform to explore novel hybrid CMOS and NVM circuit and system design.   • Offers readers a systematic and comprehensive treatment of emerging nano-scale non-volatile memory (NVM) devices; • Focuses on the internal state of NVM memristic dynamics, novel NVM readout and memory cell circuit design, and hybrid NVM memory system optimization; • Provides both theoretical analysis and pr...

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

KAUST Repository

Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2015-01-01

Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

Directory of Open Access Journals (Sweden)

Mohamed T. Ghoneim

2015-07-01

Full Text Available Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT, the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

KAUST Repository

Ghoneim, Mohamed T.

2015-07-23

Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Atomic crystals resistive switching memory

International Nuclear Information System (INIS)

Liu Chunsen; Zhang David Wei; Zhou Peng

2017-01-01

Facing the growing data storage and computing demands, a high accessing speed memory with low power and non-volatile character is urgently needed. Resistive access random memory with 4F 2 cell size, switching in sub-nanosecond, cycling endurances of over 10 12 cycles, and information retention exceeding 10 years, is considered as promising next-generation non-volatile memory. However, the energy per bit is still too high to compete against static random access memory and dynamic random access memory. The sneak leakage path and metal film sheet resistance issues hinder the further scaling down. The variation of resistance between different devices and even various cycles in the same device, hold resistive access random memory back from commercialization. The emerging of atomic crystals, possessing fine interface without dangling bonds in low dimension, can provide atomic level solutions for the obsessional issues. Moreover, the unique properties of atomic crystals also enable new type resistive switching memories, which provide a brand-new direction for the resistive access random memory. (topical reviews)

Role of Al2O3 thin layer on improving the resistive switching properties of Ta5Si3-based conductive bridge random accesses memory device

Science.gov (United States)

Kumar, Dayanand; Aluguri, Rakesh; Chand, Umesh; Tseng, Tseung-Yuen

2018-04-01

Ta5Si3-based conductive bridge random access memory (CBRAM) devices have been investigated to improve their resistive switching characteristics for their application in future nonvolatile memory technology. Changes in the switching characteristics by the addition of a thin Al2O3 layer of different thicknesses at the bottom electrode interface of a Ta5Si3-based CBRAM devices have been studied. The double-layer device with a 1 nm Al2O3 layer has shown improved resistive switching characteristics over the single layer one with a high on/off resistance ratio of 102, high endurance of more than 104 cycles, and good retention for more than 105 s at the temperature of 130 °C. The higher thermal conductivity of Al2O3 over Ta5Si3 has been attributed to the enhanced switching properties of the double-layer devices.

Deposition and Characterization of CVD-Grown Ge-Sb Thin Film Device for Phase-Change Memory Application

Directory of Open Access Journals (Sweden)

C. C. Huang

2012-01-01

Full Text Available Germanium antimony (Ge-Sb thin films with tuneable compositions have been fabricated on SiO2/Si, borosilicate glass, and quartz glass substrates by chemical vapour deposition (CVD. Deposition takes place at atmospheric pressure using metal chloride precursors at reaction temperatures between 750 and 875°C. The compositions and structures of these thin films have been characterized by micro-Raman, scanning electron microscope (SEM with energy dispersive X-ray analysis (EDX and X-ray diffraction (XRD techniques. A prototype Ge-Sb thin film phase-change memory device has been fabricated and reversible threshold and phase-change switching demonstrated electrically, with a threshold voltage of 2.2–2.5 V. These CVD-grown Ge-Sb films show promise for applications such as phase-change memory and optical, electronic, and plasmonic switching.

Phase change memory

CERN Document Server

Qureshi, Moinuddin K

2011-01-01

As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions t

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Science.gov (United States)

Asaad, Sameh W.; Kapur, Mohit

2016-03-15

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Memory attacks on device-independent quantum cryptography.

Science.gov (United States)

Barrett, Jonathan; Colbeck, Roger; Kent, Adrian

2013-01-04

Device-independent quantum cryptographic schemes aim to guarantee security to users based only on the output statistics of any components used, and without the need to verify their internal functionality. Since this would protect users against untrustworthy or incompetent manufacturers, sabotage, or device degradation, this idea has excited much interest, and many device-independent schemes have been proposed. Here we identify a critical weakness of device-independent protocols that rely on public communication between secure laboratories. Untrusted devices may record their inputs and outputs and reveal information about them via publicly discussed outputs during later runs. Reusing devices thus compromises the security of a protocol and risks leaking secret data. Possible defenses include securely destroying or isolating used devices. However, these are costly and often impractical. We propose other more practical partial defenses as well as a new protocol structure for device-independent quantum key distribution that aims to achieve composable security in the case of two parties using a small number of devices to repeatedly share keys with each other (and no other party).

Embedded RFID Recorder in short-range wireless devices

DEFF Research Database (Denmark)

2010-01-01

range communication devices. The problem is solved in that the portable communications device comprises a wireless communications interface for communicating with another device, a memory and an RFID-recorder for receiving an RFID-signal transmitted from an RFID-interrogator, wherein the device...... is adapted for storing individual received RFID-signals in the memory. An advantage of the invention is that it provides a relatively simple scheme for extracting information from a current environment of a portable communications device. The invention may e.g. be used for adapting listening devices, e...

Flexible graphene–PZT ferroelectric nonvolatile memory

International Nuclear Information System (INIS)

Lee, Wonho; Ahn, Jong-Hyun; Kahya, Orhan; Toh, Chee Tat; Özyilmaz, Barbaros

2013-01-01

We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr 0.35 ,Ti 0.65 )O 3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol–gel methods, respectively. Such PZT films show a high remnant polarization (P r ) of 30 μC cm −2 and a coercive voltage (V c ) of 3.5 V under a voltage loop over ±11 V. The graphene–PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits. (paper)

Flexible graphene-PZT ferroelectric nonvolatile memory.

Science.gov (United States)

Lee, Wonho; Kahya, Orhan; Toh, Chee Tat; Ozyilmaz, Barbaros; Ahn, Jong-Hyun

2013-11-29

We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr0.35,Ti0.65)O3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol–gel methods, respectively. Such PZT films show a high remnant polarization (Pr) of 30 μC cm−2 and a coercive voltage (Vc) of 3.5 V under a voltage loop over ±11 V. The graphene–PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits.

Feasibility study of using a Zener diode as the selection device for bipolar RRAM and WORM memory arrays

International Nuclear Information System (INIS)

Li, Yingtao; Fu, Liping; Tao, Chunlan; Jiang, Xinyu; Sun, Pengxiao

2014-01-01

Cross-bar arrays are usually used for the high density application of resistive random access memory (RRAM) devices. However, cross-talk interference limits an increase in the integration density. In this paper, the Zener diode is proposed as a selection device to suppress the sneak current in bipolar RRAM arrays. Measurement results show that the Zener diode can act as a good selection device, and the sneak current can be effectively suppressed. The readout margin is sufficiently improved compared to that obtained without the selection device. Due to the improvement for the reading disturbance, the size of the cross-bar array can be enhanced to more than 10 3  × 10 3 . Furthermore, the possibility of using a write-once-read-many-times (WORM) cross-bar array is also demonstrated by connecting the Zener diode and the bipolar RRAM in series. These results strongly suggest that using a Zener diode as a selection device opens up great opportunities to realize high density bipolar RRAM arrays. (paper)

Functional memory metals

International Nuclear Information System (INIS)

Dunne, D.P.

2000-01-01

The field of shape memory phenomena in metals and alloys has developed in a sporadic fashion from a scientific curiosity to a vigorously growing niche industry, over a period close to a full working lifetime. Memory metal research and development is replete with scientist and engineer 'true believers', who can finally feel content that their longstanding confidence in the potential of these unusual functional materials has not been misplaced. This paper reviews the current range of medical and non-medical systems and devices which are based on memory metals and attempts to predict trends in applications over the next decade. The market is dominated by Ni Ti alloys which have proved to exhibit the best and most reproducible properties for application in a wide range of medical and non-medical devices

Shape memory alloys

International Nuclear Information System (INIS)

Kaszuwara, W.

2004-01-01

Shape memory alloys (SMA), when deformed, have the ability of returning, in certain circumstances, to their initial shape. Deformations related to this phenomenon are for polycrystals 1-8% and up to 15% for monocrystals. The deformation energy is in the range of 10 6 - 10 7 J/m 3 . The deformation is caused by martensitic transformation in the material. Shape memory alloys exhibit one directional or two directional shape memory effect as well as pseudoelastic effect. Shape change is activated by temperature change, which limits working frequency of SMA to 10 2 Hz. Other group of alloys exhibit magnetic shape memory effect. In these alloys martensitic transformation is triggered by magnetic field, thus their working frequency can be higher. Composites containing shape memory alloys can also be used as shape memory materials (applied in vibration damping devices). Another group of composite materials is called heterostructures, in which SMA alloys are incorporated in a form of thin layers The heterostructures can be used as microactuators in microelectromechanical systems (MEMS). Basic SMA comprise: Ni-Ti, Cu (Cu-Zn,Cu-Al, Cu-Sn) and Fe (Fe-Mn, Fe-Cr-Ni) alloys. Shape memory alloys find applications in such areas: automatics, safety and medical devices and many domestic appliances. Currently the most important appears to be research on magnetic shape memory materials and high temperature SMA. Vital from application point of view are composite materials especially those containing several intelligent materials. (author)

Built-In Test Engine For Memory Test

OpenAIRE

McEvoy, Paul; Farrell, Ronan

2004-01-01

In this paper we will present an on-chip method for testing high performance memory devices, that occupies minimal area and retains full flexibility. This is achieved through microcode test instructions and the associated on-chip state machine. In addition, the proposed methodology will enable at-speed testing of memory devices. The relevancy of this work is placed in context with an introduction to memory testing and the techniques and algorithms generally used today.

Memristive learning and memory functions in polyvinyl alcohol polymer memristors

Directory of Open Access Journals (Sweden)

Yan Lei

2014-07-01

Full Text Available Polymer based memristive devices can offer simplicity in fabrication and at the same time promise functionalities for artificial neural applications. In this work, inherent learning and memory functions have been achieved in polymer memristive devices employing Polyvinyl Alcohol. The change in conduction in such polymer devices strongly depends on the pulse amplitude, duration and time interval. Through repetitive stimuli training, temporary short-term memory can transfer into consolidated long-term memory. These behaviors bear remarkable similarities to certain learning and memory functions of biological systems.

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Energy Technology Data Exchange (ETDEWEB)

Ohmacht, Martin

2017-08-15

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Science.gov (United States)

Ohmacht, Martin

2014-09-09

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Realization of write-once-read-many-times memory device with O{sub 2} plasma-treated indium gallium zinc oxide thin film

Energy Technology Data Exchange (ETDEWEB)

Liu, P., E-mail: liup0013@ntu.edu.sg; Chen, T. P., E-mail: echentp@ntu.edu.sg; Li, X. D.; Wong, J. I. [School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (Singapore); Liu, Z. [School of Materials and Energy, Guangdong University of Technology, Guangzhou 510006 (China); Liu, Y. [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, Sichuan 610054 (China); Leong, K. C. [GLOBALFOUNDRIES Singapore Pte Ltd, 60 Woodlands Industrial Park D Street 2, Singapore 738406 (Singapore)

2014-01-20

A write-once-read-many-times (WORM) memory devices based on O{sub 2} plasma-treated indium gallium zinc oxide (IGZO) thin films has been demonstrated. The device has a simple Al/IGZO/Al structure. The device has a normally OFF state with a very high resistance (e.g., the resistance at 2 V is ∼10{sup 9} Ω for a device with the radius of 50 μm) as a result of the O{sub 2} plasma treatment on the IGZO thin films. The device could be switched to an ON state with a low resistance (e.g., the resistance at 2 V is ∼10{sup 3} Ω for the radius of 50 μm) by applying a voltage pulse (e.g., 10 V/1 μs). The WORM device has good data-retention and reading-endurance capabilities.

VOP memory management in MPEG-4

Science.gov (United States)

Vaithianathan, Karthikeyan; Panchanathan, Sethuraman

2001-03-01

MPEG-4 is a multimedia standard that requires Video Object Planes (VOPs). Generation of VOPs for any kind of video sequence is still a challenging problem that largely remains unsolved. Nevertheless, if this problem is treated by imposing certain constraints, solutions for specific application domains can be found. MPEG-4 applications in mobile devices is one such domain where the opposite goals namely low power and high throughput are required to be met. Efficient memory management plays a major role in reducing the power consumption. Specifically, efficient memory management for VOPs is difficult because the lifetimes of these objects vary and these life times may be overlapping. Varying life times of the objects requires dynamic memory management where memory fragmentation is a key problem that needs to be addressed. In general, memory management systems address this problem by following a combination of strategy, policy and mechanism. For MPEG4 based mobile devices that lack instruction processors, a hardware based memory management solution is necessary. In MPEG4 based mobile devices that have a RISC processor, using a Real time operating system (RTOS) for this memory management task is not expected to be efficient because the strategies and policies used by the ROTS is often tuned for handling memory segments of smaller sizes compared to object sizes. Hence, a memory management scheme specifically tuned for VOPs is important. In this paper, different strategies, policies and mechanisms for memory management are considered and an efficient combination is proposed for the case of VOP memory management along with a hardware architecture, which can handle the proposed combination.

Device for multi-dimensional γ-γ-coincidence study

International Nuclear Information System (INIS)

Gruzinova, T.M.; Erokhina, K.I.; Kutuzov, V.I.; Lemberg, I.Kh.; Petrov, S.A.; Revenko, V.S.; Senin, A.T.; Chugunov, I.N.; Shishlinov, V.M.

1977-01-01

A device for studying multi-dimensional γ-γ coincidences is described which operates on-line with the BESM-4 computer. The device comprises Ge(Li) detectors, analog-to-digital converters, shaper discriminators and fast amplifiers. To control the device operation as a whole and to elaborate necessary commands, an information distributor has been developed. The following specific features of the device operation are noted: the device may operate both in the regime of recording spectra of direct γ radiation in the block memory of multi-channel analyzer, and in the regime of data transfer to the computer memory; the device performs registration of coincidences; it transfers information to the computer which has a channel of direct access to the memory. The procedure of data processing is considered, the data being recorded on a magnetic tape. Partial spectra obtained are in a good agreement with data obtained elsewhere

A vertically integrated capacitorless memory cell

International Nuclear Information System (INIS)

Tong Xiaodong; Wu Hao; Zhao Lichuan; Wang Ming; Zhong Huicai

2013-01-01

A two-port capacitorless PNPN device with high density, high speed and low power memory fabricated using standard CMOS technology is presented. Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed (ns level), large read current margin (read current ratio of 10 4 ×), low process variation, good thermal reliability and available retention time (190 ms). Furthermore, the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure. (semiconductor devices)

Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory

International Nuclear Information System (INIS)

Li Xinkai; Huo Zongliang; Jin Lei; Jiang Dandan; Hong Peizhen; Xu Qiang; Tang Zhaoyun; Li Chunlong; Ye Tianchun

2015-01-01

This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration. (paper)

Investigation of fast initialization of spacecraft bubble memory systems

Science.gov (United States)

Looney, K. T.; Nichols, C. D.; Hayes, P. J.

1984-01-01

Bubble domain technology offers significant improvement in reliability and functionality for spacecraft onboard memory applications. In considering potential memory systems organizations, minimization of power in high capacity bubble memory systems necessitates the activation of only the desired portions of the memory. In power strobing arbitrary memory segments, a capability of fast turn on is required. Bubble device architectures, which provide redundant loop coding in the bubble devices, limit the initialization speed. Alternate initialization techniques are investigated to overcome this design limitation. An initialization technique using a small amount of external storage is demonstrated.

Overview of radiation effects on emerging non-volatile memory technologies

Directory of Open Access Journals (Sweden)

Fetahović Irfan S.

2017-01-01

Full Text Available In this paper we give an overview of radiation effects in emergent, non-volatile memory technologies. Investigations into radiation hardness of resistive random access memory, ferroelectric random access memory, magneto-resistive random access memory, and phase change memory are presented in cases where these memory devices were subjected to different types of radiation. The obtained results proved high radiation tolerance of studied devices making them good candidates for application in radiation-intensive environments. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. 171007

CMOS-compatible spintronic devices: a review

Science.gov (United States)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Efficient Signature Based Malware Detection on Mobile Devices

Directory of Open Access Journals (Sweden)

Deepak Venugopal

2008-01-01

Full Text Available The threat of malware on mobile devices is gaining attention recently. It is important to provide security solutions to these devices before these threats cause widespread damage. However, mobile devices have severe resource constraints in terms of memory and power. Hence, even though there are well developed techniques for malware detection on the PC domain, it requires considerable effort to adapt these techniques for mobile devices. In this paper, we outline the considerations for malware detection on mobile devices and propose a signature based malware detection method. Specifically, we detail a signature matching algorithm that is well suited for use in mobile device scanning due to its low memory requirements. Additionally, the matching algorithm is shown to have high scanning speed which makes it unobtrusive to users. Our evaluation and comparison study with the well known Clam-AV scanner shows that our solution consumes less than 50% of the memory used by Clam-AV while maintaining a fast scanning rate.

Electric field mediated non-volatile tuning magnetism in CoPt/PMN-PT heterostructure for magnetoelectric memory devices

Science.gov (United States)

Yang, Y. T.; Li, J.; Peng, X. L.; Wang, X. Q.; Wang, D. H.; Cao, Q. Q.; Du, Y. W.

2016-02-01

We report a power efficient non-volatile magnetoelectric memory in the CoPt/(011)PMN-PT heterostructure. Two reversible and stable electric field induced coercivity states (i.e., high-HC or low-HC) are obtained due to the strain mediated converse magnetoelectric effect. The reading process of the different coercive field information written by electric fields is demonstrated by using a magnetoresistance read head. This result shows good prospects in the application of novel multiferroic devices.

Radiation effect test on ADC/DAC and high density memory devices with 60Co γ-rays

International Nuclear Information System (INIS)

Xing Kefei; Wang Yueke; Pan Huafeng

2006-01-01

A test platform was constructed for 60 Co γ-ray irradiation experiment of microelectronics, with the aid of computer and a FPGA module. The tested sample devices included analog-to-digital converter AD10465, digital-to-analog converter AD9857, high density Flash memory MEF64M16 and anti-fused PROM XQR17V16, which are used in signal processing module in spaceborne systems. Evaluations were made on their ability of resisting the total dose based on the proper function criterion of the devices. The results showed that AD10465 and AD9857 ran properly after 1.59 kGy(Si) irradiation, but errors were found when MEF64M16 and XQR17V16's total ionizing dose is 0.13 kGy(Si) and 0.99 kGy(Si), respectively. (authors)

Noise-assisted morphing of memory and logic function

International Nuclear Information System (INIS)

Kohar, Vivek; Sinha, Sudeshna

2012-01-01

We demonstrate how noise allows a bistable system to behave as a memory device, as well as a logic gate. Namely, in some optimal range of noise, the system can operate flexibly, both as a NAND/AND gate and a Set–Reset latch, by varying an asymmetrizing bias. Thus we show how this system implements memory, even for sub-threshold input signals, using noise constructively to store information. This can lead to the development of reconfigurable devices, that can switch efficiently between memory tasks and logic operations. -- Highlights: ► We consider a nonlinear system in a noisy environment. ► We show that the system can function as a robust memory element. ► Further, the response of the system can be easily morphed from memory to logic operations. ► Such systems can potentially act as building blocks of “smart” computing devices.

Large scale testing of nitinol shape memory alloy devices for retrofitting of bridges

International Nuclear Information System (INIS)

Johnson, Rita; Emmanuel Maragakis, M; Saiid Saiidi, M; Padgett, Jamie E; DesRoches, Reginald

2008-01-01

A large scale testing program was conducted to determine the effects of shape memory alloy (SMA) restrainer cables on the seismic performance of in-span hinges of a representative multiple-frame concrete box girder bridge subjected to earthquake excitations. Another objective of the study was to compare the performance of SMA restrainers to that of traditional steel restrainers as restraining devices for reducing hinge displacement and the likelihood of collapse during earthquakes. The results of the tests show that SMA restrainers performed very well as restraining devices. The forces in the SMA and steel restrainers were comparable. However, the SMA restrainer cables had minimal residual strain after repeated loading and exhibited the ability to undergo many cycles with little strength and stiffness degradation. In addition, the hysteretic damping that was observed in the larger ground accelerations demonstrated the ability of the materials to dissipate energy. An analytical study was conducted to assess the anticipated seismic response of the test setup and evaluate the accuracy of the analytical model. The results of the analytical simulation illustrate that the analytical model was able to match the responses from the experimental tests, including peak stresses, strains, forces, and hinge openings

Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Science.gov (United States)

Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

2011-08-01

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

Repair and managing device in nuclear power plants

International Nuclear Information System (INIS)

Shinzawa, Katsuo.

1982-01-01

Purpose: To moderate the operator's labour by automatically carrying out the managing works for the repair of nuclear power plants. Constitution: Information concerning the content of the repair works inputted from an input device is arranged and analyzed in a calculation device and judged if it is the content for a format work or not. The calculation device has a function of extracting the information regarding the format work content from the memory device and comparing the plant information from the reading device before the repair work and after the recovering work. A printer connected to the output end of the calculation device issues an information regarding the format work content extracted from the memory device, that is, written work procedures and operation inhibition TAG. The content, period, person in charge, purpose, allowed items and the likes for the works are printed on the operation inhibition TAG. After the operation for the equipments, one half of them is charged to the equipment and the other half of them is charged to the reading device and the plant information is sent to the memory device. (Kawakami, Y.)

Single memory with multiple shift register functionality

NARCIS (Netherlands)

2010-01-01

The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing access to said memory (EM). Furthermore, access control means (A)

Spin transport and spin torque in antiferromagnetic devices

Science.gov (United States)

Železný, J.; Wadley, P.; Olejník, K.; Hoffmann, A.; Ohno, H.

2018-03-01

Ferromagnets are key materials for sensing and memory applications. In contrast, antiferromagnets, which represent the more common form of magnetically ordered materials, have found less practical application beyond their use for establishing reference magnetic orientations via exchange bias. This might change in the future due to the recent progress in materials research and discoveries of antiferromagnetic spintronic phenomena suitable for device applications. Experimental demonstration of the electrical switching and detection of the Néel order open a route towards memory devices based on antiferromagnets. Apart from the radiation and magnetic-field hardness, memory cells fabricated from antiferromagnets can be inherently multilevel, which could be used for neuromorphic computing. Switching speeds attainable in antiferromagnets far exceed those of ferromagnetic and semiconductor memory technologies. Here, we review the recent progress in electronic spin-transport and spin-torque phenomena in antiferromagnets that are dominantly of the relativistic quantum-mechanical origin. We discuss their utility in pure antiferromagnetic or hybrid ferromagnetic/antiferromagnetic memory devices.

An optically transparent and flexible memory with embedded gold nanoparticles in a polymethylsilsesquioxane dielectric

International Nuclear Information System (INIS)

Ooi, P.C.; Aw, K.C.; Gao, W.; Razak, K.A.

2013-01-01

In this work, we demonstrated a simple fabrication route towards an optically transparent and flexible memory device. The device is simple and consists of a metal/insulator/semiconductor structure; namely MIS. The preliminary MIS study with gold nanoparticles embedded between the polymethylsilsesquioxane layers was fabricated on p-Si substrate and the capacitance versus voltage measurements confirmed the charge trapped capability of the fabricated MIS memory device. Subsequently, an optically transparent and flexible MIS memory device made from indium–tin-oxide coated polyethylene terephthalate substrate and pentacene was used to replace the opaque p-Si substrate as the active layer. Current versus voltage (I–V) plot of the transparent and flexible device shows the presence of hysteresis. In an I–V plot, three distinct regions have been identified and the transport mechanisms are explained. The fabricated optically transparent and mechanically flexible MIS memory device can be programmed and erased multiple times, similar to a flash memory. Mechanical characterization to determine the robustness of the flexible memory device was also conducted but failed to establish any relationship in this preliminary work as the effect was random. Hence, more work is needed to understand the reliability of this device, especially when they are subjected to mechanical stress. - Highlights: ► An optically transparent and mechanically flexible memory is presented. ► Electrical characteristics show reprogrammable memory similar to flash memory. ► Transport mechanisms are proposed and explained. ► Mechanical bending tests are conducted

An optically transparent and flexible memory with embedded gold nanoparticles in a polymethylsilsesquioxane dielectric

Energy Technology Data Exchange (ETDEWEB)

Ooi, P.C. [Mechanical Engineering, The University of Auckland (New Zealand); Aw, K.C., E-mail: k.aw@auckland.ac.nz [Mechanical Engineering, The University of Auckland (New Zealand); Gao, W. [Chemical and Materials Engineering, The University of Auckland (New Zealand); Razak, K.A. [School of Materials and Mineral Resources Engineering, Universiti Sains (Malaysia); NanoBiotechnology Research and Innovation, INFORMM, Universiti Sains (Malaysia)

2013-10-01

In this work, we demonstrated a simple fabrication route towards an optically transparent and flexible memory device. The device is simple and consists of a metal/insulator/semiconductor structure; namely MIS. The preliminary MIS study with gold nanoparticles embedded between the polymethylsilsesquioxane layers was fabricated on p-Si substrate and the capacitance versus voltage measurements confirmed the charge trapped capability of the fabricated MIS memory device. Subsequently, an optically transparent and flexible MIS memory device made from indium–tin-oxide coated polyethylene terephthalate substrate and pentacene was used to replace the opaque p-Si substrate as the active layer. Current versus voltage (I–V) plot of the transparent and flexible device shows the presence of hysteresis. In an I–V plot, three distinct regions have been identified and the transport mechanisms are explained. The fabricated optically transparent and mechanically flexible MIS memory device can be programmed and erased multiple times, similar to a flash memory. Mechanical characterization to determine the robustness of the flexible memory device was also conducted but failed to establish any relationship in this preliminary work as the effect was random. Hence, more work is needed to understand the reliability of this device, especially when they are subjected to mechanical stress. - Highlights: ► An optically transparent and mechanically flexible memory is presented. ► Electrical characteristics show reprogrammable memory similar to flash memory. ► Transport mechanisms are proposed and explained. ► Mechanical bending tests are conducted.

Performance enhancement in p-channel charge-trapping flash memory devices with Si/Ge super-lattice channel and band-to-band tunneling induced hot-electron injection

International Nuclear Information System (INIS)

Liu, Li-Jung; Chang-Liao, Kuei-Shu; Jian, Yi-Chuen; Wang, Tien-Ko; Tsai, Ming-Jinn

2013-01-01

P-channel charge-trapping flash memory devices with Si, SiGe, and Si/Ge super-lattice channel are investigated in this work. A Si/Ge super-lattice structure with extremely low roughness and good crystal structure is obtained by precisely controlling the epitaxy thickness of Ge layer. Both programming and erasing (P/E) speeds are significantly improved by employing this Si/Ge super-lattice channel. Moreover, satisfactory retention and excellent endurance characteristics up to 10 6 P/E cycles with 3.8 V memory window show that the degradation on reliability properties is negligible when super-lattice channel is introduced. - Highlights: ► A super-lattice structure is proposed to introduce more Ge content into channel. ► Super-lattice structure possesses low roughness and good crystal structure. ► P-channel flash devices with Si, SiGe, and super-lattice channel are investigated. ► Programming/erasing speeds are significantly improved. ► Reliability properties can be kept for device with super-lattice channel

Testing of modern semiconductor memory structures

NARCIS (Netherlands)

Gaydadjiev, G.N.

2007-01-01

In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application

GA-based optimum design of a shape memory alloy device for seismic response mitigation

International Nuclear Information System (INIS)

Ozbulut, O E; Roschke, P N; Lin, P Y; Loh, C H

2010-01-01

Damping systems discussed in this work are optimized so that a three-story steel frame structure and its shape memory alloy (SMA) bracing system minimize response metrics due to a custom-tailored earthquake excitation. Multiple-objective numerical optimization that simultaneously minimizes displacements and accelerations of the structure is carried out with a genetic algorithm (GA) in order to optimize SMA bracing elements within the structure. After design of an optimal SMA damping system is complete, full-scale experimental shake table tests are conducted on a large-scale steel frame that is equipped with the optimal SMA devices. A fuzzy inference system is developed from data collected during the testing to simulate the dynamic material response of the SMA bracing subcomponents. Finally, nonlinear analyses of a three-story braced frame are carried out to evaluate the performance of comparable SMA and commonly used steel braces under dynamic loading conditions and to assess the effectiveness of GA-optimized SMA bracing design as compared to alternative designs of SMA braces. It is shown that peak displacement of a structure can be reduced without causing significant acceleration response amplification through a judicious selection of physical characteristics of the SMA devices. Also, SMA devices provide a recentering mechanism for the structure to return to its original position after a seismic event

Post polymerization cure shape memory polymers

Energy Technology Data Exchange (ETDEWEB)

Wilson, Thomas S.; Hearon, II, Michael Keith; Bearinger, Jane P.

2017-01-10

This invention relates to chemical polymer compositions, methods of synthesis, and fabrication methods for devices regarding polymers capable of displaying shape memory behavior (SMPs) and which can first be polymerized to a linear or branched polymeric structure, having thermoplastic properties, subsequently processed into a device through processes typical of polymer melts, solutions, and dispersions and then crossed linked to a shape memory thermoset polymer retaining the processed shape.

Post polymerization cure shape memory polymers

Science.gov (United States)

Wilson, Thomas S; Hearon, Michael Keith; Bearinger, Jane P

2014-11-11

This invention relates to chemical polymer compositions, methods of synthesis, and fabrication methods for devices regarding polymers capable of displaying shape memory behavior (SMPs) and which can first be polymerized to a linear or branched polymeric structure, having thermoplastic properties, subsequently processed into a device through processes typical of polymer melts, solutions, and dispersions and then crossed linked to a shape memory thermoset polymer retaining the processed shape.

Overview of one transistor type of hybrid organic ferroelectric non-volatile memory

Institute of Scientific and Technical Information of China (English)

Young; Tea; Chun; Daping; Chu

2015-01-01

Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.

Pattern recognition with magnonic holographic memory device

International Nuclear Information System (INIS)

Kozhevnikov, A.; Dudko, G.; Filimonov, Y.; Gertz, F.; Khitun, A.

2015-01-01

In this work, we present experimental data demonstrating the possibility of using magnonic holographic devices for pattern recognition. The prototype eight-terminal device consists of a magnetic matrix with micro-antennas placed on the periphery of the matrix to excite and detect spin waves. The principle of operation is based on the effect of spin wave interference, which is similar to the operation of optical holographic devices. Input information is encoded in the phases of the spin waves generated on the edges of the magnonic matrix, while the output corresponds to the amplitude of the inductive voltage produced by the interfering spin waves on the other side of the matrix. The level of the output voltage depends on the combination of the input phases as well as on the internal structure of the magnonic matrix. Experimental data collected for several magnonic matrixes show the unique output signatures in which maxima and minima correspond to specific input phase patterns. Potentially, magnonic holographic devices may provide a higher storage density compare to optical counterparts due to a shorter wavelength and compatibility with conventional electronic devices. The challenges and shortcoming of the magnonic holographic devices are also discussed

Scientific developments of liquid crystal-based optical memory: a review

Science.gov (United States)

Prakash, Jai; Chandran, Achu; Biradar, Ashok M.

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Shape memory alloy actuator

Science.gov (United States)

Varma, Venugopal K.

2001-01-01

An actuator for cycling between first and second positions includes a first shaped memory alloy (SMA) leg, a second SMA leg. At least one heating/cooling device is thermally connected to at least one of the legs, each heating/cooling device capable of simultaneously heating one leg while cooling the other leg. The heating/cooling devices can include thermoelectric and/or thermoionic elements.

Architectures for a quantum random access memory

Science.gov (United States)

Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

2008-11-01

A random access memory, or RAM, is a device that, when interrogated, returns the content of a memory location in a memory array. A quantum RAM, or qRAM, allows one to access superpositions of memory sites, which may contain either quantum or classical information. RAMs and qRAMs with n -bit addresses can access 2n memory sites. Any design for a RAM or qRAM then requires O(2n) two-bit logic gates. At first sight this requirement might seem to make large scale quantum versions of such devices impractical, due to the difficulty of constructing and operating coherent devices with large numbers of quantum logic gates. Here we analyze two different RAM architectures (the conventional fanout and the “bucket brigade”) and propose some proof-of-principle implementations, which show that, in principle, only O(n) two-qubit physical interactions need take place during each qRAM call. That is, although a qRAM needs O(2n) quantum logic gates, only O(n) need to be activated during a memory call. The resulting decrease in resources could give rise to the construction of large qRAMs that could operate without the need for extensive quantum error correction.

Oxygen-ion-migration-modulated bipolar resistive switching and complementary resistive switching in tungsten/indium tin oxide/gold memory device

Science.gov (United States)

Wu, Xinghui; Zhang, Qiuhui; Cui, Nana; Xu, Weiwei; Wang, Kefu; Jiang, Wei; Xu, Qixing

2018-06-01

In this paper, we report our investigation of room-temperature-fabricated tungsten/indium tin oxide/gold (W/ITO/Au) resistive random access memory (RRAM), which exhibits asymmetric bipolar resistive switching (BRS) behavior. The device displays good write/erase endurance and data retention properties. The device shows complementary resistive switching (CRS) characteristics after controlling the compliance current. A WO x layer electrically formed at the W/ITO in the forming process. Mobile oxygen ions within ITO migrate toward the electrode/ITO interface and produce a semiconductor-like layer that acts as a free-carrier barrier. The CRS characteristic here can be elucidated in light of the evolution of an asymmetric free-carrier blocking layer at the electrode/ITO interface.

Conducting polymer based biomolecular electronic devices

Indian Academy of Sciences (India)

Conducting polymers; LB films; biosensor microactuators; monolayers. ... have been projected for applications for a wide range of biomolecular electronic devices such as optical, electronic, drug-delivery, memory and biosensing devices.

Semiconductor-based, large-area, flexible, electronic devices

Science.gov (United States)

Goyal, Amit [Knoxville, TN

2011-03-15

Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Application of reflective memory network in Tokamak fast controller

International Nuclear Information System (INIS)

Weng Chuqiao; Zhang Ming; Liu Rui; Zheng Wei; Zhuang Ge

2014-01-01

A specific application of reflective memory network in Tokamak fast controller was introduced in this paper. The PMC-5565 reflective memory card and ACC-5565 network hub were used to build a reflective memory real-time network to test its real- time function. The real-time, rapidity and determinacy of the time delay for fast controller controlling power device under the reflective memory network were tested in the LabVIEW RT real-time operation system. Depending on the reflective memory technology, the data in several fast controllers were synchronized, and multiple control tasks using a single control task were finished. The experiment results show that the reflective memory network can meet the real-time requirements for fast controller to perform the feedback control over devices. (authors)

Pulsed ion-beam assisted deposition of Ge nanocrystals on SiO2 for non-volatile memory device

International Nuclear Information System (INIS)

Stepina, N.P.; Dvurechenskii, A.V.; Armbrister, V.A.; Kirienko, V.V.; Novikov, P.L.; Kesler, V.G.; Gutakovskii, A.K.; Smagina, Z.V.; Spesivtzev, E.V.

2008-01-01

A floating gate memory structure, utilizing Ge nanocrystals (NCs) deposited on tunnel SiO 2 , have been fabricated using pulsed low energy ion-beam induced molecular-beam deposition (MBD) in ultra-high vacuum. The ion-beam action is shown to stimulate the nucleation of Ge NCs when being applied after thin Ge layer deposition. Growth conditions for independent change of NCs size and array density were established allowing to optimize the structure parameters required for memory device. Activation energy E = 0.25 eV was determined from the temperature dependence of NCs array density. Monte Carlo simulation has shown that the process, determining NCs array density, is the surface diffusion. Embedding of the crystalline Ge dots into silicon oxide was carried out by selective oxidation of Si(100)/SiO 2 /Ge(NCs)/poly-Si structure. MOS-capacitor obtained after oxidation showed a hysteresis in its C-V curves attributed to charge retention in the Ge dots

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

Science.gov (United States)

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

Bank switched memory interface for an image processor

International Nuclear Information System (INIS)

Barron, M.; Downward, J.

1980-09-01

A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

Science.gov (United States)

Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

2012-11-01

We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

Nano-islands Based Charge Trapping Memory: A Scalability Study

KAUST Repository

Elatab, Nazek; Saadat, Irfan; Saraswat, Krishna; Nayfeh, Ammar

2017-01-01

Zinc-oxide (ZnO) and zirconia (ZrO2) metal oxides have been studied extensively in the past few decades with several potential applications including memory devices. In this work, a scalability study, based on the ITRS roadmap, is conducted on memory devices with ZnO and ZrO2 nano-islands charge trapping layer. Both nano-islands are deposited using atomic layer deposition (ALD), however, the different sizes, distribution and properties of the materials result in different memory performance. The results show that at the 32-nm node charge trapping memory with 127 ZrO2 nano-islands can provide a 9.4 V memory window. However, with ZnO only 31 nano-islands can provide a window of 2.5 V. The results indicate that ZrO2 nano-islands are more promising than ZnO in scaled down devices due to their higher density, higher-k, and absence of quantum confinement effects.

Nano-islands Based Charge Trapping Memory: A Scalability Study

KAUST Repository

Elatab, Nazek

2017-10-19

Zinc-oxide (ZnO) and zirconia (ZrO2) metal oxides have been studied extensively in the past few decades with several potential applications including memory devices. In this work, a scalability study, based on the ITRS roadmap, is conducted on memory devices with ZnO and ZrO2 nano-islands charge trapping layer. Both nano-islands are deposited using atomic layer deposition (ALD), however, the different sizes, distribution and properties of the materials result in different memory performance. The results show that at the 32-nm node charge trapping memory with 127 ZrO2 nano-islands can provide a 9.4 V memory window. However, with ZnO only 31 nano-islands can provide a window of 2.5 V. The results indicate that ZrO2 nano-islands are more promising than ZnO in scaled down devices due to their higher density, higher-k, and absence of quantum confinement effects.

High-speed noise-free optical quantum memory

Science.gov (United States)

Kaczmarek, K. T.; Ledingham, P. M.; Brecht, B.; Thomas, S. E.; Thekkadath, G. S.; Lazo-Arjona, O.; Munns, J. H. D.; Poem, E.; Feizpour, A.; Saunders, D. J.; Nunn, J.; Walmsley, I. A.

2018-04-01

Optical quantum memories are devices that store and recall quantum light and are vital to the realization of future photonic quantum networks. To date, much effort has been put into improving storage times and efficiencies of such devices to enable long-distance communications. However, less attention has been devoted to building quantum memories which add zero noise to the output. Even small additional noise can render the memory classical by destroying the fragile quantum signatures of the stored light. Therefore, noise performance is a critical parameter for all quantum memories. Here we introduce an intrinsically noise-free quantum memory protocol based on two-photon off-resonant cascaded absorption (ORCA). We demonstrate successful storage of GHz-bandwidth heralded single photons in a warm atomic vapor with no added noise, confirmed by the unaltered photon-number statistics upon recall. Our ORCA memory meets the stringent noise requirements for quantum memories while combining high-speed and room-temperature operation with technical simplicity, and therefore is immediately applicable to low-latency quantum networks.

Cyclic degradation of antagonistic shape memory actuated structures

International Nuclear Information System (INIS)

Sofla, A Y N; Elzey, D M; Wadley, H N G

2008-01-01

Antagonistic shape memory actuated structures exploit opposing pairs of one-way shape memory alloy (SMA) linear actuators to create devices capable of a fully reversible response. Unlike many conventional reversible SMA devices they do not require bias force components (springs) to return them to their pre-actuated configuration. However, the repeated use of SMA antagonistic devices results in the accumulation of plastic strain in the actuators which can diminish their actuation stroke. We have investigated this phenomenon and the effect of shape memory alloy pre-strain upon it for near equi-atomic NiTi actuators. We find that the degradation eventually stabilizes during cycling. A thermomechanical treatment has been found to significantly reduce degradation in cyclic response of the actuators

Shape-memory polymer foam device for treating aneurysms

Energy Technology Data Exchange (ETDEWEB)

Ortega, Jason M.; Benett, William J.; Small, Ward; Wilson, Thomas S.; Maitland, Duncan J; Hartman, Jonathan

2017-05-30

A system for treating an aneurysm in a blood vessel or vein, wherein the aneurysm has a dome, an interior, and a neck. The system includes a shape memory polymer foam in the interior of the aneurysm between the dome and the neck. The shape memory polymer foam has pores that include a first multiplicity of pores having a first pore size and a second multiplicity of pores having a second pore size. The second pore size is larger than said first pore size. The first multiplicity of pores are located in the neck of the aneurysm. The second multiplicity of pores are located in the dome of the aneurysm.

S-Band POSIX Device Drivers for RTEMS

Science.gov (United States)

Lux, James P.; Lang, Minh; Peters, Kenneth J.; Taylor, Gregory H.

2011-01-01

This is a set of POSIX device driver level abstractions in the RTEMS RTOS (Real-Time Executive for Multiprocessor Systems real-time operating system) to SBand radio hardware devices that have been instantiated in an FPGA (field-programmable gate array). These include A/D (analog-to-digital) sample capture, D/A (digital-to-analog) sample playback, PLL (phase-locked-loop) tuning, and PWM (pulse-width-modulation)-controlled gain. This software interfaces to Sband radio hardware in an attached Xilinx Virtex-2 FPGA. It uses plug-and-play device discovery to map memory to device IDs. Instead of interacting with hardware devices directly, using direct-memory mapped access at the application level, this driver provides an application programming interface (API) offering that easily uses standard POSIX function calls. This simplifies application programming, enables portability, and offers an additional level of protection to the hardware. There are three separate device drivers included in this package: sband_device (ADC capture and DAC playback), pll_device (RF front end PLL tuning), and pwm_device (RF front end AGC control).

Influence of Cu diffusion conditions on the switching of Cu-SiO2-based resistive memory devices

International Nuclear Information System (INIS)

Thermadam, S. Puthen; Bhagat, S.K.; Alford, T.L.; Sakaguchi, Y.; Kozicki, M.N.; Mitkova, M.

2010-01-01

This paper presents a study of Cu diffusion at various temperatures in thin SiO 2 films and the influence of diffusion conditions on the switching of Programmable Metallization Cell (PMC) devices formed from such Cu-doped films. Film composition and diffusion products were analyzed using secondary ion mass spectroscopy, Rutherford backscattering spectrometry, X-ray diffraction and Raman spectroscopy methods. We found a strong dependence of the diffused Cu concentration, which varied between 0.8 at.% and 10 -3 at.%, on the annealing temperature. X-ray diffraction and Raman studies revealed that Cu does not react with the SiO 2 network and remains in elemental form after diffusion for the annealing conditions used. PMC resistive memory cells were fabricated with such Cu-diffused SiO 2 films and device performance, including the stability of the switching voltage, is discussed in the context of the material characteristics.

Brownmillerite thin films as fast ion conductors for ultimate-performance resistance switching memory.

Science.gov (United States)

Acharya, Susant Kumar; Jo, Janghyun; Raveendra, Nallagatlla Venkata; Dash, Umasankar; Kim, Miyoung; Baik, Hionsuck; Lee, Sangik; Park, Bae Ho; Lee, Jae Sung; Chae, Seung Chul; Hwang, Cheol Seong; Jung, Chang Uk

2017-07-27

An oxide-based resistance memory is a leading candidate to replace Si-based flash memory as it meets the emerging specifications for future memory devices. The non-uniformity in the key switching parameters and low endurance in conventional resistance memory devices are preventing its practical application. Here, a novel strategy to overcome the aforementioned challenges has been unveiled by tuning the growth direction of epitaxial brownmillerite SrFeO 2.5 thin films along the SrTiO 3 [111] direction so that the oxygen vacancy channels can connect both the top and bottom electrodes rather directly. The controlled oxygen vacancy channels help reduce the randomness of the conducting filament (CF). The resulting device displayed high endurance over 10 6 cycles, and a short switching time of ∼10 ns. In addition, the device showed very high uniformity in the key switching parameters for device-to-device and within a device. This work demonstrates a feasible example for improving the nanoscale device performance by controlling the atomic structure of a functional oxide layer.

Optical quantum memory

Science.gov (United States)

Lvovsky, Alexander I.; Sanders, Barry C.; Tittel, Wolfgang

2009-12-01

Quantum memory is essential for the development of many devices in quantum information processing, including a synchronization tool that matches various processes within a quantum computer, an identity quantum gate that leaves any state unchanged, and a mechanism to convert heralded photons to on-demand photons. In addition to quantum computing, quantum memory will be instrumental for implementing long-distance quantum communication using quantum repeaters. The importance of this basic quantum gate is exemplified by the multitude of optical quantum memory mechanisms being studied, such as optical delay lines, cavities and electromagnetically induced transparency, as well as schemes that rely on photon echoes and the off-resonant Faraday interaction. Here, we report on state-of-the-art developments in the field of optical quantum memory, establish criteria for successful quantum memory and detail current performance levels.

Increment memory module for spectrometric data recording

International Nuclear Information System (INIS)

Zhuchkov, A.A.; Myagkikh, A.I.

1988-01-01

Incremental memory unit designed to input differential energy spectra of nuclear radiation is described. ROM application as incremental device has allowed to reduce the number of elements and do simplify information readout from the unit. 12-bit 2048 channels present memory unit organization. The device is connected directly with the bus of microprocessor systems similar to KR 580. Incrementation maximal time constitutes 3 mks. It is possible to use this unit in multichannel counting mode

Characterizations and thermal stability improvement of phase-change memory device containing Ce-doped GeSbTe films

Energy Technology Data Exchange (ETDEWEB)

Huang, Yu-Jen; Tsai, Min-Chuan; Wang, Chiung-Hsin; Hsieh, Tsung-Eong, E-mail: tehsieh@mail.nctu.edu.tw

2012-02-29

Phase-transition temperature of GeSbTe (GST) chalcogenide film was drastically increased from 159 to 236 Degree-Sign C by cerium (Ce) doping (up to 8.6 at.%) without altering the resistivity property of GST. Grain refinement via the solid-solution mechanism and the amplification of p-type semiconducting behavior in Ce-doped GST were observed. They were correlated with the enhancement of thermal stability and data retention property of GST as revealed by exothermal and isothermal analyses. Phase-change memory (PCM) device characterized at various temperatures revealed an effective thermal stability improvement on the threshold voltage of PCM device by Ce doping. - Highlights: Black-Right-Pointing-Pointer Ce doping increased phase-change temperature of GST from 159 to 236 Degree-Sign C. Black-Right-Pointing-Pointer No suppression of resistivity level in amorphous Ce-doped GST. Black-Right-Pointing-Pointer Resistance ratio of amorphous and crystalline Ce-doped GST was preserved at 10{sup 5}. Black-Right-Pointing-Pointer p-type semiconducting behavior of GST was enhanced by Ce-doping. Black-Right-Pointing-Pointer Ce-doping improved the thermal stability of threshold voltage of GST PCM device.

Holographic associative memories in document retrieval systems

International Nuclear Information System (INIS)

Becker, P.J.; Bolle, H.; Keller, A.; Kistner, W.; Riecke, W.D.; Wagner, U.

1979-03-01

The objective of this work was the implementation of a holographic memory with associative readout for a document retrieval system. Taking advantage of the favourable properties of holography - associative readout of the memory, parallel processing in the response store - may give shorter response times than sequentially organized data memories. Such a system may also operate in the interactive mode including chain associations. In order to avoid technological difficulties, the experimental setup made use of commercially available components only. As a result an improved holographic structure is proposed which uses volume holograms in photorefractive crystals as storage device. In two chapters of appendix we give a review of the state of the art of electrooptic devices for coherent optical data processing and of competing technologies (semiconductor associative memories and associative program systems). (orig.) [de

Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

Science.gov (United States)

Shin, Sunhae; Rok Kim, Kyung

2015-06-01

In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

Application of phase-change materials in memory taxonomy

OpenAIRE

Wang, Lei; Tu, Liang; Wen, Jing

2017-01-01

Abstract Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other...

Device simulation of charge collection and single-event upset

International Nuclear Information System (INIS)

Dodd, P.E.

1996-01-01

In this paper the author reviews the current status of device simulation of ionizing-radiation-induced charge collection and single-event upset (SEU), with an emphasis on significant results of recent years. The author presents an overview of device-modeling techniques applicable to the SEU problem and the unique challenges this task presents to the device modeler. He examines unloaded simulations of radiation-induced charge collection in simple p/n diodes, SEU in dynamic random access memories (DRAM's), and SEU in static random access memories (SRAM's). The author concludes with a few thoughts on future issues likely to confront the SEU device modeler

An Artificial Flexible Visual Memory System Based on an UV-Motivated Memristor.

Science.gov (United States)

Chen, Shuai; Lou, Zheng; Chen, Di; Shen, Guozhen

2018-02-01

For the mimicry of human visual memory, a prominent challenge is how to detect and store the image information by electronic devices, which demands a multifunctional integration to sense light like eyes and to memorize image information like the brain by transforming optical signals to electrical signals that can be recognized by electronic devices. Although current image sensors can perceive simple images in real time, the image information fades away when the external image stimuli are removed. The deficiency between the state-of-the-art image sensors and visual memory system inspires the logical integration of image sensors and memory devices to realize the sensing and memory process toward light information for the bionic design of human visual memory. Hence, a facile architecture is designed to construct artificial flexible visual memory system by employing an UV-motivated memristor. The visual memory arrays can realize the detection and memory process of UV light distribution with a patterned image for a long-term retention and the stored image information can be reset by a negative voltage sweep and reprogrammed to the same or an other image distribution, which proves the effective reusability. These results provide new opportunities for the mimicry of human visual memory and enable the flexible visual memory device to be applied in future wearable electronics, electronic eyes, multifunctional robotics, and auxiliary equipment for visual handicapped. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

An overview of Experimental Condensed Matter Physics in Argentina by 2014, and Oxides for Non Volatile Memory Devices: The MeMOSat Project

Science.gov (United States)

Levy, Pablo

2015-03-01

In the first part of my talk, I will describe the status of the experimental research in Condensed Matter Physics in Argentina, biased towards developments related to micro and nanotechnology. In the second part, I will describe the MeMOSat Project, a consortium aimed at producing non-volatile memory devices to work in aggressive environments, like those found in the aerospace and nuclear industries. Our devices rely on the Resistive Switching mechanism, which produces a permanent but reversible change in the electrical resistance across a metal-insulator-metal structure by means of a pulsed protocol of electrical stimuli. Our project is devoted to the study of Memory Mechanisms in Oxides (MeMO) in order to establish a technological platform that tests the Resistive RAM (ReRAM) technology for aerospace applications. A review of MeMOSat's activities is presented, covering the initial Proof of Concept in ceramic millimeter sized samples; the study of different oxide-metal couples including (LaPr)2/3Ca1/3MnO, La2/3Ca1/3MnO3, YBa2Cu3O7, TiO2, HfO2, MgO and CuO; and recent miniaturized arrays of micrometer sized devices controlled by in-house designed electronics, which were launched with the BugSat01 satellite in June2014 by the argentinian company Satellogic.

Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

Science.gov (United States)

Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

2015-09-01

Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

Hf layer thickness dependence of resistive switching characteristics of Ti/Hf/HfO2/Au resistive random access memory device

Science.gov (United States)

Nakajima, Ryo; Azuma, Atsushi; Yoshida, Hayato; Shimizu, Tomohiro; Ito, Takeshi; Shingubara, Shoso

2018-06-01

Resistive random access memory (ReRAM) devices with a HfO2 dielectric layer have been studied extensively owing to the good reproducibility of their SET/RESET switching properties. Furthermore, it was reported that a thin Hf layer next to a HfO2 layer stabilized switching properties because of the oxygen scavenging effect. In this work, we studied the Hf thickness dependence of the resistance switching characteristics of a Ti/Hf/HfO2/Au ReRAM device. It is found that the optimum Hf thickness is approximately 10 nm to obtain good reproducibility of SET/RESET voltages with a small RESET current. However, when the Hf thickness was very small (∼2 nm), the device failed after the first RESET process owing to the very large RESET current. In the case of a very thick Hf layer (∼20 nm), RESET did not occur owing to the formation of a leaky dielectric layer. We observed the occurrence of multiple resistance states in the RESET process of the device with a Hf thickness of 10 nm by increasing the RESET voltage stepwise.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

Science.gov (United States)

Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro

2013-04-01

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Record Endurance for Single-Walled Carbon Nanotube–Based Memory Cell

Directory of Open Access Journals (Sweden)

Yang Y

2010-01-01

Full Text Available Abstract We study memory devices consisting of single-walled carbon nanotube transistors with charge storage at the SiO2/nanotube interface. We show that this type of memory device is robust, withstanding over 105 operating cycles, with a current drive capability up to 10−6 A at 20 mV drain bias, thus competing with state-of-the-art Si-devices. We find that the device performance depends on temperature and pressure, while both endurance and data retention are improved in vacuum.

Impacts of post-metallization annealing on the memory performance of Ti/HfO2-based resistive memory

International Nuclear Information System (INIS)

Chen, Pang-Shiu; Chen, Yu-Sheng; Lee, Heng-Yuan

2013-01-01

Impacts of post-metallization annealing (PMA) on bipolar resistance switching of Ti/HfO x stacked films were investigated. A Ti capping film as a scavenging layer with assistance of PMA is used to tune the dielectric strength of the 10-nm-thick HfO x layer. The polycrystalline microstructure of 10-nm-thick HfO x seems immune to the temperature of PMA in this work. The initial resistance and forming voltage in the Ti/HfO x devices mitigate as the increment of the annealing temperature. With enough annealing temperature (>450 °C), the device shows a good on/off ratio, high temperature operation ability and robust endurance (>10 6 cycles). Through the reaction between Ti and HfO x at 500 °C, the abundant oxygen ions are depleted from the insulator and the left charge-defects building conductive percolative paths in the dielectric layer. The operation-polarity independence of the form-free HfO x device in initial state is demonstrated. The forming-free memory with initial low resistance of 800 Ω at 0.1 V can be operated with stable bipolar resistance switching via initially positive or negative voltage sweep. The formless device with 10 nm thick HfO x also exhibits excellent nonvolatile memory performances, including enough on/off ratio, improved HRS uniformity and good high temperature retention (3 × 10 4 s at 200 °C). The results of this work suggest that the PMA temperature will affect the memory window and cycling reliability of the Ti/HfO x -based resistive memory. Optimum temperature (450 °C) will improve the memory performance of the Ti/HfO x stacked layer. (paper)

Electroforming free resistive switching memory in two-dimensional VOx nanosheets

KAUST Repository

Hota, Mrinal Kanti

2015-10-21

We report two-dimensional VOx nanosheets containing multi-oxidation states (V5+, V4+, and V3+), prepared by a hydrothermal process for potential applications in resistive switching devices. The experimental results demonstrate a highly reproducible, electroforming-free, low SET bias bipolar resistive switching memory performance with endurance for more than 100 cycles maintaining OFF/ON ratio of ∼60 times. These devices show better memory performance as compared to previously reported VOx thin film based devices. The memory mechanism in VOx is proposed to be originated from the migration of oxygen vacancies/ions, an influence of the bottom electrode and existence of multi-oxidation states.

Copper oxide resistive switching memory for e-textile

Directory of Open Access Journals (Sweden)

Jin-Woo Han

2011-09-01

Full Text Available A resistive switching memory suitable for integration into textiles is demonstrated on a copper wire network. Starting from copper wires, a Cu/CuxO/Pt sandwich structure is fabricated. The active oxide film is produced by simple thermal oxidation of Cu in atmospheric ambient. The devices display a resistance switching ratio of 102 between the high and low resistance states. The memory states are reversible and retained over 107 seconds, with the states remaining nondestructive after multiple read operations. The presented device on the wire network can potentially offer a memory for integration into smart textile.

Scoliosis correction with shape-memory metal: results of an experimental study

OpenAIRE

Wever, D.; Elstrodt, J.; Veldhuizen, A.; v Horn, J.

2001-01-01

The biocompatibility and functionality of a new scoliosis correction device, based on the properties of the shape-memory metal nickel-titanium alloy, were studied. With this device, the shape recovery forces of a shape-memory metal rod are used to achieve a gradual three-dimensional scoliosis correction. In the experimental study the action of the new device was inverted: the device was used to induce a scoliotic curve instead of correcting one. Surgical procedures were performed in six pigs....

Pulsed ion-beam assisted deposition of Ge nanocrystals on SiO{sub 2} for non-volatile memory device

Energy Technology Data Exchange (ETDEWEB)

Stepina, N.P. [Institute of Semiconductor Physics, Lavrenteva 13, 630090 Novosibirsk (Russian Federation)], E-mail: nstepina@mail.ru; Dvurechenskii, A.V.; Armbrister, V.A.; Kirienko, V.V.; Novikov, P.L.; Kesler, V.G.; Gutakovskii, A.K.; Smagina, Z.V.; Spesivtzev, E.V. [Institute of Semiconductor Physics, Lavrenteva 13, 630090 Novosibirsk (Russian Federation)

2008-11-03

A floating gate memory structure, utilizing Ge nanocrystals (NCs) deposited on tunnel SiO{sub 2}, have been fabricated using pulsed low energy ion-beam induced molecular-beam deposition (MBD) in ultra-high vacuum. The ion-beam action is shown to stimulate the nucleation of Ge NCs when being applied after thin Ge layer deposition. Growth conditions for independent change of NCs size and array density were established allowing to optimize the structure parameters required for memory device. Activation energy E = 0.25 eV was determined from the temperature dependence of NCs array density. Monte Carlo simulation has shown that the process, determining NCs array density, is the surface diffusion. Embedding of the crystalline Ge dots into silicon oxide was carried out by selective oxidation of Si(100)/SiO{sub 2} /Ge(NCs)/poly-Si structure. MOS-capacitor obtained after oxidation showed a hysteresis in its C-V curves attributed to charge retention in the Ge dots.

Graphene resistive random memory — the promising memory device in next generation

International Nuclear Information System (INIS)

Wang Xue-Feng; Zhao Hai-Ming; Yang Yi; Ren Tian-Ling

2017-01-01

Graphene-based resistive random access memory (GRRAM) has grasped researchers’ attention due to its merits compared with ordinary RRAM. In this paper, we briefly review different types of GRRAMs. These GRRAMs can be divided into two categories: graphene RRAM and graphene oxide (GO)/reduced graphene oxide (rGO) RRAM. Using graphene as the electrode, GRRAM can own many good characteristics, such as low power consumption, higher density, transparency, SET voltage modulation, high uniformity, and so on. Graphene flakes sandwiched between two dielectric layers can lower the SET voltage and achieve multilevel switching. Moreover, the GRRAM with rGO and GO as the dielectric or electrode can be simply fabricated. Flexible and high performance RRAM and GO film can be modified by adding other materials layer or making a composite with polymer, nanoparticle, and 2D materials to further improve the performance. Above all, GRRAM shows huge potential to become the next generation memory. (topical reviews)

3D Printing: 3D Printing of Shape Memory Polymers for Flexible Electronic Devices (Adv. Mater. 22/2016).

Science.gov (United States)

Zarek, Matt; Layani, Michael; Cooperstein, Ido; Sachyani, Ela; Cohn, Daniel; Magdassi, Shlomo

2016-06-01

On page 4449, D. Cohn, S. Magdassi, and co-workers describe a general and facile method based on 3D printing of methacrylated macromonomers to fabricate shape-memory objects that can be used in flexible and responsive electrical circuits. Such responsive objects can be used in the fabrication of soft robotics, minimal invasive medical devices, sensors, and wearable electronics. The use of 3D printing overcomes the poor processing characteristics of thermosets and enables complex geometries that are not easily accessible by other techniques. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Materials and Physics Challenges for Spin Transfer Torque Magnetic Random Access Memories

Energy Technology Data Exchange (ETDEWEB)

Heinonen, O.

2014-10-05

Magnetic random access memories utilizing the spin transfer torque effect for writing information are a strong contender for non-volatile memories scalable to the 20 nm node, and perhaps beyond. I will here examine how these devices behave as the device size is scaled down from 70 nm size to 20 nm. As device sizes go below ~50 nm, the size becomes comparable to intrinsic magnetic length scales and the device behavior does not simply scale with size. This has implications for the device design and puts additional constraints on the materials in the device.

Axially modulated arch resonator for logic and memory applications

KAUST Repository

Hafiz, Md Abdullah Al

2018-01-17

We demonstrate reconfigurable logic and random access memory devices based on an axially modulated clamped-guided arch resonator. The device is electrostatically actuated and the motional signal is capacitively sensed, while the resonance frequency is modulated through an axial electrostatic force from the guided side of the microbeam. A multi-physics finite element model is used to verify the effectiveness of the axial modulation. We present two case studies: first, a reconfigurable two-input logic gate based on the linear resonance frequency modulation, and second, a memory element based on the hysteretic frequency response of the resonator working in the nonlinear regime. The energy consumptions of the device for both logic and memory operations are in the range of picojoules, promising for energy efficient alternative computing paradigm.

NAND flash memory technologies

CERN Document Server

Aritome, Seiichi

2016-01-01

This book discusses basic and advanced NAND flash memory technologies, including the principle of NAND flash, memory cell technologies, multi-bits cell technologies, scaling challenges of memory cell, reliability, and 3-dimensional cell as the future technology. Chapter 1 describes the background and early history of NAND flash. The basic device structures and operations are described in Chapter 2. Next, the author discusses the memory cell technologies focused on scaling in Chapter 3, and introduces the advanced operations for multi-level cells in Chapter 4. The physical limitations for scaling are examined in Chapter 5, and Chapter 6 describes the reliability of NAND flash memory. Chapter 7 examines 3-dimensional (3D) NAND flash memory cells and discusses the pros and cons in structure, process, operations, scalability, and performance. In Chapter 8, challenges of 3D NAND flash memory are dis ussed. Finally, in Chapter 9, the author summarizes and describes the prospect of technologies and market for the fu...

Material Engineering for Phase Change Memory

Science.gov (United States)

Cabrera, David M.

As semiconductor devices continue to scale downward, and portable consumer electronics become more prevalent there is a need to develop memory technology that will scale with devices and use less energy, while maintaining performance. One of the leading prototypical memories that is being investigated is phase change memory. Phase change memory (PCM) is a non-volatile memory composed of 1 transistor and 1 resistor. The resistive structure includes a memory material alloy which can change between amorphous and crystalline states repeatedly using current/voltage pulses of different lengths and magnitudes. The most widely studied PCM materials are chalcogenides - Germanium-Antimony-Tellerium (GST) with Ge2Sb2Te3 and Germanium-Tellerium (GeTe) being some of the most popular stochiometries. As these cells are scaled downward, the current/voltage needed to switch these materials becomes comparable to the voltage needed to sense the cell's state. The International Roadmap for Semiconductors aims to raise the threshold field of these devices from 66.6 V/mum to be at least 375 V/mum for the year 2024. These cells are also prone to resistance drift between states, leading to bit corruption and memory loss. Phase change material properties are known to influence PCM device performance such as crystallization temperature having an effect on data retention and litetime, while resistivity values in the amorphous and crystalline phases have an effect on the current/voltage needed to write/erase the cell. Addition of dopants is also known to modify the phase change material parameters. The materials G2S2T5, GeTe, with dopants - nitrogen, silicon, titanium, and aluminum oxide and undoped Gallium-Antimonide (GaSb) are studied for these desired characteristics. Thin films of these compositions are deposited via physical vapor deposition at IBM Watson Research Center. Crystallization temperatures are investigated using time resolved x-ray diffraction at Brookhaven National Laboratory

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

Science.gov (United States)

Li, Yue (Inventor); Bruck, Jehoshua (Inventor)

2018-01-01

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Scoliosis correction with shape-memory metal : results of an experimental study

NARCIS (Netherlands)

Elstrodt, JA; Veldhuizen, AG; van Horn, [No Value

The biocompatibility and functionality of a new scoliosis correction device, based on the properties of the shape-memory metal nickel-titanium alloy, were studied. With this device, the shape recovery forces of a shape-memory metal rod are used to achieve a gradual three-dimensional scoliosis

Review of radiation effects on ReRAM devices and technology

Science.gov (United States)

Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

2017-08-01

A review of the ionizing radiation effects on resistive random access memory (ReRAM) technology and devices is presented in this article. The review focuses on vertical devices exhibiting bipolar resistance switching, devices that have already exhibited interesting properties and characteristics for memory applications and, in particular, for non-volatile memory applications. Non-volatile memories are important devices for any type of electronic and embedded system, as they are for space applications. In such applications, specific environmental issues related to the existence of cosmic rays and Van Allen radiation belts around the Earth contribute to specific failure mechanisms related to the energy deposition induced by such ionizing radiation. Such effects are important in non-volatile memory as the current leading technology, i.e. flash-based technology, is sensitive to the total ionizing dose (TID) and single-event effects. New technologies such as ReRAM, if competing with or complementing the existing non-volatile area of memories from the point of view of performance, also have to exhibit great reliability for use in radiation environments such as space. This has driven research on the radiation effects of such ReRAM technology, on both the conductive-bridge RAM as well as the valence-change memories, or OxRAM variants of the technology. Initial characterizations of ReRAM technology showed a high degree of resilience to TID, developing researchers’ interest in characterizing such resilience as well as investigating the cause of such behavior. The state of the art of such research is reviewed in this article.

A direct metal transfer method for cross-bar type polymer non-volatile memory applications

International Nuclear Information System (INIS)

Kim, Tae-Wook; Lee, Kyeongmi; Oh, Seung-Hwan; Wang, Gunuk; Kim, Dong-Yu; Jung, Gun-Young; Lee, Takhee

2008-01-01

Polymer non-volatile memory devices in 8 x 8 array cross-bar architecture were fabricated by a non-aqueous direct metal transfer (DMT) method using a two-step thermal treatment. Top electrodes with a linewidth of 2 μm were transferred onto the polymer layer by the DMT method. The switching behaviour of memory devices fabricated by the DMT method was very similar to that of devices fabricated by the conventional shadow mask method. The devices fabricated using the DMT method showed three orders of magnitude of on/off ratio with stable resistance switching, demonstrating that the DMT method can be a simple process to fabricate organic memory array devices

The MONOS memory transistor: application in a radiation-hard nonvolatile RAM

International Nuclear Information System (INIS)

Brown, W.D.

1985-01-01

The MONOS (metal-oxide-nitride-oxide-silicon) device is a prime candidate for use as the nonvolatile memory element in a radiation-hardened RAM (random-access memory). The endurance, retention and radiation properties of MONOS memory transistors have been studied as a function of post nitride deposition annealing. Following the nitride layer deposition, all devices were subjected to an 800 0 C oxidation step and some were then annealed at 900 0 C in nitrogen. The nitrogen anneal produces an increase in memory window size of approximately 40%. The memory window center of the annealed devices is shifted toward more positive voltages and is more stable with endurance cycling. Endurance cycling to 10 9 cycles produces a 20% increase in memory window size and a 60% increase in decay rate. For a radiation total dose of 10 6 rads (Si), the memory window size is essentially unchanged and the decay rate increases approximately 13%. A combination of 10 9 cycles and 10 6 rads (Si) reduces the decades of retention (in sec) from 6.3 to 4.3 for a +- 23-V 16-μsec write/erase pulse. (author)

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

Science.gov (United States)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Single event simulation for memories using accelerated ions

International Nuclear Information System (INIS)

Sakagawa, Y.; Shiono, N.; Mizusawa, T.; Sekiguchi, M.; Sato, K.; Sugai, I.; Hirao, Y.; Nishimura, J.; Hattori, T.

1987-01-01

To evaluate the error immunity of the LSI memories from cosmic rays in space, an irradiation test using accelerated heavy ions is performed. The sensitive regions for 64 K DRAM (Dynamic Random Access Memory) and 4 K SRAM (Static Random Access Memory) are determined from the irradiation test results and the design parameters of the devices. The observed errors can be classified into two types. One is the direct ionization type and the other is the recoil produced error type. Sensitive region is determined for the devices. Error rate estimation methods for both types are proposed and applied to those memories used in space. The error rate of direct ionization exceeds the recoil type by 2 or 3 orders. And the direct ionization is susceptible to shield thickness. (author)

Low-power resistive random access memory by confining the formation of conducting filaments

International Nuclear Information System (INIS)

Huang, Yi-Jen; Lee, Si-Chen; Shen, Tzu-Hsien; Lee, Lan-Hsuan; Wen, Cheng-Yen

2016-01-01

Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO_x/silver nanoparticles/TiO_x/AlTiO_x, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO_x layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

SOLID-STATE STORAGE DEVICE FLASH TRANSLATION LAYER

DEFF Research Database (Denmark)

2017-01-01

Embodiments of the present invention include a method for storing a data page d on a solid-state storage device, wherein the solid-state storage device is configured to maintain a mapping table in a Log-Structure Merge (LSM) tree having a C0 component which is a random access memory (RAM) device...

Initial Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

Science.gov (United States)

MacLeond, Todd C.; Sims, W. Herb; Varnavas,Kosta A.; Ho, Fat D.

2011-01-01

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite that launched in November 2010. The memory device being tested is a commercial Ramtron Inc. 512K memory device. The circuit was designed into the satellite avionics and is not used to control the satellite. The test consists of writing and reading data with the ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is sent to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test is one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The initial data from the test is presented. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

Writing to and reading from a nano-scale crossbar memory based on memristors

International Nuclear Information System (INIS)

Vontobel, Pascal O; Robinett, Warren; Kuekes, Philip J; Stewart, Duncan R; Straznicky, Joseph; Stanley Williams, R

2009-01-01

We present a design study for a nano-scale crossbar memory system that uses memristors with symmetrical but highly nonlinear current-voltage characteristics as memory elements. The memory is non-volatile since the memristors retain their state when un-powered. In order to address the nano-wires that make up this nano-scale crossbar, we use two coded demultiplexers implemented using mixed-scale crossbars (in which CMOS-wires cross nano-wires and in which the crosspoint junctions have one-time configurable memristors). This memory system does not utilize the kind of devices (diodes or transistors) that are normally used to isolate the memory cell being written to and read from in conventional memories. Instead, special techniques are introduced to perform the writing and the reading operation reliably by taking advantage of the nonlinearity of the type of memristors used. After discussing both writing and reading strategies for our memory system in general, we focus on a 64 x 64 memory array and present simulation results that show the feasibility of these writing and reading procedures. Besides simulating the case where all device parameters assume exactly their nominal value, we also simulate the much more realistic case where the device parameters stray around their nominal value: we observe a degradation in margins, but writing and reading is still feasible. These simulation results are based on a device model for memristors derived from measurements of fabricated devices in nano-scale crossbars using Pt and Ti nano-wires and using oxygen-depleted TiO 2 as the switching material.

Hybrid dual gate ferroelectric memory for multilevel information storage

KAUST Repository

Khan, Yasser

2015-01-01

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200°C), and demonstrate excellent performance with high hole mobility of 2.7 cm2 V-1 s-1, large memory window of ∼18 V, and a low sub-threshold swing ∼-4 V dec-1. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.

A fast ECL bus memory: dual input memory

International Nuclear Information System (INIS)

Cesaroni, F.; Pascale, G.; Gentile, S.; Gao, Z.

1992-01-01

A fast and flexible dual input memory (DIM) has been constructed as single CAMAC unit. The device has been designed to receive via front panel two 16-bit data words, which can be stored in sequential mode into a memory and, at the same time, presented on the output. The design implemented also the possibility to connect 16-bit differential ECL outputs of many DIMs modules on the same bus. Its timing characteristics for writing and reading into and from memory is only 20 ns. This makes the module a useful element for all kinds of fast acquisition systems, as tempory storage of data, or data source or spy module. It will be, for example, used in the new energy tripper of the L3 experiment, designed for 8x8 bunch mode operation of LEP in 1992. (orig.)

Multithreaded Asynchronous Graph Traversal for In-Memory and Semi-External Memory

KAUST Repository

Pearce, Roger

2010-11-01

Processing large graphs is becoming increasingly important for many domains such as social networks, bioinformatics, etc. Unfortunately, many algorithms and implementations do not scale with increasing graph sizes. As a result, researchers have attempted to meet the growing data demands using parallel and external memory techniques. We present a novel asynchronous approach to compute Breadth-First-Search (BFS), Single-Source-Shortest-Paths, and Connected Components for large graphs in shared memory. Our highly parallel asynchronous approach hides data latency due to both poor locality and delays in the underlying graph data storage. We present an experimental study applying our technique to both In-Memory and Semi-External Memory graphs utilizing multi-core processors and solid-state memory devices. Our experiments using synthetic and real-world datasets show that our asynchronous approach is able to overcome data latencies and provide significant speedup over alternative approaches. For example, on billion vertex graphs our asynchronous BFS scales up to 14x on 16-cores. © 2010 IEEE.

Effect of CuPc layer insertion on the memory performance of CdS nanocomposite diodes

Energy Technology Data Exchange (ETDEWEB)

Tripathi, S.K., E-mail: surya@pu.ac.in; Kaur, Ramneek; Jyoti

2016-09-15

Highlights: • CdS nanocomposite as an active layer investigated for memory device application. • Effect of copper phthalocyanine layer insertion on the memory performance studied. • Bipolar switching behaviour with high ON/OFF ratio ∼1.4 × 10{sup 4}. • Series resistance and interface states dominate the electrical properties of the device. - Abstract: In the present work, semiconductor diodes with CdS nanocomposite as an active layer have been fabricated and investigated for memory device applications. The effect of copper phthalocyanine (CuPc) layer insertion between the bottom electrode and CdS nanocomposite has been studied. I–V characteristics show electrical hysteresis behaviour vital for memory storage application. The as-fabricated devices exhibit bipolar switching behaviour with OFF to ON state transition at positive bias and vice versa. Device with CuPc layer exhibits I{sub ON}/I{sub OFF} ratio ∼ 1.4 × 10{sup 4}. Possible conduction mechanism has been described on the basis of theoretical current conduction models. The frequency dispersion capacitance, series resistance and conductance of the devices have been studied and discussed. At low frequency, the series resistance and the interface states dominate the electrical properties of the device. The results indicate that the multilayered devices open up the possibility of new generation non-volatile memory devices with low cost, high density and stability.

Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

Science.gov (United States)

Li, Wen; Guo, Fengning; Ling, Haifeng; Liu, Hui; Yi, Mingdong; Zhang, Peng; Wang, Wenjun; Xie, Linghai; Huang, Wei

2018-01-01

In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG 3 ) is reported. The WG 3 NSs are prepared from phase separation by spin-coating blend solutions of WG 3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG 3 film, the device based on WG 3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10 4 s), and reliable switching properties. A quantitative study of the WG 3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG 3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG 3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Proof of Concept Study for the Design, Manufacturing, and Testing of a Patient-Specific Shape Memory Device for Treatment of Unicoronal Craniosynostosis.

Science.gov (United States)

Borghi, Alessandro; Rodgers, Will; Schievano, Silvia; Ponniah, Allan; Jeelani, Owase; Dunaway, David

2018-01-01

Treatment of unicoronal craniosynostosis is a surgically challenging problem, due to the involvement of coronal suture and cranial base, with complex asymmetries of the calvarium and orbit. Several techniques for correction have been described, including surgical bony remodeling, early strip craniotomy with orthotic helmet remodeling and distraction. Current distraction devices provide unidirectional forces and have had very limited success. Nitinol is a shape memory alloy that can be programmed to the shape of a patient-specific anatomy by means of thermal treatment.In this work, a methodology to produce a nitinol patient-specific distractor is presented: computer tomography images of a 16-month-old patient with unicoronal craniosynostosis were processed to create a 3-dimensional model of his skull and define the ideal shape postsurgery. A mesh was produced from a nitinol sheet, formed to the ideal skull shape and heat treated to be malleable at room temperature. The mesh was afterward deformed to be attached to a rapid prototyped plastic skull, replica of the patient initial anatomy. The mesh/skull construct was placed in hot water to activate the mesh shape memory property: the deformed plastic skull was computed tomography scanned for comparison of its shape with the initial anatomy and with the desired shape, showing that the nitinol mesh had been able to distract the plastic skull to a shape close to the desired one.The shape-memory properties of nitinol allow for the design and production of patient-specific devices able to deliver complex, preprogrammable shape changes.

Nano-memory-element applications of carbon nanocapsule encapsulating potassium ions: molecular dynamics study

International Nuclear Information System (INIS)

Kang, Jeong Won; Hwang, Ho Jung

2004-01-01

We investigated the internal dynamics of ionic fluidic shuttle memory elements consisting of potassium ions encapsulated in C 640 nanocapsules. The systems proposed were the encapsulated-ion shuttle memory devices such as (13 K + ) at C 640 , (3 K + -C 60 -2 K + ) at C 640 and (5 K + -C 60 ) at C 640 . The energetics and the operating responses of ionic fluidic shuttle memory devices, such as transitions between the two states of the C 640 capsule, were examined by using classical molecular dynamics simulations of the shuttle media in the C 640 capsule under external force fields. The operating force fields for stable operations of the shuttle memory device were investigated.

Memory Circuit Fault Simulator

Science.gov (United States)

Sheldon, Douglas J.; McClure, Tucker

2013-01-01

Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

Data processing device

International Nuclear Information System (INIS)

Kita, Yoshio.

1994-01-01

A data processing device for use in a thermonuclear testing device comprises a frequency component judging section for analog signals, a sample time selection section based on the result of the judgement, a storing memory section for selecting digital data memorized in the sampling time. Namely, the frequency components of the analog signals are detected by the frequency component judging section, and one of a plurality of previously set sampling times is selected by the sampling time selection section based on the result of the judgement of the frequency component judging section. Then, digital data obtained by A/D conversion are read and preliminarily memorized in the storing memory section. Subsequently, the digital data memorized in the sampling time selected by the sampling time selection section are selected and transmitted to a superior computer. The amount of data to be memorized can greatly reduced, to reduce the cost. (N.H.)

Polymer Ferroelectric Memory for Flexible Electronics

KAUST Repository

Khan, Mohd Adnan

2013-01-01

With the projected growth of the flexible and plastic electronics industry, there is renewed interest in the research community to develop high performance all-polymeric memory which will be an essential component of any electronic circuit. Some of the efforts in polymer memories are based on different mechanisms such as filamentary conduction, charge trapping effects, dipole alignment, and reduction-oxidation to name a few. Among these the leading candidate are those based on the mechanism of ferroelectricity. Polymer ferroelectric memory can be used in niche applications like smart cards, RFID tags, sensors etc. This dissertation will focus on novel material and device engineering to fabricate high performance low temperature polymeric ferroelectric memory for flexible electronics. We address and find solutions to some fundamental problems affecting all polymer ferroelectric memory like high coercive fields, fatigue and thermal stability issues, poor breakdown strength and poor p-type hole mobilities. Some of the strategies adopted in this dissertation are: Use of different flexible substrates, electrode engineering to improve charge injection and fatigue properties of ferroelectric polymers, large area ink jet printing of ferroelectric memory devices, use of polymer blends to improve insulating properties of ferroelectric polymers and use of oxide semiconductors to fabricate high mobility p-type ferroelectric memory. During the course of this dissertation we have fabricated: the first all-polymer ferroelectric capacitors with solvent modified highly conducting polymeric poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) [PEDOT:PSS] electrodes on plastic substrates with performance as good as devices with metallic Platinum-Gold electrodes on silicon substrates; the first all-polymer high performance ferroelectric memory on banknotes for security applications; novel ferroelectric capacitors based on blends of ferroelectric poly(vinylidene fluoride

Polymer Ferroelectric Memory for Flexible Electronics

KAUST Repository

Khan, Mohd Adnan

2013-11-01

With the projected growth of the flexible and plastic electronics industry, there is renewed interest in the research community to develop high performance all-polymeric memory which will be an essential component of any electronic circuit. Some of the efforts in polymer memories are based on different mechanisms such as filamentary conduction, charge trapping effects, dipole alignment, and reduction-oxidation to name a few. Among these the leading candidate are those based on the mechanism of ferroelectricity. Polymer ferroelectric memory can be used in niche applications like smart cards, RFID tags, sensors etc. This dissertation will focus on novel material and device engineering to fabricate high performance low temperature polymeric ferroelectric memory for flexible electronics. We address and find solutions to some fundamental problems affecting all polymer ferroelectric memory like high coercive fields, fatigue and thermal stability issues, poor breakdown strength and poor p-type hole mobilities. Some of the strategies adopted in this dissertation are: Use of different flexible substrates, electrode engineering to improve charge injection and fatigue properties of ferroelectric polymers, large area ink jet printing of ferroelectric memory devices, use of polymer blends to improve insulating properties of ferroelectric polymers and use of oxide semiconductors to fabricate high mobility p-type ferroelectric memory. During the course of this dissertation we have fabricated: the first all-polymer ferroelectric capacitors with solvent modified highly conducting polymeric poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) [PEDOT:PSS] electrodes on plastic substrates with performance as good as devices with metallic Platinum-Gold electrodes on silicon substrates; the first all-polymer high performance ferroelectric memory on banknotes for security applications; novel ferroelectric capacitors based on blends of ferroelectric poly(vinylidene fluoride

Quantum finite-depth memory channels: Case study

International Nuclear Information System (INIS)

Rybar, Tomas; Ziman, Mario

2009-01-01

We analyze the depth of the memory of quantum memory channels generated by a fixed unitary transformation describing the interaction between the principal system and internal degrees of freedom of the process device. We investigate the simplest case of a qubit memory channel with a two-level memory system. In particular, we explicitly characterize all interactions for which the memory depth is finite. We show that the memory effects are either infinite, or they disappear after at most two uses of the channel. Memory channels of finite depth can be to some extent controlled and manipulated by so-called reset sequences. We show that actions separated by the sequences of inputs of the length of the memory depth are independent and constitute memoryless channels.

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

Science.gov (United States)

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Introduction to magnetic random-access memory

CERN Document Server

Dieny, Bernard; Lee, Kyung-Jin

2017-01-01

Magnetic random-access memory (MRAM) is poised to replace traditional computer memory based on complementary metal-oxide semiconductors (CMOS). MRAM will surpass all other types of memory devices in terms of nonvolatility, low energy dissipation, fast switching speed, radiation hardness, and durability. Although toggle-MRAM is currently a commercial product, it is clear that future developments in MRAM will be based on spin-transfer torque, which makes use of electrons’ spin angular momentum instead of their charge. MRAM will require an amalgamation of magnetics and microelectronics technologies. However, researchers and developers in magnetics and in microelectronics attend different technical conferences, publish in different journals, use different tools, and have different backgrounds in condensed-matter physics, electrical engineering, and materials science. This book is an introduction to MRAM for microelectronics engineers written by specialists in magnetic mat rials and devices. It presents the bas...

Next generation spin torque memories

CERN Document Server

Kaushik, Brajesh Kumar; Kulkarni, Anant Aravind; Prajapati, Sanjay

2017-01-01

This book offers detailed insights into spin transfer torque (STT) based devices, circuits and memories. Starting with the basic concepts and device physics, it then addresses advanced STT applications and discusses the outlook for this cutting-edge technology. It also describes the architectures, performance parameters, fabrication, and the prospects of STT based devices. Further, moving from the device to the system perspective it presents a non-volatile computing architecture composed of STT based magneto-resistive and all-spin logic devices and demonstrates that efficient STT based magneto-resistive and all-spin logic devices can turn the dream of instant on/off non-volatile computing into reality.

Operation mode switchable charge-trap memory based on few-layer MoS2

Science.gov (United States)

Hou, Xiang; Yan, Xiao; Liu, Chunsen; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-03-01

Ultrathin layered two-dimensional (2D) semiconductors like MoS2 and WSe2 have received a lot of attention because of their excellent electrical properties and potential applications in electronic devices. We demonstrate a charge-trap memory with two different tunable operation modes based on a few-layer MoS2 channel and an Al2O3/HfO2/Al2O3 charge storage stack. Our device shows excellent memory properties under the traditional three-terminal operation mode. More importantly, unlike conventional charge-trap devices, this device can also realize the memory performance with just two terminals (drain and source) because of the unique atomic crystal electrical characteristics. Under the two-terminal operation mode, the erase/program current ratio can reach up to 104 with a stable retention property. Our study indicates that the conventional charge-trap memory cell can also realize the memory performance without the gate terminal based on novel two dimensional materials, which is meaningful for low power consumption and high integration density applications.

Operation guide device for nuclear power plants

International Nuclear Information System (INIS)

Araki, Tsuneyasu

1982-01-01

Purpose: To enable to maintain the soundness of nuclear fuels and each of equipments by compensating the effect of the xenon density on the reactor core thermal power resulted upon load following operation of a nuclear reactor. Constitution: The device comprises an instrumentation system for measuring the status of the nuclear reactor, a reactor core performance calculator for calculating the reactor core performance based on the output from the instrumentation system, a xenon density calculator for calculating the xenon density based on the output from the performance calculator, a memory unit for storing the output from the reactor core performance calculator and the xenon density calculator and for transferring the stored memory to a nuclear reactor status forecasting device and an alternative load pattern searching device for searching, in cooperation with the memory unit, an alternative load pattern which is within an operation restrictive condition and most closed to a demanded load pattern when a monitor for the deviation from the flowrate distribution detects the deviation from the operation restrictive conditions. (Yoshino, Y.)

Axially Modulated Clamped-Guided Arch Resonator for Memory and Logic Applications

KAUST Repository

Hafiz, Md Abdullah Al; Tella, Sherif Adekunle; Alcheikh, Nouha; Fariborzi, Hossein; Younis, Mohammad I.

2017-01-01

We experimentally demonstrate memory and logic devices based on an axially modulated clamped-guided arch resonator. The device are electrostatically actuated and capacitively sensed, while the resonance frequency modulation is achieved through an axial electrostatic force from the guided side of the clamped-guided arch microbeam. We present two case studies: first, a dynamic memory based on the nonlinear frequency response of the resonator, and second, a reprogrammable two-input logic gate based on the linear frequency modulation of the resonator. These devices show energy cost per memory/logic operation in pJ, are fully compatible with CMOS fabrication processes, have the potential for on-chip system integration, and operate at room temperature.

Axially Modulated Clamped-Guided Arch Resonator for Memory and Logic Applications

KAUST Repository

Hafiz, Md Abdullah Al

2017-11-03

We experimentally demonstrate memory and logic devices based on an axially modulated clamped-guided arch resonator. The device are electrostatically actuated and capacitively sensed, while the resonance frequency modulation is achieved through an axial electrostatic force from the guided side of the clamped-guided arch microbeam. We present two case studies: first, a dynamic memory based on the nonlinear frequency response of the resonator, and second, a reprogrammable two-input logic gate based on the linear frequency modulation of the resonator. These devices show energy cost per memory/logic operation in pJ, are fully compatible with CMOS fabrication processes, have the potential for on-chip system integration, and operate at room temperature.

Flexural pivot device

International Nuclear Information System (INIS)

Flaherty, Robert.

1986-01-01

A flexural pivot device or rotational actuator comprises first and sceond tubular members connected by flexural members of shape-memory-alloy. These are curved in the austenitic phase at a first temperature and after cooling to the martensitic phase are flattened. On heating one of the flexural members, it bends causing relative rotation of the tubular members. Heating of another member can produce opposite rotation. Heating is electrical or by hot gas. The device may be used in a nuclear reactor. (author)

Characteristics of Reduced Graphene Oxide Quantum Dots for a Flexible Memory Thin Film Transistor.

Science.gov (United States)

Kim, Yo-Han; Lee, Eun Yeol; Lee, Hyun Ho; Seo, Tae Seok

2017-05-17

Reduced graphene oxide quantum dot (rGOQD) devices in formats of capacitor and thin film transistor (TFT) were demonstrated and examined as the first trial to achieve nonambipolar channel property. In addition, through a gold nanoparticle (Au NP) layer embedded between the rGOQD active channel and dielectric layer, memory capacitor and TFT performances were realized by capacitance-voltage (C-V) hysteresis and gate program, erase, and reprogram biases. First, capacitor structure of the rGOQD memory device was constructed to examine memory charging effect featured in hysteretic C-V behavior with a 30 nm dielectric layer of cross-linked poly(vinyl alcohol). For the intervening Au NP charging layer, self-assembled monolayer (SAM) formation of the Au NP was executed to utilize electrostatic interaction by a dip-coating process under ambient environments with a conformal fabrication uniformity. Second, the rGOQD memory TFT device was also constructed in the same format of the Au NPs SAMs on a flexible substrate. Characteristics of the rGOQD TFT output showed novel saturation curves unlike typical graphene-based TFTs. However, The rGOQD TFT device reveals relatively low on/off ratio of 10 1 and mobility of 5.005 cm 2 /V·s. For the memory capacitor, the flat-band voltage shift (ΔV FB ) was measured as 3.74 V for ±10 V sweep, and for the memory TFT, the threshold voltage shift (ΔV th ) by the Au NP charging was detected as 7.84 V. In summary, it was concluded that the rGOQD memory device could accomplish an ideal graphene-based memory performance, which could have provided a wide memory window and saturated output characteristics.

Using DMA for copying performance counter data to memory

Science.gov (United States)

Gara, Alan; Salapura, Valentina; Wisniewski, Robert W

2013-12-31

A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance data.

Architectural Techniques to Enable Reliable and Scalable Memory Systems

OpenAIRE

Nair, Prashant J.

2017-01-01

High capacity and scalable memory systems play a vital role in enabling our desktops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is because we rely on technology scaling to improve memory density, and at small feature sizes, memory cells tend to break easily. Today, memory reliability is seen as the key impediment towards using high-density devices, adopting new technologies, and even bui...

Automatic disease diagnosis using optimised weightless neural networks for low-power wearable devices.

Science.gov (United States)

Cheruku, Ramalingaswamy; Edla, Damodar Reddy; Kuppili, Venkatanareshbabu; Dharavath, Ramesh; Beechu, Nareshkumar Reddy

2017-08-01

Low-power wearable devices for disease diagnosis are used at anytime and anywhere. These are non-invasive and pain-free for the better quality of life. However, these devices are resource constrained in terms of memory and processing capability. Memory constraint allows these devices to store a limited number of patterns and processing constraint provides delayed response. It is a challenging task to design a robust classification system under above constraints with high accuracy. In this Letter, to resolve this problem, a novel architecture for weightless neural networks (WNNs) has been proposed. It uses variable sized random access memories to optimise the memory usage and a modified binary TRIE data structure for reducing the test time. In addition, a bio-inspired-based genetic algorithm has been employed to improve the accuracy. The proposed architecture is experimented on various disease datasets using its software and hardware realisations. The experimental results prove that the proposed architecture achieves better performance in terms of accuracy, memory saving and test time as compared to standard WNNs. It also outperforms in terms of accuracy as compared to conventional neural network-based classifiers. The proposed architecture is a powerful part of most of the low-power wearable devices for the solution of memory, accuracy and time issues.

Electrical latching of microelectromechanical devices

Science.gov (United States)

Garcia, Ernest J.; Sleefe, Gerard E.

2004-11-02

Methods are disclosed for row and column addressing of an array of microelectromechanical (MEM) devices. The methods of the present invention are applicable to MEM micromirrors or memory elements and allow the MEM array to be programmed and maintained latched in a programmed state with a voltage that is generally lower than the voltage required for electrostatically switching the MEM devices.

Nanoscale superconducting memory based on the kinetic inductance of asymmetric nanowire loops

Science.gov (United States)

Murphy, Andrew; Averin, Dmitri V.; Bezryadin, Alexey

2017-06-01

The demand for low-dissipation nanoscale memory devices is as strong as ever. As Moore’s law is staggering, and the demand for a low-power-consuming supercomputer is high, the goal of making information processing circuits out of superconductors is one of the central goals of modern technology and physics. So far, digital superconducting circuits could not demonstrate their immense potential. One important reason for this is that a dense superconducting memory technology is not yet available. Miniaturization of traditional superconducting quantum interference devices is difficult below a few micrometers because their operation relies on the geometric inductance of the superconducting loop. Magnetic memories do allow nanometer-scale miniaturization, but they are not purely superconducting (Baek et al 2014 Nat. Commun. 5 3888). Our approach is to make nanometer scale memory cells based on the kinetic inductance (and not geometric inductance) of superconducting nanowire loops, which have already shown many fascinating properties (Aprili 2006 Nat. Nanotechnol. 1 15; Hopkins et al 2005 Science 308 1762). This allows much smaller devices and naturally eliminates magnetic-field cross-talk. We demonstrate that the vorticity, i.e., the winding number of the order parameter, of a closed superconducting loop can be used for realizing a nanoscale nonvolatile memory device. We demonstrate how to alter the vorticity in a controlled fashion by applying calibrated current pulses. A reliable read-out of the memory is also demonstrated. We present arguments that such memory can be developed to operate without energy dissipation.

Study of radiation effects on semiconductor devices

International Nuclear Information System (INIS)

Kuboyama, Satoshi; Shindou, Hiroyuki; Ikeda, Naomi; Iwata, Yoshiyuki; Murakami, Takeshi

2004-01-01

Fine structure of the recent semiconductor devices has made them more sensitive to the space radiation environment with trapped high-energy protons and heavy ions. A new failure mode caused by bulk damage had been reported on such devices with small structure, and its effect on commercial synchronous dynamic random access memory (SDRAMs) was analyzed from the irradiation test results performed at Heavy ion Medical Accelerator in Chiba (HIMAC). Single event upset (SEU) data of static random access memory (SRAMs) were also collected to establish the method of estimating the proton-induced SEU rate from the results of heavy ion irradiation tests. (authors)

Laser welding of Ti-Ni type shape memory alloy

International Nuclear Information System (INIS)

Hirose, Akio; Araki, Takao; Uchihara, Masato; Honda, Keizoh; Kondoh, Mitsuaki.

1990-01-01

The present study was undertaken to apply the laser welding to the joining of a shape memory alloy. Butt welding of a Ti-Ni type shape memory alloy was performed using 10 kW CO 2 laser. The laser welded specimens showed successfully the shape memory effect and super elasticity. These properties were approximately identical with those of the base metal. The change in super elasticity of the welded specimen during tension cycling was investigated. Significant changes in stress-strain curves and residual strain were not observed in the laser welded specimen after the 50-time cyclic test. The weld metal exhibited the celler dendrite. It was revealed by electron diffraction analysis that the phase of the weld metal was the TiNi phase of B2 structure which is the same as the parent phase of base metal and oxide inclusions crystallized at the dendrite boundary. However, oxygen contamination in the weld metal by laser welding did not occur because there was almost no difference in oxygen content between the base metal and the weld metal. The transformation temperatures of the weld metal were almost the same as those of the base metal. From these results, laser welding is applicable to the joining of the Ti-Ni type shape memory alloy. As the application of laser welding to new shape memory devices, the multiplex shape memory device of welded Ti-50.5 at % Ni and Ti-51.0 at % Ni was produced. The device showed two-stage shape memory effects due to the difference in transformation temperature between the two shape memory alloys. (author)

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Science.gov (United States)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Plasma memories associated to a particle detector

International Nuclear Information System (INIS)

Comby, G.; Mangeot, Ph.

1978-01-01

The realization of a localized and persisting memory of a detected particle which can be easily read out offers new possibilities for the detection of events with high multiplicity. The association of the plasma memory to a spark chamber allows the test of the principles of memorization and read-out. By means of one gap of plasma memories, one can read out without ambiguity the coordinates of a large number of memories. This device can be adapted to other types of detectors and also to larger geometries. (Auth.)

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

Science.gov (United States)

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition.

Science.gov (United States)

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-06-17

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

A review of emerging non-volatile memory (NVM) technologies and applications

Science.gov (United States)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Memory device sensitivity trends in aircraft's environment; Evolution de la sensibilite de composants memoires en altitude avion

Energy Technology Data Exchange (ETDEWEB)

Bouchet, T.; Fourtine, S. [Aerospatiale-Matra Airbus, 31 - Toulouse (France); Calvet, M.C. [Aerospatiale-Matra Lanceur, 78 - Les Mureaux (France)

1999-07-01

The authors present the SEU (single event upset) sensitivity of 31 SRAM (static random access memory) and 8 DRAM (dynamic random access memory) according to their technologies. 2 methods have been used to compute the SEU rate: the NCS (neutron cross section) method and the BGR (burst generation rate) method, the physics data required by both methods have been either found in scientific literature or directly measured. The use of new technologies implies a quicker time response through a dramatic reduction of chip size and of the amount of energy representing 1 bit. The reduction of size makes less particles are likely to interact with the chip but the reduction of the critical charge implies that these interactions are more likely to damage the chip. The SEU sensitivity is then parted between these 2 opposed trends. Results show that for technologies beyond 0,18 {mu}m these 2 trends balance roughly. Nevertheless the feedback experience shows that the number of errors is increasing. This is due to the fact that avionics requires more and more memory to perform numerical functions, the number of bits is increasing so is the risk of errors. As far as SEU is concerned, RAM devices are less and less sensitive comparatively for 1 bit, and DRAM seem to be less sensitive than SRAM. (A.C.)

Energy efficient hybrid computing systems using spin devices

Science.gov (United States)

Sharad, Mrigank

Emerging spin-devices like magnetic tunnel junctions (MTJ's), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ˜20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode' processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ˜100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters.

Towards Scalable Graph Computation on Mobile Devices.

Science.gov (United States)

Chen, Yiqi; Lin, Zhiyuan; Pienta, Robert; Kahng, Minsuk; Chau, Duen Horng

2014-10-01

Mobile devices have become increasingly central to our everyday activities, due to their portability, multi-touch capabilities, and ever-improving computational power. Such attractive features have spurred research interest in leveraging mobile devices for computation. We explore a novel approach that aims to use a single mobile device to perform scalable graph computation on large graphs that do not fit in the device's limited main memory, opening up the possibility of performing on-device analysis of large datasets, without relying on the cloud. Based on the familiar memory mapping capability provided by today's mobile operating systems, our approach to scale up computation is powerful and intentionally kept simple to maximize its applicability across the iOS and Android platforms. Our experiments demonstrate that an iPad mini can perform fast computation on large real graphs with as many as 272 million edges (Google+ social graph), at a speed that is only a few times slower than a 13″ Macbook Pro. Through creating a real world iOS app with this technique, we demonstrate the strong potential application for scalable graph computation on a single mobile device using our approach.

Towards Scalable Graph Computation on Mobile Devices

Science.gov (United States)

Chen, Yiqi; Lin, Zhiyuan; Pienta, Robert; Kahng, Minsuk; Chau, Duen Horng

2015-01-01

Mobile devices have become increasingly central to our everyday activities, due to their portability, multi-touch capabilities, and ever-improving computational power. Such attractive features have spurred research interest in leveraging mobile devices for computation. We explore a novel approach that aims to use a single mobile device to perform scalable graph computation on large graphs that do not fit in the device's limited main memory, opening up the possibility of performing on-device analysis of large datasets, without relying on the cloud. Based on the familiar memory mapping capability provided by today's mobile operating systems, our approach to scale up computation is powerful and intentionally kept simple to maximize its applicability across the iOS and Android platforms. Our experiments demonstrate that an iPad mini can perform fast computation on large real graphs with as many as 272 million edges (Google+ social graph), at a speed that is only a few times slower than a 13″ Macbook Pro. Through creating a real world iOS app with this technique, we demonstrate the strong potential application for scalable graph computation on a single mobile device using our approach. PMID:25859564

3D Printing of Shape Memory Polymers for Flexible Electronic Devices.

Science.gov (United States)

Zarek, Matt; Layani, Michael; Cooperstein, Ido; Sachyani, Ela; Cohn, Daniel; Magdassi, Shlomo

2016-06-01

The formation of 3D objects composed of shape memory polymers for flexible electronics is described. Layer-by-layer photopolymerization of methacrylated semicrystalline molten macromonomers by a 3D digital light processing printer enables rapid fabrication of complex objects and imparts shape memory functionality for electrical circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Printing an ITO-free flexible poly (4-vinylphenol) resistive switching device

Science.gov (United States)

Ali, Junaid; Rehman, Muhammad Muqeet; Siddiqui, Ghayas Uddin; Aziz, Shahid; Choi, Kyung Hyun

2018-02-01

Resistive switching in a sandwich structure of silver (Ag)/Polyvinyl phenol (PVP)/carbon nanotube (CNTs)-silver nanowires (AgNWs) coated on a flexible PET substrate is reported in this work. Densely populated networks of one dimensional nano materials (1DNM), CNTs-AgNWs have been used as the conductive bottom electrode with the prominent features of high flexibility and low sheet resistance of 90 Ω/sq. Thin, yet uniform active layer of PVP was deposited on top of the spin coated 1DNM thin film through state of the art printing technique of electrohydrodynamic atomization (EHDA) with an average thickness of 170 ± 28 nm. Ag dots with an active area of ∼0.1 mm2 were deposited through roll to plate printing system as the top electrodes to complete the device fabrication of flexible memory device. Our memory device exhibited suitable electrical characteristics with OFF/ON ratio of 100:1, retention time of 60 min and electrical endurance for 100 voltage sweeps without any noticeable decay in performance. The resistive switching characteristics at a low current compliance of 3 nA were also evaluated for the application of low power consumption. This memory device is flexible and can sustain more than 100 bending cycles at a bending diameter of 2 cm with stable HRS and LRS values. Our proposed device shows promise to be used as a future potential nonvolatile memory device in flexible electronics.

Design of two-terminal PNPN diode for high-density and high-speed memory applications

International Nuclear Information System (INIS)

Tong Xiaodong; Wu Hao; Liang Qingqing; Zhong Huicai; Zhu Huilong; Zhao Chao; Ye Tianchun

2014-01-01

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLSI applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability. (semiconductor devices)

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies